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PCI: Remove DEFINE_PCI_DEVICE_TABLE macro use
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
a05b8c58 16 along with this program; if not, see <http://www.gnu.org/licenses/>.
95ea3627
ID		 17 */
18
19/*
20 Module: rt2400pci
21 Abstract: rt2400pci device specific routines.
22 Supported chipsets: RT2460.
23 */
24
95ea3627
ID		 25#include <linux/delay.h>
26#include <linux/etherdevice.h>
95ea3627
ID		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/eeprom_93cx6.h>
5a0e3ad6 31#include <linux/slab.h>
95ea3627
ID		 32
33#include "rt2x00.h"
69a2bac8 34#include "rt2x00mmio.h"
95ea3627
ID		 35#include "rt2x00pci.h"
36#include "rt2400pci.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
172c5911 41 * rt2x00mmio_register_read and rt2x00mmio_register_write.
95ea3627
ID		 42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
f5a9987d 47 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
c9c3b1a5 51#define WAIT_FOR_BBP(__dev, __reg) \
172c5911 52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
c9c3b1a5 53#define WAIT_FOR_RF(__dev, __reg) \
172c5911 54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 55
0e14f6d3 56static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 57 const unsigned int word, const u8 value)
58{
59 u32 reg;
60
8ff48a8b
ID		 61 mutex_lock(&rt2x00dev->csr_mutex);
62
95ea3627 63 /*
c9c3b1a5
ID		 64 * Wait until the BBP becomes available, afterwards we
65 * can safely write the new data into the register.
95ea3627 66 */
c9c3b1a5
ID		 67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
68 reg = 0;
69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
73
172c5911 74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
c9c3b1a5 75 }
8ff48a8b 76
8ff48a8b 77 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 78}
79
0e14f6d3 80static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 81 const unsigned int word, u8 *value)
82{
83 u32 reg;
84
8ff48a8b
ID		 85 mutex_lock(&rt2x00dev->csr_mutex);
86
95ea3627 87 /*
c9c3b1a5
ID		 88 * Wait until the BBP becomes available, afterwards we
89 * can safely write the read request into the register.
90 * After the data has been written, we wait until hardware
91 * returns the correct value, if at any time the register
92 * doesn't become available in time, reg will be 0xffffffff
93 * which means we return 0xff to the caller.
95ea3627 94 */
c9c3b1a5
ID		 95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
96 reg = 0;
97 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
98 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
99 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 100
172c5911 101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 102
c9c3b1a5
ID		 103 WAIT_FOR_BBP(rt2x00dev, &reg);
104 }
95ea3627
ID		 105
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 107
108 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 109}
110
0e14f6d3 111static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 112 const unsigned int word, const u32 value)
113{
114 u32 reg;
95ea3627 115
8ff48a8b
ID		 116 mutex_lock(&rt2x00dev->csr_mutex);
117
c9c3b1a5
ID		 118 /*
119 * Wait until the RF becomes available, afterwards we
120 * can safely write the new data into the register.
121 */
122 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
123 reg = 0;
124 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
125 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
126 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
127 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
128
172c5911 129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
c9c3b1a5 130 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 131 }
132
8ff48a8b 133 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 134}
135
136static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
137{
138 struct rt2x00_dev *rt2x00dev = eeprom->data;
139 u32 reg;
140
172c5911 141 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
95ea3627
ID		 142
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
145 eeprom->reg_data_clock =
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
147 eeprom->reg_chip_select =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
149}
150
151static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
152{
153 struct rt2x00_dev *rt2x00dev = eeprom->data;
154 u32 reg = 0;
155
156 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
159 !!eeprom->reg_data_clock);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
161 !!eeprom->reg_chip_select);
162
172c5911 163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
95ea3627
ID		 164}
165
166#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 167static const struct rt2x00debug rt2400pci_rt2x00debug = {
168 .owner = THIS_MODULE,
169 .csr = {
172c5911
GJ		 170 .read = rt2x00mmio_register_read,
171 .write = rt2x00mmio_register_write,
743b97ca
ID		 172 .flags = RT2X00DEBUGFS_OFFSET,
173 .word_base = CSR_REG_BASE,
95ea3627
ID		 174 .word_size = sizeof(u32),
175 .word_count = CSR_REG_SIZE / sizeof(u32),
176 },
177 .eeprom = {
178 .read = rt2x00_eeprom_read,
179 .write = rt2x00_eeprom_write,
743b97ca 180 .word_base = EEPROM_BASE,
95ea3627
ID		 181 .word_size = sizeof(u16),
182 .word_count = EEPROM_SIZE / sizeof(u16),
183 },
184 .bbp = {
185 .read = rt2400pci_bbp_read,
186 .write = rt2400pci_bbp_write,
743b97ca 187 .word_base = BBP_BASE,
95ea3627
ID		 188 .word_size = sizeof(u8),
189 .word_count = BBP_SIZE / sizeof(u8),
190 },
191 .rf = {
192 .read = rt2x00_rf_read,
193 .write = rt2400pci_rf_write,
743b97ca 194 .word_base = RF_BASE,
95ea3627
ID		 195 .word_size = sizeof(u32),
196 .word_count = RF_SIZE / sizeof(u32),
197 },
198};
199#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
200
95ea3627
ID		 201static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
202{
203 u32 reg;
204
172c5911 205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 206 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
95ea3627 207}
95ea3627 208
771fd565 209#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 210static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 211 enum led_brightness brightness)
212{
213 struct rt2x00_led *led =
214 container_of(led_cdev, struct rt2x00_led, led_dev);
215 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 216 u32 reg;
217
172c5911 218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
a9450b70 219
a2e1d52a 220 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 221 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 222 else if (led->type == LED_TYPE_ACTIVITY)
223 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70 224
172c5911 225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a9450b70 226}
a2e1d52a
ID		 227
228static int rt2400pci_blink_set(struct led_classdev *led_cdev,
229 unsigned long *delay_on,
230 unsigned long *delay_off)
231{
232 struct rt2x00_led *led =
233 container_of(led_cdev, struct rt2x00_led, led_dev);
234 u32 reg;
235
172c5911 236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
a2e1d52a
ID		 237 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
238 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
172c5911 239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a2e1d52a
ID		 240
241 return 0;
242}
475433be
ID		 243
244static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
245 struct rt2x00_led *led,
246 enum led_type type)
247{
248 led->rt2x00dev = rt2x00dev;
249 led->type = type;
250 led->led_dev.brightness_set = rt2400pci_brightness_set;
251 led->led_dev.blink_set = rt2400pci_blink_set;
252 led->flags = LED_INITIALIZED;
253}
771fd565 254#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 255
95ea3627
ID		 256/*
257 * Configuration handlers.
258 */
3a643d24
ID		 259static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
260 const unsigned int filter_flags)
261{
262 u32 reg;
263
264 /*
265 * Start configuration steps.
266 * Note that the version error will always be dropped
267 * since there is no filter for it at this time.
268 */
172c5911 269 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
3a643d24
ID		 270 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
271 !(filter_flags & FIF_FCSFAIL));
272 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
273 !(filter_flags & FIF_PLCPFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
275 !(filter_flags & FIF_CONTROL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
277 !(filter_flags & FIF_PROMISC_IN_BSS));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 279 !(filter_flags & FIF_PROMISC_IN_BSS) &&
280 !rt2x00dev->intf_ap_count);
3a643d24 281 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
172c5911 282 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
3a643d24
ID		 283}
284
6bb40dd1
ID		 285static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
286 struct rt2x00_intf *intf,
287 struct rt2x00intf_conf *conf,
288 const unsigned int flags)
95ea3627 289{
6bb40dd1
ID		 290 unsigned int bcn_preload;
291 u32 reg;
95ea3627 292
6bb40dd1 293 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 294 /*
295 * Enable beacon config
296 */
bad13639 297 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
172c5911 298 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
6bb40dd1 299 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
172c5911 300 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 301
6bb40dd1
ID		 302 /*
303 * Enable synchronisation.
304 */
172c5911 305 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1 306 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
172c5911 307 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
6bb40dd1 308 }
95ea3627 309
6bb40dd1 310 if (flags & CONFIG_UPDATE_MAC)
172c5911
GJ		 311 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
312 conf->mac, sizeof(conf->mac));
95ea3627 313
6bb40dd1 314 if (flags & CONFIG_UPDATE_BSSID)
172c5911
GJ		 315 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
316 conf->bssid,
317 sizeof(conf->bssid));
95ea3627
ID		 318}
319
3a643d24 320static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 321 struct rt2x00lib_erp *erp,
322 u32 changed)
95ea3627 323{
5c58ee51 324 int preamble_mask;
95ea3627 325 u32 reg;
95ea3627 326
5c58ee51
ID		 327 /*
328 * When short preamble is enabled, we should set bit 0x08
329 */
02044643
HS		 330 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
331 preamble_mask = erp->short_preamble << 3;
332
172c5911 333 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
02044643
HS		 334 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
335 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
336 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
337 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
172c5911 338 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
02044643 339
172c5911 340 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
02044643
HS		 341 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
342 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
343 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
344 GET_DURATION(ACK_SIZE, 10));
172c5911 345 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
02044643 346
172c5911 347 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
02044643
HS		 348 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
349 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
351 GET_DURATION(ACK_SIZE, 20));
172c5911 352 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
02044643 353
172c5911 354 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
02044643
HS		 355 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
356 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
357 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
358 GET_DURATION(ACK_SIZE, 55));
172c5911 359 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
02044643 360
172c5911 361 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
02044643
HS		 362 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
363 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
364 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
365 GET_DURATION(ACK_SIZE, 110));
172c5911 366 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
02044643
HS		 367 }
368
369 if (changed & BSS_CHANGED_BASIC_RATES)
172c5911 370 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
02044643
HS		 371
372 if (changed & BSS_CHANGED_ERP_SLOT) {
172c5911 373 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
02044643 374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
172c5911 375 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
02044643 376
172c5911 377 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
02044643
HS		 378 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
172c5911 380 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
02044643 381
172c5911 382 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
02044643
HS		 383 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
172c5911 385 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
02044643
HS		 386 }
387
388 if (changed & BSS_CHANGED_BEACON_INT) {
172c5911 389 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
02044643
HS		 390 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
391 erp->beacon_int * 16);
392 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
393 erp->beacon_int * 16);
172c5911 394 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
02044643 395 }
95ea3627
ID		 396}
397
e4ea1c40
ID		 398static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
399 struct antenna_setup *ant)
95ea3627 400{
e4ea1c40
ID		 401 u8 r1;
402 u8 r4;
403
404 /*
405 * We should never come here because rt2x00lib is supposed
406 * to catch this and send us the correct antenna explicitely.
407 */
408 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
409 ant->tx == ANTENNA_SW_DIVERSITY);
410
411 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
412 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
413
414 /*
415 * Configure the TX antenna.
416 */
417 switch (ant->tx) {
418 case ANTENNA_HW_DIVERSITY:
419 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
420 break;
421 case ANTENNA_A:
422 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
423 break;
424 case ANTENNA_B:
425 default:
426 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
427 break;
428 }
429
430 /*
431 * Configure the RX antenna.
432 */
433 switch (ant->rx) {
434 case ANTENNA_HW_DIVERSITY:
435 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
436 break;
437 case ANTENNA_A:
438 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
439 break;
440 case ANTENNA_B:
441 default:
442 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
443 break;
444 }
445
446 rt2400pci_bbp_write(rt2x00dev, 4, r4);
447 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 448}
449
450static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 451 struct rf_channel *rf)
95ea3627 452{
95ea3627
ID		 453 /*
454 * Switch on tuning bits.
455 */
5c58ee51
ID		 456 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
457 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 458
5c58ee51
ID		 459 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
460 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
461 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 462
463 /*
464 * RF2420 chipset don't need any additional actions.
465 */
5122d898 466 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 467 return;
468
469 /*
470 * For the RT2421 chipsets we need to write an invalid
471 * reference clock rate to activate auto_tune.
472 * After that we set the value back to the correct channel.
473 */
5c58ee51 474 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 475 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 476 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 477
478 msleep(1);
479
5c58ee51
ID		 480 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
481 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
482 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 483
484 msleep(1);
485
486 /*
487 * Switch off tuning bits.
488 */
5c58ee51
ID		 489 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
490 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 491
5c58ee51
ID		 492 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
493 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 494
495 /*
496 * Clear false CRC during channel switch.
497 */
172c5911 498 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 499}
500
501static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
502{
503 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
504}
505
e4ea1c40
ID		 506static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
507 struct rt2x00lib_conf *libconf)
95ea3627 508{
e4ea1c40 509 u32 reg;
95ea3627 510
172c5911 511 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
e4ea1c40
ID		 512 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
513 libconf->conf->long_frame_max_tx_count);
514 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
515 libconf->conf->short_frame_max_tx_count);
172c5911 516 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 517}
518
7d7f19cc
ID		 519static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
520 struct rt2x00lib_conf *libconf)
521{
522 enum dev_state state =
523 (libconf->conf->flags & IEEE80211_CONF_PS) ?
524 STATE_SLEEP : STATE_AWAKE;
525 u32 reg;
526
527 if (state == STATE_SLEEP) {
172c5911 528 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
7d7f19cc 529 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 530 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 531 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
532 libconf->conf->listen_interval - 1);
533
534 /* We must first disable autowake before it can be enabled */
535 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
172c5911 536 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 537
538 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
172c5911 539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
5731858d 540 } else {
172c5911 541 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
5731858d 542 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
172c5911 543 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 544 }
545
546 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
547}
548
95ea3627 549static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 550 struct rt2x00lib_conf *libconf,
551 const unsigned int flags)
95ea3627 552{
e4ea1c40 553 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 554 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 555 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 556 rt2400pci_config_txpower(rt2x00dev,
557 libconf->conf->power_level);
e4ea1c40
ID		 558 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
559 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 560 if (flags & IEEE80211_CONF_CHANGE_PS)
561 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 562}
563
564static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 565 const int cw_min, const int cw_max)
95ea3627
ID		 566{
567 u32 reg;
568
172c5911 569 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 570 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
571 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
172c5911 572 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 573}
574
95ea3627
ID		 575/*
576 * Link tuning
577 */
ebcf26da
ID		 578static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579 struct link_qual *qual)
95ea3627
ID		 580{
581 u32 reg;
582 u8 bbp;
583
584 /*
585 * Update FCS error count from register.
586 */
172c5911 587 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 588 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 589
590 /*
591 * Update False CCA count from register.
592 */
593 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 594 qual->false_cca = bbp;
95ea3627
ID		 595}
596
5352ff65
ID		 597static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
598 struct link_qual *qual, u8 vgc_level)
eb20b4e8 599{
223dcc26
ID		 600 if (qual->vgc_level_reg != vgc_level) {
601 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
602 qual->vgc_level = vgc_level;
603 qual->vgc_level_reg = vgc_level;
604 }
eb20b4e8
ID		 605}
606
5352ff65
ID		 607static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
608 struct link_qual *qual)
95ea3627 609{
5352ff65 610 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 611}
612
5352ff65
ID		 613static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
614 struct link_qual *qual, const u32 count)
95ea3627 615{
95ea3627
ID		 616 /*
617 * The link tuner should not run longer then 60 seconds,
618 * and should run once every 2 seconds.
619 */
5352ff65 620 if (count > 60 || !(count & 1))
95ea3627
ID		 621 return;
622
623 /*
624 * Base r13 link tuning on the false cca count.
625 */
5352ff65
ID		 626 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
627 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
628 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
629 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 630}
631
5450b7e2
ID		 632/*
633 * Queue handlers.
634 */
635static void rt2400pci_start_queue(struct data_queue *queue)
636{
637 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
638 u32 reg;
639
640 switch (queue->qid) {
641 case QID_RX:
172c5911 642 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
5450b7e2 643 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
172c5911 644 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 645 break;
646 case QID_BEACON:
172c5911 647 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
5450b7e2
ID		 648 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
649 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
650 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
172c5911 651 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
5450b7e2
ID		 652 break;
653 default:
654 break;
655 }
656}
657
658static void rt2400pci_kick_queue(struct data_queue *queue)
659{
660 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
661 u32 reg;
662
663 switch (queue->qid) {
f615e9a3 664 case QID_AC_VO:
172c5911 665 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 666 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
172c5911 667 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2 668 break;
f615e9a3 669 case QID_AC_VI:
172c5911 670 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 671 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
172c5911 672 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 673 break;
674 case QID_ATIM:
172c5911 675 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 676 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
172c5911 677 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 678 break;
679 default:
680 break;
681 }
682}
683
684static void rt2400pci_stop_queue(struct data_queue *queue)
685{
686 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
687 u32 reg;
688
689 switch (queue->qid) {
f615e9a3
ID		 690 case QID_AC_VO:
691 case QID_AC_VI:
5450b7e2 692 case QID_ATIM:
172c5911 693 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 694 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
172c5911 695 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 696 break;
697 case QID_RX:
172c5911 698 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
5450b7e2 699 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
172c5911 700 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 701 break;
702 case QID_BEACON:
172c5911 703 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
5450b7e2
ID		 704 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
705 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
706 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
172c5911 707 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bcf3cfd0
HS		 708
709 /*
710 * Wait for possibly running tbtt tasklets.
711 */
abc11994 712 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 713 break;
714 default:
715 break;
716 }
717}
718
95ea3627
ID		 719/*
720 * Initialization functions.
721 */
798b7adb 722static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 723{
172c5911 724 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 725 u32 word;
726
798b7adb
ID		 727 if (entry->queue->qid == QID_RX) {
728 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 729
798b7adb
ID		 730 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
731 } else {
732 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 733
798b7adb
ID		 734 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
735 rt2x00_get_field32(word, TXD_W0_VALID));
736 }
95ea3627
ID		 737}
738
798b7adb 739static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 740{
172c5911 741 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
798b7adb 742 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 743 u32 word;
744
798b7adb
ID		 745 if (entry->queue->qid == QID_RX) {
746 rt2x00_desc_read(entry_priv->desc, 2, &word);
747 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
748 rt2x00_desc_write(entry_priv->desc, 2, word);
749
750 rt2x00_desc_read(entry_priv->desc, 1, &word);
751 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
752 rt2x00_desc_write(entry_priv->desc, 1, word);
753
754 rt2x00_desc_read(entry_priv->desc, 0, &word);
755 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
756 rt2x00_desc_write(entry_priv->desc, 0, word);
757 } else {
758 rt2x00_desc_read(entry_priv->desc, 0, &word);
759 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
760 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
761 rt2x00_desc_write(entry_priv->desc, 0, word);
762 }
95ea3627
ID		 763}
764
181d6902 765static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 766{
172c5911 767 struct queue_entry_priv_mmio *entry_priv;
95ea3627
ID		 768 u32 reg;
769
95ea3627
ID		 770 /*
771 * Initialize registers.
772 */
172c5911 773 rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 774 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
775 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 776 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 777 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
172c5911 778 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
95ea3627 779
b8be63ff 780 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
172c5911 781 rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 782 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 783 entry_priv->desc_dma);
172c5911 784 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
95ea3627 785
b8be63ff 786 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
172c5911 787 rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 788 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 789 entry_priv->desc_dma);
172c5911 790 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
95ea3627 791
e74df4a7 792 entry_priv = rt2x00dev->atim->entries[0].priv_data;
172c5911 793 rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 794 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 795 entry_priv->desc_dma);
172c5911 796 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
95ea3627 797
e74df4a7 798 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
172c5911 799 rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 800 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 801 entry_priv->desc_dma);
172c5911 802 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
95ea3627 803
172c5911 804 rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
95ea3627 805 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 806 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
172c5911 807 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
95ea3627 808
b8be63ff 809 entry_priv = rt2x00dev->rx->entries[0].priv_data;
172c5911 810 rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 811 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
812 entry_priv->desc_dma);
172c5911 813 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
95ea3627
ID		 814
815 return 0;
816}
817
818static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
819{
820 u32 reg;
821
172c5911
GJ		 822 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
823 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
824 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
825 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
95ea3627 826
172c5911 827 rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
95ea3627
ID		 828 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
829 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
830 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
172c5911 831 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
95ea3627 832
172c5911 833 rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
95ea3627
ID		 834 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
835 (rt2x00dev->rx->data_size / 128));
172c5911 836 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
95ea3627 837
172c5911 838 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1f909162
ID		 839 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
840 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
841 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
842 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
843 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
844 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
845 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
846 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
172c5911 847 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1f909162 848
172c5911 849 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
95ea3627 850
172c5911 851 rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);
95ea3627
ID		 852 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
853 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
854 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
172c5911 856 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
95ea3627 857
172c5911 858 rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
95ea3627
ID		 859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
172c5911 865 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
95ea3627 866
172c5911 867 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
95ea3627
ID		 868
869 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
870 return -EBUSY;
871
172c5911
GJ		 872 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
873 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
95ea3627 874
172c5911 875 rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
95ea3627 876 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
172c5911 877 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
95ea3627 878
172c5911 879 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
95ea3627
ID		 880 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
881 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
882 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
172c5911 884 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
95ea3627 885
172c5911 886 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
95ea3627
ID		 887 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
888 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
889 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
172c5911 890 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627 891
172c5911 892 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
95ea3627
ID		 893 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
894 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
172c5911 895 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627
ID		 896
897 /*
898 * We must clear the FCS and FIFO error count.
899 * These registers are cleared on read,
900 * so we may pass a useless variable to store the value.
901 */
172c5911
GJ		 902 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
903 rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
95ea3627
ID		 904
905 return 0;
906}
907
2b08da3f 908static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 909{
910 unsigned int i;
95ea3627
ID		 911 u8 value;
912
913 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
914 rt2400pci_bbp_read(rt2x00dev, 0, &value);
915 if ((value != 0xff) && (value != 0x00))
2b08da3f 916 return 0;
95ea3627
ID		 917 udelay(REGISTER_BUSY_DELAY);
918 }
919
ec9c4989 920 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
95ea3627 921 return -EACCES;
2b08da3f
ID		 922}
923
924static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
925{
926 unsigned int i;
927 u16 eeprom;
928 u8 reg_id;
929 u8 value;
930
931 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
932 return -EACCES;
95ea3627 933
95ea3627
ID		 934 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
935 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
936 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
937 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
938 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
939 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
940 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
941 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
942 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
943 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
944 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
945 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
946 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
947 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
948
95ea3627
ID		 949 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
950 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
951
952 if (eeprom != 0xffff && eeprom != 0x0000) {
953 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
954 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 955 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
956 }
957 }
95ea3627
ID		 958
959 return 0;
960}
961
962/*
963 * Device state switch handlers.
964 */
95ea3627
ID		 965static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
966 enum dev_state state)
967{
b550911a 968 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 969 u32 reg;
bcf3cfd0 970 unsigned long flags;
95ea3627
ID		 971
972 /*
973 * When interrupts are being enabled, the interrupt registers
974 * should clear the register to assure a clean state.
975 */
976 if (state == STATE_RADIO_IRQ_ON) {
172c5911
GJ		 977 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
978 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
95ea3627
ID		 979 }
980
981 /*
982 * Only toggle the interrupts bits we are going to use.
983 * Non-checked interrupt bits are disabled by default.
984 */
bcf3cfd0
HS		 985 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
986
172c5911 987 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
95ea3627
ID		 988 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
989 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
990 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
991 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
992 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
172c5911 993 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0
HS		 994
995 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
996
997 if (state == STATE_RADIO_IRQ_OFF) {
998 /*
999 * Ensure that all tasklets are finished before
1000 * disabling the interrupts.
1001 */
abc11994
HS		 1002 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1003 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1004 tasklet_kill(&rt2x00dev->tbtt_tasklet);
bcf3cfd0 1005 }
95ea3627
ID		 1006}
1007
1008static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1009{
1010 /*
1011 * Initialize all registers.
1012 */
2b08da3f
ID		 1013 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1014 rt2400pci_init_registers(rt2x00dev) ||
1015 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 1016 return -EIO;
95ea3627 1017
95ea3627
ID		 1018 return 0;
1019}
1020
1021static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1022{
95ea3627 1023 /*
a2c9b652 1024 * Disable power
95ea3627 1025 */
172c5911 1026 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1027}
1028
1029static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1030 enum dev_state state)
1031{
9655a6ec 1032 u32 reg, reg2;
95ea3627
ID		 1033 unsigned int i;
1034 char put_to_sleep;
1035 char bbp_state;
1036 char rf_state;
1037
1038 put_to_sleep = (state != STATE_AWAKE);
1039
172c5911 1040 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
95ea3627
ID		 1041 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1042 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1043 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1044 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
172c5911 1045 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1046
1047 /*
1048 * Device is not guaranteed to be in the requested state yet.
1049 * We must wait until the register indicates that the
1050 * device has entered the correct state.
1051 */
1052 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
172c5911 1053 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
9655a6ec
GW		 1054 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1055 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1056 if (bbp_state == state && rf_state == state)
1057 return 0;
172c5911 1058 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1059 msleep(10);
1060 }
1061
95ea3627
ID		 1062 return -EBUSY;
1063}
1064
1065static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1066 enum dev_state state)
1067{
1068 int retval = 0;
1069
1070 switch (state) {
1071 case STATE_RADIO_ON:
1072 retval = rt2400pci_enable_radio(rt2x00dev);
1073 break;
1074 case STATE_RADIO_OFF:
1075 rt2400pci_disable_radio(rt2x00dev);
1076 break;
2b08da3f
ID		 1077 case STATE_RADIO_IRQ_ON:
1078 case STATE_RADIO_IRQ_OFF:
1079 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1080 break;
1081 case STATE_DEEP_SLEEP:
1082 case STATE_SLEEP:
1083 case STATE_STANDBY:
1084 case STATE_AWAKE:
1085 retval = rt2400pci_set_state(rt2x00dev, state);
1086 break;
1087 default:
1088 retval = -ENOTSUPP;
1089 break;
1090 }
1091
2b08da3f 1092 if (unlikely(retval))
ec9c4989
JP		 1093 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1094 state, retval);
2b08da3f 1095
95ea3627
ID		 1096 return retval;
1097}
1098
1099/*
1100 * TX descriptor initialization
1101 */
93331458 1102static void rt2400pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1103 struct txentry_desc *txdesc)
95ea3627 1104{
93331458 1105 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
172c5911 1106 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
85b7a8b3 1107 __le32 *txd = entry_priv->desc;
95ea3627 1108 u32 word;
95ea3627
ID		 1109
1110 /*
1111 * Start writing the descriptor words.
1112 */
85b7a8b3 1113 rt2x00_desc_read(txd, 1, &word);
c4da0048 1114 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1115 rt2x00_desc_write(txd, 1, word);
4de36fe5 1116
95ea3627 1117 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1118 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1119 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1120 rt2x00_desc_write(txd, 2, word);
1121
1122 rt2x00_desc_read(txd, 3, &word);
26a1d07f 1123 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
49da2605
ID		 1124 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1125 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
26a1d07f 1126 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
49da2605
ID		 1127 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1128 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1129 rt2x00_desc_write(txd, 3, word);
1130
1131 rt2x00_desc_read(txd, 4, &word);
26a1d07f
HS		 1132 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1133 txdesc->u.plcp.length_low);
49da2605
ID		 1134 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1135 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
26a1d07f
HS		 1136 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1137 txdesc->u.plcp.length_high);
49da2605
ID		 1138 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1139 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1140 rt2x00_desc_write(txd, 4, word);
1141
e01f1ec3
GW		 1142 /*
1143 * Writing TXD word 0 must the last to prevent a race condition with
1144 * the device, whereby the device may take hold of the TXD before we
1145 * finished updating it.
1146 */
95ea3627
ID		 1147 rt2x00_desc_read(txd, 0, &word);
1148 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1149 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1150 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1151 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1152 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1153 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1154 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1155 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1156 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902 1157 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
2517794b 1158 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1159 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1160 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1161 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1162
1163 /*
1164 * Register descriptor details in skb frame descriptor.
1165 */
1166 skbdesc->desc = txd;
1167 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1168}
1169
1170/*
1171 * TX data initialization
1172 */
f224f4ef
GW		 1173static void rt2400pci_write_beacon(struct queue_entry *entry,
1174 struct txentry_desc *txdesc)
bd88a781
ID		 1175{
1176 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1177 u32 reg;
1178
1179 /*
1180 * Disable beaconing while we are reloading the beacon data,
1181 * otherwise we might be sending out invalid data.
1182 */
172c5911 1183 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
bd88a781 1184 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
172c5911 1185 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781 1186
4ea545d4 1187 if (rt2x00queue_map_txskb(entry)) {
ec9c4989 1188 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
4ea545d4
SG		 1189 goto out;
1190 }
1191 /*
1192 * Enable beaconing again.
1193 */
1194 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
5c3b685c
GW		 1195 /*
1196 * Write the TX descriptor for the beacon.
1197 */
93331458 1198 rt2400pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1199
1200 /*
1201 * Dump beacon to userspace through debugfs.
1202 */
1203 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
4ea545d4 1204out:
d61cb266
GW		 1205 /*
1206 * Enable beaconing again.
1207 */
d61cb266 1208 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
172c5911 1209 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1210}
1211
95ea3627
ID		 1212/*
1213 * RX control handlers
1214 */
181d6902
ID		 1215static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1216 struct rxdone_entry_desc *rxdesc)
95ea3627 1217{
ae73e58e 1218 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
172c5911 1219 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 1220 u32 word0;
1221 u32 word2;
89993890 1222 u32 word3;
ae73e58e
ID		 1223 u32 word4;
1224 u64 tsf;
1225 u32 rx_low;
1226 u32 rx_high;
95ea3627 1227
b8be63ff
ID		 1228 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1229 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1230 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1231 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1232
4150c572 1233 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1234 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1235 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1236 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1237
ae73e58e
ID		 1238 /*
1239 * We only get the lower 32bits from the timestamp,
1240 * to get the full 64bits we must complement it with
1241 * the timestamp from get_tsf().
1242 * Note that when a wraparound of the lower 32bits
1243 * has occurred between the frame arrival and the get_tsf()
1244 * call, we must decrease the higher 32bits with 1 to get
1245 * to correct value.
1246 */
37a41b4a 1247 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
ae73e58e
ID		 1248 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1249 rx_high = upper_32_bits(tsf);
1250
1251 if ((u32)tsf <= rx_low)
1252 rx_high--;
1253
95ea3627
ID		 1254 /*
1255 * Obtain the status about this packet.
8ed09854
ID		 1256 * The signal is the PLCP value, and needs to be stripped
1257 * of the preamble bit (0x08).
95ea3627 1258 */
ae73e58e 1259 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1260 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
2bf127a5 1261 rxdesc->rssi = rt2x00_get_field32(word3, RXD_W3_RSSI) -
181d6902 1262 entry->queue->rt2x00dev->rssi_offset;
181d6902 1263 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1264
dec13b6b 1265 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1266 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1267 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1268}
1269
1270/*
1271 * Interrupt functions.
1272 */
181d6902 1273static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1274 const enum data_queue_qid queue_idx)
95ea3627 1275{
61c6e489 1276 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
172c5911 1277 struct queue_entry_priv_mmio *entry_priv;
181d6902
ID		 1278 struct queue_entry *entry;
1279 struct txdone_entry_desc txdesc;
95ea3627 1280 u32 word;
95ea3627 1281
181d6902
ID		 1282 while (!rt2x00queue_empty(queue)) {
1283 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1284 entry_priv = entry->priv_data;
1285 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1286
1287 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1288 !rt2x00_get_field32(word, TXD_W0_VALID))
1289 break;
1290
1291 /*
1292 * Obtain the status about this packet.
1293 */
fb55f4d1
ID		 1294 txdesc.flags = 0;
1295 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1296 case 0: /* Success */
1297 case 1: /* Success with retry */
1298 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1299 break;
1300 case 2: /* Failure, excessive retries */
1301 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1302 /* Don't break, this is a failed frame! */
1303 default: /* Failure */
1304 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1305 }
181d6902 1306 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1307
e513a0b6 1308 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1309 }
95ea3627
ID		 1310}
1311
7a5a681a
HS		 1312static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1313 struct rt2x00_field32 irq_field)
95ea3627 1314{
bcf3cfd0 1315 u32 reg;
95ea3627
ID		 1316
1317 /*
bcf3cfd0
HS		 1318 * Enable a single interrupt. The interrupt mask register
1319 * access needs locking.
95ea3627 1320 */
0aa13b2e 1321 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1322
172c5911 1323 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
bcf3cfd0 1324 rt2x00_set_field32(&reg, irq_field, 0);
172c5911 1325 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
95ea3627 1326
0aa13b2e 1327 spin_unlock_irq(&rt2x00dev->irqmask_lock);
bcf3cfd0 1328}
95ea3627 1329
bcf3cfd0
HS		 1330static void rt2400pci_txstatus_tasklet(unsigned long data)
1331{
1332 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1333 u32 reg;
95ea3627
ID		 1334
1335 /*
bcf3cfd0 1336 * Handle all tx queues.
95ea3627 1337 */
bcf3cfd0
HS		 1338 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1339 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1340 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1341
1342 /*
bcf3cfd0 1343 * Enable all TXDONE interrupts again.
95ea3627 1344 */
abc11994
HS		 1345 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1346 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1347
172c5911 1348 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
abc11994
HS		 1349 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1350 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1351 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
172c5911 1352 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1353
abc11994
HS		 1354 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1355 }
bcf3cfd0
HS		 1356}
1357
1358static void rt2400pci_tbtt_tasklet(unsigned long data)
1359{
1360 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1361 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1362 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1363 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
bcf3cfd0
HS		 1364}
1365
1366static void rt2400pci_rxdone_tasklet(unsigned long data)
1367{
1368 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
172c5911 1369 if (rt2x00mmio_rxdone(rt2x00dev))
16638937 1370 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1371 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1372 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1373}
1374
78e256c9
HS		 1375static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1376{
1377 struct rt2x00_dev *rt2x00dev = dev_instance;
bcf3cfd0 1378 u32 reg, mask;
78e256c9
HS		 1379
1380 /*
1381 * Get the interrupt sources & saved to local variable.
1382 * Write register value back to clear pending interrupts.
1383 */
172c5911
GJ		 1384 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1385 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
78e256c9
HS		 1386
1387 if (!reg)
1388 return IRQ_NONE;
1389
1390 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1391 return IRQ_HANDLED;
1392
bcf3cfd0
HS		 1393 mask = reg;
1394
1395 /*
1396 * Schedule tasklets for interrupt handling.
1397 */
1398 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1399 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1400
1401 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1402 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1403
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1405 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1406 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1407 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1408 /*
1409 * Mask out all txdone interrupts.
1410 */
1411 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1412 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1413 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1414 }
78e256c9 1415
bcf3cfd0
HS		 1416 /*
1417 * Disable all interrupts for which a tasklet was scheduled right now,
1418 * the tasklet will reenable the appropriate interrupts.
1419 */
0aa13b2e 1420 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1421
172c5911 1422 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
bcf3cfd0 1423 reg |= mask;
172c5911 1424 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1425
0aa13b2e 1426 spin_unlock(&rt2x00dev->irqmask_lock);
bcf3cfd0
HS		 1427
1428
1429
1430 return IRQ_HANDLED;
78e256c9
HS		 1431}
1432
95ea3627
ID		 1433/*
1434 * Device probe functions.
1435 */
1436static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1437{
1438 struct eeprom_93cx6 eeprom;
1439 u32 reg;
1440 u16 word;
1441 u8 *mac;
1442
172c5911 1443 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
95ea3627
ID		 1444
1445 eeprom.data = rt2x00dev;
1446 eeprom.register_read = rt2400pci_eepromregister_read;
1447 eeprom.register_write = rt2400pci_eepromregister_write;
1448 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1449 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1450 eeprom.reg_data_in = 0;
1451 eeprom.reg_data_out = 0;
1452 eeprom.reg_data_clock = 0;
1453 eeprom.reg_chip_select = 0;
1454
1455 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1456 EEPROM_SIZE / sizeof(u16));
1457
1458 /*
1459 * Start validation of the data that has been read.
1460 */
1461 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1462 if (!is_valid_ether_addr(mac)) {
f4f7f414 1463 eth_random_addr(mac);
ec9c4989 1464 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1465 }
1466
1467 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1468 if (word == 0xffff) {
ec9c4989 1469 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
95ea3627
ID		 1470 return -EINVAL;
1471 }
1472
1473 return 0;
1474}
1475
1476static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1477{
1478 u32 reg;
1479 u16 value;
1480 u16 eeprom;
1481
1482 /*
1483 * Read EEPROM word for configuration.
1484 */
1485 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1486
1487 /*
1488 * Identify RF chipset.
1489 */
1490 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
172c5911 1491 rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1492 rt2x00_set_chip(rt2x00dev, RT2460, value,
1493 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1494
5122d898 1495 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
ec9c4989 1496 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
95ea3627
ID		 1497 return -ENODEV;
1498 }
1499
1500 /*
1501 * Identify default antenna configuration.
1502 */
addc81bd 1503 rt2x00dev->default_ant.tx =
95ea3627 1504 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1505 rt2x00dev->default_ant.rx =
95ea3627
ID		 1506 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1507
addc81bd
ID		 1508 /*
1509 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1510 * I am not 100% sure about this, but the legacy drivers do not
1511 * indicate antenna swapping in software is required when
1512 * diversity is enabled.
1513 */
1514 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1515 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1516 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1517 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1518
95ea3627
ID		 1519 /*
1520 * Store led mode, for correct led behaviour.
1521 */
771fd565 1522#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1523 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1524
475433be 1525 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1526 if (value == LED_MODE_TXRX_ACTIVITY ||
1527 value == LED_MODE_DEFAULT ||
1528 value == LED_MODE_ASUS)
475433be
ID		 1529 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1530 LED_TYPE_ACTIVITY);
771fd565 1531#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1532
1533 /*
1534 * Detect if this device has an hardware controlled radio.
1535 */
1536 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1537 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 1538
1539 /*
1540 * Check if the BBP tuning should be enabled.
1541 */
27df2a9c 1542 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
7dab73b3 1543 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1544
1545 return 0;
1546}
1547
1548/*
1549 * RF value list for RF2420 & RF2421
1550 * Supports: 2.4 GHz
1551 */
8c5e7a5f 1552static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1553 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1554 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1555 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1556 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1557 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1558 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1559 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1560 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1561 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1562 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1563 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1564 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1565 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1566 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1567};
1568
8c5e7a5f 1569static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1570{
1571 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1572 struct channel_info *info;
1573 char *tx_power;
95ea3627
ID		 1574 unsigned int i;
1575
1576 /*
1577 * Initialize all hw fields.
1578 */
566bfe5a 1579 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1580 IEEE80211_HW_SIGNAL_DBM |
1581 IEEE80211_HW_SUPPORTS_PS |
1582 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1583
14a3bf89 1584 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1585 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1586 rt2x00_eeprom_addr(rt2x00dev,
1587 EEPROM_MAC_ADDR_0));
1588
95ea3627
ID		 1589 /*
1590 * Initialize hw_mode information.
1591 */
31562e80
ID		 1592 spec->supported_bands = SUPPORT_BAND_2GHZ;
1593 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1594
8c5e7a5f
ID		 1595 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1596 spec->channels = rf_vals_b;
1597
1598 /*
1599 * Create channel information array
1600 */
baeb2ffa 1601 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1602 if (!info)
1603 return -ENOMEM;
1604
1605 spec->channels_info = info;
1606
1607 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1608 for (i = 0; i < 14; i++) {
1609 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1610 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1611 }
8c5e7a5f
ID		 1612
1613 return 0;
95ea3627
ID		 1614}
1615
1616static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1617{
1618 int retval;
a396e100 1619 u32 reg;
95ea3627
ID		 1620
1621 /*
1622 * Allocate eeprom data.
1623 */
1624 retval = rt2400pci_validate_eeprom(rt2x00dev);
1625 if (retval)
1626 return retval;
1627
1628 retval = rt2400pci_init_eeprom(rt2x00dev);
1629 if (retval)
1630 return retval;
1631
a396e100
GW		 1632 /*
1633 * Enable rfkill polling by setting GPIO direction of the
1634 * rfkill switch GPIO pin correctly.
1635 */
172c5911 1636 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 1637 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
172c5911 1638 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
a396e100 1639
95ea3627
ID		 1640 /*
1641 * Initialize hw specifications.
1642 */
8c5e7a5f
ID		 1643 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1644 if (retval)
1645 return retval;
95ea3627
ID		 1646
1647 /*
c4da0048 1648 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1649 */
7dab73b3
ID		 1650 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1651 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1652 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1653
1654 /*
1655 * Set the rssi offset.
1656 */
1657 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1658
1659 return 0;
1660}
1661
1662/*
1663 * IEEE80211 stack callback functions.
1664 */
8a3a3c85
EP		 1665static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1666 struct ieee80211_vif *vif, u16 queue,
95ea3627
ID		 1667 const struct ieee80211_tx_queue_params *params)
1668{
1669 struct rt2x00_dev *rt2x00dev = hw->priv;
1670
1671 /*
1672 * We don't support variating cw_min and cw_max variables
1673 * per queue. So by default we only configure the TX queue,
1674 * and ignore all other configurations.
1675 */
e100bb64 1676 if (queue != 0)
95ea3627
ID		 1677 return -EINVAL;
1678
8a3a3c85 1679 if (rt2x00mac_conf_tx(hw, vif, queue, params))
95ea3627
ID		 1680 return -EINVAL;
1681
1682 /*
1683 * Write configuration to register.
1684 */
181d6902
ID		 1685 rt2400pci_config_cw(rt2x00dev,
1686 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1687
1688 return 0;
1689}
1690
37a41b4a
EP		 1691static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1692 struct ieee80211_vif *vif)
95ea3627
ID		 1693{
1694 struct rt2x00_dev *rt2x00dev = hw->priv;
1695 u64 tsf;
1696 u32 reg;
1697
172c5911 1698 rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
95ea3627 1699 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
172c5911 1700 rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
95ea3627
ID		 1701 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1702
1703 return tsf;
1704}
1705
95ea3627
ID		 1706static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1707{
1708 struct rt2x00_dev *rt2x00dev = hw->priv;
1709 u32 reg;
1710
172c5911 1711 rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
95ea3627
ID		 1712 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1713}
1714
1715static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1716 .tx = rt2x00mac_tx,
4150c572
JB		 1717 .start = rt2x00mac_start,
1718 .stop = rt2x00mac_stop,
95ea3627
ID		 1719 .add_interface = rt2x00mac_add_interface,
1720 .remove_interface = rt2x00mac_remove_interface,
1721 .config = rt2x00mac_config,
3a643d24 1722 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1723 .sw_scan_start = rt2x00mac_sw_scan_start,
1724 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1725 .get_stats = rt2x00mac_get_stats,
471b3efd 1726 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1727 .conf_tx = rt2400pci_conf_tx,
95ea3627 1728 .get_tsf = rt2400pci_get_tsf,
95ea3627 1729 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1730 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1731 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 1732 .set_antenna = rt2x00mac_set_antenna,
1733 .get_antenna = rt2x00mac_get_antenna,
e7dee444 1734 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1735 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 1736};
1737
1738static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1739 .irq_handler = rt2400pci_interrupt,
bcf3cfd0
HS		 1740 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1741 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1742 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
95ea3627 1743 .probe_hw = rt2400pci_probe_hw,
172c5911
GJ		 1744 .initialize = rt2x00mmio_initialize,
1745 .uninitialize = rt2x00mmio_uninitialize,
798b7adb
ID		 1746 .get_entry_state = rt2400pci_get_entry_state,
1747 .clear_entry = rt2400pci_clear_entry,
95ea3627 1748 .set_device_state = rt2400pci_set_device_state,
95ea3627 1749 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1750 .link_stats = rt2400pci_link_stats,
1751 .reset_tuner = rt2400pci_reset_tuner,
1752 .link_tuner = rt2400pci_link_tuner,
dbba306f
ID		 1753 .start_queue = rt2400pci_start_queue,
1754 .kick_queue = rt2400pci_kick_queue,
1755 .stop_queue = rt2400pci_stop_queue,
172c5911 1756 .flush_queue = rt2x00mmio_flush_queue,
95ea3627 1757 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1758 .write_beacon = rt2400pci_write_beacon,
95ea3627 1759 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1760 .config_filter = rt2400pci_config_filter,
6bb40dd1 1761 .config_intf = rt2400pci_config_intf,
72810379 1762 .config_erp = rt2400pci_config_erp,
e4ea1c40 1763 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1764 .config = rt2400pci_config,
1765};
1766
3d8979ba
GJ		 1767static void rt2400pci_queue_init(struct data_queue *queue)
1768{
1769 switch (queue->qid) {
1770 case QID_RX:
1771 queue->limit = 24;
1772 queue->data_size = DATA_FRAME_SIZE;
1773 queue->desc_size = RXD_DESC_SIZE;
1774 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1775 break;
181d6902 1776
3d8979ba
GJ		 1777 case QID_AC_VO:
1778 case QID_AC_VI:
1779 case QID_AC_BE:
1780 case QID_AC_BK:
1781 queue->limit = 24;
1782 queue->data_size = DATA_FRAME_SIZE;
1783 queue->desc_size = TXD_DESC_SIZE;
1784 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1785 break;
181d6902 1786
3d8979ba
GJ		 1787 case QID_BEACON:
1788 queue->limit = 1;
1789 queue->data_size = MGMT_FRAME_SIZE;
1790 queue->desc_size = TXD_DESC_SIZE;
1791 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1792 break;
181d6902 1793
3d8979ba
GJ		 1794 case QID_ATIM:
1795 queue->limit = 8;
1796 queue->data_size = DATA_FRAME_SIZE;
1797 queue->desc_size = TXD_DESC_SIZE;
1798 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
1799 break;
1800
1801 default:
1802 BUG();
1803 break;
1804 }
1805}
181d6902 1806
95ea3627 1807static const struct rt2x00_ops rt2400pci_ops = {
04d0362e 1808 .name = KBUILD_MODNAME,
04d0362e
GW		 1809 .max_ap_intf = 1,
1810 .eeprom_size = EEPROM_SIZE,
1811 .rf_size = RF_SIZE,
1812 .tx_queues = NUM_TX_QUEUES,
3d8979ba 1813 .queue_init = rt2400pci_queue_init,
04d0362e
GW		 1814 .lib = &rt2400pci_rt2x00_ops,
1815 .hw = &rt2400pci_mac80211_ops,
95ea3627 1816#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1817 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1818#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1819};
1820
1821/*
1822 * RT2400pci module information.
1823 */
9baa3c34 1824static const struct pci_device_id rt2400pci_device_table[] = {
e01ae27f 1825 { PCI_DEVICE(0x1814, 0x0101) },
95ea3627
ID		 1826 { 0, }
1827};
1828
e01ae27f 1829
95ea3627
ID		 1830MODULE_AUTHOR(DRV_PROJECT);
1831MODULE_VERSION(DRV_VERSION);
1832MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1833MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1834MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1835MODULE_LICENSE("GPL");
1836
e01ae27f
GW		 1837static int rt2400pci_probe(struct pci_dev *pci_dev,
1838 const struct pci_device_id *id)
1839{
1840 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1841}
1842
95ea3627 1843static struct pci_driver rt2400pci_driver = {
2360157c 1844 .name = KBUILD_MODNAME,
95ea3627 1845 .id_table = rt2400pci_device_table,
e01ae27f 1846 .probe = rt2400pci_probe,
69202359 1847 .remove = rt2x00pci_remove,
95ea3627
ID		 1848 .suspend = rt2x00pci_suspend,
1849 .resume = rt2x00pci_resume,
1850};
1851
5b0a3b7e 1852module_pci_driver(rt2400pci_driver);
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