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b43legacy: reinit on too many PHY TX errors
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt2400pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt2400pci.h"
43
44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
0e14f6d3 57static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 58{
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70}
71
0e14f6d3 72static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 73 const unsigned int word, const u8 value)
74{
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2400pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96}
97
0e14f6d3 98static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 99 const unsigned int word, u8 *value)
100{
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2400pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2400pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133}
134
0e14f6d3 135static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 136 const unsigned int word, const u32 value)
137{
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163}
164
165static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166{
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178}
179
180static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181{
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193}
194
195#ifdef CONFIG_RT2X00_LIB_DEBUGFS
196#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
0e14f6d3 198static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 199 const unsigned int word, u32 *data)
200{
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202}
203
0e14f6d3 204static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 205 const unsigned int word, u32 data)
206{
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208}
209
210static const struct rt2x00debug rt2400pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2400pci_read_csr,
214 .write = rt2400pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2400pci_bbp_read,
226 .write = rt2400pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2400pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236};
237#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239#ifdef CONFIG_RT2400PCI_RFKILL
240static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241{
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246}
81873e9c
ID		 247#else
248#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 249#endif /* CONFIG_RT2400PCI_RFKILL */
250
251/*
252 * Configuration handlers.
253 */
4abee4bb
ID		 254static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
255 __le32 *mac)
95ea3627 256{
4abee4bb
ID		 257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
95ea3627
ID		 259}
260
4abee4bb
ID		 261static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
262 __le32 *bssid)
95ea3627 263{
4abee4bb
ID		 264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
95ea3627
ID		 266}
267
feb24691
ID		 268static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
269 const int tsf_sync)
95ea3627
ID		 270{
271 u32 reg;
272
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
274
95ea3627
ID		 275 /*
276 * Enable beacon config
277 */
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
279 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 281 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
282
283 /*
284 * Enable synchronisation.
285 */
286 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572
JB		 287 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
288 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627 289 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 290 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 291 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
292}
293
5c58ee51
ID		 294static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
295 const int short_preamble,
296 const int ack_timeout,
297 const int ack_consume_time)
95ea3627 298{
5c58ee51 299 int preamble_mask;
95ea3627 300 u32 reg;
95ea3627 301
5c58ee51
ID		 302 /*
303 * When short preamble is enabled, we should set bit 0x08
304 */
305 preamble_mask = short_preamble << 3;
95ea3627
ID		 306
307 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 308 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
309 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 310 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
311
95ea3627 312 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 313 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 314 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
315 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
316 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
317
318 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 319 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 320 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
321 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
322 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
323
324 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 325 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 326 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
327 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
328 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
329
330 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 331 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 332 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
333 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
334 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
335}
336
337static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 338 const int basic_rate_mask)
95ea3627 339{
5c58ee51 340 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 341}
342
343static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 344 struct rf_channel *rf)
95ea3627 345{
95ea3627
ID		 346 /*
347 * Switch on tuning bits.
348 */
5c58ee51
ID		 349 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
350 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 351
5c58ee51
ID		 352 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
353 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
354 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 355
356 /*
357 * RF2420 chipset don't need any additional actions.
358 */
359 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
360 return;
361
362 /*
363 * For the RT2421 chipsets we need to write an invalid
364 * reference clock rate to activate auto_tune.
365 * After that we set the value back to the correct channel.
366 */
5c58ee51 367 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 368 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 369 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 370
371 msleep(1);
372
5c58ee51
ID		 373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 376
377 msleep(1);
378
379 /*
380 * Switch off tuning bits.
381 */
5c58ee51
ID		 382 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
383 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 384
5c58ee51
ID		 385 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 387
388 /*
389 * Clear false CRC during channel switch.
390 */
5c58ee51 391 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 392}
393
394static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
395{
396 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
397}
398
399static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 400 struct antenna_setup *ant)
95ea3627
ID		 401{
402 u8 r1;
403 u8 r4;
404
405 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
406 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
407
408 /*
409 * Configure the TX antenna.
410 */
addc81bd 411 switch (ant->tx) {
95ea3627
ID		 412 case ANTENNA_HW_DIVERSITY:
413 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
414 break;
415 case ANTENNA_A:
416 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
417 break;
39e75857
ID		 418 case ANTENNA_SW_DIVERSITY:
419 /*
420 * NOTE: We should never come here because rt2x00lib is
421 * supposed to catch this and send us the correct antenna
422 * explicitely. However we are nog going to bug about this.
423 * Instead, just default to antenna B.
424 */
95ea3627
ID		 425 case ANTENNA_B:
426 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
427 break;
428 }
429
430 /*
431 * Configure the RX antenna.
432 */
addc81bd 433 switch (ant->rx) {
95ea3627
ID		 434 case ANTENNA_HW_DIVERSITY:
435 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
436 break;
437 case ANTENNA_A:
438 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
439 break;
39e75857
ID		 440 case ANTENNA_SW_DIVERSITY:
441 /*
442 * NOTE: We should never come here because rt2x00lib is
443 * supposed to catch this and send us the correct antenna
444 * explicitely. However we are nog going to bug about this.
445 * Instead, just default to antenna B.
446 */
95ea3627
ID		 447 case ANTENNA_B:
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
449 break;
450 }
451
452 rt2400pci_bbp_write(rt2x00dev, 4, r4);
453 rt2400pci_bbp_write(rt2x00dev, 1, r1);
454}
455
456static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 457 struct rt2x00lib_conf *libconf)
95ea3627
ID		 458{
459 u32 reg;
460
461 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 462 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 463 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
464
465 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 466 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
467 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 468 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
469
470 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 471 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
472 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 473 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
474
475 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
476 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
477 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
478 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
479
480 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 481 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
482 libconf->conf->beacon_int * 16);
483 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
484 libconf->conf->beacon_int * 16);
95ea3627
ID		 485 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
486}
487
488static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
489 const unsigned int flags,
5c58ee51 490 struct rt2x00lib_conf *libconf)
95ea3627 491{
95ea3627 492 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 493 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 494 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 495 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 496 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 497 rt2400pci_config_txpower(rt2x00dev,
498 libconf->conf->power_level);
95ea3627 499 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 500 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 501 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 502 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 503}
504
505static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
506 struct ieee80211_tx_queue_params *params)
507{
508 u32 reg;
509
510 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
511 rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
512 rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
513 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
514}
515
516/*
517 * LED functions.
518 */
519static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
520{
521 u32 reg;
522
523 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
524
525 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
526 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
ddc827f9
ID		 527 rt2x00_set_field32(&reg, LEDCSR_LINK,
528 (rt2x00dev->led_mode != LED_MODE_ASUS));
529 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
530 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
95ea3627
ID		 531 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
532}
533
534static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
535{
536 u32 reg;
537
538 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
539 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
540 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
541 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
542}
543
544/*
545 * Link tuning
546 */
ebcf26da
ID		 547static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
548 struct link_qual *qual)
95ea3627
ID		 549{
550 u32 reg;
551 u8 bbp;
552
553 /*
554 * Update FCS error count from register.
555 */
556 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 557 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 558
559 /*
560 * Update False CCA count from register.
561 */
562 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 563 qual->false_cca = bbp;
95ea3627
ID		 564}
565
566static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
567{
568 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
569 rt2x00dev->link.vgc_level = 0x08;
570}
571
572static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
573{
574 u8 reg;
575
576 /*
577 * The link tuner should not run longer then 60 seconds,
578 * and should run once every 2 seconds.
579 */
580 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
581 return;
582
583 /*
584 * Base r13 link tuning on the false cca count.
585 */
586 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
587
ebcf26da 588 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 589 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
590 rt2x00dev->link.vgc_level = reg;
ebcf26da 591 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 592 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
593 rt2x00dev->link.vgc_level = reg;
594 }
595}
596
597/*
598 * Initialization functions.
599 */
600static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
601{
602 struct data_ring *ring = rt2x00dev->rx;
4bd7c452 603 __le32 *rxd;
95ea3627
ID		 604 unsigned int i;
605 u32 word;
606
607 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
608
609 for (i = 0; i < ring->stats.limit; i++) {
610 rxd = ring->entry[i].priv;
611
612 rt2x00_desc_read(rxd, 2, &word);
613 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
614 ring->data_size);
615 rt2x00_desc_write(rxd, 2, word);
616
617 rt2x00_desc_read(rxd, 1, &word);
618 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
619 ring->entry[i].data_dma);
620 rt2x00_desc_write(rxd, 1, word);
621
622 rt2x00_desc_read(rxd, 0, &word);
623 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
624 rt2x00_desc_write(rxd, 0, word);
625 }
626
627 rt2x00_ring_index_clear(rt2x00dev->rx);
628}
629
630static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
631{
632 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
4bd7c452 633 __le32 *txd;
95ea3627
ID		 634 unsigned int i;
635 u32 word;
636
637 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
638
639 for (i = 0; i < ring->stats.limit; i++) {
640 txd = ring->entry[i].priv;
641
642 rt2x00_desc_read(txd, 1, &word);
643 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
644 ring->entry[i].data_dma);
645 rt2x00_desc_write(txd, 1, word);
646
647 rt2x00_desc_read(txd, 2, &word);
648 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
649 ring->data_size);
650 rt2x00_desc_write(txd, 2, word);
651
652 rt2x00_desc_read(txd, 0, &word);
653 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
654 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
655 rt2x00_desc_write(txd, 0, word);
656 }
657
658 rt2x00_ring_index_clear(ring);
659}
660
661static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
662{
663 u32 reg;
664
665 /*
666 * Initialize rings.
667 */
668 rt2400pci_init_rxring(rt2x00dev);
669 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
670 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
671 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
672 rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
673
674 /*
675 * Initialize registers.
676 */
677 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
678 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
679 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
680 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
681 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
682 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
683 rt2x00dev->bcn[1].stats.limit);
684 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
685 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
686 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
687
688 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
689 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
690 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
691 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
692
693 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
694 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
695 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
696 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
697
698 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
699 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
700 rt2x00dev->bcn[1].data_dma);
701 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
702
703 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
704 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
705 rt2x00dev->bcn[0].data_dma);
706 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
707
708 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
709 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
710 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
711 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
712
713 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
714 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
715 rt2x00dev->rx->data_dma);
716 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
717
718 return 0;
719}
720
721static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
722{
723 u32 reg;
724
725 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
726 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
727 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
728 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
729
730 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
731 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
732 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
733 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
734 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
735
736 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
737 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
738 (rt2x00dev->rx->data_size / 128));
739 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
740
741 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
742
743 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
744 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
745 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
746 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
747 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
748 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
749
750 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
751 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
752 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
753 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
754 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
755 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
756 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
757 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
758
759 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
760
761 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
762 return -EBUSY;
763
764 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
765 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
766
767 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
768 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
769 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
770
771 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
772 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
773 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
774 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
775 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
776 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
777
778 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
779 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
780 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
781 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
782 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
783
784 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
785 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
786 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
787 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
788
789 /*
790 * We must clear the FCS and FIFO error count.
791 * These registers are cleared on read,
792 * so we may pass a useless variable to store the value.
793 */
794 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
795 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
796
797 return 0;
798}
799
800static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
801{
802 unsigned int i;
803 u16 eeprom;
804 u8 reg_id;
805 u8 value;
806
807 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
808 rt2400pci_bbp_read(rt2x00dev, 0, &value);
809 if ((value != 0xff) && (value != 0x00))
810 goto continue_csr_init;
811 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
812 udelay(REGISTER_BUSY_DELAY);
813 }
814
815 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
816 return -EACCES;
817
818continue_csr_init:
819 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
820 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
821 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
822 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
823 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
824 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
825 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
826 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
827 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
828 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
829 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
830 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
831 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
832 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
833
834 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
835 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
836 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
837
838 if (eeprom != 0xffff && eeprom != 0x0000) {
839 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
840 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
841 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
842 reg_id, value);
843 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
844 }
845 }
846 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
847
848 return 0;
849}
850
851/*
852 * Device state switch handlers.
853 */
854static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
855 enum dev_state state)
856{
857 u32 reg;
858
859 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
860 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
861 state == STATE_RADIO_RX_OFF);
862 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
863}
864
865static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
866 enum dev_state state)
867{
868 int mask = (state == STATE_RADIO_IRQ_OFF);
869 u32 reg;
870
871 /*
872 * When interrupts are being enabled, the interrupt registers
873 * should clear the register to assure a clean state.
874 */
875 if (state == STATE_RADIO_IRQ_ON) {
876 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
877 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
878 }
879
880 /*
881 * Only toggle the interrupts bits we are going to use.
882 * Non-checked interrupt bits are disabled by default.
883 */
884 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
885 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
886 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
887 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
888 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
889 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
890 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
891}
892
893static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
894{
895 /*
896 * Initialize all registers.
897 */
898 if (rt2400pci_init_rings(rt2x00dev) ||
899 rt2400pci_init_registers(rt2x00dev) ||
900 rt2400pci_init_bbp(rt2x00dev)) {
901 ERROR(rt2x00dev, "Register initialization failed.\n");
902 return -EIO;
903 }
904
905 /*
906 * Enable interrupts.
907 */
908 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
909
910 /*
911 * Enable LED
912 */
913 rt2400pci_enable_led(rt2x00dev);
914
915 return 0;
916}
917
918static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
919{
920 u32 reg;
921
922 /*
923 * Disable LED
924 */
925 rt2400pci_disable_led(rt2x00dev);
926
927 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
928
929 /*
930 * Disable synchronisation.
931 */
932 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
933
934 /*
935 * Cancel RX and TX.
936 */
937 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
938 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
939 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
940
941 /*
942 * Disable interrupts.
943 */
944 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
945}
946
947static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
948 enum dev_state state)
949{
950 u32 reg;
951 unsigned int i;
952 char put_to_sleep;
953 char bbp_state;
954 char rf_state;
955
956 put_to_sleep = (state != STATE_AWAKE);
957
958 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
959 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
960 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
961 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
962 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
963 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
964
965 /*
966 * Device is not guaranteed to be in the requested state yet.
967 * We must wait until the register indicates that the
968 * device has entered the correct state.
969 */
970 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
971 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
972 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
973 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
974 if (bbp_state == state && rf_state == state)
975 return 0;
976 msleep(10);
977 }
978
979 NOTICE(rt2x00dev, "Device failed to enter state %d, "
980 "current device state: bbp %d and rf %d.\n",
981 state, bbp_state, rf_state);
982
983 return -EBUSY;
984}
985
986static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
987 enum dev_state state)
988{
989 int retval = 0;
990
991 switch (state) {
992 case STATE_RADIO_ON:
993 retval = rt2400pci_enable_radio(rt2x00dev);
994 break;
995 case STATE_RADIO_OFF:
996 rt2400pci_disable_radio(rt2x00dev);
997 break;
998 case STATE_RADIO_RX_ON:
999 case STATE_RADIO_RX_OFF:
1000 rt2400pci_toggle_rx(rt2x00dev, state);
1001 break;
1002 case STATE_DEEP_SLEEP:
1003 case STATE_SLEEP:
1004 case STATE_STANDBY:
1005 case STATE_AWAKE:
1006 retval = rt2400pci_set_state(rt2x00dev, state);
1007 break;
1008 default:
1009 retval = -ENOTSUPP;
1010 break;
1011 }
1012
1013 return retval;
1014}
1015
1016/*
1017 * TX descriptor initialization
1018 */
1019static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
4bd7c452 1020 __le32 *txd,
4150c572 1021 struct txdata_entry_desc *desc,
95ea3627
ID		 1022 struct ieee80211_hdr *ieee80211hdr,
1023 unsigned int length,
1024 struct ieee80211_tx_control *control)
1025{
1026 u32 word;
1027 u32 signal = 0;
1028 u32 service = 0;
1029 u32 length_high = 0;
1030 u32 length_low = 0;
1031
1032 /*
1033 * The PLCP values should be treated as if they
1034 * were BBP values.
1035 */
1036 rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1037 rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1038 rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1039
1040 rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1041 rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1042 rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1043
1044 rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1045 rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1046 rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1047
1048 rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1049 rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1050 rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1051
1052 /*
1053 * Start writing the descriptor words.
1054 */
1055 rt2x00_desc_read(txd, 2, &word);
1056 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1057 rt2x00_desc_write(txd, 2, word);
1058
1059 rt2x00_desc_read(txd, 3, &word);
1060 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1061 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1062 rt2x00_desc_write(txd, 3, word);
1063
1064 rt2x00_desc_read(txd, 4, &word);
1065 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1066 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1067 rt2x00_desc_write(txd, 4, word);
1068
1069 rt2x00_desc_read(txd, 0, &word);
1070 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1071 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1072 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1073 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1074 rt2x00_set_field32(&word, TXD_W0_ACK,
2700f8b0 1075 test_bit(ENTRY_TXD_ACK, &desc->flags));
95ea3627
ID		 1076 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1077 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1078 rt2x00_set_field32(&word, TXD_W0_RTS,
1079 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1080 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1081 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1082 !!(control->flags &
1083 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1084 rt2x00_desc_write(txd, 0, word);
1085}
1086
1087/*
1088 * TX data initialization
1089 */
1090static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1091 unsigned int queue)
1092{
1093 u32 reg;
1094
1095 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1096 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1097 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1098 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1099 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1100 }
1101 return;
1102 }
1103
1104 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1105 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1106 (queue == IEEE80211_TX_QUEUE_DATA0));
1107 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1108 (queue == IEEE80211_TX_QUEUE_DATA1));
1109 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1110 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
95ea3627
ID		 1111 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1112}
1113
1114/*
1115 * RX control handlers
1116 */
4150c572
JB		 1117static void rt2400pci_fill_rxdone(struct data_entry *entry,
1118 struct rxdata_entry_desc *desc)
95ea3627 1119{
4bd7c452 1120 __le32 *rxd = entry->priv;
95ea3627
ID		 1121 u32 word0;
1122 u32 word2;
1123
1124 rt2x00_desc_read(rxd, 0, &word0);
1125 rt2x00_desc_read(rxd, 2, &word2);
1126
4150c572
JB		 1127 desc->flags = 0;
1128 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1129 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1130 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1131 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1132
1133 /*
1134 * Obtain the status about this packet.
1135 */
4150c572
JB		 1136 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1137 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1138 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1139 desc->ofdm = 0;
1140 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1141}
1142
1143/*
1144 * Interrupt functions.
1145 */
1146static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1147{
1148 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1149 struct data_entry *entry;
4bd7c452 1150 __le32 *txd;
95ea3627
ID		 1151 u32 word;
1152 int tx_status;
1153 int retry;
1154
1155 while (!rt2x00_ring_empty(ring)) {
1156 entry = rt2x00_get_data_entry_done(ring);
1157 txd = entry->priv;
1158 rt2x00_desc_read(txd, 0, &word);
1159
1160 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1161 !rt2x00_get_field32(word, TXD_W0_VALID))
1162 break;
1163
1164 /*
1165 * Obtain the status about this packet.
1166 */
1167 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1168 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1169
3957ccb5 1170 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
95ea3627 1171 }
95ea3627
ID		 1172}
1173
1174static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1175{
1176 struct rt2x00_dev *rt2x00dev = dev_instance;
1177 u32 reg;
1178
1179 /*
1180 * Get the interrupt sources & saved to local variable.
1181 * Write register value back to clear pending interrupts.
1182 */
1183 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1184 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1185
1186 if (!reg)
1187 return IRQ_NONE;
1188
1189 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1190 return IRQ_HANDLED;
1191
1192 /*
1193 * Handle interrupts, walk through all bits
1194 * and run the tasks, the bits are checked in order of
1195 * priority.
1196 */
1197
1198 /*
1199 * 1 - Beacon timer expired interrupt.
1200 */
1201 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1202 rt2x00lib_beacondone(rt2x00dev);
1203
1204 /*
1205 * 2 - Rx ring done interrupt.
1206 */
1207 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1208 rt2x00pci_rxdone(rt2x00dev);
1209
1210 /*
1211 * 3 - Atim ring transmit done interrupt.
1212 */
1213 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1214 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1215
1216 /*
1217 * 4 - Priority ring transmit done interrupt.
1218 */
1219 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1220 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1221
1222 /*
1223 * 5 - Tx ring transmit done interrupt.
1224 */
1225 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1226 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1227
1228 return IRQ_HANDLED;
1229}
1230
1231/*
1232 * Device probe functions.
1233 */
1234static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1235{
1236 struct eeprom_93cx6 eeprom;
1237 u32 reg;
1238 u16 word;
1239 u8 *mac;
1240
1241 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1242
1243 eeprom.data = rt2x00dev;
1244 eeprom.register_read = rt2400pci_eepromregister_read;
1245 eeprom.register_write = rt2400pci_eepromregister_write;
1246 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1247 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1248 eeprom.reg_data_in = 0;
1249 eeprom.reg_data_out = 0;
1250 eeprom.reg_data_clock = 0;
1251 eeprom.reg_chip_select = 0;
1252
1253 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1254 EEPROM_SIZE / sizeof(u16));
1255
1256 /*
1257 * Start validation of the data that has been read.
1258 */
1259 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1260 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1261 DECLARE_MAC_BUF(macbuf);
1262
95ea3627 1263 random_ether_addr(mac);
0795af57 1264 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1265 }
1266
1267 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1268 if (word == 0xffff) {
1269 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1270 return -EINVAL;
1271 }
1272
1273 return 0;
1274}
1275
1276static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1277{
1278 u32 reg;
1279 u16 value;
1280 u16 eeprom;
1281
1282 /*
1283 * Read EEPROM word for configuration.
1284 */
1285 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1286
1287 /*
1288 * Identify RF chipset.
1289 */
1290 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1291 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1292 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1293
1294 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1295 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1296 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1297 return -ENODEV;
1298 }
1299
1300 /*
1301 * Identify default antenna configuration.
1302 */
addc81bd 1303 rt2x00dev->default_ant.tx =
95ea3627 1304 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1305 rt2x00dev->default_ant.rx =
95ea3627
ID		 1306 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1307
addc81bd
ID		 1308 /*
1309 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1310 * I am not 100% sure about this, but the legacy drivers do not
1311 * indicate antenna swapping in software is required when
1312 * diversity is enabled.
1313 */
1314 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1315 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1316 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1317 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1318
95ea3627
ID		 1319 /*
1320 * Store led mode, for correct led behaviour.
1321 */
1322 rt2x00dev->led_mode =
1323 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1324
1325 /*
1326 * Detect if this device has an hardware controlled radio.
1327 */
81873e9c 1328#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1329 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1330 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1331#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1332
1333 /*
1334 * Check if the BBP tuning should be enabled.
1335 */
1336 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1337 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1338
1339 return 0;
1340}
1341
1342/*
1343 * RF value list for RF2420 & RF2421
1344 * Supports: 2.4 GHz
1345 */
1346static const struct rf_channel rf_vals_bg[] = {
1347 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1348 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1349 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1350 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1351 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1352 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1353 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1354 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1355 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1356 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1357 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1358 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1359 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1360 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1361};
1362
1363static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1364{
1365 struct hw_mode_spec *spec = &rt2x00dev->spec;
1366 u8 *txpower;
1367 unsigned int i;
1368
1369 /*
1370 * Initialize all hw fields.
1371 */
4150c572 1372 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1373 rt2x00dev->hw->extra_tx_headroom = 0;
1374 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1375 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1376 rt2x00dev->hw->queues = 2;
1377
1378 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1379 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1380 rt2x00_eeprom_addr(rt2x00dev,
1381 EEPROM_MAC_ADDR_0));
1382
1383 /*
1384 * Convert tx_power array in eeprom.
1385 */
1386 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1387 for (i = 0; i < 14; i++)
1388 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1389
1390 /*
1391 * Initialize hw_mode information.
1392 */
1393 spec->num_modes = 1;
1394 spec->num_rates = 4;
1395 spec->tx_power_a = NULL;
1396 spec->tx_power_bg = txpower;
1397 spec->tx_power_default = DEFAULT_TXPOWER;
1398
1399 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1400 spec->channels = rf_vals_bg;
1401}
1402
1403static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1404{
1405 int retval;
1406
1407 /*
1408 * Allocate eeprom data.
1409 */
1410 retval = rt2400pci_validate_eeprom(rt2x00dev);
1411 if (retval)
1412 return retval;
1413
1414 retval = rt2400pci_init_eeprom(rt2x00dev);
1415 if (retval)
1416 return retval;
1417
1418 /*
1419 * Initialize hw specifications.
1420 */
1421 rt2400pci_probe_hw_mode(rt2x00dev);
1422
1423 /*
1424 * This device requires the beacon ring
1425 */
066cb637 1426 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1427
1428 /*
1429 * Set the rssi offset.
1430 */
1431 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1432
1433 return 0;
1434}
1435
1436/*
1437 * IEEE80211 stack callback functions.
1438 */
4150c572
JB		 1439static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1440 unsigned int changed_flags,
1441 unsigned int *total_flags,
1442 int mc_count,
1443 struct dev_addr_list *mc_list)
1444{
1445 struct rt2x00_dev *rt2x00dev = hw->priv;
1446 struct interface *intf = &rt2x00dev->interface;
1447 u32 reg;
1448
1449 /*
1450 * Mask off any flags we are going to ignore from
1451 * the total_flags field.
1452 */
1453 *total_flags &=
1454 FIF_ALLMULTI |
1455 FIF_FCSFAIL |
1456 FIF_PLCPFAIL |
1457 FIF_CONTROL |
1458 FIF_OTHER_BSS |
1459 FIF_PROMISC_IN_BSS;
1460
1461 /*
1462 * Apply some rules to the filters:
1463 * - Some filters imply different filters to be set.
1464 * - Some things we can't filter out at all.
1465 * - Some filters are set based on interface type.
1466 */
1467 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1468 if (*total_flags & FIF_OTHER_BSS ||
1469 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1470 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1471 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1472 *total_flags |= FIF_PROMISC_IN_BSS;
1473
1474 /*
1475 * Check if there is any work left for us.
1476 */
1477 if (intf->filter == *total_flags)
1478 return;
1479 intf->filter = *total_flags;
1480
1481 /*
1482 * Start configuration steps.
1483 * Note that the version error will always be dropped
1484 * since there is no filter for it at this time.
1485 */
1486 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1487 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1488 !(*total_flags & FIF_FCSFAIL));
1489 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1490 !(*total_flags & FIF_PLCPFAIL));
1491 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1492 !(*total_flags & FIF_CONTROL));
1493 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1494 !(*total_flags & FIF_PROMISC_IN_BSS));
1495 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1496 !(*total_flags & FIF_PROMISC_IN_BSS));
1497 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1498 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1499}
1500
95ea3627
ID		 1501static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1502 u32 short_retry, u32 long_retry)
1503{
1504 struct rt2x00_dev *rt2x00dev = hw->priv;
1505 u32 reg;
1506
1507 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1508 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1509 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1510 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1511
1512 return 0;
1513}
1514
1515static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1516 int queue,
1517 const struct ieee80211_tx_queue_params *params)
1518{
1519 struct rt2x00_dev *rt2x00dev = hw->priv;
1520
1521 /*
1522 * We don't support variating cw_min and cw_max variables
1523 * per queue. So by default we only configure the TX queue,
1524 * and ignore all other configurations.
1525 */
1526 if (queue != IEEE80211_TX_QUEUE_DATA0)
1527 return -EINVAL;
1528
1529 if (rt2x00mac_conf_tx(hw, queue, params))
1530 return -EINVAL;
1531
1532 /*
1533 * Write configuration to register.
1534 */
1535 rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1536
1537 return 0;
1538}
1539
1540static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1541{
1542 struct rt2x00_dev *rt2x00dev = hw->priv;
1543 u64 tsf;
1544 u32 reg;
1545
1546 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1547 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1548 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1549 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1550
1551 return tsf;
1552}
1553
1554static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1555{
1556 struct rt2x00_dev *rt2x00dev = hw->priv;
1557
1558 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1559 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1560}
1561
1562static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1563{
1564 struct rt2x00_dev *rt2x00dev = hw->priv;
1565 u32 reg;
1566
1567 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1568 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1569}
1570
1571static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1572 .tx = rt2x00mac_tx,
4150c572
JB		 1573 .start = rt2x00mac_start,
1574 .stop = rt2x00mac_stop,
95ea3627
ID		 1575 .add_interface = rt2x00mac_add_interface,
1576 .remove_interface = rt2x00mac_remove_interface,
1577 .config = rt2x00mac_config,
1578 .config_interface = rt2x00mac_config_interface,
4150c572 1579 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1580 .get_stats = rt2x00mac_get_stats,
1581 .set_retry_limit = rt2400pci_set_retry_limit,
5c58ee51 1582 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1583 .conf_tx = rt2400pci_conf_tx,
1584 .get_tx_stats = rt2x00mac_get_tx_stats,
1585 .get_tsf = rt2400pci_get_tsf,
1586 .reset_tsf = rt2400pci_reset_tsf,
1587 .beacon_update = rt2x00pci_beacon_update,
1588 .tx_last_beacon = rt2400pci_tx_last_beacon,
1589};
1590
1591static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1592 .irq_handler = rt2400pci_interrupt,
1593 .probe_hw = rt2400pci_probe_hw,
1594 .initialize = rt2x00pci_initialize,
1595 .uninitialize = rt2x00pci_uninitialize,
1596 .set_device_state = rt2400pci_set_device_state,
95ea3627 1597 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1598 .link_stats = rt2400pci_link_stats,
1599 .reset_tuner = rt2400pci_reset_tuner,
1600 .link_tuner = rt2400pci_link_tuner,
1601 .write_tx_desc = rt2400pci_write_tx_desc,
1602 .write_tx_data = rt2x00pci_write_tx_data,
1603 .kick_tx_queue = rt2400pci_kick_tx_queue,
1604 .fill_rxdone = rt2400pci_fill_rxdone,
1605 .config_mac_addr = rt2400pci_config_mac_addr,
1606 .config_bssid = rt2400pci_config_bssid,
95ea3627 1607 .config_type = rt2400pci_config_type,
5c58ee51 1608 .config_preamble = rt2400pci_config_preamble,
95ea3627
ID		 1609 .config = rt2400pci_config,
1610};
1611
1612static const struct rt2x00_ops rt2400pci_ops = {
1613 .name = DRV_NAME,
1614 .rxd_size = RXD_DESC_SIZE,
1615 .txd_size = TXD_DESC_SIZE,
1616 .eeprom_size = EEPROM_SIZE,
1617 .rf_size = RF_SIZE,
1618 .lib = &rt2400pci_rt2x00_ops,
1619 .hw = &rt2400pci_mac80211_ops,
1620#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1621 .debugfs = &rt2400pci_rt2x00debug,
1622#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1623};
1624
1625/*
1626 * RT2400pci module information.
1627 */
1628static struct pci_device_id rt2400pci_device_table[] = {
1629 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1630 { 0, }
1631};
1632
1633MODULE_AUTHOR(DRV_PROJECT);
1634MODULE_VERSION(DRV_VERSION);
1635MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1636MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1637MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1638MODULE_LICENSE("GPL");
1639
1640static struct pci_driver rt2400pci_driver = {
1641 .name = DRV_NAME,
1642 .id_table = rt2400pci_device_table,
1643 .probe = rt2x00pci_probe,
1644 .remove = __devexit_p(rt2x00pci_remove),
1645 .suspend = rt2x00pci_suspend,
1646 .resume = rt2x00pci_resume,
1647};
1648
1649static int __init rt2400pci_init(void)
1650{
1651 return pci_register_driver(&rt2400pci_driver);
1652}
1653
1654static void __exit rt2400pci_exit(void)
1655{
1656 pci_unregister_driver(&rt2400pci_driver);
1657}
1658
1659module_init(rt2400pci_init);
1660module_exit(rt2400pci_exit);
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