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Merge remote-tracking branch 'regulator/topic/palmas' into v3.9-rc8
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
69a2bac8 37#include "rt2x00mmio.h"
95ea3627
ID		 38#include "rt2x00pci.h"
39#include "rt2400pci.h"
40
41/*
42 * Register access.
43 * All access to the CSR registers will go through the methods
44 * rt2x00pci_register_read and rt2x00pci_register_write.
45 * BBP and RF register require indirect register access,
46 * and use the CSR registers BBPCSR and RFCSR to achieve this.
47 * These indirect registers work with busy bits,
48 * and we will try maximal REGISTER_BUSY_COUNT times to access
49 * the register while taking a REGISTER_BUSY_DELAY us delay
f5a9987d 50 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 51 * the access attempt is considered to have failed,
52 * and we will print an error.
53 */
c9c3b1a5
ID		 54#define WAIT_FOR_BBP(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
56#define WAIT_FOR_RF(__dev, __reg) \
57 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 58
0e14f6d3 59static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 60 const unsigned int word, const u8 value)
61{
62 u32 reg;
63
8ff48a8b
ID		 64 mutex_lock(&rt2x00dev->csr_mutex);
65
95ea3627 66 /*
c9c3b1a5
ID		 67 * Wait until the BBP becomes available, afterwards we
68 * can safely write the new data into the register.
95ea3627 69 */
c9c3b1a5
ID		 70 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
71 reg = 0;
72 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
73 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
74 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
75 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
76
77 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
78 }
8ff48a8b 79
8ff48a8b 80 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 81}
82
0e14f6d3 83static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int word, u8 *value)
85{
86 u32 reg;
87
8ff48a8b
ID		 88 mutex_lock(&rt2x00dev->csr_mutex);
89
95ea3627 90 /*
c9c3b1a5
ID		 91 * Wait until the BBP becomes available, afterwards we
92 * can safely write the read request into the register.
93 * After the data has been written, we wait until hardware
94 * returns the correct value, if at any time the register
95 * doesn't become available in time, reg will be 0xffffffff
96 * which means we return 0xff to the caller.
95ea3627 97 */
c9c3b1a5
ID		 98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
101 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
102 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 103
c9c3b1a5 104 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 105
c9c3b1a5
ID		 106 WAIT_FOR_BBP(rt2x00dev, &reg);
107 }
95ea3627
ID		 108
109 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 110
111 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 112}
113
0e14f6d3 114static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 115 const unsigned int word, const u32 value)
116{
117 u32 reg;
95ea3627 118
8ff48a8b
ID		 119 mutex_lock(&rt2x00dev->csr_mutex);
120
c9c3b1a5
ID		 121 /*
122 * Wait until the RF becomes available, afterwards we
123 * can safely write the new data into the register.
124 */
125 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
128 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
129 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
130 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
131
132 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
133 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 134 }
135
8ff48a8b 136 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 137}
138
139static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
140{
141 struct rt2x00_dev *rt2x00dev = eeprom->data;
142 u32 reg;
143
144 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
145
146 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
147 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
148 eeprom->reg_data_clock =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
150 eeprom->reg_chip_select =
151 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
152}
153
154static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
155{
156 struct rt2x00_dev *rt2x00dev = eeprom->data;
157 u32 reg = 0;
158
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
162 !!eeprom->reg_data_clock);
163 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
164 !!eeprom->reg_chip_select);
165
166 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
167}
168
169#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 170static const struct rt2x00debug rt2400pci_rt2x00debug = {
171 .owner = THIS_MODULE,
172 .csr = {
743b97ca
ID		 173 .read = rt2x00pci_register_read,
174 .write = rt2x00pci_register_write,
175 .flags = RT2X00DEBUGFS_OFFSET,
176 .word_base = CSR_REG_BASE,
95ea3627
ID		 177 .word_size = sizeof(u32),
178 .word_count = CSR_REG_SIZE / sizeof(u32),
179 },
180 .eeprom = {
181 .read = rt2x00_eeprom_read,
182 .write = rt2x00_eeprom_write,
743b97ca 183 .word_base = EEPROM_BASE,
95ea3627
ID		 184 .word_size = sizeof(u16),
185 .word_count = EEPROM_SIZE / sizeof(u16),
186 },
187 .bbp = {
188 .read = rt2400pci_bbp_read,
189 .write = rt2400pci_bbp_write,
743b97ca 190 .word_base = BBP_BASE,
95ea3627
ID		 191 .word_size = sizeof(u8),
192 .word_count = BBP_SIZE / sizeof(u8),
193 },
194 .rf = {
195 .read = rt2x00_rf_read,
196 .write = rt2400pci_rf_write,
743b97ca 197 .word_base = RF_BASE,
95ea3627
ID		 198 .word_size = sizeof(u32),
199 .word_count = RF_SIZE / sizeof(u32),
200 },
201};
202#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
203
95ea3627
ID		 204static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
205{
206 u32 reg;
207
208 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 209 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
95ea3627 210}
95ea3627 211
771fd565 212#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 213static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 214 enum led_brightness brightness)
215{
216 struct rt2x00_led *led =
217 container_of(led_cdev, struct rt2x00_led, led_dev);
218 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 219 u32 reg;
220
221 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
222
a2e1d52a 223 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 224 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 225 else if (led->type == LED_TYPE_ACTIVITY)
226 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 227
228 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
229}
a2e1d52a
ID		 230
231static int rt2400pci_blink_set(struct led_classdev *led_cdev,
232 unsigned long *delay_on,
233 unsigned long *delay_off)
234{
235 struct rt2x00_led *led =
236 container_of(led_cdev, struct rt2x00_led, led_dev);
237 u32 reg;
238
239 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
240 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
241 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
242 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
243
244 return 0;
245}
475433be
ID		 246
247static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
248 struct rt2x00_led *led,
249 enum led_type type)
250{
251 led->rt2x00dev = rt2x00dev;
252 led->type = type;
253 led->led_dev.brightness_set = rt2400pci_brightness_set;
254 led->led_dev.blink_set = rt2400pci_blink_set;
255 led->flags = LED_INITIALIZED;
256}
771fd565 257#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 258
95ea3627
ID		 259/*
260 * Configuration handlers.
261 */
3a643d24
ID		 262static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
263 const unsigned int filter_flags)
264{
265 u32 reg;
266
267 /*
268 * Start configuration steps.
269 * Note that the version error will always be dropped
270 * since there is no filter for it at this time.
271 */
272 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
273 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
274 !(filter_flags & FIF_FCSFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
276 !(filter_flags & FIF_PLCPFAIL));
277 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
278 !(filter_flags & FIF_CONTROL));
279 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
280 !(filter_flags & FIF_PROMISC_IN_BSS));
281 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 282 !(filter_flags & FIF_PROMISC_IN_BSS) &&
283 !rt2x00dev->intf_ap_count);
3a643d24
ID		 284 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
286}
287
6bb40dd1
ID		 288static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
289 struct rt2x00_intf *intf,
290 struct rt2x00intf_conf *conf,
291 const unsigned int flags)
95ea3627 292{
6bb40dd1
ID		 293 unsigned int bcn_preload;
294 u32 reg;
95ea3627 295
6bb40dd1 296 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 297 /*
298 * Enable beacon config
299 */
bad13639 300 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 301 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
302 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
303 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 304
6bb40dd1
ID		 305 /*
306 * Enable synchronisation.
307 */
308 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1
ID		 309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
311 }
95ea3627 312
6bb40dd1
ID		 313 if (flags & CONFIG_UPDATE_MAC)
314 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
315 conf->mac, sizeof(conf->mac));
95ea3627 316
6bb40dd1
ID		 317 if (flags & CONFIG_UPDATE_BSSID)
318 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
319 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 320}
321
3a643d24 322static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 323 struct rt2x00lib_erp *erp,
324 u32 changed)
95ea3627 325{
5c58ee51 326 int preamble_mask;
95ea3627 327 u32 reg;
95ea3627 328
5c58ee51
ID		 329 /*
330 * When short preamble is enabled, we should set bit 0x08
331 */
02044643
HS		 332 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
333 preamble_mask = erp->short_preamble << 3;
334
335 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
337 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
338 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
339 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
340 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
341
342 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
343 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
344 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
345 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
346 GET_DURATION(ACK_SIZE, 10));
347 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
348
349 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
350 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
351 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
352 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
353 GET_DURATION(ACK_SIZE, 20));
354 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
355
356 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
357 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
358 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
359 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
360 GET_DURATION(ACK_SIZE, 55));
361 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
362
363 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
364 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
365 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
366 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
367 GET_DURATION(ACK_SIZE, 110));
368 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
369 }
370
371 if (changed & BSS_CHANGED_BASIC_RATES)
372 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
373
374 if (changed & BSS_CHANGED_ERP_SLOT) {
375 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
376 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
377 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
378
379 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
380 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
381 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
382 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
383
384 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
385 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
386 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
387 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
388 }
389
390 if (changed & BSS_CHANGED_BEACON_INT) {
391 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
392 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
393 erp->beacon_int * 16);
394 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
395 erp->beacon_int * 16);
396 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
397 }
95ea3627
ID		 398}
399
e4ea1c40
ID		 400static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
401 struct antenna_setup *ant)
95ea3627 402{
e4ea1c40
ID		 403 u8 r1;
404 u8 r4;
405
406 /*
407 * We should never come here because rt2x00lib is supposed
408 * to catch this and send us the correct antenna explicitely.
409 */
410 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
411 ant->tx == ANTENNA_SW_DIVERSITY);
412
413 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
414 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
415
416 /*
417 * Configure the TX antenna.
418 */
419 switch (ant->tx) {
420 case ANTENNA_HW_DIVERSITY:
421 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
422 break;
423 case ANTENNA_A:
424 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
425 break;
426 case ANTENNA_B:
427 default:
428 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
429 break;
430 }
431
432 /*
433 * Configure the RX antenna.
434 */
435 switch (ant->rx) {
436 case ANTENNA_HW_DIVERSITY:
437 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
438 break;
439 case ANTENNA_A:
440 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
441 break;
442 case ANTENNA_B:
443 default:
444 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
445 break;
446 }
447
448 rt2400pci_bbp_write(rt2x00dev, 4, r4);
449 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 450}
451
452static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 453 struct rf_channel *rf)
95ea3627 454{
95ea3627
ID		 455 /*
456 * Switch on tuning bits.
457 */
5c58ee51
ID		 458 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
459 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 460
5c58ee51
ID		 461 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
462 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
463 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 464
465 /*
466 * RF2420 chipset don't need any additional actions.
467 */
5122d898 468 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 469 return;
470
471 /*
472 * For the RT2421 chipsets we need to write an invalid
473 * reference clock rate to activate auto_tune.
474 * After that we set the value back to the correct channel.
475 */
5c58ee51 476 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 477 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 478 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 479
480 msleep(1);
481
5c58ee51
ID		 482 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
483 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
484 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 485
486 msleep(1);
487
488 /*
489 * Switch off tuning bits.
490 */
5c58ee51
ID		 491 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
492 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 493
5c58ee51
ID		 494 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
495 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 496
497 /*
498 * Clear false CRC during channel switch.
499 */
5c58ee51 500 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 501}
502
503static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
504{
505 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
506}
507
e4ea1c40
ID		 508static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
509 struct rt2x00lib_conf *libconf)
95ea3627 510{
e4ea1c40 511 u32 reg;
95ea3627 512
e4ea1c40
ID		 513 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
514 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
515 libconf->conf->long_frame_max_tx_count);
516 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
517 libconf->conf->short_frame_max_tx_count);
518 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 519}
520
7d7f19cc
ID		 521static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
522 struct rt2x00lib_conf *libconf)
523{
524 enum dev_state state =
525 (libconf->conf->flags & IEEE80211_CONF_PS) ?
526 STATE_SLEEP : STATE_AWAKE;
527 u32 reg;
528
529 if (state == STATE_SLEEP) {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 532 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 533 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
534 libconf->conf->listen_interval - 1);
535
536 /* We must first disable autowake before it can be enabled */
537 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
538 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
539
540 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
541 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 542 } else {
543 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
544 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
545 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 546 }
547
548 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
549}
550
95ea3627 551static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 552 struct rt2x00lib_conf *libconf,
553 const unsigned int flags)
95ea3627 554{
e4ea1c40 555 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 556 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 557 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 558 rt2400pci_config_txpower(rt2x00dev,
559 libconf->conf->power_level);
e4ea1c40
ID		 560 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
561 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 562 if (flags & IEEE80211_CONF_CHANGE_PS)
563 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 564}
565
566static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 567 const int cw_min, const int cw_max)
95ea3627
ID		 568{
569 u32 reg;
570
571 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 572 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
573 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 574 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
575}
576
95ea3627
ID		 577/*
578 * Link tuning
579 */
ebcf26da
ID		 580static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
581 struct link_qual *qual)
95ea3627
ID		 582{
583 u32 reg;
584 u8 bbp;
585
586 /*
587 * Update FCS error count from register.
588 */
589 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 590 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 591
592 /*
593 * Update False CCA count from register.
594 */
595 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 596 qual->false_cca = bbp;
95ea3627
ID		 597}
598
5352ff65
ID		 599static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
600 struct link_qual *qual, u8 vgc_level)
eb20b4e8 601{
223dcc26
ID		 602 if (qual->vgc_level_reg != vgc_level) {
603 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
604 qual->vgc_level = vgc_level;
605 qual->vgc_level_reg = vgc_level;
606 }
eb20b4e8
ID		 607}
608
5352ff65
ID		 609static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
610 struct link_qual *qual)
95ea3627 611{
5352ff65 612 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 613}
614
5352ff65
ID		 615static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
616 struct link_qual *qual, const u32 count)
95ea3627 617{
95ea3627
ID		 618 /*
619 * The link tuner should not run longer then 60 seconds,
620 * and should run once every 2 seconds.
621 */
5352ff65 622 if (count > 60 || !(count & 1))
95ea3627
ID		 623 return;
624
625 /*
626 * Base r13 link tuning on the false cca count.
627 */
5352ff65
ID		 628 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
629 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
630 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
631 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 632}
633
5450b7e2
ID		 634/*
635 * Queue handlers.
636 */
637static void rt2400pci_start_queue(struct data_queue *queue)
638{
639 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
640 u32 reg;
641
642 switch (queue->qid) {
643 case QID_RX:
644 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
645 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
646 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
647 break;
648 case QID_BEACON:
649 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
650 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
651 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
652 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
653 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
654 break;
655 default:
656 break;
657 }
658}
659
660static void rt2400pci_kick_queue(struct data_queue *queue)
661{
662 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
663 u32 reg;
664
665 switch (queue->qid) {
f615e9a3 666 case QID_AC_VO:
5450b7e2
ID		 667 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
668 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
669 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
670 break;
f615e9a3 671 case QID_AC_VI:
5450b7e2
ID		 672 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
673 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
674 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
675 break;
676 case QID_ATIM:
677 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
678 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
679 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
680 break;
681 default:
682 break;
683 }
684}
685
686static void rt2400pci_stop_queue(struct data_queue *queue)
687{
688 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
689 u32 reg;
690
691 switch (queue->qid) {
f615e9a3
ID		 692 case QID_AC_VO:
693 case QID_AC_VI:
5450b7e2
ID		 694 case QID_ATIM:
695 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
696 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
697 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
698 break;
699 case QID_RX:
700 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
701 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
702 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
703 break;
704 case QID_BEACON:
705 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
706 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
707 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
708 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
709 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bcf3cfd0
HS		 710
711 /*
712 * Wait for possibly running tbtt tasklets.
713 */
abc11994 714 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 715 break;
716 default:
717 break;
718 }
719}
720
95ea3627
ID		 721/*
722 * Initialization functions.
723 */
798b7adb 724static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 725{
b8be63ff 726 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 727 u32 word;
728
798b7adb
ID		 729 if (entry->queue->qid == QID_RX) {
730 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 731
798b7adb
ID		 732 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
733 } else {
734 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 735
798b7adb
ID		 736 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
737 rt2x00_get_field32(word, TXD_W0_VALID));
738 }
95ea3627
ID		 739}
740
798b7adb 741static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 742{
b8be63ff 743 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 744 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 745 u32 word;
746
798b7adb
ID		 747 if (entry->queue->qid == QID_RX) {
748 rt2x00_desc_read(entry_priv->desc, 2, &word);
749 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
750 rt2x00_desc_write(entry_priv->desc, 2, word);
751
752 rt2x00_desc_read(entry_priv->desc, 1, &word);
753 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
754 rt2x00_desc_write(entry_priv->desc, 1, word);
755
756 rt2x00_desc_read(entry_priv->desc, 0, &word);
757 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
758 rt2x00_desc_write(entry_priv->desc, 0, word);
759 } else {
760 rt2x00_desc_read(entry_priv->desc, 0, &word);
761 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
762 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
763 rt2x00_desc_write(entry_priv->desc, 0, word);
764 }
95ea3627
ID		 765}
766
181d6902 767static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 768{
b8be63ff 769 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 770 u32 reg;
771
95ea3627
ID		 772 /*
773 * Initialize registers.
774 */
775 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 776 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
777 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 778 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 779 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 780 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
781
b8be63ff 782 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 783 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 784 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 785 entry_priv->desc_dma);
95ea3627
ID		 786 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
787
b8be63ff 788 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 789 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 790 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 791 entry_priv->desc_dma);
95ea3627
ID		 792 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
793
e74df4a7 794 entry_priv = rt2x00dev->atim->entries[0].priv_data;
95ea3627 795 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 796 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 797 entry_priv->desc_dma);
95ea3627
ID		 798 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
799
e74df4a7 800 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
95ea3627 801 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 802 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 803 entry_priv->desc_dma);
95ea3627
ID		 804 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
805
806 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
807 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 808 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 809 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
810
b8be63ff 811 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 812 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 813 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
814 entry_priv->desc_dma);
95ea3627
ID		 815 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
816
817 return 0;
818}
819
820static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
821{
822 u32 reg;
823
824 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
825 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
826 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
827 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
828
829 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
830 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
831 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
832 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
833 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
834
835 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
836 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
837 (rt2x00dev->rx->data_size / 128));
838 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
839
1f909162
ID		 840 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
841 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
842 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
843 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
844 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
845 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
846 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
847 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
848 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
849 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
850
95ea3627
ID		 851 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
852
853 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
854 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
856 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
857 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
858 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
859
860 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
866 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
867 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
868
869 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
870
871 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
872 return -EBUSY;
873
874 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
875 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
876
877 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
878 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
879 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
880
881 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
882 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
884 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
885 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
886 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
887
888 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
889 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
890 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
891 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
892 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
893
894 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
895 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
896 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
897 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
898
899 /*
900 * We must clear the FCS and FIFO error count.
901 * These registers are cleared on read,
902 * so we may pass a useless variable to store the value.
903 */
904 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
905 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
906
907 return 0;
908}
909
2b08da3f 910static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 911{
912 unsigned int i;
95ea3627
ID		 913 u8 value;
914
915 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
916 rt2400pci_bbp_read(rt2x00dev, 0, &value);
917 if ((value != 0xff) && (value != 0x00))
2b08da3f 918 return 0;
95ea3627
ID		 919 udelay(REGISTER_BUSY_DELAY);
920 }
921
922 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
923 return -EACCES;
2b08da3f
ID		 924}
925
926static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
927{
928 unsigned int i;
929 u16 eeprom;
930 u8 reg_id;
931 u8 value;
932
933 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
934 return -EACCES;
95ea3627 935
95ea3627
ID		 936 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
937 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
938 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
939 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
940 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
941 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
942 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
943 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
944 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
945 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
946 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
947 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
948 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
949 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
950
95ea3627
ID		 951 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
952 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
953
954 if (eeprom != 0xffff && eeprom != 0x0000) {
955 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
956 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 957 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
958 }
959 }
95ea3627
ID		 960
961 return 0;
962}
963
964/*
965 * Device state switch handlers.
966 */
95ea3627
ID		 967static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
968 enum dev_state state)
969{
b550911a 970 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 971 u32 reg;
bcf3cfd0 972 unsigned long flags;
95ea3627
ID		 973
974 /*
975 * When interrupts are being enabled, the interrupt registers
976 * should clear the register to assure a clean state.
977 */
978 if (state == STATE_RADIO_IRQ_ON) {
979 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
980 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
981 }
982
983 /*
984 * Only toggle the interrupts bits we are going to use.
985 * Non-checked interrupt bits are disabled by default.
986 */
bcf3cfd0
HS		 987 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
988
95ea3627
ID		 989 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
990 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
991 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
992 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
993 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
994 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
995 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0
HS		 996
997 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
998
999 if (state == STATE_RADIO_IRQ_OFF) {
1000 /*
1001 * Ensure that all tasklets are finished before
1002 * disabling the interrupts.
1003 */
abc11994
HS		 1004 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1005 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1006 tasklet_kill(&rt2x00dev->tbtt_tasklet);
bcf3cfd0 1007 }
95ea3627
ID		 1008}
1009
1010static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1011{
1012 /*
1013 * Initialize all registers.
1014 */
2b08da3f
ID		 1015 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1016 rt2400pci_init_registers(rt2x00dev) ||
1017 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 1018 return -EIO;
95ea3627 1019
95ea3627
ID		 1020 return 0;
1021}
1022
1023static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1024{
95ea3627 1025 /*
a2c9b652 1026 * Disable power
95ea3627 1027 */
a2c9b652 1028 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1029}
1030
1031static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1032 enum dev_state state)
1033{
9655a6ec 1034 u32 reg, reg2;
95ea3627
ID		 1035 unsigned int i;
1036 char put_to_sleep;
1037 char bbp_state;
1038 char rf_state;
1039
1040 put_to_sleep = (state != STATE_AWAKE);
1041
1042 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1043 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1044 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1045 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1046 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1047 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1048
1049 /*
1050 * Device is not guaranteed to be in the requested state yet.
1051 * We must wait until the register indicates that the
1052 * device has entered the correct state.
1053 */
1054 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1055 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1056 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1057 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1058 if (bbp_state == state && rf_state == state)
1059 return 0;
9655a6ec 1060 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1061 msleep(10);
1062 }
1063
95ea3627
ID		 1064 return -EBUSY;
1065}
1066
1067static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1068 enum dev_state state)
1069{
1070 int retval = 0;
1071
1072 switch (state) {
1073 case STATE_RADIO_ON:
1074 retval = rt2400pci_enable_radio(rt2x00dev);
1075 break;
1076 case STATE_RADIO_OFF:
1077 rt2400pci_disable_radio(rt2x00dev);
1078 break;
2b08da3f
ID		 1079 case STATE_RADIO_IRQ_ON:
1080 case STATE_RADIO_IRQ_OFF:
1081 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1082 break;
1083 case STATE_DEEP_SLEEP:
1084 case STATE_SLEEP:
1085 case STATE_STANDBY:
1086 case STATE_AWAKE:
1087 retval = rt2400pci_set_state(rt2x00dev, state);
1088 break;
1089 default:
1090 retval = -ENOTSUPP;
1091 break;
1092 }
1093
2b08da3f
ID		 1094 if (unlikely(retval))
1095 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1096 state, retval);
1097
95ea3627
ID		 1098 return retval;
1099}
1100
1101/*
1102 * TX descriptor initialization
1103 */
93331458 1104static void rt2400pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1105 struct txentry_desc *txdesc)
95ea3627 1106{
93331458
ID		 1107 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1108 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1109 __le32 *txd = entry_priv->desc;
95ea3627 1110 u32 word;
95ea3627
ID		 1111
1112 /*
1113 * Start writing the descriptor words.
1114 */
85b7a8b3 1115 rt2x00_desc_read(txd, 1, &word);
c4da0048 1116 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1117 rt2x00_desc_write(txd, 1, word);
4de36fe5 1118
95ea3627 1119 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1120 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1121 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1122 rt2x00_desc_write(txd, 2, word);
1123
1124 rt2x00_desc_read(txd, 3, &word);
26a1d07f 1125 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
49da2605
ID		 1126 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1127 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
26a1d07f 1128 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
49da2605
ID		 1129 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1130 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1131 rt2x00_desc_write(txd, 3, word);
1132
1133 rt2x00_desc_read(txd, 4, &word);
26a1d07f
HS		 1134 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1135 txdesc->u.plcp.length_low);
49da2605
ID		 1136 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1137 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
26a1d07f
HS		 1138 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1139 txdesc->u.plcp.length_high);
49da2605
ID		 1140 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1141 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1142 rt2x00_desc_write(txd, 4, word);
1143
e01f1ec3
GW		 1144 /*
1145 * Writing TXD word 0 must the last to prevent a race condition with
1146 * the device, whereby the device may take hold of the TXD before we
1147 * finished updating it.
1148 */
95ea3627
ID		 1149 rt2x00_desc_read(txd, 0, &word);
1150 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1151 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1152 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1153 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1154 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1155 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1156 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1157 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1158 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902 1159 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
2517794b 1160 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1161 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1162 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1163 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1164
1165 /*
1166 * Register descriptor details in skb frame descriptor.
1167 */
1168 skbdesc->desc = txd;
1169 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1170}
1171
1172/*
1173 * TX data initialization
1174 */
f224f4ef
GW		 1175static void rt2400pci_write_beacon(struct queue_entry *entry,
1176 struct txentry_desc *txdesc)
bd88a781
ID		 1177{
1178 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1179 u32 reg;
1180
1181 /*
1182 * Disable beaconing while we are reloading the beacon data,
1183 * otherwise we might be sending out invalid data.
1184 */
1185 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1186 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1187 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1188
4ea545d4
SG		 1189 if (rt2x00queue_map_txskb(entry)) {
1190 ERROR(rt2x00dev, "Fail to map beacon, aborting\n");
1191 goto out;
1192 }
1193 /*
1194 * Enable beaconing again.
1195 */
1196 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
5c3b685c
GW		 1197 /*
1198 * Write the TX descriptor for the beacon.
1199 */
93331458 1200 rt2400pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1201
1202 /*
1203 * Dump beacon to userspace through debugfs.
1204 */
1205 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
4ea545d4 1206out:
d61cb266
GW		 1207 /*
1208 * Enable beaconing again.
1209 */
d61cb266
GW		 1210 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1211 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1212}
1213
95ea3627
ID		 1214/*
1215 * RX control handlers
1216 */
181d6902
ID		 1217static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1218 struct rxdone_entry_desc *rxdesc)
95ea3627 1219{
ae73e58e 1220 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1221 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1222 u32 word0;
1223 u32 word2;
89993890 1224 u32 word3;
ae73e58e
ID		 1225 u32 word4;
1226 u64 tsf;
1227 u32 rx_low;
1228 u32 rx_high;
95ea3627 1229
b8be63ff
ID		 1230 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1231 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1232 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1233 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1234
4150c572 1235 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1236 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1237 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1238 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1239
ae73e58e
ID		 1240 /*
1241 * We only get the lower 32bits from the timestamp,
1242 * to get the full 64bits we must complement it with
1243 * the timestamp from get_tsf().
1244 * Note that when a wraparound of the lower 32bits
1245 * has occurred between the frame arrival and the get_tsf()
1246 * call, we must decrease the higher 32bits with 1 to get
1247 * to correct value.
1248 */
37a41b4a 1249 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
ae73e58e
ID		 1250 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1251 rx_high = upper_32_bits(tsf);
1252
1253 if ((u32)tsf <= rx_low)
1254 rx_high--;
1255
95ea3627
ID		 1256 /*
1257 * Obtain the status about this packet.
8ed09854
ID		 1258 * The signal is the PLCP value, and needs to be stripped
1259 * of the preamble bit (0x08).
95ea3627 1260 */
ae73e58e 1261 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1262 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1263 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1264 entry->queue->rt2x00dev->rssi_offset;
181d6902 1265 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1266
dec13b6b 1267 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1268 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1269 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1270}
1271
1272/*
1273 * Interrupt functions.
1274 */
181d6902 1275static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1276 const enum data_queue_qid queue_idx)
95ea3627 1277{
61c6e489 1278 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
b8be63ff 1279 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1280 struct queue_entry *entry;
1281 struct txdone_entry_desc txdesc;
95ea3627 1282 u32 word;
95ea3627 1283
181d6902
ID		 1284 while (!rt2x00queue_empty(queue)) {
1285 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1286 entry_priv = entry->priv_data;
1287 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1288
1289 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1290 !rt2x00_get_field32(word, TXD_W0_VALID))
1291 break;
1292
1293 /*
1294 * Obtain the status about this packet.
1295 */
fb55f4d1
ID		 1296 txdesc.flags = 0;
1297 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1298 case 0: /* Success */
1299 case 1: /* Success with retry */
1300 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1301 break;
1302 case 2: /* Failure, excessive retries */
1303 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1304 /* Don't break, this is a failed frame! */
1305 default: /* Failure */
1306 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1307 }
181d6902 1308 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1309
e513a0b6 1310 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1311 }
95ea3627
ID		 1312}
1313
7a5a681a
HS		 1314static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1315 struct rt2x00_field32 irq_field)
95ea3627 1316{
bcf3cfd0 1317 u32 reg;
95ea3627
ID		 1318
1319 /*
bcf3cfd0
HS		 1320 * Enable a single interrupt. The interrupt mask register
1321 * access needs locking.
95ea3627 1322 */
0aa13b2e 1323 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1324
bcf3cfd0
HS		 1325 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1326 rt2x00_set_field32(&reg, irq_field, 0);
1327 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
95ea3627 1328
0aa13b2e 1329 spin_unlock_irq(&rt2x00dev->irqmask_lock);
bcf3cfd0 1330}
95ea3627 1331
bcf3cfd0
HS		 1332static void rt2400pci_txstatus_tasklet(unsigned long data)
1333{
1334 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1335 u32 reg;
95ea3627
ID		 1336
1337 /*
bcf3cfd0 1338 * Handle all tx queues.
95ea3627 1339 */
bcf3cfd0
HS		 1340 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1341 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1342 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1343
1344 /*
bcf3cfd0 1345 * Enable all TXDONE interrupts again.
95ea3627 1346 */
abc11994
HS		 1347 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1348 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1349
abc11994
HS		 1350 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1351 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1352 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1353 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1354 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1355
abc11994
HS		 1356 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1357 }
bcf3cfd0
HS		 1358}
1359
1360static void rt2400pci_tbtt_tasklet(unsigned long data)
1361{
1362 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1363 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1364 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1365 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
bcf3cfd0
HS		 1366}
1367
1368static void rt2400pci_rxdone_tasklet(unsigned long data)
1369{
1370 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 1371 if (rt2x00pci_rxdone(rt2x00dev))
1372 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1373 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1374 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1375}
1376
78e256c9
HS		 1377static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1378{
1379 struct rt2x00_dev *rt2x00dev = dev_instance;
bcf3cfd0 1380 u32 reg, mask;
78e256c9
HS		 1381
1382 /*
1383 * Get the interrupt sources & saved to local variable.
1384 * Write register value back to clear pending interrupts.
1385 */
1386 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1387 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1388
1389 if (!reg)
1390 return IRQ_NONE;
1391
1392 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1393 return IRQ_HANDLED;
1394
bcf3cfd0
HS		 1395 mask = reg;
1396
1397 /*
1398 * Schedule tasklets for interrupt handling.
1399 */
1400 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1401 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1402
1403 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1404 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1405
1406 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1407 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1408 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1409 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1410 /*
1411 * Mask out all txdone interrupts.
1412 */
1413 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1414 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1415 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1416 }
78e256c9 1417
bcf3cfd0
HS		 1418 /*
1419 * Disable all interrupts for which a tasklet was scheduled right now,
1420 * the tasklet will reenable the appropriate interrupts.
1421 */
0aa13b2e 1422 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1423
bcf3cfd0
HS		 1424 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1425 reg |= mask;
1426 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1427
0aa13b2e 1428 spin_unlock(&rt2x00dev->irqmask_lock);
bcf3cfd0
HS		 1429
1430
1431
1432 return IRQ_HANDLED;
78e256c9
HS		 1433}
1434
95ea3627
ID		 1435/*
1436 * Device probe functions.
1437 */
1438static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1439{
1440 struct eeprom_93cx6 eeprom;
1441 u32 reg;
1442 u16 word;
1443 u8 *mac;
1444
1445 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1446
1447 eeprom.data = rt2x00dev;
1448 eeprom.register_read = rt2400pci_eepromregister_read;
1449 eeprom.register_write = rt2400pci_eepromregister_write;
1450 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1451 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1452 eeprom.reg_data_in = 0;
1453 eeprom.reg_data_out = 0;
1454 eeprom.reg_data_clock = 0;
1455 eeprom.reg_chip_select = 0;
1456
1457 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1458 EEPROM_SIZE / sizeof(u16));
1459
1460 /*
1461 * Start validation of the data that has been read.
1462 */
1463 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1464 if (!is_valid_ether_addr(mac)) {
f4f7f414 1465 eth_random_addr(mac);
e174961c 1466 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1467 }
1468
1469 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1470 if (word == 0xffff) {
1471 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1472 return -EINVAL;
1473 }
1474
1475 return 0;
1476}
1477
1478static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1479{
1480 u32 reg;
1481 u16 value;
1482 u16 eeprom;
1483
1484 /*
1485 * Read EEPROM word for configuration.
1486 */
1487 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1488
1489 /*
1490 * Identify RF chipset.
1491 */
1492 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1493 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1494 rt2x00_set_chip(rt2x00dev, RT2460, value,
1495 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1496
5122d898 1497 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1498 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1499 return -ENODEV;
1500 }
1501
1502 /*
1503 * Identify default antenna configuration.
1504 */
addc81bd 1505 rt2x00dev->default_ant.tx =
95ea3627 1506 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1507 rt2x00dev->default_ant.rx =
95ea3627
ID		 1508 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1509
addc81bd
ID		 1510 /*
1511 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1512 * I am not 100% sure about this, but the legacy drivers do not
1513 * indicate antenna swapping in software is required when
1514 * diversity is enabled.
1515 */
1516 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1517 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1518 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1519 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1520
95ea3627
ID		 1521 /*
1522 * Store led mode, for correct led behaviour.
1523 */
771fd565 1524#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1525 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1526
475433be 1527 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1528 if (value == LED_MODE_TXRX_ACTIVITY ||
1529 value == LED_MODE_DEFAULT ||
1530 value == LED_MODE_ASUS)
475433be
ID		 1531 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1532 LED_TYPE_ACTIVITY);
771fd565 1533#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1534
1535 /*
1536 * Detect if this device has an hardware controlled radio.
1537 */
1538 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1539 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 1540
1541 /*
1542 * Check if the BBP tuning should be enabled.
1543 */
27df2a9c 1544 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
7dab73b3 1545 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1546
1547 return 0;
1548}
1549
1550/*
1551 * RF value list for RF2420 & RF2421
1552 * Supports: 2.4 GHz
1553 */
8c5e7a5f 1554static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1555 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1556 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1557 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1558 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1559 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1560 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1561 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1562 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1563 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1564 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1565 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1566 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1567 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1568 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1569};
1570
8c5e7a5f 1571static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1572{
1573 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1574 struct channel_info *info;
1575 char *tx_power;
95ea3627
ID		 1576 unsigned int i;
1577
1578 /*
1579 * Initialize all hw fields.
1580 */
566bfe5a 1581 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1582 IEEE80211_HW_SIGNAL_DBM |
1583 IEEE80211_HW_SUPPORTS_PS |
1584 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1585
14a3bf89 1586 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1587 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1588 rt2x00_eeprom_addr(rt2x00dev,
1589 EEPROM_MAC_ADDR_0));
1590
95ea3627
ID		 1591 /*
1592 * Initialize hw_mode information.
1593 */
31562e80
ID		 1594 spec->supported_bands = SUPPORT_BAND_2GHZ;
1595 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1596
8c5e7a5f
ID		 1597 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1598 spec->channels = rf_vals_b;
1599
1600 /*
1601 * Create channel information array
1602 */
baeb2ffa 1603 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1604 if (!info)
1605 return -ENOMEM;
1606
1607 spec->channels_info = info;
1608
1609 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1610 for (i = 0; i < 14; i++) {
1611 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1612 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1613 }
8c5e7a5f
ID		 1614
1615 return 0;
95ea3627
ID		 1616}
1617
1618static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1619{
1620 int retval;
a396e100 1621 u32 reg;
95ea3627
ID		 1622
1623 /*
1624 * Allocate eeprom data.
1625 */
1626 retval = rt2400pci_validate_eeprom(rt2x00dev);
1627 if (retval)
1628 return retval;
1629
1630 retval = rt2400pci_init_eeprom(rt2x00dev);
1631 if (retval)
1632 return retval;
1633
a396e100
GW		 1634 /*
1635 * Enable rfkill polling by setting GPIO direction of the
1636 * rfkill switch GPIO pin correctly.
1637 */
1638 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 1639 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
a396e100
GW		 1640 rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);
1641
95ea3627
ID		 1642 /*
1643 * Initialize hw specifications.
1644 */
8c5e7a5f
ID		 1645 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1646 if (retval)
1647 return retval;
95ea3627
ID		 1648
1649 /*
c4da0048 1650 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1651 */
7dab73b3
ID		 1652 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1653 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1654 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1655
1656 /*
1657 * Set the rssi offset.
1658 */
1659 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1660
1661 return 0;
1662}
1663
1664/*
1665 * IEEE80211 stack callback functions.
1666 */
8a3a3c85
EP		 1667static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1668 struct ieee80211_vif *vif, u16 queue,
95ea3627
ID		 1669 const struct ieee80211_tx_queue_params *params)
1670{
1671 struct rt2x00_dev *rt2x00dev = hw->priv;
1672
1673 /*
1674 * We don't support variating cw_min and cw_max variables
1675 * per queue. So by default we only configure the TX queue,
1676 * and ignore all other configurations.
1677 */
e100bb64 1678 if (queue != 0)
95ea3627
ID		 1679 return -EINVAL;
1680
8a3a3c85 1681 if (rt2x00mac_conf_tx(hw, vif, queue, params))
95ea3627
ID		 1682 return -EINVAL;
1683
1684 /*
1685 * Write configuration to register.
1686 */
181d6902
ID		 1687 rt2400pci_config_cw(rt2x00dev,
1688 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1689
1690 return 0;
1691}
1692
37a41b4a
EP		 1693static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1694 struct ieee80211_vif *vif)
95ea3627
ID		 1695{
1696 struct rt2x00_dev *rt2x00dev = hw->priv;
1697 u64 tsf;
1698 u32 reg;
1699
1700 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1701 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1702 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1703 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1704
1705 return tsf;
1706}
1707
95ea3627
ID		 1708static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1709{
1710 struct rt2x00_dev *rt2x00dev = hw->priv;
1711 u32 reg;
1712
1713 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1714 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1715}
1716
1717static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1718 .tx = rt2x00mac_tx,
4150c572
JB		 1719 .start = rt2x00mac_start,
1720 .stop = rt2x00mac_stop,
95ea3627
ID		 1721 .add_interface = rt2x00mac_add_interface,
1722 .remove_interface = rt2x00mac_remove_interface,
1723 .config = rt2x00mac_config,
3a643d24 1724 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1725 .sw_scan_start = rt2x00mac_sw_scan_start,
1726 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1727 .get_stats = rt2x00mac_get_stats,
471b3efd 1728 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1729 .conf_tx = rt2400pci_conf_tx,
95ea3627 1730 .get_tsf = rt2400pci_get_tsf,
95ea3627 1731 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1732 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1733 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 1734 .set_antenna = rt2x00mac_set_antenna,
1735 .get_antenna = rt2x00mac_get_antenna,
e7dee444 1736 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1737 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 1738};
1739
1740static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1741 .irq_handler = rt2400pci_interrupt,
bcf3cfd0
HS		 1742 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1743 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1744 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
95ea3627
ID		 1745 .probe_hw = rt2400pci_probe_hw,
1746 .initialize = rt2x00pci_initialize,
1747 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1748 .get_entry_state = rt2400pci_get_entry_state,
1749 .clear_entry = rt2400pci_clear_entry,
95ea3627 1750 .set_device_state = rt2400pci_set_device_state,
95ea3627 1751 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1752 .link_stats = rt2400pci_link_stats,
1753 .reset_tuner = rt2400pci_reset_tuner,
1754 .link_tuner = rt2400pci_link_tuner,
dbba306f
ID		 1755 .start_queue = rt2400pci_start_queue,
1756 .kick_queue = rt2400pci_kick_queue,
1757 .stop_queue = rt2400pci_stop_queue,
152a5992 1758 .flush_queue = rt2x00pci_flush_queue,
95ea3627 1759 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1760 .write_beacon = rt2400pci_write_beacon,
95ea3627 1761 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1762 .config_filter = rt2400pci_config_filter,
6bb40dd1 1763 .config_intf = rt2400pci_config_intf,
72810379 1764 .config_erp = rt2400pci_config_erp,
e4ea1c40 1765 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1766 .config = rt2400pci_config,
1767};
1768
181d6902 1769static const struct data_queue_desc rt2400pci_queue_rx = {
efd2f271 1770 .entry_num = 24,
181d6902
ID		 1771 .data_size = DATA_FRAME_SIZE,
1772 .desc_size = RXD_DESC_SIZE,
b8be63ff 1773 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1774};
1775
1776static const struct data_queue_desc rt2400pci_queue_tx = {
efd2f271 1777 .entry_num = 24,
181d6902
ID		 1778 .data_size = DATA_FRAME_SIZE,
1779 .desc_size = TXD_DESC_SIZE,
b8be63ff 1780 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1781};
1782
1783static const struct data_queue_desc rt2400pci_queue_bcn = {
efd2f271 1784 .entry_num = 1,
181d6902
ID		 1785 .data_size = MGMT_FRAME_SIZE,
1786 .desc_size = TXD_DESC_SIZE,
b8be63ff 1787 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1788};
1789
1790static const struct data_queue_desc rt2400pci_queue_atim = {
efd2f271 1791 .entry_num = 8,
181d6902
ID		 1792 .data_size = DATA_FRAME_SIZE,
1793 .desc_size = TXD_DESC_SIZE,
b8be63ff 1794 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1795};
1796
95ea3627 1797static const struct rt2x00_ops rt2400pci_ops = {
04d0362e 1798 .name = KBUILD_MODNAME,
04d0362e
GW		 1799 .max_ap_intf = 1,
1800 .eeprom_size = EEPROM_SIZE,
1801 .rf_size = RF_SIZE,
1802 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1803 .extra_tx_headroom = 0,
04d0362e
GW		 1804 .rx = &rt2400pci_queue_rx,
1805 .tx = &rt2400pci_queue_tx,
1806 .bcn = &rt2400pci_queue_bcn,
1807 .atim = &rt2400pci_queue_atim,
1808 .lib = &rt2400pci_rt2x00_ops,
1809 .hw = &rt2400pci_mac80211_ops,
95ea3627 1810#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1811 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1812#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1813};
1814
1815/*
1816 * RT2400pci module information.
1817 */
a3aa1884 1818static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
e01ae27f 1819 { PCI_DEVICE(0x1814, 0x0101) },
95ea3627
ID		 1820 { 0, }
1821};
1822
e01ae27f 1823
95ea3627
ID		 1824MODULE_AUTHOR(DRV_PROJECT);
1825MODULE_VERSION(DRV_VERSION);
1826MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1827MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1828MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1829MODULE_LICENSE("GPL");
1830
e01ae27f
GW		 1831static int rt2400pci_probe(struct pci_dev *pci_dev,
1832 const struct pci_device_id *id)
1833{
1834 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1835}
1836
95ea3627 1837static struct pci_driver rt2400pci_driver = {
2360157c 1838 .name = KBUILD_MODNAME,
95ea3627 1839 .id_table = rt2400pci_device_table,
e01ae27f 1840 .probe = rt2400pci_probe,
69202359 1841 .remove = rt2x00pci_remove,
95ea3627
ID		 1842 .suspend = rt2x00pci_suspend,
1843 .resume = rt2x00pci_resume,
1844};
1845
5b0a3b7e 1846module_pci_driver(rt2400pci_driver);
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