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drivers/net: Convert unbounded kzalloc calls to kcalloc
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt2400pci.h"
39
40/*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
c9c3b1a5
ID		 53#define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55#define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 57
0e14f6d3 58static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 59 const unsigned int word, const u8 value)
60{
61 u32 reg;
62
8ff48a8b
ID		 63 mutex_lock(&rt2x00dev->csr_mutex);
64
95ea3627 65 /*
c9c3b1a5
ID		 66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
95ea3627 68 */
c9c3b1a5
ID		 69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
8ff48a8b 78
8ff48a8b 79 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 80}
81
0e14f6d3 82static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int word, u8 *value)
84{
85 u32 reg;
86
8ff48a8b
ID		 87 mutex_lock(&rt2x00dev->csr_mutex);
88
95ea3627 89 /*
c9c3b1a5
ID		 90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
95ea3627 96 */
c9c3b1a5
ID		 97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 102
c9c3b1a5 103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 104
c9c3b1a5
ID		 105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
95ea3627
ID		 107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 109
110 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 111}
112
0e14f6d3 113static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int word, const u32 value)
115{
116 u32 reg;
95ea3627 117
8ff48a8b
ID		 118 mutex_lock(&rt2x00dev->csr_mutex);
119
c9c3b1a5
ID		 120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 133 }
134
8ff48a8b 135 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 136}
137
138static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139{
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151}
152
153static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154{
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166}
167
168#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 169static const struct rt2x00debug rt2400pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
743b97ca
ID		 172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
95ea3627
ID		 176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
743b97ca 182 .word_base = EEPROM_BASE,
95ea3627
ID		 183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2400pci_bbp_read,
188 .write = rt2400pci_bbp_write,
743b97ca 189 .word_base = BBP_BASE,
95ea3627
ID		 190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2400pci_rf_write,
743b97ca 196 .word_base = RF_BASE,
95ea3627
ID		 197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200};
201#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
95ea3627
ID		 203static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204{
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209}
95ea3627 210
771fd565 211#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 212static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 213 enum led_brightness brightness)
214{
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
a2e1d52a 222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228}
a2e1d52a
ID		 229
230static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244}
475433be
ID		 245
246static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2400pci_brightness_set;
253 led->led_dev.blink_set = rt2400pci_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
3a643d24
ID		 261static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263{
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * since there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285}
286
6bb40dd1
ID		 287static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
95ea3627 291{
6bb40dd1
ID		 292 unsigned int bcn_preload;
293 u32 reg;
95ea3627 294
6bb40dd1 295 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 296 /*
297 * Enable beacon config
298 */
bad13639 299 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 303
6bb40dd1
ID		 304 /*
305 * Enable synchronisation.
306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 308 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 310 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 311 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312 }
95ea3627 313
6bb40dd1
ID		 314 if (flags & CONFIG_UPDATE_MAC)
315 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
316 conf->mac, sizeof(conf->mac));
95ea3627 317
6bb40dd1
ID		 318 if (flags & CONFIG_UPDATE_BSSID)
319 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
320 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 321}
322
3a643d24
ID		 323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00lib_erp *erp)
95ea3627 325{
5c58ee51 326 int preamble_mask;
95ea3627 327 u32 reg;
95ea3627 328
5c58ee51
ID		 329 /*
330 * When short preamble is enabled, we should set bit 0x08
331 */
72810379 332 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 333
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
8a566afe
ID		 337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
95ea3627 341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 344 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 345 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
346
347 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 348 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 349 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 351 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 354 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 355 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 357 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 360 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 361 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 363 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 364
365 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
366
367 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
368 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
369 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
370
8a566afe
ID		 371 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
372 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
373 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
374 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
375
e4ea1c40
ID		 376 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
377 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
378 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
379 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
380
381 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
382 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
383 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
384 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 385}
386
e4ea1c40
ID		 387static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
388 struct antenna_setup *ant)
95ea3627 389{
e4ea1c40
ID		 390 u8 r1;
391 u8 r4;
392
393 /*
394 * We should never come here because rt2x00lib is supposed
395 * to catch this and send us the correct antenna explicitely.
396 */
397 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
398 ant->tx == ANTENNA_SW_DIVERSITY);
399
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402
403 /*
404 * Configure the TX antenna.
405 */
406 switch (ant->tx) {
407 case ANTENNA_HW_DIVERSITY:
408 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
409 break;
410 case ANTENNA_A:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412 break;
413 case ANTENNA_B:
414 default:
415 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
416 break;
417 }
418
419 /*
420 * Configure the RX antenna.
421 */
422 switch (ant->rx) {
423 case ANTENNA_HW_DIVERSITY:
424 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
425 break;
426 case ANTENNA_A:
427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
428 break;
429 case ANTENNA_B:
430 default:
431 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
432 break;
433 }
434
435 rt2400pci_bbp_write(rt2x00dev, 4, r4);
436 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 437}
438
439static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 440 struct rf_channel *rf)
95ea3627 441{
95ea3627
ID		 442 /*
443 * Switch on tuning bits.
444 */
5c58ee51
ID		 445 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
446 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 447
5c58ee51
ID		 448 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
449 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
450 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 451
452 /*
453 * RF2420 chipset don't need any additional actions.
454 */
5122d898 455 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 456 return;
457
458 /*
459 * For the RT2421 chipsets we need to write an invalid
460 * reference clock rate to activate auto_tune.
461 * After that we set the value back to the correct channel.
462 */
5c58ee51 463 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 464 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 465 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 466
467 msleep(1);
468
5c58ee51
ID		 469 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
470 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
471 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 472
473 msleep(1);
474
475 /*
476 * Switch off tuning bits.
477 */
5c58ee51
ID		 478 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
479 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 480
5c58ee51
ID		 481 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 483
484 /*
485 * Clear false CRC during channel switch.
486 */
5c58ee51 487 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 488}
489
490static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
491{
492 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
493}
494
e4ea1c40
ID		 495static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
496 struct rt2x00lib_conf *libconf)
95ea3627 497{
e4ea1c40 498 u32 reg;
95ea3627 499
e4ea1c40
ID		 500 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
501 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
502 libconf->conf->long_frame_max_tx_count);
503 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
504 libconf->conf->short_frame_max_tx_count);
505 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 506}
507
7d7f19cc
ID		 508static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
509 struct rt2x00lib_conf *libconf)
510{
511 enum dev_state state =
512 (libconf->conf->flags & IEEE80211_CONF_PS) ?
513 STATE_SLEEP : STATE_AWAKE;
514 u32 reg;
515
516 if (state == STATE_SLEEP) {
517 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
518 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 519 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 520 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
521 libconf->conf->listen_interval - 1);
522
523 /* We must first disable autowake before it can be enabled */
524 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
525 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
526
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 529 } else {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 533 }
534
535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
536}
537
95ea3627 538static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 539 struct rt2x00lib_conf *libconf,
540 const unsigned int flags)
95ea3627 541{
e4ea1c40 542 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 544 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 545 rt2400pci_config_txpower(rt2x00dev,
546 libconf->conf->power_level);
e4ea1c40
ID		 547 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
548 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 549 if (flags & IEEE80211_CONF_CHANGE_PS)
550 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 551}
552
553static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 554 const int cw_min, const int cw_max)
95ea3627
ID		 555{
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 559 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562}
563
95ea3627
ID		 564/*
565 * Link tuning
566 */
ebcf26da
ID		 567static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568 struct link_qual *qual)
95ea3627
ID		 569{
570 u32 reg;
571 u8 bbp;
572
573 /*
574 * Update FCS error count from register.
575 */
576 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 577 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 578
579 /*
580 * Update False CCA count from register.
581 */
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 583 qual->false_cca = bbp;
95ea3627
ID		 584}
585
5352ff65
ID		 586static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
587 struct link_qual *qual, u8 vgc_level)
eb20b4e8 588{
223dcc26
ID		 589 if (qual->vgc_level_reg != vgc_level) {
590 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
591 qual->vgc_level = vgc_level;
592 qual->vgc_level_reg = vgc_level;
593 }
eb20b4e8
ID		 594}
595
5352ff65
ID		 596static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
597 struct link_qual *qual)
95ea3627 598{
5352ff65 599 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 600}
601
5352ff65
ID		 602static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
603 struct link_qual *qual, const u32 count)
95ea3627 604{
95ea3627
ID		 605 /*
606 * The link tuner should not run longer then 60 seconds,
607 * and should run once every 2 seconds.
608 */
5352ff65 609 if (count > 60 || !(count & 1))
95ea3627
ID		 610 return;
611
612 /*
613 * Base r13 link tuning on the false cca count.
614 */
5352ff65
ID		 615 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
616 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
617 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
618 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 619}
620
621/*
622 * Initialization functions.
623 */
798b7adb 624static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 625{
b8be63ff 626 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 627 u32 word;
628
798b7adb
ID		 629 if (entry->queue->qid == QID_RX) {
630 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 631
798b7adb
ID		 632 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
633 } else {
634 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 635
798b7adb
ID		 636 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
637 rt2x00_get_field32(word, TXD_W0_VALID));
638 }
95ea3627
ID		 639}
640
798b7adb 641static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 642{
b8be63ff 643 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 644 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 645 u32 word;
646
798b7adb
ID		 647 if (entry->queue->qid == QID_RX) {
648 rt2x00_desc_read(entry_priv->desc, 2, &word);
649 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
650 rt2x00_desc_write(entry_priv->desc, 2, word);
651
652 rt2x00_desc_read(entry_priv->desc, 1, &word);
653 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
654 rt2x00_desc_write(entry_priv->desc, 1, word);
655
656 rt2x00_desc_read(entry_priv->desc, 0, &word);
657 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
658 rt2x00_desc_write(entry_priv->desc, 0, word);
659 } else {
660 rt2x00_desc_read(entry_priv->desc, 0, &word);
661 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
662 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
663 rt2x00_desc_write(entry_priv->desc, 0, word);
664 }
95ea3627
ID		 665}
666
181d6902 667static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 668{
b8be63ff 669 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 670 u32 reg;
671
95ea3627
ID		 672 /*
673 * Initialize registers.
674 */
675 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 676 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
677 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
678 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
679 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 680 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
681
b8be63ff 682 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 683 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 684 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 685 entry_priv->desc_dma);
95ea3627
ID		 686 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
687
b8be63ff 688 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 689 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 690 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 691 entry_priv->desc_dma);
95ea3627
ID		 692 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
693
b8be63ff 694 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 695 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 696 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 697 entry_priv->desc_dma);
95ea3627
ID		 698 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
699
b8be63ff 700 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 701 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 702 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 703 entry_priv->desc_dma);
95ea3627
ID		 704 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
705
706 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
707 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 708 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 709 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
710
b8be63ff 711 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 712 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 713 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
714 entry_priv->desc_dma);
95ea3627
ID		 715 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
716
717 return 0;
718}
719
720static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
721{
722 u32 reg;
723
724 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
725 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
726 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
727 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
728
729 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
730 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
731 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
732 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
733 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
734
735 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
736 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
737 (rt2x00dev->rx->data_size / 128));
738 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
739
1f909162
ID		 740 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
741 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
742 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
743 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
744 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
745 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
746 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
747 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
748 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
749 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
750
95ea3627
ID		 751 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
752
753 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
754 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
755 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
756 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
757 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
758 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
759
760 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
761 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
762 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
763 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
764 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
765 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
766 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
767 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
768
769 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
770
771 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
772 return -EBUSY;
773
774 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
775 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
776
777 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
778 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
779 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
780
781 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
782 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
783 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
784 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
785 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
786 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
787
788 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
789 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
790 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
791 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
792 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
793
794 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
795 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
796 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
797 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
798
799 /*
800 * We must clear the FCS and FIFO error count.
801 * These registers are cleared on read,
802 * so we may pass a useless variable to store the value.
803 */
804 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
805 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
806
807 return 0;
808}
809
2b08da3f 810static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 811{
812 unsigned int i;
95ea3627
ID		 813 u8 value;
814
815 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
816 rt2400pci_bbp_read(rt2x00dev, 0, &value);
817 if ((value != 0xff) && (value != 0x00))
2b08da3f 818 return 0;
95ea3627
ID		 819 udelay(REGISTER_BUSY_DELAY);
820 }
821
822 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
823 return -EACCES;
2b08da3f
ID		 824}
825
826static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
827{
828 unsigned int i;
829 u16 eeprom;
830 u8 reg_id;
831 u8 value;
832
833 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
834 return -EACCES;
95ea3627 835
95ea3627
ID		 836 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
837 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
838 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
839 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
840 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
841 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
842 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
843 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
844 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
845 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
846 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
847 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
848 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
849 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
850
95ea3627
ID		 851 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
852 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
853
854 if (eeprom != 0xffff && eeprom != 0x0000) {
855 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
856 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 857 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
858 }
859 }
95ea3627
ID		 860
861 return 0;
862}
863
864/*
865 * Device state switch handlers.
866 */
867static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
868 enum dev_state state)
869{
870 u32 reg;
871
872 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
873 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 874 (state == STATE_RADIO_RX_OFF) ||
875 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 876 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
877}
878
879static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
880 enum dev_state state)
881{
78e256c9
HS		 882 int mask = (state == STATE_RADIO_IRQ_OFF) ||
883 (state == STATE_RADIO_IRQ_OFF_ISR);
95ea3627
ID		 884 u32 reg;
885
886 /*
887 * When interrupts are being enabled, the interrupt registers
888 * should clear the register to assure a clean state.
889 */
890 if (state == STATE_RADIO_IRQ_ON) {
891 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
892 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
893 }
894
895 /*
896 * Only toggle the interrupts bits we are going to use.
897 * Non-checked interrupt bits are disabled by default.
898 */
899 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
900 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
901 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
902 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
903 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
904 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
905 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
906}
907
908static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
909{
910 /*
911 * Initialize all registers.
912 */
2b08da3f
ID		 913 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
914 rt2400pci_init_registers(rt2x00dev) ||
915 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 916 return -EIO;
95ea3627 917
95ea3627
ID		 918 return 0;
919}
920
921static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
922{
95ea3627 923 /*
a2c9b652 924 * Disable power
95ea3627 925 */
a2c9b652 926 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 927}
928
929static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
930 enum dev_state state)
931{
9655a6ec 932 u32 reg, reg2;
95ea3627
ID		 933 unsigned int i;
934 char put_to_sleep;
935 char bbp_state;
936 char rf_state;
937
938 put_to_sleep = (state != STATE_AWAKE);
939
940 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
941 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
942 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
943 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
944 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
945 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
946
947 /*
948 * Device is not guaranteed to be in the requested state yet.
949 * We must wait until the register indicates that the
950 * device has entered the correct state.
951 */
952 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 953 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
954 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
955 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 956 if (bbp_state == state && rf_state == state)
957 return 0;
9655a6ec 958 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 959 msleep(10);
960 }
961
95ea3627
ID		 962 return -EBUSY;
963}
964
965static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
966 enum dev_state state)
967{
968 int retval = 0;
969
970 switch (state) {
971 case STATE_RADIO_ON:
972 retval = rt2400pci_enable_radio(rt2x00dev);
973 break;
974 case STATE_RADIO_OFF:
975 rt2400pci_disable_radio(rt2x00dev);
976 break;
977 case STATE_RADIO_RX_ON:
61667d8d 978 case STATE_RADIO_RX_ON_LINK:
95ea3627 979 case STATE_RADIO_RX_OFF:
61667d8d 980 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 981 rt2400pci_toggle_rx(rt2x00dev, state);
982 break;
983 case STATE_RADIO_IRQ_ON:
78e256c9 984 case STATE_RADIO_IRQ_ON_ISR:
2b08da3f 985 case STATE_RADIO_IRQ_OFF:
78e256c9 986 case STATE_RADIO_IRQ_OFF_ISR:
2b08da3f 987 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 988 break;
989 case STATE_DEEP_SLEEP:
990 case STATE_SLEEP:
991 case STATE_STANDBY:
992 case STATE_AWAKE:
993 retval = rt2400pci_set_state(rt2x00dev, state);
994 break;
995 default:
996 retval = -ENOTSUPP;
997 break;
998 }
999
2b08da3f
ID		 1000 if (unlikely(retval))
1001 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1002 state, retval);
1003
95ea3627
ID		 1004 return retval;
1005}
1006
1007/*
1008 * TX descriptor initialization
1009 */
1010static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1011 struct sk_buff *skb,
61486e0f 1012 struct txentry_desc *txdesc)
95ea3627 1013{
181d6902 1014 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1015 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
85b7a8b3 1016 __le32 *txd = entry_priv->desc;
95ea3627 1017 u32 word;
95ea3627
ID		 1018
1019 /*
1020 * Start writing the descriptor words.
1021 */
85b7a8b3 1022 rt2x00_desc_read(txd, 1, &word);
c4da0048 1023 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1024 rt2x00_desc_write(txd, 1, word);
4de36fe5 1025
95ea3627 1026 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1027 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1028 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1029 rt2x00_desc_write(txd, 2, word);
1030
1031 rt2x00_desc_read(txd, 3, &word);
181d6902 1032 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1033 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1034 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1035 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1036 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1037 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1038 rt2x00_desc_write(txd, 3, word);
1039
1040 rt2x00_desc_read(txd, 4, &word);
181d6902 1041 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1042 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1043 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1044 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1045 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1046 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1047 rt2x00_desc_write(txd, 4, word);
1048
e01f1ec3
GW		 1049 /*
1050 * Writing TXD word 0 must the last to prevent a race condition with
1051 * the device, whereby the device may take hold of the TXD before we
1052 * finished updating it.
1053 */
95ea3627
ID		 1054 rt2x00_desc_read(txd, 0, &word);
1055 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1056 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1057 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1058 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1059 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1060 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1061 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1062 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1063 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1064 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1065 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1066 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1067 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1068 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1069
1070 /*
1071 * Register descriptor details in skb frame descriptor.
1072 */
1073 skbdesc->desc = txd;
1074 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1075}
1076
1077/*
1078 * TX data initialization
1079 */
f224f4ef
GW		 1080static void rt2400pci_write_beacon(struct queue_entry *entry,
1081 struct txentry_desc *txdesc)
bd88a781
ID		 1082{
1083 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1084 u32 reg;
1085
1086 /*
1087 * Disable beaconing while we are reloading the beacon data,
1088 * otherwise we might be sending out invalid data.
1089 */
1090 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1091 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1092 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1093
bd88a781
ID		 1094 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1095
5c3b685c
GW		 1096 /*
1097 * Write the TX descriptor for the beacon.
1098 */
1099 rt2400pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1100
1101 /*
1102 * Dump beacon to userspace through debugfs.
1103 */
1104 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
d61cb266
GW		 1105
1106 /*
1107 * Enable beaconing again.
1108 */
1109 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1110 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1111 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1112 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1113}
1114
95ea3627 1115static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1116 const enum data_queue_qid queue)
95ea3627
ID		 1117{
1118 u32 reg;
1119
95ea3627 1120 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1121 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1122 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1123 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1124 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1125}
1126
a2c9b652
ID		 1127static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1128 const enum data_queue_qid qid)
1129{
1130 u32 reg;
1131
1132 if (qid == QID_BEACON) {
1133 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1134 } else {
1135 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1136 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1137 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1138 }
1139}
1140
95ea3627
ID		 1141/*
1142 * RX control handlers
1143 */
181d6902
ID		 1144static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1145 struct rxdone_entry_desc *rxdesc)
95ea3627 1146{
ae73e58e 1147 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1148 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1149 u32 word0;
1150 u32 word2;
89993890 1151 u32 word3;
ae73e58e
ID		 1152 u32 word4;
1153 u64 tsf;
1154 u32 rx_low;
1155 u32 rx_high;
95ea3627 1156
b8be63ff
ID		 1157 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1158 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1159 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1160 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1161
4150c572 1162 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1163 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1164 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1165 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1166
ae73e58e
ID		 1167 /*
1168 * We only get the lower 32bits from the timestamp,
1169 * to get the full 64bits we must complement it with
1170 * the timestamp from get_tsf().
1171 * Note that when a wraparound of the lower 32bits
1172 * has occurred between the frame arrival and the get_tsf()
1173 * call, we must decrease the higher 32bits with 1 to get
1174 * to correct value.
1175 */
1176 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1177 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1178 rx_high = upper_32_bits(tsf);
1179
1180 if ((u32)tsf <= rx_low)
1181 rx_high--;
1182
95ea3627
ID		 1183 /*
1184 * Obtain the status about this packet.
8ed09854
ID		 1185 * The signal is the PLCP value, and needs to be stripped
1186 * of the preamble bit (0x08).
95ea3627 1187 */
ae73e58e 1188 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1189 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1190 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1191 entry->queue->rt2x00dev->rssi_offset;
181d6902 1192 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1193
dec13b6b 1194 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1195 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1196 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1197}
1198
1199/*
1200 * Interrupt functions.
1201 */
181d6902 1202static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1203 const enum data_queue_qid queue_idx)
95ea3627 1204{
181d6902 1205 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1206 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1207 struct queue_entry *entry;
1208 struct txdone_entry_desc txdesc;
95ea3627 1209 u32 word;
95ea3627 1210
181d6902
ID		 1211 while (!rt2x00queue_empty(queue)) {
1212 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1213 entry_priv = entry->priv_data;
1214 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1215
1216 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1217 !rt2x00_get_field32(word, TXD_W0_VALID))
1218 break;
1219
1220 /*
1221 * Obtain the status about this packet.
1222 */
fb55f4d1
ID		 1223 txdesc.flags = 0;
1224 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1225 case 0: /* Success */
1226 case 1: /* Success with retry */
1227 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1228 break;
1229 case 2: /* Failure, excessive retries */
1230 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1231 /* Don't break, this is a failed frame! */
1232 default: /* Failure */
1233 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1234 }
181d6902 1235 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1236
e513a0b6 1237 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1238 }
95ea3627
ID		 1239}
1240
78e256c9 1241static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
95ea3627
ID		 1242{
1243 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 1244 u32 reg = rt2x00dev->irqvalue[0];
95ea3627
ID		 1245
1246 /*
1247 * Handle interrupts, walk through all bits
1248 * and run the tasks, the bits are checked in order of
1249 * priority.
1250 */
1251
1252 /*
1253 * 1 - Beacon timer expired interrupt.
1254 */
1255 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1256 rt2x00lib_beacondone(rt2x00dev);
1257
1258 /*
1259 * 2 - Rx ring done interrupt.
1260 */
1261 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1262 rt2x00pci_rxdone(rt2x00dev);
1263
1264 /*
1265 * 3 - Atim ring transmit done interrupt.
1266 */
1267 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1268 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1269
1270 /*
1271 * 4 - Priority ring transmit done interrupt.
1272 */
1273 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1274 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1275
1276 /*
1277 * 5 - Tx ring transmit done interrupt.
1278 */
1279 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1280 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627 1281
78e256c9
HS		 1282 /* Enable interrupts again. */
1283 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1284 STATE_RADIO_IRQ_ON_ISR);
95ea3627
ID		 1285 return IRQ_HANDLED;
1286}
1287
78e256c9
HS		 1288static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1289{
1290 struct rt2x00_dev *rt2x00dev = dev_instance;
1291 u32 reg;
1292
1293 /*
1294 * Get the interrupt sources & saved to local variable.
1295 * Write register value back to clear pending interrupts.
1296 */
1297 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1298 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1299
1300 if (!reg)
1301 return IRQ_NONE;
1302
1303 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1304 return IRQ_HANDLED;
1305
1306 /* Store irqvalues for use in the interrupt thread. */
1307 rt2x00dev->irqvalue[0] = reg;
1308
1309 /* Disable interrupts, will be enabled again in the interrupt thread. */
1310 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1311 STATE_RADIO_IRQ_OFF_ISR);
1312
1313 return IRQ_WAKE_THREAD;
1314}
1315
95ea3627
ID		 1316/*
1317 * Device probe functions.
1318 */
1319static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1320{
1321 struct eeprom_93cx6 eeprom;
1322 u32 reg;
1323 u16 word;
1324 u8 *mac;
1325
1326 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1327
1328 eeprom.data = rt2x00dev;
1329 eeprom.register_read = rt2400pci_eepromregister_read;
1330 eeprom.register_write = rt2400pci_eepromregister_write;
1331 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1332 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1333 eeprom.reg_data_in = 0;
1334 eeprom.reg_data_out = 0;
1335 eeprom.reg_data_clock = 0;
1336 eeprom.reg_chip_select = 0;
1337
1338 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1339 EEPROM_SIZE / sizeof(u16));
1340
1341 /*
1342 * Start validation of the data that has been read.
1343 */
1344 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1345 if (!is_valid_ether_addr(mac)) {
1346 random_ether_addr(mac);
e174961c 1347 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1348 }
1349
1350 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1351 if (word == 0xffff) {
1352 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1353 return -EINVAL;
1354 }
1355
1356 return 0;
1357}
1358
1359static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1360{
1361 u32 reg;
1362 u16 value;
1363 u16 eeprom;
1364
1365 /*
1366 * Read EEPROM word for configuration.
1367 */
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1369
1370 /*
1371 * Identify RF chipset.
1372 */
1373 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1374 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1375 rt2x00_set_chip(rt2x00dev, RT2460, value,
1376 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1377
5122d898 1378 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1379 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1380 return -ENODEV;
1381 }
1382
1383 /*
1384 * Identify default antenna configuration.
1385 */
addc81bd 1386 rt2x00dev->default_ant.tx =
95ea3627 1387 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1388 rt2x00dev->default_ant.rx =
95ea3627
ID		 1389 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1390
addc81bd
ID		 1391 /*
1392 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1393 * I am not 100% sure about this, but the legacy drivers do not
1394 * indicate antenna swapping in software is required when
1395 * diversity is enabled.
1396 */
1397 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1398 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1399 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1400 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1401
95ea3627
ID		 1402 /*
1403 * Store led mode, for correct led behaviour.
1404 */
771fd565 1405#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1406 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1407
475433be 1408 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1409 if (value == LED_MODE_TXRX_ACTIVITY ||
1410 value == LED_MODE_DEFAULT ||
1411 value == LED_MODE_ASUS)
475433be
ID		 1412 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1413 LED_TYPE_ACTIVITY);
771fd565 1414#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1415
1416 /*
1417 * Detect if this device has an hardware controlled radio.
1418 */
1419 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1420 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1421
1422 /*
1423 * Check if the BBP tuning should be enabled.
1424 */
27df2a9c
ID		 1425 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1426 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 1427
1428 return 0;
1429}
1430
1431/*
1432 * RF value list for RF2420 & RF2421
1433 * Supports: 2.4 GHz
1434 */
8c5e7a5f 1435static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1436 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1437 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1438 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1439 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1440 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1441 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1442 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1443 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1444 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1445 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1446 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1447 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1448 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1449 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1450};
1451
8c5e7a5f 1452static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1453{
1454 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1455 struct channel_info *info;
1456 char *tx_power;
95ea3627
ID		 1457 unsigned int i;
1458
1459 /*
1460 * Initialize all hw fields.
1461 */
566bfe5a 1462 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1463 IEEE80211_HW_SIGNAL_DBM |
1464 IEEE80211_HW_SUPPORTS_PS |
1465 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1466
14a3bf89 1467 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1468 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1469 rt2x00_eeprom_addr(rt2x00dev,
1470 EEPROM_MAC_ADDR_0));
1471
95ea3627
ID		 1472 /*
1473 * Initialize hw_mode information.
1474 */
31562e80
ID		 1475 spec->supported_bands = SUPPORT_BAND_2GHZ;
1476 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1477
8c5e7a5f
ID		 1478 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1479 spec->channels = rf_vals_b;
1480
1481 /*
1482 * Create channel information array
1483 */
baeb2ffa 1484 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1485 if (!info)
1486 return -ENOMEM;
1487
1488 spec->channels_info = info;
1489
1490 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1491 for (i = 0; i < 14; i++)
1492 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1493
1494 return 0;
95ea3627
ID		 1495}
1496
1497static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1498{
1499 int retval;
1500
1501 /*
1502 * Allocate eeprom data.
1503 */
1504 retval = rt2400pci_validate_eeprom(rt2x00dev);
1505 if (retval)
1506 return retval;
1507
1508 retval = rt2400pci_init_eeprom(rt2x00dev);
1509 if (retval)
1510 return retval;
1511
1512 /*
1513 * Initialize hw specifications.
1514 */
8c5e7a5f
ID		 1515 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1516 if (retval)
1517 return retval;
95ea3627
ID		 1518
1519 /*
c4da0048 1520 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1521 */
181d6902 1522 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1523 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1524
1525 /*
1526 * Set the rssi offset.
1527 */
1528 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1529
1530 return 0;
1531}
1532
1533/*
1534 * IEEE80211 stack callback functions.
1535 */
e100bb64 1536static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1537 const struct ieee80211_tx_queue_params *params)
1538{
1539 struct rt2x00_dev *rt2x00dev = hw->priv;
1540
1541 /*
1542 * We don't support variating cw_min and cw_max variables
1543 * per queue. So by default we only configure the TX queue,
1544 * and ignore all other configurations.
1545 */
e100bb64 1546 if (queue != 0)
95ea3627
ID		 1547 return -EINVAL;
1548
1549 if (rt2x00mac_conf_tx(hw, queue, params))
1550 return -EINVAL;
1551
1552 /*
1553 * Write configuration to register.
1554 */
181d6902
ID		 1555 rt2400pci_config_cw(rt2x00dev,
1556 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1557
1558 return 0;
1559}
1560
1561static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1562{
1563 struct rt2x00_dev *rt2x00dev = hw->priv;
1564 u64 tsf;
1565 u32 reg;
1566
1567 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1568 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1569 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1570 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1571
1572 return tsf;
1573}
1574
95ea3627
ID		 1575static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1576{
1577 struct rt2x00_dev *rt2x00dev = hw->priv;
1578 u32 reg;
1579
1580 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1581 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1582}
1583
1584static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1585 .tx = rt2x00mac_tx,
4150c572
JB		 1586 .start = rt2x00mac_start,
1587 .stop = rt2x00mac_stop,
95ea3627
ID		 1588 .add_interface = rt2x00mac_add_interface,
1589 .remove_interface = rt2x00mac_remove_interface,
1590 .config = rt2x00mac_config,
3a643d24 1591 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1592 .sw_scan_start = rt2x00mac_sw_scan_start,
1593 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1594 .get_stats = rt2x00mac_get_stats,
471b3efd 1595 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1596 .conf_tx = rt2400pci_conf_tx,
95ea3627 1597 .get_tsf = rt2400pci_get_tsf,
95ea3627 1598 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1599 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1600};
1601
1602static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1603 .irq_handler = rt2400pci_interrupt,
78e256c9 1604 .irq_handler_thread = rt2400pci_interrupt_thread,
95ea3627
ID		 1605 .probe_hw = rt2400pci_probe_hw,
1606 .initialize = rt2x00pci_initialize,
1607 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1608 .get_entry_state = rt2400pci_get_entry_state,
1609 .clear_entry = rt2400pci_clear_entry,
95ea3627 1610 .set_device_state = rt2400pci_set_device_state,
95ea3627 1611 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1612 .link_stats = rt2400pci_link_stats,
1613 .reset_tuner = rt2400pci_reset_tuner,
1614 .link_tuner = rt2400pci_link_tuner,
1615 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1616 .write_beacon = rt2400pci_write_beacon,
95ea3627 1617 .kick_tx_queue = rt2400pci_kick_tx_queue,
a2c9b652 1618 .kill_tx_queue = rt2400pci_kill_tx_queue,
95ea3627 1619 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1620 .config_filter = rt2400pci_config_filter,
6bb40dd1 1621 .config_intf = rt2400pci_config_intf,
72810379 1622 .config_erp = rt2400pci_config_erp,
e4ea1c40 1623 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1624 .config = rt2400pci_config,
1625};
1626
181d6902
ID		 1627static const struct data_queue_desc rt2400pci_queue_rx = {
1628 .entry_num = RX_ENTRIES,
1629 .data_size = DATA_FRAME_SIZE,
1630 .desc_size = RXD_DESC_SIZE,
b8be63ff 1631 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1632};
1633
1634static const struct data_queue_desc rt2400pci_queue_tx = {
1635 .entry_num = TX_ENTRIES,
1636 .data_size = DATA_FRAME_SIZE,
1637 .desc_size = TXD_DESC_SIZE,
b8be63ff 1638 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1639};
1640
1641static const struct data_queue_desc rt2400pci_queue_bcn = {
1642 .entry_num = BEACON_ENTRIES,
1643 .data_size = MGMT_FRAME_SIZE,
1644 .desc_size = TXD_DESC_SIZE,
b8be63ff 1645 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1646};
1647
1648static const struct data_queue_desc rt2400pci_queue_atim = {
1649 .entry_num = ATIM_ENTRIES,
1650 .data_size = DATA_FRAME_SIZE,
1651 .desc_size = TXD_DESC_SIZE,
b8be63ff 1652 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1653};
1654
95ea3627 1655static const struct rt2x00_ops rt2400pci_ops = {
04d0362e
GW		 1656 .name = KBUILD_MODNAME,
1657 .max_sta_intf = 1,
1658 .max_ap_intf = 1,
1659 .eeprom_size = EEPROM_SIZE,
1660 .rf_size = RF_SIZE,
1661 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1662 .extra_tx_headroom = 0,
04d0362e
GW		 1663 .rx = &rt2400pci_queue_rx,
1664 .tx = &rt2400pci_queue_tx,
1665 .bcn = &rt2400pci_queue_bcn,
1666 .atim = &rt2400pci_queue_atim,
1667 .lib = &rt2400pci_rt2x00_ops,
1668 .hw = &rt2400pci_mac80211_ops,
95ea3627 1669#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1670 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1671#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1672};
1673
1674/*
1675 * RT2400pci module information.
1676 */
a3aa1884 1677static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
95ea3627
ID		 1678 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1679 { 0, }
1680};
1681
1682MODULE_AUTHOR(DRV_PROJECT);
1683MODULE_VERSION(DRV_VERSION);
1684MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1685MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1686MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1687MODULE_LICENSE("GPL");
1688
1689static struct pci_driver rt2400pci_driver = {
2360157c 1690 .name = KBUILD_MODNAME,
95ea3627
ID		 1691 .id_table = rt2400pci_device_table,
1692 .probe = rt2x00pci_probe,
1693 .remove = __devexit_p(rt2x00pci_remove),
1694 .suspend = rt2x00pci_suspend,
1695 .resume = rt2x00pci_resume,
1696};
1697
1698static int __init rt2400pci_init(void)
1699{
1700 return pci_register_driver(&rt2400pci_driver);
1701}
1702
1703static void __exit rt2400pci_exit(void)
1704{
1705 pci_unregister_driver(&rt2400pci_driver);
1706}
1707
1708module_init(rt2400pci_init);
1709module_exit(rt2400pci_exit);
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