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rt2x00: Clean up all driver's kick_tx_queue callback functions.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
c9c3b1a5
ID		 52#define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54#define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 56
0e14f6d3 57static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 58 const unsigned int word, const u8 value)
59{
60 u32 reg;
61
8ff48a8b
ID		 62 mutex_lock(&rt2x00dev->csr_mutex);
63
95ea3627 64 /*
c9c3b1a5
ID		 65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
95ea3627 67 */
c9c3b1a5
ID		 68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
8ff48a8b 77
8ff48a8b 78 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 79}
80
0e14f6d3 81static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 82 const unsigned int word, u8 *value)
83{
84 u32 reg;
85
8ff48a8b
ID		 86 mutex_lock(&rt2x00dev->csr_mutex);
87
95ea3627 88 /*
c9c3b1a5
ID		 89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95ea3627 95 */
c9c3b1a5
ID		 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 101
c9c3b1a5 102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 103
c9c3b1a5
ID		 104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
95ea3627
ID		 106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 108
109 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 110}
111
0e14f6d3 112static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 113 const unsigned int word, const u32 value)
114{
115 u32 reg;
95ea3627 116
8ff48a8b
ID		 117 mutex_lock(&rt2x00dev->csr_mutex);
118
c9c3b1a5
ID		 119 /*
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
122 */
123 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124 reg = 0;
125 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 132 }
133
8ff48a8b 134 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 135}
136
137static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138{
139 struct rt2x00_dev *rt2x00dev = eeprom->data;
140 u32 reg;
141
142 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146 eeprom->reg_data_clock =
147 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148 eeprom->reg_chip_select =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150}
151
152static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153{
154 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 u32 reg = 0;
156
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160 !!eeprom->reg_data_clock);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162 !!eeprom->reg_chip_select);
163
164 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165}
166
167#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 168static const struct rt2x00debug rt2400pci_rt2x00debug = {
169 .owner = THIS_MODULE,
170 .csr = {
743b97ca
ID		 171 .read = rt2x00pci_register_read,
172 .write = rt2x00pci_register_write,
173 .flags = RT2X00DEBUGFS_OFFSET,
174 .word_base = CSR_REG_BASE,
95ea3627
ID		 175 .word_size = sizeof(u32),
176 .word_count = CSR_REG_SIZE / sizeof(u32),
177 },
178 .eeprom = {
179 .read = rt2x00_eeprom_read,
180 .write = rt2x00_eeprom_write,
743b97ca 181 .word_base = EEPROM_BASE,
95ea3627
ID		 182 .word_size = sizeof(u16),
183 .word_count = EEPROM_SIZE / sizeof(u16),
184 },
185 .bbp = {
186 .read = rt2400pci_bbp_read,
187 .write = rt2400pci_bbp_write,
743b97ca 188 .word_base = BBP_BASE,
95ea3627
ID		 189 .word_size = sizeof(u8),
190 .word_count = BBP_SIZE / sizeof(u8),
191 },
192 .rf = {
193 .read = rt2x00_rf_read,
194 .write = rt2400pci_rf_write,
743b97ca 195 .word_base = RF_BASE,
95ea3627
ID		 196 .word_size = sizeof(u32),
197 .word_count = RF_SIZE / sizeof(u32),
198 },
199};
200#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
95ea3627
ID		 202static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203{
204 u32 reg;
205
206 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
207 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208}
95ea3627 209
771fd565 210#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 211static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 212 enum led_brightness brightness)
213{
214 struct rt2x00_led *led =
215 container_of(led_cdev, struct rt2x00_led, led_dev);
216 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 217 u32 reg;
218
219 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
220
a2e1d52a 221 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 222 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 223 else if (led->type == LED_TYPE_ACTIVITY)
224 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 225
226 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227}
a2e1d52a
ID		 228
229static int rt2400pci_blink_set(struct led_classdev *led_cdev,
230 unsigned long *delay_on,
231 unsigned long *delay_off)
232{
233 struct rt2x00_led *led =
234 container_of(led_cdev, struct rt2x00_led, led_dev);
235 u32 reg;
236
237 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
238 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
239 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
240 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242 return 0;
243}
475433be
ID		 244
245static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
246 struct rt2x00_led *led,
247 enum led_type type)
248{
249 led->rt2x00dev = rt2x00dev;
250 led->type = type;
251 led->led_dev.brightness_set = rt2400pci_brightness_set;
252 led->led_dev.blink_set = rt2400pci_blink_set;
253 led->flags = LED_INITIALIZED;
254}
771fd565 255#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 256
95ea3627
ID		 257/*
258 * Configuration handlers.
259 */
3a643d24
ID		 260static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 const unsigned int filter_flags)
262{
263 u32 reg;
264
265 /*
266 * Start configuration steps.
267 * Note that the version error will always be dropped
268 * since there is no filter for it at this time.
269 */
270 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
271 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
272 !(filter_flags & FIF_FCSFAIL));
273 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
274 !(filter_flags & FIF_PLCPFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
276 !(filter_flags & FIF_CONTROL));
277 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
278 !(filter_flags & FIF_PROMISC_IN_BSS));
279 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 280 !(filter_flags & FIF_PROMISC_IN_BSS) &&
281 !rt2x00dev->intf_ap_count);
3a643d24
ID		 282 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
283 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
284}
285
6bb40dd1
ID		 286static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
287 struct rt2x00_intf *intf,
288 struct rt2x00intf_conf *conf,
289 const unsigned int flags)
95ea3627 290{
6bb40dd1
ID		 291 unsigned int bcn_preload;
292 u32 reg;
95ea3627 293
6bb40dd1 294 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 295 /*
296 * Enable beacon config
297 */
bad13639 298 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 299 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
300 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
301 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 302
6bb40dd1
ID		 303 /*
304 * Enable synchronisation.
305 */
306 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 307 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 309 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 310 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
311 }
95ea3627 312
6bb40dd1
ID		 313 if (flags & CONFIG_UPDATE_MAC)
314 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
315 conf->mac, sizeof(conf->mac));
95ea3627 316
6bb40dd1
ID		 317 if (flags & CONFIG_UPDATE_BSSID)
318 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
319 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 320}
321
3a643d24
ID		 322static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00lib_erp *erp)
95ea3627 324{
5c58ee51 325 int preamble_mask;
95ea3627 326 u32 reg;
95ea3627 327
5c58ee51
ID		 328 /*
329 * When short preamble is enabled, we should set bit 0x08
330 */
72810379 331 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 332
333 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 334 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
335 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
8a566afe
ID		 336 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
337 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 338 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
339
95ea3627 340 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 341 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 342 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 343 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 344 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
345
346 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 347 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 348 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 349 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 350 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
351
352 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 353 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 354 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 355 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 356 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
357
358 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 359 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 360 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 361 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 362 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 363
364 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
365
366 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
367 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
368 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
369
8a566afe
ID		 370 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
371 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
372 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
373 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
374
e4ea1c40
ID		 375 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
376 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
377 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
378 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
379
380 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
381 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
382 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
383 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 384}
385
e4ea1c40
ID		 386static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
387 struct antenna_setup *ant)
95ea3627 388{
e4ea1c40
ID		 389 u8 r1;
390 u8 r4;
391
392 /*
393 * We should never come here because rt2x00lib is supposed
394 * to catch this and send us the correct antenna explicitely.
395 */
396 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
397 ant->tx == ANTENNA_SW_DIVERSITY);
398
399 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
400 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
401
402 /*
403 * Configure the TX antenna.
404 */
405 switch (ant->tx) {
406 case ANTENNA_HW_DIVERSITY:
407 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
408 break;
409 case ANTENNA_A:
410 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
411 break;
412 case ANTENNA_B:
413 default:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
415 break;
416 }
417
418 /*
419 * Configure the RX antenna.
420 */
421 switch (ant->rx) {
422 case ANTENNA_HW_DIVERSITY:
423 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
424 break;
425 case ANTENNA_A:
426 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
427 break;
428 case ANTENNA_B:
429 default:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
431 break;
432 }
433
434 rt2400pci_bbp_write(rt2x00dev, 4, r4);
435 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 436}
437
438static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 439 struct rf_channel *rf)
95ea3627 440{
95ea3627
ID		 441 /*
442 * Switch on tuning bits.
443 */
5c58ee51
ID		 444 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
445 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 446
5c58ee51
ID		 447 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
448 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
449 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 450
451 /*
452 * RF2420 chipset don't need any additional actions.
453 */
5122d898 454 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 455 return;
456
457 /*
458 * For the RT2421 chipsets we need to write an invalid
459 * reference clock rate to activate auto_tune.
460 * After that we set the value back to the correct channel.
461 */
5c58ee51 462 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 463 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 464 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 465
466 msleep(1);
467
5c58ee51
ID		 468 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
469 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
470 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 471
472 msleep(1);
473
474 /*
475 * Switch off tuning bits.
476 */
5c58ee51
ID		 477 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
478 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 479
5c58ee51
ID		 480 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
481 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 482
483 /*
484 * Clear false CRC during channel switch.
485 */
5c58ee51 486 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 487}
488
489static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
490{
491 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
492}
493
e4ea1c40
ID		 494static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
495 struct rt2x00lib_conf *libconf)
95ea3627 496{
e4ea1c40 497 u32 reg;
95ea3627 498
e4ea1c40
ID		 499 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
500 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
501 libconf->conf->long_frame_max_tx_count);
502 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
503 libconf->conf->short_frame_max_tx_count);
504 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 505}
506
7d7f19cc
ID		 507static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
508 struct rt2x00lib_conf *libconf)
509{
510 enum dev_state state =
511 (libconf->conf->flags & IEEE80211_CONF_PS) ?
512 STATE_SLEEP : STATE_AWAKE;
513 u32 reg;
514
515 if (state == STATE_SLEEP) {
516 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
517 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 518 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 519 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
520 libconf->conf->listen_interval - 1);
521
522 /* We must first disable autowake before it can be enabled */
523 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
524 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
525
526 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
527 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 528 } else {
529 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
530 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
531 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 532 }
533
534 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
535}
536
95ea3627 537static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 538 struct rt2x00lib_conf *libconf,
539 const unsigned int flags)
95ea3627 540{
e4ea1c40 541 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 542 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 543 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 544 rt2400pci_config_txpower(rt2x00dev,
545 libconf->conf->power_level);
e4ea1c40
ID		 546 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
547 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 548 if (flags & IEEE80211_CONF_CHANGE_PS)
549 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 550}
551
552static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 553 const int cw_min, const int cw_max)
95ea3627
ID		 554{
555 u32 reg;
556
557 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 558 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
559 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 560 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
561}
562
95ea3627
ID		 563/*
564 * Link tuning
565 */
ebcf26da
ID		 566static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
567 struct link_qual *qual)
95ea3627
ID		 568{
569 u32 reg;
570 u8 bbp;
571
572 /*
573 * Update FCS error count from register.
574 */
575 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 576 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 577
578 /*
579 * Update False CCA count from register.
580 */
581 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 582 qual->false_cca = bbp;
95ea3627
ID		 583}
584
5352ff65
ID		 585static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
586 struct link_qual *qual, u8 vgc_level)
eb20b4e8
ID		 587{
588 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
5352ff65
ID		 589 qual->vgc_level = vgc_level;
590 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 591}
592
5352ff65
ID		 593static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
594 struct link_qual *qual)
95ea3627 595{
5352ff65 596 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 597}
598
5352ff65
ID		 599static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
600 struct link_qual *qual, const u32 count)
95ea3627 601{
95ea3627
ID		 602 /*
603 * The link tuner should not run longer then 60 seconds,
604 * and should run once every 2 seconds.
605 */
5352ff65 606 if (count > 60 || !(count & 1))
95ea3627
ID		 607 return;
608
609 /*
610 * Base r13 link tuning on the false cca count.
611 */
5352ff65
ID		 612 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
613 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
614 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
615 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 616}
617
618/*
619 * Initialization functions.
620 */
798b7adb 621static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 622{
b8be63ff 623 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 624 u32 word;
625
798b7adb
ID		 626 if (entry->queue->qid == QID_RX) {
627 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 628
798b7adb
ID		 629 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
630 } else {
631 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 632
798b7adb
ID		 633 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
634 rt2x00_get_field32(word, TXD_W0_VALID));
635 }
95ea3627
ID		 636}
637
798b7adb 638static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 639{
b8be63ff 640 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 642 u32 word;
643
798b7adb
ID		 644 if (entry->queue->qid == QID_RX) {
645 rt2x00_desc_read(entry_priv->desc, 2, &word);
646 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
647 rt2x00_desc_write(entry_priv->desc, 2, word);
648
649 rt2x00_desc_read(entry_priv->desc, 1, &word);
650 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
651 rt2x00_desc_write(entry_priv->desc, 1, word);
652
653 rt2x00_desc_read(entry_priv->desc, 0, &word);
654 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
655 rt2x00_desc_write(entry_priv->desc, 0, word);
656 } else {
657 rt2x00_desc_read(entry_priv->desc, 0, &word);
658 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
659 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
660 rt2x00_desc_write(entry_priv->desc, 0, word);
661 }
95ea3627
ID		 662}
663
181d6902 664static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 665{
b8be63ff 666 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 667 u32 reg;
668
95ea3627
ID		 669 /*
670 * Initialize registers.
671 */
672 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 673 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
674 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
675 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
676 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 677 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
678
b8be63ff 679 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 680 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 681 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 682 entry_priv->desc_dma);
95ea3627
ID		 683 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
684
b8be63ff 685 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 686 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 687 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 688 entry_priv->desc_dma);
95ea3627
ID		 689 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
690
b8be63ff 691 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 692 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 693 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 694 entry_priv->desc_dma);
95ea3627
ID		 695 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
696
b8be63ff 697 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 698 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 699 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 700 entry_priv->desc_dma);
95ea3627
ID		 701 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
702
703 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
704 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 705 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 706 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
707
b8be63ff 708 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 709 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 710 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
711 entry_priv->desc_dma);
95ea3627
ID		 712 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
713
714 return 0;
715}
716
717static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
718{
719 u32 reg;
720
721 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
722 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
723 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
724 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
725
726 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
727 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
728 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
729 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
730 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
731
732 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
733 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
734 (rt2x00dev->rx->data_size / 128));
735 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
736
1f909162
ID		 737 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
738 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
739 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
740 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
741 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
742 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
743 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
744 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
745 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
746 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
747
95ea3627
ID		 748 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
749
750 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
751 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
752 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
753 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
754 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
755 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
756
757 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
758 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
759 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
760 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
761 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
762 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
763 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
764 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
765
766 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
767
768 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
769 return -EBUSY;
770
771 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
772 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
773
774 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
775 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
776 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
777
778 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
779 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
780 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
781 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
782 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
783 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
784
785 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
786 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
787 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
788 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
789 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
790
791 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
792 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
793 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
794 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
795
796 /*
797 * We must clear the FCS and FIFO error count.
798 * These registers are cleared on read,
799 * so we may pass a useless variable to store the value.
800 */
801 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
802 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
803
804 return 0;
805}
806
2b08da3f 807static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 808{
809 unsigned int i;
95ea3627
ID		 810 u8 value;
811
812 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
813 rt2400pci_bbp_read(rt2x00dev, 0, &value);
814 if ((value != 0xff) && (value != 0x00))
2b08da3f 815 return 0;
95ea3627
ID		 816 udelay(REGISTER_BUSY_DELAY);
817 }
818
819 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
820 return -EACCES;
2b08da3f
ID		 821}
822
823static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
824{
825 unsigned int i;
826 u16 eeprom;
827 u8 reg_id;
828 u8 value;
829
830 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
831 return -EACCES;
95ea3627 832
95ea3627
ID		 833 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
834 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
835 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
836 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
837 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
838 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
839 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
840 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
841 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
842 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
843 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
844 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
845 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
846 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
847
95ea3627
ID		 848 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
849 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
850
851 if (eeprom != 0xffff && eeprom != 0x0000) {
852 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
853 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 854 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
855 }
856 }
95ea3627
ID		 857
858 return 0;
859}
860
861/*
862 * Device state switch handlers.
863 */
864static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
865 enum dev_state state)
866{
867 u32 reg;
868
869 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
870 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 871 (state == STATE_RADIO_RX_OFF) ||
872 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 873 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
874}
875
876static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
877 enum dev_state state)
878{
879 int mask = (state == STATE_RADIO_IRQ_OFF);
880 u32 reg;
881
882 /*
883 * When interrupts are being enabled, the interrupt registers
884 * should clear the register to assure a clean state.
885 */
886 if (state == STATE_RADIO_IRQ_ON) {
887 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
888 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
889 }
890
891 /*
892 * Only toggle the interrupts bits we are going to use.
893 * Non-checked interrupt bits are disabled by default.
894 */
895 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
896 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
897 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
898 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
899 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
900 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
901 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
902}
903
904static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
905{
906 /*
907 * Initialize all registers.
908 */
2b08da3f
ID		 909 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
910 rt2400pci_init_registers(rt2x00dev) ||
911 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 912 return -EIO;
95ea3627 913
95ea3627
ID		 914 return 0;
915}
916
917static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
918{
95ea3627 919 /*
a2c9b652 920 * Disable power
95ea3627 921 */
a2c9b652 922 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 923}
924
925static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
926 enum dev_state state)
927{
928 u32 reg;
929 unsigned int i;
930 char put_to_sleep;
931 char bbp_state;
932 char rf_state;
933
934 put_to_sleep = (state != STATE_AWAKE);
935
936 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
937 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
938 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
939 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
940 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
941 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
942
943 /*
944 * Device is not guaranteed to be in the requested state yet.
945 * We must wait until the register indicates that the
946 * device has entered the correct state.
947 */
948 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
949 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
950 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
951 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
952 if (bbp_state == state && rf_state == state)
953 return 0;
954 msleep(10);
955 }
956
95ea3627
ID		 957 return -EBUSY;
958}
959
960static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
961 enum dev_state state)
962{
963 int retval = 0;
964
965 switch (state) {
966 case STATE_RADIO_ON:
967 retval = rt2400pci_enable_radio(rt2x00dev);
968 break;
969 case STATE_RADIO_OFF:
970 rt2400pci_disable_radio(rt2x00dev);
971 break;
972 case STATE_RADIO_RX_ON:
61667d8d 973 case STATE_RADIO_RX_ON_LINK:
95ea3627 974 case STATE_RADIO_RX_OFF:
61667d8d 975 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 976 rt2400pci_toggle_rx(rt2x00dev, state);
977 break;
978 case STATE_RADIO_IRQ_ON:
979 case STATE_RADIO_IRQ_OFF:
980 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 981 break;
982 case STATE_DEEP_SLEEP:
983 case STATE_SLEEP:
984 case STATE_STANDBY:
985 case STATE_AWAKE:
986 retval = rt2400pci_set_state(rt2x00dev, state);
987 break;
988 default:
989 retval = -ENOTSUPP;
990 break;
991 }
992
2b08da3f
ID		 993 if (unlikely(retval))
994 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
995 state, retval);
996
95ea3627
ID		 997 return retval;
998}
999
1000/*
1001 * TX descriptor initialization
1002 */
1003static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1004 struct sk_buff *skb,
61486e0f 1005 struct txentry_desc *txdesc)
95ea3627 1006{
181d6902 1007 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1008 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1009 __le32 *txd = skbdesc->desc;
95ea3627 1010 u32 word;
95ea3627
ID		 1011
1012 /*
1013 * Start writing the descriptor words.
1014 */
4de36fe5 1015 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1016 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1017 rt2x00_desc_write(entry_priv->desc, 1, word);
1018
95ea3627 1019 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1020 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1021 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1022 rt2x00_desc_write(txd, 2, word);
1023
1024 rt2x00_desc_read(txd, 3, &word);
181d6902 1025 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1026 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1027 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1028 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1029 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1030 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1031 rt2x00_desc_write(txd, 3, word);
1032
1033 rt2x00_desc_read(txd, 4, &word);
181d6902 1034 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1035 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1037 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1038 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1039 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1040 rt2x00_desc_write(txd, 4, word);
1041
1042 rt2x00_desc_read(txd, 0, &word);
1043 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1044 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1045 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1046 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1047 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1048 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1049 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1050 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1051 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1052 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1053 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1054 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1055 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627
ID		 1056 rt2x00_desc_write(txd, 0, word);
1057}
1058
1059/*
1060 * TX data initialization
1061 */
bd88a781
ID		 1062static void rt2400pci_write_beacon(struct queue_entry *entry)
1063{
1064 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1065 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1066 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1067 u32 word;
1068 u32 reg;
1069
1070 /*
1071 * Disable beaconing while we are reloading the beacon data,
1072 * otherwise we might be sending out invalid data.
1073 */
1074 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1075 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1076 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1077
1078 /*
1079 * Replace rt2x00lib allocated descriptor with the
1080 * pointer to the _real_ hardware descriptor.
1081 * After that, map the beacon to DMA and update the
1082 * descriptor.
1083 */
1084 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1085 skbdesc->desc = entry_priv->desc;
1086
1087 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1088
1089 rt2x00_desc_read(entry_priv->desc, 1, &word);
1090 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1091 rt2x00_desc_write(entry_priv->desc, 1, word);
d61cb266
GW		 1092
1093 /*
1094 * Enable beaconing again.
1095 */
1096 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1097 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1098 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1099 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1100}
1101
95ea3627 1102static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1103 const enum data_queue_qid queue)
95ea3627
ID		 1104{
1105 u32 reg;
1106
95ea3627 1107 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1108 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1109 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1110 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1111 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1112}
1113
a2c9b652
ID		 1114static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1115 const enum data_queue_qid qid)
1116{
1117 u32 reg;
1118
1119 if (qid == QID_BEACON) {
1120 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1121 } else {
1122 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1123 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1124 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1125 }
1126}
1127
95ea3627
ID		 1128/*
1129 * RX control handlers
1130 */
181d6902
ID		 1131static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1132 struct rxdone_entry_desc *rxdesc)
95ea3627 1133{
ae73e58e 1134 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1135 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1136 u32 word0;
1137 u32 word2;
89993890 1138 u32 word3;
ae73e58e
ID		 1139 u32 word4;
1140 u64 tsf;
1141 u32 rx_low;
1142 u32 rx_high;
95ea3627 1143
b8be63ff
ID		 1144 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1145 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1146 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1147 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1148
4150c572 1149 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1150 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1151 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1152 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1153
ae73e58e
ID		 1154 /*
1155 * We only get the lower 32bits from the timestamp,
1156 * to get the full 64bits we must complement it with
1157 * the timestamp from get_tsf().
1158 * Note that when a wraparound of the lower 32bits
1159 * has occurred between the frame arrival and the get_tsf()
1160 * call, we must decrease the higher 32bits with 1 to get
1161 * to correct value.
1162 */
1163 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1164 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1165 rx_high = upper_32_bits(tsf);
1166
1167 if ((u32)tsf <= rx_low)
1168 rx_high--;
1169
95ea3627
ID		 1170 /*
1171 * Obtain the status about this packet.
8ed09854
ID		 1172 * The signal is the PLCP value, and needs to be stripped
1173 * of the preamble bit (0x08).
95ea3627 1174 */
ae73e58e 1175 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1176 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1177 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1178 entry->queue->rt2x00dev->rssi_offset;
181d6902 1179 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1180
dec13b6b 1181 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1182 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1183 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1184}
1185
1186/*
1187 * Interrupt functions.
1188 */
181d6902 1189static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1190 const enum data_queue_qid queue_idx)
95ea3627 1191{
181d6902 1192 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1193 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1194 struct queue_entry *entry;
1195 struct txdone_entry_desc txdesc;
95ea3627 1196 u32 word;
95ea3627 1197
181d6902
ID		 1198 while (!rt2x00queue_empty(queue)) {
1199 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1200 entry_priv = entry->priv_data;
1201 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1202
1203 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1204 !rt2x00_get_field32(word, TXD_W0_VALID))
1205 break;
1206
1207 /*
1208 * Obtain the status about this packet.
1209 */
fb55f4d1
ID		 1210 txdesc.flags = 0;
1211 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1212 case 0: /* Success */
1213 case 1: /* Success with retry */
1214 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1215 break;
1216 case 2: /* Failure, excessive retries */
1217 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1218 /* Don't break, this is a failed frame! */
1219 default: /* Failure */
1220 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1221 }
181d6902 1222 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1223
d74f5ba4 1224 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1225 }
95ea3627
ID		 1226}
1227
1228static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1229{
1230 struct rt2x00_dev *rt2x00dev = dev_instance;
1231 u32 reg;
1232
1233 /*
1234 * Get the interrupt sources & saved to local variable.
1235 * Write register value back to clear pending interrupts.
1236 */
1237 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1238 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1239
1240 if (!reg)
1241 return IRQ_NONE;
1242
0262ab0d 1243 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1244 return IRQ_HANDLED;
1245
1246 /*
1247 * Handle interrupts, walk through all bits
1248 * and run the tasks, the bits are checked in order of
1249 * priority.
1250 */
1251
1252 /*
1253 * 1 - Beacon timer expired interrupt.
1254 */
1255 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1256 rt2x00lib_beacondone(rt2x00dev);
1257
1258 /*
1259 * 2 - Rx ring done interrupt.
1260 */
1261 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1262 rt2x00pci_rxdone(rt2x00dev);
1263
1264 /*
1265 * 3 - Atim ring transmit done interrupt.
1266 */
1267 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1268 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1269
1270 /*
1271 * 4 - Priority ring transmit done interrupt.
1272 */
1273 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1274 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1275
1276 /*
1277 * 5 - Tx ring transmit done interrupt.
1278 */
1279 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1280 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1281
1282 return IRQ_HANDLED;
1283}
1284
1285/*
1286 * Device probe functions.
1287 */
1288static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1289{
1290 struct eeprom_93cx6 eeprom;
1291 u32 reg;
1292 u16 word;
1293 u8 *mac;
1294
1295 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1296
1297 eeprom.data = rt2x00dev;
1298 eeprom.register_read = rt2400pci_eepromregister_read;
1299 eeprom.register_write = rt2400pci_eepromregister_write;
1300 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1301 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1302 eeprom.reg_data_in = 0;
1303 eeprom.reg_data_out = 0;
1304 eeprom.reg_data_clock = 0;
1305 eeprom.reg_chip_select = 0;
1306
1307 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1308 EEPROM_SIZE / sizeof(u16));
1309
1310 /*
1311 * Start validation of the data that has been read.
1312 */
1313 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1314 if (!is_valid_ether_addr(mac)) {
1315 random_ether_addr(mac);
e174961c 1316 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1317 }
1318
1319 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1320 if (word == 0xffff) {
1321 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1322 return -EINVAL;
1323 }
1324
1325 return 0;
1326}
1327
1328static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1329{
1330 u32 reg;
1331 u16 value;
1332 u16 eeprom;
1333
1334 /*
1335 * Read EEPROM word for configuration.
1336 */
1337 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1338
1339 /*
1340 * Identify RF chipset.
1341 */
1342 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1343 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1344 rt2x00_set_chip(rt2x00dev, RT2460, value,
1345 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1346
5122d898 1347 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1348 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1349 return -ENODEV;
1350 }
1351
1352 /*
1353 * Identify default antenna configuration.
1354 */
addc81bd 1355 rt2x00dev->default_ant.tx =
95ea3627 1356 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1357 rt2x00dev->default_ant.rx =
95ea3627
ID		 1358 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1359
addc81bd
ID		 1360 /*
1361 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1362 * I am not 100% sure about this, but the legacy drivers do not
1363 * indicate antenna swapping in software is required when
1364 * diversity is enabled.
1365 */
1366 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1367 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1368 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1369 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1370
95ea3627
ID		 1371 /*
1372 * Store led mode, for correct led behaviour.
1373 */
771fd565 1374#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1375 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1376
475433be 1377 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1378 if (value == LED_MODE_TXRX_ACTIVITY ||
1379 value == LED_MODE_DEFAULT ||
1380 value == LED_MODE_ASUS)
475433be
ID		 1381 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1382 LED_TYPE_ACTIVITY);
771fd565 1383#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1384
1385 /*
1386 * Detect if this device has an hardware controlled radio.
1387 */
1388 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1389 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1390
1391 /*
1392 * Check if the BBP tuning should be enabled.
1393 */
1394 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1395 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1396
1397 return 0;
1398}
1399
1400/*
1401 * RF value list for RF2420 & RF2421
1402 * Supports: 2.4 GHz
1403 */
8c5e7a5f 1404static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1405 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1406 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1407 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1408 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1409 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1410 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1411 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1412 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1413 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1414 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1415 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1416 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1417 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1418 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1419};
1420
8c5e7a5f 1421static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1422{
1423 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1424 struct channel_info *info;
1425 char *tx_power;
95ea3627
ID		 1426 unsigned int i;
1427
1428 /*
1429 * Initialize all hw fields.
1430 */
566bfe5a 1431 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1432 IEEE80211_HW_SIGNAL_DBM |
1433 IEEE80211_HW_SUPPORTS_PS |
1434 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1435
14a3bf89 1436 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1437 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1438 rt2x00_eeprom_addr(rt2x00dev,
1439 EEPROM_MAC_ADDR_0));
1440
95ea3627
ID		 1441 /*
1442 * Initialize hw_mode information.
1443 */
31562e80
ID		 1444 spec->supported_bands = SUPPORT_BAND_2GHZ;
1445 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1446
8c5e7a5f
ID		 1447 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1448 spec->channels = rf_vals_b;
1449
1450 /*
1451 * Create channel information array
1452 */
1453 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1454 if (!info)
1455 return -ENOMEM;
1456
1457 spec->channels_info = info;
1458
1459 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1460 for (i = 0; i < 14; i++)
1461 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1462
1463 return 0;
95ea3627
ID		 1464}
1465
1466static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1467{
1468 int retval;
1469
1470 /*
1471 * Allocate eeprom data.
1472 */
1473 retval = rt2400pci_validate_eeprom(rt2x00dev);
1474 if (retval)
1475 return retval;
1476
1477 retval = rt2400pci_init_eeprom(rt2x00dev);
1478 if (retval)
1479 return retval;
1480
1481 /*
1482 * Initialize hw specifications.
1483 */
8c5e7a5f
ID		 1484 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1485 if (retval)
1486 return retval;
95ea3627
ID		 1487
1488 /*
c4da0048 1489 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1490 */
181d6902 1491 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1492 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1493
1494 /*
1495 * Set the rssi offset.
1496 */
1497 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1498
1499 return 0;
1500}
1501
1502/*
1503 * IEEE80211 stack callback functions.
1504 */
e100bb64 1505static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1506 const struct ieee80211_tx_queue_params *params)
1507{
1508 struct rt2x00_dev *rt2x00dev = hw->priv;
1509
1510 /*
1511 * We don't support variating cw_min and cw_max variables
1512 * per queue. So by default we only configure the TX queue,
1513 * and ignore all other configurations.
1514 */
e100bb64 1515 if (queue != 0)
95ea3627
ID		 1516 return -EINVAL;
1517
1518 if (rt2x00mac_conf_tx(hw, queue, params))
1519 return -EINVAL;
1520
1521 /*
1522 * Write configuration to register.
1523 */
181d6902
ID		 1524 rt2400pci_config_cw(rt2x00dev,
1525 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1526
1527 return 0;
1528}
1529
1530static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1531{
1532 struct rt2x00_dev *rt2x00dev = hw->priv;
1533 u64 tsf;
1534 u32 reg;
1535
1536 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1537 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1538 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1539 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1540
1541 return tsf;
1542}
1543
95ea3627
ID		 1544static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1545{
1546 struct rt2x00_dev *rt2x00dev = hw->priv;
1547 u32 reg;
1548
1549 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1550 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1551}
1552
1553static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1554 .tx = rt2x00mac_tx,
4150c572
JB		 1555 .start = rt2x00mac_start,
1556 .stop = rt2x00mac_stop,
95ea3627
ID		 1557 .add_interface = rt2x00mac_add_interface,
1558 .remove_interface = rt2x00mac_remove_interface,
1559 .config = rt2x00mac_config,
3a643d24 1560 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1561 .set_tim = rt2x00mac_set_tim,
95ea3627 1562 .get_stats = rt2x00mac_get_stats,
471b3efd 1563 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1564 .conf_tx = rt2400pci_conf_tx,
95ea3627 1565 .get_tsf = rt2400pci_get_tsf,
95ea3627 1566 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1567 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1568};
1569
1570static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1571 .irq_handler = rt2400pci_interrupt,
1572 .probe_hw = rt2400pci_probe_hw,
1573 .initialize = rt2x00pci_initialize,
1574 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1575 .get_entry_state = rt2400pci_get_entry_state,
1576 .clear_entry = rt2400pci_clear_entry,
95ea3627 1577 .set_device_state = rt2400pci_set_device_state,
95ea3627 1578 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1579 .link_stats = rt2400pci_link_stats,
1580 .reset_tuner = rt2400pci_reset_tuner,
1581 .link_tuner = rt2400pci_link_tuner,
1582 .write_tx_desc = rt2400pci_write_tx_desc,
1583 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1584 .write_beacon = rt2400pci_write_beacon,
95ea3627 1585 .kick_tx_queue = rt2400pci_kick_tx_queue,
a2c9b652 1586 .kill_tx_queue = rt2400pci_kill_tx_queue,
95ea3627 1587 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1588 .config_filter = rt2400pci_config_filter,
6bb40dd1 1589 .config_intf = rt2400pci_config_intf,
72810379 1590 .config_erp = rt2400pci_config_erp,
e4ea1c40 1591 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1592 .config = rt2400pci_config,
1593};
1594
181d6902
ID		 1595static const struct data_queue_desc rt2400pci_queue_rx = {
1596 .entry_num = RX_ENTRIES,
1597 .data_size = DATA_FRAME_SIZE,
1598 .desc_size = RXD_DESC_SIZE,
b8be63ff 1599 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1600};
1601
1602static const struct data_queue_desc rt2400pci_queue_tx = {
1603 .entry_num = TX_ENTRIES,
1604 .data_size = DATA_FRAME_SIZE,
1605 .desc_size = TXD_DESC_SIZE,
b8be63ff 1606 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1607};
1608
1609static const struct data_queue_desc rt2400pci_queue_bcn = {
1610 .entry_num = BEACON_ENTRIES,
1611 .data_size = MGMT_FRAME_SIZE,
1612 .desc_size = TXD_DESC_SIZE,
b8be63ff 1613 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1614};
1615
1616static const struct data_queue_desc rt2400pci_queue_atim = {
1617 .entry_num = ATIM_ENTRIES,
1618 .data_size = DATA_FRAME_SIZE,
1619 .desc_size = TXD_DESC_SIZE,
b8be63ff 1620 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1621};
1622
95ea3627 1623static const struct rt2x00_ops rt2400pci_ops = {
04d0362e
GW		 1624 .name = KBUILD_MODNAME,
1625 .max_sta_intf = 1,
1626 .max_ap_intf = 1,
1627 .eeprom_size = EEPROM_SIZE,
1628 .rf_size = RF_SIZE,
1629 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1630 .extra_tx_headroom = 0,
04d0362e
GW		 1631 .rx = &rt2400pci_queue_rx,
1632 .tx = &rt2400pci_queue_tx,
1633 .bcn = &rt2400pci_queue_bcn,
1634 .atim = &rt2400pci_queue_atim,
1635 .lib = &rt2400pci_rt2x00_ops,
1636 .hw = &rt2400pci_mac80211_ops,
95ea3627 1637#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1638 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1639#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1640};
1641
1642/*
1643 * RT2400pci module information.
1644 */
a3aa1884 1645static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
95ea3627
ID		 1646 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1647 { 0, }
1648};
1649
1650MODULE_AUTHOR(DRV_PROJECT);
1651MODULE_VERSION(DRV_VERSION);
1652MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1653MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1654MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1655MODULE_LICENSE("GPL");
1656
1657static struct pci_driver rt2400pci_driver = {
2360157c 1658 .name = KBUILD_MODNAME,
95ea3627
ID		 1659 .id_table = rt2400pci_device_table,
1660 .probe = rt2x00pci_probe,
1661 .remove = __devexit_p(rt2x00pci_remove),
1662 .suspend = rt2x00pci_suspend,
1663 .resume = rt2x00pci_resume,
1664};
1665
1666static int __init rt2400pci_init(void)
1667{
1668 return pci_register_driver(&rt2400pci_driver);
1669}
1670
1671static void __exit rt2400pci_exit(void)
1672{
1673 pci_unregister_driver(&rt2400pci_driver);
1674}
1675
1676module_init(rt2400pci_init);
1677module_exit(rt2400pci_exit);
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