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rt2x00: Introduce extra queue entry sanity flag
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt2400pci.h"
39
40/*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
c9c3b1a5
ID		 53#define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55#define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 57
0e14f6d3 58static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 59 const unsigned int word, const u8 value)
60{
61 u32 reg;
62
8ff48a8b
ID		 63 mutex_lock(&rt2x00dev->csr_mutex);
64
95ea3627 65 /*
c9c3b1a5
ID		 66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
95ea3627 68 */
c9c3b1a5
ID		 69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
8ff48a8b 78
8ff48a8b 79 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 80}
81
0e14f6d3 82static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int word, u8 *value)
84{
85 u32 reg;
86
8ff48a8b
ID		 87 mutex_lock(&rt2x00dev->csr_mutex);
88
95ea3627 89 /*
c9c3b1a5
ID		 90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
95ea3627 96 */
c9c3b1a5
ID		 97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 102
c9c3b1a5 103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 104
c9c3b1a5
ID		 105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
95ea3627
ID		 107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 109
110 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 111}
112
0e14f6d3 113static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int word, const u32 value)
115{
116 u32 reg;
95ea3627 117
8ff48a8b
ID		 118 mutex_lock(&rt2x00dev->csr_mutex);
119
c9c3b1a5
ID		 120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 133 }
134
8ff48a8b 135 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 136}
137
138static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139{
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151}
152
153static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154{
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166}
167
168#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 169static const struct rt2x00debug rt2400pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
743b97ca
ID		 172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
95ea3627
ID		 176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
743b97ca 182 .word_base = EEPROM_BASE,
95ea3627
ID		 183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2400pci_bbp_read,
188 .write = rt2400pci_bbp_write,
743b97ca 189 .word_base = BBP_BASE,
95ea3627
ID		 190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2400pci_rf_write,
743b97ca 196 .word_base = RF_BASE,
95ea3627
ID		 197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200};
201#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
95ea3627
ID		 203static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204{
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209}
95ea3627 210
771fd565 211#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 212static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 213 enum led_brightness brightness)
214{
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
a2e1d52a 222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228}
a2e1d52a
ID		 229
230static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244}
475433be
ID		 245
246static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2400pci_brightness_set;
253 led->led_dev.blink_set = rt2400pci_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
3a643d24
ID		 261static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263{
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * since there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285}
286
6bb40dd1
ID		 287static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
95ea3627 291{
6bb40dd1
ID		 292 unsigned int bcn_preload;
293 u32 reg;
95ea3627 294
6bb40dd1 295 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 296 /*
297 * Enable beacon config
298 */
bad13639 299 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 303
6bb40dd1
ID		 304 /*
305 * Enable synchronisation.
306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 308 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 310 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 311 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312 }
95ea3627 313
6bb40dd1
ID		 314 if (flags & CONFIG_UPDATE_MAC)
315 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
316 conf->mac, sizeof(conf->mac));
95ea3627 317
6bb40dd1
ID		 318 if (flags & CONFIG_UPDATE_BSSID)
319 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
320 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 321}
322
3a643d24 323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 324 struct rt2x00lib_erp *erp,
325 u32 changed)
95ea3627 326{
5c58ee51 327 int preamble_mask;
95ea3627 328 u32 reg;
95ea3627 329
5c58ee51
ID		 330 /*
331 * When short preamble is enabled, we should set bit 0x08
332 */
02044643
HS		 333 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
334 preamble_mask = erp->short_preamble << 3;
335
336 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
337 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
338 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
339 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
340 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
341 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
342
343 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
344 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
345 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
347 GET_DURATION(ACK_SIZE, 10));
348 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
349
350 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
351 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
352 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
353 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
354 GET_DURATION(ACK_SIZE, 20));
355 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
356
357 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
358 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
359 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
360 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
361 GET_DURATION(ACK_SIZE, 55));
362 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
363
364 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
365 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
366 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
367 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
368 GET_DURATION(ACK_SIZE, 110));
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370 }
371
372 if (changed & BSS_CHANGED_BASIC_RATES)
373 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
374
375 if (changed & BSS_CHANGED_ERP_SLOT) {
376 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
377 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
378 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
379
380 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
381 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
382 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
383 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
384
385 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
386 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
387 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
388 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
389 }
390
391 if (changed & BSS_CHANGED_BEACON_INT) {
392 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
393 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
394 erp->beacon_int * 16);
395 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
396 erp->beacon_int * 16);
397 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
398 }
95ea3627
ID		 399}
400
e4ea1c40
ID		 401static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
402 struct antenna_setup *ant)
95ea3627 403{
e4ea1c40
ID		 404 u8 r1;
405 u8 r4;
406
407 /*
408 * We should never come here because rt2x00lib is supposed
409 * to catch this and send us the correct antenna explicitely.
410 */
411 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
412 ant->tx == ANTENNA_SW_DIVERSITY);
413
414 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
415 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
416
417 /*
418 * Configure the TX antenna.
419 */
420 switch (ant->tx) {
421 case ANTENNA_HW_DIVERSITY:
422 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
423 break;
424 case ANTENNA_A:
425 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
426 break;
427 case ANTENNA_B:
428 default:
429 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
430 break;
431 }
432
433 /*
434 * Configure the RX antenna.
435 */
436 switch (ant->rx) {
437 case ANTENNA_HW_DIVERSITY:
438 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
439 break;
440 case ANTENNA_A:
441 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
442 break;
443 case ANTENNA_B:
444 default:
445 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
446 break;
447 }
448
449 rt2400pci_bbp_write(rt2x00dev, 4, r4);
450 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 451}
452
453static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 454 struct rf_channel *rf)
95ea3627 455{
95ea3627
ID		 456 /*
457 * Switch on tuning bits.
458 */
5c58ee51
ID		 459 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
460 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 461
5c58ee51
ID		 462 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
463 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
464 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 465
466 /*
467 * RF2420 chipset don't need any additional actions.
468 */
5122d898 469 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 470 return;
471
472 /*
473 * For the RT2421 chipsets we need to write an invalid
474 * reference clock rate to activate auto_tune.
475 * After that we set the value back to the correct channel.
476 */
5c58ee51 477 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 478 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 479 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 480
481 msleep(1);
482
5c58ee51
ID		 483 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
484 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 486
487 msleep(1);
488
489 /*
490 * Switch off tuning bits.
491 */
5c58ee51
ID		 492 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
493 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 494
5c58ee51
ID		 495 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
496 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 497
498 /*
499 * Clear false CRC during channel switch.
500 */
5c58ee51 501 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 502}
503
504static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
505{
506 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
507}
508
e4ea1c40
ID		 509static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
510 struct rt2x00lib_conf *libconf)
95ea3627 511{
e4ea1c40 512 u32 reg;
95ea3627 513
e4ea1c40
ID		 514 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
515 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
516 libconf->conf->long_frame_max_tx_count);
517 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
518 libconf->conf->short_frame_max_tx_count);
519 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 520}
521
7d7f19cc
ID		 522static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
523 struct rt2x00lib_conf *libconf)
524{
525 enum dev_state state =
526 (libconf->conf->flags & IEEE80211_CONF_PS) ?
527 STATE_SLEEP : STATE_AWAKE;
528 u32 reg;
529
530 if (state == STATE_SLEEP) {
531 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
532 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 533 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 534 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
535 libconf->conf->listen_interval - 1);
536
537 /* We must first disable autowake before it can be enabled */
538 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
539 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
540
541 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
542 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 543 } else {
544 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
545 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
546 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 547 }
548
549 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
550}
551
95ea3627 552static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 553 struct rt2x00lib_conf *libconf,
554 const unsigned int flags)
95ea3627 555{
e4ea1c40 556 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 557 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 558 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 559 rt2400pci_config_txpower(rt2x00dev,
560 libconf->conf->power_level);
e4ea1c40
ID		 561 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
562 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 563 if (flags & IEEE80211_CONF_CHANGE_PS)
564 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 565}
566
567static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 568 const int cw_min, const int cw_max)
95ea3627
ID		 569{
570 u32 reg;
571
572 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 573 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
574 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 575 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
576}
577
95ea3627
ID		 578/*
579 * Link tuning
580 */
ebcf26da
ID		 581static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
582 struct link_qual *qual)
95ea3627
ID		 583{
584 u32 reg;
585 u8 bbp;
586
587 /*
588 * Update FCS error count from register.
589 */
590 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 591 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 592
593 /*
594 * Update False CCA count from register.
595 */
596 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 597 qual->false_cca = bbp;
95ea3627
ID		 598}
599
5352ff65
ID		 600static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
601 struct link_qual *qual, u8 vgc_level)
eb20b4e8 602{
223dcc26
ID		 603 if (qual->vgc_level_reg != vgc_level) {
604 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
605 qual->vgc_level = vgc_level;
606 qual->vgc_level_reg = vgc_level;
607 }
eb20b4e8
ID		 608}
609
5352ff65
ID		 610static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
611 struct link_qual *qual)
95ea3627 612{
5352ff65 613 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 614}
615
5352ff65
ID		 616static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
617 struct link_qual *qual, const u32 count)
95ea3627 618{
95ea3627
ID		 619 /*
620 * The link tuner should not run longer then 60 seconds,
621 * and should run once every 2 seconds.
622 */
5352ff65 623 if (count > 60 || !(count & 1))
95ea3627
ID		 624 return;
625
626 /*
627 * Base r13 link tuning on the false cca count.
628 */
5352ff65
ID		 629 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
630 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
631 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
632 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 633}
634
5450b7e2
ID		 635/*
636 * Queue handlers.
637 */
638static void rt2400pci_start_queue(struct data_queue *queue)
639{
640 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
641 u32 reg;
642
643 switch (queue->qid) {
644 case QID_RX:
645 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
646 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
647 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
648 break;
649 case QID_BEACON:
650 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
651 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
652 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
653 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
654 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
655 break;
656 default:
657 break;
658 }
659}
660
661static void rt2400pci_kick_queue(struct data_queue *queue)
662{
663 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
664 u32 reg;
665
666 switch (queue->qid) {
667 case QID_AC_BE:
668 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
669 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
670 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
671 break;
672 case QID_AC_BK:
673 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
674 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
675 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
676 break;
677 case QID_ATIM:
678 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
679 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
680 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
681 break;
682 default:
683 break;
684 }
685}
686
687static void rt2400pci_stop_queue(struct data_queue *queue)
688{
689 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
690 u32 reg;
691
692 switch (queue->qid) {
693 case QID_AC_BE:
694 case QID_AC_BK:
695 case QID_ATIM:
696 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
697 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
698 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
699 break;
700 case QID_RX:
701 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
702 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
703 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
704 break;
705 case QID_BEACON:
706 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
707 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
708 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
709 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
710 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
711 break;
712 default:
713 break;
714 }
715}
716
95ea3627
ID		 717/*
718 * Initialization functions.
719 */
798b7adb 720static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 721{
b8be63ff 722 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 723 u32 word;
724
798b7adb
ID		 725 if (entry->queue->qid == QID_RX) {
726 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 727
798b7adb
ID		 728 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
729 } else {
730 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 731
798b7adb
ID		 732 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
733 rt2x00_get_field32(word, TXD_W0_VALID));
734 }
95ea3627
ID		 735}
736
798b7adb 737static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 738{
b8be63ff 739 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 740 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 741 u32 word;
742
798b7adb
ID		 743 if (entry->queue->qid == QID_RX) {
744 rt2x00_desc_read(entry_priv->desc, 2, &word);
745 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
746 rt2x00_desc_write(entry_priv->desc, 2, word);
747
748 rt2x00_desc_read(entry_priv->desc, 1, &word);
749 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
750 rt2x00_desc_write(entry_priv->desc, 1, word);
751
752 rt2x00_desc_read(entry_priv->desc, 0, &word);
753 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
754 rt2x00_desc_write(entry_priv->desc, 0, word);
755 } else {
756 rt2x00_desc_read(entry_priv->desc, 0, &word);
757 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
758 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
759 rt2x00_desc_write(entry_priv->desc, 0, word);
760 }
95ea3627
ID		 761}
762
181d6902 763static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 764{
b8be63ff 765 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 766 u32 reg;
767
95ea3627
ID		 768 /*
769 * Initialize registers.
770 */
771 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 772 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
773 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
774 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
775 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 776 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
777
b8be63ff 778 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 779 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 780 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 781 entry_priv->desc_dma);
95ea3627
ID		 782 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
783
b8be63ff 784 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 785 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 786 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 787 entry_priv->desc_dma);
95ea3627
ID		 788 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
789
b8be63ff 790 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 791 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 792 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 793 entry_priv->desc_dma);
95ea3627
ID		 794 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
795
b8be63ff 796 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 797 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 798 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 799 entry_priv->desc_dma);
95ea3627
ID		 800 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
801
802 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
803 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 804 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 805 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
806
b8be63ff 807 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 808 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 809 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
810 entry_priv->desc_dma);
95ea3627
ID		 811 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
812
813 return 0;
814}
815
816static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
817{
818 u32 reg;
819
820 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
821 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
822 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
823 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
824
825 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
826 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
827 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
828 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
829 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
830
831 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
832 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
833 (rt2x00dev->rx->data_size / 128));
834 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
835
1f909162
ID		 836 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
837 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
838 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
839 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
840 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
841 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
842 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
843 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
844 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
845 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
846
95ea3627
ID		 847 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
848
849 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
850 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
851 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
852 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
853 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
854 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
855
856 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
857 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
858 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
863 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
864
865 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
866
867 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
868 return -EBUSY;
869
870 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
871 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
872
873 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
874 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
875 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
876
877 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
878 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
879 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
880 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
881 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
882 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
883
884 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
885 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
886 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
887 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
888 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
889
890 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
891 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
892 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
893 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
894
895 /*
896 * We must clear the FCS and FIFO error count.
897 * These registers are cleared on read,
898 * so we may pass a useless variable to store the value.
899 */
900 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
901 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
902
903 return 0;
904}
905
2b08da3f 906static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 907{
908 unsigned int i;
95ea3627
ID		 909 u8 value;
910
911 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
912 rt2400pci_bbp_read(rt2x00dev, 0, &value);
913 if ((value != 0xff) && (value != 0x00))
2b08da3f 914 return 0;
95ea3627
ID		 915 udelay(REGISTER_BUSY_DELAY);
916 }
917
918 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
919 return -EACCES;
2b08da3f
ID		 920}
921
922static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
923{
924 unsigned int i;
925 u16 eeprom;
926 u8 reg_id;
927 u8 value;
928
929 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
930 return -EACCES;
95ea3627 931
95ea3627
ID		 932 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
933 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
934 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
935 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
936 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
937 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
938 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
939 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
940 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
941 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
942 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
943 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
944 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
945 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
946
95ea3627
ID		 947 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
948 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
949
950 if (eeprom != 0xffff && eeprom != 0x0000) {
951 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
952 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 953 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
954 }
955 }
95ea3627
ID		 956
957 return 0;
958}
959
960/*
961 * Device state switch handlers.
962 */
95ea3627
ID		 963static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
964 enum dev_state state)
965{
78e256c9
HS		 966 int mask = (state == STATE_RADIO_IRQ_OFF) ||
967 (state == STATE_RADIO_IRQ_OFF_ISR);
95ea3627
ID		 968 u32 reg;
969
970 /*
971 * When interrupts are being enabled, the interrupt registers
972 * should clear the register to assure a clean state.
973 */
974 if (state == STATE_RADIO_IRQ_ON) {
975 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
976 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
977 }
978
979 /*
980 * Only toggle the interrupts bits we are going to use.
981 * Non-checked interrupt bits are disabled by default.
982 */
983 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
984 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
985 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
986 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
987 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
988 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
989 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
990}
991
992static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
993{
994 /*
995 * Initialize all registers.
996 */
2b08da3f
ID		 997 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
998 rt2400pci_init_registers(rt2x00dev) ||
999 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 1000 return -EIO;
95ea3627 1001
95ea3627
ID		 1002 return 0;
1003}
1004
1005static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1006{
95ea3627 1007 /*
a2c9b652 1008 * Disable power
95ea3627 1009 */
a2c9b652 1010 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1011}
1012
1013static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1014 enum dev_state state)
1015{
9655a6ec 1016 u32 reg, reg2;
95ea3627
ID		 1017 unsigned int i;
1018 char put_to_sleep;
1019 char bbp_state;
1020 char rf_state;
1021
1022 put_to_sleep = (state != STATE_AWAKE);
1023
1024 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1025 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1026 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1027 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1028 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1029 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1030
1031 /*
1032 * Device is not guaranteed to be in the requested state yet.
1033 * We must wait until the register indicates that the
1034 * device has entered the correct state.
1035 */
1036 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1037 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1038 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1039 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1040 if (bbp_state == state && rf_state == state)
1041 return 0;
9655a6ec 1042 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1043 msleep(10);
1044 }
1045
95ea3627
ID		 1046 return -EBUSY;
1047}
1048
1049static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1050 enum dev_state state)
1051{
1052 int retval = 0;
1053
1054 switch (state) {
1055 case STATE_RADIO_ON:
1056 retval = rt2400pci_enable_radio(rt2x00dev);
1057 break;
1058 case STATE_RADIO_OFF:
1059 rt2400pci_disable_radio(rt2x00dev);
1060 break;
2b08da3f 1061 case STATE_RADIO_IRQ_ON:
78e256c9 1062 case STATE_RADIO_IRQ_ON_ISR:
2b08da3f 1063 case STATE_RADIO_IRQ_OFF:
78e256c9 1064 case STATE_RADIO_IRQ_OFF_ISR:
2b08da3f 1065 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1066 break;
1067 case STATE_DEEP_SLEEP:
1068 case STATE_SLEEP:
1069 case STATE_STANDBY:
1070 case STATE_AWAKE:
1071 retval = rt2400pci_set_state(rt2x00dev, state);
1072 break;
1073 default:
1074 retval = -ENOTSUPP;
1075 break;
1076 }
1077
2b08da3f
ID		 1078 if (unlikely(retval))
1079 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1080 state, retval);
1081
95ea3627
ID		 1082 return retval;
1083}
1084
1085/*
1086 * TX descriptor initialization
1087 */
93331458 1088static void rt2400pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1089 struct txentry_desc *txdesc)
95ea3627 1090{
93331458
ID		 1091 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1092 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1093 __le32 *txd = entry_priv->desc;
95ea3627 1094 u32 word;
95ea3627
ID		 1095
1096 /*
1097 * Start writing the descriptor words.
1098 */
85b7a8b3 1099 rt2x00_desc_read(txd, 1, &word);
c4da0048 1100 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1101 rt2x00_desc_write(txd, 1, word);
4de36fe5 1102
95ea3627 1103 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1104 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1105 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1106 rt2x00_desc_write(txd, 2, word);
1107
1108 rt2x00_desc_read(txd, 3, &word);
181d6902 1109 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1110 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1111 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1112 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1113 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1114 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1115 rt2x00_desc_write(txd, 3, word);
1116
1117 rt2x00_desc_read(txd, 4, &word);
181d6902 1118 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1119 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1121 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1122 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1123 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1124 rt2x00_desc_write(txd, 4, word);
1125
e01f1ec3
GW		 1126 /*
1127 * Writing TXD word 0 must the last to prevent a race condition with
1128 * the device, whereby the device may take hold of the TXD before we
1129 * finished updating it.
1130 */
95ea3627
ID		 1131 rt2x00_desc_read(txd, 0, &word);
1132 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1133 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1134 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1135 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1136 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1137 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1138 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1139 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1140 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1141 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1142 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1143 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1144 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1145 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1146
1147 /*
1148 * Register descriptor details in skb frame descriptor.
1149 */
1150 skbdesc->desc = txd;
1151 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1152}
1153
1154/*
1155 * TX data initialization
1156 */
f224f4ef
GW		 1157static void rt2400pci_write_beacon(struct queue_entry *entry,
1158 struct txentry_desc *txdesc)
bd88a781
ID		 1159{
1160 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1161 u32 reg;
1162
1163 /*
1164 * Disable beaconing while we are reloading the beacon data,
1165 * otherwise we might be sending out invalid data.
1166 */
1167 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1168 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1169 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1170
fa69560f 1171 rt2x00queue_map_txskb(entry);
bd88a781 1172
5c3b685c
GW		 1173 /*
1174 * Write the TX descriptor for the beacon.
1175 */
93331458 1176 rt2400pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1177
1178 /*
1179 * Dump beacon to userspace through debugfs.
1180 */
1181 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
d61cb266
GW		 1182
1183 /*
1184 * Enable beaconing again.
1185 */
1186 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1187 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1188 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1189 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1190}
1191
95ea3627
ID		 1192/*
1193 * RX control handlers
1194 */
181d6902
ID		 1195static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1196 struct rxdone_entry_desc *rxdesc)
95ea3627 1197{
ae73e58e 1198 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1199 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1200 u32 word0;
1201 u32 word2;
89993890 1202 u32 word3;
ae73e58e
ID		 1203 u32 word4;
1204 u64 tsf;
1205 u32 rx_low;
1206 u32 rx_high;
95ea3627 1207
b8be63ff
ID		 1208 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1209 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1210 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1211 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1212
4150c572 1213 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1214 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1215 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1216 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1217
ae73e58e
ID		 1218 /*
1219 * We only get the lower 32bits from the timestamp,
1220 * to get the full 64bits we must complement it with
1221 * the timestamp from get_tsf().
1222 * Note that when a wraparound of the lower 32bits
1223 * has occurred between the frame arrival and the get_tsf()
1224 * call, we must decrease the higher 32bits with 1 to get
1225 * to correct value.
1226 */
1227 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1228 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1229 rx_high = upper_32_bits(tsf);
1230
1231 if ((u32)tsf <= rx_low)
1232 rx_high--;
1233
95ea3627
ID		 1234 /*
1235 * Obtain the status about this packet.
8ed09854
ID		 1236 * The signal is the PLCP value, and needs to be stripped
1237 * of the preamble bit (0x08).
95ea3627 1238 */
ae73e58e 1239 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1240 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1241 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1242 entry->queue->rt2x00dev->rssi_offset;
181d6902 1243 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1244
dec13b6b 1245 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1246 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1247 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1248}
1249
1250/*
1251 * Interrupt functions.
1252 */
181d6902 1253static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1254 const enum data_queue_qid queue_idx)
95ea3627 1255{
181d6902 1256 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1257 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1258 struct queue_entry *entry;
1259 struct txdone_entry_desc txdesc;
95ea3627 1260 u32 word;
95ea3627 1261
181d6902
ID		 1262 while (!rt2x00queue_empty(queue)) {
1263 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1264 entry_priv = entry->priv_data;
1265 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1266
1267 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1268 !rt2x00_get_field32(word, TXD_W0_VALID))
1269 break;
1270
1271 /*
1272 * Obtain the status about this packet.
1273 */
fb55f4d1
ID		 1274 txdesc.flags = 0;
1275 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1276 case 0: /* Success */
1277 case 1: /* Success with retry */
1278 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1279 break;
1280 case 2: /* Failure, excessive retries */
1281 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1282 /* Don't break, this is a failed frame! */
1283 default: /* Failure */
1284 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1285 }
181d6902 1286 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1287
e513a0b6 1288 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1289 }
95ea3627
ID		 1290}
1291
78e256c9 1292static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
95ea3627
ID		 1293{
1294 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 1295 u32 reg = rt2x00dev->irqvalue[0];
95ea3627
ID		 1296
1297 /*
1298 * Handle interrupts, walk through all bits
1299 * and run the tasks, the bits are checked in order of
1300 * priority.
1301 */
1302
1303 /*
1304 * 1 - Beacon timer expired interrupt.
1305 */
1306 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1307 rt2x00lib_beacondone(rt2x00dev);
1308
1309 /*
1310 * 2 - Rx ring done interrupt.
1311 */
1312 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1313 rt2x00pci_rxdone(rt2x00dev);
1314
1315 /*
1316 * 3 - Atim ring transmit done interrupt.
1317 */
1318 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1319 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1320
1321 /*
1322 * 4 - Priority ring transmit done interrupt.
1323 */
1324 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1325 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1326
1327 /*
1328 * 5 - Tx ring transmit done interrupt.
1329 */
1330 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1331 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627 1332
78e256c9
HS		 1333 /* Enable interrupts again. */
1334 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1335 STATE_RADIO_IRQ_ON_ISR);
95ea3627
ID		 1336 return IRQ_HANDLED;
1337}
1338
78e256c9
HS		 1339static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1340{
1341 struct rt2x00_dev *rt2x00dev = dev_instance;
1342 u32 reg;
1343
1344 /*
1345 * Get the interrupt sources & saved to local variable.
1346 * Write register value back to clear pending interrupts.
1347 */
1348 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1349 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1350
1351 if (!reg)
1352 return IRQ_NONE;
1353
1354 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1355 return IRQ_HANDLED;
1356
1357 /* Store irqvalues for use in the interrupt thread. */
1358 rt2x00dev->irqvalue[0] = reg;
1359
1360 /* Disable interrupts, will be enabled again in the interrupt thread. */
1361 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1362 STATE_RADIO_IRQ_OFF_ISR);
1363
1364 return IRQ_WAKE_THREAD;
1365}
1366
95ea3627
ID		 1367/*
1368 * Device probe functions.
1369 */
1370static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1371{
1372 struct eeprom_93cx6 eeprom;
1373 u32 reg;
1374 u16 word;
1375 u8 *mac;
1376
1377 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1378
1379 eeprom.data = rt2x00dev;
1380 eeprom.register_read = rt2400pci_eepromregister_read;
1381 eeprom.register_write = rt2400pci_eepromregister_write;
1382 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1383 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1384 eeprom.reg_data_in = 0;
1385 eeprom.reg_data_out = 0;
1386 eeprom.reg_data_clock = 0;
1387 eeprom.reg_chip_select = 0;
1388
1389 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1390 EEPROM_SIZE / sizeof(u16));
1391
1392 /*
1393 * Start validation of the data that has been read.
1394 */
1395 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1396 if (!is_valid_ether_addr(mac)) {
1397 random_ether_addr(mac);
e174961c 1398 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1399 }
1400
1401 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1402 if (word == 0xffff) {
1403 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1404 return -EINVAL;
1405 }
1406
1407 return 0;
1408}
1409
1410static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1411{
1412 u32 reg;
1413 u16 value;
1414 u16 eeprom;
1415
1416 /*
1417 * Read EEPROM word for configuration.
1418 */
1419 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1420
1421 /*
1422 * Identify RF chipset.
1423 */
1424 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1425 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1426 rt2x00_set_chip(rt2x00dev, RT2460, value,
1427 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1428
5122d898 1429 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1430 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1431 return -ENODEV;
1432 }
1433
1434 /*
1435 * Identify default antenna configuration.
1436 */
addc81bd 1437 rt2x00dev->default_ant.tx =
95ea3627 1438 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1439 rt2x00dev->default_ant.rx =
95ea3627
ID		 1440 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1441
addc81bd
ID		 1442 /*
1443 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1444 * I am not 100% sure about this, but the legacy drivers do not
1445 * indicate antenna swapping in software is required when
1446 * diversity is enabled.
1447 */
1448 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1449 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1450 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1451 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1452
95ea3627
ID		 1453 /*
1454 * Store led mode, for correct led behaviour.
1455 */
771fd565 1456#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1457 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1458
475433be 1459 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1460 if (value == LED_MODE_TXRX_ACTIVITY ||
1461 value == LED_MODE_DEFAULT ||
1462 value == LED_MODE_ASUS)
475433be
ID		 1463 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1464 LED_TYPE_ACTIVITY);
771fd565 1465#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1466
1467 /*
1468 * Detect if this device has an hardware controlled radio.
1469 */
1470 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1471 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1472
1473 /*
1474 * Check if the BBP tuning should be enabled.
1475 */
27df2a9c
ID		 1476 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1477 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 1478
1479 return 0;
1480}
1481
1482/*
1483 * RF value list for RF2420 & RF2421
1484 * Supports: 2.4 GHz
1485 */
8c5e7a5f 1486static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1487 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1488 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1489 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1490 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1491 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1492 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1493 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1494 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1495 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1496 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1497 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1498 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1499 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1500 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1501};
1502
8c5e7a5f 1503static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1504{
1505 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1506 struct channel_info *info;
1507 char *tx_power;
95ea3627
ID		 1508 unsigned int i;
1509
1510 /*
1511 * Initialize all hw fields.
1512 */
566bfe5a 1513 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1514 IEEE80211_HW_SIGNAL_DBM |
1515 IEEE80211_HW_SUPPORTS_PS |
1516 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1517
14a3bf89 1518 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1519 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1520 rt2x00_eeprom_addr(rt2x00dev,
1521 EEPROM_MAC_ADDR_0));
1522
95ea3627
ID		 1523 /*
1524 * Initialize hw_mode information.
1525 */
31562e80
ID		 1526 spec->supported_bands = SUPPORT_BAND_2GHZ;
1527 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1528
8c5e7a5f
ID		 1529 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1530 spec->channels = rf_vals_b;
1531
1532 /*
1533 * Create channel information array
1534 */
baeb2ffa 1535 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1536 if (!info)
1537 return -ENOMEM;
1538
1539 spec->channels_info = info;
1540
1541 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1542 for (i = 0; i < 14; i++) {
1543 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1544 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1545 }
8c5e7a5f
ID		 1546
1547 return 0;
95ea3627
ID		 1548}
1549
1550static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1551{
1552 int retval;
1553
1554 /*
1555 * Allocate eeprom data.
1556 */
1557 retval = rt2400pci_validate_eeprom(rt2x00dev);
1558 if (retval)
1559 return retval;
1560
1561 retval = rt2400pci_init_eeprom(rt2x00dev);
1562 if (retval)
1563 return retval;
1564
1565 /*
1566 * Initialize hw specifications.
1567 */
8c5e7a5f
ID		 1568 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1569 if (retval)
1570 return retval;
95ea3627
ID		 1571
1572 /*
c4da0048 1573 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1574 */
181d6902 1575 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1576 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1577
1578 /*
1579 * Set the rssi offset.
1580 */
1581 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1582
1583 return 0;
1584}
1585
1586/*
1587 * IEEE80211 stack callback functions.
1588 */
e100bb64 1589static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1590 const struct ieee80211_tx_queue_params *params)
1591{
1592 struct rt2x00_dev *rt2x00dev = hw->priv;
1593
1594 /*
1595 * We don't support variating cw_min and cw_max variables
1596 * per queue. So by default we only configure the TX queue,
1597 * and ignore all other configurations.
1598 */
e100bb64 1599 if (queue != 0)
95ea3627
ID		 1600 return -EINVAL;
1601
1602 if (rt2x00mac_conf_tx(hw, queue, params))
1603 return -EINVAL;
1604
1605 /*
1606 * Write configuration to register.
1607 */
181d6902
ID		 1608 rt2400pci_config_cw(rt2x00dev,
1609 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1610
1611 return 0;
1612}
1613
1614static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1615{
1616 struct rt2x00_dev *rt2x00dev = hw->priv;
1617 u64 tsf;
1618 u32 reg;
1619
1620 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1621 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1622 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1623 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1624
1625 return tsf;
1626}
1627
95ea3627
ID		 1628static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1629{
1630 struct rt2x00_dev *rt2x00dev = hw->priv;
1631 u32 reg;
1632
1633 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1634 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1635}
1636
1637static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1638 .tx = rt2x00mac_tx,
4150c572
JB		 1639 .start = rt2x00mac_start,
1640 .stop = rt2x00mac_stop,
95ea3627
ID		 1641 .add_interface = rt2x00mac_add_interface,
1642 .remove_interface = rt2x00mac_remove_interface,
1643 .config = rt2x00mac_config,
3a643d24 1644 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1645 .sw_scan_start = rt2x00mac_sw_scan_start,
1646 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1647 .get_stats = rt2x00mac_get_stats,
471b3efd 1648 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1649 .conf_tx = rt2400pci_conf_tx,
95ea3627 1650 .get_tsf = rt2400pci_get_tsf,
95ea3627 1651 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1652 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1653 .flush = rt2x00mac_flush,
95ea3627
ID		 1654};
1655
1656static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1657 .irq_handler = rt2400pci_interrupt,
78e256c9 1658 .irq_handler_thread = rt2400pci_interrupt_thread,
95ea3627
ID		 1659 .probe_hw = rt2400pci_probe_hw,
1660 .initialize = rt2x00pci_initialize,
1661 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1662 .get_entry_state = rt2400pci_get_entry_state,
1663 .clear_entry = rt2400pci_clear_entry,
95ea3627 1664 .set_device_state = rt2400pci_set_device_state,
95ea3627 1665 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1666 .link_stats = rt2400pci_link_stats,
1667 .reset_tuner = rt2400pci_reset_tuner,
1668 .link_tuner = rt2400pci_link_tuner,
dbba306f
ID		 1669 .start_queue = rt2400pci_start_queue,
1670 .kick_queue = rt2400pci_kick_queue,
1671 .stop_queue = rt2400pci_stop_queue,
95ea3627 1672 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1673 .write_beacon = rt2400pci_write_beacon,
95ea3627 1674 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1675 .config_filter = rt2400pci_config_filter,
6bb40dd1 1676 .config_intf = rt2400pci_config_intf,
72810379 1677 .config_erp = rt2400pci_config_erp,
e4ea1c40 1678 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1679 .config = rt2400pci_config,
1680};
1681
181d6902 1682static const struct data_queue_desc rt2400pci_queue_rx = {
efd2f271 1683 .entry_num = 24,
181d6902
ID		 1684 .data_size = DATA_FRAME_SIZE,
1685 .desc_size = RXD_DESC_SIZE,
b8be63ff 1686 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1687};
1688
1689static const struct data_queue_desc rt2400pci_queue_tx = {
efd2f271 1690 .entry_num = 24,
181d6902
ID		 1691 .data_size = DATA_FRAME_SIZE,
1692 .desc_size = TXD_DESC_SIZE,
b8be63ff 1693 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1694};
1695
1696static const struct data_queue_desc rt2400pci_queue_bcn = {
efd2f271 1697 .entry_num = 1,
181d6902
ID		 1698 .data_size = MGMT_FRAME_SIZE,
1699 .desc_size = TXD_DESC_SIZE,
b8be63ff 1700 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1701};
1702
1703static const struct data_queue_desc rt2400pci_queue_atim = {
efd2f271 1704 .entry_num = 8,
181d6902
ID		 1705 .data_size = DATA_FRAME_SIZE,
1706 .desc_size = TXD_DESC_SIZE,
b8be63ff 1707 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1708};
1709
95ea3627 1710static const struct rt2x00_ops rt2400pci_ops = {
04d0362e
GW		 1711 .name = KBUILD_MODNAME,
1712 .max_sta_intf = 1,
1713 .max_ap_intf = 1,
1714 .eeprom_size = EEPROM_SIZE,
1715 .rf_size = RF_SIZE,
1716 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1717 .extra_tx_headroom = 0,
04d0362e
GW		 1718 .rx = &rt2400pci_queue_rx,
1719 .tx = &rt2400pci_queue_tx,
1720 .bcn = &rt2400pci_queue_bcn,
1721 .atim = &rt2400pci_queue_atim,
1722 .lib = &rt2400pci_rt2x00_ops,
1723 .hw = &rt2400pci_mac80211_ops,
95ea3627 1724#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1725 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1726#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1727};
1728
1729/*
1730 * RT2400pci module information.
1731 */
a3aa1884 1732static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
95ea3627
ID		 1733 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1734 { 0, }
1735};
1736
1737MODULE_AUTHOR(DRV_PROJECT);
1738MODULE_VERSION(DRV_VERSION);
1739MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1740MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1741MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1742MODULE_LICENSE("GPL");
1743
1744static struct pci_driver rt2400pci_driver = {
2360157c 1745 .name = KBUILD_MODNAME,
95ea3627
ID		 1746 .id_table = rt2400pci_device_table,
1747 .probe = rt2x00pci_probe,
1748 .remove = __devexit_p(rt2x00pci_remove),
1749 .suspend = rt2x00pci_suspend,
1750 .resume = rt2x00pci_resume,
1751};
1752
1753static int __init rt2400pci_init(void)
1754{
1755 return pci_register_driver(&rt2400pci_driver);
1756}
1757
1758static void __exit rt2400pci_exit(void)
1759{
1760 pci_unregister_driver(&rt2400pci_driver);
1761}
1762
1763module_init(rt2400pci_init);
1764module_exit(rt2400pci_exit);
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