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rt2x00: TO_DS filter depends on intf_ap_count
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70
ID		 246#ifdef CONFIG_RT2400PCI_LEDS
247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
3a643d24
ID		 273static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
274 const unsigned int filter_flags)
275{
276 u32 reg;
277
278 /*
279 * Start configuration steps.
280 * Note that the version error will always be dropped
281 * since there is no filter for it at this time.
282 */
283 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
285 !(filter_flags & FIF_FCSFAIL));
286 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
287 !(filter_flags & FIF_PLCPFAIL));
288 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
289 !(filter_flags & FIF_CONTROL));
290 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
291 !(filter_flags & FIF_PROMISC_IN_BSS));
292 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 293 !(filter_flags & FIF_PROMISC_IN_BSS) &&
294 !rt2x00dev->intf_ap_count);
3a643d24
ID		 295 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
296 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
297}
298
6bb40dd1
ID		 299static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
300 struct rt2x00_intf *intf,
301 struct rt2x00intf_conf *conf,
302 const unsigned int flags)
95ea3627 303{
6bb40dd1
ID		 304 unsigned int bcn_preload;
305 u32 reg;
95ea3627 306
6bb40dd1 307 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 308 /*
309 * Enable beacon config
310 */
311 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
312 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
313 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
314 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 315
6bb40dd1
ID		 316 /*
317 * Enable synchronisation.
318 */
319 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 320 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 321 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 322 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 323 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
324 }
95ea3627 325
6bb40dd1
ID		 326 if (flags & CONFIG_UPDATE_MAC)
327 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
328 conf->mac, sizeof(conf->mac));
95ea3627 329
6bb40dd1
ID		 330 if (flags & CONFIG_UPDATE_BSSID)
331 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
332 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 333}
334
3a643d24
ID		 335static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
336 struct rt2x00lib_erp *erp)
95ea3627 337{
5c58ee51 338 int preamble_mask;
95ea3627 339 u32 reg;
95ea3627 340
5c58ee51
ID		 341 /*
342 * When short preamble is enabled, we should set bit 0x08
343 */
72810379 344 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 345
346 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 347 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
348 erp->ack_timeout);
349 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
350 erp->ack_consume_time);
95ea3627
ID		 351 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
352
95ea3627 353 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 354 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 355 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
357 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 360 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 361 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
363 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 366 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 367 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
369 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 372 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 373 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
375 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
376}
377
378static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 379 const int basic_rate_mask)
95ea3627 380{
5c58ee51 381 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 382}
383
384static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 385 struct rf_channel *rf)
95ea3627 386{
95ea3627
ID		 387 /*
388 * Switch on tuning bits.
389 */
5c58ee51
ID		 390 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
391 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 392
5c58ee51
ID		 393 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
394 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
395 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 396
397 /*
398 * RF2420 chipset don't need any additional actions.
399 */
400 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
401 return;
402
403 /*
404 * For the RT2421 chipsets we need to write an invalid
405 * reference clock rate to activate auto_tune.
406 * After that we set the value back to the correct channel.
407 */
5c58ee51 408 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 409 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 410 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 411
412 msleep(1);
413
5c58ee51
ID		 414 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
415 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
416 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 417
418 msleep(1);
419
420 /*
421 * Switch off tuning bits.
422 */
5c58ee51
ID		 423 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
424 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 425
5c58ee51
ID		 426 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
427 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 428
429 /*
430 * Clear false CRC during channel switch.
431 */
5c58ee51 432 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 433}
434
435static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
436{
437 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
438}
439
440static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 441 struct antenna_setup *ant)
95ea3627
ID		 442{
443 u8 r1;
444 u8 r4;
445
a4fe07d9
ID		 446 /*
447 * We should never come here because rt2x00lib is supposed
448 * to catch this and send us the correct antenna explicitely.
449 */
450 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
451 ant->tx == ANTENNA_SW_DIVERSITY);
452
95ea3627
ID		 453 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
454 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
455
456 /*
457 * Configure the TX antenna.
458 */
addc81bd 459 switch (ant->tx) {
95ea3627
ID		 460 case ANTENNA_HW_DIVERSITY:
461 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
462 break;
463 case ANTENNA_A:
464 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
465 break;
466 case ANTENNA_B:
a4fe07d9 467 default:
95ea3627
ID		 468 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
469 break;
470 }
471
472 /*
473 * Configure the RX antenna.
474 */
addc81bd 475 switch (ant->rx) {
95ea3627
ID		 476 case ANTENNA_HW_DIVERSITY:
477 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
478 break;
479 case ANTENNA_A:
480 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
481 break;
482 case ANTENNA_B:
a4fe07d9 483 default:
95ea3627
ID		 484 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
485 break;
486 }
487
488 rt2400pci_bbp_write(rt2x00dev, 4, r4);
489 rt2400pci_bbp_write(rt2x00dev, 1, r1);
490}
491
492static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 493 struct rt2x00lib_conf *libconf)
95ea3627
ID		 494{
495 u32 reg;
496
497 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 498 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 499 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
500
501 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 502 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
503 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 504 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
505
506 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 507 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
508 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 509 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
510
511 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
512 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
513 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
514 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
515
516 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 517 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
518 libconf->conf->beacon_int * 16);
519 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
520 libconf->conf->beacon_int * 16);
95ea3627
ID		 521 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
522}
523
524static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 525 struct rt2x00lib_conf *libconf,
526 const unsigned int flags)
95ea3627 527{
95ea3627 528 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 529 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 530 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 531 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 532 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 533 rt2400pci_config_txpower(rt2x00dev,
534 libconf->conf->power_level);
95ea3627 535 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 536 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 537 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 538 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 539}
540
541static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 542 const int cw_min, const int cw_max)
95ea3627
ID		 543{
544 u32 reg;
545
546 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 547 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
548 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 549 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
550}
551
95ea3627
ID		 552/*
553 * Link tuning
554 */
ebcf26da
ID		 555static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
556 struct link_qual *qual)
95ea3627
ID		 557{
558 u32 reg;
559 u8 bbp;
560
561 /*
562 * Update FCS error count from register.
563 */
564 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 565 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 566
567 /*
568 * Update False CCA count from register.
569 */
570 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 571 qual->false_cca = bbp;
95ea3627
ID		 572}
573
574static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
575{
576 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
577 rt2x00dev->link.vgc_level = 0x08;
578}
579
580static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
581{
582 u8 reg;
583
584 /*
585 * The link tuner should not run longer then 60 seconds,
586 * and should run once every 2 seconds.
587 */
588 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
589 return;
590
591 /*
592 * Base r13 link tuning on the false cca count.
593 */
594 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
595
ebcf26da 596 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 597 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
598 rt2x00dev->link.vgc_level = reg;
ebcf26da 599 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 600 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
601 rt2x00dev->link.vgc_level = reg;
602 }
603}
604
605/*
606 * Initialization functions.
607 */
837e7f24 608static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 609 struct queue_entry *entry)
95ea3627 610{
181d6902 611 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 612 u32 word;
613
181d6902 614 rt2x00_desc_read(priv_rx->desc, 2, &word);
30b3a23c
ID		 615 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
616 entry->queue->data_size);
181d6902 617 rt2x00_desc_write(priv_rx->desc, 2, word);
95ea3627 618
181d6902 619 rt2x00_desc_read(priv_rx->desc, 1, &word);
30b3a23c 620 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
181d6902 621 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 622
181d6902 623 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 624 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 625 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 626}
627
837e7f24 628static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 629 struct queue_entry *entry)
95ea3627 630{
181d6902 631 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 632 u32 word;
633
181d6902 634 rt2x00_desc_read(priv_tx->desc, 1, &word);
30b3a23c 635 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
181d6902 636 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 637
181d6902
ID		 638 rt2x00_desc_read(priv_tx->desc, 2, &word);
639 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
640 entry->queue->data_size);
641 rt2x00_desc_write(priv_tx->desc, 2, word);
95ea3627 642
181d6902 643 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 644 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
645 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 646 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 647}
648
181d6902 649static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 650{
181d6902
ID		 651 struct queue_entry_priv_pci_rx *priv_rx;
652 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 653 u32 reg;
654
95ea3627
ID		 655 /*
656 * Initialize registers.
657 */
658 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 659 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
660 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
661 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
662 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 663 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
664
181d6902 665 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 666 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c
ID		 667 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
668 priv_tx->desc_dma);
95ea3627
ID		 669 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
670
181d6902 671 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 672 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c
ID		 673 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
674 priv_tx->desc_dma);
95ea3627
ID		 675 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
676
181d6902 677 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 678 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c
ID		 679 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
680 priv_tx->desc_dma);
95ea3627
ID		 681 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
682
181d6902 683 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 684 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c
ID		 685 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
686 priv_tx->desc_dma);
95ea3627
ID		 687 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
688
689 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
690 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 691 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 692 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
693
181d6902 694 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 695 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
dac37d72 696 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
95ea3627
ID		 697 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
698
699 return 0;
700}
701
702static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
703{
704 u32 reg;
705
706 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
707 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
708 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
709 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
710
711 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
712 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
713 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
714 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
715 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
716
717 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
718 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
719 (rt2x00dev->rx->data_size / 128));
720 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
721
a9450b70
ID		 722 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
723 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
724 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
725 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
726
95ea3627
ID		 727 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
728
729 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
730 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
731 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
732 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
733 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
734 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
735
736 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
737 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
738 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
739 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
740 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
741 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
742 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
743 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
744
745 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
746
747 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
748 return -EBUSY;
749
750 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
751 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
752
753 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
754 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
755 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
756
757 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
758 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
759 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
760 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
761 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
762 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
763
764 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
765 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
766 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
767 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
768 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
769
770 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
771 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
772 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
773 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
774
775 /*
776 * We must clear the FCS and FIFO error count.
777 * These registers are cleared on read,
778 * so we may pass a useless variable to store the value.
779 */
780 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
781 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
782
783 return 0;
784}
785
786static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
787{
788 unsigned int i;
789 u16 eeprom;
790 u8 reg_id;
791 u8 value;
792
793 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
794 rt2400pci_bbp_read(rt2x00dev, 0, &value);
795 if ((value != 0xff) && (value != 0x00))
796 goto continue_csr_init;
797 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
798 udelay(REGISTER_BUSY_DELAY);
799 }
800
801 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
802 return -EACCES;
803
804continue_csr_init:
805 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
806 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
807 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
808 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
809 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
810 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
811 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
812 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
813 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
814 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
815 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
816 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
817 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
818 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
819
95ea3627
ID		 820 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
821 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
822
823 if (eeprom != 0xffff && eeprom != 0x0000) {
824 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
825 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 826 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
827 }
828 }
95ea3627
ID		 829
830 return 0;
831}
832
833/*
834 * Device state switch handlers.
835 */
836static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
837 enum dev_state state)
838{
839 u32 reg;
840
841 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
842 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
843 state == STATE_RADIO_RX_OFF);
844 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
845}
846
847static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
848 enum dev_state state)
849{
850 int mask = (state == STATE_RADIO_IRQ_OFF);
851 u32 reg;
852
853 /*
854 * When interrupts are being enabled, the interrupt registers
855 * should clear the register to assure a clean state.
856 */
857 if (state == STATE_RADIO_IRQ_ON) {
858 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
859 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
860 }
861
862 /*
863 * Only toggle the interrupts bits we are going to use.
864 * Non-checked interrupt bits are disabled by default.
865 */
866 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
867 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
868 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
869 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
870 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
871 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
872 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
873}
874
875static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
876{
877 /*
878 * Initialize all registers.
879 */
181d6902 880 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 881 rt2400pci_init_registers(rt2x00dev) ||
882 rt2400pci_init_bbp(rt2x00dev)) {
883 ERROR(rt2x00dev, "Register initialization failed.\n");
884 return -EIO;
885 }
886
887 /*
888 * Enable interrupts.
889 */
890 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
891
95ea3627
ID		 892 return 0;
893}
894
895static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
896{
897 u32 reg;
898
95ea3627
ID		 899 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
900
901 /*
902 * Disable synchronisation.
903 */
904 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
905
906 /*
907 * Cancel RX and TX.
908 */
909 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
910 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
911 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
912
913 /*
914 * Disable interrupts.
915 */
916 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
917}
918
919static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
920 enum dev_state state)
921{
922 u32 reg;
923 unsigned int i;
924 char put_to_sleep;
925 char bbp_state;
926 char rf_state;
927
928 put_to_sleep = (state != STATE_AWAKE);
929
930 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
931 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
932 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
933 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
934 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
935 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
936
937 /*
938 * Device is not guaranteed to be in the requested state yet.
939 * We must wait until the register indicates that the
940 * device has entered the correct state.
941 */
942 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
943 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
944 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
945 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
946 if (bbp_state == state && rf_state == state)
947 return 0;
948 msleep(10);
949 }
950
951 NOTICE(rt2x00dev, "Device failed to enter state %d, "
952 "current device state: bbp %d and rf %d.\n",
953 state, bbp_state, rf_state);
954
955 return -EBUSY;
956}
957
958static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
959 enum dev_state state)
960{
961 int retval = 0;
962
963 switch (state) {
964 case STATE_RADIO_ON:
965 retval = rt2400pci_enable_radio(rt2x00dev);
966 break;
967 case STATE_RADIO_OFF:
968 rt2400pci_disable_radio(rt2x00dev);
969 break;
970 case STATE_RADIO_RX_ON:
61667d8d
ID		 971 case STATE_RADIO_RX_ON_LINK:
972 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
973 break;
95ea3627 974 case STATE_RADIO_RX_OFF:
61667d8d
ID		 975 case STATE_RADIO_RX_OFF_LINK:
976 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 977 break;
978 case STATE_DEEP_SLEEP:
979 case STATE_SLEEP:
980 case STATE_STANDBY:
981 case STATE_AWAKE:
982 retval = rt2400pci_set_state(rt2x00dev, state);
983 break;
984 default:
985 retval = -ENOTSUPP;
986 break;
987 }
988
989 return retval;
990}
991
992/*
993 * TX descriptor initialization
994 */
995static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 996 struct sk_buff *skb,
181d6902 997 struct txentry_desc *txdesc,
95ea3627
ID		 998 struct ieee80211_tx_control *control)
999{
181d6902 1000 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1001 __le32 *txd = skbdesc->desc;
95ea3627 1002 u32 word;
95ea3627
ID		 1003
1004 /*
1005 * Start writing the descriptor words.
1006 */
1007 rt2x00_desc_read(txd, 2, &word);
dd3193e1 1008 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1009 rt2x00_desc_write(txd, 2, word);
1010
1011 rt2x00_desc_read(txd, 3, &word);
181d6902 1012 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1013 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1014 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1015 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1016 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1017 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1018 rt2x00_desc_write(txd, 3, word);
1019
1020 rt2x00_desc_read(txd, 4, &word);
181d6902 1021 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1022 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1023 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1024 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1025 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1026 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1027 rt2x00_desc_write(txd, 4, word);
1028
1029 rt2x00_desc_read(txd, 0, &word);
1030 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1031 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1032 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1033 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1034 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1035 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1036 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1037 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1038 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1039 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1040 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1041 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1042 !!(control->flags &
1043 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1044 rt2x00_desc_write(txd, 0, word);
1045}
1046
1047/*
1048 * TX data initialization
1049 */
1050static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1051 const unsigned int queue)
95ea3627
ID		 1052{
1053 u32 reg;
1054
5957da4c 1055 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1056 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1057 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1058 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1059 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1060 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1061 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1062 }
1063 return;
1064 }
1065
1066 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1067 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1068 (queue == IEEE80211_TX_QUEUE_DATA0));
1069 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1070 (queue == IEEE80211_TX_QUEUE_DATA1));
1071 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1072 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1073 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1074}
1075
1076/*
1077 * RX control handlers
1078 */
181d6902
ID		 1079static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1080 struct rxdone_entry_desc *rxdesc)
95ea3627 1081{
181d6902 1082 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1083 u32 word0;
1084 u32 word2;
89993890 1085 u32 word3;
95ea3627 1086
181d6902
ID		 1087 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1088 rt2x00_desc_read(priv_rx->desc, 2, &word2);
89993890 1089 rt2x00_desc_read(priv_rx->desc, 3, &word3);
95ea3627 1090
181d6902 1091 rxdesc->flags = 0;
4150c572 1092 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1093 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1094 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1095 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1096
1097 /*
1098 * Obtain the status about this packet.
8ed09854
ID		 1099 * The signal is the PLCP value, and needs to be stripped
1100 * of the preamble bit (0x08).
95ea3627 1101 */
8ed09854 1102 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1103 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1104 entry->queue->rt2x00dev->rssi_offset;
181d6902 1105 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02
ID		 1106
1107 rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;
1108 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1109 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1110}
1111
1112/*
1113 * Interrupt functions.
1114 */
181d6902
ID		 1115static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1116 const enum ieee80211_tx_queue queue_idx)
95ea3627 1117{
181d6902
ID		 1118 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1119 struct queue_entry_priv_pci_tx *priv_tx;
1120 struct queue_entry *entry;
1121 struct txdone_entry_desc txdesc;
95ea3627 1122 u32 word;
95ea3627 1123
181d6902
ID		 1124 while (!rt2x00queue_empty(queue)) {
1125 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1126 priv_tx = entry->priv_data;
1127 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1128
1129 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1130 !rt2x00_get_field32(word, TXD_W0_VALID))
1131 break;
1132
1133 /*
1134 * Obtain the status about this packet.
1135 */
181d6902
ID		 1136 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1137 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1138
181d6902 1139 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1140 }
95ea3627
ID		 1141}
1142
1143static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1144{
1145 struct rt2x00_dev *rt2x00dev = dev_instance;
1146 u32 reg;
1147
1148 /*
1149 * Get the interrupt sources & saved to local variable.
1150 * Write register value back to clear pending interrupts.
1151 */
1152 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1153 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1154
1155 if (!reg)
1156 return IRQ_NONE;
1157
1158 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1159 return IRQ_HANDLED;
1160
1161 /*
1162 * Handle interrupts, walk through all bits
1163 * and run the tasks, the bits are checked in order of
1164 * priority.
1165 */
1166
1167 /*
1168 * 1 - Beacon timer expired interrupt.
1169 */
1170 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1171 rt2x00lib_beacondone(rt2x00dev);
1172
1173 /*
1174 * 2 - Rx ring done interrupt.
1175 */
1176 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1177 rt2x00pci_rxdone(rt2x00dev);
1178
1179 /*
1180 * 3 - Atim ring transmit done interrupt.
1181 */
1182 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1183 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1184
1185 /*
1186 * 4 - Priority ring transmit done interrupt.
1187 */
1188 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1189 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1190
1191 /*
1192 * 5 - Tx ring transmit done interrupt.
1193 */
1194 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1195 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1196
1197 return IRQ_HANDLED;
1198}
1199
1200/*
1201 * Device probe functions.
1202 */
1203static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1204{
1205 struct eeprom_93cx6 eeprom;
1206 u32 reg;
1207 u16 word;
1208 u8 *mac;
1209
1210 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1211
1212 eeprom.data = rt2x00dev;
1213 eeprom.register_read = rt2400pci_eepromregister_read;
1214 eeprom.register_write = rt2400pci_eepromregister_write;
1215 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1216 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1217 eeprom.reg_data_in = 0;
1218 eeprom.reg_data_out = 0;
1219 eeprom.reg_data_clock = 0;
1220 eeprom.reg_chip_select = 0;
1221
1222 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1223 EEPROM_SIZE / sizeof(u16));
1224
1225 /*
1226 * Start validation of the data that has been read.
1227 */
1228 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1229 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1230 DECLARE_MAC_BUF(macbuf);
1231
95ea3627 1232 random_ether_addr(mac);
0795af57 1233 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1234 }
1235
1236 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1237 if (word == 0xffff) {
1238 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1239 return -EINVAL;
1240 }
1241
1242 return 0;
1243}
1244
1245static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1246{
1247 u32 reg;
1248 u16 value;
1249 u16 eeprom;
1250
1251 /*
1252 * Read EEPROM word for configuration.
1253 */
1254 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1255
1256 /*
1257 * Identify RF chipset.
1258 */
1259 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1260 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1261 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1262
1263 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1264 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1265 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1266 return -ENODEV;
1267 }
1268
1269 /*
1270 * Identify default antenna configuration.
1271 */
addc81bd 1272 rt2x00dev->default_ant.tx =
95ea3627 1273 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1274 rt2x00dev->default_ant.rx =
95ea3627
ID		 1275 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1276
addc81bd
ID		 1277 /*
1278 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1279 * I am not 100% sure about this, but the legacy drivers do not
1280 * indicate antenna swapping in software is required when
1281 * diversity is enabled.
1282 */
1283 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1284 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1285 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1286 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1287
95ea3627
ID		 1288 /*
1289 * Store led mode, for correct led behaviour.
1290 */
a9450b70
ID		 1291#ifdef CONFIG_RT2400PCI_LEDS
1292 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1293
1294 switch (value) {
1295 case LED_MODE_ASUS:
1296 case LED_MODE_ALPHA:
1297 case LED_MODE_DEFAULT:
1298 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1299 break;
1300 case LED_MODE_TXRX_ACTIVITY:
1301 rt2x00dev->led_flags =
1302 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1303 break;
1304 case LED_MODE_SIGNAL_STRENGTH:
1305 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1306 break;
1307 }
1308#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1309
1310 /*
1311 * Detect if this device has an hardware controlled radio.
1312 */
81873e9c 1313#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1314 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1315 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1316#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1317
1318 /*
1319 * Check if the BBP tuning should be enabled.
1320 */
1321 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1322 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1323
1324 return 0;
1325}
1326
1327/*
1328 * RF value list for RF2420 & RF2421
1329 * Supports: 2.4 GHz
1330 */
1331static const struct rf_channel rf_vals_bg[] = {
1332 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1333 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1334 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1335 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1336 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1337 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1338 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1339 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1340 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1341 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1342 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1343 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1344 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1345 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1346};
1347
1348static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1349{
1350 struct hw_mode_spec *spec = &rt2x00dev->spec;
1351 u8 *txpower;
1352 unsigned int i;
1353
1354 /*
1355 * Initialize all hw fields.
1356 */
4150c572 1357 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1358 rt2x00dev->hw->extra_tx_headroom = 0;
1359 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1360 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1361 rt2x00dev->hw->queues = 2;
1362
1363 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1364 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1365 rt2x00_eeprom_addr(rt2x00dev,
1366 EEPROM_MAC_ADDR_0));
1367
1368 /*
1369 * Convert tx_power array in eeprom.
1370 */
1371 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1372 for (i = 0; i < 14; i++)
1373 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1374
1375 /*
1376 * Initialize hw_mode information.
1377 */
31562e80
ID		 1378 spec->supported_bands = SUPPORT_BAND_2GHZ;
1379 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627
ID		 1380 spec->tx_power_a = NULL;
1381 spec->tx_power_bg = txpower;
1382 spec->tx_power_default = DEFAULT_TXPOWER;
1383
1384 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1385 spec->channels = rf_vals_bg;
1386}
1387
1388static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1389{
1390 int retval;
1391
1392 /*
1393 * Allocate eeprom data.
1394 */
1395 retval = rt2400pci_validate_eeprom(rt2x00dev);
1396 if (retval)
1397 return retval;
1398
1399 retval = rt2400pci_init_eeprom(rt2x00dev);
1400 if (retval)
1401 return retval;
1402
1403 /*
1404 * Initialize hw specifications.
1405 */
1406 rt2400pci_probe_hw_mode(rt2x00dev);
1407
1408 /*
181d6902 1409 * This device requires the atim queue
95ea3627 1410 */
181d6902 1411 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1412
1413 /*
1414 * Set the rssi offset.
1415 */
1416 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1417
1418 return 0;
1419}
1420
1421/*
1422 * IEEE80211 stack callback functions.
1423 */
1424static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1425 u32 short_retry, u32 long_retry)
1426{
1427 struct rt2x00_dev *rt2x00dev = hw->priv;
1428 u32 reg;
1429
1430 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1431 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1432 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1433 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1434
1435 return 0;
1436}
1437
1438static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1439 int queue,
1440 const struct ieee80211_tx_queue_params *params)
1441{
1442 struct rt2x00_dev *rt2x00dev = hw->priv;
1443
1444 /*
1445 * We don't support variating cw_min and cw_max variables
1446 * per queue. So by default we only configure the TX queue,
1447 * and ignore all other configurations.
1448 */
1449 if (queue != IEEE80211_TX_QUEUE_DATA0)
1450 return -EINVAL;
1451
1452 if (rt2x00mac_conf_tx(hw, queue, params))
1453 return -EINVAL;
1454
1455 /*
1456 * Write configuration to register.
1457 */
181d6902
ID		 1458 rt2400pci_config_cw(rt2x00dev,
1459 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1460
1461 return 0;
1462}
1463
1464static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1465{
1466 struct rt2x00_dev *rt2x00dev = hw->priv;
1467 u64 tsf;
1468 u32 reg;
1469
1470 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1471 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1472 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1473 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1474
1475 return tsf;
1476}
1477
5957da4c
ID		 1478static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1479 struct ieee80211_tx_control *control)
1480{
1481 struct rt2x00_dev *rt2x00dev = hw->priv;
1482 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1483 struct queue_entry_priv_pci_tx *priv_tx;
1484 struct skb_frame_desc *skbdesc;
8af244cc 1485 u32 reg;
5957da4c
ID		 1486
1487 if (unlikely(!intf->beacon))
1488 return -ENOBUFS;
5957da4c
ID		 1489 priv_tx = intf->beacon->priv_data;
1490
1491 /*
1492 * Fill in skb descriptor
1493 */
1494 skbdesc = get_skb_frame_desc(skb);
1495 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1496 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1497 skbdesc->data = skb->data;
1498 skbdesc->data_len = skb->len;
1499 skbdesc->desc = priv_tx->desc;
1500 skbdesc->desc_len = intf->beacon->queue->desc_size;
1501 skbdesc->entry = intf->beacon;
1502
8af244cc
ID		 1503 /*
1504 * Disable beaconing while we are reloading the beacon data,
1505 * otherwise we might be sending out invalid data.
1506 */
1507 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1508 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1509 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1510 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1511 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1512
5957da4c
ID		 1513 /*
1514 * mac80211 doesn't provide the control->queue variable
1515 * for beacons. Set our own queue identification so
1516 * it can be used during descriptor initialization.
1517 */
1518 control->queue = RT2X00_BCN_QUEUE_BEACON;
1519 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1520
1521 /*
1522 * Enable beacon generation.
1523 * Write entire beacon with descriptor to register,
1524 * and kick the beacon generator.
1525 */
1526 memcpy(priv_tx->data, skb->data, skb->len);
1527 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1528
1529 return 0;
1530}
1531
95ea3627
ID		 1532static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1533{
1534 struct rt2x00_dev *rt2x00dev = hw->priv;
1535 u32 reg;
1536
1537 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1538 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1539}
1540
1541static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1542 .tx = rt2x00mac_tx,
4150c572
JB		 1543 .start = rt2x00mac_start,
1544 .stop = rt2x00mac_stop,
95ea3627
ID		 1545 .add_interface = rt2x00mac_add_interface,
1546 .remove_interface = rt2x00mac_remove_interface,
1547 .config = rt2x00mac_config,
1548 .config_interface = rt2x00mac_config_interface,
3a643d24 1549 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1550 .get_stats = rt2x00mac_get_stats,
1551 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1552 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1553 .conf_tx = rt2400pci_conf_tx,
1554 .get_tx_stats = rt2x00mac_get_tx_stats,
1555 .get_tsf = rt2400pci_get_tsf,
5957da4c 1556 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1557 .tx_last_beacon = rt2400pci_tx_last_beacon,
1558};
1559
1560static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1561 .irq_handler = rt2400pci_interrupt,
1562 .probe_hw = rt2400pci_probe_hw,
1563 .initialize = rt2x00pci_initialize,
1564 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1565 .init_rxentry = rt2400pci_init_rxentry,
1566 .init_txentry = rt2400pci_init_txentry,
95ea3627 1567 .set_device_state = rt2400pci_set_device_state,
95ea3627 1568 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1569 .link_stats = rt2400pci_link_stats,
1570 .reset_tuner = rt2400pci_reset_tuner,
1571 .link_tuner = rt2400pci_link_tuner,
a9450b70 1572 .led_brightness = rt2400pci_led_brightness,
95ea3627
ID		 1573 .write_tx_desc = rt2400pci_write_tx_desc,
1574 .write_tx_data = rt2x00pci_write_tx_data,
1575 .kick_tx_queue = rt2400pci_kick_tx_queue,
1576 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1577 .config_filter = rt2400pci_config_filter,
6bb40dd1 1578 .config_intf = rt2400pci_config_intf,
72810379 1579 .config_erp = rt2400pci_config_erp,
95ea3627
ID		 1580 .config = rt2400pci_config,
1581};
1582
181d6902
ID		 1583static const struct data_queue_desc rt2400pci_queue_rx = {
1584 .entry_num = RX_ENTRIES,
1585 .data_size = DATA_FRAME_SIZE,
1586 .desc_size = RXD_DESC_SIZE,
1587 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1588};
1589
1590static const struct data_queue_desc rt2400pci_queue_tx = {
1591 .entry_num = TX_ENTRIES,
1592 .data_size = DATA_FRAME_SIZE,
1593 .desc_size = TXD_DESC_SIZE,
1594 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1595};
1596
1597static const struct data_queue_desc rt2400pci_queue_bcn = {
1598 .entry_num = BEACON_ENTRIES,
1599 .data_size = MGMT_FRAME_SIZE,
1600 .desc_size = TXD_DESC_SIZE,
1601 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1602};
1603
1604static const struct data_queue_desc rt2400pci_queue_atim = {
1605 .entry_num = ATIM_ENTRIES,
1606 .data_size = DATA_FRAME_SIZE,
1607 .desc_size = TXD_DESC_SIZE,
1608 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1609};
1610
95ea3627 1611static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1612 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1613 .max_sta_intf = 1,
1614 .max_ap_intf = 1,
95ea3627
ID		 1615 .eeprom_size = EEPROM_SIZE,
1616 .rf_size = RF_SIZE,
181d6902
ID		 1617 .rx = &rt2400pci_queue_rx,
1618 .tx = &rt2400pci_queue_tx,
1619 .bcn = &rt2400pci_queue_bcn,
1620 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1621 .lib = &rt2400pci_rt2x00_ops,
1622 .hw = &rt2400pci_mac80211_ops,
1623#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1624 .debugfs = &rt2400pci_rt2x00debug,
1625#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1626};
1627
1628/*
1629 * RT2400pci module information.
1630 */
1631static struct pci_device_id rt2400pci_device_table[] = {
1632 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1633 { 0, }
1634};
1635
1636MODULE_AUTHOR(DRV_PROJECT);
1637MODULE_VERSION(DRV_VERSION);
1638MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1639MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1640MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1641MODULE_LICENSE("GPL");
1642
1643static struct pci_driver rt2400pci_driver = {
2360157c 1644 .name = KBUILD_MODNAME,
95ea3627
ID		 1645 .id_table = rt2400pci_device_table,
1646 .probe = rt2x00pci_probe,
1647 .remove = __devexit_p(rt2x00pci_remove),
1648 .suspend = rt2x00pci_suspend,
1649 .resume = rt2x00pci_resume,
1650};
1651
1652static int __init rt2400pci_init(void)
1653{
1654 return pci_register_driver(&rt2400pci_driver);
1655}
1656
1657static void __exit rt2400pci_exit(void)
1658{
1659 pci_unregister_driver(&rt2400pci_driver);
1660}
1661
1662module_init(rt2400pci_init);
1663module_exit(rt2400pci_exit);
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