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ath9k_htc: fix build error when ATH9K_HTC_DEBUGFS not enabled
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt2400pci.h"
39
40/*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
c9c3b1a5
ID		 53#define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55#define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 57
0e14f6d3 58static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 59 const unsigned int word, const u8 value)
60{
61 u32 reg;
62
8ff48a8b
ID		 63 mutex_lock(&rt2x00dev->csr_mutex);
64
95ea3627 65 /*
c9c3b1a5
ID		 66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
95ea3627 68 */
c9c3b1a5
ID		 69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
8ff48a8b 78
8ff48a8b 79 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 80}
81
0e14f6d3 82static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int word, u8 *value)
84{
85 u32 reg;
86
8ff48a8b
ID		 87 mutex_lock(&rt2x00dev->csr_mutex);
88
95ea3627 89 /*
c9c3b1a5
ID		 90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
95ea3627 96 */
c9c3b1a5
ID		 97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 102
c9c3b1a5 103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 104
c9c3b1a5
ID		 105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
95ea3627
ID		 107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 109
110 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 111}
112
0e14f6d3 113static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int word, const u32 value)
115{
116 u32 reg;
95ea3627 117
8ff48a8b
ID		 118 mutex_lock(&rt2x00dev->csr_mutex);
119
c9c3b1a5
ID		 120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 133 }
134
8ff48a8b 135 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 136}
137
138static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139{
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151}
152
153static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154{
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166}
167
168#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 169static const struct rt2x00debug rt2400pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
743b97ca
ID		 172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
95ea3627
ID		 176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
743b97ca 182 .word_base = EEPROM_BASE,
95ea3627
ID		 183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2400pci_bbp_read,
188 .write = rt2400pci_bbp_write,
743b97ca 189 .word_base = BBP_BASE,
95ea3627
ID		 190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2400pci_rf_write,
743b97ca 196 .word_base = RF_BASE,
95ea3627
ID		 197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200};
201#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
95ea3627
ID		 203static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204{
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209}
95ea3627 210
771fd565 211#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 212static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 213 enum led_brightness brightness)
214{
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
a2e1d52a 222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228}
a2e1d52a
ID		 229
230static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244}
475433be
ID		 245
246static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2400pci_brightness_set;
253 led->led_dev.blink_set = rt2400pci_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
3a643d24
ID		 261static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263{
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * since there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285}
286
6bb40dd1
ID		 287static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
95ea3627 291{
6bb40dd1
ID		 292 unsigned int bcn_preload;
293 u32 reg;
95ea3627 294
6bb40dd1 295 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 296 /*
297 * Enable beacon config
298 */
bad13639 299 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 303
6bb40dd1
ID		 304 /*
305 * Enable synchronisation.
306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 308 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 310 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 311 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312 }
95ea3627 313
6bb40dd1
ID		 314 if (flags & CONFIG_UPDATE_MAC)
315 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
316 conf->mac, sizeof(conf->mac));
95ea3627 317
6bb40dd1
ID		 318 if (flags & CONFIG_UPDATE_BSSID)
319 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
320 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 321}
322
3a643d24
ID		 323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00lib_erp *erp)
95ea3627 325{
5c58ee51 326 int preamble_mask;
95ea3627 327 u32 reg;
95ea3627 328
5c58ee51
ID		 329 /*
330 * When short preamble is enabled, we should set bit 0x08
331 */
72810379 332 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 333
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
8a566afe
ID		 337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
95ea3627 341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 344 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 345 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
346
347 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 348 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 349 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 351 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 354 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 355 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 357 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 360 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 361 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 363 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 364
365 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
366
367 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
368 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
369 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
370
8a566afe
ID		 371 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
372 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
373 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
374 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
375
e4ea1c40
ID		 376 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
377 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
378 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
379 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
380
381 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
382 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
383 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
384 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 385}
386
e4ea1c40
ID		 387static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
388 struct antenna_setup *ant)
95ea3627 389{
e4ea1c40
ID		 390 u8 r1;
391 u8 r4;
392
393 /*
394 * We should never come here because rt2x00lib is supposed
395 * to catch this and send us the correct antenna explicitely.
396 */
397 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
398 ant->tx == ANTENNA_SW_DIVERSITY);
399
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402
403 /*
404 * Configure the TX antenna.
405 */
406 switch (ant->tx) {
407 case ANTENNA_HW_DIVERSITY:
408 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
409 break;
410 case ANTENNA_A:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412 break;
413 case ANTENNA_B:
414 default:
415 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
416 break;
417 }
418
419 /*
420 * Configure the RX antenna.
421 */
422 switch (ant->rx) {
423 case ANTENNA_HW_DIVERSITY:
424 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
425 break;
426 case ANTENNA_A:
427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
428 break;
429 case ANTENNA_B:
430 default:
431 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
432 break;
433 }
434
435 rt2400pci_bbp_write(rt2x00dev, 4, r4);
436 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 437}
438
439static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 440 struct rf_channel *rf)
95ea3627 441{
95ea3627
ID		 442 /*
443 * Switch on tuning bits.
444 */
5c58ee51
ID		 445 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
446 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 447
5c58ee51
ID		 448 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
449 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
450 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 451
452 /*
453 * RF2420 chipset don't need any additional actions.
454 */
5122d898 455 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 456 return;
457
458 /*
459 * For the RT2421 chipsets we need to write an invalid
460 * reference clock rate to activate auto_tune.
461 * After that we set the value back to the correct channel.
462 */
5c58ee51 463 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 464 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 465 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 466
467 msleep(1);
468
5c58ee51
ID		 469 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
470 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
471 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 472
473 msleep(1);
474
475 /*
476 * Switch off tuning bits.
477 */
5c58ee51
ID		 478 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
479 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 480
5c58ee51
ID		 481 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 483
484 /*
485 * Clear false CRC during channel switch.
486 */
5c58ee51 487 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 488}
489
490static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
491{
492 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
493}
494
e4ea1c40
ID		 495static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
496 struct rt2x00lib_conf *libconf)
95ea3627 497{
e4ea1c40 498 u32 reg;
95ea3627 499
e4ea1c40
ID		 500 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
501 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
502 libconf->conf->long_frame_max_tx_count);
503 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
504 libconf->conf->short_frame_max_tx_count);
505 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 506}
507
7d7f19cc
ID		 508static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
509 struct rt2x00lib_conf *libconf)
510{
511 enum dev_state state =
512 (libconf->conf->flags & IEEE80211_CONF_PS) ?
513 STATE_SLEEP : STATE_AWAKE;
514 u32 reg;
515
516 if (state == STATE_SLEEP) {
517 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
518 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 519 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 520 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
521 libconf->conf->listen_interval - 1);
522
523 /* We must first disable autowake before it can be enabled */
524 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
525 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
526
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 529 } else {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 533 }
534
535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
536}
537
95ea3627 538static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 539 struct rt2x00lib_conf *libconf,
540 const unsigned int flags)
95ea3627 541{
e4ea1c40 542 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 544 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 545 rt2400pci_config_txpower(rt2x00dev,
546 libconf->conf->power_level);
e4ea1c40
ID		 547 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
548 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 549 if (flags & IEEE80211_CONF_CHANGE_PS)
550 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 551}
552
553static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 554 const int cw_min, const int cw_max)
95ea3627
ID		 555{
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 559 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562}
563
95ea3627
ID		 564/*
565 * Link tuning
566 */
ebcf26da
ID		 567static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568 struct link_qual *qual)
95ea3627
ID		 569{
570 u32 reg;
571 u8 bbp;
572
573 /*
574 * Update FCS error count from register.
575 */
576 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 577 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 578
579 /*
580 * Update False CCA count from register.
581 */
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 583 qual->false_cca = bbp;
95ea3627
ID		 584}
585
5352ff65
ID		 586static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
587 struct link_qual *qual, u8 vgc_level)
eb20b4e8
ID		 588{
589 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
5352ff65
ID		 590 qual->vgc_level = vgc_level;
591 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 592}
593
5352ff65
ID		 594static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
595 struct link_qual *qual)
95ea3627 596{
5352ff65 597 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 598}
599
5352ff65
ID		 600static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
601 struct link_qual *qual, const u32 count)
95ea3627 602{
95ea3627
ID		 603 /*
604 * The link tuner should not run longer then 60 seconds,
605 * and should run once every 2 seconds.
606 */
5352ff65 607 if (count > 60 || !(count & 1))
95ea3627
ID		 608 return;
609
610 /*
611 * Base r13 link tuning on the false cca count.
612 */
5352ff65
ID		 613 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
614 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
615 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
616 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 617}
618
619/*
620 * Initialization functions.
621 */
798b7adb 622static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 623{
b8be63ff 624 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 625 u32 word;
626
798b7adb
ID		 627 if (entry->queue->qid == QID_RX) {
628 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 629
798b7adb
ID		 630 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
631 } else {
632 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 633
798b7adb
ID		 634 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
635 rt2x00_get_field32(word, TXD_W0_VALID));
636 }
95ea3627
ID		 637}
638
798b7adb 639static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 640{
b8be63ff 641 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 642 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 643 u32 word;
644
798b7adb
ID		 645 if (entry->queue->qid == QID_RX) {
646 rt2x00_desc_read(entry_priv->desc, 2, &word);
647 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
648 rt2x00_desc_write(entry_priv->desc, 2, word);
649
650 rt2x00_desc_read(entry_priv->desc, 1, &word);
651 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
652 rt2x00_desc_write(entry_priv->desc, 1, word);
653
654 rt2x00_desc_read(entry_priv->desc, 0, &word);
655 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
656 rt2x00_desc_write(entry_priv->desc, 0, word);
657 } else {
658 rt2x00_desc_read(entry_priv->desc, 0, &word);
659 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
660 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
661 rt2x00_desc_write(entry_priv->desc, 0, word);
662 }
95ea3627
ID		 663}
664
181d6902 665static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 666{
b8be63ff 667 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 668 u32 reg;
669
95ea3627
ID		 670 /*
671 * Initialize registers.
672 */
673 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 674 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
675 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
676 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
677 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 678 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
679
b8be63ff 680 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 681 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 682 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 683 entry_priv->desc_dma);
95ea3627
ID		 684 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
685
b8be63ff 686 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 687 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 688 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 689 entry_priv->desc_dma);
95ea3627
ID		 690 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
691
b8be63ff 692 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 693 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 694 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 695 entry_priv->desc_dma);
95ea3627
ID		 696 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
697
b8be63ff 698 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 699 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 700 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 701 entry_priv->desc_dma);
95ea3627
ID		 702 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
703
704 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
705 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 706 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 707 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
708
b8be63ff 709 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 710 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 711 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
712 entry_priv->desc_dma);
95ea3627
ID		 713 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
714
715 return 0;
716}
717
718static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
719{
720 u32 reg;
721
722 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
723 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
724 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
725 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
726
727 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
728 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
729 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
730 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
731 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
732
733 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
734 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
735 (rt2x00dev->rx->data_size / 128));
736 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
737
1f909162
ID		 738 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
739 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
740 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
741 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
742 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
743 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
744 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
745 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
746 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
747 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
748
95ea3627
ID		 749 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
750
751 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
752 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
753 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
754 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
755 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
756 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
757
758 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
759 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
760 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
761 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
762 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
763 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
764 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
765 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
766
767 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
768
769 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
770 return -EBUSY;
771
772 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
773 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
774
775 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
776 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
777 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
778
779 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
780 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
781 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
782 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
783 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
784 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
785
786 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
787 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
788 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
789 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
790 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
791
792 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
793 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
794 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
795 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
796
797 /*
798 * We must clear the FCS and FIFO error count.
799 * These registers are cleared on read,
800 * so we may pass a useless variable to store the value.
801 */
802 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
803 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
804
805 return 0;
806}
807
2b08da3f 808static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 809{
810 unsigned int i;
95ea3627
ID		 811 u8 value;
812
813 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
814 rt2400pci_bbp_read(rt2x00dev, 0, &value);
815 if ((value != 0xff) && (value != 0x00))
2b08da3f 816 return 0;
95ea3627
ID		 817 udelay(REGISTER_BUSY_DELAY);
818 }
819
820 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
821 return -EACCES;
2b08da3f
ID		 822}
823
824static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
825{
826 unsigned int i;
827 u16 eeprom;
828 u8 reg_id;
829 u8 value;
830
831 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
832 return -EACCES;
95ea3627 833
95ea3627
ID		 834 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
835 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
836 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
837 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
838 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
839 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
840 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
841 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
842 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
843 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
844 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
845 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
846 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
847 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
848
95ea3627
ID		 849 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
850 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
851
852 if (eeprom != 0xffff && eeprom != 0x0000) {
853 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
854 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 855 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
856 }
857 }
95ea3627
ID		 858
859 return 0;
860}
861
862/*
863 * Device state switch handlers.
864 */
865static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
866 enum dev_state state)
867{
868 u32 reg;
869
870 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
871 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 872 (state == STATE_RADIO_RX_OFF) ||
873 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 874 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
875}
876
877static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
878 enum dev_state state)
879{
880 int mask = (state == STATE_RADIO_IRQ_OFF);
881 u32 reg;
882
883 /*
884 * When interrupts are being enabled, the interrupt registers
885 * should clear the register to assure a clean state.
886 */
887 if (state == STATE_RADIO_IRQ_ON) {
888 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
889 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
890 }
891
892 /*
893 * Only toggle the interrupts bits we are going to use.
894 * Non-checked interrupt bits are disabled by default.
895 */
896 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
897 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
898 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
899 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
900 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
901 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
902 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
903}
904
905static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
906{
907 /*
908 * Initialize all registers.
909 */
2b08da3f
ID		 910 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
911 rt2400pci_init_registers(rt2x00dev) ||
912 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 913 return -EIO;
95ea3627 914
95ea3627
ID		 915 return 0;
916}
917
918static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
919{
95ea3627 920 /*
a2c9b652 921 * Disable power
95ea3627 922 */
a2c9b652 923 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 924}
925
926static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
927 enum dev_state state)
928{
9655a6ec 929 u32 reg, reg2;
95ea3627
ID		 930 unsigned int i;
931 char put_to_sleep;
932 char bbp_state;
933 char rf_state;
934
935 put_to_sleep = (state != STATE_AWAKE);
936
937 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
938 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
939 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
940 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
941 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
942 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
943
944 /*
945 * Device is not guaranteed to be in the requested state yet.
946 * We must wait until the register indicates that the
947 * device has entered the correct state.
948 */
949 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 950 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
951 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
952 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 953 if (bbp_state == state && rf_state == state)
954 return 0;
9655a6ec 955 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 956 msleep(10);
957 }
958
95ea3627
ID		 959 return -EBUSY;
960}
961
962static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
963 enum dev_state state)
964{
965 int retval = 0;
966
967 switch (state) {
968 case STATE_RADIO_ON:
969 retval = rt2400pci_enable_radio(rt2x00dev);
970 break;
971 case STATE_RADIO_OFF:
972 rt2400pci_disable_radio(rt2x00dev);
973 break;
974 case STATE_RADIO_RX_ON:
61667d8d 975 case STATE_RADIO_RX_ON_LINK:
95ea3627 976 case STATE_RADIO_RX_OFF:
61667d8d 977 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 978 rt2400pci_toggle_rx(rt2x00dev, state);
979 break;
980 case STATE_RADIO_IRQ_ON:
981 case STATE_RADIO_IRQ_OFF:
982 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 983 break;
984 case STATE_DEEP_SLEEP:
985 case STATE_SLEEP:
986 case STATE_STANDBY:
987 case STATE_AWAKE:
988 retval = rt2400pci_set_state(rt2x00dev, state);
989 break;
990 default:
991 retval = -ENOTSUPP;
992 break;
993 }
994
2b08da3f
ID		 995 if (unlikely(retval))
996 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
997 state, retval);
998
95ea3627
ID		 999 return retval;
1000}
1001
1002/*
1003 * TX descriptor initialization
1004 */
1005static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1006 struct sk_buff *skb,
61486e0f 1007 struct txentry_desc *txdesc)
95ea3627 1008{
181d6902 1009 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1010 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
85b7a8b3 1011 __le32 *txd = entry_priv->desc;
95ea3627 1012 u32 word;
95ea3627
ID		 1013
1014 /*
1015 * Start writing the descriptor words.
1016 */
85b7a8b3 1017 rt2x00_desc_read(txd, 1, &word);
c4da0048 1018 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1019 rt2x00_desc_write(txd, 1, word);
4de36fe5 1020
95ea3627 1021 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1022 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1023 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1024 rt2x00_desc_write(txd, 2, word);
1025
1026 rt2x00_desc_read(txd, 3, &word);
181d6902 1027 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1028 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1029 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1030 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1031 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1032 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1033 rt2x00_desc_write(txd, 3, word);
1034
1035 rt2x00_desc_read(txd, 4, &word);
181d6902 1036 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1037 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1038 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1039 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1040 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1041 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1042 rt2x00_desc_write(txd, 4, word);
1043
e01f1ec3
GW		 1044 /*
1045 * Writing TXD word 0 must the last to prevent a race condition with
1046 * the device, whereby the device may take hold of the TXD before we
1047 * finished updating it.
1048 */
95ea3627
ID		 1049 rt2x00_desc_read(txd, 0, &word);
1050 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1051 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1052 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1053 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1054 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1055 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1056 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1057 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1058 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1059 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1060 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1061 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1062 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1063 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1064
1065 /*
1066 * Register descriptor details in skb frame descriptor.
1067 */
1068 skbdesc->desc = txd;
1069 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1070}
1071
1072/*
1073 * TX data initialization
1074 */
f224f4ef
GW		 1075static void rt2400pci_write_beacon(struct queue_entry *entry,
1076 struct txentry_desc *txdesc)
bd88a781
ID		 1077{
1078 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1079 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1080 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1081 u32 word;
1082 u32 reg;
1083
1084 /*
1085 * Disable beaconing while we are reloading the beacon data,
1086 * otherwise we might be sending out invalid data.
1087 */
1088 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1089 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1090 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1091
bd88a781
ID		 1092 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1093
1094 rt2x00_desc_read(entry_priv->desc, 1, &word);
1095 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1096 rt2x00_desc_write(entry_priv->desc, 1, word);
d61cb266
GW		 1097
1098 /*
1099 * Enable beaconing again.
1100 */
1101 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1102 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1103 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1104 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1105}
1106
95ea3627 1107static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1108 const enum data_queue_qid queue)
95ea3627
ID		 1109{
1110 u32 reg;
1111
95ea3627 1112 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1113 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1114 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1115 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1116 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1117}
1118
a2c9b652
ID		 1119static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1120 const enum data_queue_qid qid)
1121{
1122 u32 reg;
1123
1124 if (qid == QID_BEACON) {
1125 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1126 } else {
1127 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1128 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1129 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1130 }
1131}
1132
95ea3627
ID		 1133/*
1134 * RX control handlers
1135 */
181d6902
ID		 1136static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1137 struct rxdone_entry_desc *rxdesc)
95ea3627 1138{
ae73e58e 1139 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1140 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1141 u32 word0;
1142 u32 word2;
89993890 1143 u32 word3;
ae73e58e
ID		 1144 u32 word4;
1145 u64 tsf;
1146 u32 rx_low;
1147 u32 rx_high;
95ea3627 1148
b8be63ff
ID		 1149 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1150 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1151 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1152 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1153
4150c572 1154 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1155 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1156 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1157 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1158
ae73e58e
ID		 1159 /*
1160 * We only get the lower 32bits from the timestamp,
1161 * to get the full 64bits we must complement it with
1162 * the timestamp from get_tsf().
1163 * Note that when a wraparound of the lower 32bits
1164 * has occurred between the frame arrival and the get_tsf()
1165 * call, we must decrease the higher 32bits with 1 to get
1166 * to correct value.
1167 */
1168 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1169 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1170 rx_high = upper_32_bits(tsf);
1171
1172 if ((u32)tsf <= rx_low)
1173 rx_high--;
1174
95ea3627
ID		 1175 /*
1176 * Obtain the status about this packet.
8ed09854
ID		 1177 * The signal is the PLCP value, and needs to be stripped
1178 * of the preamble bit (0x08).
95ea3627 1179 */
ae73e58e 1180 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1181 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1182 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1183 entry->queue->rt2x00dev->rssi_offset;
181d6902 1184 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1185
dec13b6b 1186 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1187 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1188 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1189}
1190
1191/*
1192 * Interrupt functions.
1193 */
181d6902 1194static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1195 const enum data_queue_qid queue_idx)
95ea3627 1196{
181d6902 1197 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1198 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1199 struct queue_entry *entry;
1200 struct txdone_entry_desc txdesc;
95ea3627 1201 u32 word;
95ea3627 1202
181d6902
ID		 1203 while (!rt2x00queue_empty(queue)) {
1204 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1205 entry_priv = entry->priv_data;
1206 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1207
1208 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1209 !rt2x00_get_field32(word, TXD_W0_VALID))
1210 break;
1211
1212 /*
1213 * Obtain the status about this packet.
1214 */
fb55f4d1
ID		 1215 txdesc.flags = 0;
1216 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1217 case 0: /* Success */
1218 case 1: /* Success with retry */
1219 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1220 break;
1221 case 2: /* Failure, excessive retries */
1222 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1223 /* Don't break, this is a failed frame! */
1224 default: /* Failure */
1225 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1226 }
181d6902 1227 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1228
d74f5ba4 1229 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1230 }
95ea3627
ID		 1231}
1232
1233static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1234{
1235 struct rt2x00_dev *rt2x00dev = dev_instance;
1236 u32 reg;
1237
1238 /*
1239 * Get the interrupt sources & saved to local variable.
1240 * Write register value back to clear pending interrupts.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1243 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1244
1245 if (!reg)
1246 return IRQ_NONE;
1247
0262ab0d 1248 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1249 return IRQ_HANDLED;
1250
1251 /*
1252 * Handle interrupts, walk through all bits
1253 * and run the tasks, the bits are checked in order of
1254 * priority.
1255 */
1256
1257 /*
1258 * 1 - Beacon timer expired interrupt.
1259 */
1260 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1261 rt2x00lib_beacondone(rt2x00dev);
1262
1263 /*
1264 * 2 - Rx ring done interrupt.
1265 */
1266 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1267 rt2x00pci_rxdone(rt2x00dev);
1268
1269 /*
1270 * 3 - Atim ring transmit done interrupt.
1271 */
1272 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1273 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1274
1275 /*
1276 * 4 - Priority ring transmit done interrupt.
1277 */
1278 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1279 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1280
1281 /*
1282 * 5 - Tx ring transmit done interrupt.
1283 */
1284 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1285 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1286
1287 return IRQ_HANDLED;
1288}
1289
1290/*
1291 * Device probe functions.
1292 */
1293static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1294{
1295 struct eeprom_93cx6 eeprom;
1296 u32 reg;
1297 u16 word;
1298 u8 *mac;
1299
1300 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1301
1302 eeprom.data = rt2x00dev;
1303 eeprom.register_read = rt2400pci_eepromregister_read;
1304 eeprom.register_write = rt2400pci_eepromregister_write;
1305 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1306 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1307 eeprom.reg_data_in = 0;
1308 eeprom.reg_data_out = 0;
1309 eeprom.reg_data_clock = 0;
1310 eeprom.reg_chip_select = 0;
1311
1312 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1313 EEPROM_SIZE / sizeof(u16));
1314
1315 /*
1316 * Start validation of the data that has been read.
1317 */
1318 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1319 if (!is_valid_ether_addr(mac)) {
1320 random_ether_addr(mac);
e174961c 1321 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1322 }
1323
1324 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1325 if (word == 0xffff) {
1326 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1327 return -EINVAL;
1328 }
1329
1330 return 0;
1331}
1332
1333static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1334{
1335 u32 reg;
1336 u16 value;
1337 u16 eeprom;
1338
1339 /*
1340 * Read EEPROM word for configuration.
1341 */
1342 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1343
1344 /*
1345 * Identify RF chipset.
1346 */
1347 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1348 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1349 rt2x00_set_chip(rt2x00dev, RT2460, value,
1350 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1351
5122d898 1352 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1353 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1354 return -ENODEV;
1355 }
1356
1357 /*
1358 * Identify default antenna configuration.
1359 */
addc81bd 1360 rt2x00dev->default_ant.tx =
95ea3627 1361 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1362 rt2x00dev->default_ant.rx =
95ea3627
ID		 1363 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1364
addc81bd
ID		 1365 /*
1366 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1367 * I am not 100% sure about this, but the legacy drivers do not
1368 * indicate antenna swapping in software is required when
1369 * diversity is enabled.
1370 */
1371 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1372 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1373 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1374 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1375
95ea3627
ID		 1376 /*
1377 * Store led mode, for correct led behaviour.
1378 */
771fd565 1379#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1380 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1381
475433be 1382 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1383 if (value == LED_MODE_TXRX_ACTIVITY ||
1384 value == LED_MODE_DEFAULT ||
1385 value == LED_MODE_ASUS)
475433be
ID		 1386 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1387 LED_TYPE_ACTIVITY);
771fd565 1388#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1389
1390 /*
1391 * Detect if this device has an hardware controlled radio.
1392 */
1393 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1394 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1395
1396 /*
1397 * Check if the BBP tuning should be enabled.
1398 */
1399 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1400 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1401
1402 return 0;
1403}
1404
1405/*
1406 * RF value list for RF2420 & RF2421
1407 * Supports: 2.4 GHz
1408 */
8c5e7a5f 1409static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1410 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1411 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1412 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1413 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1414 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1415 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1416 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1417 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1418 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1419 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1420 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1421 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1422 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1423 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1424};
1425
8c5e7a5f 1426static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1427{
1428 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1429 struct channel_info *info;
1430 char *tx_power;
95ea3627
ID		 1431 unsigned int i;
1432
1433 /*
1434 * Initialize all hw fields.
1435 */
566bfe5a 1436 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1437 IEEE80211_HW_SIGNAL_DBM |
1438 IEEE80211_HW_SUPPORTS_PS |
1439 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1440
14a3bf89 1441 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1442 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1443 rt2x00_eeprom_addr(rt2x00dev,
1444 EEPROM_MAC_ADDR_0));
1445
95ea3627
ID		 1446 /*
1447 * Initialize hw_mode information.
1448 */
31562e80
ID		 1449 spec->supported_bands = SUPPORT_BAND_2GHZ;
1450 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1451
8c5e7a5f
ID		 1452 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1453 spec->channels = rf_vals_b;
1454
1455 /*
1456 * Create channel information array
1457 */
1458 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1459 if (!info)
1460 return -ENOMEM;
1461
1462 spec->channels_info = info;
1463
1464 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1465 for (i = 0; i < 14; i++)
1466 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1467
1468 return 0;
95ea3627
ID		 1469}
1470
1471static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1472{
1473 int retval;
1474
1475 /*
1476 * Allocate eeprom data.
1477 */
1478 retval = rt2400pci_validate_eeprom(rt2x00dev);
1479 if (retval)
1480 return retval;
1481
1482 retval = rt2400pci_init_eeprom(rt2x00dev);
1483 if (retval)
1484 return retval;
1485
1486 /*
1487 * Initialize hw specifications.
1488 */
8c5e7a5f
ID		 1489 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1490 if (retval)
1491 return retval;
95ea3627
ID		 1492
1493 /*
c4da0048 1494 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1495 */
181d6902 1496 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1497 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1498
1499 /*
1500 * Set the rssi offset.
1501 */
1502 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1503
1504 return 0;
1505}
1506
1507/*
1508 * IEEE80211 stack callback functions.
1509 */
e100bb64 1510static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1511 const struct ieee80211_tx_queue_params *params)
1512{
1513 struct rt2x00_dev *rt2x00dev = hw->priv;
1514
1515 /*
1516 * We don't support variating cw_min and cw_max variables
1517 * per queue. So by default we only configure the TX queue,
1518 * and ignore all other configurations.
1519 */
e100bb64 1520 if (queue != 0)
95ea3627
ID		 1521 return -EINVAL;
1522
1523 if (rt2x00mac_conf_tx(hw, queue, params))
1524 return -EINVAL;
1525
1526 /*
1527 * Write configuration to register.
1528 */
181d6902
ID		 1529 rt2400pci_config_cw(rt2x00dev,
1530 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1531
1532 return 0;
1533}
1534
1535static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1536{
1537 struct rt2x00_dev *rt2x00dev = hw->priv;
1538 u64 tsf;
1539 u32 reg;
1540
1541 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1542 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1543 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1544 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1545
1546 return tsf;
1547}
1548
95ea3627
ID		 1549static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1550{
1551 struct rt2x00_dev *rt2x00dev = hw->priv;
1552 u32 reg;
1553
1554 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1555 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1556}
1557
1558static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1559 .tx = rt2x00mac_tx,
4150c572
JB		 1560 .start = rt2x00mac_start,
1561 .stop = rt2x00mac_stop,
95ea3627
ID		 1562 .add_interface = rt2x00mac_add_interface,
1563 .remove_interface = rt2x00mac_remove_interface,
1564 .config = rt2x00mac_config,
3a643d24 1565 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1566 .set_tim = rt2x00mac_set_tim,
95ea3627 1567 .get_stats = rt2x00mac_get_stats,
471b3efd 1568 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1569 .conf_tx = rt2400pci_conf_tx,
95ea3627 1570 .get_tsf = rt2400pci_get_tsf,
95ea3627 1571 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1572 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1573};
1574
1575static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1576 .irq_handler = rt2400pci_interrupt,
1577 .probe_hw = rt2400pci_probe_hw,
1578 .initialize = rt2x00pci_initialize,
1579 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1580 .get_entry_state = rt2400pci_get_entry_state,
1581 .clear_entry = rt2400pci_clear_entry,
95ea3627 1582 .set_device_state = rt2400pci_set_device_state,
95ea3627 1583 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1584 .link_stats = rt2400pci_link_stats,
1585 .reset_tuner = rt2400pci_reset_tuner,
1586 .link_tuner = rt2400pci_link_tuner,
1587 .write_tx_desc = rt2400pci_write_tx_desc,
1588 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1589 .write_beacon = rt2400pci_write_beacon,
95ea3627 1590 .kick_tx_queue = rt2400pci_kick_tx_queue,
a2c9b652 1591 .kill_tx_queue = rt2400pci_kill_tx_queue,
95ea3627 1592 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1593 .config_filter = rt2400pci_config_filter,
6bb40dd1 1594 .config_intf = rt2400pci_config_intf,
72810379 1595 .config_erp = rt2400pci_config_erp,
e4ea1c40 1596 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1597 .config = rt2400pci_config,
1598};
1599
181d6902
ID		 1600static const struct data_queue_desc rt2400pci_queue_rx = {
1601 .entry_num = RX_ENTRIES,
1602 .data_size = DATA_FRAME_SIZE,
1603 .desc_size = RXD_DESC_SIZE,
b8be63ff 1604 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1605};
1606
1607static const struct data_queue_desc rt2400pci_queue_tx = {
1608 .entry_num = TX_ENTRIES,
1609 .data_size = DATA_FRAME_SIZE,
1610 .desc_size = TXD_DESC_SIZE,
b8be63ff 1611 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1612};
1613
1614static const struct data_queue_desc rt2400pci_queue_bcn = {
1615 .entry_num = BEACON_ENTRIES,
1616 .data_size = MGMT_FRAME_SIZE,
1617 .desc_size = TXD_DESC_SIZE,
b8be63ff 1618 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1619};
1620
1621static const struct data_queue_desc rt2400pci_queue_atim = {
1622 .entry_num = ATIM_ENTRIES,
1623 .data_size = DATA_FRAME_SIZE,
1624 .desc_size = TXD_DESC_SIZE,
b8be63ff 1625 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1626};
1627
95ea3627 1628static const struct rt2x00_ops rt2400pci_ops = {
04d0362e
GW		 1629 .name = KBUILD_MODNAME,
1630 .max_sta_intf = 1,
1631 .max_ap_intf = 1,
1632 .eeprom_size = EEPROM_SIZE,
1633 .rf_size = RF_SIZE,
1634 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1635 .extra_tx_headroom = 0,
04d0362e
GW		 1636 .rx = &rt2400pci_queue_rx,
1637 .tx = &rt2400pci_queue_tx,
1638 .bcn = &rt2400pci_queue_bcn,
1639 .atim = &rt2400pci_queue_atim,
1640 .lib = &rt2400pci_rt2x00_ops,
1641 .hw = &rt2400pci_mac80211_ops,
95ea3627 1642#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1643 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1644#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1645};
1646
1647/*
1648 * RT2400pci module information.
1649 */
a3aa1884 1650static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
95ea3627
ID		 1651 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1652 { 0, }
1653};
1654
1655MODULE_AUTHOR(DRV_PROJECT);
1656MODULE_VERSION(DRV_VERSION);
1657MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1658MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1659MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1660MODULE_LICENSE("GPL");
1661
1662static struct pci_driver rt2400pci_driver = {
2360157c 1663 .name = KBUILD_MODNAME,
95ea3627
ID		 1664 .id_table = rt2400pci_device_table,
1665 .probe = rt2x00pci_probe,
1666 .remove = __devexit_p(rt2x00pci_remove),
1667 .suspend = rt2x00pci_suspend,
1668 .resume = rt2x00pci_resume,
1669};
1670
1671static int __init rt2400pci_init(void)
1672{
1673 return pci_register_driver(&rt2400pci_driver);
1674}
1675
1676static void __exit rt2400pci_exit(void)
1677{
1678 pci_unregister_driver(&rt2400pci_driver);
1679}
1680
1681module_init(rt2400pci_init);
1682module_exit(rt2400pci_exit);
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