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ath9k: correct warning about unintialized variable 'tid'
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
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95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
58169529 234#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627
ID		 235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
58169529 244#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627 245
771fd565 246#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 247static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
475433be
ID		 280
281static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2400pci_brightness_set;
288 led->led_dev.blink_set = rt2400pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
771fd565 291#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 292
95ea3627
ID		 293/*
294 * Configuration handlers.
295 */
3a643d24
ID		 296static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
297 const unsigned int filter_flags)
298{
299 u32 reg;
300
301 /*
302 * Start configuration steps.
303 * Note that the version error will always be dropped
304 * since there is no filter for it at this time.
305 */
306 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
307 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
308 !(filter_flags & FIF_FCSFAIL));
309 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
310 !(filter_flags & FIF_PLCPFAIL));
311 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
312 !(filter_flags & FIF_CONTROL));
313 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
314 !(filter_flags & FIF_PROMISC_IN_BSS));
315 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 316 !(filter_flags & FIF_PROMISC_IN_BSS) &&
317 !rt2x00dev->intf_ap_count);
3a643d24
ID		 318 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
319 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
320}
321
6bb40dd1
ID		 322static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00_intf *intf,
324 struct rt2x00intf_conf *conf,
325 const unsigned int flags)
95ea3627 326{
6bb40dd1
ID		 327 unsigned int bcn_preload;
328 u32 reg;
95ea3627 329
6bb40dd1 330 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 331 /*
332 * Enable beacon config
333 */
334 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
335 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
336 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
337 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 338
6bb40dd1
ID		 339 /*
340 * Enable synchronisation.
341 */
342 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 343 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 344 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 345 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 346 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
347 }
95ea3627 348
6bb40dd1
ID		 349 if (flags & CONFIG_UPDATE_MAC)
350 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
351 conf->mac, sizeof(conf->mac));
95ea3627 352
6bb40dd1
ID		 353 if (flags & CONFIG_UPDATE_BSSID)
354 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
355 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 356}
357
3a643d24
ID		 358static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
359 struct rt2x00lib_erp *erp)
95ea3627 360{
5c58ee51 361 int preamble_mask;
95ea3627 362 u32 reg;
95ea3627 363
5c58ee51
ID		 364 /*
365 * When short preamble is enabled, we should set bit 0x08
366 */
72810379 367 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 368
369 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 370 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
371 erp->ack_timeout);
372 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
373 erp->ack_consume_time);
95ea3627
ID		 374 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
375
95ea3627 376 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 377 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627
ID		 378 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
379 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
380 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
381
382 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 383 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 384 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
385 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
386 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
387
388 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 389 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 390 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
391 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
392 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 395 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 396 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
398 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 399
400 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
401
402 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
403 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
404 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
405
406 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
407 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
408 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
409 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
410
411 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
412 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
413 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
414 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 415}
416
e4ea1c40
ID		 417static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
418 struct antenna_setup *ant)
95ea3627 419{
e4ea1c40
ID		 420 u8 r1;
421 u8 r4;
422
423 /*
424 * We should never come here because rt2x00lib is supposed
425 * to catch this and send us the correct antenna explicitely.
426 */
427 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
428 ant->tx == ANTENNA_SW_DIVERSITY);
429
430 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
431 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
432
433 /*
434 * Configure the TX antenna.
435 */
436 switch (ant->tx) {
437 case ANTENNA_HW_DIVERSITY:
438 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
439 break;
440 case ANTENNA_A:
441 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
442 break;
443 case ANTENNA_B:
444 default:
445 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
446 break;
447 }
448
449 /*
450 * Configure the RX antenna.
451 */
452 switch (ant->rx) {
453 case ANTENNA_HW_DIVERSITY:
454 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
455 break;
456 case ANTENNA_A:
457 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
458 break;
459 case ANTENNA_B:
460 default:
461 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
462 break;
463 }
464
465 rt2400pci_bbp_write(rt2x00dev, 4, r4);
466 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 467}
468
469static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 470 struct rf_channel *rf)
95ea3627 471{
95ea3627
ID		 472 /*
473 * Switch on tuning bits.
474 */
5c58ee51
ID		 475 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
476 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 477
5c58ee51
ID		 478 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
479 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
480 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 481
482 /*
483 * RF2420 chipset don't need any additional actions.
484 */
485 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
486 return;
487
488 /*
489 * For the RT2421 chipsets we need to write an invalid
490 * reference clock rate to activate auto_tune.
491 * After that we set the value back to the correct channel.
492 */
5c58ee51 493 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 494 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 495 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 496
497 msleep(1);
498
5c58ee51
ID		 499 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
500 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
501 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 502
503 msleep(1);
504
505 /*
506 * Switch off tuning bits.
507 */
5c58ee51
ID		 508 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
509 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 510
5c58ee51
ID		 511 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
512 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 513
514 /*
515 * Clear false CRC during channel switch.
516 */
5c58ee51 517 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 518}
519
520static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
521{
522 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
523}
524
e4ea1c40
ID		 525static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
526 struct rt2x00lib_conf *libconf)
95ea3627 527{
e4ea1c40 528 u32 reg;
95ea3627 529
e4ea1c40
ID		 530 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
531 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
532 libconf->conf->long_frame_max_tx_count);
533 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
534 libconf->conf->short_frame_max_tx_count);
535 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 536}
537
538static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 539 struct rt2x00lib_conf *libconf)
95ea3627
ID		 540{
541 u32 reg;
542
95ea3627
ID		 543 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
544 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
545 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
546 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
547
548 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 549 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
550 libconf->conf->beacon_int * 16);
551 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
552 libconf->conf->beacon_int * 16);
95ea3627
ID		 553 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
554}
555
556static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 557 struct rt2x00lib_conf *libconf,
558 const unsigned int flags)
95ea3627 559{
e4ea1c40 560 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 561 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 562 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 563 rt2400pci_config_txpower(rt2x00dev,
564 libconf->conf->power_level);
e4ea1c40
ID		 565 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
566 rt2400pci_config_retry_limit(rt2x00dev, libconf);
567 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 568 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 569}
570
571static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 572 const int cw_min, const int cw_max)
95ea3627
ID		 573{
574 u32 reg;
575
576 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 577 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
578 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 579 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
580}
581
95ea3627
ID		 582/*
583 * Link tuning
584 */
ebcf26da
ID		 585static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
586 struct link_qual *qual)
95ea3627
ID		 587{
588 u32 reg;
589 u8 bbp;
590
591 /*
592 * Update FCS error count from register.
593 */
594 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 595 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 596
597 /*
598 * Update False CCA count from register.
599 */
600 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 601 qual->false_cca = bbp;
95ea3627
ID		 602}
603
604static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
605{
606 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
607 rt2x00dev->link.vgc_level = 0x08;
608}
609
610static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
611{
612 u8 reg;
613
614 /*
615 * The link tuner should not run longer then 60 seconds,
616 * and should run once every 2 seconds.
617 */
618 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
619 return;
620
621 /*
622 * Base r13 link tuning on the false cca count.
623 */
624 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
625
ebcf26da 626 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 627 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
628 rt2x00dev->link.vgc_level = reg;
ebcf26da 629 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 630 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
631 rt2x00dev->link.vgc_level = reg;
632 }
633}
634
635/*
636 * Initialization functions.
637 */
837e7f24 638static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 639 struct queue_entry *entry)
95ea3627 640{
b8be63ff 641 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 642 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 643 u32 word;
644
b8be63ff 645 rt2x00_desc_read(entry_priv->desc, 2, &word);
c4da0048 646 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
b8be63ff 647 rt2x00_desc_write(entry_priv->desc, 2, word);
95ea3627 648
b8be63ff 649 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 650 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
b8be63ff 651 rt2x00_desc_write(entry_priv->desc, 1, word);
95ea3627 652
b8be63ff 653 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 654 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 655 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 656}
657
837e7f24 658static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 659 struct queue_entry *entry)
95ea3627 660{
b8be63ff 661 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 662 u32 word;
663
b8be63ff 664 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 665 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
666 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 667 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 668}
669
181d6902 670static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 671{
b8be63ff 672 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 673 u32 reg;
674
95ea3627
ID		 675 /*
676 * Initialize registers.
677 */
678 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 679 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
680 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
681 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
682 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 683 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
684
b8be63ff 685 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 686 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 687 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 688 entry_priv->desc_dma);
95ea3627
ID		 689 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
690
b8be63ff 691 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 692 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 693 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 694 entry_priv->desc_dma);
95ea3627
ID		 695 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
696
b8be63ff 697 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 698 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 699 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 700 entry_priv->desc_dma);
95ea3627
ID		 701 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
702
b8be63ff 703 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 704 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 705 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 706 entry_priv->desc_dma);
95ea3627
ID		 707 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
708
709 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
710 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 711 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 712 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
713
b8be63ff 714 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 715 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 716 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
717 entry_priv->desc_dma);
95ea3627
ID		 718 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
719
720 return 0;
721}
722
723static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
724{
725 u32 reg;
726
727 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
728 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
729 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
730 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
731
732 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
733 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
734 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
735 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
736 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
737
738 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
739 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
740 (rt2x00dev->rx->data_size / 128));
741 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
742
1f909162
ID		 743 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
744 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
745 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
746 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
747 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
748 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
749 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
750 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
751 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
752 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
753
95ea3627
ID		 754 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
755
756 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
757 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
758 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
759 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
760 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
761 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
762
763 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
764 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
765 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
766 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
767 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
768 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
769 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
770 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
771
772 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
773
774 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
775 return -EBUSY;
776
777 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
778 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
779
780 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
781 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
782 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
783
784 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
785 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
786 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
787 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
788 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
789 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
790
791 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
792 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
793 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
794 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
795 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
796
797 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
798 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
799 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
800 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
801
802 /*
803 * We must clear the FCS and FIFO error count.
804 * These registers are cleared on read,
805 * so we may pass a useless variable to store the value.
806 */
807 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
808 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
809
810 return 0;
811}
812
2b08da3f 813static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 814{
815 unsigned int i;
95ea3627
ID		 816 u8 value;
817
818 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
819 rt2400pci_bbp_read(rt2x00dev, 0, &value);
820 if ((value != 0xff) && (value != 0x00))
2b08da3f 821 return 0;
95ea3627
ID		 822 udelay(REGISTER_BUSY_DELAY);
823 }
824
825 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
826 return -EACCES;
2b08da3f
ID		 827}
828
829static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
830{
831 unsigned int i;
832 u16 eeprom;
833 u8 reg_id;
834 u8 value;
835
836 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
837 return -EACCES;
95ea3627 838
95ea3627
ID		 839 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
840 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
841 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
842 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
843 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
844 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
845 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
846 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
847 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
848 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
849 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
850 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
851 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
852 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
853
95ea3627
ID		 854 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
855 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
856
857 if (eeprom != 0xffff && eeprom != 0x0000) {
858 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
859 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 860 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
861 }
862 }
95ea3627
ID		 863
864 return 0;
865}
866
867/*
868 * Device state switch handlers.
869 */
870static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
871 enum dev_state state)
872{
873 u32 reg;
874
875 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
876 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 877 (state == STATE_RADIO_RX_OFF) ||
878 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 879 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
880}
881
882static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
883 enum dev_state state)
884{
885 int mask = (state == STATE_RADIO_IRQ_OFF);
886 u32 reg;
887
888 /*
889 * When interrupts are being enabled, the interrupt registers
890 * should clear the register to assure a clean state.
891 */
892 if (state == STATE_RADIO_IRQ_ON) {
893 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
894 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
895 }
896
897 /*
898 * Only toggle the interrupts bits we are going to use.
899 * Non-checked interrupt bits are disabled by default.
900 */
901 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
902 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
903 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
904 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
905 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
906 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
907 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
908}
909
910static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
911{
912 /*
913 * Initialize all registers.
914 */
2b08da3f
ID		 915 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
916 rt2400pci_init_registers(rt2x00dev) ||
917 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 918 return -EIO;
95ea3627 919
95ea3627
ID		 920 return 0;
921}
922
923static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
924{
925 u32 reg;
926
95ea3627
ID		 927 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
928
929 /*
930 * Disable synchronisation.
931 */
932 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
933
934 /*
935 * Cancel RX and TX.
936 */
937 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
938 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
939 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
95ea3627
ID		 940}
941
942static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
943 enum dev_state state)
944{
945 u32 reg;
946 unsigned int i;
947 char put_to_sleep;
948 char bbp_state;
949 char rf_state;
950
951 put_to_sleep = (state != STATE_AWAKE);
952
953 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
954 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
955 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
956 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
957 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
958 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
959
960 /*
961 * Device is not guaranteed to be in the requested state yet.
962 * We must wait until the register indicates that the
963 * device has entered the correct state.
964 */
965 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
966 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
967 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
968 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
969 if (bbp_state == state && rf_state == state)
970 return 0;
971 msleep(10);
972 }
973
95ea3627
ID		 974 return -EBUSY;
975}
976
977static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
978 enum dev_state state)
979{
980 int retval = 0;
981
982 switch (state) {
983 case STATE_RADIO_ON:
984 retval = rt2400pci_enable_radio(rt2x00dev);
985 break;
986 case STATE_RADIO_OFF:
987 rt2400pci_disable_radio(rt2x00dev);
988 break;
989 case STATE_RADIO_RX_ON:
61667d8d 990 case STATE_RADIO_RX_ON_LINK:
95ea3627 991 case STATE_RADIO_RX_OFF:
61667d8d 992 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 993 rt2400pci_toggle_rx(rt2x00dev, state);
994 break;
995 case STATE_RADIO_IRQ_ON:
996 case STATE_RADIO_IRQ_OFF:
997 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 998 break;
999 case STATE_DEEP_SLEEP:
1000 case STATE_SLEEP:
1001 case STATE_STANDBY:
1002 case STATE_AWAKE:
1003 retval = rt2400pci_set_state(rt2x00dev, state);
1004 break;
1005 default:
1006 retval = -ENOTSUPP;
1007 break;
1008 }
1009
2b08da3f
ID		 1010 if (unlikely(retval))
1011 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1012 state, retval);
1013
95ea3627
ID		 1014 return retval;
1015}
1016
1017/*
1018 * TX descriptor initialization
1019 */
1020static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1021 struct sk_buff *skb,
61486e0f 1022 struct txentry_desc *txdesc)
95ea3627 1023{
181d6902 1024 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1025 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1026 __le32 *txd = skbdesc->desc;
95ea3627 1027 u32 word;
95ea3627
ID		 1028
1029 /*
1030 * Start writing the descriptor words.
1031 */
4de36fe5 1032 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1033 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1034 rt2x00_desc_write(entry_priv->desc, 1, word);
1035
95ea3627 1036 rt2x00_desc_read(txd, 2, &word);
d56d453a
GW		 1037 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1038 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
95ea3627
ID		 1039 rt2x00_desc_write(txd, 2, word);
1040
1041 rt2x00_desc_read(txd, 3, &word);
181d6902 1042 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1043 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1044 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1045 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1046 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1047 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1048 rt2x00_desc_write(txd, 3, word);
1049
1050 rt2x00_desc_read(txd, 4, &word);
181d6902 1051 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1052 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1053 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1054 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1055 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1056 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1057 rt2x00_desc_write(txd, 4, word);
1058
1059 rt2x00_desc_read(txd, 0, &word);
1060 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1061 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1062 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1063 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1064 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1065 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1066 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1067 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1068 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1069 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1070 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1071 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1072 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627
ID		 1073 rt2x00_desc_write(txd, 0, word);
1074}
1075
1076/*
1077 * TX data initialization
1078 */
bd88a781
ID		 1079static void rt2400pci_write_beacon(struct queue_entry *entry)
1080{
1081 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1082 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1083 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1084 u32 word;
1085 u32 reg;
1086
1087 /*
1088 * Disable beaconing while we are reloading the beacon data,
1089 * otherwise we might be sending out invalid data.
1090 */
1091 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1092 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1093 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1094 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1095 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1096
1097 /*
1098 * Replace rt2x00lib allocated descriptor with the
1099 * pointer to the _real_ hardware descriptor.
1100 * After that, map the beacon to DMA and update the
1101 * descriptor.
1102 */
1103 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1104 skbdesc->desc = entry_priv->desc;
1105
1106 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1107
1108 rt2x00_desc_read(entry_priv->desc, 1, &word);
1109 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1110 rt2x00_desc_write(entry_priv->desc, 1, word);
1111}
1112
95ea3627 1113static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1114 const enum data_queue_qid queue)
95ea3627
ID		 1115{
1116 u32 reg;
1117
e58c6aca 1118 if (queue == QID_BEACON) {
95ea3627
ID		 1119 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1120 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1121 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1122 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1123 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1124 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1125 }
1126 return;
1127 }
1128
1129 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1130 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1131 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1132 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1133 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1134}
1135
1136/*
1137 * RX control handlers
1138 */
181d6902
ID		 1139static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1140 struct rxdone_entry_desc *rxdesc)
95ea3627 1141{
ae73e58e 1142 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1143 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1144 u32 word0;
1145 u32 word2;
89993890 1146 u32 word3;
ae73e58e
ID		 1147 u32 word4;
1148 u64 tsf;
1149 u32 rx_low;
1150 u32 rx_high;
95ea3627 1151
b8be63ff
ID		 1152 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1153 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1154 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1155 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1156
4150c572 1157 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1158 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1159 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1160 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1161
ae73e58e
ID		 1162 /*
1163 * We only get the lower 32bits from the timestamp,
1164 * to get the full 64bits we must complement it with
1165 * the timestamp from get_tsf().
1166 * Note that when a wraparound of the lower 32bits
1167 * has occurred between the frame arrival and the get_tsf()
1168 * call, we must decrease the higher 32bits with 1 to get
1169 * to correct value.
1170 */
1171 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1172 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1173 rx_high = upper_32_bits(tsf);
1174
1175 if ((u32)tsf <= rx_low)
1176 rx_high--;
1177
95ea3627
ID		 1178 /*
1179 * Obtain the status about this packet.
8ed09854
ID		 1180 * The signal is the PLCP value, and needs to be stripped
1181 * of the preamble bit (0x08).
95ea3627 1182 */
ae73e58e 1183 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1184 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1185 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1186 entry->queue->rt2x00dev->rssi_offset;
181d6902 1187 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1188
dec13b6b 1189 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1190 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1191 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1192}
1193
1194/*
1195 * Interrupt functions.
1196 */
181d6902 1197static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1198 const enum data_queue_qid queue_idx)
95ea3627 1199{
181d6902 1200 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1201 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1202 struct queue_entry *entry;
1203 struct txdone_entry_desc txdesc;
95ea3627 1204 u32 word;
95ea3627 1205
181d6902
ID		 1206 while (!rt2x00queue_empty(queue)) {
1207 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1208 entry_priv = entry->priv_data;
1209 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1210
1211 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1212 !rt2x00_get_field32(word, TXD_W0_VALID))
1213 break;
1214
1215 /*
1216 * Obtain the status about this packet.
1217 */
fb55f4d1
ID		 1218 txdesc.flags = 0;
1219 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1220 case 0: /* Success */
1221 case 1: /* Success with retry */
1222 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1223 break;
1224 case 2: /* Failure, excessive retries */
1225 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1226 /* Don't break, this is a failed frame! */
1227 default: /* Failure */
1228 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1229 }
181d6902 1230 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1231
d74f5ba4 1232 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1233 }
95ea3627
ID		 1234}
1235
1236static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1237{
1238 struct rt2x00_dev *rt2x00dev = dev_instance;
1239 u32 reg;
1240
1241 /*
1242 * Get the interrupt sources & saved to local variable.
1243 * Write register value back to clear pending interrupts.
1244 */
1245 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1246 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1247
1248 if (!reg)
1249 return IRQ_NONE;
1250
0262ab0d 1251 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1252 return IRQ_HANDLED;
1253
1254 /*
1255 * Handle interrupts, walk through all bits
1256 * and run the tasks, the bits are checked in order of
1257 * priority.
1258 */
1259
1260 /*
1261 * 1 - Beacon timer expired interrupt.
1262 */
1263 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1264 rt2x00lib_beacondone(rt2x00dev);
1265
1266 /*
1267 * 2 - Rx ring done interrupt.
1268 */
1269 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1270 rt2x00pci_rxdone(rt2x00dev);
1271
1272 /*
1273 * 3 - Atim ring transmit done interrupt.
1274 */
1275 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1276 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1277
1278 /*
1279 * 4 - Priority ring transmit done interrupt.
1280 */
1281 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1282 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1283
1284 /*
1285 * 5 - Tx ring transmit done interrupt.
1286 */
1287 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1288 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1289
1290 return IRQ_HANDLED;
1291}
1292
1293/*
1294 * Device probe functions.
1295 */
1296static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1297{
1298 struct eeprom_93cx6 eeprom;
1299 u32 reg;
1300 u16 word;
1301 u8 *mac;
1302
1303 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1304
1305 eeprom.data = rt2x00dev;
1306 eeprom.register_read = rt2400pci_eepromregister_read;
1307 eeprom.register_write = rt2400pci_eepromregister_write;
1308 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1309 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1310 eeprom.reg_data_in = 0;
1311 eeprom.reg_data_out = 0;
1312 eeprom.reg_data_clock = 0;
1313 eeprom.reg_chip_select = 0;
1314
1315 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1316 EEPROM_SIZE / sizeof(u16));
1317
1318 /*
1319 * Start validation of the data that has been read.
1320 */
1321 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1322 if (!is_valid_ether_addr(mac)) {
1323 random_ether_addr(mac);
e174961c 1324 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1325 }
1326
1327 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1328 if (word == 0xffff) {
1329 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1330 return -EINVAL;
1331 }
1332
1333 return 0;
1334}
1335
1336static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1337{
1338 u32 reg;
1339 u16 value;
1340 u16 eeprom;
1341
1342 /*
1343 * Read EEPROM word for configuration.
1344 */
1345 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1346
1347 /*
1348 * Identify RF chipset.
1349 */
1350 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1351 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1352 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1353
1354 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1355 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1356 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1357 return -ENODEV;
1358 }
1359
1360 /*
1361 * Identify default antenna configuration.
1362 */
addc81bd 1363 rt2x00dev->default_ant.tx =
95ea3627 1364 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1365 rt2x00dev->default_ant.rx =
95ea3627
ID		 1366 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1367
addc81bd
ID		 1368 /*
1369 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1370 * I am not 100% sure about this, but the legacy drivers do not
1371 * indicate antenna swapping in software is required when
1372 * diversity is enabled.
1373 */
1374 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1375 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1376 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1377 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1378
95ea3627
ID		 1379 /*
1380 * Store led mode, for correct led behaviour.
1381 */
771fd565 1382#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1383 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1384
475433be
ID		 1385 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1386 if (value == LED_MODE_TXRX_ACTIVITY)
1387 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1388 LED_TYPE_ACTIVITY);
771fd565 1389#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1390
1391 /*
1392 * Detect if this device has an hardware controlled radio.
1393 */
58169529 1394#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627 1395 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1396 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
58169529 1397#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627
ID		 1398
1399 /*
1400 * Check if the BBP tuning should be enabled.
1401 */
1402 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1403 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1404
1405 return 0;
1406}
1407
1408/*
1409 * RF value list for RF2420 & RF2421
1410 * Supports: 2.4 GHz
1411 */
8c5e7a5f 1412static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1413 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1414 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1415 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1416 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1417 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1418 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1419 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1420 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1421 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1422 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1423 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1424 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1425 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1426 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1427};
1428
8c5e7a5f 1429static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1430{
1431 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1432 struct channel_info *info;
1433 char *tx_power;
95ea3627
ID		 1434 unsigned int i;
1435
1436 /*
1437 * Initialize all hw fields.
1438 */
566bfe5a
BR		 1439 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1440 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1441 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 1442
14a3bf89 1443 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1444 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1445 rt2x00_eeprom_addr(rt2x00dev,
1446 EEPROM_MAC_ADDR_0));
1447
95ea3627
ID		 1448 /*
1449 * Initialize hw_mode information.
1450 */
31562e80
ID		 1451 spec->supported_bands = SUPPORT_BAND_2GHZ;
1452 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1453
8c5e7a5f
ID		 1454 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1455 spec->channels = rf_vals_b;
1456
1457 /*
1458 * Create channel information array
1459 */
1460 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1461 if (!info)
1462 return -ENOMEM;
1463
1464 spec->channels_info = info;
1465
1466 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1467 for (i = 0; i < 14; i++)
1468 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1469
1470 return 0;
95ea3627
ID		 1471}
1472
1473static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1474{
1475 int retval;
1476
1477 /*
1478 * Allocate eeprom data.
1479 */
1480 retval = rt2400pci_validate_eeprom(rt2x00dev);
1481 if (retval)
1482 return retval;
1483
1484 retval = rt2400pci_init_eeprom(rt2x00dev);
1485 if (retval)
1486 return retval;
1487
1488 /*
1489 * Initialize hw specifications.
1490 */
8c5e7a5f
ID		 1491 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1492 if (retval)
1493 return retval;
95ea3627
ID		 1494
1495 /*
c4da0048 1496 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1497 */
181d6902 1498 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1499 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1500
1501 /*
1502 * Set the rssi offset.
1503 */
1504 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1505
1506 return 0;
1507}
1508
1509/*
1510 * IEEE80211 stack callback functions.
1511 */
e100bb64 1512static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1513 const struct ieee80211_tx_queue_params *params)
1514{
1515 struct rt2x00_dev *rt2x00dev = hw->priv;
1516
1517 /*
1518 * We don't support variating cw_min and cw_max variables
1519 * per queue. So by default we only configure the TX queue,
1520 * and ignore all other configurations.
1521 */
e100bb64 1522 if (queue != 0)
95ea3627
ID		 1523 return -EINVAL;
1524
1525 if (rt2x00mac_conf_tx(hw, queue, params))
1526 return -EINVAL;
1527
1528 /*
1529 * Write configuration to register.
1530 */
181d6902
ID		 1531 rt2400pci_config_cw(rt2x00dev,
1532 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1533
1534 return 0;
1535}
1536
1537static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1538{
1539 struct rt2x00_dev *rt2x00dev = hw->priv;
1540 u64 tsf;
1541 u32 reg;
1542
1543 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1544 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1545 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1546 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1547
1548 return tsf;
1549}
1550
95ea3627
ID		 1551static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1552{
1553 struct rt2x00_dev *rt2x00dev = hw->priv;
1554 u32 reg;
1555
1556 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1557 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1558}
1559
1560static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1561 .tx = rt2x00mac_tx,
4150c572
JB		 1562 .start = rt2x00mac_start,
1563 .stop = rt2x00mac_stop,
95ea3627
ID		 1564 .add_interface = rt2x00mac_add_interface,
1565 .remove_interface = rt2x00mac_remove_interface,
1566 .config = rt2x00mac_config,
1567 .config_interface = rt2x00mac_config_interface,
3a643d24 1568 .configure_filter = rt2x00mac_configure_filter,
95ea3627 1569 .get_stats = rt2x00mac_get_stats,
471b3efd 1570 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1571 .conf_tx = rt2400pci_conf_tx,
1572 .get_tx_stats = rt2x00mac_get_tx_stats,
1573 .get_tsf = rt2400pci_get_tsf,
95ea3627
ID		 1574 .tx_last_beacon = rt2400pci_tx_last_beacon,
1575};
1576
1577static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1578 .irq_handler = rt2400pci_interrupt,
1579 .probe_hw = rt2400pci_probe_hw,
1580 .initialize = rt2x00pci_initialize,
1581 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1582 .init_rxentry = rt2400pci_init_rxentry,
1583 .init_txentry = rt2400pci_init_txentry,
95ea3627 1584 .set_device_state = rt2400pci_set_device_state,
95ea3627 1585 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1586 .link_stats = rt2400pci_link_stats,
1587 .reset_tuner = rt2400pci_reset_tuner,
1588 .link_tuner = rt2400pci_link_tuner,
1589 .write_tx_desc = rt2400pci_write_tx_desc,
1590 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1591 .write_beacon = rt2400pci_write_beacon,
95ea3627
ID		 1592 .kick_tx_queue = rt2400pci_kick_tx_queue,
1593 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1594 .config_filter = rt2400pci_config_filter,
6bb40dd1 1595 .config_intf = rt2400pci_config_intf,
72810379 1596 .config_erp = rt2400pci_config_erp,
e4ea1c40 1597 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1598 .config = rt2400pci_config,
1599};
1600
181d6902
ID		 1601static const struct data_queue_desc rt2400pci_queue_rx = {
1602 .entry_num = RX_ENTRIES,
1603 .data_size = DATA_FRAME_SIZE,
1604 .desc_size = RXD_DESC_SIZE,
b8be63ff 1605 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1606};
1607
1608static const struct data_queue_desc rt2400pci_queue_tx = {
1609 .entry_num = TX_ENTRIES,
1610 .data_size = DATA_FRAME_SIZE,
1611 .desc_size = TXD_DESC_SIZE,
b8be63ff 1612 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1613};
1614
1615static const struct data_queue_desc rt2400pci_queue_bcn = {
1616 .entry_num = BEACON_ENTRIES,
1617 .data_size = MGMT_FRAME_SIZE,
1618 .desc_size = TXD_DESC_SIZE,
b8be63ff 1619 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1620};
1621
1622static const struct data_queue_desc rt2400pci_queue_atim = {
1623 .entry_num = ATIM_ENTRIES,
1624 .data_size = DATA_FRAME_SIZE,
1625 .desc_size = TXD_DESC_SIZE,
b8be63ff 1626 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1627};
1628
95ea3627 1629static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1630 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1631 .max_sta_intf = 1,
1632 .max_ap_intf = 1,
95ea3627
ID		 1633 .eeprom_size = EEPROM_SIZE,
1634 .rf_size = RF_SIZE,
61448f88 1635 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 1636 .rx = &rt2400pci_queue_rx,
1637 .tx = &rt2400pci_queue_tx,
1638 .bcn = &rt2400pci_queue_bcn,
1639 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1640 .lib = &rt2400pci_rt2x00_ops,
1641 .hw = &rt2400pci_mac80211_ops,
1642#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1643 .debugfs = &rt2400pci_rt2x00debug,
1644#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1645};
1646
1647/*
1648 * RT2400pci module information.
1649 */
1650static struct pci_device_id rt2400pci_device_table[] = {
1651 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1652 { 0, }
1653};
1654
1655MODULE_AUTHOR(DRV_PROJECT);
1656MODULE_VERSION(DRV_VERSION);
1657MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1658MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1659MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1660MODULE_LICENSE("GPL");
1661
1662static struct pci_driver rt2400pci_driver = {
2360157c 1663 .name = KBUILD_MODNAME,
95ea3627
ID		 1664 .id_table = rt2400pci_device_table,
1665 .probe = rt2x00pci_probe,
1666 .remove = __devexit_p(rt2x00pci_remove),
1667 .suspend = rt2x00pci_suspend,
1668 .resume = rt2x00pci_resume,
1669};
1670
1671static int __init rt2400pci_init(void)
1672{
1673 return pci_register_driver(&rt2400pci_driver);
1674}
1675
1676static void __exit rt2400pci_exit(void)
1677{
1678 pci_unregister_driver(&rt2400pci_driver);
1679}
1680
1681module_init(rt2400pci_init);
1682module_exit(rt2400pci_exit);
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