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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2400pci | |
23 | Abstract: Data structures and registers for the rt2400pci module. | |
24 | Supported chipsets: RT2460. | |
25 | */ | |
26 | ||
27 | #ifndef RT2400PCI_H | |
28 | #define RT2400PCI_H | |
29 | ||
30 | /* | |
31 | * RF chip defines. | |
32 | */ | |
33 | #define RF2420 0x0000 | |
34 | #define RF2421 0x0001 | |
35 | ||
36 | /* | |
37 | * Signal information. | |
38 | * Defaul offset is required for RSSI <-> dBm conversion. | |
39 | */ | |
40 | #define MAX_SIGNAL 100 | |
41 | #define MAX_RX_SSI -1 | |
42 | #define DEFAULT_RSSI_OFFSET 100 | |
43 | ||
44 | /* | |
45 | * Register layout information. | |
46 | */ | |
47 | #define CSR_REG_BASE 0x0000 | |
48 | #define CSR_REG_SIZE 0x014c | |
49 | #define EEPROM_BASE 0x0000 | |
50 | #define EEPROM_SIZE 0x0100 | |
51 | #define BBP_SIZE 0x0020 | |
52 | #define RF_SIZE 0x0010 | |
53 | ||
54 | /* | |
55 | * Control/Status Registers(CSR). | |
56 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
57 | */ | |
58 | ||
59 | /* | |
60 | * CSR0: ASIC revision number. | |
61 | */ | |
62 | #define CSR0 0x0000 | |
63 | ||
64 | /* | |
65 | * CSR1: System control register. | |
66 | * SOFT_RESET: Software reset, 1: reset, 0: normal. | |
67 | * BBP_RESET: Hardware reset, 1: reset, 0, release. | |
68 | * HOST_READY: Host ready after initialization. | |
69 | */ | |
70 | #define CSR1 0x0004 | |
71 | #define CSR1_SOFT_RESET FIELD32(0x00000001) | |
72 | #define CSR1_BBP_RESET FIELD32(0x00000002) | |
73 | #define CSR1_HOST_READY FIELD32(0x00000004) | |
74 | ||
75 | /* | |
76 | * CSR2: System admin status register (invalid). | |
77 | */ | |
78 | #define CSR2 0x0008 | |
79 | ||
80 | /* | |
81 | * CSR3: STA MAC address register 0. | |
82 | */ | |
83 | #define CSR3 0x000c | |
84 | #define CSR3_BYTE0 FIELD32(0x000000ff) | |
85 | #define CSR3_BYTE1 FIELD32(0x0000ff00) | |
86 | #define CSR3_BYTE2 FIELD32(0x00ff0000) | |
87 | #define CSR3_BYTE3 FIELD32(0xff000000) | |
88 | ||
89 | /* | |
90 | * CSR4: STA MAC address register 1. | |
91 | */ | |
92 | #define CSR4 0x0010 | |
93 | #define CSR4_BYTE4 FIELD32(0x000000ff) | |
94 | #define CSR4_BYTE5 FIELD32(0x0000ff00) | |
95 | ||
96 | /* | |
97 | * CSR5: BSSID register 0. | |
98 | */ | |
99 | #define CSR5 0x0014 | |
100 | #define CSR5_BYTE0 FIELD32(0x000000ff) | |
101 | #define CSR5_BYTE1 FIELD32(0x0000ff00) | |
102 | #define CSR5_BYTE2 FIELD32(0x00ff0000) | |
103 | #define CSR5_BYTE3 FIELD32(0xff000000) | |
104 | ||
105 | /* | |
106 | * CSR6: BSSID register 1. | |
107 | */ | |
108 | #define CSR6 0x0018 | |
109 | #define CSR6_BYTE4 FIELD32(0x000000ff) | |
110 | #define CSR6_BYTE5 FIELD32(0x0000ff00) | |
111 | ||
112 | /* | |
113 | * CSR7: Interrupt source register. | |
114 | * Write 1 to clear interrupt. | |
115 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
116 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
117 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
118 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
119 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
120 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
121 | * RXDONE: Receive done interrupt. | |
122 | */ | |
123 | #define CSR7 0x001c | |
124 | #define CSR7_TBCN_EXPIRE FIELD32(0x00000001) | |
125 | #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) | |
126 | #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) | |
127 | #define CSR7_TXDONE_TXRING FIELD32(0x00000008) | |
128 | #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) | |
129 | #define CSR7_TXDONE_PRIORING FIELD32(0x00000020) | |
130 | #define CSR7_RXDONE FIELD32(0x00000040) | |
131 | ||
132 | /* | |
133 | * CSR8: Interrupt mask register. | |
134 | * Write 1 to mask interrupt. | |
135 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
136 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
137 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
138 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
139 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
140 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
141 | * RXDONE: Receive done interrupt. | |
142 | */ | |
143 | #define CSR8 0x0020 | |
144 | #define CSR8_TBCN_EXPIRE FIELD32(0x00000001) | |
145 | #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) | |
146 | #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) | |
147 | #define CSR8_TXDONE_TXRING FIELD32(0x00000008) | |
148 | #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) | |
149 | #define CSR8_TXDONE_PRIORING FIELD32(0x00000020) | |
150 | #define CSR8_RXDONE FIELD32(0x00000040) | |
151 | ||
152 | /* | |
153 | * CSR9: Maximum frame length register. | |
154 | * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. | |
155 | */ | |
156 | #define CSR9 0x0024 | |
157 | #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) | |
158 | ||
159 | /* | |
160 | * CSR11: Back-off control register. | |
161 | * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). | |
162 | * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). | |
163 | * SLOT_TIME: Slot time, default is 20us for 802.11b. | |
164 | * LONG_RETRY: Long retry count. | |
165 | * SHORT_RETRY: Short retry count. | |
166 | */ | |
167 | #define CSR11 0x002c | |
168 | #define CSR11_CWMIN FIELD32(0x0000000f) | |
169 | #define CSR11_CWMAX FIELD32(0x000000f0) | |
170 | #define CSR11_SLOT_TIME FIELD32(0x00001f00) | |
171 | #define CSR11_LONG_RETRY FIELD32(0x00ff0000) | |
172 | #define CSR11_SHORT_RETRY FIELD32(0xff000000) | |
173 | ||
174 | /* | |
175 | * CSR12: Synchronization configuration register 0. | |
176 | * All units in 1/16 TU. | |
177 | * BEACON_INTERVAL: Beacon interval, default is 100 TU. | |
178 | * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU. | |
179 | */ | |
180 | #define CSR12 0x0030 | |
181 | #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) | |
182 | #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) | |
183 | ||
184 | /* | |
185 | * CSR13: Synchronization configuration register 1. | |
186 | * All units in 1/16 TU. | |
187 | * ATIMW_DURATION: Atim window duration. | |
188 | * CFP_PERIOD: Cfp period, default is 0 TU. | |
189 | */ | |
190 | #define CSR13 0x0034 | |
191 | #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) | |
192 | #define CSR13_CFP_PERIOD FIELD32(0x00ff0000) | |
193 | ||
194 | /* | |
195 | * CSR14: Synchronization control register. | |
196 | * TSF_COUNT: Enable tsf auto counting. | |
197 | * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. | |
198 | * TBCN: Enable tbcn with reload value. | |
199 | * TCFP: Enable tcfp & cfp / cp switching. | |
200 | * TATIMW: Enable tatimw & atim window switching. | |
201 | * BEACON_GEN: Enable beacon generator. | |
202 | * CFP_COUNT_PRELOAD: Cfp count preload value. | |
203 | * TBCM_PRELOAD: Tbcn preload value in units of 64us. | |
204 | */ | |
205 | #define CSR14 0x0038 | |
206 | #define CSR14_TSF_COUNT FIELD32(0x00000001) | |
207 | #define CSR14_TSF_SYNC FIELD32(0x00000006) | |
208 | #define CSR14_TBCN FIELD32(0x00000008) | |
209 | #define CSR14_TCFP FIELD32(0x00000010) | |
210 | #define CSR14_TATIMW FIELD32(0x00000020) | |
211 | #define CSR14_BEACON_GEN FIELD32(0x00000040) | |
212 | #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) | |
213 | #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) | |
214 | ||
215 | /* | |
216 | * CSR15: Synchronization status register. | |
217 | * CFP: ASIC is in contention-free period. | |
218 | * ATIMW: ASIC is in ATIM window. | |
219 | * BEACON_SENT: Beacon is send. | |
220 | */ | |
221 | #define CSR15 0x003c | |
222 | #define CSR15_CFP FIELD32(0x00000001) | |
223 | #define CSR15_ATIMW FIELD32(0x00000002) | |
224 | #define CSR15_BEACON_SENT FIELD32(0x00000004) | |
225 | ||
226 | /* | |
227 | * CSR16: TSF timer register 0. | |
228 | */ | |
229 | #define CSR16 0x0040 | |
230 | #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) | |
231 | ||
232 | /* | |
233 | * CSR17: TSF timer register 1. | |
234 | */ | |
235 | #define CSR17 0x0044 | |
236 | #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) | |
237 | ||
238 | /* | |
239 | * CSR18: IFS timer register 0. | |
240 | * SIFS: Sifs, default is 10 us. | |
241 | * PIFS: Pifs, default is 30 us. | |
242 | */ | |
243 | #define CSR18 0x0048 | |
244 | #define CSR18_SIFS FIELD32(0x0000ffff) | |
245 | #define CSR18_PIFS FIELD32(0xffff0000) | |
246 | ||
247 | /* | |
248 | * CSR19: IFS timer register 1. | |
249 | * DIFS: Difs, default is 50 us. | |
250 | * EIFS: Eifs, default is 364 us. | |
251 | */ | |
252 | #define CSR19 0x004c | |
253 | #define CSR19_DIFS FIELD32(0x0000ffff) | |
254 | #define CSR19_EIFS FIELD32(0xffff0000) | |
255 | ||
256 | /* | |
257 | * CSR20: Wakeup timer register. | |
258 | * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. | |
259 | * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. | |
260 | * AUTOWAKE: Enable auto wakeup / sleep mechanism. | |
261 | */ | |
262 | #define CSR20 0x0050 | |
263 | #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) | |
264 | #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) | |
265 | #define CSR20_AUTOWAKE FIELD32(0x01000000) | |
266 | ||
267 | /* | |
268 | * CSR21: EEPROM control register. | |
269 | * RELOAD: Write 1 to reload eeprom content. | |
270 | * TYPE_93C46: 1: 93c46, 0:93c66. | |
271 | */ | |
272 | #define CSR21 0x0054 | |
273 | #define CSR21_RELOAD FIELD32(0x00000001) | |
274 | #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) | |
275 | #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) | |
276 | #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) | |
277 | #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) | |
278 | #define CSR21_TYPE_93C46 FIELD32(0x00000020) | |
279 | ||
280 | /* | |
281 | * CSR22: CFP control register. | |
282 | * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. | |
283 | * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. | |
284 | */ | |
285 | #define CSR22 0x0058 | |
286 | #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) | |
287 | #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) | |
288 | ||
289 | /* | |
290 | * Transmit related CSRs. | |
291 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
292 | */ | |
293 | ||
294 | /* | |
295 | * TXCSR0: TX Control Register. | |
296 | * KICK_TX: Kick tx ring. | |
297 | * KICK_ATIM: Kick atim ring. | |
298 | * KICK_PRIO: Kick priority ring. | |
299 | * ABORT: Abort all transmit related ring operation. | |
300 | */ | |
301 | #define TXCSR0 0x0060 | |
302 | #define TXCSR0_KICK_TX FIELD32(0x00000001) | |
303 | #define TXCSR0_KICK_ATIM FIELD32(0x00000002) | |
304 | #define TXCSR0_KICK_PRIO FIELD32(0x00000004) | |
305 | #define TXCSR0_ABORT FIELD32(0x00000008) | |
306 | ||
307 | /* | |
308 | * TXCSR1: TX Configuration Register. | |
309 | * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. | |
310 | * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. | |
311 | * TSF_OFFSET: Insert tsf offset. | |
312 | * AUTORESPONDER: Enable auto responder which include ack & cts. | |
313 | */ | |
314 | #define TXCSR1 0x0064 | |
315 | #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) | |
316 | #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) | |
317 | #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) | |
318 | #define TXCSR1_AUTORESPONDER FIELD32(0x01000000) | |
319 | ||
320 | /* | |
321 | * TXCSR2: Tx descriptor configuration register. | |
322 | * TXD_SIZE: Tx descriptor size, default is 48. | |
323 | * NUM_TXD: Number of tx entries in ring. | |
324 | * NUM_ATIM: Number of atim entries in ring. | |
325 | * NUM_PRIO: Number of priority entries in ring. | |
326 | */ | |
327 | #define TXCSR2 0x0068 | |
328 | #define TXCSR2_TXD_SIZE FIELD32(0x000000ff) | |
329 | #define TXCSR2_NUM_TXD FIELD32(0x0000ff00) | |
330 | #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) | |
331 | #define TXCSR2_NUM_PRIO FIELD32(0xff000000) | |
332 | ||
333 | /* | |
334 | * TXCSR3: TX Ring Base address register. | |
335 | */ | |
336 | #define TXCSR3 0x006c | |
337 | #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) | |
338 | ||
339 | /* | |
340 | * TXCSR4: TX Atim Ring Base address register. | |
341 | */ | |
342 | #define TXCSR4 0x0070 | |
343 | #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) | |
344 | ||
345 | /* | |
346 | * TXCSR5: TX Prio Ring Base address register. | |
347 | */ | |
348 | #define TXCSR5 0x0074 | |
349 | #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) | |
350 | ||
351 | /* | |
352 | * TXCSR6: Beacon Base address register. | |
353 | */ | |
354 | #define TXCSR6 0x0078 | |
355 | #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) | |
356 | ||
357 | /* | |
358 | * TXCSR7: Auto responder control register. | |
359 | * AR_POWERMANAGEMENT: Auto responder power management bit. | |
360 | */ | |
361 | #define TXCSR7 0x007c | |
362 | #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) | |
363 | ||
364 | /* | |
365 | * Receive related CSRs. | |
366 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
367 | */ | |
368 | ||
369 | /* | |
370 | * RXCSR0: RX Control Register. | |
371 | * DISABLE_RX: Disable rx engine. | |
372 | * DROP_CRC: Drop crc error. | |
373 | * DROP_PHYSICAL: Drop physical error. | |
374 | * DROP_CONTROL: Drop control frame. | |
375 | * DROP_NOT_TO_ME: Drop not to me unicast frame. | |
376 | * DROP_TODS: Drop frame tods bit is true. | |
377 | * DROP_VERSION_ERROR: Drop version error frame. | |
378 | * PASS_CRC: Pass all packets with crc attached. | |
379 | */ | |
380 | #define RXCSR0 0x0080 | |
381 | #define RXCSR0_DISABLE_RX FIELD32(0x00000001) | |
382 | #define RXCSR0_DROP_CRC FIELD32(0x00000002) | |
383 | #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) | |
384 | #define RXCSR0_DROP_CONTROL FIELD32(0x00000008) | |
385 | #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) | |
386 | #define RXCSR0_DROP_TODS FIELD32(0x00000020) | |
387 | #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) | |
388 | #define RXCSR0_PASS_CRC FIELD32(0x00000080) | |
389 | ||
390 | /* | |
391 | * RXCSR1: RX descriptor configuration register. | |
392 | * RXD_SIZE: Rx descriptor size, default is 32b. | |
393 | * NUM_RXD: Number of rx entries in ring. | |
394 | */ | |
395 | #define RXCSR1 0x0084 | |
396 | #define RXCSR1_RXD_SIZE FIELD32(0x000000ff) | |
397 | #define RXCSR1_NUM_RXD FIELD32(0x0000ff00) | |
398 | ||
399 | /* | |
400 | * RXCSR2: RX Ring base address register. | |
401 | */ | |
402 | #define RXCSR2 0x0088 | |
403 | #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) | |
404 | ||
405 | /* | |
406 | * RXCSR3: BBP ID register for Rx operation. | |
407 | * BBP_ID#: BBP register # id. | |
408 | * BBP_ID#_VALID: BBP register # id is valid or not. | |
409 | */ | |
410 | #define RXCSR3 0x0090 | |
411 | #define RXCSR3_BBP_ID0 FIELD32(0x0000007f) | |
412 | #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) | |
413 | #define RXCSR3_BBP_ID1 FIELD32(0x00007f00) | |
414 | #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) | |
415 | #define RXCSR3_BBP_ID2 FIELD32(0x007f0000) | |
416 | #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) | |
417 | #define RXCSR3_BBP_ID3 FIELD32(0x7f000000) | |
418 | #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) | |
419 | ||
420 | /* | |
421 | * RXCSR4: BBP ID register for Rx operation. | |
422 | * BBP_ID#: BBP register # id. | |
423 | * BBP_ID#_VALID: BBP register # id is valid or not. | |
424 | */ | |
425 | #define RXCSR4 0x0094 | |
426 | #define RXCSR4_BBP_ID4 FIELD32(0x0000007f) | |
427 | #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080) | |
428 | #define RXCSR4_BBP_ID5 FIELD32(0x00007f00) | |
429 | #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000) | |
430 | ||
431 | /* | |
432 | * ARCSR0: Auto Responder PLCP config register 0. | |
433 | * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. | |
434 | * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. | |
435 | */ | |
436 | #define ARCSR0 0x0098 | |
437 | #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff) | |
438 | #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00) | |
439 | #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000) | |
440 | #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000) | |
441 | ||
442 | /* | |
443 | * ARCSR1: Auto Responder PLCP config register 1. | |
444 | * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. | |
445 | * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. | |
446 | */ | |
447 | #define ARCSR1 0x009c | |
448 | #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) | |
449 | #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) | |
450 | #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) | |
451 | #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) | |
452 | ||
453 | /* | |
454 | * Miscellaneous Registers. | |
455 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
456 | */ | |
457 | ||
458 | /* | |
459 | * PCICSR: PCI control register. | |
460 | * BIG_ENDIAN: 1: big endian, 0: little endian. | |
461 | * RX_TRESHOLD: Rx threshold in dw to start pci access | |
462 | * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. | |
463 | * TX_TRESHOLD: Tx threshold in dw to start pci access | |
464 | * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. | |
465 | * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. | |
466 | * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. | |
467 | */ | |
468 | #define PCICSR 0x008c | |
469 | #define PCICSR_BIG_ENDIAN FIELD32(0x00000001) | |
470 | #define PCICSR_RX_TRESHOLD FIELD32(0x00000006) | |
471 | #define PCICSR_TX_TRESHOLD FIELD32(0x00000018) | |
472 | #define PCICSR_BURST_LENTH FIELD32(0x00000060) | |
473 | #define PCICSR_ENABLE_CLK FIELD32(0x00000080) | |
474 | ||
475 | /* | |
476 | * CNT0: FCS error count. | |
477 | * FCS_ERROR: FCS error count, cleared when read. | |
478 | */ | |
479 | #define CNT0 0x00a0 | |
480 | #define CNT0_FCS_ERROR FIELD32(0x0000ffff) | |
481 | ||
482 | /* | |
483 | * Statistic Register. | |
484 | * CNT1: PLCP error count. | |
485 | * CNT2: Long error count. | |
486 | * CNT3: CCA false alarm count. | |
487 | * CNT4: Rx FIFO overflow count. | |
488 | * CNT5: Tx FIFO underrun count. | |
489 | */ | |
490 | #define TIMECSR2 0x00a8 | |
491 | #define CNT1 0x00ac | |
492 | #define CNT2 0x00b0 | |
493 | #define TIMECSR3 0x00b4 | |
494 | #define CNT3 0x00b8 | |
495 | #define CNT4 0x00bc | |
496 | #define CNT5 0x00c0 | |
497 | ||
498 | /* | |
499 | * Baseband Control Register. | |
500 | */ | |
501 | ||
502 | /* | |
503 | * PWRCSR0: Power mode configuration register. | |
504 | */ | |
505 | #define PWRCSR0 0x00c4 | |
506 | ||
507 | /* | |
508 | * Power state transition time registers. | |
509 | */ | |
510 | #define PSCSR0 0x00c8 | |
511 | #define PSCSR1 0x00cc | |
512 | #define PSCSR2 0x00d0 | |
513 | #define PSCSR3 0x00d4 | |
514 | ||
515 | /* | |
516 | * PWRCSR1: Manual power control / status register. | |
517 | * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. | |
518 | * SET_STATE: Set state. Write 1 to trigger, self cleared. | |
519 | * BBP_DESIRE_STATE: BBP desired state. | |
520 | * RF_DESIRE_STATE: RF desired state. | |
521 | * BBP_CURR_STATE: BBP current state. | |
522 | * RF_CURR_STATE: RF current state. | |
523 | * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. | |
524 | */ | |
525 | #define PWRCSR1 0x00d8 | |
526 | #define PWRCSR1_SET_STATE FIELD32(0x00000001) | |
527 | #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) | |
528 | #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) | |
529 | #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) | |
530 | #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) | |
531 | #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) | |
532 | ||
533 | /* | |
534 | * TIMECSR: Timer control register. | |
535 | * US_COUNT: 1 us timer count in units of clock cycles. | |
536 | * US_64_COUNT: 64 us timer count in units of 1 us timer. | |
537 | * BEACON_EXPECT: Beacon expect window. | |
538 | */ | |
539 | #define TIMECSR 0x00dc | |
540 | #define TIMECSR_US_COUNT FIELD32(0x000000ff) | |
541 | #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) | |
542 | #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) | |
543 | ||
544 | /* | |
545 | * MACCSR0: MAC configuration register 0. | |
546 | */ | |
547 | #define MACCSR0 0x00e0 | |
548 | ||
549 | /* | |
550 | * MACCSR1: MAC configuration register 1. | |
551 | * KICK_RX: Kick one-shot rx in one-shot rx mode. | |
552 | * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. | |
553 | * BBPRX_RESET_MODE: Ralink bbp rx reset mode. | |
554 | * AUTO_TXBBP: Auto tx logic access bbp control register. | |
555 | * AUTO_RXBBP: Auto rx logic access bbp control register. | |
556 | * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. | |
557 | * INTERSIL_IF: Intersil if calibration pin. | |
558 | */ | |
559 | #define MACCSR1 0x00e4 | |
560 | #define MACCSR1_KICK_RX FIELD32(0x00000001) | |
561 | #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) | |
562 | #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) | |
563 | #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) | |
564 | #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) | |
565 | #define MACCSR1_LOOPBACK FIELD32(0x00000060) | |
566 | #define MACCSR1_INTERSIL_IF FIELD32(0x00000080) | |
567 | ||
568 | /* | |
569 | * RALINKCSR: Ralink Rx auto-reset BBCR. | |
570 | * AR_BBP_DATA#: Auto reset BBP register # data. | |
571 | * AR_BBP_ID#: Auto reset BBP register # id. | |
572 | */ | |
573 | #define RALINKCSR 0x00e8 | |
574 | #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) | |
575 | #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00) | |
576 | #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) | |
577 | #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000) | |
578 | ||
579 | /* | |
580 | * BCNCSR: Beacon interval control register. | |
581 | * CHANGE: Write one to change beacon interval. | |
582 | * DELTATIME: The delta time value. | |
583 | * NUM_BEACON: Number of beacon according to mode. | |
584 | * MODE: Please refer to asic specs. | |
585 | * PLUS: Plus or minus delta time value. | |
586 | */ | |
587 | #define BCNCSR 0x00ec | |
588 | #define BCNCSR_CHANGE FIELD32(0x00000001) | |
589 | #define BCNCSR_DELTATIME FIELD32(0x0000001e) | |
590 | #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) | |
591 | #define BCNCSR_MODE FIELD32(0x00006000) | |
592 | #define BCNCSR_PLUS FIELD32(0x00008000) | |
593 | ||
594 | /* | |
595 | * BBP / RF / IF Control Register. | |
596 | */ | |
597 | ||
598 | /* | |
599 | * BBPCSR: BBP serial control register. | |
600 | * VALUE: Register value to program into BBP. | |
601 | * REGNUM: Selected BBP register. | |
602 | * BUSY: 1: asic is busy execute BBP programming. | |
603 | * WRITE_CONTROL: 1: write BBP, 0: read BBP. | |
604 | */ | |
605 | #define BBPCSR 0x00f0 | |
606 | #define BBPCSR_VALUE FIELD32(0x000000ff) | |
607 | #define BBPCSR_REGNUM FIELD32(0x00007f00) | |
608 | #define BBPCSR_BUSY FIELD32(0x00008000) | |
609 | #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) | |
610 | ||
611 | /* | |
612 | * RFCSR: RF serial control register. | |
613 | * VALUE: Register value + id to program into rf/if. | |
614 | * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). | |
615 | * IF_SELECT: Chip to program: 0: rf, 1: if. | |
616 | * PLL_LD: Rf pll_ld status. | |
617 | * BUSY: 1: asic is busy execute rf programming. | |
618 | */ | |
619 | #define RFCSR 0x00f4 | |
620 | #define RFCSR_VALUE FIELD32(0x00ffffff) | |
621 | #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) | |
622 | #define RFCSR_IF_SELECT FIELD32(0x20000000) | |
623 | #define RFCSR_PLL_LD FIELD32(0x40000000) | |
624 | #define RFCSR_BUSY FIELD32(0x80000000) | |
625 | ||
626 | /* | |
627 | * LEDCSR: LED control register. | |
628 | * ON_PERIOD: On period, default 70ms. | |
629 | * OFF_PERIOD: Off period, default 30ms. | |
630 | * LINK: 0: linkoff, 1: linkup. | |
631 | * ACTIVITY: 0: idle, 1: active. | |
632 | */ | |
633 | #define LEDCSR 0x00f8 | |
634 | #define LEDCSR_ON_PERIOD FIELD32(0x000000ff) | |
635 | #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) | |
636 | #define LEDCSR_LINK FIELD32(0x00010000) | |
637 | #define LEDCSR_ACTIVITY FIELD32(0x00020000) | |
638 | ||
639 | /* | |
640 | * ASIC pointer information. | |
641 | * RXPTR: Current RX ring address. | |
642 | * TXPTR: Current Tx ring address. | |
643 | * PRIPTR: Current Priority ring address. | |
644 | * ATIMPTR: Current ATIM ring address. | |
645 | */ | |
646 | #define RXPTR 0x0100 | |
647 | #define TXPTR 0x0104 | |
648 | #define PRIPTR 0x0108 | |
649 | #define ATIMPTR 0x010c | |
650 | ||
651 | /* | |
652 | * GPIO and others. | |
653 | */ | |
654 | ||
655 | /* | |
656 | * GPIOCSR: GPIO control register. | |
657 | */ | |
658 | #define GPIOCSR 0x0120 | |
659 | #define GPIOCSR_BIT0 FIELD32(0x00000001) | |
660 | #define GPIOCSR_BIT1 FIELD32(0x00000002) | |
661 | #define GPIOCSR_BIT2 FIELD32(0x00000004) | |
662 | #define GPIOCSR_BIT3 FIELD32(0x00000008) | |
663 | #define GPIOCSR_BIT4 FIELD32(0x00000010) | |
664 | #define GPIOCSR_BIT5 FIELD32(0x00000020) | |
665 | #define GPIOCSR_BIT6 FIELD32(0x00000040) | |
666 | #define GPIOCSR_BIT7 FIELD32(0x00000080) | |
667 | ||
668 | /* | |
669 | * BBPPCSR: BBP Pin control register. | |
670 | */ | |
671 | #define BBPPCSR 0x0124 | |
672 | ||
673 | /* | |
674 | * BCNCSR1: Tx BEACON offset time control register. | |
675 | * PRELOAD: Beacon timer offset in units of usec. | |
676 | */ | |
677 | #define BCNCSR1 0x0130 | |
678 | #define BCNCSR1_PRELOAD FIELD32(0x0000ffff) | |
679 | ||
680 | /* | |
681 | * MACCSR2: TX_PE to RX_PE turn-around time control register | |
682 | * DELAY: RX_PE low width, in units of pci clock cycle. | |
683 | */ | |
684 | #define MACCSR2 0x0134 | |
685 | #define MACCSR2_DELAY FIELD32(0x000000ff) | |
686 | ||
687 | /* | |
688 | * ARCSR2: 1 Mbps ACK/CTS PLCP. | |
689 | */ | |
690 | #define ARCSR2 0x013c | |
691 | #define ARCSR2_SIGNAL FIELD32(0x000000ff) | |
692 | #define ARCSR2_SERVICE FIELD32(0x0000ff00) | |
693 | #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000) | |
694 | #define ARCSR2_LENGTH FIELD32(0xffff0000) | |
695 | ||
696 | /* | |
697 | * ARCSR3: 2 Mbps ACK/CTS PLCP. | |
698 | */ | |
699 | #define ARCSR3 0x0140 | |
700 | #define ARCSR3_SIGNAL FIELD32(0x000000ff) | |
701 | #define ARCSR3_SERVICE FIELD32(0x0000ff00) | |
702 | #define ARCSR3_LENGTH FIELD32(0xffff0000) | |
703 | ||
704 | /* | |
705 | * ARCSR4: 5.5 Mbps ACK/CTS PLCP. | |
706 | */ | |
707 | #define ARCSR4 0x0144 | |
708 | #define ARCSR4_SIGNAL FIELD32(0x000000ff) | |
709 | #define ARCSR4_SERVICE FIELD32(0x0000ff00) | |
710 | #define ARCSR4_LENGTH FIELD32(0xffff0000) | |
711 | ||
712 | /* | |
713 | * ARCSR5: 11 Mbps ACK/CTS PLCP. | |
714 | */ | |
715 | #define ARCSR5 0x0148 | |
716 | #define ARCSR5_SIGNAL FIELD32(0x000000ff) | |
717 | #define ARCSR5_SERVICE FIELD32(0x0000ff00) | |
718 | #define ARCSR5_LENGTH FIELD32(0xffff0000) | |
719 | ||
720 | /* | |
721 | * BBP registers. | |
722 | * The wordsize of the BBP is 8 bits. | |
723 | */ | |
724 | ||
725 | /* | |
726 | * R1: TX antenna control | |
727 | */ | |
728 | #define BBP_R1_TX_ANTENNA FIELD8(0x03) | |
729 | ||
730 | /* | |
731 | * R4: RX antenna control | |
732 | */ | |
733 | #define BBP_R4_RX_ANTENNA FIELD8(0x06) | |
734 | ||
735 | /* | |
736 | * RF registers | |
737 | */ | |
738 | ||
739 | /* | |
740 | * RF 1 | |
741 | */ | |
742 | #define RF1_TUNER FIELD32(0x00020000) | |
743 | ||
744 | /* | |
745 | * RF 3 | |
746 | */ | |
747 | #define RF3_TUNER FIELD32(0x00000100) | |
748 | #define RF3_TXPOWER FIELD32(0x00003e00) | |
749 | ||
750 | /* | |
751 | * EEPROM content. | |
752 | * The wordsize of the EEPROM is 16 bits. | |
753 | */ | |
754 | ||
755 | /* | |
756 | * HW MAC address. | |
757 | */ | |
758 | #define EEPROM_MAC_ADDR_0 0x0002 | |
759 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
760 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
761 | #define EEPROM_MAC_ADDR1 0x0003 | |
762 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
763 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
764 | #define EEPROM_MAC_ADDR_2 0x0004 | |
765 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
766 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
767 | ||
768 | /* | |
769 | * EEPROM antenna. | |
770 | * ANTENNA_NUM: Number of antenna's. | |
771 | * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
772 | * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
773 | * RF_TYPE: Rf_type of this adapter. | |
774 | * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. | |
775 | * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning. | |
776 | * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. | |
777 | */ | |
778 | #define EEPROM_ANTENNA 0x0b | |
779 | #define EEPROM_ANTENNA_NUM FIELD16(0x0003) | |
780 | #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) | |
781 | #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) | |
782 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040) | |
783 | #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180) | |
784 | #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200) | |
785 | #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) | |
786 | ||
787 | /* | |
788 | * EEPROM BBP. | |
789 | */ | |
790 | #define EEPROM_BBP_START 0x0c | |
791 | #define EEPROM_BBP_SIZE 7 | |
792 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
793 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
794 | ||
795 | /* | |
796 | * EEPROM TXPOWER | |
797 | */ | |
798 | #define EEPROM_TXPOWER_START 0x13 | |
799 | #define EEPROM_TXPOWER_SIZE 7 | |
800 | #define EEPROM_TXPOWER_1 FIELD16(0x00ff) | |
801 | #define EEPROM_TXPOWER_2 FIELD16(0xff00) | |
802 | ||
803 | /* | |
804 | * DMA descriptor defines. | |
805 | */ | |
4bd7c452 ID |
806 | #define TXD_DESC_SIZE ( 8 * sizeof(__le32) ) |
807 | #define RXD_DESC_SIZE ( 8 * sizeof(__le32) ) | |
95ea3627 ID |
808 | |
809 | /* | |
810 | * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. | |
811 | */ | |
812 | ||
813 | /* | |
814 | * Word0 | |
815 | */ | |
816 | #define TXD_W0_OWNER_NIC FIELD32(0x00000001) | |
817 | #define TXD_W0_VALID FIELD32(0x00000002) | |
818 | #define TXD_W0_RESULT FIELD32(0x0000001c) | |
819 | #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) | |
820 | #define TXD_W0_MORE_FRAG FIELD32(0x00000100) | |
821 | #define TXD_W0_ACK FIELD32(0x00000200) | |
822 | #define TXD_W0_TIMESTAMP FIELD32(0x00000400) | |
823 | #define TXD_W0_RTS FIELD32(0x00000800) | |
824 | #define TXD_W0_IFS FIELD32(0x00006000) | |
825 | #define TXD_W0_RETRY_MODE FIELD32(0x00008000) | |
826 | #define TXD_W0_AGC FIELD32(0x00ff0000) | |
827 | #define TXD_W0_R2 FIELD32(0xff000000) | |
828 | ||
829 | /* | |
830 | * Word1 | |
831 | */ | |
832 | #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
833 | ||
834 | /* | |
835 | * Word2 | |
836 | */ | |
837 | #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) | |
838 | #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000) | |
839 | ||
840 | /* | |
841 | * Word3 & 4: PLCP information | |
49da2605 ID |
842 | * The PLCP values should be treated as if they were BBP values. |
843 | */ | |
844 | #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) | |
845 | #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00) | |
846 | #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000) | |
847 | #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000) | |
848 | #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000) | |
849 | #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000) | |
850 | ||
851 | #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff) | |
852 | #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00) | |
853 | #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000) | |
854 | #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000) | |
855 | #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000) | |
856 | #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000) | |
95ea3627 ID |
857 | |
858 | /* | |
859 | * Word5 | |
860 | */ | |
861 | #define TXD_W5_BBCR4 FIELD32(0x0000ffff) | |
862 | #define TXD_W5_AGC_REG FIELD32(0x007f0000) | |
863 | #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000) | |
864 | #define TXD_W5_XXX_REG FIELD32(0x7f000000) | |
865 | #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000) | |
866 | ||
867 | /* | |
868 | * Word6 | |
869 | */ | |
870 | #define TXD_W6_SK_BUFF FIELD32(0xffffffff) | |
871 | ||
872 | /* | |
873 | * Word7 | |
874 | */ | |
875 | #define TXD_W7_RESERVED FIELD32(0xffffffff) | |
876 | ||
877 | /* | |
878 | * RX descriptor format for RX Ring. | |
879 | */ | |
880 | ||
881 | /* | |
882 | * Word0 | |
883 | */ | |
884 | #define RXD_W0_OWNER_NIC FIELD32(0x00000001) | |
885 | #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) | |
886 | #define RXD_W0_MULTICAST FIELD32(0x00000004) | |
887 | #define RXD_W0_BROADCAST FIELD32(0x00000008) | |
888 | #define RXD_W0_MY_BSS FIELD32(0x00000010) | |
889 | #define RXD_W0_CRC_ERROR FIELD32(0x00000020) | |
890 | #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) | |
891 | #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000) | |
892 | ||
893 | /* | |
894 | * Word1 | |
895 | */ | |
896 | #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
897 | ||
898 | /* | |
899 | * Word2 | |
900 | */ | |
901 | #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) | |
902 | #define RXD_W2_SIGNAL FIELD32(0x00ff0000) | |
903 | #define RXD_W2_RSSI FIELD32(0xff000000) | |
904 | ||
905 | /* | |
906 | * Word3 | |
907 | */ | |
908 | #define RXD_W3_BBR2 FIELD32(0x000000ff) | |
909 | #define RXD_W3_BBR3 FIELD32(0x0000ff00) | |
910 | #define RXD_W3_BBR4 FIELD32(0x00ff0000) | |
911 | #define RXD_W3_BBR5 FIELD32(0xff000000) | |
912 | ||
913 | /* | |
914 | * Word4 | |
915 | */ | |
916 | #define RXD_W4_RX_END_TIME FIELD32(0xffffffff) | |
917 | ||
918 | /* | |
919 | * Word5 & 6 & 7: Reserved | |
920 | */ | |
921 | #define RXD_W5_RESERVED FIELD32(0xffffffff) | |
922 | #define RXD_W6_RESERVED FIELD32(0xffffffff) | |
923 | #define RXD_W7_RESERVED FIELD32(0xffffffff) | |
924 | ||
925 | /* | |
926 | * Macro's for converting txpower from EEPROM to dscape value | |
927 | * and from dscape value to register value. | |
928 | * NOTE: Logics in rt2400pci for txpower are reversed | |
929 | * compared to the other rt2x00 drivers. A higher txpower | |
930 | * value means that the txpower must be lowered. This is | |
931 | * important when converting the value coming from the | |
932 | * dscape stack to the rt2400 acceptable value. | |
933 | */ | |
934 | #define MIN_TXPOWER 31 | |
935 | #define MAX_TXPOWER 62 | |
936 | #define DEFAULT_TXPOWER 39 | |
937 | ||
938 | #define TXPOWER_FROM_DEV(__txpower) \ | |
939 | ({ \ | |
940 | ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \ | |
941 | ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \ | |
942 | (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER); \ | |
943 | }) | |
944 | ||
945 | #define TXPOWER_TO_DEV(__txpower) \ | |
946 | ({ \ | |
947 | (__txpower) += MIN_TXPOWER; \ | |
948 | ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER : \ | |
949 | (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER : \ | |
950 | (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER))); \ | |
951 | }) | |
952 | ||
953 | #endif /* RT2400PCI_H */ |