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rt2x00: Whitespace cleanup.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
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95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
c9c3b1a5
ID		 52#define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54#define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 56
0e14f6d3 57static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 58 const unsigned int word, const u8 value)
59{
60 u32 reg;
61
8ff48a8b
ID		 62 mutex_lock(&rt2x00dev->csr_mutex);
63
95ea3627 64 /*
c9c3b1a5
ID		 65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
95ea3627 67 */
c9c3b1a5
ID		 68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
8ff48a8b 77
8ff48a8b 78 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 79}
80
0e14f6d3 81static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 82 const unsigned int word, u8 *value)
83{
84 u32 reg;
85
8ff48a8b
ID		 86 mutex_lock(&rt2x00dev->csr_mutex);
87
95ea3627 88 /*
c9c3b1a5
ID		 89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95ea3627 95 */
c9c3b1a5
ID		 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 101
c9c3b1a5 102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 103
c9c3b1a5
ID		 104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
95ea3627
ID		 106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 108
109 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 110}
111
0e14f6d3 112static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 113 const unsigned int word, const u32 value)
114{
115 u32 reg;
95ea3627 116
8ff48a8b
ID		 117 mutex_lock(&rt2x00dev->csr_mutex);
118
c9c3b1a5
ID		 119 /*
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
122 */
123 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124 reg = 0;
125 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 132 }
133
8ff48a8b 134 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 135}
136
137static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138{
139 struct rt2x00_dev *rt2x00dev = eeprom->data;
140 u32 reg;
141
142 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146 eeprom->reg_data_clock =
147 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148 eeprom->reg_chip_select =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150}
151
152static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153{
154 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 u32 reg = 0;
156
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160 !!eeprom->reg_data_clock);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162 !!eeprom->reg_chip_select);
163
164 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165}
166
167#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 168static const struct rt2x00debug rt2500pci_rt2x00debug = {
169 .owner = THIS_MODULE,
170 .csr = {
743b97ca
ID		 171 .read = rt2x00pci_register_read,
172 .write = rt2x00pci_register_write,
173 .flags = RT2X00DEBUGFS_OFFSET,
174 .word_base = CSR_REG_BASE,
95ea3627
ID		 175 .word_size = sizeof(u32),
176 .word_count = CSR_REG_SIZE / sizeof(u32),
177 },
178 .eeprom = {
179 .read = rt2x00_eeprom_read,
180 .write = rt2x00_eeprom_write,
743b97ca 181 .word_base = EEPROM_BASE,
95ea3627
ID		 182 .word_size = sizeof(u16),
183 .word_count = EEPROM_SIZE / sizeof(u16),
184 },
185 .bbp = {
186 .read = rt2500pci_bbp_read,
187 .write = rt2500pci_bbp_write,
743b97ca 188 .word_base = BBP_BASE,
95ea3627
ID		 189 .word_size = sizeof(u8),
190 .word_count = BBP_SIZE / sizeof(u8),
191 },
192 .rf = {
193 .read = rt2x00_rf_read,
194 .write = rt2500pci_rf_write,
743b97ca 195 .word_base = RF_BASE,
95ea3627
ID		 196 .word_size = sizeof(u32),
197 .word_count = RF_SIZE / sizeof(u32),
198 },
199};
200#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
95ea3627
ID		 202static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203{
204 u32 reg;
205
206 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
207 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208}
95ea3627 209
771fd565 210#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 211static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 212 enum led_brightness brightness)
213{
214 struct rt2x00_led *led =
215 container_of(led_cdev, struct rt2x00_led, led_dev);
216 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 217 u32 reg;
218
219 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
220
a2e1d52a 221 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 222 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 223 else if (led->type == LED_TYPE_ACTIVITY)
224 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 225
226 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227}
a2e1d52a
ID		 228
229static int rt2500pci_blink_set(struct led_classdev *led_cdev,
230 unsigned long *delay_on,
231 unsigned long *delay_off)
232{
233 struct rt2x00_led *led =
234 container_of(led_cdev, struct rt2x00_led, led_dev);
235 u32 reg;
236
237 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
238 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
239 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
240 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242 return 0;
243}
475433be
ID		 244
245static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
246 struct rt2x00_led *led,
247 enum led_type type)
248{
249 led->rt2x00dev = rt2x00dev;
250 led->type = type;
251 led->led_dev.brightness_set = rt2500pci_brightness_set;
252 led->led_dev.blink_set = rt2500pci_blink_set;
253 led->flags = LED_INITIALIZED;
254}
771fd565 255#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 256
95ea3627
ID		 257/*
258 * Configuration handlers.
259 */
3a643d24
ID		 260static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 const unsigned int filter_flags)
262{
263 u32 reg;
264
265 /*
266 * Start configuration steps.
267 * Note that the version error will always be dropped
268 * and broadcast frames will always be accepted since
269 * there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
285 !(filter_flags & FIF_ALLMULTI));
286 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
287 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
288}
289
6bb40dd1
ID		 290static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
291 struct rt2x00_intf *intf,
292 struct rt2x00intf_conf *conf,
293 const unsigned int flags)
95ea3627 294{
e58c6aca 295 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
6bb40dd1 296 unsigned int bcn_preload;
95ea3627
ID		 297 u32 reg;
298
6bb40dd1 299 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 300 /*
301 * Enable beacon config
302 */
bad13639 303 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 304 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
305 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
306 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
307 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 308
6bb40dd1
ID		 309 /*
310 * Enable synchronisation.
311 */
312 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 313 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 315 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 316 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
317 }
318
319 if (flags & CONFIG_UPDATE_MAC)
320 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
321 conf->mac, sizeof(conf->mac));
322
323 if (flags & CONFIG_UPDATE_BSSID)
324 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
325 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 326}
327
3a643d24
ID		 328static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
329 struct rt2x00lib_erp *erp)
95ea3627 330{
5c58ee51 331 int preamble_mask;
95ea3627 332 u32 reg;
95ea3627 333
5c58ee51
ID		 334 /*
335 * When short preamble is enabled, we should set bit 0x08
336 */
72810379 337 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 338
339 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 340 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
341 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
8a566afe
ID		 342 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
343 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 344 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
345
95ea3627 346 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 347 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 348 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 349 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 350 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
351
352 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 353 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 354 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 355 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 356 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
357
358 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 359 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 360 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 361 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 362 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
363
364 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 365 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 366 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 367 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 368 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 369
370 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
371
372 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
373 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
374 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
375
8a566afe
ID		 376 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
377 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
378 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
379 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
380
e4ea1c40
ID		 381 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
382 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
383 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
384 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
385
386 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
387 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
388 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
389 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 390}
391
e4ea1c40
ID		 392static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
393 struct antenna_setup *ant)
95ea3627 394{
e4ea1c40
ID		 395 u32 reg;
396 u8 r14;
397 u8 r2;
398
399 /*
400 * We should never come here because rt2x00lib is supposed
401 * to catch this and send us the correct antenna explicitely.
402 */
403 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
404 ant->tx == ANTENNA_SW_DIVERSITY);
405
406 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
407 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
408 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
409
410 /*
411 * Configure the TX antenna.
412 */
413 switch (ant->tx) {
414 case ANTENNA_A:
415 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
416 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
417 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
418 break;
419 case ANTENNA_B:
420 default:
421 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
422 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
423 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
424 break;
425 }
426
427 /*
428 * Configure the RX antenna.
429 */
430 switch (ant->rx) {
431 case ANTENNA_A:
432 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
433 break;
434 case ANTENNA_B:
435 default:
436 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
437 break;
438 }
439
440 /*
441 * RT2525E and RT5222 need to flip TX I/Q
442 */
443 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
444 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
445 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
446 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
447 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
448
449 /*
450 * RT2525E does not need RX I/Q Flip.
451 */
452 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
453 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
454 } else {
455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
456 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
457 }
458
459 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
460 rt2500pci_bbp_write(rt2x00dev, 14, r14);
461 rt2500pci_bbp_write(rt2x00dev, 2, r2);
95ea3627
ID		 462}
463
464static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 465 struct rf_channel *rf, const int txpower)
95ea3627 466{
95ea3627
ID		 467 u8 r70;
468
95ea3627
ID		 469 /*
470 * Set TXpower.
471 */
5c58ee51 472 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 473
474 /*
475 * Switch on tuning bits.
476 * For RT2523 devices we do not need to update the R1 register.
477 */
478 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 481
482 /*
483 * For RT2525 we should first set the channel to half band higher.
484 */
485 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
486 static const u32 vals[] = {
487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
489 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
490 0x00080d2e, 0x00080d3a
491 };
492
5c58ee51
ID		 493 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
495 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
496 if (rf->rf4)
497 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 498 }
499
5c58ee51
ID		 500 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
501 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
502 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
503 if (rf->rf4)
504 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 505
506 /*
507 * Channel 14 requires the Japan filter bit to be set.
508 */
509 r70 = 0x46;
5c58ee51 510 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 511 rt2500pci_bbp_write(rt2x00dev, 70, r70);
512
513 msleep(1);
514
515 /*
516 * Switch off tuning bits.
517 * For RT2523 devices we do not need to update the R1 register.
518 */
519 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 522 }
523
5c58ee51
ID		 524 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
525 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 526
527 /*
528 * Clear false CRC during channel switch.
529 */
5c58ee51 530 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 531}
532
533static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
534 const int txpower)
535{
536 u32 rf3;
537
538 rt2x00_rf_read(rt2x00dev, 3, &rf3);
539 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
540 rt2500pci_rf_write(rt2x00dev, 3, rf3);
541}
542
e4ea1c40
ID		 543static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
544 struct rt2x00lib_conf *libconf)
95ea3627
ID		 545{
546 u32 reg;
95ea3627 547
e4ea1c40
ID		 548 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
549 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
550 libconf->conf->long_frame_max_tx_count);
551 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
552 libconf->conf->short_frame_max_tx_count);
553 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 554}
555
7d7f19cc
ID		 556static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
557 struct rt2x00lib_conf *libconf)
558{
559 enum dev_state state =
560 (libconf->conf->flags & IEEE80211_CONF_PS) ?
561 STATE_SLEEP : STATE_AWAKE;
562 u32 reg;
563
564 if (state == STATE_SLEEP) {
565 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
566 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 567 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 568 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
569 libconf->conf->listen_interval - 1);
570
571 /* We must first disable autowake before it can be enabled */
572 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
573 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
574
575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 }
578
579 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
580}
581
95ea3627 582static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 583 struct rt2x00lib_conf *libconf,
584 const unsigned int flags)
95ea3627 585{
e4ea1c40 586 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 587 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
588 libconf->conf->power_level);
e4ea1c40
ID		 589 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
590 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 591 rt2500pci_config_txpower(rt2x00dev,
592 libconf->conf->power_level);
e4ea1c40
ID		 593 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
594 rt2500pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 595 if (flags & IEEE80211_CONF_CHANGE_PS)
596 rt2500pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 597}
598
95ea3627
ID		 599/*
600 * Link tuning
601 */
ebcf26da
ID		 602static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
603 struct link_qual *qual)
95ea3627
ID		 604{
605 u32 reg;
606
607 /*
608 * Update FCS error count from register.
609 */
610 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 611 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 612
613 /*
614 * Update False CCA count from register.
615 */
616 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 617 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 618}
619
5352ff65
ID		 620static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
621 struct link_qual *qual, u8 vgc_level)
eb20b4e8 622{
5352ff65 623 if (qual->vgc_level_reg != vgc_level) {
eb20b4e8 624 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65 625 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 626 }
627}
628
5352ff65
ID		 629static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
630 struct link_qual *qual)
95ea3627 631{
5352ff65 632 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
95ea3627
ID		 633}
634
5352ff65
ID		 635static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
636 struct link_qual *qual, const u32 count)
95ea3627 637{
95ea3627
ID		 638 /*
639 * To prevent collisions with MAC ASIC on chipsets
640 * up to version C the link tuning should halt after 20
6bb40dd1 641 * seconds while being associated.
95ea3627 642 */
755a957d 643 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
5352ff65 644 rt2x00dev->intf_associated && count > 20)
95ea3627
ID		 645 return;
646
95ea3627
ID		 647 /*
648 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 649 * to the dynamic CCA tuning. Chipset version D and higher
650 * should go straight to dynamic CCA tuning when they
651 * are not associated.
95ea3627 652 */
6bb40dd1
ID		 653 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
654 !rt2x00dev->intf_associated)
95ea3627
ID		 655 goto dynamic_cca_tune;
656
657 /*
658 * A too low RSSI will cause too much false CCA which will
659 * then corrupt the R17 tuning. To remidy this the tuning should
660 * be stopped (While making sure the R17 value will not exceed limits)
661 */
5352ff65
ID		 662 if (qual->rssi < -80 && count > 20) {
663 if (qual->vgc_level_reg >= 0x41)
664 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 665 return;
666 }
667
668 /*
669 * Special big-R17 for short distance
670 */
5352ff65
ID		 671 if (qual->rssi >= -58) {
672 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
95ea3627
ID		 673 return;
674 }
675
676 /*
677 * Special mid-R17 for middle distance
678 */
5352ff65
ID		 679 if (qual->rssi >= -74) {
680 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
95ea3627
ID		 681 return;
682 }
683
684 /*
685 * Leave short or middle distance condition, restore r17
686 * to the dynamic tuning range.
687 */
5352ff65
ID		 688 if (qual->vgc_level_reg >= 0x41) {
689 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 690 return;
691 }
692
693dynamic_cca_tune:
694
695 /*
696 * R17 is inside the dynamic tuning range,
697 * start tuning the link based on the false cca counter.
698 */
5352ff65
ID		 699 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
700 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
701 qual->vgc_level = qual->vgc_level_reg;
702 } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
703 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
704 qual->vgc_level = qual->vgc_level_reg;
95ea3627
ID		 705 }
706}
707
708/*
709 * Initialization functions.
710 */
798b7adb 711static bool rt2500pci_get_entry_state(struct queue_entry *entry)
95ea3627 712{
b8be63ff 713 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 714 u32 word;
715
798b7adb
ID		 716 if (entry->queue->qid == QID_RX) {
717 rt2x00_desc_read(entry_priv->desc, 0, &word);
718
719 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
720 } else {
721 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 722
798b7adb
ID		 723 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
724 rt2x00_get_field32(word, TXD_W0_VALID));
725 }
95ea3627
ID		 726}
727
798b7adb 728static void rt2500pci_clear_entry(struct queue_entry *entry)
95ea3627 729{
b8be63ff 730 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 731 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 732 u32 word;
733
798b7adb
ID		 734 if (entry->queue->qid == QID_RX) {
735 rt2x00_desc_read(entry_priv->desc, 1, &word);
736 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
737 rt2x00_desc_write(entry_priv->desc, 1, word);
738
739 rt2x00_desc_read(entry_priv->desc, 0, &word);
740 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
741 rt2x00_desc_write(entry_priv->desc, 0, word);
742 } else {
743 rt2x00_desc_read(entry_priv->desc, 0, &word);
744 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
745 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
746 rt2x00_desc_write(entry_priv->desc, 0, word);
747 }
95ea3627
ID		 748}
749
181d6902 750static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 751{
b8be63ff 752 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 753 u32 reg;
754
95ea3627
ID		 755 /*
756 * Initialize registers.
757 */
758 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 759 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
760 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
761 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
762 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 763 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
764
b8be63ff 765 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 766 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 767 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 768 entry_priv->desc_dma);
95ea3627
ID		 769 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
770
b8be63ff 771 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 772 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 773 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 774 entry_priv->desc_dma);
95ea3627
ID		 775 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
776
b8be63ff 777 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 778 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 779 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 780 entry_priv->desc_dma);
95ea3627
ID		 781 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
782
b8be63ff 783 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 784 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 785 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 786 entry_priv->desc_dma);
95ea3627
ID		 787 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
788
789 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
790 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 791 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 792 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
793
b8be63ff 794 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 795 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 796 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
797 entry_priv->desc_dma);
95ea3627
ID		 798 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
799
800 return 0;
801}
802
803static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
804{
805 u32 reg;
806
807 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
808 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
809 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
811
812 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
813 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
814 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
815 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
816 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
817
818 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
819 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
820 rt2x00dev->rx->data_size / 128);
821 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
822
823 /*
824 * Always use CWmin and CWmax set in descriptor.
825 */
826 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
827 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
828 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
829
1f909162
ID		 830 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
831 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
832 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
833 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
834 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
835 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
836 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
837 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
838 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
839 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
840
95ea3627
ID		 841 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
842
843 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
844 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
845 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
846 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
847 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
852 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
853
854 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
855 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
856 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
857 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
858 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
859 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
860
861 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
862 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
863 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
864 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
865 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
866 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
867
868 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
869 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
870 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
871 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
872 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
873 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
874
875 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
876 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
877 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
878 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
879 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
884 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
885
886 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
887 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
888 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
889 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
890 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
891 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
892 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
893 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
894 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
895
896 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
897
898 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
899 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
900
901 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
902 return -EBUSY;
903
904 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
905 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
906
907 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
908 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
909 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
910
911 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
912 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
913 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
914 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
915 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
918 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
919
920 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
921
922 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
923
924 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
925 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
926 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
927 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
928 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
929
930 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
931 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
932 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
933 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
934
935 /*
936 * We must clear the FCS and FIFO error count.
937 * These registers are cleared on read,
938 * so we may pass a useless variable to store the value.
939 */
940 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
941 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
942
943 return 0;
944}
945
2b08da3f 946static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 947{
948 unsigned int i;
95ea3627
ID		 949 u8 value;
950
951 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
952 rt2500pci_bbp_read(rt2x00dev, 0, &value);
953 if ((value != 0xff) && (value != 0x00))
2b08da3f 954 return 0;
95ea3627
ID		 955 udelay(REGISTER_BUSY_DELAY);
956 }
957
958 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
959 return -EACCES;
2b08da3f
ID		 960}
961
962static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
963{
964 unsigned int i;
965 u16 eeprom;
966 u8 reg_id;
967 u8 value;
968
969 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
970 return -EACCES;
95ea3627 971
95ea3627
ID		 972 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
973 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
974 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
975 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
976 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
977 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
978 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
979 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
980 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
981 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
982 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
984 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
985 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
986 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
987 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
988 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
989 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
990 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
991 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
992 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
993 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
994 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
995 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
996 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
997 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
998 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
999 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1001 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1002
95ea3627
ID		 1003 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1004 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1005
1006 if (eeprom != 0xffff && eeprom != 0x0000) {
1007 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1008 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1009 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1010 }
1011 }
95ea3627
ID		 1012
1013 return 0;
1014}
1015
1016/*
1017 * Device state switch handlers.
1018 */
1019static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1020 enum dev_state state)
1021{
1022 u32 reg;
1023
1024 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1025 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 1026 (state == STATE_RADIO_RX_OFF) ||
1027 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1028 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1029}
1030
1031static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1032 enum dev_state state)
1033{
1034 int mask = (state == STATE_RADIO_IRQ_OFF);
1035 u32 reg;
1036
1037 /*
1038 * When interrupts are being enabled, the interrupt registers
1039 * should clear the register to assure a clean state.
1040 */
1041 if (state == STATE_RADIO_IRQ_ON) {
1042 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1043 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1044 }
1045
1046 /*
1047 * Only toggle the interrupts bits we are going to use.
1048 * Non-checked interrupt bits are disabled by default.
1049 */
1050 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1051 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1052 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1053 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1054 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1055 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1056 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1057}
1058
1059static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1060{
1061 /*
1062 * Initialize all registers.
1063 */
2b08da3f
ID		 1064 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1065 rt2500pci_init_registers(rt2x00dev) ||
1066 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1067 return -EIO;
95ea3627 1068
95ea3627
ID		 1069 return 0;
1070}
1071
1072static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1073{
95ea3627 1074 /*
a2c9b652 1075 * Disable power
95ea3627 1076 */
a2c9b652 1077 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1078}
1079
1080static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1081 enum dev_state state)
1082{
1083 u32 reg;
1084 unsigned int i;
1085 char put_to_sleep;
1086 char bbp_state;
1087 char rf_state;
1088
1089 put_to_sleep = (state != STATE_AWAKE);
1090
1091 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1092 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1093 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1094 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1095 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1096 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1097
1098 /*
1099 * Device is not guaranteed to be in the requested state yet.
1100 * We must wait until the register indicates that the
1101 * device has entered the correct state.
1102 */
1103 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1104 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1105 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1106 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1107 if (bbp_state == state && rf_state == state)
1108 return 0;
1109 msleep(10);
1110 }
1111
95ea3627
ID		 1112 return -EBUSY;
1113}
1114
1115static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1116 enum dev_state state)
1117{
1118 int retval = 0;
1119
1120 switch (state) {
1121 case STATE_RADIO_ON:
1122 retval = rt2500pci_enable_radio(rt2x00dev);
1123 break;
1124 case STATE_RADIO_OFF:
1125 rt2500pci_disable_radio(rt2x00dev);
1126 break;
1127 case STATE_RADIO_RX_ON:
61667d8d 1128 case STATE_RADIO_RX_ON_LINK:
95ea3627 1129 case STATE_RADIO_RX_OFF:
61667d8d 1130 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1131 rt2500pci_toggle_rx(rt2x00dev, state);
1132 break;
1133 case STATE_RADIO_IRQ_ON:
1134 case STATE_RADIO_IRQ_OFF:
1135 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1136 break;
1137 case STATE_DEEP_SLEEP:
1138 case STATE_SLEEP:
1139 case STATE_STANDBY:
1140 case STATE_AWAKE:
1141 retval = rt2500pci_set_state(rt2x00dev, state);
1142 break;
1143 default:
1144 retval = -ENOTSUPP;
1145 break;
1146 }
1147
2b08da3f
ID		 1148 if (unlikely(retval))
1149 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1150 state, retval);
1151
95ea3627
ID		 1152 return retval;
1153}
1154
1155/*
1156 * TX descriptor initialization
1157 */
1158static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1159 struct sk_buff *skb,
61486e0f 1160 struct txentry_desc *txdesc)
95ea3627 1161{
181d6902 1162 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1163 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1164 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1165 u32 word;
1166
1167 /*
1168 * Start writing the descriptor words.
1169 */
4de36fe5 1170 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1171 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1172 rt2x00_desc_write(entry_priv->desc, 1, word);
1173
95ea3627
ID		 1174 rt2x00_desc_read(txd, 2, &word);
1175 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1176 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1177 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1178 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1179 rt2x00_desc_write(txd, 2, word);
1180
1181 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1182 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1183 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1184 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1185 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1186 rt2x00_desc_write(txd, 3, word);
1187
1188 rt2x00_desc_read(txd, 10, &word);
1189 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1190 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1191 rt2x00_desc_write(txd, 10, word);
1192
1193 rt2x00_desc_read(txd, 0, &word);
1194 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1195 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1196 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1197 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1198 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1199 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1200 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1201 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1202 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1203 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1204 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1205 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1206 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1207 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
bf4634af 1208 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627
ID		 1209 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1210 rt2x00_desc_write(txd, 0, word);
1211}
1212
1213/*
1214 * TX data initialization
1215 */
bd88a781
ID		 1216static void rt2500pci_write_beacon(struct queue_entry *entry)
1217{
1218 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1219 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1220 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1221 u32 word;
1222 u32 reg;
1223
1224 /*
1225 * Disable beaconing while we are reloading the beacon data,
1226 * otherwise we might be sending out invalid data.
1227 */
1228 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1229 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1230 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1231
1232 /*
1233 * Replace rt2x00lib allocated descriptor with the
1234 * pointer to the _real_ hardware descriptor.
1235 * After that, map the beacon to DMA and update the
1236 * descriptor.
1237 */
1238 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1239 skbdesc->desc = entry_priv->desc;
1240
1241 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1242
1243 rt2x00_desc_read(entry_priv->desc, 1, &word);
1244 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1245 rt2x00_desc_write(entry_priv->desc, 1, word);
1246}
1247
95ea3627 1248static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1249 const enum data_queue_qid queue)
95ea3627
ID		 1250{
1251 u32 reg;
1252
e58c6aca 1253 if (queue == QID_BEACON) {
95ea3627
ID		 1254 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1255 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1256 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1257 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1258 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1259 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1260 }
1261 return;
1262 }
1263
1264 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1265 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1266 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1267 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1268 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1269}
1270
a2c9b652
ID		 1271static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1272 const enum data_queue_qid qid)
1273{
1274 u32 reg;
1275
1276 if (qid == QID_BEACON) {
1277 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1278 } else {
1279 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1280 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1281 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1282 }
1283}
1284
95ea3627
ID		 1285/*
1286 * RX control handlers
1287 */
181d6902
ID		 1288static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1289 struct rxdone_entry_desc *rxdesc)
95ea3627 1290{
b8be63ff 1291 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1292 u32 word0;
1293 u32 word2;
1294
b8be63ff
ID		 1295 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1296 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1297
4150c572 1298 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1299 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1300 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1301 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1302
89993890
ID		 1303 /*
1304 * Obtain the status about this packet.
1305 * When frame was received with an OFDM bitrate,
1306 * the signal is the PLCP value. If it was received with
1307 * a CCK bitrate the signal is the rate in 100kbit/s.
1308 */
181d6902
ID		 1309 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1310 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1311 entry->queue->rt2x00dev->rssi_offset;
181d6902 1312 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1313
19d30e02
ID		 1314 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1315 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1316 else
1317 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1318 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1319 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1320}
1321
1322/*
1323 * Interrupt functions.
1324 */
181d6902 1325static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1326 const enum data_queue_qid queue_idx)
95ea3627 1327{
181d6902 1328 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1329 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1330 struct queue_entry *entry;
1331 struct txdone_entry_desc txdesc;
95ea3627 1332 u32 word;
95ea3627 1333
181d6902
ID		 1334 while (!rt2x00queue_empty(queue)) {
1335 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1336 entry_priv = entry->priv_data;
1337 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1338
1339 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1340 !rt2x00_get_field32(word, TXD_W0_VALID))
1341 break;
1342
1343 /*
1344 * Obtain the status about this packet.
1345 */
fb55f4d1
ID		 1346 txdesc.flags = 0;
1347 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1348 case 0: /* Success */
1349 case 1: /* Success with retry */
1350 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1351 break;
1352 case 2: /* Failure, excessive retries */
1353 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1354 /* Don't break, this is a failed frame! */
1355 default: /* Failure */
1356 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1357 }
181d6902 1358 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1359
d74f5ba4 1360 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1361 }
95ea3627
ID		 1362}
1363
1364static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1365{
1366 struct rt2x00_dev *rt2x00dev = dev_instance;
1367 u32 reg;
1368
1369 /*
1370 * Get the interrupt sources & saved to local variable.
1371 * Write register value back to clear pending interrupts.
1372 */
1373 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1374 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1375
1376 if (!reg)
1377 return IRQ_NONE;
1378
0262ab0d 1379 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1380 return IRQ_HANDLED;
1381
1382 /*
1383 * Handle interrupts, walk through all bits
1384 * and run the tasks, the bits are checked in order of
1385 * priority.
1386 */
1387
1388 /*
1389 * 1 - Beacon timer expired interrupt.
1390 */
1391 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1392 rt2x00lib_beacondone(rt2x00dev);
1393
1394 /*
1395 * 2 - Rx ring done interrupt.
1396 */
1397 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1398 rt2x00pci_rxdone(rt2x00dev);
1399
1400 /*
1401 * 3 - Atim ring transmit done interrupt.
1402 */
1403 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1404 rt2500pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1405
1406 /*
1407 * 4 - Priority ring transmit done interrupt.
1408 */
1409 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1410 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1411
1412 /*
1413 * 5 - Tx ring transmit done interrupt.
1414 */
1415 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1416 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1417
1418 return IRQ_HANDLED;
1419}
1420
1421/*
1422 * Device probe functions.
1423 */
1424static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1425{
1426 struct eeprom_93cx6 eeprom;
1427 u32 reg;
1428 u16 word;
1429 u8 *mac;
1430
1431 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1432
1433 eeprom.data = rt2x00dev;
1434 eeprom.register_read = rt2500pci_eepromregister_read;
1435 eeprom.register_write = rt2500pci_eepromregister_write;
1436 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1437 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1438 eeprom.reg_data_in = 0;
1439 eeprom.reg_data_out = 0;
1440 eeprom.reg_data_clock = 0;
1441 eeprom.reg_chip_select = 0;
1442
1443 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1444 EEPROM_SIZE / sizeof(u16));
1445
1446 /*
1447 * Start validation of the data that has been read.
1448 */
1449 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1450 if (!is_valid_ether_addr(mac)) {
1451 random_ether_addr(mac);
e174961c 1452 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1453 }
1454
1455 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1456 if (word == 0xffff) {
1457 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1458 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1459 ANTENNA_SW_DIVERSITY);
1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1461 ANTENNA_SW_DIVERSITY);
1462 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1463 LED_MODE_DEFAULT);
95ea3627
ID		 1464 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1466 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1467 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1468 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1469 }
1470
1471 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1472 if (word == 0xffff) {
1473 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1474 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1475 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1476 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1477 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1478 }
1479
1480 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1481 if (word == 0xffff) {
1482 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1483 DEFAULT_RSSI_OFFSET);
1484 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1485 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1486 }
1487
1488 return 0;
1489}
1490
1491static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1492{
1493 u32 reg;
1494 u16 value;
1495 u16 eeprom;
1496
1497 /*
1498 * Read EEPROM word for configuration.
1499 */
1500 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1501
1502 /*
1503 * Identify RF chipset.
1504 */
1505 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1506 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
440ddada 1507 rt2x00_set_chip_rf(rt2x00dev, value, reg);
16475b09 1508 rt2x00_print_chip(rt2x00dev);
95ea3627
ID		 1509
1510 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1511 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1512 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1513 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1514 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1515 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1516 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1517 return -ENODEV;
1518 }
1519
1520 /*
1521 * Identify default antenna configuration.
1522 */
addc81bd 1523 rt2x00dev->default_ant.tx =
95ea3627 1524 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1525 rt2x00dev->default_ant.rx =
95ea3627
ID		 1526 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1527
1528 /*
1529 * Store led mode, for correct led behaviour.
1530 */
771fd565 1531#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1532 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1533
475433be 1534 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1535 if (value == LED_MODE_TXRX_ACTIVITY ||
1536 value == LED_MODE_DEFAULT ||
1537 value == LED_MODE_ASUS)
475433be
ID		 1538 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1539 LED_TYPE_ACTIVITY);
771fd565 1540#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1541
1542 /*
1543 * Detect if this device has an hardware controlled radio.
1544 */
1545 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1546 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1547
1548 /*
1549 * Check if the BBP tuning should be enabled.
1550 */
1551 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1552
1553 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1554 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1555
1556 /*
1557 * Read the RSSI <-> dBm offset information.
1558 */
1559 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1560 rt2x00dev->rssi_offset =
1561 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1562
1563 return 0;
1564}
1565
1566/*
1567 * RF value list for RF2522
1568 * Supports: 2.4 GHz
1569 */
1570static const struct rf_channel rf_vals_bg_2522[] = {
1571 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1572 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1573 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1574 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1575 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1576 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1577 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1578 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1579 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1580 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1581 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1582 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1583 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1584 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1585};
1586
1587/*
1588 * RF value list for RF2523
1589 * Supports: 2.4 GHz
1590 */
1591static const struct rf_channel rf_vals_bg_2523[] = {
1592 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1593 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1594 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1595 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1596 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1597 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1598 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1599 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1600 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1601 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1602 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1603 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1604 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1605 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1606};
1607
1608/*
1609 * RF value list for RF2524
1610 * Supports: 2.4 GHz
1611 */
1612static const struct rf_channel rf_vals_bg_2524[] = {
1613 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1614 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1615 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1616 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1617 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1618 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1619 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1620 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1621 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1622 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1623 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1624 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1625 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1626 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1627};
1628
1629/*
1630 * RF value list for RF2525
1631 * Supports: 2.4 GHz
1632 */
1633static const struct rf_channel rf_vals_bg_2525[] = {
1634 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1635 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1636 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1637 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1638 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1639 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1640 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1641 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1642 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1643 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1644 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1645 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1646 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1647 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1648};
1649
1650/*
1651 * RF value list for RF2525e
1652 * Supports: 2.4 GHz
1653 */
1654static const struct rf_channel rf_vals_bg_2525e[] = {
1655 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1656 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1657 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1658 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1659 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1660 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1661 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1662 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1663 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1664 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1665 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1666 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1667 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1668 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1669};
1670
1671/*
1672 * RF value list for RF5222
1673 * Supports: 2.4 GHz & 5.2 GHz
1674 */
1675static const struct rf_channel rf_vals_5222[] = {
1676 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1677 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1678 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1679 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1680 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1681 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1682 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1683 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1684 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1685 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1686 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1687 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1688 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1689 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1690
1691 /* 802.11 UNI / HyperLan 2 */
1692 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1693 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1694 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1695 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1696 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1697 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1698 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1699 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1700
1701 /* 802.11 HyperLan 2 */
1702 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1703 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1704 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1705 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1706 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1707 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1708 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1709 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1710 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1711 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1712
1713 /* 802.11 UNII */
1714 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1715 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1716 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1717 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1718 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1719};
1720
8c5e7a5f 1721static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1722{
1723 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1724 struct channel_info *info;
1725 char *tx_power;
95ea3627
ID		 1726 unsigned int i;
1727
1728 /*
1729 * Initialize all hw fields.
1730 */
566bfe5a 1731 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1732 IEEE80211_HW_SIGNAL_DBM |
1733 IEEE80211_HW_SUPPORTS_PS |
1734 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1735
95ea3627 1736 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 1737
14a3bf89 1738 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1739 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1740 rt2x00_eeprom_addr(rt2x00dev,
1741 EEPROM_MAC_ADDR_0));
1742
95ea3627
ID		 1743 /*
1744 * Initialize hw_mode information.
1745 */
31562e80
ID		 1746 spec->supported_bands = SUPPORT_BAND_2GHZ;
1747 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1748
1749 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1750 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1751 spec->channels = rf_vals_bg_2522;
1752 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1753 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1754 spec->channels = rf_vals_bg_2523;
1755 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1756 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1757 spec->channels = rf_vals_bg_2524;
1758 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1759 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1760 spec->channels = rf_vals_bg_2525;
1761 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1762 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1763 spec->channels = rf_vals_bg_2525e;
1764 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
31562e80 1765 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1766 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1767 spec->channels = rf_vals_5222;
95ea3627 1768 }
8c5e7a5f
ID		 1769
1770 /*
1771 * Create channel information array
1772 */
1773 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1774 if (!info)
1775 return -ENOMEM;
1776
1777 spec->channels_info = info;
1778
1779 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1780 for (i = 0; i < 14; i++)
1781 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1782
1783 if (spec->num_channels > 14) {
1784 for (i = 14; i < spec->num_channels; i++)
1785 info[i].tx_power1 = DEFAULT_TXPOWER;
1786 }
1787
1788 return 0;
95ea3627
ID		 1789}
1790
1791static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1792{
1793 int retval;
1794
1795 /*
1796 * Allocate eeprom data.
1797 */
1798 retval = rt2500pci_validate_eeprom(rt2x00dev);
1799 if (retval)
1800 return retval;
1801
1802 retval = rt2500pci_init_eeprom(rt2x00dev);
1803 if (retval)
1804 return retval;
1805
1806 /*
1807 * Initialize hw specifications.
1808 */
8c5e7a5f
ID		 1809 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1810 if (retval)
1811 return retval;
95ea3627
ID		 1812
1813 /*
c4da0048 1814 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1815 */
181d6902 1816 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1817 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1818
1819 /*
1820 * Set the rssi offset.
1821 */
1822 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1823
1824 return 0;
1825}
1826
1827/*
1828 * IEEE80211 stack callback functions.
1829 */
95ea3627
ID		 1830static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1831{
1832 struct rt2x00_dev *rt2x00dev = hw->priv;
1833 u64 tsf;
1834 u32 reg;
1835
1836 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1837 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1838 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1839 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1840
1841 return tsf;
1842}
1843
95ea3627
ID		 1844static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1845{
1846 struct rt2x00_dev *rt2x00dev = hw->priv;
1847 u32 reg;
1848
1849 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1850 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1851}
1852
1853static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1854 .tx = rt2x00mac_tx,
4150c572
JB		 1855 .start = rt2x00mac_start,
1856 .stop = rt2x00mac_stop,
95ea3627
ID		 1857 .add_interface = rt2x00mac_add_interface,
1858 .remove_interface = rt2x00mac_remove_interface,
1859 .config = rt2x00mac_config,
3a643d24 1860 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1861 .set_tim = rt2x00mac_set_tim,
95ea3627 1862 .get_stats = rt2x00mac_get_stats,
471b3efd 1863 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1864 .conf_tx = rt2x00mac_conf_tx,
1865 .get_tx_stats = rt2x00mac_get_tx_stats,
1866 .get_tsf = rt2500pci_get_tsf,
95ea3627 1867 .tx_last_beacon = rt2500pci_tx_last_beacon,
e47a5cdd 1868 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1869};
1870
1871static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1872 .irq_handler = rt2500pci_interrupt,
1873 .probe_hw = rt2500pci_probe_hw,
1874 .initialize = rt2x00pci_initialize,
1875 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1876 .get_entry_state = rt2500pci_get_entry_state,
1877 .clear_entry = rt2500pci_clear_entry,
95ea3627 1878 .set_device_state = rt2500pci_set_device_state,
95ea3627 1879 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1880 .link_stats = rt2500pci_link_stats,
1881 .reset_tuner = rt2500pci_reset_tuner,
1882 .link_tuner = rt2500pci_link_tuner,
1883 .write_tx_desc = rt2500pci_write_tx_desc,
1884 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1885 .write_beacon = rt2500pci_write_beacon,
95ea3627 1886 .kick_tx_queue = rt2500pci_kick_tx_queue,
a2c9b652 1887 .kill_tx_queue = rt2500pci_kill_tx_queue,
95ea3627 1888 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1889 .config_filter = rt2500pci_config_filter,
6bb40dd1 1890 .config_intf = rt2500pci_config_intf,
72810379 1891 .config_erp = rt2500pci_config_erp,
e4ea1c40 1892 .config_ant = rt2500pci_config_ant,
95ea3627
ID		 1893 .config = rt2500pci_config,
1894};
1895
181d6902
ID		 1896static const struct data_queue_desc rt2500pci_queue_rx = {
1897 .entry_num = RX_ENTRIES,
1898 .data_size = DATA_FRAME_SIZE,
1899 .desc_size = RXD_DESC_SIZE,
b8be63ff 1900 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1901};
1902
1903static const struct data_queue_desc rt2500pci_queue_tx = {
1904 .entry_num = TX_ENTRIES,
1905 .data_size = DATA_FRAME_SIZE,
1906 .desc_size = TXD_DESC_SIZE,
b8be63ff 1907 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1908};
1909
1910static const struct data_queue_desc rt2500pci_queue_bcn = {
1911 .entry_num = BEACON_ENTRIES,
1912 .data_size = MGMT_FRAME_SIZE,
1913 .desc_size = TXD_DESC_SIZE,
b8be63ff 1914 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1915};
1916
1917static const struct data_queue_desc rt2500pci_queue_atim = {
1918 .entry_num = ATIM_ENTRIES,
1919 .data_size = DATA_FRAME_SIZE,
1920 .desc_size = TXD_DESC_SIZE,
b8be63ff 1921 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1922};
1923
95ea3627 1924static const struct rt2x00_ops rt2500pci_ops = {
04d0362e
GW		 1925 .name = KBUILD_MODNAME,
1926 .max_sta_intf = 1,
1927 .max_ap_intf = 1,
1928 .eeprom_size = EEPROM_SIZE,
1929 .rf_size = RF_SIZE,
1930 .tx_queues = NUM_TX_QUEUES,
1931 .rx = &rt2500pci_queue_rx,
1932 .tx = &rt2500pci_queue_tx,
1933 .bcn = &rt2500pci_queue_bcn,
1934 .atim = &rt2500pci_queue_atim,
1935 .lib = &rt2500pci_rt2x00_ops,
1936 .hw = &rt2500pci_mac80211_ops,
95ea3627 1937#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1938 .debugfs = &rt2500pci_rt2x00debug,
95ea3627
ID		 1939#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1940};
1941
1942/*
1943 * RT2500pci module information.
1944 */
1945static struct pci_device_id rt2500pci_device_table[] = {
1946 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1947 { 0, }
1948};
1949
1950MODULE_AUTHOR(DRV_PROJECT);
1951MODULE_VERSION(DRV_VERSION);
1952MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1953MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1954MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1955MODULE_LICENSE("GPL");
1956
1957static struct pci_driver rt2500pci_driver = {
2360157c 1958 .name = KBUILD_MODNAME,
95ea3627
ID		 1959 .id_table = rt2500pci_device_table,
1960 .probe = rt2x00pci_probe,
1961 .remove = __devexit_p(rt2x00pci_remove),
1962 .suspend = rt2x00pci_suspend,
1963 .resume = rt2x00pci_resume,
1964};
1965
1966static int __init rt2500pci_init(void)
1967{
1968 return pci_register_driver(&rt2500pci_driver);
1969}
1970
1971static void __exit rt2500pci_exit(void)
1972{
1973 pci_unregister_driver(&rt2500pci_driver);
1974}
1975
1976module_init(rt2500pci_init);
1977module_exit(rt2500pci_exit);
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