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[PATCH] rt2x00: Use enum defines
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt2500pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt2500pci.h"
43
44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58{
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70}
71
72static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74{
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2500pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96}
97
98static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100{
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2500pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2500pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133}
134
135static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137{
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163}
164
165static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166{
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178}
179
180static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181{
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193}
194
195#ifdef CONFIG_RT2X00_LIB_DEBUGFS
196#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200{
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202}
203
204static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206{
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208}
209
210static const struct rt2x00debug rt2500pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2500pci_read_csr,
214 .write = rt2500pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2500pci_bbp_read,
226 .write = rt2500pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2500pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236};
237#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239#ifdef CONFIG_RT2500PCI_RFKILL
240static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241{
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246}
81873e9c
ID		 247#else
248#define rt2500pci_rfkill_poll NULL
dcf5475b 249#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 250
251/*
252 * Configuration handlers.
253 */
4abee4bb
ID		 254static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
255 __le32 *mac)
95ea3627 256{
4abee4bb
ID		 257 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
258 (2 * sizeof(__le32)));
95ea3627
ID		 259}
260
4abee4bb
ID		 261static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
262 __le32 *bssid)
95ea3627 263{
4abee4bb
ID		 264 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
265 (2 * sizeof(__le32)));
95ea3627
ID		 266}
267
feb24691
ID		 268static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
269 const int tsf_sync)
95ea3627
ID		 270{
271 u32 reg;
272
273 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
274
95ea3627
ID		 275 /*
276 * Enable beacon config
277 */
278 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
279 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 280 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 281 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
282 rt2x00lib_get_ring(rt2x00dev,
283 IEEE80211_TX_QUEUE_BEACON)
284 ->tx_params.cw_min);
285 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
286
287 /*
288 * Enable synchronisation.
289 */
290 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572
JB		 291 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
292 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627 293 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 294 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 295 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
296}
297
5c58ee51
ID		 298static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
299 const int short_preamble,
300 const int ack_timeout,
301 const int ack_consume_time)
95ea3627 302{
5c58ee51 303 int preamble_mask;
95ea3627 304 u32 reg;
95ea3627 305
5c58ee51
ID		 306 /*
307 * When short preamble is enabled, we should set bit 0x08
308 */
309 preamble_mask = short_preamble << 3;
95ea3627
ID		 310
311 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 312 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
313 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 314 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
315
95ea3627 316 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 317 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 318 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
319 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
320 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
321
322 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 323 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 324 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
325 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
326 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
327
328 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 329 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 330 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
331 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
332 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
333
334 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 335 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 336 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
337 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
338 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
339}
340
341static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 342 const int basic_rate_mask)
95ea3627 343{
5c58ee51 344 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 345}
346
347static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 348 struct rf_channel *rf, const int txpower)
95ea3627 349{
95ea3627
ID		 350 u8 r70;
351
95ea3627
ID		 352 /*
353 * Set TXpower.
354 */
5c58ee51 355 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 356
357 /*
358 * Switch on tuning bits.
359 * For RT2523 devices we do not need to update the R1 register.
360 */
361 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 362 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
363 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 364
365 /*
366 * For RT2525 we should first set the channel to half band higher.
367 */
368 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
369 static const u32 vals[] = {
370 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
371 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
372 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
373 0x00080d2e, 0x00080d3a
374 };
375
5c58ee51
ID		 376 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
377 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
378 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
379 if (rf->rf4)
380 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 381 }
382
5c58ee51
ID		 383 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
384 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
385 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
386 if (rf->rf4)
387 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 388
389 /*
390 * Channel 14 requires the Japan filter bit to be set.
391 */
392 r70 = 0x46;
5c58ee51 393 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 394 rt2500pci_bbp_write(rt2x00dev, 70, r70);
395
396 msleep(1);
397
398 /*
399 * Switch off tuning bits.
400 * For RT2523 devices we do not need to update the R1 register.
401 */
402 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 405 }
406
5c58ee51
ID		 407 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
408 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 409
410 /*
411 * Clear false CRC during channel switch.
412 */
5c58ee51 413 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 414}
415
416static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
417 const int txpower)
418{
419 u32 rf3;
420
421 rt2x00_rf_read(rt2x00dev, 3, &rf3);
422 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
423 rt2500pci_rf_write(rt2x00dev, 3, rf3);
424}
425
426static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
427 const int antenna_tx, const int antenna_rx)
428{
429 u32 reg;
430 u8 r14;
431 u8 r2;
432
433 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
434 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
435 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
436
437 /*
438 * Configure the TX antenna.
439 */
440 switch (antenna_tx) {
441 case ANTENNA_SW_DIVERSITY:
442 case ANTENNA_HW_DIVERSITY:
443 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
444 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
445 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
446 break;
447 case ANTENNA_A:
448 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
449 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
450 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
451 break;
452 case ANTENNA_B:
453 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
454 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
455 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
456 break;
457 }
458
459 /*
460 * Configure the RX antenna.
461 */
462 switch (antenna_rx) {
463 case ANTENNA_SW_DIVERSITY:
464 case ANTENNA_HW_DIVERSITY:
465 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
466 break;
467 case ANTENNA_A:
468 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
469 break;
470 case ANTENNA_B:
471 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
472 break;
473 }
474
475 /*
476 * RT2525E and RT5222 need to flip TX I/Q
477 */
478 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
479 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
480 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
481 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
482 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
483
484 /*
485 * RT2525E does not need RX I/Q Flip.
486 */
487 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
488 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
489 } else {
490 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
491 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
492 }
493
494 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
495 rt2500pci_bbp_write(rt2x00dev, 14, r14);
496 rt2500pci_bbp_write(rt2x00dev, 2, r2);
497}
498
499static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 500 struct rt2x00lib_conf *libconf)
95ea3627
ID		 501{
502 u32 reg;
503
504 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 505 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 506 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
507
508 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 509 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
510 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 511 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
512
513 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 514 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
515 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 516 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
517
518 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
519 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
520 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
521 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
522
523 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 524 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
525 libconf->conf->beacon_int * 16);
526 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
527 libconf->conf->beacon_int * 16);
95ea3627
ID		 528 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
529}
530
531static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
532 const unsigned int flags,
5c58ee51 533 struct rt2x00lib_conf *libconf)
95ea3627 534{
95ea3627 535 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 536 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 537 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 538 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
539 libconf->conf->power_level);
95ea3627 540 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 541 rt2500pci_config_txpower(rt2x00dev,
542 libconf->conf->power_level);
95ea3627 543 if (flags & CONFIG_UPDATE_ANTENNA)
5c58ee51
ID		 544 rt2500pci_config_antenna(rt2x00dev,
545 libconf->conf->antenna_sel_tx,
546 libconf->conf->antenna_sel_rx);
95ea3627 547 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 548 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 549}
550
551/*
552 * LED functions.
553 */
554static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
555{
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
559
560 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
561 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
562
563 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
564 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
565 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
566 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
567 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
568 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
569 } else {
570 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
571 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
572 }
573
574 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
575}
576
577static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
578{
579 u32 reg;
580
581 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
582 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
583 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
584 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
585}
586
587/*
588 * Link tuning
589 */
ebcf26da
ID		 590static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
591 struct link_qual *qual)
95ea3627
ID		 592{
593 u32 reg;
594
595 /*
596 * Update FCS error count from register.
597 */
598 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 599 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 600
601 /*
602 * Update False CCA count from register.
603 */
604 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 605 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 606}
607
608static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
609{
610 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
611 rt2x00dev->link.vgc_level = 0x48;
612}
613
614static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
615{
616 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
617 u8 r17;
618
619 /*
620 * To prevent collisions with MAC ASIC on chipsets
621 * up to version C the link tuning should halt after 20
622 * seconds.
623 */
755a957d 624 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
95ea3627
ID		 625 rt2x00dev->link.count > 20)
626 return;
627
628 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
629
630 /*
631 * Chipset versions C and lower should directly continue
632 * to the dynamic CCA tuning.
633 */
755a957d 634 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
95ea3627
ID		 635 goto dynamic_cca_tune;
636
637 /*
638 * A too low RSSI will cause too much false CCA which will
639 * then corrupt the R17 tuning. To remidy this the tuning should
640 * be stopped (While making sure the R17 value will not exceed limits)
641 */
642 if (rssi < -80 && rt2x00dev->link.count > 20) {
643 if (r17 >= 0x41) {
644 r17 = rt2x00dev->link.vgc_level;
645 rt2500pci_bbp_write(rt2x00dev, 17, r17);
646 }
647 return;
648 }
649
650 /*
651 * Special big-R17 for short distance
652 */
653 if (rssi >= -58) {
654 if (r17 != 0x50)
655 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
656 return;
657 }
658
659 /*
660 * Special mid-R17 for middle distance
661 */
662 if (rssi >= -74) {
663 if (r17 != 0x41)
664 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
665 return;
666 }
667
668 /*
669 * Leave short or middle distance condition, restore r17
670 * to the dynamic tuning range.
671 */
672 if (r17 >= 0x41) {
673 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
674 return;
675 }
676
677dynamic_cca_tune:
678
679 /*
680 * R17 is inside the dynamic tuning range,
681 * start tuning the link based on the false cca counter.
682 */
ebcf26da 683 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 684 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
685 rt2x00dev->link.vgc_level = r17;
ebcf26da 686 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 687 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
688 rt2x00dev->link.vgc_level = r17;
689 }
690}
691
692/*
693 * Initialization functions.
694 */
695static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
696{
697 struct data_ring *ring = rt2x00dev->rx;
698 struct data_desc *rxd;
699 unsigned int i;
700 u32 word;
701
702 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
703
704 for (i = 0; i < ring->stats.limit; i++) {
705 rxd = ring->entry[i].priv;
706
707 rt2x00_desc_read(rxd, 1, &word);
708 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
709 ring->entry[i].data_dma);
710 rt2x00_desc_write(rxd, 1, word);
711
712 rt2x00_desc_read(rxd, 0, &word);
713 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
714 rt2x00_desc_write(rxd, 0, word);
715 }
716
717 rt2x00_ring_index_clear(rt2x00dev->rx);
718}
719
720static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
721{
722 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
723 struct data_desc *txd;
724 unsigned int i;
725 u32 word;
726
727 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
728
729 for (i = 0; i < ring->stats.limit; i++) {
730 txd = ring->entry[i].priv;
731
732 rt2x00_desc_read(txd, 1, &word);
733 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
734 ring->entry[i].data_dma);
735 rt2x00_desc_write(txd, 1, word);
736
737 rt2x00_desc_read(txd, 0, &word);
738 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
739 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
740 rt2x00_desc_write(txd, 0, word);
741 }
742
743 rt2x00_ring_index_clear(ring);
744}
745
746static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
747{
748 u32 reg;
749
750 /*
751 * Initialize rings.
752 */
753 rt2500pci_init_rxring(rt2x00dev);
754 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
755 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
756 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
757 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
758
759 /*
760 * Initialize registers.
761 */
762 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
763 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
764 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
765 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
766 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
767 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
768 rt2x00dev->bcn[1].stats.limit);
769 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
770 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
771 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
772
773 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
774 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
775 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
776 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
777
778 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
779 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
780 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
781 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
782
783 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
784 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
785 rt2x00dev->bcn[1].data_dma);
786 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
787
788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
790 rt2x00dev->bcn[0].data_dma);
791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
792
793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
794 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
797
798 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
799 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
800 rt2x00dev->rx->data_dma);
801 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
802
803 return 0;
804}
805
806static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
807{
808 u32 reg;
809
810 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
813 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
814
815 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
816 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
817 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
818 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
819 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
820
821 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
822 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
823 rt2x00dev->rx->data_size / 128);
824 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
825
826 /*
827 * Always use CWmin and CWmax set in descriptor.
828 */
829 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
830 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
831 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
832
833 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
834
835 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
836 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
837 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
838 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
839 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
840 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
841 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
842 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
843 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
844 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
845
846 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
847 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
848 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
849 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
850 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
851 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
852
853 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
854 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
855 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
856 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
857 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
858 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
859
860 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
861 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
862 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
863 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
864 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
865 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
866
867 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
868 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
869 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
870 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
871 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
872 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
873 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
874 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
875 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
876 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
877
878 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
879 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
880 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
881 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
882 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
883 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
884 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
885 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
886 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
887
888 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
889
890 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
891 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
892
893 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
894 return -EBUSY;
895
896 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
897 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
898
899 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
900 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
901 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
902
903 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
904 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
905 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
906 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
907 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
908 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
909 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
910 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
911
912 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
913
914 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
915
916 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
917 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
918 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
919 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
920 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
921
922 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
923 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
924 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
925 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
926
927 /*
928 * We must clear the FCS and FIFO error count.
929 * These registers are cleared on read,
930 * so we may pass a useless variable to store the value.
931 */
932 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
933 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
934
935 return 0;
936}
937
938static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
939{
940 unsigned int i;
941 u16 eeprom;
942 u8 reg_id;
943 u8 value;
944
945 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
946 rt2500pci_bbp_read(rt2x00dev, 0, &value);
947 if ((value != 0xff) && (value != 0x00))
948 goto continue_csr_init;
949 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
950 udelay(REGISTER_BUSY_DELAY);
951 }
952
953 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
954 return -EACCES;
955
956continue_csr_init:
957 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
958 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
959 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
960 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
961 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
962 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
963 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
964 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
965 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
966 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
967 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
968 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
969 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
970 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
971 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
972 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
973 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
974 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
975 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
976 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
977 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
978 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
979 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
980 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
981 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
982 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
984 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
986 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
987
988 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
989 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
990 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
991
992 if (eeprom != 0xffff && eeprom != 0x0000) {
993 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
994 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
995 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
996 reg_id, value);
997 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
998 }
999 }
1000 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1001
1002 return 0;
1003}
1004
1005/*
1006 * Device state switch handlers.
1007 */
1008static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1009 enum dev_state state)
1010{
1011 u32 reg;
1012
1013 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1014 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1015 state == STATE_RADIO_RX_OFF);
1016 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1017}
1018
1019static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1020 enum dev_state state)
1021{
1022 int mask = (state == STATE_RADIO_IRQ_OFF);
1023 u32 reg;
1024
1025 /*
1026 * When interrupts are being enabled, the interrupt registers
1027 * should clear the register to assure a clean state.
1028 */
1029 if (state == STATE_RADIO_IRQ_ON) {
1030 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1031 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1032 }
1033
1034 /*
1035 * Only toggle the interrupts bits we are going to use.
1036 * Non-checked interrupt bits are disabled by default.
1037 */
1038 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1039 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1040 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1041 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1042 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1043 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1044 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1045}
1046
1047static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1048{
1049 /*
1050 * Initialize all registers.
1051 */
1052 if (rt2500pci_init_rings(rt2x00dev) ||
1053 rt2500pci_init_registers(rt2x00dev) ||
1054 rt2500pci_init_bbp(rt2x00dev)) {
1055 ERROR(rt2x00dev, "Register initialization failed.\n");
1056 return -EIO;
1057 }
1058
1059 /*
1060 * Enable interrupts.
1061 */
1062 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1063
1064 /*
1065 * Enable LED
1066 */
1067 rt2500pci_enable_led(rt2x00dev);
1068
1069 return 0;
1070}
1071
1072static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1073{
1074 u32 reg;
1075
1076 /*
1077 * Disable LED
1078 */
1079 rt2500pci_disable_led(rt2x00dev);
1080
1081 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1082
1083 /*
1084 * Disable synchronisation.
1085 */
1086 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1087
1088 /*
1089 * Cancel RX and TX.
1090 */
1091 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1092 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1093 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1094
1095 /*
1096 * Disable interrupts.
1097 */
1098 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1099}
1100
1101static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1102 enum dev_state state)
1103{
1104 u32 reg;
1105 unsigned int i;
1106 char put_to_sleep;
1107 char bbp_state;
1108 char rf_state;
1109
1110 put_to_sleep = (state != STATE_AWAKE);
1111
1112 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1113 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1114 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1115 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1116 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1117 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1118
1119 /*
1120 * Device is not guaranteed to be in the requested state yet.
1121 * We must wait until the register indicates that the
1122 * device has entered the correct state.
1123 */
1124 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1125 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1126 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1127 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1128 if (bbp_state == state && rf_state == state)
1129 return 0;
1130 msleep(10);
1131 }
1132
1133 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1134 "current device state: bbp %d and rf %d.\n",
1135 state, bbp_state, rf_state);
1136
1137 return -EBUSY;
1138}
1139
1140static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1141 enum dev_state state)
1142{
1143 int retval = 0;
1144
1145 switch (state) {
1146 case STATE_RADIO_ON:
1147 retval = rt2500pci_enable_radio(rt2x00dev);
1148 break;
1149 case STATE_RADIO_OFF:
1150 rt2500pci_disable_radio(rt2x00dev);
1151 break;
1152 case STATE_RADIO_RX_ON:
1153 case STATE_RADIO_RX_OFF:
1154 rt2500pci_toggle_rx(rt2x00dev, state);
1155 break;
1156 case STATE_DEEP_SLEEP:
1157 case STATE_SLEEP:
1158 case STATE_STANDBY:
1159 case STATE_AWAKE:
1160 retval = rt2500pci_set_state(rt2x00dev, state);
1161 break;
1162 default:
1163 retval = -ENOTSUPP;
1164 break;
1165 }
1166
1167 return retval;
1168}
1169
1170/*
1171 * TX descriptor initialization
1172 */
1173static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1174 struct data_desc *txd,
4150c572 1175 struct txdata_entry_desc *desc,
95ea3627
ID		 1176 struct ieee80211_hdr *ieee80211hdr,
1177 unsigned int length,
1178 struct ieee80211_tx_control *control)
1179{
1180 u32 word;
1181
1182 /*
1183 * Start writing the descriptor words.
1184 */
1185 rt2x00_desc_read(txd, 2, &word);
1186 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1187 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1188 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1189 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1190 rt2x00_desc_write(txd, 2, word);
1191
1192 rt2x00_desc_read(txd, 3, &word);
1193 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1194 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1195 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1196 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1197 rt2x00_desc_write(txd, 3, word);
1198
1199 rt2x00_desc_read(txd, 10, &word);
1200 rt2x00_set_field32(&word, TXD_W10_RTS,
1201 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1202 rt2x00_desc_write(txd, 10, word);
1203
1204 rt2x00_desc_read(txd, 0, &word);
1205 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1206 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1207 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1208 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1209 rt2x00_set_field32(&word, TXD_W0_ACK,
1210 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1211 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1212 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1213 rt2x00_set_field32(&word, TXD_W0_OFDM,
1214 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1215 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1216 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1217 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1218 !!(control->flags &
1219 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1220 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1221 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1222 rt2x00_desc_write(txd, 0, word);
1223}
1224
1225/*
1226 * TX data initialization
1227 */
1228static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1229 unsigned int queue)
1230{
1231 u32 reg;
1232
1233 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1234 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1235 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1236 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1237 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1238 }
1239 return;
1240 }
1241
1242 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1243 if (queue == IEEE80211_TX_QUEUE_DATA0)
1244 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1245 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1246 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1247 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1248 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1249 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1250}
1251
1252/*
1253 * RX control handlers
1254 */
4150c572
JB		 1255static void rt2500pci_fill_rxdone(struct data_entry *entry,
1256 struct rxdata_entry_desc *desc)
95ea3627
ID		 1257{
1258 struct data_desc *rxd = entry->priv;
1259 u32 word0;
1260 u32 word2;
1261
1262 rt2x00_desc_read(rxd, 0, &word0);
1263 rt2x00_desc_read(rxd, 2, &word2);
1264
4150c572
JB		 1265 desc->flags = 0;
1266 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1267 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1268 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1269 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1270
4150c572
JB		 1271 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1272 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1273 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1274 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1275 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1276}
1277
1278/*
1279 * Interrupt functions.
1280 */
1281static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1282{
1283 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1284 struct data_entry *entry;
1285 struct data_desc *txd;
1286 u32 word;
1287 int tx_status;
1288 int retry;
1289
1290 while (!rt2x00_ring_empty(ring)) {
1291 entry = rt2x00_get_data_entry_done(ring);
1292 txd = entry->priv;
1293 rt2x00_desc_read(txd, 0, &word);
1294
1295 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1296 !rt2x00_get_field32(word, TXD_W0_VALID))
1297 break;
1298
1299 /*
1300 * Obtain the status about this packet.
1301 */
1302 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1303 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1304
1305 rt2x00lib_txdone(entry, tx_status, retry);
1306
1307 /*
1308 * Make this entry available for reuse.
1309 */
1310 entry->flags = 0;
1311 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1312 rt2x00_desc_write(txd, 0, word);
1313 rt2x00_ring_index_done_inc(ring);
1314 }
1315
1316 /*
1317 * If the data ring was full before the txdone handler
1318 * we must make sure the packet queue in the mac80211 stack
1319 * is reenabled when the txdone handler has finished.
1320 */
1321 entry = ring->entry;
1322 if (!rt2x00_ring_full(ring))
1323 ieee80211_wake_queue(rt2x00dev->hw,
1324 entry->tx_status.control.queue);
1325}
1326
1327static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1328{
1329 struct rt2x00_dev *rt2x00dev = dev_instance;
1330 u32 reg;
1331
1332 /*
1333 * Get the interrupt sources & saved to local variable.
1334 * Write register value back to clear pending interrupts.
1335 */
1336 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1337 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1338
1339 if (!reg)
1340 return IRQ_NONE;
1341
1342 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1343 return IRQ_HANDLED;
1344
1345 /*
1346 * Handle interrupts, walk through all bits
1347 * and run the tasks, the bits are checked in order of
1348 * priority.
1349 */
1350
1351 /*
1352 * 1 - Beacon timer expired interrupt.
1353 */
1354 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1355 rt2x00lib_beacondone(rt2x00dev);
1356
1357 /*
1358 * 2 - Rx ring done interrupt.
1359 */
1360 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1361 rt2x00pci_rxdone(rt2x00dev);
1362
1363 /*
1364 * 3 - Atim ring transmit done interrupt.
1365 */
1366 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1367 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1368
1369 /*
1370 * 4 - Priority ring transmit done interrupt.
1371 */
1372 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1373 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1374
1375 /*
1376 * 5 - Tx ring transmit done interrupt.
1377 */
1378 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1379 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1380
1381 return IRQ_HANDLED;
1382}
1383
1384/*
1385 * Device probe functions.
1386 */
1387static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1388{
1389 struct eeprom_93cx6 eeprom;
1390 u32 reg;
1391 u16 word;
1392 u8 *mac;
1393
1394 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1395
1396 eeprom.data = rt2x00dev;
1397 eeprom.register_read = rt2500pci_eepromregister_read;
1398 eeprom.register_write = rt2500pci_eepromregister_write;
1399 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1400 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1401 eeprom.reg_data_in = 0;
1402 eeprom.reg_data_out = 0;
1403 eeprom.reg_data_clock = 0;
1404 eeprom.reg_chip_select = 0;
1405
1406 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1407 EEPROM_SIZE / sizeof(u16));
1408
1409 /*
1410 * Start validation of the data that has been read.
1411 */
1412 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1413 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1414 DECLARE_MAC_BUF(macbuf);
1415
95ea3627 1416 random_ether_addr(mac);
0795af57
JP		 1417 EEPROM(rt2x00dev, "MAC: %s\n",
1418 print_mac(macbuf, mac));
95ea3627
ID		 1419 }
1420
1421 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1422 if (word == 0xffff) {
1423 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1424 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1425 ANTENNA_SW_DIVERSITY);
1426 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1427 ANTENNA_SW_DIVERSITY);
1428 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1429 LED_MODE_DEFAULT);
95ea3627
ID		 1430 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1431 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1432 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1433 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1434 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1435 }
1436
1437 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1438 if (word == 0xffff) {
1439 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1440 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1441 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1442 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1443 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1444 }
1445
1446 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1447 if (word == 0xffff) {
1448 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1449 DEFAULT_RSSI_OFFSET);
1450 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1451 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1452 }
1453
1454 return 0;
1455}
1456
1457static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1458{
1459 u32 reg;
1460 u16 value;
1461 u16 eeprom;
1462
1463 /*
1464 * Read EEPROM word for configuration.
1465 */
1466 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1467
1468 /*
1469 * Identify RF chipset.
1470 */
1471 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1472 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1473 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1474
1475 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1476 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1477 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1478 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1479 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1480 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1481 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1482 return -ENODEV;
1483 }
1484
1485 /*
1486 * Identify default antenna configuration.
1487 */
1488 rt2x00dev->hw->conf.antenna_sel_tx =
1489 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1490 rt2x00dev->hw->conf.antenna_sel_rx =
1491 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1492
1493 /*
1494 * Store led mode, for correct led behaviour.
1495 */
1496 rt2x00dev->led_mode =
1497 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1498
1499 /*
1500 * Detect if this device has an hardware controlled radio.
1501 */
81873e9c 1502#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1503 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1504 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1505#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1506
1507 /*
1508 * Check if the BBP tuning should be enabled.
1509 */
1510 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1511
1512 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1513 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1514
1515 /*
1516 * Read the RSSI <-> dBm offset information.
1517 */
1518 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1519 rt2x00dev->rssi_offset =
1520 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1521
1522 return 0;
1523}
1524
1525/*
1526 * RF value list for RF2522
1527 * Supports: 2.4 GHz
1528 */
1529static const struct rf_channel rf_vals_bg_2522[] = {
1530 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1531 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1532 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1533 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1534 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1535 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1536 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1537 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1538 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1539 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1540 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1541 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1542 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1543 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1544};
1545
1546/*
1547 * RF value list for RF2523
1548 * Supports: 2.4 GHz
1549 */
1550static const struct rf_channel rf_vals_bg_2523[] = {
1551 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1552 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1553 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1554 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1555 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1556 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1557 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1558 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1559 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1560 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1561 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1562 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1563 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1564 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1565};
1566
1567/*
1568 * RF value list for RF2524
1569 * Supports: 2.4 GHz
1570 */
1571static const struct rf_channel rf_vals_bg_2524[] = {
1572 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1573 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1574 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1575 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1576 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1577 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1578 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1579 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1580 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1581 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1582 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1583 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1584 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1585 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1586};
1587
1588/*
1589 * RF value list for RF2525
1590 * Supports: 2.4 GHz
1591 */
1592static const struct rf_channel rf_vals_bg_2525[] = {
1593 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1594 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1595 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1596 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1597 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1598 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1599 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1600 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1601 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1602 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1603 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1604 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1605 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1606 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1607};
1608
1609/*
1610 * RF value list for RF2525e
1611 * Supports: 2.4 GHz
1612 */
1613static const struct rf_channel rf_vals_bg_2525e[] = {
1614 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1615 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1616 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1617 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1618 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1619 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1620 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1621 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1622 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1623 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1624 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1625 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1626 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1627 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1628};
1629
1630/*
1631 * RF value list for RF5222
1632 * Supports: 2.4 GHz & 5.2 GHz
1633 */
1634static const struct rf_channel rf_vals_5222[] = {
1635 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1636 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1637 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1638 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1639 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1640 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1641 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1642 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1643 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1644 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1645 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1646 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1647 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1648 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1649
1650 /* 802.11 UNI / HyperLan 2 */
1651 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1652 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1653 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1654 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1655 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1656 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1657 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1658 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1659
1660 /* 802.11 HyperLan 2 */
1661 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1662 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1663 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1664 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1665 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1666 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1667 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1668 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1669 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1670 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1671
1672 /* 802.11 UNII */
1673 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1674 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1675 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1676 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1677 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1678};
1679
1680static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1681{
1682 struct hw_mode_spec *spec = &rt2x00dev->spec;
1683 u8 *txpower;
1684 unsigned int i;
1685
1686 /*
1687 * Initialize all hw fields.
1688 */
4150c572 1689 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1690 rt2x00dev->hw->extra_tx_headroom = 0;
1691 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1692 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1693 rt2x00dev->hw->queues = 2;
1694
1695 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1696 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1697 rt2x00_eeprom_addr(rt2x00dev,
1698 EEPROM_MAC_ADDR_0));
1699
1700 /*
1701 * Convert tx_power array in eeprom.
1702 */
1703 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1704 for (i = 0; i < 14; i++)
1705 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1706
1707 /*
1708 * Initialize hw_mode information.
1709 */
1710 spec->num_modes = 2;
1711 spec->num_rates = 12;
1712 spec->tx_power_a = NULL;
1713 spec->tx_power_bg = txpower;
1714 spec->tx_power_default = DEFAULT_TXPOWER;
1715
1716 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1717 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1718 spec->channels = rf_vals_bg_2522;
1719 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1720 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1721 spec->channels = rf_vals_bg_2523;
1722 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1723 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1724 spec->channels = rf_vals_bg_2524;
1725 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1726 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1727 spec->channels = rf_vals_bg_2525;
1728 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1729 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1730 spec->channels = rf_vals_bg_2525e;
1731 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1732 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1733 spec->channels = rf_vals_5222;
1734 spec->num_modes = 3;
1735 }
1736}
1737
1738static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1739{
1740 int retval;
1741
1742 /*
1743 * Allocate eeprom data.
1744 */
1745 retval = rt2500pci_validate_eeprom(rt2x00dev);
1746 if (retval)
1747 return retval;
1748
1749 retval = rt2500pci_init_eeprom(rt2x00dev);
1750 if (retval)
1751 return retval;
1752
1753 /*
1754 * Initialize hw specifications.
1755 */
1756 rt2500pci_probe_hw_mode(rt2x00dev);
1757
1758 /*
1759 * This device requires the beacon ring
1760 */
066cb637 1761 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1762
1763 /*
1764 * Set the rssi offset.
1765 */
1766 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1767
1768 return 0;
1769}
1770
1771/*
1772 * IEEE80211 stack callback functions.
1773 */
4150c572
JB		 1774static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1775 unsigned int changed_flags,
1776 unsigned int *total_flags,
1777 int mc_count,
1778 struct dev_addr_list *mc_list)
1779{
1780 struct rt2x00_dev *rt2x00dev = hw->priv;
1781 struct interface *intf = &rt2x00dev->interface;
1782 u32 reg;
1783
1784 /*
1785 * Mask off any flags we are going to ignore from
1786 * the total_flags field.
1787 */
1788 *total_flags &=
1789 FIF_ALLMULTI |
1790 FIF_FCSFAIL |
1791 FIF_PLCPFAIL |
1792 FIF_CONTROL |
1793 FIF_OTHER_BSS |
1794 FIF_PROMISC_IN_BSS;
1795
1796 /*
1797 * Apply some rules to the filters:
1798 * - Some filters imply different filters to be set.
1799 * - Some things we can't filter out at all.
1800 * - Some filters are set based on interface type.
1801 */
1802 if (mc_count)
1803 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1804 if (*total_flags & FIF_OTHER_BSS ||
1805 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1806 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1807 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1808 *total_flags |= FIF_PROMISC_IN_BSS;
1809
1810 /*
1811 * Check if there is any work left for us.
1812 */
1813 if (intf->filter == *total_flags)
1814 return;
1815 intf->filter = *total_flags;
1816
1817 /*
1818 * Start configuration steps.
1819 * Note that the version error will always be dropped
1820 * and broadcast frames will always be accepted since
1821 * there is no filter for it at this time.
1822 */
1823 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1824 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1825 !(*total_flags & FIF_FCSFAIL));
1826 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1827 !(*total_flags & FIF_PLCPFAIL));
1828 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1829 !(*total_flags & FIF_CONTROL));
1830 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1831 !(*total_flags & FIF_PROMISC_IN_BSS));
1832 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1833 !(*total_flags & FIF_PROMISC_IN_BSS));
1834 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1835 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1836 !(*total_flags & FIF_ALLMULTI));
1837 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1838 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1839}
1840
95ea3627
ID		 1841static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1842 u32 short_retry, u32 long_retry)
1843{
1844 struct rt2x00_dev *rt2x00dev = hw->priv;
1845 u32 reg;
1846
1847 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1848 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1849 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1850 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1851
1852 return 0;
1853}
1854
1855static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1856{
1857 struct rt2x00_dev *rt2x00dev = hw->priv;
1858 u64 tsf;
1859 u32 reg;
1860
1861 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1862 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1863 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1864 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1865
1866 return tsf;
1867}
1868
1869static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1870{
1871 struct rt2x00_dev *rt2x00dev = hw->priv;
1872
1873 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1874 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1875}
1876
1877static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1878{
1879 struct rt2x00_dev *rt2x00dev = hw->priv;
1880 u32 reg;
1881
1882 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1883 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1884}
1885
1886static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1887 .tx = rt2x00mac_tx,
4150c572
JB		 1888 .start = rt2x00mac_start,
1889 .stop = rt2x00mac_stop,
95ea3627
ID		 1890 .add_interface = rt2x00mac_add_interface,
1891 .remove_interface = rt2x00mac_remove_interface,
1892 .config = rt2x00mac_config,
1893 .config_interface = rt2x00mac_config_interface,
4150c572 1894 .configure_filter = rt2500pci_configure_filter,
95ea3627
ID		 1895 .get_stats = rt2x00mac_get_stats,
1896 .set_retry_limit = rt2500pci_set_retry_limit,
5c58ee51 1897 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1898 .conf_tx = rt2x00mac_conf_tx,
1899 .get_tx_stats = rt2x00mac_get_tx_stats,
1900 .get_tsf = rt2500pci_get_tsf,
1901 .reset_tsf = rt2500pci_reset_tsf,
1902 .beacon_update = rt2x00pci_beacon_update,
1903 .tx_last_beacon = rt2500pci_tx_last_beacon,
1904};
1905
1906static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1907 .irq_handler = rt2500pci_interrupt,
1908 .probe_hw = rt2500pci_probe_hw,
1909 .initialize = rt2x00pci_initialize,
1910 .uninitialize = rt2x00pci_uninitialize,
1911 .set_device_state = rt2500pci_set_device_state,
95ea3627 1912 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1913 .link_stats = rt2500pci_link_stats,
1914 .reset_tuner = rt2500pci_reset_tuner,
1915 .link_tuner = rt2500pci_link_tuner,
1916 .write_tx_desc = rt2500pci_write_tx_desc,
1917 .write_tx_data = rt2x00pci_write_tx_data,
1918 .kick_tx_queue = rt2500pci_kick_tx_queue,
1919 .fill_rxdone = rt2500pci_fill_rxdone,
1920 .config_mac_addr = rt2500pci_config_mac_addr,
1921 .config_bssid = rt2500pci_config_bssid,
95ea3627 1922 .config_type = rt2500pci_config_type,
5c58ee51 1923 .config_preamble = rt2500pci_config_preamble,
95ea3627
ID		 1924 .config = rt2500pci_config,
1925};
1926
1927static const struct rt2x00_ops rt2500pci_ops = {
1928 .name = DRV_NAME,
1929 .rxd_size = RXD_DESC_SIZE,
1930 .txd_size = TXD_DESC_SIZE,
1931 .eeprom_size = EEPROM_SIZE,
1932 .rf_size = RF_SIZE,
1933 .lib = &rt2500pci_rt2x00_ops,
1934 .hw = &rt2500pci_mac80211_ops,
1935#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1936 .debugfs = &rt2500pci_rt2x00debug,
1937#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1938};
1939
1940/*
1941 * RT2500pci module information.
1942 */
1943static struct pci_device_id rt2500pci_device_table[] = {
1944 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1945 { 0, }
1946};
1947
1948MODULE_AUTHOR(DRV_PROJECT);
1949MODULE_VERSION(DRV_VERSION);
1950MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1951MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1952MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1953MODULE_LICENSE("GPL");
1954
1955static struct pci_driver rt2500pci_driver = {
1956 .name = DRV_NAME,
1957 .id_table = rt2500pci_device_table,
1958 .probe = rt2x00pci_probe,
1959 .remove = __devexit_p(rt2x00pci_remove),
1960 .suspend = rt2x00pci_suspend,
1961 .resume = rt2x00pci_resume,
1962};
1963
1964static int __init rt2500pci_init(void)
1965{
1966 return pci_register_driver(&rt2500pci_driver);
1967}
1968
1969static void __exit rt2500pci_exit(void)
1970{
1971 pci_unregister_driver(&rt2500pci_driver);
1972}
1973
1974module_init(rt2500pci_init);
1975module_exit(rt2500pci_exit);
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