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rt2x00: Move packet filter flags
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2500PCI_RFKILL
235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
dcf5475b 244#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 245
246/*
247 * Configuration handlers.
248 */
4abee4bb
ID		 249static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
250 __le32 *mac)
95ea3627 251{
4abee4bb
ID		 252 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
253 (2 * sizeof(__le32)));
95ea3627
ID		 254}
255
4abee4bb
ID		 256static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
257 __le32 *bssid)
95ea3627 258{
4abee4bb
ID		 259 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
260 (2 * sizeof(__le32)));
95ea3627
ID		 261}
262
feb24691
ID		 263static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
264 const int tsf_sync)
95ea3627
ID		 265{
266 u32 reg;
267
268 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
269
95ea3627
ID		 270 /*
271 * Enable beacon config
272 */
273 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
274 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 275 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 276 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
277 rt2x00lib_get_ring(rt2x00dev,
278 IEEE80211_TX_QUEUE_BEACON)
279 ->tx_params.cw_min);
280 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
281
282 /*
283 * Enable synchronisation.
284 */
285 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572 286 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
3867705b 287 rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON));
95ea3627 288 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 289 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 290 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
291}
292
5c58ee51
ID		 293static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
294 const int short_preamble,
295 const int ack_timeout,
296 const int ack_consume_time)
95ea3627 297{
5c58ee51 298 int preamble_mask;
95ea3627 299 u32 reg;
95ea3627 300
5c58ee51
ID		 301 /*
302 * When short preamble is enabled, we should set bit 0x08
303 */
304 preamble_mask = short_preamble << 3;
95ea3627
ID		 305
306 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 307 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
308 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 309 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
310
95ea3627 311 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 312 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 313 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
314 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
315 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
316
317 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 318 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 319 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
320 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
321 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
322
323 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 324 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 325 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
326 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
327 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
328
329 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 330 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 331 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
332 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
333 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
334}
335
336static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 337 const int basic_rate_mask)
95ea3627 338{
5c58ee51 339 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 340}
341
342static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 343 struct rf_channel *rf, const int txpower)
95ea3627 344{
95ea3627
ID		 345 u8 r70;
346
95ea3627
ID		 347 /*
348 * Set TXpower.
349 */
5c58ee51 350 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 351
352 /*
353 * Switch on tuning bits.
354 * For RT2523 devices we do not need to update the R1 register.
355 */
356 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 357 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
358 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 359
360 /*
361 * For RT2525 we should first set the channel to half band higher.
362 */
363 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
364 static const u32 vals[] = {
365 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
366 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
367 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
368 0x00080d2e, 0x00080d3a
369 };
370
5c58ee51
ID		 371 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
372 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
373 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
374 if (rf->rf4)
375 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 376 }
377
5c58ee51
ID		 378 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
379 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
380 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
381 if (rf->rf4)
382 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 383
384 /*
385 * Channel 14 requires the Japan filter bit to be set.
386 */
387 r70 = 0x46;
5c58ee51 388 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 389 rt2500pci_bbp_write(rt2x00dev, 70, r70);
390
391 msleep(1);
392
393 /*
394 * Switch off tuning bits.
395 * For RT2523 devices we do not need to update the R1 register.
396 */
397 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 398 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
399 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 400 }
401
5c58ee51
ID		 402 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
403 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 404
405 /*
406 * Clear false CRC during channel switch.
407 */
5c58ee51 408 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 409}
410
411static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
412 const int txpower)
413{
414 u32 rf3;
415
416 rt2x00_rf_read(rt2x00dev, 3, &rf3);
417 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
418 rt2500pci_rf_write(rt2x00dev, 3, rf3);
419}
420
421static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 422 struct antenna_setup *ant)
95ea3627
ID		 423{
424 u32 reg;
425 u8 r14;
426 u8 r2;
427
428 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
429 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
430 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
431
432 /*
433 * Configure the TX antenna.
434 */
addc81bd 435 switch (ant->tx) {
95ea3627
ID		 436 case ANTENNA_A:
437 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
438 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
439 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
440 break;
39e75857
ID		 441 case ANTENNA_HW_DIVERSITY:
442 case ANTENNA_SW_DIVERSITY:
443 /*
444 * NOTE: We should never come here because rt2x00lib is
445 * supposed to catch this and send us the correct antenna
446 * explicitely. However we are nog going to bug about this.
447 * Instead, just default to antenna B.
448 */
95ea3627
ID		 449 case ANTENNA_B:
450 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
451 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
452 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
453 break;
454 }
455
456 /*
457 * Configure the RX antenna.
458 */
addc81bd 459 switch (ant->rx) {
95ea3627
ID		 460 case ANTENNA_A:
461 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
462 break;
39e75857
ID		 463 case ANTENNA_HW_DIVERSITY:
464 case ANTENNA_SW_DIVERSITY:
465 /*
466 * NOTE: We should never come here because rt2x00lib is
467 * supposed to catch this and send us the correct antenna
468 * explicitely. However we are nog going to bug about this.
469 * Instead, just default to antenna B.
470 */
95ea3627
ID		 471 case ANTENNA_B:
472 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
473 break;
474 }
475
476 /*
477 * RT2525E and RT5222 need to flip TX I/Q
478 */
479 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
480 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
481 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
482 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
483 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
484
485 /*
486 * RT2525E does not need RX I/Q Flip.
487 */
488 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
489 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
490 } else {
491 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
492 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
493 }
494
495 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
496 rt2500pci_bbp_write(rt2x00dev, 14, r14);
497 rt2500pci_bbp_write(rt2x00dev, 2, r2);
498}
499
500static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 501 struct rt2x00lib_conf *libconf)
95ea3627
ID		 502{
503 u32 reg;
504
505 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 506 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 507 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
508
509 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 510 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
511 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 512 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
513
514 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 515 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
516 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 517 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
518
519 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
520 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
521 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
522 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
523
524 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 525 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
526 libconf->conf->beacon_int * 16);
527 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
528 libconf->conf->beacon_int * 16);
95ea3627
ID		 529 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
530}
531
532static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
533 const unsigned int flags,
5c58ee51 534 struct rt2x00lib_conf *libconf)
95ea3627 535{
95ea3627 536 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 537 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 538 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 539 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
540 libconf->conf->power_level);
95ea3627 541 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 542 rt2500pci_config_txpower(rt2x00dev,
543 libconf->conf->power_level);
95ea3627 544 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 545 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 546 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 547 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 548}
549
550/*
551 * LED functions.
552 */
553static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
554{
555 u32 reg;
556
557 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
558
559 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
560 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
ddc827f9
ID		 561 rt2x00_set_field32(&reg, LEDCSR_LINK,
562 (rt2x00dev->led_mode != LED_MODE_ASUS));
563 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
564 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
95ea3627
ID		 565 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
566}
567
568static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
569{
570 u32 reg;
571
572 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
573 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
574 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
575 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
576}
577
578/*
579 * Link tuning
580 */
ebcf26da
ID		 581static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
582 struct link_qual *qual)
95ea3627
ID		 583{
584 u32 reg;
585
586 /*
587 * Update FCS error count from register.
588 */
589 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 590 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 591
592 /*
593 * Update False CCA count from register.
594 */
595 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 596 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 597}
598
599static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
600{
601 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
602 rt2x00dev->link.vgc_level = 0x48;
603}
604
605static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
606{
607 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
608 u8 r17;
609
610 /*
611 * To prevent collisions with MAC ASIC on chipsets
612 * up to version C the link tuning should halt after 20
613 * seconds.
614 */
755a957d 615 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
95ea3627
ID		 616 rt2x00dev->link.count > 20)
617 return;
618
619 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
620
621 /*
622 * Chipset versions C and lower should directly continue
623 * to the dynamic CCA tuning.
624 */
755a957d 625 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
95ea3627
ID		 626 goto dynamic_cca_tune;
627
628 /*
629 * A too low RSSI will cause too much false CCA which will
630 * then corrupt the R17 tuning. To remidy this the tuning should
631 * be stopped (While making sure the R17 value will not exceed limits)
632 */
633 if (rssi < -80 && rt2x00dev->link.count > 20) {
634 if (r17 >= 0x41) {
635 r17 = rt2x00dev->link.vgc_level;
636 rt2500pci_bbp_write(rt2x00dev, 17, r17);
637 }
638 return;
639 }
640
641 /*
642 * Special big-R17 for short distance
643 */
644 if (rssi >= -58) {
645 if (r17 != 0x50)
646 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
647 return;
648 }
649
650 /*
651 * Special mid-R17 for middle distance
652 */
653 if (rssi >= -74) {
654 if (r17 != 0x41)
655 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
656 return;
657 }
658
659 /*
660 * Leave short or middle distance condition, restore r17
661 * to the dynamic tuning range.
662 */
663 if (r17 >= 0x41) {
664 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
665 return;
666 }
667
668dynamic_cca_tune:
669
670 /*
671 * R17 is inside the dynamic tuning range,
672 * start tuning the link based on the false cca counter.
673 */
ebcf26da 674 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 675 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
676 rt2x00dev->link.vgc_level = r17;
ebcf26da 677 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 678 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
679 rt2x00dev->link.vgc_level = r17;
680 }
681}
682
683/*
684 * Initialization functions.
685 */
686static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
687{
688 struct data_ring *ring = rt2x00dev->rx;
4bd7c452 689 __le32 *rxd;
95ea3627
ID		 690 unsigned int i;
691 u32 word;
692
693 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
694
695 for (i = 0; i < ring->stats.limit; i++) {
696 rxd = ring->entry[i].priv;
697
698 rt2x00_desc_read(rxd, 1, &word);
699 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
700 ring->entry[i].data_dma);
701 rt2x00_desc_write(rxd, 1, word);
702
703 rt2x00_desc_read(rxd, 0, &word);
704 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
705 rt2x00_desc_write(rxd, 0, word);
706 }
707
708 rt2x00_ring_index_clear(rt2x00dev->rx);
709}
710
711static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
712{
713 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
4bd7c452 714 __le32 *txd;
95ea3627
ID		 715 unsigned int i;
716 u32 word;
717
718 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
719
720 for (i = 0; i < ring->stats.limit; i++) {
721 txd = ring->entry[i].priv;
722
723 rt2x00_desc_read(txd, 1, &word);
724 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
725 ring->entry[i].data_dma);
726 rt2x00_desc_write(txd, 1, word);
727
728 rt2x00_desc_read(txd, 0, &word);
729 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
730 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
731 rt2x00_desc_write(txd, 0, word);
732 }
733
734 rt2x00_ring_index_clear(ring);
735}
736
737static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
738{
739 u32 reg;
740
741 /*
742 * Initialize rings.
743 */
744 rt2500pci_init_rxring(rt2x00dev);
745 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
746 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
747 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
748 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
749
750 /*
751 * Initialize registers.
752 */
753 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
754 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
755 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
756 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
757 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
758 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
759 rt2x00dev->bcn[1].stats.limit);
760 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
761 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
762 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
763
764 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
765 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
766 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
767 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
768
769 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
770 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
771 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
772 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
773
774 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
775 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
776 rt2x00dev->bcn[1].data_dma);
777 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
778
779 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
780 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
781 rt2x00dev->bcn[0].data_dma);
782 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
783
784 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
785 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
786 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
787 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
788
789 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
790 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
791 rt2x00dev->rx->data_dma);
792 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
793
794 return 0;
795}
796
797static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
798{
799 u32 reg;
800
801 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
802 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
803 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
804 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
805
806 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
807 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
808 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
809 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
810 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
811
812 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
813 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
814 rt2x00dev->rx->data_size / 128);
815 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
816
817 /*
818 * Always use CWmin and CWmax set in descriptor.
819 */
820 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
821 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
822 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
823
824 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
825
826 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
827 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
828 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
829 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
830 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
831 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
832 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
833 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
834 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
835 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
836
837 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
838 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
839 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
840 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
841 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
842 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
843
844 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
845 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
846 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
847 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
848 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
849 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
850
851 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
852 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
853 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
854 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
855 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
856 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
857
858 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
866 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
867 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
868
869 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
870 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
871 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
872 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
873 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
874 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
875 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
876 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
877 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
878
879 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
880
881 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
882 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
883
884 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
885 return -EBUSY;
886
887 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
888 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
889
890 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
891 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
892 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
893
894 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
895 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
896 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
897 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
898 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
899 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
900 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
901 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
902
903 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
904
905 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
906
907 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
908 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
909 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
910 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
911 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
912
913 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
914 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
915 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
916 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
917
918 /*
919 * We must clear the FCS and FIFO error count.
920 * These registers are cleared on read,
921 * so we may pass a useless variable to store the value.
922 */
923 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
924 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
925
926 return 0;
927}
928
929static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
930{
931 unsigned int i;
932 u16 eeprom;
933 u8 reg_id;
934 u8 value;
935
936 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
937 rt2500pci_bbp_read(rt2x00dev, 0, &value);
938 if ((value != 0xff) && (value != 0x00))
939 goto continue_csr_init;
940 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
941 udelay(REGISTER_BUSY_DELAY);
942 }
943
944 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
945 return -EACCES;
946
947continue_csr_init:
948 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
949 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
950 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
951 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
952 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
953 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
954 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
955 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
956 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
957 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
958 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
959 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
960 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
961 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
962 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
963 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
964 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
965 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
966 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
967 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
968 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
969 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
970 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
971 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
972 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
973 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
974 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
975 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
976 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
977 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
978
979 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
980 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
981 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
982
983 if (eeprom != 0xffff && eeprom != 0x0000) {
984 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
985 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
986 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
987 reg_id, value);
988 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
989 }
990 }
991 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
992
993 return 0;
994}
995
996/*
997 * Device state switch handlers.
998 */
999static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1000 enum dev_state state)
1001{
1002 u32 reg;
1003
1004 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1005 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1006 state == STATE_RADIO_RX_OFF);
1007 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1008}
1009
1010static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1011 enum dev_state state)
1012{
1013 int mask = (state == STATE_RADIO_IRQ_OFF);
1014 u32 reg;
1015
1016 /*
1017 * When interrupts are being enabled, the interrupt registers
1018 * should clear the register to assure a clean state.
1019 */
1020 if (state == STATE_RADIO_IRQ_ON) {
1021 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1022 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1023 }
1024
1025 /*
1026 * Only toggle the interrupts bits we are going to use.
1027 * Non-checked interrupt bits are disabled by default.
1028 */
1029 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1030 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1031 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1032 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1033 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1034 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1035 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1036}
1037
1038static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1039{
1040 /*
1041 * Initialize all registers.
1042 */
1043 if (rt2500pci_init_rings(rt2x00dev) ||
1044 rt2500pci_init_registers(rt2x00dev) ||
1045 rt2500pci_init_bbp(rt2x00dev)) {
1046 ERROR(rt2x00dev, "Register initialization failed.\n");
1047 return -EIO;
1048 }
1049
1050 /*
1051 * Enable interrupts.
1052 */
1053 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1054
1055 /*
1056 * Enable LED
1057 */
1058 rt2500pci_enable_led(rt2x00dev);
1059
1060 return 0;
1061}
1062
1063static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1064{
1065 u32 reg;
1066
1067 /*
1068 * Disable LED
1069 */
1070 rt2500pci_disable_led(rt2x00dev);
1071
1072 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1073
1074 /*
1075 * Disable synchronisation.
1076 */
1077 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1078
1079 /*
1080 * Cancel RX and TX.
1081 */
1082 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1083 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1084 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1085
1086 /*
1087 * Disable interrupts.
1088 */
1089 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1090}
1091
1092static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1093 enum dev_state state)
1094{
1095 u32 reg;
1096 unsigned int i;
1097 char put_to_sleep;
1098 char bbp_state;
1099 char rf_state;
1100
1101 put_to_sleep = (state != STATE_AWAKE);
1102
1103 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1104 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1105 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1106 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1107 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1108 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1109
1110 /*
1111 * Device is not guaranteed to be in the requested state yet.
1112 * We must wait until the register indicates that the
1113 * device has entered the correct state.
1114 */
1115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1116 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1117 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1118 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1119 if (bbp_state == state && rf_state == state)
1120 return 0;
1121 msleep(10);
1122 }
1123
1124 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1125 "current device state: bbp %d and rf %d.\n",
1126 state, bbp_state, rf_state);
1127
1128 return -EBUSY;
1129}
1130
1131static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1132 enum dev_state state)
1133{
1134 int retval = 0;
1135
1136 switch (state) {
1137 case STATE_RADIO_ON:
1138 retval = rt2500pci_enable_radio(rt2x00dev);
1139 break;
1140 case STATE_RADIO_OFF:
1141 rt2500pci_disable_radio(rt2x00dev);
1142 break;
1143 case STATE_RADIO_RX_ON:
1144 case STATE_RADIO_RX_OFF:
1145 rt2500pci_toggle_rx(rt2x00dev, state);
1146 break;
1147 case STATE_DEEP_SLEEP:
1148 case STATE_SLEEP:
1149 case STATE_STANDBY:
1150 case STATE_AWAKE:
1151 retval = rt2500pci_set_state(rt2x00dev, state);
1152 break;
1153 default:
1154 retval = -ENOTSUPP;
1155 break;
1156 }
1157
1158 return retval;
1159}
1160
1161/*
1162 * TX descriptor initialization
1163 */
1164static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
4bd7c452 1165 __le32 *txd,
4150c572 1166 struct txdata_entry_desc *desc,
95ea3627
ID		 1167 struct ieee80211_hdr *ieee80211hdr,
1168 unsigned int length,
1169 struct ieee80211_tx_control *control)
1170{
1171 u32 word;
1172
1173 /*
1174 * Start writing the descriptor words.
1175 */
1176 rt2x00_desc_read(txd, 2, &word);
1177 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1178 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1179 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1180 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1181 rt2x00_desc_write(txd, 2, word);
1182
1183 rt2x00_desc_read(txd, 3, &word);
1184 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1185 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1186 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1187 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1188 rt2x00_desc_write(txd, 3, word);
1189
1190 rt2x00_desc_read(txd, 10, &word);
1191 rt2x00_set_field32(&word, TXD_W10_RTS,
1192 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1193 rt2x00_desc_write(txd, 10, word);
1194
1195 rt2x00_desc_read(txd, 0, &word);
1196 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1197 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1198 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1199 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1200 rt2x00_set_field32(&word, TXD_W0_ACK,
2700f8b0 1201 test_bit(ENTRY_TXD_ACK, &desc->flags));
95ea3627
ID		 1202 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1203 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1204 rt2x00_set_field32(&word, TXD_W0_OFDM,
1205 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1206 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1207 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1208 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1209 !!(control->flags &
1210 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1211 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1212 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1213 rt2x00_desc_write(txd, 0, word);
1214}
1215
1216/*
1217 * TX data initialization
1218 */
1219static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1220 unsigned int queue)
1221{
1222 u32 reg;
1223
1224 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1225 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1226 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1227 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1228 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1229 }
1230 return;
1231 }
1232
1233 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1234 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1235 (queue == IEEE80211_TX_QUEUE_DATA0));
1236 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1237 (queue == IEEE80211_TX_QUEUE_DATA1));
1238 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1239 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
95ea3627
ID		 1240 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1241}
1242
1243/*
1244 * RX control handlers
1245 */
4150c572
JB		 1246static void rt2500pci_fill_rxdone(struct data_entry *entry,
1247 struct rxdata_entry_desc *desc)
95ea3627 1248{
4bd7c452 1249 __le32 *rxd = entry->priv;
95ea3627
ID		 1250 u32 word0;
1251 u32 word2;
1252
1253 rt2x00_desc_read(rxd, 0, &word0);
1254 rt2x00_desc_read(rxd, 2, &word2);
1255
4150c572
JB		 1256 desc->flags = 0;
1257 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1258 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1259 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1260 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1261
4150c572
JB		 1262 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1263 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1264 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1265 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1266 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1267}
1268
1269/*
1270 * Interrupt functions.
1271 */
1272static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1273{
1274 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1275 struct data_entry *entry;
4bd7c452 1276 __le32 *txd;
95ea3627
ID		 1277 u32 word;
1278 int tx_status;
1279 int retry;
1280
1281 while (!rt2x00_ring_empty(ring)) {
1282 entry = rt2x00_get_data_entry_done(ring);
1283 txd = entry->priv;
1284 rt2x00_desc_read(txd, 0, &word);
1285
1286 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1287 !rt2x00_get_field32(word, TXD_W0_VALID))
1288 break;
1289
1290 /*
1291 * Obtain the status about this packet.
1292 */
1293 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1294 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1295
3957ccb5 1296 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
95ea3627 1297 }
95ea3627
ID		 1298}
1299
1300static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1301{
1302 struct rt2x00_dev *rt2x00dev = dev_instance;
1303 u32 reg;
1304
1305 /*
1306 * Get the interrupt sources & saved to local variable.
1307 * Write register value back to clear pending interrupts.
1308 */
1309 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1310 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1311
1312 if (!reg)
1313 return IRQ_NONE;
1314
1315 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1316 return IRQ_HANDLED;
1317
1318 /*
1319 * Handle interrupts, walk through all bits
1320 * and run the tasks, the bits are checked in order of
1321 * priority.
1322 */
1323
1324 /*
1325 * 1 - Beacon timer expired interrupt.
1326 */
1327 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1328 rt2x00lib_beacondone(rt2x00dev);
1329
1330 /*
1331 * 2 - Rx ring done interrupt.
1332 */
1333 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1334 rt2x00pci_rxdone(rt2x00dev);
1335
1336 /*
1337 * 3 - Atim ring transmit done interrupt.
1338 */
1339 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1340 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1341
1342 /*
1343 * 4 - Priority ring transmit done interrupt.
1344 */
1345 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1346 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1347
1348 /*
1349 * 5 - Tx ring transmit done interrupt.
1350 */
1351 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1352 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1353
1354 return IRQ_HANDLED;
1355}
1356
1357/*
1358 * Device probe functions.
1359 */
1360static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1361{
1362 struct eeprom_93cx6 eeprom;
1363 u32 reg;
1364 u16 word;
1365 u8 *mac;
1366
1367 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1368
1369 eeprom.data = rt2x00dev;
1370 eeprom.register_read = rt2500pci_eepromregister_read;
1371 eeprom.register_write = rt2500pci_eepromregister_write;
1372 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1373 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1374 eeprom.reg_data_in = 0;
1375 eeprom.reg_data_out = 0;
1376 eeprom.reg_data_clock = 0;
1377 eeprom.reg_chip_select = 0;
1378
1379 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1380 EEPROM_SIZE / sizeof(u16));
1381
1382 /*
1383 * Start validation of the data that has been read.
1384 */
1385 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1386 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1387 DECLARE_MAC_BUF(macbuf);
1388
95ea3627 1389 random_ether_addr(mac);
0795af57
JP		 1390 EEPROM(rt2x00dev, "MAC: %s\n",
1391 print_mac(macbuf, mac));
95ea3627
ID		 1392 }
1393
1394 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1395 if (word == 0xffff) {
1396 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1397 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1398 ANTENNA_SW_DIVERSITY);
1399 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1400 ANTENNA_SW_DIVERSITY);
1401 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1402 LED_MODE_DEFAULT);
95ea3627
ID		 1403 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1404 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1405 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1406 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1407 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1408 }
1409
1410 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1411 if (word == 0xffff) {
1412 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1413 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1414 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1415 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1416 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1417 }
1418
1419 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1420 if (word == 0xffff) {
1421 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1422 DEFAULT_RSSI_OFFSET);
1423 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1424 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1425 }
1426
1427 return 0;
1428}
1429
1430static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1431{
1432 u32 reg;
1433 u16 value;
1434 u16 eeprom;
1435
1436 /*
1437 * Read EEPROM word for configuration.
1438 */
1439 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1440
1441 /*
1442 * Identify RF chipset.
1443 */
1444 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1445 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1446 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1447
1448 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1449 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1450 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1451 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1452 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1453 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1454 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1455 return -ENODEV;
1456 }
1457
1458 /*
1459 * Identify default antenna configuration.
1460 */
addc81bd 1461 rt2x00dev->default_ant.tx =
95ea3627 1462 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1463 rt2x00dev->default_ant.rx =
95ea3627
ID		 1464 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1465
1466 /*
1467 * Store led mode, for correct led behaviour.
1468 */
1469 rt2x00dev->led_mode =
1470 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1471
1472 /*
1473 * Detect if this device has an hardware controlled radio.
1474 */
81873e9c 1475#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1476 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1477 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1478#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1479
1480 /*
1481 * Check if the BBP tuning should be enabled.
1482 */
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1484
1485 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1486 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1487
1488 /*
1489 * Read the RSSI <-> dBm offset information.
1490 */
1491 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1492 rt2x00dev->rssi_offset =
1493 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1494
1495 return 0;
1496}
1497
1498/*
1499 * RF value list for RF2522
1500 * Supports: 2.4 GHz
1501 */
1502static const struct rf_channel rf_vals_bg_2522[] = {
1503 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1504 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1505 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1506 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1507 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1508 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1509 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1510 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1511 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1512 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1513 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1514 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1515 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1516 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1517};
1518
1519/*
1520 * RF value list for RF2523
1521 * Supports: 2.4 GHz
1522 */
1523static const struct rf_channel rf_vals_bg_2523[] = {
1524 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1525 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1526 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1527 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1528 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1529 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1530 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1531 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1532 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1533 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1534 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1535 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1536 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1537 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1538};
1539
1540/*
1541 * RF value list for RF2524
1542 * Supports: 2.4 GHz
1543 */
1544static const struct rf_channel rf_vals_bg_2524[] = {
1545 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1546 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1547 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1548 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1549 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1550 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1551 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1552 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1553 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1554 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1555 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1556 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1557 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1558 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1559};
1560
1561/*
1562 * RF value list for RF2525
1563 * Supports: 2.4 GHz
1564 */
1565static const struct rf_channel rf_vals_bg_2525[] = {
1566 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1567 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1568 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1569 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1570 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1571 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1572 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1573 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1574 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1575 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1576 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1577 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1578 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1579 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1580};
1581
1582/*
1583 * RF value list for RF2525e
1584 * Supports: 2.4 GHz
1585 */
1586static const struct rf_channel rf_vals_bg_2525e[] = {
1587 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1588 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1589 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1590 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1591 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1592 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1593 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1594 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1595 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1596 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1597 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1598 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1599 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1600 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1601};
1602
1603/*
1604 * RF value list for RF5222
1605 * Supports: 2.4 GHz & 5.2 GHz
1606 */
1607static const struct rf_channel rf_vals_5222[] = {
1608 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1609 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1610 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1611 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1612 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1613 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1614 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1615 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1616 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1617 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1618 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1619 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1620 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1621 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1622
1623 /* 802.11 UNI / HyperLan 2 */
1624 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1625 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1626 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1627 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1628 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1629 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1630 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1631 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1632
1633 /* 802.11 HyperLan 2 */
1634 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1635 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1636 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1637 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1638 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1639 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1640 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1641 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1642 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1643 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1644
1645 /* 802.11 UNII */
1646 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1647 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1648 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1649 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1650 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1651};
1652
1653static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1654{
1655 struct hw_mode_spec *spec = &rt2x00dev->spec;
1656 u8 *txpower;
1657 unsigned int i;
1658
1659 /*
1660 * Initialize all hw fields.
1661 */
4150c572 1662 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1663 rt2x00dev->hw->extra_tx_headroom = 0;
1664 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1665 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1666 rt2x00dev->hw->queues = 2;
1667
1668 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1669 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1670 rt2x00_eeprom_addr(rt2x00dev,
1671 EEPROM_MAC_ADDR_0));
1672
1673 /*
1674 * Convert tx_power array in eeprom.
1675 */
1676 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1677 for (i = 0; i < 14; i++)
1678 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1679
1680 /*
1681 * Initialize hw_mode information.
1682 */
1683 spec->num_modes = 2;
1684 spec->num_rates = 12;
1685 spec->tx_power_a = NULL;
1686 spec->tx_power_bg = txpower;
1687 spec->tx_power_default = DEFAULT_TXPOWER;
1688
1689 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1690 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1691 spec->channels = rf_vals_bg_2522;
1692 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1693 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1694 spec->channels = rf_vals_bg_2523;
1695 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1696 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1697 spec->channels = rf_vals_bg_2524;
1698 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1699 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1700 spec->channels = rf_vals_bg_2525;
1701 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1702 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1703 spec->channels = rf_vals_bg_2525e;
1704 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1705 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1706 spec->channels = rf_vals_5222;
1707 spec->num_modes = 3;
1708 }
1709}
1710
1711static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1712{
1713 int retval;
1714
1715 /*
1716 * Allocate eeprom data.
1717 */
1718 retval = rt2500pci_validate_eeprom(rt2x00dev);
1719 if (retval)
1720 return retval;
1721
1722 retval = rt2500pci_init_eeprom(rt2x00dev);
1723 if (retval)
1724 return retval;
1725
1726 /*
1727 * Initialize hw specifications.
1728 */
1729 rt2500pci_probe_hw_mode(rt2x00dev);
1730
1731 /*
1732 * This device requires the beacon ring
1733 */
066cb637 1734 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1735
1736 /*
1737 * Set the rssi offset.
1738 */
1739 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1740
1741 return 0;
1742}
1743
1744/*
1745 * IEEE80211 stack callback functions.
1746 */
4150c572
JB		 1747static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1748 unsigned int changed_flags,
1749 unsigned int *total_flags,
1750 int mc_count,
1751 struct dev_addr_list *mc_list)
1752{
1753 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1754 u32 reg;
1755
1756 /*
1757 * Mask off any flags we are going to ignore from
1758 * the total_flags field.
1759 */
1760 *total_flags &=
1761 FIF_ALLMULTI |
1762 FIF_FCSFAIL |
1763 FIF_PLCPFAIL |
1764 FIF_CONTROL |
1765 FIF_OTHER_BSS |
1766 FIF_PROMISC_IN_BSS;
1767
1768 /*
1769 * Apply some rules to the filters:
1770 * - Some filters imply different filters to be set.
1771 * - Some things we can't filter out at all.
4150c572
JB		 1772 */
1773 if (mc_count)
1774 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1775 if (*total_flags & FIF_OTHER_BSS ||
1776 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1777 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1778
1779 /*
1780 * Check if there is any work left for us.
1781 */
3c4f2085 1782 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1783 return;
3c4f2085 1784 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1785
1786 /*
1787 * Start configuration steps.
1788 * Note that the version error will always be dropped
1789 * and broadcast frames will always be accepted since
1790 * there is no filter for it at this time.
1791 */
1792 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1793 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1794 !(*total_flags & FIF_FCSFAIL));
1795 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1796 !(*total_flags & FIF_PLCPFAIL));
1797 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1798 !(*total_flags & FIF_CONTROL));
1799 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1800 !(*total_flags & FIF_PROMISC_IN_BSS));
1801 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1802 !(*total_flags & FIF_PROMISC_IN_BSS));
1803 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1804 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1805 !(*total_flags & FIF_ALLMULTI));
1806 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1807 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1808}
1809
95ea3627
ID		 1810static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1811 u32 short_retry, u32 long_retry)
1812{
1813 struct rt2x00_dev *rt2x00dev = hw->priv;
1814 u32 reg;
1815
1816 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1817 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1818 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1819 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1820
1821 return 0;
1822}
1823
1824static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1825{
1826 struct rt2x00_dev *rt2x00dev = hw->priv;
1827 u64 tsf;
1828 u32 reg;
1829
1830 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1831 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1832 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1833 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1834
1835 return tsf;
1836}
1837
1838static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1839{
1840 struct rt2x00_dev *rt2x00dev = hw->priv;
1841
1842 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1843 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1844}
1845
1846static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1847{
1848 struct rt2x00_dev *rt2x00dev = hw->priv;
1849 u32 reg;
1850
1851 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1852 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1853}
1854
1855static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1856 .tx = rt2x00mac_tx,
4150c572
JB		 1857 .start = rt2x00mac_start,
1858 .stop = rt2x00mac_stop,
95ea3627
ID		 1859 .add_interface = rt2x00mac_add_interface,
1860 .remove_interface = rt2x00mac_remove_interface,
1861 .config = rt2x00mac_config,
1862 .config_interface = rt2x00mac_config_interface,
4150c572 1863 .configure_filter = rt2500pci_configure_filter,
95ea3627
ID		 1864 .get_stats = rt2x00mac_get_stats,
1865 .set_retry_limit = rt2500pci_set_retry_limit,
5c58ee51 1866 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 1867 .conf_tx = rt2x00mac_conf_tx,
1868 .get_tx_stats = rt2x00mac_get_tx_stats,
1869 .get_tsf = rt2500pci_get_tsf,
1870 .reset_tsf = rt2500pci_reset_tsf,
1871 .beacon_update = rt2x00pci_beacon_update,
1872 .tx_last_beacon = rt2500pci_tx_last_beacon,
1873};
1874
1875static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1876 .irq_handler = rt2500pci_interrupt,
1877 .probe_hw = rt2500pci_probe_hw,
1878 .initialize = rt2x00pci_initialize,
1879 .uninitialize = rt2x00pci_uninitialize,
1880 .set_device_state = rt2500pci_set_device_state,
95ea3627 1881 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1882 .link_stats = rt2500pci_link_stats,
1883 .reset_tuner = rt2500pci_reset_tuner,
1884 .link_tuner = rt2500pci_link_tuner,
1885 .write_tx_desc = rt2500pci_write_tx_desc,
1886 .write_tx_data = rt2x00pci_write_tx_data,
1887 .kick_tx_queue = rt2500pci_kick_tx_queue,
1888 .fill_rxdone = rt2500pci_fill_rxdone,
1889 .config_mac_addr = rt2500pci_config_mac_addr,
1890 .config_bssid = rt2500pci_config_bssid,
95ea3627 1891 .config_type = rt2500pci_config_type,
5c58ee51 1892 .config_preamble = rt2500pci_config_preamble,
95ea3627
ID		 1893 .config = rt2500pci_config,
1894};
1895
1896static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1897 .name = KBUILD_MODNAME,
95ea3627
ID		 1898 .rxd_size = RXD_DESC_SIZE,
1899 .txd_size = TXD_DESC_SIZE,
1900 .eeprom_size = EEPROM_SIZE,
1901 .rf_size = RF_SIZE,
1902 .lib = &rt2500pci_rt2x00_ops,
1903 .hw = &rt2500pci_mac80211_ops,
1904#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1905 .debugfs = &rt2500pci_rt2x00debug,
1906#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1907};
1908
1909/*
1910 * RT2500pci module information.
1911 */
1912static struct pci_device_id rt2500pci_device_table[] = {
1913 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1914 { 0, }
1915};
1916
1917MODULE_AUTHOR(DRV_PROJECT);
1918MODULE_VERSION(DRV_VERSION);
1919MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1920MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1921MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1922MODULE_LICENSE("GPL");
1923
1924static struct pci_driver rt2500pci_driver = {
2360157c 1925 .name = KBUILD_MODNAME,
95ea3627
ID		 1926 .id_table = rt2500pci_device_table,
1927 .probe = rt2x00pci_probe,
1928 .remove = __devexit_p(rt2x00pci_remove),
1929 .suspend = rt2x00pci_suspend,
1930 .resume = rt2x00pci_resume,
1931};
1932
1933static int __init rt2500pci_init(void)
1934{
1935 return pci_register_driver(&rt2500pci_driver);
1936}
1937
1938static void __exit rt2500pci_exit(void)
1939{
1940 pci_unregister_driver(&rt2500pci_driver);
1941}
1942
1943module_init(rt2500pci_init);
1944module_exit(rt2500pci_exit);
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