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95ea3627 | 1 | /* |
4e54c711 | 2 | Copyright (C) 2004 - 2009 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2500pci | |
23 | Abstract: rt2500pci device specific routines. | |
24 | Supported chipsets: RT2560. | |
25 | */ | |
26 | ||
95ea3627 ID |
27 | #include <linux/delay.h> |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/eeprom_93cx6.h> | |
34 | ||
35 | #include "rt2x00.h" | |
36 | #include "rt2x00pci.h" | |
37 | #include "rt2500pci.h" | |
38 | ||
39 | /* | |
40 | * Register access. | |
41 | * All access to the CSR registers will go through the methods | |
42 | * rt2x00pci_register_read and rt2x00pci_register_write. | |
43 | * BBP and RF register require indirect register access, | |
44 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
45 | * These indirect registers work with busy bits, | |
46 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
47 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
48 | * between each attampt. When the busy bit is still set at that time, | |
49 | * the access attempt is considered to have failed, | |
50 | * and we will print an error. | |
51 | */ | |
c9c3b1a5 ID |
52 | #define WAIT_FOR_BBP(__dev, __reg) \ |
53 | rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) | |
54 | #define WAIT_FOR_RF(__dev, __reg) \ | |
55 | rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) | |
95ea3627 | 56 | |
0e14f6d3 | 57 | static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
58 | const unsigned int word, const u8 value) |
59 | { | |
60 | u32 reg; | |
61 | ||
8ff48a8b ID |
62 | mutex_lock(&rt2x00dev->csr_mutex); |
63 | ||
95ea3627 | 64 | /* |
c9c3b1a5 ID |
65 | * Wait until the BBP becomes available, afterwards we |
66 | * can safely write the new data into the register. | |
95ea3627 | 67 | */ |
c9c3b1a5 ID |
68 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
69 | reg = 0; | |
70 | rt2x00_set_field32(®, BBPCSR_VALUE, value); | |
71 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
72 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
73 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); | |
74 | ||
75 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); | |
76 | } | |
8ff48a8b | 77 | |
8ff48a8b | 78 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
79 | } |
80 | ||
0e14f6d3 | 81 | static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
82 | const unsigned int word, u8 *value) |
83 | { | |
84 | u32 reg; | |
85 | ||
8ff48a8b ID |
86 | mutex_lock(&rt2x00dev->csr_mutex); |
87 | ||
95ea3627 | 88 | /* |
c9c3b1a5 ID |
89 | * Wait until the BBP becomes available, afterwards we |
90 | * can safely write the read request into the register. | |
91 | * After the data has been written, we wait until hardware | |
92 | * returns the correct value, if at any time the register | |
93 | * doesn't become available in time, reg will be 0xffffffff | |
94 | * which means we return 0xff to the caller. | |
95ea3627 | 95 | */ |
c9c3b1a5 ID |
96 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
97 | reg = 0; | |
98 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); | |
99 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); | |
100 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); | |
95ea3627 | 101 | |
c9c3b1a5 | 102 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
95ea3627 | 103 | |
c9c3b1a5 ID |
104 | WAIT_FOR_BBP(rt2x00dev, ®); |
105 | } | |
95ea3627 ID |
106 | |
107 | *value = rt2x00_get_field32(reg, BBPCSR_VALUE); | |
8ff48a8b ID |
108 | |
109 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
110 | } |
111 | ||
0e14f6d3 | 112 | static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
113 | const unsigned int word, const u32 value) |
114 | { | |
115 | u32 reg; | |
95ea3627 ID |
116 | |
117 | if (!word) | |
118 | return; | |
119 | ||
8ff48a8b ID |
120 | mutex_lock(&rt2x00dev->csr_mutex); |
121 | ||
c9c3b1a5 ID |
122 | /* |
123 | * Wait until the RF becomes available, afterwards we | |
124 | * can safely write the new data into the register. | |
125 | */ | |
126 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
127 | reg = 0; | |
128 | rt2x00_set_field32(®, RFCSR_VALUE, value); | |
129 | rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); | |
130 | rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); | |
131 | rt2x00_set_field32(®, RFCSR_BUSY, 1); | |
132 | ||
133 | rt2x00pci_register_write(rt2x00dev, RFCSR, reg); | |
134 | rt2x00_rf_write(rt2x00dev, word, value); | |
95ea3627 ID |
135 | } |
136 | ||
8ff48a8b | 137 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
138 | } |
139 | ||
140 | static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) | |
141 | { | |
142 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
143 | u32 reg; | |
144 | ||
145 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); | |
146 | ||
147 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); | |
148 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); | |
149 | eeprom->reg_data_clock = | |
150 | !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); | |
151 | eeprom->reg_chip_select = | |
152 | !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); | |
153 | } | |
154 | ||
155 | static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
156 | { | |
157 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
158 | u32 reg = 0; | |
159 | ||
160 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); | |
161 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); | |
162 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, | |
163 | !!eeprom->reg_data_clock); | |
164 | rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, | |
165 | !!eeprom->reg_chip_select); | |
166 | ||
167 | rt2x00pci_register_write(rt2x00dev, CSR21, reg); | |
168 | } | |
169 | ||
170 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
171 | static const struct rt2x00debug rt2500pci_rt2x00debug = { |
172 | .owner = THIS_MODULE, | |
173 | .csr = { | |
743b97ca ID |
174 | .read = rt2x00pci_register_read, |
175 | .write = rt2x00pci_register_write, | |
176 | .flags = RT2X00DEBUGFS_OFFSET, | |
177 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
178 | .word_size = sizeof(u32), |
179 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
180 | }, | |
181 | .eeprom = { | |
182 | .read = rt2x00_eeprom_read, | |
183 | .write = rt2x00_eeprom_write, | |
743b97ca | 184 | .word_base = EEPROM_BASE, |
95ea3627 ID |
185 | .word_size = sizeof(u16), |
186 | .word_count = EEPROM_SIZE / sizeof(u16), | |
187 | }, | |
188 | .bbp = { | |
189 | .read = rt2500pci_bbp_read, | |
190 | .write = rt2500pci_bbp_write, | |
743b97ca | 191 | .word_base = BBP_BASE, |
95ea3627 ID |
192 | .word_size = sizeof(u8), |
193 | .word_count = BBP_SIZE / sizeof(u8), | |
194 | }, | |
195 | .rf = { | |
196 | .read = rt2x00_rf_read, | |
197 | .write = rt2500pci_rf_write, | |
743b97ca | 198 | .word_base = RF_BASE, |
95ea3627 ID |
199 | .word_size = sizeof(u32), |
200 | .word_count = RF_SIZE / sizeof(u32), | |
201 | }, | |
202 | }; | |
203 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
204 | ||
58169529 | 205 | #ifdef CONFIG_RT2X00_LIB_RFKILL |
95ea3627 ID |
206 | static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
207 | { | |
208 | u32 reg; | |
209 | ||
210 | rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); | |
211 | return rt2x00_get_field32(reg, GPIOCSR_BIT0); | |
212 | } | |
81873e9c ID |
213 | #else |
214 | #define rt2500pci_rfkill_poll NULL | |
58169529 | 215 | #endif /* CONFIG_RT2X00_LIB_RFKILL */ |
95ea3627 | 216 | |
771fd565 | 217 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 218 | static void rt2500pci_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
219 | enum led_brightness brightness) |
220 | { | |
221 | struct rt2x00_led *led = | |
222 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
223 | unsigned int enabled = brightness != LED_OFF; | |
a9450b70 ID |
224 | u32 reg; |
225 | ||
226 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); | |
227 | ||
a2e1d52a | 228 | if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) |
a9450b70 | 229 | rt2x00_set_field32(®, LEDCSR_LINK, enabled); |
a2e1d52a ID |
230 | else if (led->type == LED_TYPE_ACTIVITY) |
231 | rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); | |
a9450b70 ID |
232 | |
233 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); | |
234 | } | |
a2e1d52a ID |
235 | |
236 | static int rt2500pci_blink_set(struct led_classdev *led_cdev, | |
237 | unsigned long *delay_on, | |
238 | unsigned long *delay_off) | |
239 | { | |
240 | struct rt2x00_led *led = | |
241 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
242 | u32 reg; | |
243 | ||
244 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); | |
245 | rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); | |
246 | rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); | |
247 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); | |
248 | ||
249 | return 0; | |
250 | } | |
475433be ID |
251 | |
252 | static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, | |
253 | struct rt2x00_led *led, | |
254 | enum led_type type) | |
255 | { | |
256 | led->rt2x00dev = rt2x00dev; | |
257 | led->type = type; | |
258 | led->led_dev.brightness_set = rt2500pci_brightness_set; | |
259 | led->led_dev.blink_set = rt2500pci_blink_set; | |
260 | led->flags = LED_INITIALIZED; | |
261 | } | |
771fd565 | 262 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 263 | |
95ea3627 ID |
264 | /* |
265 | * Configuration handlers. | |
266 | */ | |
3a643d24 ID |
267 | static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, |
268 | const unsigned int filter_flags) | |
269 | { | |
270 | u32 reg; | |
271 | ||
272 | /* | |
273 | * Start configuration steps. | |
274 | * Note that the version error will always be dropped | |
275 | * and broadcast frames will always be accepted since | |
276 | * there is no filter for it at this time. | |
277 | */ | |
278 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | |
279 | rt2x00_set_field32(®, RXCSR0_DROP_CRC, | |
280 | !(filter_flags & FIF_FCSFAIL)); | |
281 | rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, | |
282 | !(filter_flags & FIF_PLCPFAIL)); | |
283 | rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, | |
284 | !(filter_flags & FIF_CONTROL)); | |
285 | rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, | |
286 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
287 | rt2x00_set_field32(®, RXCSR0_DROP_TODS, | |
e0b005fa ID |
288 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
289 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
290 | rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); |
291 | rt2x00_set_field32(®, RXCSR0_DROP_MCAST, | |
292 | !(filter_flags & FIF_ALLMULTI)); | |
293 | rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); | |
294 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | |
295 | } | |
296 | ||
6bb40dd1 ID |
297 | static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, |
298 | struct rt2x00_intf *intf, | |
299 | struct rt2x00intf_conf *conf, | |
300 | const unsigned int flags) | |
95ea3627 | 301 | { |
e58c6aca | 302 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); |
6bb40dd1 | 303 | unsigned int bcn_preload; |
95ea3627 ID |
304 | u32 reg; |
305 | ||
6bb40dd1 | 306 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
307 | /* |
308 | * Enable beacon config | |
309 | */ | |
bad13639 | 310 | bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); |
6bb40dd1 ID |
311 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); |
312 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); | |
313 | rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); | |
314 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); | |
95ea3627 | 315 | |
6bb40dd1 ID |
316 | /* |
317 | * Enable synchronisation. | |
318 | */ | |
319 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | |
fd3c91c5 | 320 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
6bb40dd1 | 321 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
fd3c91c5 | 322 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
6bb40dd1 ID |
323 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
324 | } | |
325 | ||
326 | if (flags & CONFIG_UPDATE_MAC) | |
327 | rt2x00pci_register_multiwrite(rt2x00dev, CSR3, | |
328 | conf->mac, sizeof(conf->mac)); | |
329 | ||
330 | if (flags & CONFIG_UPDATE_BSSID) | |
331 | rt2x00pci_register_multiwrite(rt2x00dev, CSR5, | |
332 | conf->bssid, sizeof(conf->bssid)); | |
95ea3627 ID |
333 | } |
334 | ||
3a643d24 ID |
335 | static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, |
336 | struct rt2x00lib_erp *erp) | |
95ea3627 | 337 | { |
5c58ee51 | 338 | int preamble_mask; |
95ea3627 | 339 | u32 reg; |
95ea3627 | 340 | |
5c58ee51 ID |
341 | /* |
342 | * When short preamble is enabled, we should set bit 0x08 | |
343 | */ | |
72810379 | 344 | preamble_mask = erp->short_preamble << 3; |
95ea3627 ID |
345 | |
346 | rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); | |
72810379 ID |
347 | rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, |
348 | erp->ack_timeout); | |
349 | rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, | |
350 | erp->ack_consume_time); | |
95ea3627 ID |
351 | rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); |
352 | ||
95ea3627 | 353 | rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); |
44a9809b | 354 | rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); |
95ea3627 | 355 | rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); |
bad13639 | 356 | rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); |
95ea3627 ID |
357 | rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); |
358 | ||
359 | rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); | |
5c58ee51 | 360 | rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); |
95ea3627 | 361 | rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); |
bad13639 | 362 | rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); |
95ea3627 ID |
363 | rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); |
364 | ||
365 | rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); | |
5c58ee51 | 366 | rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); |
95ea3627 | 367 | rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); |
bad13639 | 368 | rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); |
95ea3627 ID |
369 | rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); |
370 | ||
371 | rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); | |
5c58ee51 | 372 | rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); |
95ea3627 | 373 | rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); |
bad13639 | 374 | rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); |
95ea3627 | 375 | rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); |
e4ea1c40 ID |
376 | |
377 | rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); | |
378 | ||
379 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); | |
380 | rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); | |
381 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
382 | ||
383 | rt2x00pci_register_read(rt2x00dev, CSR18, ®); | |
384 | rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); | |
385 | rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); | |
386 | rt2x00pci_register_write(rt2x00dev, CSR18, reg); | |
387 | ||
388 | rt2x00pci_register_read(rt2x00dev, CSR19, ®); | |
389 | rt2x00_set_field32(®, CSR19_DIFS, erp->difs); | |
390 | rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); | |
391 | rt2x00pci_register_write(rt2x00dev, CSR19, reg); | |
95ea3627 ID |
392 | } |
393 | ||
e4ea1c40 ID |
394 | static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, |
395 | struct antenna_setup *ant) | |
95ea3627 | 396 | { |
e4ea1c40 ID |
397 | u32 reg; |
398 | u8 r14; | |
399 | u8 r2; | |
400 | ||
401 | /* | |
402 | * We should never come here because rt2x00lib is supposed | |
403 | * to catch this and send us the correct antenna explicitely. | |
404 | */ | |
405 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
406 | ant->tx == ANTENNA_SW_DIVERSITY); | |
407 | ||
408 | rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®); | |
409 | rt2500pci_bbp_read(rt2x00dev, 14, &r14); | |
410 | rt2500pci_bbp_read(rt2x00dev, 2, &r2); | |
411 | ||
412 | /* | |
413 | * Configure the TX antenna. | |
414 | */ | |
415 | switch (ant->tx) { | |
416 | case ANTENNA_A: | |
417 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); | |
418 | rt2x00_set_field32(®, BBPCSR1_CCK, 0); | |
419 | rt2x00_set_field32(®, BBPCSR1_OFDM, 0); | |
420 | break; | |
421 | case ANTENNA_B: | |
422 | default: | |
423 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2); | |
424 | rt2x00_set_field32(®, BBPCSR1_CCK, 2); | |
425 | rt2x00_set_field32(®, BBPCSR1_OFDM, 2); | |
426 | break; | |
427 | } | |
428 | ||
429 | /* | |
430 | * Configure the RX antenna. | |
431 | */ | |
432 | switch (ant->rx) { | |
433 | case ANTENNA_A: | |
434 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); | |
435 | break; | |
436 | case ANTENNA_B: | |
437 | default: | |
438 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2); | |
439 | break; | |
440 | } | |
441 | ||
442 | /* | |
443 | * RT2525E and RT5222 need to flip TX I/Q | |
444 | */ | |
445 | if (rt2x00_rf(&rt2x00dev->chip, RF2525E) || | |
446 | rt2x00_rf(&rt2x00dev->chip, RF5222)) { | |
447 | rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); | |
448 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); | |
449 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); | |
450 | ||
451 | /* | |
452 | * RT2525E does not need RX I/Q Flip. | |
453 | */ | |
454 | if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) | |
455 | rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); | |
456 | } else { | |
457 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); | |
458 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); | |
459 | } | |
460 | ||
461 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg); | |
462 | rt2500pci_bbp_write(rt2x00dev, 14, r14); | |
463 | rt2500pci_bbp_write(rt2x00dev, 2, r2); | |
95ea3627 ID |
464 | } |
465 | ||
466 | static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 467 | struct rf_channel *rf, const int txpower) |
95ea3627 | 468 | { |
95ea3627 ID |
469 | u8 r70; |
470 | ||
95ea3627 ID |
471 | /* |
472 | * Set TXpower. | |
473 | */ | |
5c58ee51 | 474 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
95ea3627 ID |
475 | |
476 | /* | |
477 | * Switch on tuning bits. | |
478 | * For RT2523 devices we do not need to update the R1 register. | |
479 | */ | |
480 | if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) | |
5c58ee51 ID |
481 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); |
482 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); | |
95ea3627 ID |
483 | |
484 | /* | |
485 | * For RT2525 we should first set the channel to half band higher. | |
486 | */ | |
487 | if (rt2x00_rf(&rt2x00dev->chip, RF2525)) { | |
488 | static const u32 vals[] = { | |
489 | 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, | |
490 | 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, | |
491 | 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, | |
492 | 0x00080d2e, 0x00080d3a | |
493 | }; | |
494 | ||
5c58ee51 ID |
495 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
496 | rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); | |
497 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
498 | if (rf->rf4) | |
499 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); | |
95ea3627 ID |
500 | } |
501 | ||
5c58ee51 ID |
502 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
503 | rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); | |
504 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
505 | if (rf->rf4) | |
506 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); | |
95ea3627 ID |
507 | |
508 | /* | |
509 | * Channel 14 requires the Japan filter bit to be set. | |
510 | */ | |
511 | r70 = 0x46; | |
5c58ee51 | 512 | rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14); |
95ea3627 ID |
513 | rt2500pci_bbp_write(rt2x00dev, 70, r70); |
514 | ||
515 | msleep(1); | |
516 | ||
517 | /* | |
518 | * Switch off tuning bits. | |
519 | * For RT2523 devices we do not need to update the R1 register. | |
520 | */ | |
521 | if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) { | |
5c58ee51 ID |
522 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); |
523 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); | |
95ea3627 ID |
524 | } |
525 | ||
5c58ee51 ID |
526 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); |
527 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); | |
95ea3627 ID |
528 | |
529 | /* | |
530 | * Clear false CRC during channel switch. | |
531 | */ | |
5c58ee51 | 532 | rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); |
95ea3627 ID |
533 | } |
534 | ||
535 | static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, | |
536 | const int txpower) | |
537 | { | |
538 | u32 rf3; | |
539 | ||
540 | rt2x00_rf_read(rt2x00dev, 3, &rf3); | |
541 | rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
542 | rt2500pci_rf_write(rt2x00dev, 3, rf3); | |
543 | } | |
544 | ||
e4ea1c40 ID |
545 | static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
546 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
547 | { |
548 | u32 reg; | |
95ea3627 | 549 | |
e4ea1c40 ID |
550 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
551 | rt2x00_set_field32(®, CSR11_LONG_RETRY, | |
552 | libconf->conf->long_frame_max_tx_count); | |
553 | rt2x00_set_field32(®, CSR11_SHORT_RETRY, | |
554 | libconf->conf->short_frame_max_tx_count); | |
555 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
95ea3627 ID |
556 | } |
557 | ||
558 | static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 559 | struct rt2x00lib_conf *libconf) |
95ea3627 ID |
560 | { |
561 | u32 reg; | |
562 | ||
95ea3627 ID |
563 | rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); |
564 | rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); | |
565 | rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); | |
566 | rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); | |
567 | ||
568 | rt2x00pci_register_read(rt2x00dev, CSR12, ®); | |
5c58ee51 ID |
569 | rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, |
570 | libconf->conf->beacon_int * 16); | |
571 | rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, | |
572 | libconf->conf->beacon_int * 16); | |
95ea3627 ID |
573 | rt2x00pci_register_write(rt2x00dev, CSR12, reg); |
574 | } | |
575 | ||
7d7f19cc ID |
576 | static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, |
577 | struct rt2x00lib_conf *libconf) | |
578 | { | |
579 | enum dev_state state = | |
580 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
581 | STATE_SLEEP : STATE_AWAKE; | |
582 | u32 reg; | |
583 | ||
584 | if (state == STATE_SLEEP) { | |
585 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); | |
586 | rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, | |
587 | (libconf->conf->beacon_int - 20) * 16); | |
588 | rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, | |
589 | libconf->conf->listen_interval - 1); | |
590 | ||
591 | /* We must first disable autowake before it can be enabled */ | |
592 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); | |
593 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); | |
594 | ||
595 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); | |
596 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); | |
597 | } | |
598 | ||
599 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
600 | } | |
601 | ||
95ea3627 | 602 | static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
603 | struct rt2x00lib_conf *libconf, |
604 | const unsigned int flags) | |
95ea3627 | 605 | { |
e4ea1c40 | 606 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
607 | rt2500pci_config_channel(rt2x00dev, &libconf->rf, |
608 | libconf->conf->power_level); | |
e4ea1c40 ID |
609 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
610 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 ID |
611 | rt2500pci_config_txpower(rt2x00dev, |
612 | libconf->conf->power_level); | |
e4ea1c40 ID |
613 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
614 | rt2500pci_config_retry_limit(rt2x00dev, libconf); | |
615 | if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL) | |
5c58ee51 | 616 | rt2500pci_config_duration(rt2x00dev, libconf); |
7d7f19cc ID |
617 | if (flags & IEEE80211_CONF_CHANGE_PS) |
618 | rt2500pci_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
619 | } |
620 | ||
95ea3627 ID |
621 | /* |
622 | * Link tuning | |
623 | */ | |
ebcf26da ID |
624 | static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, |
625 | struct link_qual *qual) | |
95ea3627 ID |
626 | { |
627 | u32 reg; | |
628 | ||
629 | /* | |
630 | * Update FCS error count from register. | |
631 | */ | |
632 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); | |
ebcf26da | 633 | qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); |
95ea3627 ID |
634 | |
635 | /* | |
636 | * Update False CCA count from register. | |
637 | */ | |
638 | rt2x00pci_register_read(rt2x00dev, CNT3, ®); | |
ebcf26da | 639 | qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); |
95ea3627 ID |
640 | } |
641 | ||
5352ff65 ID |
642 | static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
643 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 644 | { |
5352ff65 | 645 | if (qual->vgc_level_reg != vgc_level) { |
eb20b4e8 | 646 | rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); |
5352ff65 | 647 | qual->vgc_level_reg = vgc_level; |
eb20b4e8 ID |
648 | } |
649 | } | |
650 | ||
5352ff65 ID |
651 | static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
652 | struct link_qual *qual) | |
95ea3627 | 653 | { |
5352ff65 | 654 | rt2500pci_set_vgc(rt2x00dev, qual, 0x48); |
95ea3627 ID |
655 | } |
656 | ||
5352ff65 ID |
657 | static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
658 | struct link_qual *qual, const u32 count) | |
95ea3627 | 659 | { |
95ea3627 ID |
660 | /* |
661 | * To prevent collisions with MAC ASIC on chipsets | |
662 | * up to version C the link tuning should halt after 20 | |
6bb40dd1 | 663 | * seconds while being associated. |
95ea3627 | 664 | */ |
755a957d | 665 | if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D && |
5352ff65 | 666 | rt2x00dev->intf_associated && count > 20) |
95ea3627 ID |
667 | return; |
668 | ||
95ea3627 ID |
669 | /* |
670 | * Chipset versions C and lower should directly continue | |
6bb40dd1 ID |
671 | * to the dynamic CCA tuning. Chipset version D and higher |
672 | * should go straight to dynamic CCA tuning when they | |
673 | * are not associated. | |
95ea3627 | 674 | */ |
6bb40dd1 ID |
675 | if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D || |
676 | !rt2x00dev->intf_associated) | |
95ea3627 ID |
677 | goto dynamic_cca_tune; |
678 | ||
679 | /* | |
680 | * A too low RSSI will cause too much false CCA which will | |
681 | * then corrupt the R17 tuning. To remidy this the tuning should | |
682 | * be stopped (While making sure the R17 value will not exceed limits) | |
683 | */ | |
5352ff65 ID |
684 | if (qual->rssi < -80 && count > 20) { |
685 | if (qual->vgc_level_reg >= 0x41) | |
686 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); | |
95ea3627 ID |
687 | return; |
688 | } | |
689 | ||
690 | /* | |
691 | * Special big-R17 for short distance | |
692 | */ | |
5352ff65 ID |
693 | if (qual->rssi >= -58) { |
694 | rt2500pci_set_vgc(rt2x00dev, qual, 0x50); | |
95ea3627 ID |
695 | return; |
696 | } | |
697 | ||
698 | /* | |
699 | * Special mid-R17 for middle distance | |
700 | */ | |
5352ff65 ID |
701 | if (qual->rssi >= -74) { |
702 | rt2500pci_set_vgc(rt2x00dev, qual, 0x41); | |
95ea3627 ID |
703 | return; |
704 | } | |
705 | ||
706 | /* | |
707 | * Leave short or middle distance condition, restore r17 | |
708 | * to the dynamic tuning range. | |
709 | */ | |
5352ff65 ID |
710 | if (qual->vgc_level_reg >= 0x41) { |
711 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); | |
95ea3627 ID |
712 | return; |
713 | } | |
714 | ||
715 | dynamic_cca_tune: | |
716 | ||
717 | /* | |
718 | * R17 is inside the dynamic tuning range, | |
719 | * start tuning the link based on the false cca counter. | |
720 | */ | |
5352ff65 ID |
721 | if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) { |
722 | rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); | |
723 | qual->vgc_level = qual->vgc_level_reg; | |
724 | } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) { | |
725 | rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); | |
726 | qual->vgc_level = qual->vgc_level_reg; | |
95ea3627 ID |
727 | } |
728 | } | |
729 | ||
730 | /* | |
731 | * Initialization functions. | |
732 | */ | |
798b7adb | 733 | static bool rt2500pci_get_entry_state(struct queue_entry *entry) |
95ea3627 | 734 | { |
b8be63ff | 735 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
736 | u32 word; |
737 | ||
798b7adb ID |
738 | if (entry->queue->qid == QID_RX) { |
739 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
740 | ||
741 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); | |
742 | } else { | |
743 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 | 744 | |
798b7adb ID |
745 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
746 | rt2x00_get_field32(word, TXD_W0_VALID)); | |
747 | } | |
95ea3627 ID |
748 | } |
749 | ||
798b7adb | 750 | static void rt2500pci_clear_entry(struct queue_entry *entry) |
95ea3627 | 751 | { |
b8be63ff | 752 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
798b7adb | 753 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
95ea3627 ID |
754 | u32 word; |
755 | ||
798b7adb ID |
756 | if (entry->queue->qid == QID_RX) { |
757 | rt2x00_desc_read(entry_priv->desc, 1, &word); | |
758 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | |
759 | rt2x00_desc_write(entry_priv->desc, 1, word); | |
760 | ||
761 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
762 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | |
763 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
764 | } else { | |
765 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
766 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | |
767 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | |
768 | rt2x00_desc_write(entry_priv->desc, 0, word); | |
769 | } | |
95ea3627 ID |
770 | } |
771 | ||
181d6902 | 772 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) |
95ea3627 | 773 | { |
b8be63ff | 774 | struct queue_entry_priv_pci *entry_priv; |
95ea3627 ID |
775 | u32 reg; |
776 | ||
95ea3627 ID |
777 | /* |
778 | * Initialize registers. | |
779 | */ | |
780 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); | |
181d6902 ID |
781 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
782 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); | |
783 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); | |
784 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); | |
95ea3627 ID |
785 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
786 | ||
b8be63ff | 787 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
95ea3627 | 788 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
30b3a23c | 789 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
b8be63ff | 790 | entry_priv->desc_dma); |
95ea3627 ID |
791 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
792 | ||
b8be63ff | 793 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
95ea3627 | 794 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
30b3a23c | 795 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
b8be63ff | 796 | entry_priv->desc_dma); |
95ea3627 ID |
797 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
798 | ||
b8be63ff | 799 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; |
95ea3627 | 800 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
30b3a23c | 801 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
b8be63ff | 802 | entry_priv->desc_dma); |
95ea3627 ID |
803 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
804 | ||
b8be63ff | 805 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; |
95ea3627 | 806 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
30b3a23c | 807 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
b8be63ff | 808 | entry_priv->desc_dma); |
95ea3627 ID |
809 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
810 | ||
811 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); | |
812 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); | |
181d6902 | 813 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
95ea3627 ID |
814 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
815 | ||
b8be63ff | 816 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
95ea3627 | 817 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
b8be63ff ID |
818 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
819 | entry_priv->desc_dma); | |
95ea3627 ID |
820 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) | |
826 | { | |
827 | u32 reg; | |
828 | ||
829 | rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); | |
830 | rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); | |
831 | rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002); | |
832 | rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); | |
833 | ||
834 | rt2x00pci_register_read(rt2x00dev, TIMECSR, ®); | |
835 | rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); | |
836 | rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); | |
837 | rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); | |
838 | rt2x00pci_register_write(rt2x00dev, TIMECSR, reg); | |
839 | ||
840 | rt2x00pci_register_read(rt2x00dev, CSR9, ®); | |
841 | rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, | |
842 | rt2x00dev->rx->data_size / 128); | |
843 | rt2x00pci_register_write(rt2x00dev, CSR9, reg); | |
844 | ||
845 | /* | |
846 | * Always use CWmin and CWmax set in descriptor. | |
847 | */ | |
848 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); | |
849 | rt2x00_set_field32(®, CSR11_CW_SELECT, 0); | |
850 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); | |
851 | ||
1f909162 ID |
852 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
853 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | |
854 | rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); | |
855 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
856 | rt2x00_set_field32(®, CSR14_TCFP, 0); | |
857 | rt2x00_set_field32(®, CSR14_TATIMW, 0); | |
858 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
859 | rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); | |
860 | rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); | |
861 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
862 | ||
95ea3627 ID |
863 | rt2x00pci_register_write(rt2x00dev, CNT3, 0); |
864 | ||
865 | rt2x00pci_register_read(rt2x00dev, TXCSR8, ®); | |
866 | rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); | |
867 | rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); | |
868 | rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); | |
869 | rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); | |
870 | rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); | |
871 | rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); | |
872 | rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); | |
873 | rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); | |
874 | rt2x00pci_register_write(rt2x00dev, TXCSR8, reg); | |
875 | ||
876 | rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®); | |
877 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); | |
878 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); | |
879 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); | |
880 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); | |
881 | rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg); | |
882 | ||
883 | rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®); | |
884 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); | |
885 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); | |
886 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); | |
887 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); | |
888 | rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg); | |
889 | ||
890 | rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®); | |
891 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); | |
892 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); | |
893 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); | |
894 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); | |
895 | rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg); | |
896 | ||
897 | rt2x00pci_register_read(rt2x00dev, RXCSR3, ®); | |
898 | rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ | |
899 | rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); | |
900 | rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ | |
901 | rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); | |
902 | rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ | |
903 | rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); | |
904 | rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ | |
905 | rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); | |
906 | rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); | |
907 | ||
908 | rt2x00pci_register_read(rt2x00dev, PCICSR, ®); | |
909 | rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); | |
910 | rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); | |
911 | rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); | |
912 | rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); | |
913 | rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); | |
914 | rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); | |
915 | rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); | |
916 | rt2x00pci_register_write(rt2x00dev, PCICSR, reg); | |
917 | ||
918 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); | |
919 | ||
920 | rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); | |
921 | rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0); | |
922 | ||
923 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
924 | return -EBUSY; | |
925 | ||
926 | rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223); | |
927 | rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); | |
928 | ||
929 | rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); | |
930 | rt2x00_set_field32(®, MACCSR2_DELAY, 64); | |
931 | rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); | |
932 | ||
933 | rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®); | |
934 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); | |
935 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); | |
936 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); | |
937 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); | |
938 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); | |
939 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); | |
940 | rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg); | |
941 | ||
942 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200); | |
943 | ||
944 | rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020); | |
945 | ||
946 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); | |
947 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); | |
948 | rt2x00_set_field32(®, CSR1_BBP_RESET, 0); | |
949 | rt2x00_set_field32(®, CSR1_HOST_READY, 0); | |
950 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); | |
951 | ||
952 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); | |
953 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); | |
954 | rt2x00_set_field32(®, CSR1_HOST_READY, 1); | |
955 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); | |
956 | ||
957 | /* | |
958 | * We must clear the FCS and FIFO error count. | |
959 | * These registers are cleared on read, | |
960 | * so we may pass a useless variable to store the value. | |
961 | */ | |
962 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); | |
963 | rt2x00pci_register_read(rt2x00dev, CNT4, ®); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
2b08da3f | 968 | static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
969 | { |
970 | unsigned int i; | |
95ea3627 ID |
971 | u8 value; |
972 | ||
973 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
974 | rt2500pci_bbp_read(rt2x00dev, 0, &value); | |
975 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 976 | return 0; |
95ea3627 ID |
977 | udelay(REGISTER_BUSY_DELAY); |
978 | } | |
979 | ||
980 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
981 | return -EACCES; | |
2b08da3f ID |
982 | } |
983 | ||
984 | static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |
985 | { | |
986 | unsigned int i; | |
987 | u16 eeprom; | |
988 | u8 reg_id; | |
989 | u8 value; | |
990 | ||
991 | if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) | |
992 | return -EACCES; | |
95ea3627 | 993 | |
95ea3627 ID |
994 | rt2500pci_bbp_write(rt2x00dev, 3, 0x02); |
995 | rt2500pci_bbp_write(rt2x00dev, 4, 0x19); | |
996 | rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); | |
997 | rt2500pci_bbp_write(rt2x00dev, 15, 0x30); | |
998 | rt2500pci_bbp_write(rt2x00dev, 16, 0xac); | |
999 | rt2500pci_bbp_write(rt2x00dev, 18, 0x18); | |
1000 | rt2500pci_bbp_write(rt2x00dev, 19, 0xff); | |
1001 | rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); | |
1002 | rt2500pci_bbp_write(rt2x00dev, 21, 0x08); | |
1003 | rt2500pci_bbp_write(rt2x00dev, 22, 0x08); | |
1004 | rt2500pci_bbp_write(rt2x00dev, 23, 0x08); | |
1005 | rt2500pci_bbp_write(rt2x00dev, 24, 0x70); | |
1006 | rt2500pci_bbp_write(rt2x00dev, 25, 0x40); | |
1007 | rt2500pci_bbp_write(rt2x00dev, 26, 0x08); | |
1008 | rt2500pci_bbp_write(rt2x00dev, 27, 0x23); | |
1009 | rt2500pci_bbp_write(rt2x00dev, 30, 0x10); | |
1010 | rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); | |
1011 | rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); | |
1012 | rt2500pci_bbp_write(rt2x00dev, 34, 0x12); | |
1013 | rt2500pci_bbp_write(rt2x00dev, 35, 0x50); | |
1014 | rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); | |
1015 | rt2500pci_bbp_write(rt2x00dev, 40, 0x02); | |
1016 | rt2500pci_bbp_write(rt2x00dev, 41, 0x60); | |
1017 | rt2500pci_bbp_write(rt2x00dev, 53, 0x10); | |
1018 | rt2500pci_bbp_write(rt2x00dev, 54, 0x18); | |
1019 | rt2500pci_bbp_write(rt2x00dev, 56, 0x08); | |
1020 | rt2500pci_bbp_write(rt2x00dev, 57, 0x10); | |
1021 | rt2500pci_bbp_write(rt2x00dev, 58, 0x08); | |
1022 | rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); | |
1023 | rt2500pci_bbp_write(rt2x00dev, 62, 0x10); | |
1024 | ||
95ea3627 ID |
1025 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1026 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1027 | ||
1028 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1029 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1030 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1031 | rt2500pci_bbp_write(rt2x00dev, reg_id, value); |
1032 | } | |
1033 | } | |
95ea3627 ID |
1034 | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * Device state switch handlers. | |
1040 | */ | |
1041 | static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev, | |
1042 | enum dev_state state) | |
1043 | { | |
1044 | u32 reg; | |
1045 | ||
1046 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | |
1047 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, | |
2b08da3f ID |
1048 | (state == STATE_RADIO_RX_OFF) || |
1049 | (state == STATE_RADIO_RX_OFF_LINK)); | |
95ea3627 ID |
1050 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
1051 | } | |
1052 | ||
1053 | static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | |
1054 | enum dev_state state) | |
1055 | { | |
1056 | int mask = (state == STATE_RADIO_IRQ_OFF); | |
1057 | u32 reg; | |
1058 | ||
1059 | /* | |
1060 | * When interrupts are being enabled, the interrupt registers | |
1061 | * should clear the register to assure a clean state. | |
1062 | */ | |
1063 | if (state == STATE_RADIO_IRQ_ON) { | |
1064 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); | |
1065 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * Only toggle the interrupts bits we are going to use. | |
1070 | * Non-checked interrupt bits are disabled by default. | |
1071 | */ | |
1072 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | |
1073 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); | |
1074 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); | |
1075 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); | |
1076 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); | |
1077 | rt2x00_set_field32(®, CSR8_RXDONE, mask); | |
1078 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | |
1079 | } | |
1080 | ||
1081 | static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1082 | { | |
1083 | /* | |
1084 | * Initialize all registers. | |
1085 | */ | |
2b08da3f ID |
1086 | if (unlikely(rt2500pci_init_queues(rt2x00dev) || |
1087 | rt2500pci_init_registers(rt2x00dev) || | |
1088 | rt2500pci_init_bbp(rt2x00dev))) | |
95ea3627 | 1089 | return -EIO; |
95ea3627 | 1090 | |
95ea3627 ID |
1091 | return 0; |
1092 | } | |
1093 | ||
1094 | static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1095 | { | |
1096 | u32 reg; | |
1097 | ||
95ea3627 ID |
1098 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); |
1099 | ||
1100 | /* | |
1101 | * Disable synchronisation. | |
1102 | */ | |
1103 | rt2x00pci_register_write(rt2x00dev, CSR14, 0); | |
1104 | ||
1105 | /* | |
1106 | * Cancel RX and TX. | |
1107 | */ | |
1108 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | |
1109 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); | |
1110 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | |
95ea3627 ID |
1111 | } |
1112 | ||
1113 | static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, | |
1114 | enum dev_state state) | |
1115 | { | |
1116 | u32 reg; | |
1117 | unsigned int i; | |
1118 | char put_to_sleep; | |
1119 | char bbp_state; | |
1120 | char rf_state; | |
1121 | ||
1122 | put_to_sleep = (state != STATE_AWAKE); | |
1123 | ||
1124 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); | |
1125 | rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); | |
1126 | rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); | |
1127 | rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); | |
1128 | rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); | |
1129 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); | |
1130 | ||
1131 | /* | |
1132 | * Device is not guaranteed to be in the requested state yet. | |
1133 | * We must wait until the register indicates that the | |
1134 | * device has entered the correct state. | |
1135 | */ | |
1136 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1137 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); | |
1138 | bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE); | |
1139 | rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE); | |
1140 | if (bbp_state == state && rf_state == state) | |
1141 | return 0; | |
1142 | msleep(10); | |
1143 | } | |
1144 | ||
95ea3627 ID |
1145 | return -EBUSY; |
1146 | } | |
1147 | ||
1148 | static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1149 | enum dev_state state) | |
1150 | { | |
1151 | int retval = 0; | |
1152 | ||
1153 | switch (state) { | |
1154 | case STATE_RADIO_ON: | |
1155 | retval = rt2500pci_enable_radio(rt2x00dev); | |
1156 | break; | |
1157 | case STATE_RADIO_OFF: | |
1158 | rt2500pci_disable_radio(rt2x00dev); | |
1159 | break; | |
1160 | case STATE_RADIO_RX_ON: | |
61667d8d | 1161 | case STATE_RADIO_RX_ON_LINK: |
95ea3627 | 1162 | case STATE_RADIO_RX_OFF: |
61667d8d | 1163 | case STATE_RADIO_RX_OFF_LINK: |
2b08da3f ID |
1164 | rt2500pci_toggle_rx(rt2x00dev, state); |
1165 | break; | |
1166 | case STATE_RADIO_IRQ_ON: | |
1167 | case STATE_RADIO_IRQ_OFF: | |
1168 | rt2500pci_toggle_irq(rt2x00dev, state); | |
95ea3627 ID |
1169 | break; |
1170 | case STATE_DEEP_SLEEP: | |
1171 | case STATE_SLEEP: | |
1172 | case STATE_STANDBY: | |
1173 | case STATE_AWAKE: | |
1174 | retval = rt2500pci_set_state(rt2x00dev, state); | |
1175 | break; | |
1176 | default: | |
1177 | retval = -ENOTSUPP; | |
1178 | break; | |
1179 | } | |
1180 | ||
2b08da3f ID |
1181 | if (unlikely(retval)) |
1182 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1183 | state, retval); | |
1184 | ||
95ea3627 ID |
1185 | return retval; |
1186 | } | |
1187 | ||
1188 | /* | |
1189 | * TX descriptor initialization | |
1190 | */ | |
1191 | static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |
dd3193e1 | 1192 | struct sk_buff *skb, |
61486e0f | 1193 | struct txentry_desc *txdesc) |
95ea3627 | 1194 | { |
181d6902 | 1195 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
b8be63ff | 1196 | struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; |
dd3193e1 | 1197 | __le32 *txd = skbdesc->desc; |
95ea3627 ID |
1198 | u32 word; |
1199 | ||
1200 | /* | |
1201 | * Start writing the descriptor words. | |
1202 | */ | |
4de36fe5 | 1203 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
c4da0048 | 1204 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
4de36fe5 GW |
1205 | rt2x00_desc_write(entry_priv->desc, 1, word); |
1206 | ||
95ea3627 ID |
1207 | rt2x00_desc_read(txd, 2, &word); |
1208 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); | |
181d6902 ID |
1209 | rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); |
1210 | rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min); | |
1211 | rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max); | |
95ea3627 ID |
1212 | rt2x00_desc_write(txd, 2, word); |
1213 | ||
1214 | rt2x00_desc_read(txd, 3, &word); | |
181d6902 ID |
1215 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); |
1216 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); | |
1217 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); | |
1218 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); | |
95ea3627 ID |
1219 | rt2x00_desc_write(txd, 3, word); |
1220 | ||
1221 | rt2x00_desc_read(txd, 10, &word); | |
1222 | rt2x00_set_field32(&word, TXD_W10_RTS, | |
181d6902 | 1223 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
95ea3627 ID |
1224 | rt2x00_desc_write(txd, 10, word); |
1225 | ||
1226 | rt2x00_desc_read(txd, 0, &word); | |
1227 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | |
1228 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1229 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1230 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1231 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1232 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1233 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1234 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1235 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
076f9582 | 1236 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
95ea3627 | 1237 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
181d6902 | 1238 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
95ea3627 | 1239 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
61486e0f | 1240 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
bf4634af | 1241 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); |
95ea3627 ID |
1242 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
1243 | rt2x00_desc_write(txd, 0, word); | |
1244 | } | |
1245 | ||
1246 | /* | |
1247 | * TX data initialization | |
1248 | */ | |
bd88a781 ID |
1249 | static void rt2500pci_write_beacon(struct queue_entry *entry) |
1250 | { | |
1251 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1252 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; | |
1253 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
1254 | u32 word; | |
1255 | u32 reg; | |
1256 | ||
1257 | /* | |
1258 | * Disable beaconing while we are reloading the beacon data, | |
1259 | * otherwise we might be sending out invalid data. | |
1260 | */ | |
1261 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | |
1262 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | |
1263 | rt2x00_set_field32(®, CSR14_TBCN, 0); | |
1264 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | |
1265 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
1266 | ||
1267 | /* | |
1268 | * Replace rt2x00lib allocated descriptor with the | |
1269 | * pointer to the _real_ hardware descriptor. | |
1270 | * After that, map the beacon to DMA and update the | |
1271 | * descriptor. | |
1272 | */ | |
1273 | memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len); | |
1274 | skbdesc->desc = entry_priv->desc; | |
1275 | ||
1276 | rt2x00queue_map_txskb(rt2x00dev, entry->skb); | |
1277 | ||
1278 | rt2x00_desc_read(entry_priv->desc, 1, &word); | |
1279 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | |
1280 | rt2x00_desc_write(entry_priv->desc, 1, word); | |
1281 | } | |
1282 | ||
95ea3627 | 1283 | static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1284 | const enum data_queue_qid queue) |
95ea3627 ID |
1285 | { |
1286 | u32 reg; | |
1287 | ||
e58c6aca | 1288 | if (queue == QID_BEACON) { |
95ea3627 ID |
1289 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
1290 | if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { | |
8af244cc ID |
1291 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
1292 | rt2x00_set_field32(®, CSR14_TBCN, 1); | |
95ea3627 ID |
1293 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
1294 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | |
1295 | } | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | |
e58c6aca ID |
1300 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); |
1301 | rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK)); | |
1302 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM)); | |
95ea3627 ID |
1303 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
1304 | } | |
1305 | ||
1306 | /* | |
1307 | * RX control handlers | |
1308 | */ | |
181d6902 ID |
1309 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, |
1310 | struct rxdone_entry_desc *rxdesc) | |
95ea3627 | 1311 | { |
b8be63ff | 1312 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
1313 | u32 word0; |
1314 | u32 word2; | |
1315 | ||
b8be63ff ID |
1316 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1317 | rt2x00_desc_read(entry_priv->desc, 2, &word2); | |
95ea3627 | 1318 | |
4150c572 | 1319 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1320 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
4150c572 | 1321 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
181d6902 ID |
1322 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
1323 | ||
89993890 ID |
1324 | /* |
1325 | * Obtain the status about this packet. | |
1326 | * When frame was received with an OFDM bitrate, | |
1327 | * the signal is the PLCP value. If it was received with | |
1328 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
1329 | */ | |
181d6902 ID |
1330 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); |
1331 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - | |
1332 | entry->queue->rt2x00dev->rssi_offset; | |
181d6902 | 1333 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1334 | |
19d30e02 ID |
1335 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1336 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1337 | else |
1338 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1339 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1340 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
95ea3627 ID |
1341 | } |
1342 | ||
1343 | /* | |
1344 | * Interrupt functions. | |
1345 | */ | |
181d6902 | 1346 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1347 | const enum data_queue_qid queue_idx) |
95ea3627 | 1348 | { |
181d6902 | 1349 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
b8be63ff | 1350 | struct queue_entry_priv_pci *entry_priv; |
181d6902 ID |
1351 | struct queue_entry *entry; |
1352 | struct txdone_entry_desc txdesc; | |
95ea3627 | 1353 | u32 word; |
95ea3627 | 1354 | |
181d6902 ID |
1355 | while (!rt2x00queue_empty(queue)) { |
1356 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | |
b8be63ff ID |
1357 | entry_priv = entry->priv_data; |
1358 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 ID |
1359 | |
1360 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
1361 | !rt2x00_get_field32(word, TXD_W0_VALID)) | |
1362 | break; | |
1363 | ||
1364 | /* | |
1365 | * Obtain the status about this packet. | |
1366 | */ | |
fb55f4d1 ID |
1367 | txdesc.flags = 0; |
1368 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { | |
1369 | case 0: /* Success */ | |
1370 | case 1: /* Success with retry */ | |
1371 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
1372 | break; | |
1373 | case 2: /* Failure, excessive retries */ | |
1374 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | |
1375 | /* Don't break, this is a failed frame! */ | |
1376 | default: /* Failure */ | |
1377 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
1378 | } | |
181d6902 | 1379 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
95ea3627 | 1380 | |
d74f5ba4 | 1381 | rt2x00lib_txdone(entry, &txdesc); |
95ea3627 | 1382 | } |
95ea3627 ID |
1383 | } |
1384 | ||
1385 | static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) | |
1386 | { | |
1387 | struct rt2x00_dev *rt2x00dev = dev_instance; | |
1388 | u32 reg; | |
1389 | ||
1390 | /* | |
1391 | * Get the interrupt sources & saved to local variable. | |
1392 | * Write register value back to clear pending interrupts. | |
1393 | */ | |
1394 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); | |
1395 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); | |
1396 | ||
1397 | if (!reg) | |
1398 | return IRQ_NONE; | |
1399 | ||
0262ab0d | 1400 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
95ea3627 ID |
1401 | return IRQ_HANDLED; |
1402 | ||
1403 | /* | |
1404 | * Handle interrupts, walk through all bits | |
1405 | * and run the tasks, the bits are checked in order of | |
1406 | * priority. | |
1407 | */ | |
1408 | ||
1409 | /* | |
1410 | * 1 - Beacon timer expired interrupt. | |
1411 | */ | |
1412 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) | |
1413 | rt2x00lib_beacondone(rt2x00dev); | |
1414 | ||
1415 | /* | |
1416 | * 2 - Rx ring done interrupt. | |
1417 | */ | |
1418 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) | |
1419 | rt2x00pci_rxdone(rt2x00dev); | |
1420 | ||
1421 | /* | |
1422 | * 3 - Atim ring transmit done interrupt. | |
1423 | */ | |
1424 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) | |
e58c6aca | 1425 | rt2500pci_txdone(rt2x00dev, QID_ATIM); |
95ea3627 ID |
1426 | |
1427 | /* | |
1428 | * 4 - Priority ring transmit done interrupt. | |
1429 | */ | |
1430 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) | |
e58c6aca | 1431 | rt2500pci_txdone(rt2x00dev, QID_AC_BE); |
95ea3627 ID |
1432 | |
1433 | /* | |
1434 | * 5 - Tx ring transmit done interrupt. | |
1435 | */ | |
1436 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) | |
e58c6aca | 1437 | rt2500pci_txdone(rt2x00dev, QID_AC_BK); |
95ea3627 ID |
1438 | |
1439 | return IRQ_HANDLED; | |
1440 | } | |
1441 | ||
1442 | /* | |
1443 | * Device probe functions. | |
1444 | */ | |
1445 | static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1446 | { | |
1447 | struct eeprom_93cx6 eeprom; | |
1448 | u32 reg; | |
1449 | u16 word; | |
1450 | u8 *mac; | |
1451 | ||
1452 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); | |
1453 | ||
1454 | eeprom.data = rt2x00dev; | |
1455 | eeprom.register_read = rt2500pci_eepromregister_read; | |
1456 | eeprom.register_write = rt2500pci_eepromregister_write; | |
1457 | eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? | |
1458 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; | |
1459 | eeprom.reg_data_in = 0; | |
1460 | eeprom.reg_data_out = 0; | |
1461 | eeprom.reg_data_clock = 0; | |
1462 | eeprom.reg_chip_select = 0; | |
1463 | ||
1464 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
1465 | EEPROM_SIZE / sizeof(u16)); | |
1466 | ||
1467 | /* | |
1468 | * Start validation of the data that has been read. | |
1469 | */ | |
1470 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1471 | if (!is_valid_ether_addr(mac)) { | |
1472 | random_ether_addr(mac); | |
e174961c | 1473 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1474 | } |
1475 | ||
1476 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1477 | if (word == 0xffff) { | |
1478 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1479 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1480 | ANTENNA_SW_DIVERSITY); | |
1481 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1482 | ANTENNA_SW_DIVERSITY); | |
1483 | rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, | |
1484 | LED_MODE_DEFAULT); | |
95ea3627 ID |
1485 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); |
1486 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1487 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522); | |
1488 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1489 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1490 | } | |
1491 | ||
1492 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1493 | if (word == 0xffff) { | |
1494 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); | |
1495 | rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); | |
1496 | rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); | |
1497 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1498 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1499 | } | |
1500 | ||
1501 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word); | |
1502 | if (word == 0xffff) { | |
1503 | rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI, | |
1504 | DEFAULT_RSSI_OFFSET); | |
1505 | rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); | |
1506 | EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word); | |
1507 | } | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1513 | { | |
1514 | u32 reg; | |
1515 | u16 value; | |
1516 | u16 eeprom; | |
1517 | ||
1518 | /* | |
1519 | * Read EEPROM word for configuration. | |
1520 | */ | |
1521 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1522 | ||
1523 | /* | |
1524 | * Identify RF chipset. | |
1525 | */ | |
1526 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
1527 | rt2x00pci_register_read(rt2x00dev, CSR0, ®); | |
1528 | rt2x00_set_chip(rt2x00dev, RT2560, value, reg); | |
1529 | ||
1530 | if (!rt2x00_rf(&rt2x00dev->chip, RF2522) && | |
1531 | !rt2x00_rf(&rt2x00dev->chip, RF2523) && | |
1532 | !rt2x00_rf(&rt2x00dev->chip, RF2524) && | |
1533 | !rt2x00_rf(&rt2x00dev->chip, RF2525) && | |
1534 | !rt2x00_rf(&rt2x00dev->chip, RF2525E) && | |
1535 | !rt2x00_rf(&rt2x00dev->chip, RF5222)) { | |
1536 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); | |
1537 | return -ENODEV; | |
1538 | } | |
1539 | ||
1540 | /* | |
1541 | * Identify default antenna configuration. | |
1542 | */ | |
addc81bd | 1543 | rt2x00dev->default_ant.tx = |
95ea3627 | 1544 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1545 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1546 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1547 | ||
1548 | /* | |
1549 | * Store led mode, for correct led behaviour. | |
1550 | */ | |
771fd565 | 1551 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a9450b70 ID |
1552 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
1553 | ||
475433be | 1554 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
3d3e451f ID |
1555 | if (value == LED_MODE_TXRX_ACTIVITY || |
1556 | value == LED_MODE_DEFAULT || | |
1557 | value == LED_MODE_ASUS) | |
475433be ID |
1558 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
1559 | LED_TYPE_ACTIVITY); | |
771fd565 | 1560 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1561 | |
1562 | /* | |
1563 | * Detect if this device has an hardware controlled radio. | |
1564 | */ | |
58169529 | 1565 | #ifdef CONFIG_RT2X00_LIB_RFKILL |
95ea3627 | 1566 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
066cb637 | 1567 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
58169529 | 1568 | #endif /* CONFIG_RT2X00_LIB_RFKILL */ |
95ea3627 ID |
1569 | |
1570 | /* | |
1571 | * Check if the BBP tuning should be enabled. | |
1572 | */ | |
1573 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1574 | ||
1575 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) | |
1576 | __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags); | |
1577 | ||
1578 | /* | |
1579 | * Read the RSSI <-> dBm offset information. | |
1580 | */ | |
1581 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom); | |
1582 | rt2x00dev->rssi_offset = | |
1583 | rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI); | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | /* | |
1589 | * RF value list for RF2522 | |
1590 | * Supports: 2.4 GHz | |
1591 | */ | |
1592 | static const struct rf_channel rf_vals_bg_2522[] = { | |
1593 | { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 }, | |
1594 | { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 }, | |
1595 | { 3, 0x00002050, 0x000c2002, 0x00000101, 0 }, | |
1596 | { 4, 0x00002050, 0x000c2016, 0x00000101, 0 }, | |
1597 | { 5, 0x00002050, 0x000c202a, 0x00000101, 0 }, | |
1598 | { 6, 0x00002050, 0x000c203e, 0x00000101, 0 }, | |
1599 | { 7, 0x00002050, 0x000c2052, 0x00000101, 0 }, | |
1600 | { 8, 0x00002050, 0x000c2066, 0x00000101, 0 }, | |
1601 | { 9, 0x00002050, 0x000c207a, 0x00000101, 0 }, | |
1602 | { 10, 0x00002050, 0x000c208e, 0x00000101, 0 }, | |
1603 | { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 }, | |
1604 | { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 }, | |
1605 | { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 }, | |
1606 | { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 }, | |
1607 | }; | |
1608 | ||
1609 | /* | |
1610 | * RF value list for RF2523 | |
1611 | * Supports: 2.4 GHz | |
1612 | */ | |
1613 | static const struct rf_channel rf_vals_bg_2523[] = { | |
1614 | { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b }, | |
1615 | { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b }, | |
1616 | { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b }, | |
1617 | { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b }, | |
1618 | { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b }, | |
1619 | { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b }, | |
1620 | { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b }, | |
1621 | { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b }, | |
1622 | { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b }, | |
1623 | { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b }, | |
1624 | { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b }, | |
1625 | { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b }, | |
1626 | { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b }, | |
1627 | { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 }, | |
1628 | }; | |
1629 | ||
1630 | /* | |
1631 | * RF value list for RF2524 | |
1632 | * Supports: 2.4 GHz | |
1633 | */ | |
1634 | static const struct rf_channel rf_vals_bg_2524[] = { | |
1635 | { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b }, | |
1636 | { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b }, | |
1637 | { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b }, | |
1638 | { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b }, | |
1639 | { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b }, | |
1640 | { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b }, | |
1641 | { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b }, | |
1642 | { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b }, | |
1643 | { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b }, | |
1644 | { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b }, | |
1645 | { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b }, | |
1646 | { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b }, | |
1647 | { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b }, | |
1648 | { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 }, | |
1649 | }; | |
1650 | ||
1651 | /* | |
1652 | * RF value list for RF2525 | |
1653 | * Supports: 2.4 GHz | |
1654 | */ | |
1655 | static const struct rf_channel rf_vals_bg_2525[] = { | |
1656 | { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b }, | |
1657 | { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b }, | |
1658 | { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b }, | |
1659 | { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b }, | |
1660 | { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b }, | |
1661 | { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b }, | |
1662 | { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b }, | |
1663 | { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b }, | |
1664 | { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b }, | |
1665 | { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b }, | |
1666 | { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b }, | |
1667 | { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b }, | |
1668 | { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b }, | |
1669 | { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 }, | |
1670 | }; | |
1671 | ||
1672 | /* | |
1673 | * RF value list for RF2525e | |
1674 | * Supports: 2.4 GHz | |
1675 | */ | |
1676 | static const struct rf_channel rf_vals_bg_2525e[] = { | |
1677 | { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b }, | |
1678 | { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b }, | |
1679 | { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b }, | |
1680 | { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b }, | |
1681 | { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b }, | |
1682 | { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b }, | |
1683 | { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b }, | |
1684 | { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b }, | |
1685 | { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b }, | |
1686 | { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b }, | |
1687 | { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b }, | |
1688 | { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b }, | |
1689 | { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b }, | |
1690 | { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b }, | |
1691 | }; | |
1692 | ||
1693 | /* | |
1694 | * RF value list for RF5222 | |
1695 | * Supports: 2.4 GHz & 5.2 GHz | |
1696 | */ | |
1697 | static const struct rf_channel rf_vals_5222[] = { | |
1698 | { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b }, | |
1699 | { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b }, | |
1700 | { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b }, | |
1701 | { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b }, | |
1702 | { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b }, | |
1703 | { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b }, | |
1704 | { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b }, | |
1705 | { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b }, | |
1706 | { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b }, | |
1707 | { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b }, | |
1708 | { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b }, | |
1709 | { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b }, | |
1710 | { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b }, | |
1711 | { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b }, | |
1712 | ||
1713 | /* 802.11 UNI / HyperLan 2 */ | |
1714 | { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f }, | |
1715 | { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f }, | |
1716 | { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f }, | |
1717 | { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f }, | |
1718 | { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f }, | |
1719 | { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f }, | |
1720 | { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f }, | |
1721 | { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f }, | |
1722 | ||
1723 | /* 802.11 HyperLan 2 */ | |
1724 | { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f }, | |
1725 | { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f }, | |
1726 | { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f }, | |
1727 | { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f }, | |
1728 | { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f }, | |
1729 | { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f }, | |
1730 | { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f }, | |
1731 | { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f }, | |
1732 | { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f }, | |
1733 | { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f }, | |
1734 | ||
1735 | /* 802.11 UNII */ | |
1736 | { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f }, | |
1737 | { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 }, | |
1738 | { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 }, | |
1739 | { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 }, | |
1740 | { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 }, | |
1741 | }; | |
1742 | ||
8c5e7a5f | 1743 | static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1744 | { |
1745 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
1746 | struct channel_info *info; |
1747 | char *tx_power; | |
95ea3627 ID |
1748 | unsigned int i; |
1749 | ||
1750 | /* | |
1751 | * Initialize all hw fields. | |
1752 | */ | |
566bfe5a | 1753 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
4be8c387 JB |
1754 | IEEE80211_HW_SIGNAL_DBM | |
1755 | IEEE80211_HW_SUPPORTS_PS | | |
1756 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
566bfe5a | 1757 | |
95ea3627 | 1758 | rt2x00dev->hw->extra_tx_headroom = 0; |
95ea3627 | 1759 | |
14a3bf89 | 1760 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
1761 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
1762 | rt2x00_eeprom_addr(rt2x00dev, | |
1763 | EEPROM_MAC_ADDR_0)); | |
1764 | ||
95ea3627 ID |
1765 | /* |
1766 | * Initialize hw_mode information. | |
1767 | */ | |
31562e80 ID |
1768 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
1769 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 ID |
1770 | |
1771 | if (rt2x00_rf(&rt2x00dev->chip, RF2522)) { | |
1772 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); | |
1773 | spec->channels = rf_vals_bg_2522; | |
1774 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) { | |
1775 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); | |
1776 | spec->channels = rf_vals_bg_2523; | |
1777 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) { | |
1778 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); | |
1779 | spec->channels = rf_vals_bg_2524; | |
1780 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) { | |
1781 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); | |
1782 | spec->channels = rf_vals_bg_2525; | |
1783 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) { | |
1784 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); | |
1785 | spec->channels = rf_vals_bg_2525e; | |
1786 | } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) { | |
31562e80 | 1787 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
1788 | spec->num_channels = ARRAY_SIZE(rf_vals_5222); |
1789 | spec->channels = rf_vals_5222; | |
95ea3627 | 1790 | } |
8c5e7a5f ID |
1791 | |
1792 | /* | |
1793 | * Create channel information array | |
1794 | */ | |
1795 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); | |
1796 | if (!info) | |
1797 | return -ENOMEM; | |
1798 | ||
1799 | spec->channels_info = info; | |
1800 | ||
1801 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); | |
1802 | for (i = 0; i < 14; i++) | |
1803 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
1804 | ||
1805 | if (spec->num_channels > 14) { | |
1806 | for (i = 14; i < spec->num_channels; i++) | |
1807 | info[i].tx_power1 = DEFAULT_TXPOWER; | |
1808 | } | |
1809 | ||
1810 | return 0; | |
95ea3627 ID |
1811 | } |
1812 | ||
1813 | static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |
1814 | { | |
1815 | int retval; | |
1816 | ||
1817 | /* | |
1818 | * Allocate eeprom data. | |
1819 | */ | |
1820 | retval = rt2500pci_validate_eeprom(rt2x00dev); | |
1821 | if (retval) | |
1822 | return retval; | |
1823 | ||
1824 | retval = rt2500pci_init_eeprom(rt2x00dev); | |
1825 | if (retval) | |
1826 | return retval; | |
1827 | ||
1828 | /* | |
1829 | * Initialize hw specifications. | |
1830 | */ | |
8c5e7a5f ID |
1831 | retval = rt2500pci_probe_hw_mode(rt2x00dev); |
1832 | if (retval) | |
1833 | return retval; | |
95ea3627 ID |
1834 | |
1835 | /* | |
c4da0048 | 1836 | * This device requires the atim queue and DMA-mapped skbs. |
95ea3627 | 1837 | */ |
181d6902 | 1838 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
c4da0048 | 1839 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
95ea3627 ID |
1840 | |
1841 | /* | |
1842 | * Set the rssi offset. | |
1843 | */ | |
1844 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
1845 | ||
1846 | return 0; | |
1847 | } | |
1848 | ||
1849 | /* | |
1850 | * IEEE80211 stack callback functions. | |
1851 | */ | |
95ea3627 ID |
1852 | static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw) |
1853 | { | |
1854 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1855 | u64 tsf; | |
1856 | u32 reg; | |
1857 | ||
1858 | rt2x00pci_register_read(rt2x00dev, CSR17, ®); | |
1859 | tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; | |
1860 | rt2x00pci_register_read(rt2x00dev, CSR16, ®); | |
1861 | tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); | |
1862 | ||
1863 | return tsf; | |
1864 | } | |
1865 | ||
95ea3627 ID |
1866 | static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) |
1867 | { | |
1868 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
1869 | u32 reg; | |
1870 | ||
1871 | rt2x00pci_register_read(rt2x00dev, CSR15, ®); | |
1872 | return rt2x00_get_field32(reg, CSR15_BEACON_SENT); | |
1873 | } | |
1874 | ||
1875 | static const struct ieee80211_ops rt2500pci_mac80211_ops = { | |
1876 | .tx = rt2x00mac_tx, | |
4150c572 JB |
1877 | .start = rt2x00mac_start, |
1878 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
1879 | .add_interface = rt2x00mac_add_interface, |
1880 | .remove_interface = rt2x00mac_remove_interface, | |
1881 | .config = rt2x00mac_config, | |
1882 | .config_interface = rt2x00mac_config_interface, | |
3a643d24 | 1883 | .configure_filter = rt2x00mac_configure_filter, |
95ea3627 | 1884 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 1885 | .bss_info_changed = rt2x00mac_bss_info_changed, |
95ea3627 ID |
1886 | .conf_tx = rt2x00mac_conf_tx, |
1887 | .get_tx_stats = rt2x00mac_get_tx_stats, | |
1888 | .get_tsf = rt2500pci_get_tsf, | |
95ea3627 ID |
1889 | .tx_last_beacon = rt2500pci_tx_last_beacon, |
1890 | }; | |
1891 | ||
1892 | static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { | |
1893 | .irq_handler = rt2500pci_interrupt, | |
1894 | .probe_hw = rt2500pci_probe_hw, | |
1895 | .initialize = rt2x00pci_initialize, | |
1896 | .uninitialize = rt2x00pci_uninitialize, | |
798b7adb ID |
1897 | .get_entry_state = rt2500pci_get_entry_state, |
1898 | .clear_entry = rt2500pci_clear_entry, | |
95ea3627 | 1899 | .set_device_state = rt2500pci_set_device_state, |
95ea3627 | 1900 | .rfkill_poll = rt2500pci_rfkill_poll, |
95ea3627 ID |
1901 | .link_stats = rt2500pci_link_stats, |
1902 | .reset_tuner = rt2500pci_reset_tuner, | |
1903 | .link_tuner = rt2500pci_link_tuner, | |
1904 | .write_tx_desc = rt2500pci_write_tx_desc, | |
1905 | .write_tx_data = rt2x00pci_write_tx_data, | |
bd88a781 | 1906 | .write_beacon = rt2500pci_write_beacon, |
95ea3627 ID |
1907 | .kick_tx_queue = rt2500pci_kick_tx_queue, |
1908 | .fill_rxdone = rt2500pci_fill_rxdone, | |
3a643d24 | 1909 | .config_filter = rt2500pci_config_filter, |
6bb40dd1 | 1910 | .config_intf = rt2500pci_config_intf, |
72810379 | 1911 | .config_erp = rt2500pci_config_erp, |
e4ea1c40 | 1912 | .config_ant = rt2500pci_config_ant, |
95ea3627 ID |
1913 | .config = rt2500pci_config, |
1914 | }; | |
1915 | ||
181d6902 ID |
1916 | static const struct data_queue_desc rt2500pci_queue_rx = { |
1917 | .entry_num = RX_ENTRIES, | |
1918 | .data_size = DATA_FRAME_SIZE, | |
1919 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 1920 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
1921 | }; |
1922 | ||
1923 | static const struct data_queue_desc rt2500pci_queue_tx = { | |
1924 | .entry_num = TX_ENTRIES, | |
1925 | .data_size = DATA_FRAME_SIZE, | |
1926 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 1927 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
1928 | }; |
1929 | ||
1930 | static const struct data_queue_desc rt2500pci_queue_bcn = { | |
1931 | .entry_num = BEACON_ENTRIES, | |
1932 | .data_size = MGMT_FRAME_SIZE, | |
1933 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 1934 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
1935 | }; |
1936 | ||
1937 | static const struct data_queue_desc rt2500pci_queue_atim = { | |
1938 | .entry_num = ATIM_ENTRIES, | |
1939 | .data_size = DATA_FRAME_SIZE, | |
1940 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 1941 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
1942 | }; |
1943 | ||
95ea3627 | 1944 | static const struct rt2x00_ops rt2500pci_ops = { |
2360157c | 1945 | .name = KBUILD_MODNAME, |
6bb40dd1 ID |
1946 | .max_sta_intf = 1, |
1947 | .max_ap_intf = 1, | |
95ea3627 ID |
1948 | .eeprom_size = EEPROM_SIZE, |
1949 | .rf_size = RF_SIZE, | |
61448f88 | 1950 | .tx_queues = NUM_TX_QUEUES, |
181d6902 ID |
1951 | .rx = &rt2500pci_queue_rx, |
1952 | .tx = &rt2500pci_queue_tx, | |
1953 | .bcn = &rt2500pci_queue_bcn, | |
1954 | .atim = &rt2500pci_queue_atim, | |
95ea3627 ID |
1955 | .lib = &rt2500pci_rt2x00_ops, |
1956 | .hw = &rt2500pci_mac80211_ops, | |
1957 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
1958 | .debugfs = &rt2500pci_rt2x00debug, | |
1959 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
1960 | }; | |
1961 | ||
1962 | /* | |
1963 | * RT2500pci module information. | |
1964 | */ | |
1965 | static struct pci_device_id rt2500pci_device_table[] = { | |
1966 | { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) }, | |
1967 | { 0, } | |
1968 | }; | |
1969 | ||
1970 | MODULE_AUTHOR(DRV_PROJECT); | |
1971 | MODULE_VERSION(DRV_VERSION); | |
1972 | MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver."); | |
1973 | MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards"); | |
1974 | MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); | |
1975 | MODULE_LICENSE("GPL"); | |
1976 | ||
1977 | static struct pci_driver rt2500pci_driver = { | |
2360157c | 1978 | .name = KBUILD_MODNAME, |
95ea3627 ID |
1979 | .id_table = rt2500pci_device_table, |
1980 | .probe = rt2x00pci_probe, | |
1981 | .remove = __devexit_p(rt2x00pci_remove), | |
1982 | .suspend = rt2x00pci_suspend, | |
1983 | .resume = rt2x00pci_resume, | |
1984 | }; | |
1985 | ||
1986 | static int __init rt2500pci_init(void) | |
1987 | { | |
1988 | return pci_register_driver(&rt2500pci_driver); | |
1989 | } | |
1990 | ||
1991 | static void __exit rt2500pci_exit(void) | |
1992 | { | |
1993 | pci_unregister_driver(&rt2500pci_driver); | |
1994 | } | |
1995 | ||
1996 | module_init(rt2500pci_init); | |
1997 | module_exit(rt2500pci_exit); |