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rt2x00: Initialize AMPDU_BA_WINSIZE register
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt2500pci.h"
39
40/*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
c9c3b1a5
ID		 53#define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55#define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 57
0e14f6d3 58static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 59 const unsigned int word, const u8 value)
60{
61 u32 reg;
62
8ff48a8b
ID		 63 mutex_lock(&rt2x00dev->csr_mutex);
64
95ea3627 65 /*
c9c3b1a5
ID		 66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
95ea3627 68 */
c9c3b1a5
ID		 69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
8ff48a8b 78
8ff48a8b 79 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 80}
81
0e14f6d3 82static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int word, u8 *value)
84{
85 u32 reg;
86
8ff48a8b
ID		 87 mutex_lock(&rt2x00dev->csr_mutex);
88
95ea3627 89 /*
c9c3b1a5
ID		 90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
95ea3627 96 */
c9c3b1a5
ID		 97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 102
c9c3b1a5 103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 104
c9c3b1a5
ID		 105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
95ea3627
ID		 107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 109
110 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 111}
112
0e14f6d3 113static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int word, const u32 value)
115{
116 u32 reg;
95ea3627 117
8ff48a8b
ID		 118 mutex_lock(&rt2x00dev->csr_mutex);
119
c9c3b1a5
ID		 120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 133 }
134
8ff48a8b 135 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 136}
137
138static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139{
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151}
152
153static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154{
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166}
167
168#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 169static const struct rt2x00debug rt2500pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
743b97ca
ID		 172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
95ea3627
ID		 176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
743b97ca 182 .word_base = EEPROM_BASE,
95ea3627
ID		 183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2500pci_bbp_read,
188 .write = rt2500pci_bbp_write,
743b97ca 189 .word_base = BBP_BASE,
95ea3627
ID		 190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2500pci_rf_write,
743b97ca 196 .word_base = RF_BASE,
95ea3627
ID		 197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200};
201#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
95ea3627
ID		 203static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204{
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209}
95ea3627 210
771fd565 211#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 212static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 213 enum led_brightness brightness)
214{
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
a2e1d52a 222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228}
a2e1d52a
ID		 229
230static int rt2500pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244}
475433be
ID		 245
246static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2500pci_brightness_set;
253 led->led_dev.blink_set = rt2500pci_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
3a643d24
ID		 261static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263{
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * and broadcast frames will always be accepted since
270 * there is no filter for it at this time.
271 */
272 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
273 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
274 !(filter_flags & FIF_FCSFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
276 !(filter_flags & FIF_PLCPFAIL));
277 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
278 !(filter_flags & FIF_CONTROL));
279 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
280 !(filter_flags & FIF_PROMISC_IN_BSS));
281 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 282 !(filter_flags & FIF_PROMISC_IN_BSS) &&
283 !rt2x00dev->intf_ap_count);
3a643d24
ID		 284 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
286 !(filter_flags & FIF_ALLMULTI));
287 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
288 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
289}
290
6bb40dd1
ID		 291static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
292 struct rt2x00_intf *intf,
293 struct rt2x00intf_conf *conf,
294 const unsigned int flags)
95ea3627 295{
e58c6aca 296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
6bb40dd1 297 unsigned int bcn_preload;
95ea3627
ID		 298 u32 reg;
299
6bb40dd1 300 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 301 /*
302 * Enable beacon config
303 */
bad13639 304 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 305 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
306 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
307 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
308 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 309
6bb40dd1
ID		 310 /*
311 * Enable synchronisation.
312 */
313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 314 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 316 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 317 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318 }
319
320 if (flags & CONFIG_UPDATE_MAC)
321 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
322 conf->mac, sizeof(conf->mac));
323
324 if (flags & CONFIG_UPDATE_BSSID)
325 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
326 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 327}
328
3a643d24
ID		 329static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 struct rt2x00lib_erp *erp)
95ea3627 331{
5c58ee51 332 int preamble_mask;
95ea3627 333 u32 reg;
95ea3627 334
5c58ee51
ID		 335 /*
336 * When short preamble is enabled, we should set bit 0x08
337 */
72810379 338 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 339
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
8a566afe
ID		 343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
95ea3627 347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 370
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
8a566afe
ID		 377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
381
e4ea1c40
ID		 382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
386
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 391}
392
e4ea1c40
ID		 393static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
394 struct antenna_setup *ant)
95ea3627 395{
e4ea1c40
ID		 396 u32 reg;
397 u8 r14;
398 u8 r2;
399
400 /*
401 * We should never come here because rt2x00lib is supposed
402 * to catch this and send us the correct antenna explicitely.
403 */
404 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
405 ant->tx == ANTENNA_SW_DIVERSITY);
406
407 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
408 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
409 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
410
411 /*
412 * Configure the TX antenna.
413 */
414 switch (ant->tx) {
415 case ANTENNA_A:
416 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
417 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
418 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
419 break;
420 case ANTENNA_B:
421 default:
422 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
423 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
424 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
425 break;
426 }
427
428 /*
429 * Configure the RX antenna.
430 */
431 switch (ant->rx) {
432 case ANTENNA_A:
433 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
434 break;
435 case ANTENNA_B:
436 default:
437 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
438 break;
439 }
440
441 /*
442 * RT2525E and RT5222 need to flip TX I/Q
443 */
5122d898 444 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
e4ea1c40
ID		 445 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
446 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
447 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
448
449 /*
450 * RT2525E does not need RX I/Q Flip.
451 */
5122d898 452 if (rt2x00_rf(rt2x00dev, RF2525E))
e4ea1c40
ID		 453 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
454 } else {
455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
456 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
457 }
458
459 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
460 rt2500pci_bbp_write(rt2x00dev, 14, r14);
461 rt2500pci_bbp_write(rt2x00dev, 2, r2);
95ea3627
ID		 462}
463
464static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 465 struct rf_channel *rf, const int txpower)
95ea3627 466{
95ea3627
ID		 467 u8 r70;
468
95ea3627
ID		 469 /*
470 * Set TXpower.
471 */
5c58ee51 472 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 473
474 /*
475 * Switch on tuning bits.
476 * For RT2523 devices we do not need to update the R1 register.
477 */
5122d898 478 if (!rt2x00_rf(rt2x00dev, RF2523))
5c58ee51
ID		 479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 481
482 /*
483 * For RT2525 we should first set the channel to half band higher.
484 */
5122d898 485 if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 486 static const u32 vals[] = {
487 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
488 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
489 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
490 0x00080d2e, 0x00080d3a
491 };
492
5c58ee51
ID		 493 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
495 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
496 if (rf->rf4)
497 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 498 }
499
5c58ee51
ID		 500 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
501 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
502 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
503 if (rf->rf4)
504 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 505
506 /*
507 * Channel 14 requires the Japan filter bit to be set.
508 */
509 r70 = 0x46;
5c58ee51 510 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 511 rt2500pci_bbp_write(rt2x00dev, 70, r70);
512
513 msleep(1);
514
515 /*
516 * Switch off tuning bits.
517 * For RT2523 devices we do not need to update the R1 register.
518 */
5122d898 519 if (!rt2x00_rf(rt2x00dev, RF2523)) {
5c58ee51
ID		 520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 522 }
523
5c58ee51
ID		 524 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
525 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 526
527 /*
528 * Clear false CRC during channel switch.
529 */
5c58ee51 530 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 531}
532
533static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
534 const int txpower)
535{
536 u32 rf3;
537
538 rt2x00_rf_read(rt2x00dev, 3, &rf3);
539 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
540 rt2500pci_rf_write(rt2x00dev, 3, rf3);
541}
542
e4ea1c40
ID		 543static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
544 struct rt2x00lib_conf *libconf)
95ea3627
ID		 545{
546 u32 reg;
95ea3627 547
e4ea1c40
ID		 548 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
549 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
550 libconf->conf->long_frame_max_tx_count);
551 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
552 libconf->conf->short_frame_max_tx_count);
553 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 554}
555
7d7f19cc
ID		 556static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
557 struct rt2x00lib_conf *libconf)
558{
559 enum dev_state state =
560 (libconf->conf->flags & IEEE80211_CONF_PS) ?
561 STATE_SLEEP : STATE_AWAKE;
562 u32 reg;
563
564 if (state == STATE_SLEEP) {
565 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
566 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 567 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 568 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
569 libconf->conf->listen_interval - 1);
570
571 /* We must first disable autowake before it can be enabled */
572 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
573 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
574
575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 577 } else {
578 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
579 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
580 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 581 }
582
583 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
584}
585
95ea3627 586static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 587 struct rt2x00lib_conf *libconf,
588 const unsigned int flags)
95ea3627 589{
e4ea1c40 590 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 591 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
592 libconf->conf->power_level);
e4ea1c40
ID		 593 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
594 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 595 rt2500pci_config_txpower(rt2x00dev,
596 libconf->conf->power_level);
e4ea1c40
ID		 597 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
598 rt2500pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 599 if (flags & IEEE80211_CONF_CHANGE_PS)
600 rt2500pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 601}
602
95ea3627
ID		 603/*
604 * Link tuning
605 */
ebcf26da
ID		 606static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
607 struct link_qual *qual)
95ea3627
ID		 608{
609 u32 reg;
610
611 /*
612 * Update FCS error count from register.
613 */
614 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 615 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 616
617 /*
618 * Update False CCA count from register.
619 */
620 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 621 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 622}
623
5352ff65
ID		 624static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
625 struct link_qual *qual, u8 vgc_level)
eb20b4e8 626{
5352ff65 627 if (qual->vgc_level_reg != vgc_level) {
eb20b4e8 628 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
223dcc26 629 qual->vgc_level = vgc_level;
5352ff65 630 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 631 }
632}
633
5352ff65
ID		 634static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
635 struct link_qual *qual)
95ea3627 636{
5352ff65 637 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
95ea3627
ID		 638}
639
5352ff65
ID		 640static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
641 struct link_qual *qual, const u32 count)
95ea3627 642{
95ea3627
ID		 643 /*
644 * To prevent collisions with MAC ASIC on chipsets
645 * up to version C the link tuning should halt after 20
6bb40dd1 646 * seconds while being associated.
95ea3627 647 */
5122d898 648 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
5352ff65 649 rt2x00dev->intf_associated && count > 20)
95ea3627
ID		 650 return;
651
95ea3627
ID		 652 /*
653 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 654 * to the dynamic CCA tuning. Chipset version D and higher
655 * should go straight to dynamic CCA tuning when they
656 * are not associated.
95ea3627 657 */
5122d898 658 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
6bb40dd1 659 !rt2x00dev->intf_associated)
95ea3627
ID		 660 goto dynamic_cca_tune;
661
662 /*
663 * A too low RSSI will cause too much false CCA which will
664 * then corrupt the R17 tuning. To remidy this the tuning should
665 * be stopped (While making sure the R17 value will not exceed limits)
666 */
5352ff65
ID		 667 if (qual->rssi < -80 && count > 20) {
668 if (qual->vgc_level_reg >= 0x41)
669 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 670 return;
671 }
672
673 /*
674 * Special big-R17 for short distance
675 */
5352ff65
ID		 676 if (qual->rssi >= -58) {
677 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
95ea3627
ID		 678 return;
679 }
680
681 /*
682 * Special mid-R17 for middle distance
683 */
5352ff65
ID		 684 if (qual->rssi >= -74) {
685 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
95ea3627
ID		 686 return;
687 }
688
689 /*
690 * Leave short or middle distance condition, restore r17
691 * to the dynamic tuning range.
692 */
5352ff65
ID		 693 if (qual->vgc_level_reg >= 0x41) {
694 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 695 return;
696 }
697
698dynamic_cca_tune:
699
700 /*
701 * R17 is inside the dynamic tuning range,
702 * start tuning the link based on the false cca counter.
703 */
223dcc26 704 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
5352ff65 705 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
223dcc26 706 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
5352ff65 707 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
95ea3627
ID		 708}
709
710/*
711 * Initialization functions.
712 */
798b7adb 713static bool rt2500pci_get_entry_state(struct queue_entry *entry)
95ea3627 714{
b8be63ff 715 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 716 u32 word;
717
798b7adb
ID		 718 if (entry->queue->qid == QID_RX) {
719 rt2x00_desc_read(entry_priv->desc, 0, &word);
720
721 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
722 } else {
723 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 724
798b7adb
ID		 725 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
726 rt2x00_get_field32(word, TXD_W0_VALID));
727 }
95ea3627
ID		 728}
729
798b7adb 730static void rt2500pci_clear_entry(struct queue_entry *entry)
95ea3627 731{
b8be63ff 732 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 733 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 734 u32 word;
735
798b7adb
ID		 736 if (entry->queue->qid == QID_RX) {
737 rt2x00_desc_read(entry_priv->desc, 1, &word);
738 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
739 rt2x00_desc_write(entry_priv->desc, 1, word);
740
741 rt2x00_desc_read(entry_priv->desc, 0, &word);
742 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
743 rt2x00_desc_write(entry_priv->desc, 0, word);
744 } else {
745 rt2x00_desc_read(entry_priv->desc, 0, &word);
746 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
747 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
748 rt2x00_desc_write(entry_priv->desc, 0, word);
749 }
95ea3627
ID		 750}
751
181d6902 752static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 753{
b8be63ff 754 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 755 u32 reg;
756
95ea3627
ID		 757 /*
758 * Initialize registers.
759 */
760 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 761 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
762 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
763 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 765 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
766
b8be63ff 767 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 768 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 769 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 770 entry_priv->desc_dma);
95ea3627
ID		 771 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
772
b8be63ff 773 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 774 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 775 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 776 entry_priv->desc_dma);
95ea3627
ID		 777 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
778
b8be63ff 779 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 780 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 781 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 782 entry_priv->desc_dma);
95ea3627
ID		 783 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
784
b8be63ff 785 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 786 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 787 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 788 entry_priv->desc_dma);
95ea3627
ID		 789 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
790
791 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
792 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 793 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 794 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
795
b8be63ff 796 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 797 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 798 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
799 entry_priv->desc_dma);
95ea3627
ID		 800 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
801
802 return 0;
803}
804
805static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
806{
807 u32 reg;
808
809 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
813
814 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
815 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
816 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
817 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
818 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
819
820 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
821 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
822 rt2x00dev->rx->data_size / 128);
823 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
824
825 /*
826 * Always use CWmin and CWmax set in descriptor.
827 */
828 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
829 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
830 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
831
1f909162
ID		 832 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
833 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
834 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
835 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
836 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
837 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
838 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
839 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
840 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
841 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
842
95ea3627
ID		 843 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
844
845 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
846 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
847 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
852 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
853 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
854 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
855
856 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
857 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
858 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
859 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
860 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
861 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
862
863 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
864 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
865 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
866 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
867 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
868 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
869
870 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
871 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
872 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
873 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
874 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
875 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
876
877 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
878 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
879 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
884 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
885 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
886 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
887
888 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
889 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
890 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
891 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
892 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
893 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
894 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
895 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
896 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
897
898 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
899
900 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
901 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
902
903 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
904 return -EBUSY;
905
906 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
907 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
908
909 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
910 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
911 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
912
913 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
914 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
915 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
918 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
919 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
920 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
921
922 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
923
924 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
925
926 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
927 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
928 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
929 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
930 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
931
932 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
933 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
934 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
935 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
936
937 /*
938 * We must clear the FCS and FIFO error count.
939 * These registers are cleared on read,
940 * so we may pass a useless variable to store the value.
941 */
942 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
943 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
944
945 return 0;
946}
947
2b08da3f 948static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 949{
950 unsigned int i;
95ea3627
ID		 951 u8 value;
952
953 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
954 rt2500pci_bbp_read(rt2x00dev, 0, &value);
955 if ((value != 0xff) && (value != 0x00))
2b08da3f 956 return 0;
95ea3627
ID		 957 udelay(REGISTER_BUSY_DELAY);
958 }
959
960 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
961 return -EACCES;
2b08da3f
ID		 962}
963
964static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
965{
966 unsigned int i;
967 u16 eeprom;
968 u8 reg_id;
969 u8 value;
970
971 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
972 return -EACCES;
95ea3627 973
95ea3627
ID		 974 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
975 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
976 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
977 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
978 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
979 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
980 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
981 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
982 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
984 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
986 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
987 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
988 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
989 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
990 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
991 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
992 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
993 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
994 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
995 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
996 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
997 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
998 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
999 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1001 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1003 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1004
95ea3627
ID		 1005 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1006 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1007
1008 if (eeprom != 0xffff && eeprom != 0x0000) {
1009 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1010 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1011 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1012 }
1013 }
95ea3627
ID		 1014
1015 return 0;
1016}
1017
1018/*
1019 * Device state switch handlers.
1020 */
1021static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1022 enum dev_state state)
1023{
1024 u32 reg;
1025
1026 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1027 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 1028 (state == STATE_RADIO_RX_OFF) ||
1029 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1030 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1031}
1032
1033static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1034 enum dev_state state)
1035{
78e256c9
HS		 1036 int mask = (state == STATE_RADIO_IRQ_OFF) ||
1037 (state == STATE_RADIO_IRQ_OFF_ISR);
95ea3627
ID		 1038 u32 reg;
1039
1040 /*
1041 * When interrupts are being enabled, the interrupt registers
1042 * should clear the register to assure a clean state.
1043 */
1044 if (state == STATE_RADIO_IRQ_ON) {
1045 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1047 }
1048
1049 /*
1050 * Only toggle the interrupts bits we are going to use.
1051 * Non-checked interrupt bits are disabled by default.
1052 */
1053 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1054 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1055 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1056 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1058 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1059 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1060}
1061
1062static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1063{
1064 /*
1065 * Initialize all registers.
1066 */
2b08da3f
ID		 1067 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1068 rt2500pci_init_registers(rt2x00dev) ||
1069 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1070 return -EIO;
95ea3627 1071
95ea3627
ID		 1072 return 0;
1073}
1074
1075static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1076{
95ea3627 1077 /*
a2c9b652 1078 * Disable power
95ea3627 1079 */
a2c9b652 1080 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1081}
1082
1083static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1084 enum dev_state state)
1085{
9655a6ec 1086 u32 reg, reg2;
95ea3627
ID		 1087 unsigned int i;
1088 char put_to_sleep;
1089 char bbp_state;
1090 char rf_state;
1091
1092 put_to_sleep = (state != STATE_AWAKE);
1093
1094 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1095 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1096 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1097 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1098 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1099 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1100
1101 /*
1102 * Device is not guaranteed to be in the requested state yet.
1103 * We must wait until the register indicates that the
1104 * device has entered the correct state.
1105 */
1106 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1107 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1108 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1109 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1110 if (bbp_state == state && rf_state == state)
1111 return 0;
9655a6ec 1112 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1113 msleep(10);
1114 }
1115
95ea3627
ID		 1116 return -EBUSY;
1117}
1118
1119static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1120 enum dev_state state)
1121{
1122 int retval = 0;
1123
1124 switch (state) {
1125 case STATE_RADIO_ON:
1126 retval = rt2500pci_enable_radio(rt2x00dev);
1127 break;
1128 case STATE_RADIO_OFF:
1129 rt2500pci_disable_radio(rt2x00dev);
1130 break;
1131 case STATE_RADIO_RX_ON:
61667d8d 1132 case STATE_RADIO_RX_ON_LINK:
95ea3627 1133 case STATE_RADIO_RX_OFF:
61667d8d 1134 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1135 rt2500pci_toggle_rx(rt2x00dev, state);
1136 break;
1137 case STATE_RADIO_IRQ_ON:
78e256c9 1138 case STATE_RADIO_IRQ_ON_ISR:
2b08da3f 1139 case STATE_RADIO_IRQ_OFF:
78e256c9 1140 case STATE_RADIO_IRQ_OFF_ISR:
2b08da3f 1141 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1142 break;
1143 case STATE_DEEP_SLEEP:
1144 case STATE_SLEEP:
1145 case STATE_STANDBY:
1146 case STATE_AWAKE:
1147 retval = rt2500pci_set_state(rt2x00dev, state);
1148 break;
1149 default:
1150 retval = -ENOTSUPP;
1151 break;
1152 }
1153
2b08da3f
ID		 1154 if (unlikely(retval))
1155 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1156 state, retval);
1157
95ea3627
ID		 1158 return retval;
1159}
1160
1161/*
1162 * TX descriptor initialization
1163 */
93331458 1164static void rt2500pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1165 struct txentry_desc *txdesc)
95ea3627 1166{
93331458
ID		 1167 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1168 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1169 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1170 u32 word;
1171
1172 /*
1173 * Start writing the descriptor words.
1174 */
85b7a8b3 1175 rt2x00_desc_read(txd, 1, &word);
c4da0048 1176 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1177 rt2x00_desc_write(txd, 1, word);
4de36fe5 1178
95ea3627
ID		 1179 rt2x00_desc_read(txd, 2, &word);
1180 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1181 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1182 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1183 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1184 rt2x00_desc_write(txd, 2, word);
1185
1186 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1187 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1191 rt2x00_desc_write(txd, 3, word);
1192
1193 rt2x00_desc_read(txd, 10, &word);
1194 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1195 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1196 rt2x00_desc_write(txd, 10, word);
1197
e01f1ec3
GW		 1198 /*
1199 * Writing TXD word 0 must the last to prevent a race condition with
1200 * the device, whereby the device may take hold of the TXD before we
1201 * finished updating it.
1202 */
95ea3627
ID		 1203 rt2x00_desc_read(txd, 0, &word);
1204 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1205 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1206 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1207 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1208 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1209 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1210 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1211 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1212 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1213 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1214 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1215 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1216 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1217 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
df624ca5 1218 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1220 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1221
1222 /*
1223 * Register descriptor details in skb frame descriptor.
1224 */
1225 skbdesc->desc = txd;
1226 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1227}
1228
1229/*
1230 * TX data initialization
1231 */
f224f4ef
GW		 1232static void rt2500pci_write_beacon(struct queue_entry *entry,
1233 struct txentry_desc *txdesc)
bd88a781
ID		 1234{
1235 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1236 u32 reg;
1237
1238 /*
1239 * Disable beaconing while we are reloading the beacon data,
1240 * otherwise we might be sending out invalid data.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1243 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1244 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1245
bd88a781
ID		 1246 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1247
5c3b685c
GW		 1248 /*
1249 * Write the TX descriptor for the beacon.
1250 */
93331458 1251 rt2500pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1252
1253 /*
1254 * Dump beacon to userspace through debugfs.
1255 */
1256 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
d61cb266
GW		 1257
1258 /*
1259 * Enable beaconing again.
1260 */
1261 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1262 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1263 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1264 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1265}
1266
93331458 1267static void rt2500pci_kick_tx_queue(struct data_queue *queue)
95ea3627 1268{
93331458 1269 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
95ea3627
ID		 1270 u32 reg;
1271
95ea3627 1272 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
93331458
ID		 1273 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE));
1274 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK));
1275 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM));
95ea3627
ID		 1276 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1277}
1278
93331458 1279static void rt2500pci_kill_tx_queue(struct data_queue *queue)
a2c9b652 1280{
93331458 1281 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
a2c9b652
ID		 1282 u32 reg;
1283
93331458 1284 if (queue->qid == QID_BEACON) {
a2c9b652
ID		 1285 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1286 } else {
1287 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1288 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1289 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1290 }
1291}
1292
95ea3627
ID		 1293/*
1294 * RX control handlers
1295 */
181d6902
ID		 1296static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1297 struct rxdone_entry_desc *rxdesc)
95ea3627 1298{
b8be63ff 1299 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1300 u32 word0;
1301 u32 word2;
1302
b8be63ff
ID		 1303 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1304 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1305
4150c572 1306 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1307 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1308 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1309 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1310
89993890
ID		 1311 /*
1312 * Obtain the status about this packet.
1313 * When frame was received with an OFDM bitrate,
1314 * the signal is the PLCP value. If it was received with
1315 * a CCK bitrate the signal is the rate in 100kbit/s.
1316 */
181d6902
ID		 1317 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1318 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1319 entry->queue->rt2x00dev->rssi_offset;
181d6902 1320 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1321
19d30e02
ID		 1322 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1323 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1324 else
1325 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1326 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1327 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1328}
1329
1330/*
1331 * Interrupt functions.
1332 */
181d6902 1333static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1334 const enum data_queue_qid queue_idx)
95ea3627 1335{
181d6902 1336 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1337 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1338 struct queue_entry *entry;
1339 struct txdone_entry_desc txdesc;
95ea3627 1340 u32 word;
95ea3627 1341
181d6902
ID		 1342 while (!rt2x00queue_empty(queue)) {
1343 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1344 entry_priv = entry->priv_data;
1345 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1346
1347 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1348 !rt2x00_get_field32(word, TXD_W0_VALID))
1349 break;
1350
1351 /*
1352 * Obtain the status about this packet.
1353 */
fb55f4d1
ID		 1354 txdesc.flags = 0;
1355 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1356 case 0: /* Success */
1357 case 1: /* Success with retry */
1358 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1359 break;
1360 case 2: /* Failure, excessive retries */
1361 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1362 /* Don't break, this is a failed frame! */
1363 default: /* Failure */
1364 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1365 }
181d6902 1366 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1367
e513a0b6 1368 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1369 }
95ea3627
ID		 1370}
1371
78e256c9 1372static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance)
95ea3627
ID		 1373{
1374 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9 1375 u32 reg = rt2x00dev->irqvalue[0];
95ea3627
ID		 1376
1377 /*
1378 * Handle interrupts, walk through all bits
1379 * and run the tasks, the bits are checked in order of
1380 * priority.
1381 */
1382
1383 /*
1384 * 1 - Beacon timer expired interrupt.
1385 */
1386 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1387 rt2x00lib_beacondone(rt2x00dev);
1388
1389 /*
1390 * 2 - Rx ring done interrupt.
1391 */
1392 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1393 rt2x00pci_rxdone(rt2x00dev);
1394
1395 /*
1396 * 3 - Atim ring transmit done interrupt.
1397 */
1398 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1399 rt2500pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1400
1401 /*
1402 * 4 - Priority ring transmit done interrupt.
1403 */
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1405 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1406
1407 /*
1408 * 5 - Tx ring transmit done interrupt.
1409 */
1410 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1411 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627 1412
78e256c9
HS		 1413 /* Enable interrupts again. */
1414 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1415 STATE_RADIO_IRQ_ON_ISR);
1416
95ea3627
ID		 1417 return IRQ_HANDLED;
1418}
1419
78e256c9
HS		 1420static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1421{
1422 struct rt2x00_dev *rt2x00dev = dev_instance;
1423 u32 reg;
1424
1425 /*
1426 * Get the interrupt sources & saved to local variable.
1427 * Write register value back to clear pending interrupts.
1428 */
1429 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1430 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1431
1432 if (!reg)
1433 return IRQ_NONE;
1434
1435 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1436 return IRQ_HANDLED;
1437
1438 /* Store irqvalues for use in the interrupt thread. */
1439 rt2x00dev->irqvalue[0] = reg;
1440
1441 /* Disable interrupts, will be enabled again in the interrupt thread. */
1442 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1443 STATE_RADIO_IRQ_OFF_ISR);
1444
1445 return IRQ_WAKE_THREAD;
1446}
1447
95ea3627
ID		 1448/*
1449 * Device probe functions.
1450 */
1451static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1452{
1453 struct eeprom_93cx6 eeprom;
1454 u32 reg;
1455 u16 word;
1456 u8 *mac;
1457
1458 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1459
1460 eeprom.data = rt2x00dev;
1461 eeprom.register_read = rt2500pci_eepromregister_read;
1462 eeprom.register_write = rt2500pci_eepromregister_write;
1463 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1464 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1465 eeprom.reg_data_in = 0;
1466 eeprom.reg_data_out = 0;
1467 eeprom.reg_data_clock = 0;
1468 eeprom.reg_chip_select = 0;
1469
1470 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1471 EEPROM_SIZE / sizeof(u16));
1472
1473 /*
1474 * Start validation of the data that has been read.
1475 */
1476 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1477 if (!is_valid_ether_addr(mac)) {
1478 random_ether_addr(mac);
e174961c 1479 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1480 }
1481
1482 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1483 if (word == 0xffff) {
1484 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1485 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1486 ANTENNA_SW_DIVERSITY);
1487 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1488 ANTENNA_SW_DIVERSITY);
1489 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1490 LED_MODE_DEFAULT);
95ea3627
ID		 1491 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1492 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1493 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1494 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1495 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1496 }
1497
1498 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1499 if (word == 0xffff) {
1500 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1501 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1502 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1503 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1504 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1505 }
1506
1507 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1508 if (word == 0xffff) {
1509 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1510 DEFAULT_RSSI_OFFSET);
1511 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1512 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1513 }
1514
1515 return 0;
1516}
1517
1518static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1519{
1520 u32 reg;
1521 u16 value;
1522 u16 eeprom;
1523
1524 /*
1525 * Read EEPROM word for configuration.
1526 */
1527 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1528
1529 /*
1530 * Identify RF chipset.
1531 */
1532 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1533 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1534 rt2x00_set_chip(rt2x00dev, RT2560, value,
1535 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1536
5122d898
GW		 1537 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1538 !rt2x00_rf(rt2x00dev, RF2523) &&
1539 !rt2x00_rf(rt2x00dev, RF2524) &&
1540 !rt2x00_rf(rt2x00dev, RF2525) &&
1541 !rt2x00_rf(rt2x00dev, RF2525E) &&
1542 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1543 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1544 return -ENODEV;
1545 }
1546
1547 /*
1548 * Identify default antenna configuration.
1549 */
addc81bd 1550 rt2x00dev->default_ant.tx =
95ea3627 1551 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1552 rt2x00dev->default_ant.rx =
95ea3627
ID		 1553 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1554
1555 /*
1556 * Store led mode, for correct led behaviour.
1557 */
771fd565 1558#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1559 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1560
475433be 1561 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1562 if (value == LED_MODE_TXRX_ACTIVITY ||
1563 value == LED_MODE_DEFAULT ||
1564 value == LED_MODE_ASUS)
475433be
ID		 1565 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1566 LED_TYPE_ACTIVITY);
771fd565 1567#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1568
1569 /*
1570 * Detect if this device has an hardware controlled radio.
1571 */
1572 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1573 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1574
1575 /*
1576 * Check if the BBP tuning should be enabled.
1577 */
1578 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
27df2a9c
ID		 1579 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1580 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 1581
1582 /*
1583 * Read the RSSI <-> dBm offset information.
1584 */
1585 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1586 rt2x00dev->rssi_offset =
1587 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1588
1589 return 0;
1590}
1591
1592/*
1593 * RF value list for RF2522
1594 * Supports: 2.4 GHz
1595 */
1596static const struct rf_channel rf_vals_bg_2522[] = {
1597 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1598 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1599 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1600 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1601 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1602 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1603 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1604 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1605 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1606 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1607 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1608 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1609 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1610 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1611};
1612
1613/*
1614 * RF value list for RF2523
1615 * Supports: 2.4 GHz
1616 */
1617static const struct rf_channel rf_vals_bg_2523[] = {
1618 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1619 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1620 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1621 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1622 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1623 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1624 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1625 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1626 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1627 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1628 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1629 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1630 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1631 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1632};
1633
1634/*
1635 * RF value list for RF2524
1636 * Supports: 2.4 GHz
1637 */
1638static const struct rf_channel rf_vals_bg_2524[] = {
1639 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1640 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1641 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1642 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1643 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1644 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1645 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1646 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1647 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1648 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1649 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1650 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1651 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1652 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1653};
1654
1655/*
1656 * RF value list for RF2525
1657 * Supports: 2.4 GHz
1658 */
1659static const struct rf_channel rf_vals_bg_2525[] = {
1660 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1661 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1662 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1663 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1664 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1665 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1666 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1667 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1668 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1669 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1670 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1671 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1672 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1673 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1674};
1675
1676/*
1677 * RF value list for RF2525e
1678 * Supports: 2.4 GHz
1679 */
1680static const struct rf_channel rf_vals_bg_2525e[] = {
1681 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1682 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1683 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1684 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1685 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1686 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1687 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1688 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1689 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1690 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1691 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1692 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1693 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1694 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1695};
1696
1697/*
1698 * RF value list for RF5222
1699 * Supports: 2.4 GHz & 5.2 GHz
1700 */
1701static const struct rf_channel rf_vals_5222[] = {
1702 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1703 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1704 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1705 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1706 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1707 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1708 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1709 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1710 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1711 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1712 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1713 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1714 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1715 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1716
1717 /* 802.11 UNI / HyperLan 2 */
1718 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1719 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1720 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1721 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1722 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1723 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1724 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1725 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1726
1727 /* 802.11 HyperLan 2 */
1728 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1729 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1730 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1731 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1732 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1733 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1734 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1735 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1736 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1737 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1738
1739 /* 802.11 UNII */
1740 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1741 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1742 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1743 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1744 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1745};
1746
8c5e7a5f 1747static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1748{
1749 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1750 struct channel_info *info;
1751 char *tx_power;
95ea3627
ID		 1752 unsigned int i;
1753
1754 /*
1755 * Initialize all hw fields.
1756 */
566bfe5a 1757 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1758 IEEE80211_HW_SIGNAL_DBM |
1759 IEEE80211_HW_SUPPORTS_PS |
1760 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1761
14a3bf89 1762 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1763 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1764 rt2x00_eeprom_addr(rt2x00dev,
1765 EEPROM_MAC_ADDR_0));
1766
95ea3627
ID		 1767 /*
1768 * Initialize hw_mode information.
1769 */
31562e80
ID		 1770 spec->supported_bands = SUPPORT_BAND_2GHZ;
1771 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1772
5122d898 1773 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1774 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1775 spec->channels = rf_vals_bg_2522;
5122d898 1776 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1777 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1778 spec->channels = rf_vals_bg_2523;
5122d898 1779 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1780 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1781 spec->channels = rf_vals_bg_2524;
5122d898 1782 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1783 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1784 spec->channels = rf_vals_bg_2525;
5122d898 1785 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1786 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1787 spec->channels = rf_vals_bg_2525e;
5122d898 1788 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1789 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1790 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1791 spec->channels = rf_vals_5222;
95ea3627 1792 }
8c5e7a5f
ID		 1793
1794 /*
1795 * Create channel information array
1796 */
1797 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1798 if (!info)
1799 return -ENOMEM;
1800
1801 spec->channels_info = info;
1802
1803 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1804 for (i = 0; i < 14; i++) {
1805 info[i].max_power = MAX_TXPOWER;
1806 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1807 }
8c5e7a5f
ID		 1808
1809 if (spec->num_channels > 14) {
8d1331b3
ID		 1810 for (i = 14; i < spec->num_channels; i++) {
1811 info[i].max_power = MAX_TXPOWER;
1812 info[i].default_power1 = DEFAULT_TXPOWER;
1813 }
8c5e7a5f
ID		 1814 }
1815
1816 return 0;
95ea3627
ID		 1817}
1818
1819static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1820{
1821 int retval;
1822
1823 /*
1824 * Allocate eeprom data.
1825 */
1826 retval = rt2500pci_validate_eeprom(rt2x00dev);
1827 if (retval)
1828 return retval;
1829
1830 retval = rt2500pci_init_eeprom(rt2x00dev);
1831 if (retval)
1832 return retval;
1833
1834 /*
1835 * Initialize hw specifications.
1836 */
8c5e7a5f
ID		 1837 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1838 if (retval)
1839 return retval;
95ea3627
ID		 1840
1841 /*
c4da0048 1842 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1843 */
181d6902 1844 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1845 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1846
1847 /*
1848 * Set the rssi offset.
1849 */
1850 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1851
1852 return 0;
1853}
1854
1855/*
1856 * IEEE80211 stack callback functions.
1857 */
95ea3627
ID		 1858static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1859{
1860 struct rt2x00_dev *rt2x00dev = hw->priv;
1861 u64 tsf;
1862 u32 reg;
1863
1864 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1865 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1866 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1867 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1868
1869 return tsf;
1870}
1871
95ea3627
ID		 1872static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1873{
1874 struct rt2x00_dev *rt2x00dev = hw->priv;
1875 u32 reg;
1876
1877 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1878 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1879}
1880
1881static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1882 .tx = rt2x00mac_tx,
4150c572
JB		 1883 .start = rt2x00mac_start,
1884 .stop = rt2x00mac_stop,
95ea3627
ID		 1885 .add_interface = rt2x00mac_add_interface,
1886 .remove_interface = rt2x00mac_remove_interface,
1887 .config = rt2x00mac_config,
3a643d24 1888 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1889 .sw_scan_start = rt2x00mac_sw_scan_start,
1890 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1891 .get_stats = rt2x00mac_get_stats,
471b3efd 1892 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1893 .conf_tx = rt2x00mac_conf_tx,
95ea3627 1894 .get_tsf = rt2500pci_get_tsf,
95ea3627 1895 .tx_last_beacon = rt2500pci_tx_last_beacon,
e47a5cdd 1896 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1897};
1898
1899static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1900 .irq_handler = rt2500pci_interrupt,
78e256c9 1901 .irq_handler_thread = rt2500pci_interrupt_thread,
95ea3627
ID		 1902 .probe_hw = rt2500pci_probe_hw,
1903 .initialize = rt2x00pci_initialize,
1904 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1905 .get_entry_state = rt2500pci_get_entry_state,
1906 .clear_entry = rt2500pci_clear_entry,
95ea3627 1907 .set_device_state = rt2500pci_set_device_state,
95ea3627 1908 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1909 .link_stats = rt2500pci_link_stats,
1910 .reset_tuner = rt2500pci_reset_tuner,
1911 .link_tuner = rt2500pci_link_tuner,
1912 .write_tx_desc = rt2500pci_write_tx_desc,
bd88a781 1913 .write_beacon = rt2500pci_write_beacon,
95ea3627 1914 .kick_tx_queue = rt2500pci_kick_tx_queue,
a2c9b652 1915 .kill_tx_queue = rt2500pci_kill_tx_queue,
95ea3627 1916 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1917 .config_filter = rt2500pci_config_filter,
6bb40dd1 1918 .config_intf = rt2500pci_config_intf,
72810379 1919 .config_erp = rt2500pci_config_erp,
e4ea1c40 1920 .config_ant = rt2500pci_config_ant,
95ea3627
ID		 1921 .config = rt2500pci_config,
1922};
1923
181d6902
ID		 1924static const struct data_queue_desc rt2500pci_queue_rx = {
1925 .entry_num = RX_ENTRIES,
1926 .data_size = DATA_FRAME_SIZE,
1927 .desc_size = RXD_DESC_SIZE,
b8be63ff 1928 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1929};
1930
1931static const struct data_queue_desc rt2500pci_queue_tx = {
1932 .entry_num = TX_ENTRIES,
1933 .data_size = DATA_FRAME_SIZE,
1934 .desc_size = TXD_DESC_SIZE,
b8be63ff 1935 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1936};
1937
1938static const struct data_queue_desc rt2500pci_queue_bcn = {
1939 .entry_num = BEACON_ENTRIES,
1940 .data_size = MGMT_FRAME_SIZE,
1941 .desc_size = TXD_DESC_SIZE,
b8be63ff 1942 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1943};
1944
1945static const struct data_queue_desc rt2500pci_queue_atim = {
1946 .entry_num = ATIM_ENTRIES,
1947 .data_size = DATA_FRAME_SIZE,
1948 .desc_size = TXD_DESC_SIZE,
b8be63ff 1949 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1950};
1951
95ea3627 1952static const struct rt2x00_ops rt2500pci_ops = {
04d0362e
GW		 1953 .name = KBUILD_MODNAME,
1954 .max_sta_intf = 1,
1955 .max_ap_intf = 1,
1956 .eeprom_size = EEPROM_SIZE,
1957 .rf_size = RF_SIZE,
1958 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1959 .extra_tx_headroom = 0,
04d0362e
GW		 1960 .rx = &rt2500pci_queue_rx,
1961 .tx = &rt2500pci_queue_tx,
1962 .bcn = &rt2500pci_queue_bcn,
1963 .atim = &rt2500pci_queue_atim,
1964 .lib = &rt2500pci_rt2x00_ops,
1965 .hw = &rt2500pci_mac80211_ops,
95ea3627 1966#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1967 .debugfs = &rt2500pci_rt2x00debug,
95ea3627
ID		 1968#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1969};
1970
1971/*
1972 * RT2500pci module information.
1973 */
a3aa1884 1974static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
95ea3627
ID		 1975 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1976 { 0, }
1977};
1978
1979MODULE_AUTHOR(DRV_PROJECT);
1980MODULE_VERSION(DRV_VERSION);
1981MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1982MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1983MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1984MODULE_LICENSE("GPL");
1985
1986static struct pci_driver rt2500pci_driver = {
2360157c 1987 .name = KBUILD_MODNAME,
95ea3627
ID		 1988 .id_table = rt2500pci_device_table,
1989 .probe = rt2x00pci_probe,
1990 .remove = __devexit_p(rt2x00pci_remove),
1991 .suspend = rt2x00pci_suspend,
1992 .resume = rt2x00pci_resume,
1993};
1994
1995static int __init rt2500pci_init(void)
1996{
1997 return pci_register_driver(&rt2500pci_driver);
1998}
1999
2000static void __exit rt2500pci_exit(void)
2001{
2002 pci_unregister_driver(&rt2500pci_driver);
2003}
2004
2005module_init(rt2500pci_init);
2006module_exit(rt2500pci_exit);
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