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rt2x00: Fix beacon descriptor writing for rt61pci.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
c9c3b1a5
ID		 52#define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54#define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 56
0e14f6d3 57static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 58 const unsigned int word, const u8 value)
59{
60 u32 reg;
61
8ff48a8b
ID		 62 mutex_lock(&rt2x00dev->csr_mutex);
63
95ea3627 64 /*
c9c3b1a5
ID		 65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
95ea3627 67 */
c9c3b1a5
ID		 68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
8ff48a8b 77
8ff48a8b 78 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 79}
80
0e14f6d3 81static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 82 const unsigned int word, u8 *value)
83{
84 u32 reg;
85
8ff48a8b
ID		 86 mutex_lock(&rt2x00dev->csr_mutex);
87
95ea3627 88 /*
c9c3b1a5
ID		 89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95ea3627 95 */
c9c3b1a5
ID		 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 101
c9c3b1a5 102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 103
c9c3b1a5
ID		 104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
95ea3627
ID		 106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 108
109 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 110}
111
0e14f6d3 112static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 113 const unsigned int word, const u32 value)
114{
115 u32 reg;
95ea3627 116
8ff48a8b
ID		 117 mutex_lock(&rt2x00dev->csr_mutex);
118
c9c3b1a5
ID		 119 /*
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
122 */
123 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124 reg = 0;
125 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 132 }
133
8ff48a8b 134 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 135}
136
137static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138{
139 struct rt2x00_dev *rt2x00dev = eeprom->data;
140 u32 reg;
141
142 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146 eeprom->reg_data_clock =
147 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148 eeprom->reg_chip_select =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150}
151
152static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153{
154 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 u32 reg = 0;
156
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160 !!eeprom->reg_data_clock);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162 !!eeprom->reg_chip_select);
163
164 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165}
166
167#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 168static const struct rt2x00debug rt2500pci_rt2x00debug = {
169 .owner = THIS_MODULE,
170 .csr = {
743b97ca
ID		 171 .read = rt2x00pci_register_read,
172 .write = rt2x00pci_register_write,
173 .flags = RT2X00DEBUGFS_OFFSET,
174 .word_base = CSR_REG_BASE,
95ea3627
ID		 175 .word_size = sizeof(u32),
176 .word_count = CSR_REG_SIZE / sizeof(u32),
177 },
178 .eeprom = {
179 .read = rt2x00_eeprom_read,
180 .write = rt2x00_eeprom_write,
743b97ca 181 .word_base = EEPROM_BASE,
95ea3627
ID		 182 .word_size = sizeof(u16),
183 .word_count = EEPROM_SIZE / sizeof(u16),
184 },
185 .bbp = {
186 .read = rt2500pci_bbp_read,
187 .write = rt2500pci_bbp_write,
743b97ca 188 .word_base = BBP_BASE,
95ea3627
ID		 189 .word_size = sizeof(u8),
190 .word_count = BBP_SIZE / sizeof(u8),
191 },
192 .rf = {
193 .read = rt2x00_rf_read,
194 .write = rt2500pci_rf_write,
743b97ca 195 .word_base = RF_BASE,
95ea3627
ID		 196 .word_size = sizeof(u32),
197 .word_count = RF_SIZE / sizeof(u32),
198 },
199};
200#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
95ea3627
ID		 202static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203{
204 u32 reg;
205
206 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
207 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208}
95ea3627 209
771fd565 210#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 211static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 212 enum led_brightness brightness)
213{
214 struct rt2x00_led *led =
215 container_of(led_cdev, struct rt2x00_led, led_dev);
216 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 217 u32 reg;
218
219 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
220
a2e1d52a 221 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 222 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 223 else if (led->type == LED_TYPE_ACTIVITY)
224 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 225
226 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227}
a2e1d52a
ID		 228
229static int rt2500pci_blink_set(struct led_classdev *led_cdev,
230 unsigned long *delay_on,
231 unsigned long *delay_off)
232{
233 struct rt2x00_led *led =
234 container_of(led_cdev, struct rt2x00_led, led_dev);
235 u32 reg;
236
237 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
238 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
239 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
240 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242 return 0;
243}
475433be
ID		 244
245static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
246 struct rt2x00_led *led,
247 enum led_type type)
248{
249 led->rt2x00dev = rt2x00dev;
250 led->type = type;
251 led->led_dev.brightness_set = rt2500pci_brightness_set;
252 led->led_dev.blink_set = rt2500pci_blink_set;
253 led->flags = LED_INITIALIZED;
254}
771fd565 255#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 256
95ea3627
ID		 257/*
258 * Configuration handlers.
259 */
3a643d24
ID		 260static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 const unsigned int filter_flags)
262{
263 u32 reg;
264
265 /*
266 * Start configuration steps.
267 * Note that the version error will always be dropped
268 * and broadcast frames will always be accepted since
269 * there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
285 !(filter_flags & FIF_ALLMULTI));
286 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
287 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
288}
289
6bb40dd1
ID		 290static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
291 struct rt2x00_intf *intf,
292 struct rt2x00intf_conf *conf,
293 const unsigned int flags)
95ea3627 294{
e58c6aca 295 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
6bb40dd1 296 unsigned int bcn_preload;
95ea3627
ID		 297 u32 reg;
298
6bb40dd1 299 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 300 /*
301 * Enable beacon config
302 */
bad13639 303 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 304 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
305 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
306 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
307 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 308
6bb40dd1
ID		 309 /*
310 * Enable synchronisation.
311 */
312 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 313 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 315 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 316 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
317 }
318
319 if (flags & CONFIG_UPDATE_MAC)
320 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
321 conf->mac, sizeof(conf->mac));
322
323 if (flags & CONFIG_UPDATE_BSSID)
324 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
325 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 326}
327
3a643d24
ID		 328static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
329 struct rt2x00lib_erp *erp)
95ea3627 330{
5c58ee51 331 int preamble_mask;
95ea3627 332 u32 reg;
95ea3627 333
5c58ee51
ID		 334 /*
335 * When short preamble is enabled, we should set bit 0x08
336 */
72810379 337 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 338
339 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
4789666e
ID		 340 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
341 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
8a566afe
ID		 342 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
343 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
95ea3627
ID		 344 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
345
95ea3627 346 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 347 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627 348 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
bad13639 349 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
95ea3627
ID		 350 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
351
352 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 353 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627 354 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
bad13639 355 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
95ea3627
ID		 356 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
357
358 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 359 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627 360 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
bad13639 361 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
95ea3627
ID		 362 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
363
364 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 365 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627 366 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
bad13639 367 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
95ea3627 368 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
e4ea1c40
ID		 369
370 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
371
372 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
373 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
374 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
375
8a566afe
ID		 376 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
377 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
378 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
379 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
380
e4ea1c40
ID		 381 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
382 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
383 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
384 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
385
386 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
387 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
388 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
389 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
95ea3627
ID		 390}
391
e4ea1c40
ID		 392static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
393 struct antenna_setup *ant)
95ea3627 394{
e4ea1c40
ID		 395 u32 reg;
396 u8 r14;
397 u8 r2;
398
399 /*
400 * We should never come here because rt2x00lib is supposed
401 * to catch this and send us the correct antenna explicitely.
402 */
403 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
404 ant->tx == ANTENNA_SW_DIVERSITY);
405
406 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
407 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
408 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
409
410 /*
411 * Configure the TX antenna.
412 */
413 switch (ant->tx) {
414 case ANTENNA_A:
415 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
416 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
417 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
418 break;
419 case ANTENNA_B:
420 default:
421 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
422 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
423 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
424 break;
425 }
426
427 /*
428 * Configure the RX antenna.
429 */
430 switch (ant->rx) {
431 case ANTENNA_A:
432 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
433 break;
434 case ANTENNA_B:
435 default:
436 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
437 break;
438 }
439
440 /*
441 * RT2525E and RT5222 need to flip TX I/Q
442 */
5122d898 443 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
e4ea1c40
ID		 444 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
445 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
446 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
447
448 /*
449 * RT2525E does not need RX I/Q Flip.
450 */
5122d898 451 if (rt2x00_rf(rt2x00dev, RF2525E))
e4ea1c40
ID		 452 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
453 } else {
454 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
455 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
456 }
457
458 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
459 rt2500pci_bbp_write(rt2x00dev, 14, r14);
460 rt2500pci_bbp_write(rt2x00dev, 2, r2);
95ea3627
ID		 461}
462
463static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 464 struct rf_channel *rf, const int txpower)
95ea3627 465{
95ea3627
ID		 466 u8 r70;
467
95ea3627
ID		 468 /*
469 * Set TXpower.
470 */
5c58ee51 471 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 472
473 /*
474 * Switch on tuning bits.
475 * For RT2523 devices we do not need to update the R1 register.
476 */
5122d898 477 if (!rt2x00_rf(rt2x00dev, RF2523))
5c58ee51
ID		 478 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
479 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 480
481 /*
482 * For RT2525 we should first set the channel to half band higher.
483 */
5122d898 484 if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 485 static const u32 vals[] = {
486 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
487 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
488 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
489 0x00080d2e, 0x00080d3a
490 };
491
5c58ee51
ID		 492 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
493 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
494 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
495 if (rf->rf4)
496 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 497 }
498
5c58ee51
ID		 499 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
500 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
501 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
502 if (rf->rf4)
503 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 504
505 /*
506 * Channel 14 requires the Japan filter bit to be set.
507 */
508 r70 = 0x46;
5c58ee51 509 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 510 rt2500pci_bbp_write(rt2x00dev, 70, r70);
511
512 msleep(1);
513
514 /*
515 * Switch off tuning bits.
516 * For RT2523 devices we do not need to update the R1 register.
517 */
5122d898 518 if (!rt2x00_rf(rt2x00dev, RF2523)) {
5c58ee51
ID		 519 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
520 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 521 }
522
5c58ee51
ID		 523 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
524 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 525
526 /*
527 * Clear false CRC during channel switch.
528 */
5c58ee51 529 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 530}
531
532static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
533 const int txpower)
534{
535 u32 rf3;
536
537 rt2x00_rf_read(rt2x00dev, 3, &rf3);
538 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
539 rt2500pci_rf_write(rt2x00dev, 3, rf3);
540}
541
e4ea1c40
ID		 542static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
543 struct rt2x00lib_conf *libconf)
95ea3627
ID		 544{
545 u32 reg;
95ea3627 546
e4ea1c40
ID		 547 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
548 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
549 libconf->conf->long_frame_max_tx_count);
550 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
551 libconf->conf->short_frame_max_tx_count);
552 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 553}
554
7d7f19cc
ID		 555static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
556 struct rt2x00lib_conf *libconf)
557{
558 enum dev_state state =
559 (libconf->conf->flags & IEEE80211_CONF_PS) ?
560 STATE_SLEEP : STATE_AWAKE;
561 u32 reg;
562
563 if (state == STATE_SLEEP) {
564 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
565 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 566 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 567 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
568 libconf->conf->listen_interval - 1);
569
570 /* We must first disable autowake before it can be enabled */
571 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
572 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
573
574 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
575 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 576 } else {
577 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
578 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
579 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 580 }
581
582 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
583}
584
95ea3627 585static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 586 struct rt2x00lib_conf *libconf,
587 const unsigned int flags)
95ea3627 588{
e4ea1c40 589 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 590 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
591 libconf->conf->power_level);
e4ea1c40
ID		 592 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
593 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 594 rt2500pci_config_txpower(rt2x00dev,
595 libconf->conf->power_level);
e4ea1c40
ID		 596 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
597 rt2500pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 598 if (flags & IEEE80211_CONF_CHANGE_PS)
599 rt2500pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 600}
601
95ea3627
ID		 602/*
603 * Link tuning
604 */
ebcf26da
ID		 605static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
606 struct link_qual *qual)
95ea3627
ID		 607{
608 u32 reg;
609
610 /*
611 * Update FCS error count from register.
612 */
613 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 614 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 615
616 /*
617 * Update False CCA count from register.
618 */
619 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 620 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 621}
622
5352ff65
ID		 623static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
624 struct link_qual *qual, u8 vgc_level)
eb20b4e8 625{
5352ff65 626 if (qual->vgc_level_reg != vgc_level) {
eb20b4e8 627 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65 628 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 629 }
630}
631
5352ff65
ID		 632static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
633 struct link_qual *qual)
95ea3627 634{
5352ff65 635 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
95ea3627
ID		 636}
637
5352ff65
ID		 638static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
639 struct link_qual *qual, const u32 count)
95ea3627 640{
95ea3627
ID		 641 /*
642 * To prevent collisions with MAC ASIC on chipsets
643 * up to version C the link tuning should halt after 20
6bb40dd1 644 * seconds while being associated.
95ea3627 645 */
5122d898 646 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
5352ff65 647 rt2x00dev->intf_associated && count > 20)
95ea3627
ID		 648 return;
649
95ea3627
ID		 650 /*
651 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 652 * to the dynamic CCA tuning. Chipset version D and higher
653 * should go straight to dynamic CCA tuning when they
654 * are not associated.
95ea3627 655 */
5122d898 656 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
6bb40dd1 657 !rt2x00dev->intf_associated)
95ea3627
ID		 658 goto dynamic_cca_tune;
659
660 /*
661 * A too low RSSI will cause too much false CCA which will
662 * then corrupt the R17 tuning. To remidy this the tuning should
663 * be stopped (While making sure the R17 value will not exceed limits)
664 */
5352ff65
ID		 665 if (qual->rssi < -80 && count > 20) {
666 if (qual->vgc_level_reg >= 0x41)
667 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 668 return;
669 }
670
671 /*
672 * Special big-R17 for short distance
673 */
5352ff65
ID		 674 if (qual->rssi >= -58) {
675 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
95ea3627
ID		 676 return;
677 }
678
679 /*
680 * Special mid-R17 for middle distance
681 */
5352ff65
ID		 682 if (qual->rssi >= -74) {
683 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
95ea3627
ID		 684 return;
685 }
686
687 /*
688 * Leave short or middle distance condition, restore r17
689 * to the dynamic tuning range.
690 */
5352ff65
ID		 691 if (qual->vgc_level_reg >= 0x41) {
692 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 693 return;
694 }
695
696dynamic_cca_tune:
697
698 /*
699 * R17 is inside the dynamic tuning range,
700 * start tuning the link based on the false cca counter.
701 */
5352ff65
ID		 702 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
703 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
704 qual->vgc_level = qual->vgc_level_reg;
705 } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
706 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
707 qual->vgc_level = qual->vgc_level_reg;
95ea3627
ID		 708 }
709}
710
711/*
712 * Initialization functions.
713 */
798b7adb 714static bool rt2500pci_get_entry_state(struct queue_entry *entry)
95ea3627 715{
b8be63ff 716 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 717 u32 word;
718
798b7adb
ID		 719 if (entry->queue->qid == QID_RX) {
720 rt2x00_desc_read(entry_priv->desc, 0, &word);
721
722 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
723 } else {
724 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 725
798b7adb
ID		 726 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
727 rt2x00_get_field32(word, TXD_W0_VALID));
728 }
95ea3627
ID		 729}
730
798b7adb 731static void rt2500pci_clear_entry(struct queue_entry *entry)
95ea3627 732{
b8be63ff 733 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 734 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 735 u32 word;
736
798b7adb
ID		 737 if (entry->queue->qid == QID_RX) {
738 rt2x00_desc_read(entry_priv->desc, 1, &word);
739 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
740 rt2x00_desc_write(entry_priv->desc, 1, word);
741
742 rt2x00_desc_read(entry_priv->desc, 0, &word);
743 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
744 rt2x00_desc_write(entry_priv->desc, 0, word);
745 } else {
746 rt2x00_desc_read(entry_priv->desc, 0, &word);
747 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
748 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
749 rt2x00_desc_write(entry_priv->desc, 0, word);
750 }
95ea3627
ID		 751}
752
181d6902 753static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 754{
b8be63ff 755 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 756 u32 reg;
757
95ea3627
ID		 758 /*
759 * Initialize registers.
760 */
761 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 762 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
763 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
765 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 766 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
767
b8be63ff 768 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 769 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 770 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 771 entry_priv->desc_dma);
95ea3627
ID		 772 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
773
b8be63ff 774 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 775 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 776 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 777 entry_priv->desc_dma);
95ea3627
ID		 778 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
779
b8be63ff 780 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 781 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 782 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 783 entry_priv->desc_dma);
95ea3627
ID		 784 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
785
b8be63ff 786 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 787 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 788 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 789 entry_priv->desc_dma);
95ea3627
ID		 790 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
791
792 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
793 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 794 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 795 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
796
b8be63ff 797 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 798 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 799 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
800 entry_priv->desc_dma);
95ea3627
ID		 801 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
802
803 return 0;
804}
805
806static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
807{
808 u32 reg;
809
810 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
813 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
814
815 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
816 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
817 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
818 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
819 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
820
821 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
822 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
823 rt2x00dev->rx->data_size / 128);
824 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
825
826 /*
827 * Always use CWmin and CWmax set in descriptor.
828 */
829 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
830 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
831 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
832
1f909162
ID		 833 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
834 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
835 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
836 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
837 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
838 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
839 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
840 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
841 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
842 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
843
95ea3627
ID		 844 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
845
846 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
847 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
852 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
853 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
854 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
855 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
856
857 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
858 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
859 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
860 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
861 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
862 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
863
864 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
865 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
866 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
867 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
868 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
869 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
870
871 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
872 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
873 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
874 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
875 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
876 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
877
878 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
879 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
884 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
885 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
886 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
887 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
888
889 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
890 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
891 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
892 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
893 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
894 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
895 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
896 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
897 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
898
899 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
900
901 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
902 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
903
904 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
905 return -EBUSY;
906
907 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
908 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
909
910 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
911 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
912 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
913
914 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
915 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
918 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
919 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
920 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
921 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
922
923 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
924
925 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
926
927 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
928 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
929 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
930 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
931 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
932
933 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
934 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
935 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
936 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
937
938 /*
939 * We must clear the FCS and FIFO error count.
940 * These registers are cleared on read,
941 * so we may pass a useless variable to store the value.
942 */
943 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
944 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
945
946 return 0;
947}
948
2b08da3f 949static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 950{
951 unsigned int i;
95ea3627
ID		 952 u8 value;
953
954 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
955 rt2500pci_bbp_read(rt2x00dev, 0, &value);
956 if ((value != 0xff) && (value != 0x00))
2b08da3f 957 return 0;
95ea3627
ID		 958 udelay(REGISTER_BUSY_DELAY);
959 }
960
961 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
962 return -EACCES;
2b08da3f
ID		 963}
964
965static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
966{
967 unsigned int i;
968 u16 eeprom;
969 u8 reg_id;
970 u8 value;
971
972 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
973 return -EACCES;
95ea3627 974
95ea3627
ID		 975 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
976 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
977 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
978 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
979 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
980 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
981 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
982 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
983 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
984 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
986 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
987 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
988 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
989 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
990 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
991 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
992 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
993 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
994 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
995 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
996 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
997 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
998 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
999 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1000 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1001 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1002 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1003 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1004 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1005
95ea3627
ID		 1006 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1007 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1008
1009 if (eeprom != 0xffff && eeprom != 0x0000) {
1010 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1011 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1012 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1013 }
1014 }
95ea3627
ID		 1015
1016 return 0;
1017}
1018
1019/*
1020 * Device state switch handlers.
1021 */
1022static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1023 enum dev_state state)
1024{
1025 u32 reg;
1026
1027 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1028 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 1029 (state == STATE_RADIO_RX_OFF) ||
1030 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1031 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1032}
1033
1034static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1035 enum dev_state state)
1036{
1037 int mask = (state == STATE_RADIO_IRQ_OFF);
1038 u32 reg;
1039
1040 /*
1041 * When interrupts are being enabled, the interrupt registers
1042 * should clear the register to assure a clean state.
1043 */
1044 if (state == STATE_RADIO_IRQ_ON) {
1045 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1047 }
1048
1049 /*
1050 * Only toggle the interrupts bits we are going to use.
1051 * Non-checked interrupt bits are disabled by default.
1052 */
1053 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1054 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1055 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1056 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1058 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1059 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1060}
1061
1062static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1063{
1064 /*
1065 * Initialize all registers.
1066 */
2b08da3f
ID		 1067 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1068 rt2500pci_init_registers(rt2x00dev) ||
1069 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1070 return -EIO;
95ea3627 1071
95ea3627
ID		 1072 return 0;
1073}
1074
1075static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1076{
95ea3627 1077 /*
a2c9b652 1078 * Disable power
95ea3627 1079 */
a2c9b652 1080 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1081}
1082
1083static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1084 enum dev_state state)
1085{
1086 u32 reg;
1087 unsigned int i;
1088 char put_to_sleep;
1089 char bbp_state;
1090 char rf_state;
1091
1092 put_to_sleep = (state != STATE_AWAKE);
1093
1094 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1095 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1096 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1097 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1098 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1099 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1100
1101 /*
1102 * Device is not guaranteed to be in the requested state yet.
1103 * We must wait until the register indicates that the
1104 * device has entered the correct state.
1105 */
1106 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1107 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1108 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1109 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1110 if (bbp_state == state && rf_state == state)
1111 return 0;
1112 msleep(10);
1113 }
1114
95ea3627
ID		 1115 return -EBUSY;
1116}
1117
1118static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1119 enum dev_state state)
1120{
1121 int retval = 0;
1122
1123 switch (state) {
1124 case STATE_RADIO_ON:
1125 retval = rt2500pci_enable_radio(rt2x00dev);
1126 break;
1127 case STATE_RADIO_OFF:
1128 rt2500pci_disable_radio(rt2x00dev);
1129 break;
1130 case STATE_RADIO_RX_ON:
61667d8d 1131 case STATE_RADIO_RX_ON_LINK:
95ea3627 1132 case STATE_RADIO_RX_OFF:
61667d8d 1133 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1134 rt2500pci_toggle_rx(rt2x00dev, state);
1135 break;
1136 case STATE_RADIO_IRQ_ON:
1137 case STATE_RADIO_IRQ_OFF:
1138 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1139 break;
1140 case STATE_DEEP_SLEEP:
1141 case STATE_SLEEP:
1142 case STATE_STANDBY:
1143 case STATE_AWAKE:
1144 retval = rt2500pci_set_state(rt2x00dev, state);
1145 break;
1146 default:
1147 retval = -ENOTSUPP;
1148 break;
1149 }
1150
2b08da3f
ID		 1151 if (unlikely(retval))
1152 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1153 state, retval);
1154
95ea3627
ID		 1155 return retval;
1156}
1157
1158/*
1159 * TX descriptor initialization
1160 */
1161static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1162 struct sk_buff *skb,
61486e0f 1163 struct txentry_desc *txdesc)
95ea3627 1164{
181d6902 1165 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1166 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1167 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1168 u32 word;
1169
1170 /*
1171 * Start writing the descriptor words.
1172 */
4de36fe5 1173 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1174 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1175 rt2x00_desc_write(entry_priv->desc, 1, word);
1176
95ea3627
ID		 1177 rt2x00_desc_read(txd, 2, &word);
1178 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1179 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1180 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1181 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1182 rt2x00_desc_write(txd, 2, word);
1183
1184 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1185 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1186 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1187 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1189 rt2x00_desc_write(txd, 3, word);
1190
1191 rt2x00_desc_read(txd, 10, &word);
1192 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1193 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1194 rt2x00_desc_write(txd, 10, word);
1195
1196 rt2x00_desc_read(txd, 0, &word);
1197 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1198 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1199 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1200 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1201 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1202 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1203 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1204 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1205 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1206 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1207 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1208 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1209 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1210 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
df624ca5 1211 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1212 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1213 rt2x00_desc_write(txd, 0, word);
1214}
1215
1216/*
1217 * TX data initialization
1218 */
f224f4ef
GW		 1219static void rt2500pci_write_beacon(struct queue_entry *entry,
1220 struct txentry_desc *txdesc)
bd88a781
ID		 1221{
1222 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1223 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1224 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1225 u32 word;
1226 u32 reg;
1227
1228 /*
1229 * Disable beaconing while we are reloading the beacon data,
1230 * otherwise we might be sending out invalid data.
1231 */
1232 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1233 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1234 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1235
1236 /*
1237 * Replace rt2x00lib allocated descriptor with the
1238 * pointer to the _real_ hardware descriptor.
1239 * After that, map the beacon to DMA and update the
1240 * descriptor.
1241 */
1242 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1243 skbdesc->desc = entry_priv->desc;
1244
1245 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1246
1247 rt2x00_desc_read(entry_priv->desc, 1, &word);
1248 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1249 rt2x00_desc_write(entry_priv->desc, 1, word);
d61cb266
GW		 1250
1251 /*
1252 * Enable beaconing again.
1253 */
1254 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1255 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1256 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1257 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1258}
1259
95ea3627 1260static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1261 const enum data_queue_qid queue)
95ea3627
ID		 1262{
1263 u32 reg;
1264
95ea3627 1265 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1266 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1267 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1268 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1269 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1270}
1271
a2c9b652
ID		 1272static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1273 const enum data_queue_qid qid)
1274{
1275 u32 reg;
1276
1277 if (qid == QID_BEACON) {
1278 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1279 } else {
1280 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1281 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1282 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1283 }
1284}
1285
95ea3627
ID		 1286/*
1287 * RX control handlers
1288 */
181d6902
ID		 1289static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1290 struct rxdone_entry_desc *rxdesc)
95ea3627 1291{
b8be63ff 1292 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1293 u32 word0;
1294 u32 word2;
1295
b8be63ff
ID		 1296 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1297 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1298
4150c572 1299 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1300 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1301 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1302 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1303
89993890
ID		 1304 /*
1305 * Obtain the status about this packet.
1306 * When frame was received with an OFDM bitrate,
1307 * the signal is the PLCP value. If it was received with
1308 * a CCK bitrate the signal is the rate in 100kbit/s.
1309 */
181d6902
ID		 1310 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1311 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1312 entry->queue->rt2x00dev->rssi_offset;
181d6902 1313 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1314
19d30e02
ID		 1315 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1316 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1317 else
1318 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1319 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1320 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1321}
1322
1323/*
1324 * Interrupt functions.
1325 */
181d6902 1326static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1327 const enum data_queue_qid queue_idx)
95ea3627 1328{
181d6902 1329 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1330 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1331 struct queue_entry *entry;
1332 struct txdone_entry_desc txdesc;
95ea3627 1333 u32 word;
95ea3627 1334
181d6902
ID		 1335 while (!rt2x00queue_empty(queue)) {
1336 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1337 entry_priv = entry->priv_data;
1338 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1339
1340 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1341 !rt2x00_get_field32(word, TXD_W0_VALID))
1342 break;
1343
1344 /*
1345 * Obtain the status about this packet.
1346 */
fb55f4d1
ID		 1347 txdesc.flags = 0;
1348 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1349 case 0: /* Success */
1350 case 1: /* Success with retry */
1351 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1352 break;
1353 case 2: /* Failure, excessive retries */
1354 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1355 /* Don't break, this is a failed frame! */
1356 default: /* Failure */
1357 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1358 }
181d6902 1359 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1360
d74f5ba4 1361 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1362 }
95ea3627
ID		 1363}
1364
1365static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1366{
1367 struct rt2x00_dev *rt2x00dev = dev_instance;
1368 u32 reg;
1369
1370 /*
1371 * Get the interrupt sources & saved to local variable.
1372 * Write register value back to clear pending interrupts.
1373 */
1374 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1375 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1376
1377 if (!reg)
1378 return IRQ_NONE;
1379
0262ab0d 1380 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1381 return IRQ_HANDLED;
1382
1383 /*
1384 * Handle interrupts, walk through all bits
1385 * and run the tasks, the bits are checked in order of
1386 * priority.
1387 */
1388
1389 /*
1390 * 1 - Beacon timer expired interrupt.
1391 */
1392 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1393 rt2x00lib_beacondone(rt2x00dev);
1394
1395 /*
1396 * 2 - Rx ring done interrupt.
1397 */
1398 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1399 rt2x00pci_rxdone(rt2x00dev);
1400
1401 /*
1402 * 3 - Atim ring transmit done interrupt.
1403 */
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1405 rt2500pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1406
1407 /*
1408 * 4 - Priority ring transmit done interrupt.
1409 */
1410 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1411 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1412
1413 /*
1414 * 5 - Tx ring transmit done interrupt.
1415 */
1416 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1417 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1418
1419 return IRQ_HANDLED;
1420}
1421
1422/*
1423 * Device probe functions.
1424 */
1425static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1426{
1427 struct eeprom_93cx6 eeprom;
1428 u32 reg;
1429 u16 word;
1430 u8 *mac;
1431
1432 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1433
1434 eeprom.data = rt2x00dev;
1435 eeprom.register_read = rt2500pci_eepromregister_read;
1436 eeprom.register_write = rt2500pci_eepromregister_write;
1437 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1438 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1439 eeprom.reg_data_in = 0;
1440 eeprom.reg_data_out = 0;
1441 eeprom.reg_data_clock = 0;
1442 eeprom.reg_chip_select = 0;
1443
1444 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1445 EEPROM_SIZE / sizeof(u16));
1446
1447 /*
1448 * Start validation of the data that has been read.
1449 */
1450 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1451 if (!is_valid_ether_addr(mac)) {
1452 random_ether_addr(mac);
e174961c 1453 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1454 }
1455
1456 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1457 if (word == 0xffff) {
1458 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1459 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1460 ANTENNA_SW_DIVERSITY);
1461 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1462 ANTENNA_SW_DIVERSITY);
1463 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1464 LED_MODE_DEFAULT);
95ea3627
ID		 1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1466 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1467 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1468 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1469 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1470 }
1471
1472 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1473 if (word == 0xffff) {
1474 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1475 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1476 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1477 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1478 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1479 }
1480
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1482 if (word == 0xffff) {
1483 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1484 DEFAULT_RSSI_OFFSET);
1485 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1486 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1487 }
1488
1489 return 0;
1490}
1491
1492static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1493{
1494 u32 reg;
1495 u16 value;
1496 u16 eeprom;
1497
1498 /*
1499 * Read EEPROM word for configuration.
1500 */
1501 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1502
1503 /*
1504 * Identify RF chipset.
1505 */
1506 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1507 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1508 rt2x00_set_chip(rt2x00dev, RT2560, value,
1509 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1510
5122d898
GW		 1511 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1512 !rt2x00_rf(rt2x00dev, RF2523) &&
1513 !rt2x00_rf(rt2x00dev, RF2524) &&
1514 !rt2x00_rf(rt2x00dev, RF2525) &&
1515 !rt2x00_rf(rt2x00dev, RF2525E) &&
1516 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1517 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1518 return -ENODEV;
1519 }
1520
1521 /*
1522 * Identify default antenna configuration.
1523 */
addc81bd 1524 rt2x00dev->default_ant.tx =
95ea3627 1525 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1526 rt2x00dev->default_ant.rx =
95ea3627
ID		 1527 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1528
1529 /*
1530 * Store led mode, for correct led behaviour.
1531 */
771fd565 1532#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1533 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1534
475433be 1535 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1536 if (value == LED_MODE_TXRX_ACTIVITY ||
1537 value == LED_MODE_DEFAULT ||
1538 value == LED_MODE_ASUS)
475433be
ID		 1539 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1540 LED_TYPE_ACTIVITY);
771fd565 1541#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1542
1543 /*
1544 * Detect if this device has an hardware controlled radio.
1545 */
1546 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1547 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1548
1549 /*
1550 * Check if the BBP tuning should be enabled.
1551 */
1552 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1553
1554 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1555 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1556
1557 /*
1558 * Read the RSSI <-> dBm offset information.
1559 */
1560 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1561 rt2x00dev->rssi_offset =
1562 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1563
1564 return 0;
1565}
1566
1567/*
1568 * RF value list for RF2522
1569 * Supports: 2.4 GHz
1570 */
1571static const struct rf_channel rf_vals_bg_2522[] = {
1572 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1573 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1574 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1575 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1576 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1577 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1578 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1579 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1580 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1581 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1582 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1583 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1584 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1585 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1586};
1587
1588/*
1589 * RF value list for RF2523
1590 * Supports: 2.4 GHz
1591 */
1592static const struct rf_channel rf_vals_bg_2523[] = {
1593 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1594 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1595 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1596 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1597 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1598 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1599 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1600 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1601 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1602 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1603 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1604 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1605 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1606 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1607};
1608
1609/*
1610 * RF value list for RF2524
1611 * Supports: 2.4 GHz
1612 */
1613static const struct rf_channel rf_vals_bg_2524[] = {
1614 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1615 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1616 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1617 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1618 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1619 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1620 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1621 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1622 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1623 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1624 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1625 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1626 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1627 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1628};
1629
1630/*
1631 * RF value list for RF2525
1632 * Supports: 2.4 GHz
1633 */
1634static const struct rf_channel rf_vals_bg_2525[] = {
1635 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1636 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1637 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1638 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1639 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1640 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1641 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1642 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1643 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1644 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1645 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1646 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1647 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1648 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1649};
1650
1651/*
1652 * RF value list for RF2525e
1653 * Supports: 2.4 GHz
1654 */
1655static const struct rf_channel rf_vals_bg_2525e[] = {
1656 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1657 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1658 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1659 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1660 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1661 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1662 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1663 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1664 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1665 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1666 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1667 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1668 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1669 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1670};
1671
1672/*
1673 * RF value list for RF5222
1674 * Supports: 2.4 GHz & 5.2 GHz
1675 */
1676static const struct rf_channel rf_vals_5222[] = {
1677 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1678 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1679 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1680 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1681 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1682 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1683 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1684 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1685 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1686 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1687 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1688 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1689 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1690 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1691
1692 /* 802.11 UNI / HyperLan 2 */
1693 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1694 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1695 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1696 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1697 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1698 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1699 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1700 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1701
1702 /* 802.11 HyperLan 2 */
1703 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1704 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1705 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1706 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1707 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1708 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1709 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1710 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1711 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1712 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1713
1714 /* 802.11 UNII */
1715 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1716 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1717 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1718 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1719 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1720};
1721
8c5e7a5f 1722static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1723{
1724 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1725 struct channel_info *info;
1726 char *tx_power;
95ea3627
ID		 1727 unsigned int i;
1728
1729 /*
1730 * Initialize all hw fields.
1731 */
566bfe5a 1732 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1733 IEEE80211_HW_SIGNAL_DBM |
1734 IEEE80211_HW_SUPPORTS_PS |
1735 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1736
14a3bf89 1737 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1738 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1739 rt2x00_eeprom_addr(rt2x00dev,
1740 EEPROM_MAC_ADDR_0));
1741
95ea3627
ID		 1742 /*
1743 * Initialize hw_mode information.
1744 */
31562e80
ID		 1745 spec->supported_bands = SUPPORT_BAND_2GHZ;
1746 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1747
5122d898 1748 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1749 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1750 spec->channels = rf_vals_bg_2522;
5122d898 1751 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1752 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1753 spec->channels = rf_vals_bg_2523;
5122d898 1754 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1755 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1756 spec->channels = rf_vals_bg_2524;
5122d898 1757 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1758 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1759 spec->channels = rf_vals_bg_2525;
5122d898 1760 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1761 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1762 spec->channels = rf_vals_bg_2525e;
5122d898 1763 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1764 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1765 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1766 spec->channels = rf_vals_5222;
95ea3627 1767 }
8c5e7a5f
ID		 1768
1769 /*
1770 * Create channel information array
1771 */
1772 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1773 if (!info)
1774 return -ENOMEM;
1775
1776 spec->channels_info = info;
1777
1778 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1779 for (i = 0; i < 14; i++)
1780 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1781
1782 if (spec->num_channels > 14) {
1783 for (i = 14; i < spec->num_channels; i++)
1784 info[i].tx_power1 = DEFAULT_TXPOWER;
1785 }
1786
1787 return 0;
95ea3627
ID		 1788}
1789
1790static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1791{
1792 int retval;
1793
1794 /*
1795 * Allocate eeprom data.
1796 */
1797 retval = rt2500pci_validate_eeprom(rt2x00dev);
1798 if (retval)
1799 return retval;
1800
1801 retval = rt2500pci_init_eeprom(rt2x00dev);
1802 if (retval)
1803 return retval;
1804
1805 /*
1806 * Initialize hw specifications.
1807 */
8c5e7a5f
ID		 1808 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1809 if (retval)
1810 return retval;
95ea3627
ID		 1811
1812 /*
c4da0048 1813 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1814 */
181d6902 1815 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1816 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1817
1818 /*
1819 * Set the rssi offset.
1820 */
1821 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1822
1823 return 0;
1824}
1825
1826/*
1827 * IEEE80211 stack callback functions.
1828 */
95ea3627
ID		 1829static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1830{
1831 struct rt2x00_dev *rt2x00dev = hw->priv;
1832 u64 tsf;
1833 u32 reg;
1834
1835 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1836 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1837 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1838 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1839
1840 return tsf;
1841}
1842
95ea3627
ID		 1843static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1844{
1845 struct rt2x00_dev *rt2x00dev = hw->priv;
1846 u32 reg;
1847
1848 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1849 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1850}
1851
1852static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1853 .tx = rt2x00mac_tx,
4150c572
JB		 1854 .start = rt2x00mac_start,
1855 .stop = rt2x00mac_stop,
95ea3627
ID		 1856 .add_interface = rt2x00mac_add_interface,
1857 .remove_interface = rt2x00mac_remove_interface,
1858 .config = rt2x00mac_config,
3a643d24 1859 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1860 .set_tim = rt2x00mac_set_tim,
95ea3627 1861 .get_stats = rt2x00mac_get_stats,
471b3efd 1862 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1863 .conf_tx = rt2x00mac_conf_tx,
95ea3627 1864 .get_tsf = rt2500pci_get_tsf,
95ea3627 1865 .tx_last_beacon = rt2500pci_tx_last_beacon,
e47a5cdd 1866 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1867};
1868
1869static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1870 .irq_handler = rt2500pci_interrupt,
1871 .probe_hw = rt2500pci_probe_hw,
1872 .initialize = rt2x00pci_initialize,
1873 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1874 .get_entry_state = rt2500pci_get_entry_state,
1875 .clear_entry = rt2500pci_clear_entry,
95ea3627 1876 .set_device_state = rt2500pci_set_device_state,
95ea3627 1877 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1878 .link_stats = rt2500pci_link_stats,
1879 .reset_tuner = rt2500pci_reset_tuner,
1880 .link_tuner = rt2500pci_link_tuner,
1881 .write_tx_desc = rt2500pci_write_tx_desc,
1882 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1883 .write_beacon = rt2500pci_write_beacon,
95ea3627 1884 .kick_tx_queue = rt2500pci_kick_tx_queue,
a2c9b652 1885 .kill_tx_queue = rt2500pci_kill_tx_queue,
95ea3627 1886 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1887 .config_filter = rt2500pci_config_filter,
6bb40dd1 1888 .config_intf = rt2500pci_config_intf,
72810379 1889 .config_erp = rt2500pci_config_erp,
e4ea1c40 1890 .config_ant = rt2500pci_config_ant,
95ea3627
ID		 1891 .config = rt2500pci_config,
1892};
1893
181d6902
ID		 1894static const struct data_queue_desc rt2500pci_queue_rx = {
1895 .entry_num = RX_ENTRIES,
1896 .data_size = DATA_FRAME_SIZE,
1897 .desc_size = RXD_DESC_SIZE,
b8be63ff 1898 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1899};
1900
1901static const struct data_queue_desc rt2500pci_queue_tx = {
1902 .entry_num = TX_ENTRIES,
1903 .data_size = DATA_FRAME_SIZE,
1904 .desc_size = TXD_DESC_SIZE,
b8be63ff 1905 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1906};
1907
1908static const struct data_queue_desc rt2500pci_queue_bcn = {
1909 .entry_num = BEACON_ENTRIES,
1910 .data_size = MGMT_FRAME_SIZE,
1911 .desc_size = TXD_DESC_SIZE,
b8be63ff 1912 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1913};
1914
1915static const struct data_queue_desc rt2500pci_queue_atim = {
1916 .entry_num = ATIM_ENTRIES,
1917 .data_size = DATA_FRAME_SIZE,
1918 .desc_size = TXD_DESC_SIZE,
b8be63ff 1919 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1920};
1921
95ea3627 1922static const struct rt2x00_ops rt2500pci_ops = {
04d0362e
GW		 1923 .name = KBUILD_MODNAME,
1924 .max_sta_intf = 1,
1925 .max_ap_intf = 1,
1926 .eeprom_size = EEPROM_SIZE,
1927 .rf_size = RF_SIZE,
1928 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1929 .extra_tx_headroom = 0,
04d0362e
GW		 1930 .rx = &rt2500pci_queue_rx,
1931 .tx = &rt2500pci_queue_tx,
1932 .bcn = &rt2500pci_queue_bcn,
1933 .atim = &rt2500pci_queue_atim,
1934 .lib = &rt2500pci_rt2x00_ops,
1935 .hw = &rt2500pci_mac80211_ops,
95ea3627 1936#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1937 .debugfs = &rt2500pci_rt2x00debug,
95ea3627
ID		 1938#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1939};
1940
1941/*
1942 * RT2500pci module information.
1943 */
a3aa1884 1944static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
95ea3627
ID		 1945 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1946 { 0, }
1947};
1948
1949MODULE_AUTHOR(DRV_PROJECT);
1950MODULE_VERSION(DRV_VERSION);
1951MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1952MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1953MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1954MODULE_LICENSE("GPL");
1955
1956static struct pci_driver rt2500pci_driver = {
2360157c 1957 .name = KBUILD_MODNAME,
95ea3627
ID		 1958 .id_table = rt2500pci_device_table,
1959 .probe = rt2x00pci_probe,
1960 .remove = __devexit_p(rt2x00pci_remove),
1961 .suspend = rt2x00pci_suspend,
1962 .resume = rt2x00pci_resume,
1963};
1964
1965static int __init rt2500pci_init(void)
1966{
1967 return pci_register_driver(&rt2500pci_driver);
1968}
1969
1970static void __exit rt2500pci_exit(void)
1971{
1972 pci_unregister_driver(&rt2500pci_driver);
1973}
1974
1975module_init(rt2500pci_init);
1976module_exit(rt2500pci_exit);
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