]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/wireless/rt2x00/rt2500pci.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'regulator/topic/palmas' into v3.9-rc8
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
69a2bac8 37#include "rt2x00mmio.h"
95ea3627
ID		 38#include "rt2x00pci.h"
39#include "rt2500pci.h"
40
41/*
42 * Register access.
43 * All access to the CSR registers will go through the methods
44 * rt2x00pci_register_read and rt2x00pci_register_write.
45 * BBP and RF register require indirect register access,
46 * and use the CSR registers BBPCSR and RFCSR to achieve this.
47 * These indirect registers work with busy bits,
48 * and we will try maximal REGISTER_BUSY_COUNT times to access
49 * the register while taking a REGISTER_BUSY_DELAY us delay
50 * between each attampt. When the busy bit is still set at that time,
51 * the access attempt is considered to have failed,
52 * and we will print an error.
53 */
c9c3b1a5
ID		 54#define WAIT_FOR_BBP(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
56#define WAIT_FOR_RF(__dev, __reg) \
57 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 58
0e14f6d3 59static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 60 const unsigned int word, const u8 value)
61{
62 u32 reg;
63
8ff48a8b
ID		 64 mutex_lock(&rt2x00dev->csr_mutex);
65
95ea3627 66 /*
c9c3b1a5
ID		 67 * Wait until the BBP becomes available, afterwards we
68 * can safely write the new data into the register.
95ea3627 69 */
c9c3b1a5
ID		 70 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
71 reg = 0;
72 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
73 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
74 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
75 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
76
77 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
78 }
8ff48a8b 79
8ff48a8b 80 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 81}
82
0e14f6d3 83static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int word, u8 *value)
85{
86 u32 reg;
87
8ff48a8b
ID		 88 mutex_lock(&rt2x00dev->csr_mutex);
89
95ea3627 90 /*
c9c3b1a5
ID		 91 * Wait until the BBP becomes available, afterwards we
92 * can safely write the read request into the register.
93 * After the data has been written, we wait until hardware
94 * returns the correct value, if at any time the register
95 * doesn't become available in time, reg will be 0xffffffff
96 * which means we return 0xff to the caller.
95ea3627 97 */
c9c3b1a5
ID		 98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
101 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
102 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 103
c9c3b1a5 104 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 105
c9c3b1a5
ID		 106 WAIT_FOR_BBP(rt2x00dev, &reg);
107 }
95ea3627
ID		 108
109 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 110
111 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 112}
113
0e14f6d3 114static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 115 const unsigned int word, const u32 value)
116{
117 u32 reg;
95ea3627 118
8ff48a8b
ID		 119 mutex_lock(&rt2x00dev->csr_mutex);
120
c9c3b1a5
ID		 121 /*
122 * Wait until the RF becomes available, afterwards we
123 * can safely write the new data into the register.
124 */
125 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
128 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
129 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
130 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
131
132 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
133 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 134 }
135
8ff48a8b 136 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 137}
138
139static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
140{
141 struct rt2x00_dev *rt2x00dev = eeprom->data;
142 u32 reg;
143
144 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
145
146 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
147 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
148 eeprom->reg_data_clock =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
150 eeprom->reg_chip_select =
151 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
152}
153
154static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
155{
156 struct rt2x00_dev *rt2x00dev = eeprom->data;
157 u32 reg = 0;
158
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
162 !!eeprom->reg_data_clock);
163 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
164 !!eeprom->reg_chip_select);
165
166 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
167}
168
169#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 170static const struct rt2x00debug rt2500pci_rt2x00debug = {
171 .owner = THIS_MODULE,
172 .csr = {
743b97ca
ID		 173 .read = rt2x00pci_register_read,
174 .write = rt2x00pci_register_write,
175 .flags = RT2X00DEBUGFS_OFFSET,
176 .word_base = CSR_REG_BASE,
95ea3627
ID		 177 .word_size = sizeof(u32),
178 .word_count = CSR_REG_SIZE / sizeof(u32),
179 },
180 .eeprom = {
181 .read = rt2x00_eeprom_read,
182 .write = rt2x00_eeprom_write,
743b97ca 183 .word_base = EEPROM_BASE,
95ea3627
ID		 184 .word_size = sizeof(u16),
185 .word_count = EEPROM_SIZE / sizeof(u16),
186 },
187 .bbp = {
188 .read = rt2500pci_bbp_read,
189 .write = rt2500pci_bbp_write,
743b97ca 190 .word_base = BBP_BASE,
95ea3627
ID		 191 .word_size = sizeof(u8),
192 .word_count = BBP_SIZE / sizeof(u8),
193 },
194 .rf = {
195 .read = rt2x00_rf_read,
196 .write = rt2500pci_rf_write,
743b97ca 197 .word_base = RF_BASE,
95ea3627
ID		 198 .word_size = sizeof(u32),
199 .word_count = RF_SIZE / sizeof(u32),
200 },
201};
202#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
203
95ea3627
ID		 204static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
205{
206 u32 reg;
207
208 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 209 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
95ea3627 210}
95ea3627 211
771fd565 212#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 213static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 214 enum led_brightness brightness)
215{
216 struct rt2x00_led *led =
217 container_of(led_cdev, struct rt2x00_led, led_dev);
218 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 219 u32 reg;
220
221 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
222
a2e1d52a 223 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 224 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 225 else if (led->type == LED_TYPE_ACTIVITY)
226 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 227
228 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
229}
a2e1d52a
ID		 230
231static int rt2500pci_blink_set(struct led_classdev *led_cdev,
232 unsigned long *delay_on,
233 unsigned long *delay_off)
234{
235 struct rt2x00_led *led =
236 container_of(led_cdev, struct rt2x00_led, led_dev);
237 u32 reg;
238
239 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
240 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
241 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
242 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
243
244 return 0;
245}
475433be
ID		 246
247static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
248 struct rt2x00_led *led,
249 enum led_type type)
250{
251 led->rt2x00dev = rt2x00dev;
252 led->type = type;
253 led->led_dev.brightness_set = rt2500pci_brightness_set;
254 led->led_dev.blink_set = rt2500pci_blink_set;
255 led->flags = LED_INITIALIZED;
256}
771fd565 257#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 258
95ea3627
ID		 259/*
260 * Configuration handlers.
261 */
3a643d24
ID		 262static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
263 const unsigned int filter_flags)
264{
265 u32 reg;
266
267 /*
268 * Start configuration steps.
269 * Note that the version error will always be dropped
270 * and broadcast frames will always be accepted since
271 * there is no filter for it at this time.
272 */
273 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
274 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
275 !(filter_flags & FIF_FCSFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
277 !(filter_flags & FIF_PLCPFAIL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
279 !(filter_flags & FIF_CONTROL));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
281 !(filter_flags & FIF_PROMISC_IN_BSS));
282 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 283 !(filter_flags & FIF_PROMISC_IN_BSS) &&
284 !rt2x00dev->intf_ap_count);
3a643d24
ID		 285 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
286 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
287 !(filter_flags & FIF_ALLMULTI));
288 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
289 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
290}
291
6bb40dd1
ID		 292static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
293 struct rt2x00_intf *intf,
294 struct rt2x00intf_conf *conf,
295 const unsigned int flags)
95ea3627 296{
a2440830 297 struct data_queue *queue = rt2x00dev->bcn;
6bb40dd1 298 unsigned int bcn_preload;
95ea3627
ID		 299 u32 reg;
300
6bb40dd1 301 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 302 /*
303 * Enable beacon config
304 */
bad13639 305 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 306 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
307 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
308 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
309 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 310
6bb40dd1
ID		 311 /*
312 * Enable synchronisation.
313 */
314 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1
ID		 315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
317 }
318
319 if (flags & CONFIG_UPDATE_MAC)
320 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
321 conf->mac, sizeof(conf->mac));
322
323 if (flags & CONFIG_UPDATE_BSSID)
324 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
325 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 326}
327
3a643d24 328static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 329 struct rt2x00lib_erp *erp,
330 u32 changed)
95ea3627 331{
5c58ee51 332 int preamble_mask;
95ea3627 333 u32 reg;
95ea3627 334
5c58ee51
ID		 335 /*
336 * When short preamble is enabled, we should set bit 0x08
337 */
02044643
HS		 338 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
339 preamble_mask = erp->short_preamble << 3;
340
341 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
343 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
344 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
345 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
346 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
347
348 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
349 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
350 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
351 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 GET_DURATION(ACK_SIZE, 10));
353 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
354
355 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
356 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
357 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
358 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 GET_DURATION(ACK_SIZE, 20));
360 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
361
362 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
363 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
364 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
365 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 GET_DURATION(ACK_SIZE, 55));
367 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
368
369 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
370 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
371 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
372 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
373 GET_DURATION(ACK_SIZE, 110));
374 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
375 }
376
377 if (changed & BSS_CHANGED_BASIC_RATES)
378 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
379
380 if (changed & BSS_CHANGED_ERP_SLOT) {
381 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
382 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
383 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
384
385 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
386 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
387 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
388 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
389
390 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
391 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
392 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
393 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
394 }
395
396 if (changed & BSS_CHANGED_BEACON_INT) {
397 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
398 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
399 erp->beacon_int * 16);
400 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
401 erp->beacon_int * 16);
402 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
403 }
404
95ea3627
ID		 405}
406
e4ea1c40
ID		 407static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
408 struct antenna_setup *ant)
95ea3627 409{
e4ea1c40
ID		 410 u32 reg;
411 u8 r14;
412 u8 r2;
413
414 /*
415 * We should never come here because rt2x00lib is supposed
416 * to catch this and send us the correct antenna explicitely.
417 */
418 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
419 ant->tx == ANTENNA_SW_DIVERSITY);
420
421 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
422 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
423 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
424
425 /*
426 * Configure the TX antenna.
427 */
428 switch (ant->tx) {
429 case ANTENNA_A:
430 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
431 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
432 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
433 break;
434 case ANTENNA_B:
435 default:
436 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
437 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
438 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
439 break;
440 }
441
442 /*
443 * Configure the RX antenna.
444 */
445 switch (ant->rx) {
446 case ANTENNA_A:
447 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
448 break;
449 case ANTENNA_B:
450 default:
451 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
452 break;
453 }
454
455 /*
456 * RT2525E and RT5222 need to flip TX I/Q
457 */
5122d898 458 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
e4ea1c40
ID		 459 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
460 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
461 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
462
463 /*
464 * RT2525E does not need RX I/Q Flip.
465 */
5122d898 466 if (rt2x00_rf(rt2x00dev, RF2525E))
e4ea1c40
ID		 467 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
468 } else {
469 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
470 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
471 }
472
473 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
474 rt2500pci_bbp_write(rt2x00dev, 14, r14);
475 rt2500pci_bbp_write(rt2x00dev, 2, r2);
95ea3627
ID		 476}
477
478static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 479 struct rf_channel *rf, const int txpower)
95ea3627 480{
95ea3627
ID		 481 u8 r70;
482
95ea3627
ID		 483 /*
484 * Set TXpower.
485 */
5c58ee51 486 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 487
488 /*
489 * Switch on tuning bits.
490 * For RT2523 devices we do not need to update the R1 register.
491 */
5122d898 492 if (!rt2x00_rf(rt2x00dev, RF2523))
5c58ee51
ID		 493 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
494 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 495
496 /*
497 * For RT2525 we should first set the channel to half band higher.
498 */
5122d898 499 if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 500 static const u32 vals[] = {
501 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
502 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
503 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
504 0x00080d2e, 0x00080d3a
505 };
506
5c58ee51
ID		 507 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
508 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
509 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
510 if (rf->rf4)
511 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 512 }
513
5c58ee51
ID		 514 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
515 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
516 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
517 if (rf->rf4)
518 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 519
520 /*
521 * Channel 14 requires the Japan filter bit to be set.
522 */
523 r70 = 0x46;
5c58ee51 524 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 525 rt2500pci_bbp_write(rt2x00dev, 70, r70);
526
527 msleep(1);
528
529 /*
530 * Switch off tuning bits.
531 * For RT2523 devices we do not need to update the R1 register.
532 */
5122d898 533 if (!rt2x00_rf(rt2x00dev, RF2523)) {
5c58ee51
ID		 534 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
535 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 536 }
537
5c58ee51
ID		 538 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
539 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 540
541 /*
542 * Clear false CRC during channel switch.
543 */
5c58ee51 544 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 545}
546
547static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
548 const int txpower)
549{
550 u32 rf3;
551
552 rt2x00_rf_read(rt2x00dev, 3, &rf3);
553 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
554 rt2500pci_rf_write(rt2x00dev, 3, rf3);
555}
556
e4ea1c40
ID		 557static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
558 struct rt2x00lib_conf *libconf)
95ea3627
ID		 559{
560 u32 reg;
95ea3627 561
e4ea1c40
ID		 562 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
563 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
564 libconf->conf->long_frame_max_tx_count);
565 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
566 libconf->conf->short_frame_max_tx_count);
567 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 568}
569
7d7f19cc
ID		 570static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
571 struct rt2x00lib_conf *libconf)
572{
573 enum dev_state state =
574 (libconf->conf->flags & IEEE80211_CONF_PS) ?
575 STATE_SLEEP : STATE_AWAKE;
576 u32 reg;
577
578 if (state == STATE_SLEEP) {
579 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
580 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 581 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 582 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
583 libconf->conf->listen_interval - 1);
584
585 /* We must first disable autowake before it can be enabled */
586 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
587 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
588
589 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
590 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 591 } else {
592 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
593 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
594 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 595 }
596
597 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
598}
599
95ea3627 600static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 601 struct rt2x00lib_conf *libconf,
602 const unsigned int flags)
95ea3627 603{
e4ea1c40 604 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 605 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
606 libconf->conf->power_level);
e4ea1c40
ID		 607 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
608 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 609 rt2500pci_config_txpower(rt2x00dev,
610 libconf->conf->power_level);
e4ea1c40
ID		 611 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
612 rt2500pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 613 if (flags & IEEE80211_CONF_CHANGE_PS)
614 rt2500pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 615}
616
95ea3627
ID		 617/*
618 * Link tuning
619 */
ebcf26da
ID		 620static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
621 struct link_qual *qual)
95ea3627
ID		 622{
623 u32 reg;
624
625 /*
626 * Update FCS error count from register.
627 */
628 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 629 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 630
631 /*
632 * Update False CCA count from register.
633 */
634 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 635 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 636}
637
5352ff65
ID		 638static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
639 struct link_qual *qual, u8 vgc_level)
eb20b4e8 640{
5352ff65 641 if (qual->vgc_level_reg != vgc_level) {
eb20b4e8 642 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
223dcc26 643 qual->vgc_level = vgc_level;
5352ff65 644 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 645 }
646}
647
5352ff65
ID		 648static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
649 struct link_qual *qual)
95ea3627 650{
5352ff65 651 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
95ea3627
ID		 652}
653
5352ff65
ID		 654static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
655 struct link_qual *qual, const u32 count)
95ea3627 656{
95ea3627
ID		 657 /*
658 * To prevent collisions with MAC ASIC on chipsets
659 * up to version C the link tuning should halt after 20
6bb40dd1 660 * seconds while being associated.
95ea3627 661 */
5122d898 662 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
5352ff65 663 rt2x00dev->intf_associated && count > 20)
95ea3627
ID		 664 return;
665
95ea3627
ID		 666 /*
667 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 668 * to the dynamic CCA tuning. Chipset version D and higher
669 * should go straight to dynamic CCA tuning when they
670 * are not associated.
95ea3627 671 */
5122d898 672 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
6bb40dd1 673 !rt2x00dev->intf_associated)
95ea3627
ID		 674 goto dynamic_cca_tune;
675
676 /*
677 * A too low RSSI will cause too much false CCA which will
678 * then corrupt the R17 tuning. To remidy this the tuning should
679 * be stopped (While making sure the R17 value will not exceed limits)
680 */
5352ff65
ID		 681 if (qual->rssi < -80 && count > 20) {
682 if (qual->vgc_level_reg >= 0x41)
683 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 684 return;
685 }
686
687 /*
688 * Special big-R17 for short distance
689 */
5352ff65
ID		 690 if (qual->rssi >= -58) {
691 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
95ea3627
ID		 692 return;
693 }
694
695 /*
696 * Special mid-R17 for middle distance
697 */
5352ff65
ID		 698 if (qual->rssi >= -74) {
699 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
95ea3627
ID		 700 return;
701 }
702
703 /*
704 * Leave short or middle distance condition, restore r17
705 * to the dynamic tuning range.
706 */
5352ff65
ID		 707 if (qual->vgc_level_reg >= 0x41) {
708 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 709 return;
710 }
711
712dynamic_cca_tune:
713
714 /*
715 * R17 is inside the dynamic tuning range,
716 * start tuning the link based on the false cca counter.
717 */
223dcc26 718 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
5352ff65 719 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
223dcc26 720 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
5352ff65 721 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
95ea3627
ID		 722}
723
5450b7e2
ID		 724/*
725 * Queue handlers.
726 */
727static void rt2500pci_start_queue(struct data_queue *queue)
728{
729 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
730 u32 reg;
731
732 switch (queue->qid) {
733 case QID_RX:
734 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
735 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
736 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
737 break;
738 case QID_BEACON:
739 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
740 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
741 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
742 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
743 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
744 break;
745 default:
746 break;
747 }
748}
749
750static void rt2500pci_kick_queue(struct data_queue *queue)
751{
752 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
753 u32 reg;
754
755 switch (queue->qid) {
f615e9a3 756 case QID_AC_VO:
5450b7e2
ID		 757 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
758 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
759 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
760 break;
f615e9a3 761 case QID_AC_VI:
5450b7e2
ID		 762 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
763 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
764 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
765 break;
766 case QID_ATIM:
767 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
768 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
769 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
770 break;
771 default:
772 break;
773 }
774}
775
776static void rt2500pci_stop_queue(struct data_queue *queue)
777{
778 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
779 u32 reg;
780
781 switch (queue->qid) {
f615e9a3
ID		 782 case QID_AC_VO:
783 case QID_AC_VI:
5450b7e2
ID		 784 case QID_ATIM:
785 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
786 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
787 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
788 break;
789 case QID_RX:
790 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
791 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
792 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
793 break;
794 case QID_BEACON:
795 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
796 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
797 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
798 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
799 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
16222a0d
HS		 800
801 /*
802 * Wait for possibly running tbtt tasklets.
803 */
abc11994 804 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 805 break;
806 default:
807 break;
808 }
809}
810
95ea3627
ID		 811/*
812 * Initialization functions.
813 */
798b7adb 814static bool rt2500pci_get_entry_state(struct queue_entry *entry)
95ea3627 815{
b8be63ff 816 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 817 u32 word;
818
798b7adb
ID		 819 if (entry->queue->qid == QID_RX) {
820 rt2x00_desc_read(entry_priv->desc, 0, &word);
821
822 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
823 } else {
824 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 825
798b7adb
ID		 826 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
827 rt2x00_get_field32(word, TXD_W0_VALID));
828 }
95ea3627
ID		 829}
830
798b7adb 831static void rt2500pci_clear_entry(struct queue_entry *entry)
95ea3627 832{
b8be63ff 833 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 834 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 835 u32 word;
836
798b7adb
ID		 837 if (entry->queue->qid == QID_RX) {
838 rt2x00_desc_read(entry_priv->desc, 1, &word);
839 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
840 rt2x00_desc_write(entry_priv->desc, 1, word);
841
842 rt2x00_desc_read(entry_priv->desc, 0, &word);
843 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
844 rt2x00_desc_write(entry_priv->desc, 0, word);
845 } else {
846 rt2x00_desc_read(entry_priv->desc, 0, &word);
847 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
848 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
849 rt2x00_desc_write(entry_priv->desc, 0, word);
850 }
95ea3627
ID		 851}
852
181d6902 853static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 854{
b8be63ff 855 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 856 u32 reg;
857
95ea3627
ID		 858 /*
859 * Initialize registers.
860 */
861 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 862 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
863 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 864 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 865 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 866 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
867
b8be63ff 868 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 869 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 870 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 871 entry_priv->desc_dma);
95ea3627
ID		 872 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
873
b8be63ff 874 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 875 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 876 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 877 entry_priv->desc_dma);
95ea3627
ID		 878 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
879
e74df4a7 880 entry_priv = rt2x00dev->atim->entries[0].priv_data;
95ea3627 881 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 882 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 883 entry_priv->desc_dma);
95ea3627
ID		 884 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
885
e74df4a7 886 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
95ea3627 887 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 888 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 889 entry_priv->desc_dma);
95ea3627
ID		 890 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
891
892 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
893 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 894 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 895 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
896
b8be63ff 897 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 898 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 899 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
900 entry_priv->desc_dma);
95ea3627
ID		 901 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
902
903 return 0;
904}
905
906static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
907{
908 u32 reg;
909
910 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
911 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
912 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
913 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
914
915 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
916 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
917 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
918 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
919 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
920
921 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
922 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
923 rt2x00dev->rx->data_size / 128);
924 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
925
926 /*
927 * Always use CWmin and CWmax set in descriptor.
928 */
929 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
930 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
931 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
932
1f909162
ID		 933 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
934 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
935 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
936 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
937 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
938 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
939 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
940 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
941 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
942 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
943
95ea3627
ID		 944 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
945
946 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
947 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
948 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
949 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
950 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
951 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
952 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
953 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
954 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
955 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
956
957 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
958 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
959 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
960 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
961 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
962 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
963
964 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
965 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
966 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
967 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
968 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
969 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
970
971 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
972 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
973 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
974 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
975 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
976 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
977
978 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
979 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
980 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
981 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
982 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
983 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
984 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
985 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
986 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
987 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
988
989 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
990 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
991 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
992 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
993 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
994 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
995 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
996 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
997 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
998
999 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
1000
1001 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
1002 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
1003
1004 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1005 return -EBUSY;
1006
1007 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
1008 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
1009
1010 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
1011 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1012 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
1013
1014 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
1015 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1016 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1017 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1018 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1019 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1020 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1021 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
1022
1023 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1024
1025 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1026
1027 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1028 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1029 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1030 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1031 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1032
1033 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1034 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1035 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1036 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1037
1038 /*
1039 * We must clear the FCS and FIFO error count.
1040 * These registers are cleared on read,
1041 * so we may pass a useless variable to store the value.
1042 */
1043 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1044 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
1045
1046 return 0;
1047}
1048
2b08da3f 1049static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1050{
1051 unsigned int i;
95ea3627
ID		 1052 u8 value;
1053
1054 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1055 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1056 if ((value != 0xff) && (value != 0x00))
2b08da3f 1057 return 0;
95ea3627
ID		 1058 udelay(REGISTER_BUSY_DELAY);
1059 }
1060
1061 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1062 return -EACCES;
2b08da3f
ID		 1063}
1064
1065static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1066{
1067 unsigned int i;
1068 u16 eeprom;
1069 u8 reg_id;
1070 u8 value;
1071
1072 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1073 return -EACCES;
95ea3627 1074
95ea3627
ID		 1075 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1076 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1077 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1078 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1079 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1080 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1081 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1082 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1083 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1084 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1085 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1086 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1087 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1088 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1089 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1090 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1091 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1092 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1093 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1094 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1095 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1096 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1097 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1098 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1099 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1100 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1101 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1102 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1103 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1104 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1105
95ea3627
ID		 1106 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1107 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1108
1109 if (eeprom != 0xffff && eeprom != 0x0000) {
1110 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1111 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1112 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1113 }
1114 }
95ea3627
ID		 1115
1116 return 0;
1117}
1118
1119/*
1120 * Device state switch handlers.
1121 */
95ea3627
ID		 1122static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1123 enum dev_state state)
1124{
b550911a 1125 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 1126 u32 reg;
16222a0d 1127 unsigned long flags;
95ea3627
ID		 1128
1129 /*
1130 * When interrupts are being enabled, the interrupt registers
1131 * should clear the register to assure a clean state.
1132 */
1133 if (state == STATE_RADIO_IRQ_ON) {
1134 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1135 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1136 }
1137
1138 /*
1139 * Only toggle the interrupts bits we are going to use.
1140 * Non-checked interrupt bits are disabled by default.
1141 */
16222a0d
HS		 1142 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1143
95ea3627
ID		 1144 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1145 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1146 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1147 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1148 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1149 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1150 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
16222a0d
HS		 1151
1152 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1153
1154 if (state == STATE_RADIO_IRQ_OFF) {
1155 /*
1156 * Ensure that all tasklets are finished.
1157 */
abc11994
HS		 1158 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1159 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1160 tasklet_kill(&rt2x00dev->tbtt_tasklet);
16222a0d 1161 }
95ea3627
ID		 1162}
1163
1164static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1165{
1166 /*
1167 * Initialize all registers.
1168 */
2b08da3f
ID		 1169 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1170 rt2500pci_init_registers(rt2x00dev) ||
1171 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1172 return -EIO;
95ea3627 1173
95ea3627
ID		 1174 return 0;
1175}
1176
1177static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1178{
95ea3627 1179 /*
a2c9b652 1180 * Disable power
95ea3627 1181 */
a2c9b652 1182 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1183}
1184
1185static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1186 enum dev_state state)
1187{
9655a6ec 1188 u32 reg, reg2;
95ea3627
ID		 1189 unsigned int i;
1190 char put_to_sleep;
1191 char bbp_state;
1192 char rf_state;
1193
1194 put_to_sleep = (state != STATE_AWAKE);
1195
1196 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1197 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1198 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1199 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1200 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1201 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1202
1203 /*
1204 * Device is not guaranteed to be in the requested state yet.
1205 * We must wait until the register indicates that the
1206 * device has entered the correct state.
1207 */
1208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1209 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1210 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1211 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1212 if (bbp_state == state && rf_state == state)
1213 return 0;
9655a6ec 1214 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1215 msleep(10);
1216 }
1217
95ea3627
ID		 1218 return -EBUSY;
1219}
1220
1221static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1222 enum dev_state state)
1223{
1224 int retval = 0;
1225
1226 switch (state) {
1227 case STATE_RADIO_ON:
1228 retval = rt2500pci_enable_radio(rt2x00dev);
1229 break;
1230 case STATE_RADIO_OFF:
1231 rt2500pci_disable_radio(rt2x00dev);
1232 break;
2b08da3f
ID		 1233 case STATE_RADIO_IRQ_ON:
1234 case STATE_RADIO_IRQ_OFF:
1235 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1236 break;
1237 case STATE_DEEP_SLEEP:
1238 case STATE_SLEEP:
1239 case STATE_STANDBY:
1240 case STATE_AWAKE:
1241 retval = rt2500pci_set_state(rt2x00dev, state);
1242 break;
1243 default:
1244 retval = -ENOTSUPP;
1245 break;
1246 }
1247
2b08da3f
ID		 1248 if (unlikely(retval))
1249 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1250 state, retval);
1251
95ea3627
ID		 1252 return retval;
1253}
1254
1255/*
1256 * TX descriptor initialization
1257 */
93331458 1258static void rt2500pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1259 struct txentry_desc *txdesc)
95ea3627 1260{
93331458
ID		 1261 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1262 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1263 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1264 u32 word;
1265
1266 /*
1267 * Start writing the descriptor words.
1268 */
85b7a8b3 1269 rt2x00_desc_read(txd, 1, &word);
c4da0048 1270 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1271 rt2x00_desc_write(txd, 1, word);
4de36fe5 1272
95ea3627
ID		 1273 rt2x00_desc_read(txd, 2, &word);
1274 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
2b23cdaa
HS		 1275 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1276 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1277 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
95ea3627
ID		 1278 rt2x00_desc_write(txd, 2, word);
1279
1280 rt2x00_desc_read(txd, 3, &word);
26a1d07f
HS		 1281 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1282 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1283 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1284 txdesc->u.plcp.length_low);
1285 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1286 txdesc->u.plcp.length_high);
95ea3627
ID		 1287 rt2x00_desc_write(txd, 3, word);
1288
1289 rt2x00_desc_read(txd, 10, &word);
1290 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1291 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1292 rt2x00_desc_write(txd, 10, word);
1293
e01f1ec3
GW		 1294 /*
1295 * Writing TXD word 0 must the last to prevent a race condition with
1296 * the device, whereby the device may take hold of the TXD before we
1297 * finished updating it.
1298 */
95ea3627
ID		 1299 rt2x00_desc_read(txd, 0, &word);
1300 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1301 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1302 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1303 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1304 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1305 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1306 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1307 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1308 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1309 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1310 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
2517794b 1311 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1312 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1313 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
df624ca5 1314 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1315 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1316 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1317
1318 /*
1319 * Register descriptor details in skb frame descriptor.
1320 */
1321 skbdesc->desc = txd;
1322 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1323}
1324
1325/*
1326 * TX data initialization
1327 */
f224f4ef
GW		 1328static void rt2500pci_write_beacon(struct queue_entry *entry,
1329 struct txentry_desc *txdesc)
bd88a781
ID		 1330{
1331 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1332 u32 reg;
1333
1334 /*
1335 * Disable beaconing while we are reloading the beacon data,
1336 * otherwise we might be sending out invalid data.
1337 */
1338 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1339 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1340 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1341
4ea545d4
SG		 1342 if (rt2x00queue_map_txskb(entry)) {
1343 ERROR(rt2x00dev, "Fail to map beacon, aborting\n");
1344 goto out;
1345 }
bd88a781 1346
5c3b685c
GW		 1347 /*
1348 * Write the TX descriptor for the beacon.
1349 */
93331458 1350 rt2500pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1351
1352 /*
1353 * Dump beacon to userspace through debugfs.
1354 */
1355 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
4ea545d4 1356out:
d61cb266
GW		 1357 /*
1358 * Enable beaconing again.
1359 */
d61cb266
GW		 1360 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1361 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1362}
1363
95ea3627
ID		 1364/*
1365 * RX control handlers
1366 */
181d6902
ID		 1367static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1368 struct rxdone_entry_desc *rxdesc)
95ea3627 1369{
b8be63ff 1370 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1371 u32 word0;
1372 u32 word2;
1373
b8be63ff
ID		 1374 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1375 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1376
4150c572 1377 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1378 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1379 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1380 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1381
89993890
ID		 1382 /*
1383 * Obtain the status about this packet.
1384 * When frame was received with an OFDM bitrate,
1385 * the signal is the PLCP value. If it was received with
1386 * a CCK bitrate the signal is the rate in 100kbit/s.
1387 */
181d6902
ID		 1388 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1389 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1390 entry->queue->rt2x00dev->rssi_offset;
181d6902 1391 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1392
19d30e02
ID		 1393 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1394 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1395 else
1396 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1397 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1398 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1399}
1400
1401/*
1402 * Interrupt functions.
1403 */
181d6902 1404static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1405 const enum data_queue_qid queue_idx)
95ea3627 1406{
61c6e489 1407 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
b8be63ff 1408 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1409 struct queue_entry *entry;
1410 struct txdone_entry_desc txdesc;
95ea3627 1411 u32 word;
95ea3627 1412
181d6902
ID		 1413 while (!rt2x00queue_empty(queue)) {
1414 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1415 entry_priv = entry->priv_data;
1416 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1417
1418 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1419 !rt2x00_get_field32(word, TXD_W0_VALID))
1420 break;
1421
1422 /*
1423 * Obtain the status about this packet.
1424 */
fb55f4d1
ID		 1425 txdesc.flags = 0;
1426 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1427 case 0: /* Success */
1428 case 1: /* Success with retry */
1429 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1430 break;
1431 case 2: /* Failure, excessive retries */
1432 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1433 /* Don't break, this is a failed frame! */
1434 default: /* Failure */
1435 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1436 }
181d6902 1437 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1438
e513a0b6 1439 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1440 }
95ea3627
ID		 1441}
1442
7a5a681a
HS		 1443static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1444 struct rt2x00_field32 irq_field)
95ea3627 1445{
16222a0d 1446 u32 reg;
95ea3627
ID		 1447
1448 /*
16222a0d
HS		 1449 * Enable a single interrupt. The interrupt mask register
1450 * access needs locking.
95ea3627 1451 */
0aa13b2e 1452 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1453
16222a0d
HS		 1454 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1455 rt2x00_set_field32(&reg, irq_field, 0);
1456 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
95ea3627 1457
0aa13b2e 1458 spin_unlock_irq(&rt2x00dev->irqmask_lock);
16222a0d 1459}
95ea3627 1460
16222a0d
HS		 1461static void rt2500pci_txstatus_tasklet(unsigned long data)
1462{
1463 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1464 u32 reg;
95ea3627
ID		 1465
1466 /*
16222a0d 1467 * Handle all tx queues.
95ea3627 1468 */
16222a0d
HS		 1469 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1470 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1471 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1472
1473 /*
16222a0d 1474 * Enable all TXDONE interrupts again.
95ea3627 1475 */
abc11994
HS		 1476 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1477 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1478
abc11994
HS		 1479 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1480 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1481 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1482 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1483 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
78e256c9 1484
abc11994
HS		 1485 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1486 }
16222a0d
HS		 1487}
1488
1489static void rt2500pci_tbtt_tasklet(unsigned long data)
1490{
1491 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1492 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1493 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1494 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
16222a0d
HS		 1495}
1496
1497static void rt2500pci_rxdone_tasklet(unsigned long data)
1498{
1499 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 1500 if (rt2x00pci_rxdone(rt2x00dev))
1501 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1502 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1503 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1504}
1505
78e256c9
HS		 1506static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1507{
1508 struct rt2x00_dev *rt2x00dev = dev_instance;
16222a0d 1509 u32 reg, mask;
78e256c9
HS		 1510
1511 /*
1512 * Get the interrupt sources & saved to local variable.
1513 * Write register value back to clear pending interrupts.
1514 */
1515 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1516 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1517
1518 if (!reg)
1519 return IRQ_NONE;
1520
1521 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1522 return IRQ_HANDLED;
1523
16222a0d
HS		 1524 mask = reg;
1525
1526 /*
1527 * Schedule tasklets for interrupt handling.
1528 */
1529 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1530 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1531
1532 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1533 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1534
1535 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1536 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1537 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1538 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1539 /*
1540 * Mask out all txdone interrupts.
1541 */
1542 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1543 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1544 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1545 }
1546
1547 /*
1548 * Disable all interrupts for which a tasklet was scheduled right now,
1549 * the tasklet will reenable the appropriate interrupts.
1550 */
0aa13b2e 1551 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1552
16222a0d
HS		 1553 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1554 reg |= mask;
1555 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1556
0aa13b2e 1557 spin_unlock(&rt2x00dev->irqmask_lock);
78e256c9 1558
16222a0d 1559 return IRQ_HANDLED;
78e256c9
HS		 1560}
1561
95ea3627
ID		 1562/*
1563 * Device probe functions.
1564 */
1565static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1566{
1567 struct eeprom_93cx6 eeprom;
1568 u32 reg;
1569 u16 word;
1570 u8 *mac;
1571
1572 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1573
1574 eeprom.data = rt2x00dev;
1575 eeprom.register_read = rt2500pci_eepromregister_read;
1576 eeprom.register_write = rt2500pci_eepromregister_write;
1577 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1578 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1579 eeprom.reg_data_in = 0;
1580 eeprom.reg_data_out = 0;
1581 eeprom.reg_data_clock = 0;
1582 eeprom.reg_chip_select = 0;
1583
1584 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1585 EEPROM_SIZE / sizeof(u16));
1586
1587 /*
1588 * Start validation of the data that has been read.
1589 */
1590 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1591 if (!is_valid_ether_addr(mac)) {
f4f7f414 1592 eth_random_addr(mac);
e174961c 1593 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1594 }
1595
1596 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1597 if (word == 0xffff) {
1598 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1599 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1600 ANTENNA_SW_DIVERSITY);
1601 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1602 ANTENNA_SW_DIVERSITY);
1603 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1604 LED_MODE_DEFAULT);
95ea3627
ID		 1605 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1606 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1607 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1608 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1609 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1610 }
1611
1612 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1613 if (word == 0xffff) {
1614 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1615 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1616 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1617 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1618 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1619 }
1620
1621 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1622 if (word == 0xffff) {
1623 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1624 DEFAULT_RSSI_OFFSET);
1625 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1626 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1627 }
1628
1629 return 0;
1630}
1631
1632static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1633{
1634 u32 reg;
1635 u16 value;
1636 u16 eeprom;
1637
1638 /*
1639 * Read EEPROM word for configuration.
1640 */
1641 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1642
1643 /*
1644 * Identify RF chipset.
1645 */
1646 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1647 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1648 rt2x00_set_chip(rt2x00dev, RT2560, value,
1649 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1650
5122d898
GW		 1651 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1652 !rt2x00_rf(rt2x00dev, RF2523) &&
1653 !rt2x00_rf(rt2x00dev, RF2524) &&
1654 !rt2x00_rf(rt2x00dev, RF2525) &&
1655 !rt2x00_rf(rt2x00dev, RF2525E) &&
1656 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1657 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1658 return -ENODEV;
1659 }
1660
1661 /*
1662 * Identify default antenna configuration.
1663 */
addc81bd 1664 rt2x00dev->default_ant.tx =
95ea3627 1665 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1666 rt2x00dev->default_ant.rx =
95ea3627
ID		 1667 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1668
1669 /*
1670 * Store led mode, for correct led behaviour.
1671 */
771fd565 1672#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1673 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1674
475433be 1675 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1676 if (value == LED_MODE_TXRX_ACTIVITY ||
1677 value == LED_MODE_DEFAULT ||
1678 value == LED_MODE_ASUS)
475433be
ID		 1679 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1680 LED_TYPE_ACTIVITY);
771fd565 1681#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1682
1683 /*
1684 * Detect if this device has an hardware controlled radio.
1685 */
1686 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1687 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 1688
1689 /*
1690 * Check if the BBP tuning should be enabled.
1691 */
1692 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
27df2a9c 1693 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
7dab73b3 1694 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1695
1696 /*
1697 * Read the RSSI <-> dBm offset information.
1698 */
1699 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1700 rt2x00dev->rssi_offset =
1701 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1702
1703 return 0;
1704}
1705
1706/*
1707 * RF value list for RF2522
1708 * Supports: 2.4 GHz
1709 */
1710static const struct rf_channel rf_vals_bg_2522[] = {
1711 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1712 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1713 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1714 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1715 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1716 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1717 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1718 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1719 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1720 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1721 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1722 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1723 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1724 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1725};
1726
1727/*
1728 * RF value list for RF2523
1729 * Supports: 2.4 GHz
1730 */
1731static const struct rf_channel rf_vals_bg_2523[] = {
1732 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1733 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1734 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1735 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1736 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1737 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1738 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1739 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1740 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1741 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1742 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1743 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1744 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1745 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1746};
1747
1748/*
1749 * RF value list for RF2524
1750 * Supports: 2.4 GHz
1751 */
1752static const struct rf_channel rf_vals_bg_2524[] = {
1753 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1754 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1755 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1756 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1757 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1758 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1759 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1760 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1761 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1762 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1763 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1764 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1765 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1766 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1767};
1768
1769/*
1770 * RF value list for RF2525
1771 * Supports: 2.4 GHz
1772 */
1773static const struct rf_channel rf_vals_bg_2525[] = {
1774 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1775 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1776 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1777 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1778 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1779 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1780 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1781 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1782 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1783 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1784 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1785 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1786 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1787 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1788};
1789
1790/*
1791 * RF value list for RF2525e
1792 * Supports: 2.4 GHz
1793 */
1794static const struct rf_channel rf_vals_bg_2525e[] = {
1795 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1796 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1797 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1798 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1799 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1800 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1801 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1802 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1803 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1804 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1805 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1806 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1807 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1808 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1809};
1810
1811/*
1812 * RF value list for RF5222
1813 * Supports: 2.4 GHz & 5.2 GHz
1814 */
1815static const struct rf_channel rf_vals_5222[] = {
1816 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1817 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1818 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1819 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1820 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1821 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1822 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1823 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1824 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1825 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1826 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1827 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1828 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1829 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1830
1831 /* 802.11 UNI / HyperLan 2 */
1832 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1833 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1834 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1835 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1836 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1837 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1838 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1839 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1840
1841 /* 802.11 HyperLan 2 */
1842 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1843 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1844 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1845 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1846 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1847 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1848 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1849 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1850 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1851 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1852
1853 /* 802.11 UNII */
1854 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1855 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1856 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1857 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1858 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1859};
1860
8c5e7a5f 1861static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1862{
1863 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1864 struct channel_info *info;
1865 char *tx_power;
95ea3627
ID		 1866 unsigned int i;
1867
1868 /*
1869 * Initialize all hw fields.
1870 */
566bfe5a 1871 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1872 IEEE80211_HW_SIGNAL_DBM |
1873 IEEE80211_HW_SUPPORTS_PS |
1874 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1875
14a3bf89 1876 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1877 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1878 rt2x00_eeprom_addr(rt2x00dev,
1879 EEPROM_MAC_ADDR_0));
1880
95ea3627
ID		 1881 /*
1882 * Initialize hw_mode information.
1883 */
31562e80
ID		 1884 spec->supported_bands = SUPPORT_BAND_2GHZ;
1885 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1886
5122d898 1887 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1888 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1889 spec->channels = rf_vals_bg_2522;
5122d898 1890 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1891 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1892 spec->channels = rf_vals_bg_2523;
5122d898 1893 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1894 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1895 spec->channels = rf_vals_bg_2524;
5122d898 1896 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1897 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1898 spec->channels = rf_vals_bg_2525;
5122d898 1899 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1900 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1901 spec->channels = rf_vals_bg_2525e;
5122d898 1902 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1903 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1904 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1905 spec->channels = rf_vals_5222;
95ea3627 1906 }
8c5e7a5f
ID		 1907
1908 /*
1909 * Create channel information array
1910 */
baeb2ffa 1911 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1912 if (!info)
1913 return -ENOMEM;
1914
1915 spec->channels_info = info;
1916
1917 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1918 for (i = 0; i < 14; i++) {
1919 info[i].max_power = MAX_TXPOWER;
1920 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1921 }
8c5e7a5f
ID		 1922
1923 if (spec->num_channels > 14) {
8d1331b3
ID		 1924 for (i = 14; i < spec->num_channels; i++) {
1925 info[i].max_power = MAX_TXPOWER;
1926 info[i].default_power1 = DEFAULT_TXPOWER;
1927 }
8c5e7a5f
ID		 1928 }
1929
1930 return 0;
95ea3627
ID		 1931}
1932
1933static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1934{
1935 int retval;
a396e100 1936 u32 reg;
95ea3627
ID		 1937
1938 /*
1939 * Allocate eeprom data.
1940 */
1941 retval = rt2500pci_validate_eeprom(rt2x00dev);
1942 if (retval)
1943 return retval;
1944
1945 retval = rt2500pci_init_eeprom(rt2x00dev);
1946 if (retval)
1947 return retval;
1948
a396e100
GW		 1949 /*
1950 * Enable rfkill polling by setting GPIO direction of the
1951 * rfkill switch GPIO pin correctly.
1952 */
1953 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
1954 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1955 rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);
1956
95ea3627
ID		 1957 /*
1958 * Initialize hw specifications.
1959 */
8c5e7a5f
ID		 1960 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1961 if (retval)
1962 return retval;
95ea3627
ID		 1963
1964 /*
c4da0048 1965 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1966 */
7dab73b3
ID		 1967 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1968 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1969 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1970
1971 /*
1972 * Set the rssi offset.
1973 */
1974 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1975
1976 return 0;
1977}
1978
1979/*
1980 * IEEE80211 stack callback functions.
1981 */
37a41b4a
EP		 1982static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1983 struct ieee80211_vif *vif)
95ea3627
ID		 1984{
1985 struct rt2x00_dev *rt2x00dev = hw->priv;
1986 u64 tsf;
1987 u32 reg;
1988
1989 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1990 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1991 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1992 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1993
1994 return tsf;
1995}
1996
95ea3627
ID		 1997static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1998{
1999 struct rt2x00_dev *rt2x00dev = hw->priv;
2000 u32 reg;
2001
2002 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
2003 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2004}
2005
2006static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2007 .tx = rt2x00mac_tx,
4150c572
JB		 2008 .start = rt2x00mac_start,
2009 .stop = rt2x00mac_stop,
95ea3627
ID		 2010 .add_interface = rt2x00mac_add_interface,
2011 .remove_interface = rt2x00mac_remove_interface,
2012 .config = rt2x00mac_config,
3a643d24 2013 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 2014 .sw_scan_start = rt2x00mac_sw_scan_start,
2015 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2016 .get_stats = rt2x00mac_get_stats,
471b3efd 2017 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 2018 .conf_tx = rt2x00mac_conf_tx,
95ea3627 2019 .get_tsf = rt2500pci_get_tsf,
95ea3627 2020 .tx_last_beacon = rt2500pci_tx_last_beacon,
e47a5cdd 2021 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2022 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 2023 .set_antenna = rt2x00mac_set_antenna,
2024 .get_antenna = rt2x00mac_get_antenna,
e7dee444 2025 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 2026 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 2027};
2028
2029static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2030 .irq_handler = rt2500pci_interrupt,
16222a0d
HS		 2031 .txstatus_tasklet = rt2500pci_txstatus_tasklet,
2032 .tbtt_tasklet = rt2500pci_tbtt_tasklet,
2033 .rxdone_tasklet = rt2500pci_rxdone_tasklet,
95ea3627
ID		 2034 .probe_hw = rt2500pci_probe_hw,
2035 .initialize = rt2x00pci_initialize,
2036 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2037 .get_entry_state = rt2500pci_get_entry_state,
2038 .clear_entry = rt2500pci_clear_entry,
95ea3627 2039 .set_device_state = rt2500pci_set_device_state,
95ea3627 2040 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 2041 .link_stats = rt2500pci_link_stats,
2042 .reset_tuner = rt2500pci_reset_tuner,
2043 .link_tuner = rt2500pci_link_tuner,
dbba306f
ID		 2044 .start_queue = rt2500pci_start_queue,
2045 .kick_queue = rt2500pci_kick_queue,
2046 .stop_queue = rt2500pci_stop_queue,
152a5992 2047 .flush_queue = rt2x00pci_flush_queue,
95ea3627 2048 .write_tx_desc = rt2500pci_write_tx_desc,
bd88a781 2049 .write_beacon = rt2500pci_write_beacon,
95ea3627 2050 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 2051 .config_filter = rt2500pci_config_filter,
6bb40dd1 2052 .config_intf = rt2500pci_config_intf,
72810379 2053 .config_erp = rt2500pci_config_erp,
e4ea1c40 2054 .config_ant = rt2500pci_config_ant,
95ea3627
ID		 2055 .config = rt2500pci_config,
2056};
2057
181d6902 2058static const struct data_queue_desc rt2500pci_queue_rx = {
efd2f271 2059 .entry_num = 32,
181d6902
ID		 2060 .data_size = DATA_FRAME_SIZE,
2061 .desc_size = RXD_DESC_SIZE,
b8be63ff 2062 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2063};
2064
2065static const struct data_queue_desc rt2500pci_queue_tx = {
efd2f271 2066 .entry_num = 32,
181d6902
ID		 2067 .data_size = DATA_FRAME_SIZE,
2068 .desc_size = TXD_DESC_SIZE,
b8be63ff 2069 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2070};
2071
2072static const struct data_queue_desc rt2500pci_queue_bcn = {
efd2f271 2073 .entry_num = 1,
181d6902
ID		 2074 .data_size = MGMT_FRAME_SIZE,
2075 .desc_size = TXD_DESC_SIZE,
b8be63ff 2076 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2077};
2078
2079static const struct data_queue_desc rt2500pci_queue_atim = {
efd2f271 2080 .entry_num = 8,
181d6902
ID		 2081 .data_size = DATA_FRAME_SIZE,
2082 .desc_size = TXD_DESC_SIZE,
b8be63ff 2083 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2084};
2085
95ea3627 2086static const struct rt2x00_ops rt2500pci_ops = {
04d0362e 2087 .name = KBUILD_MODNAME,
04d0362e
GW		 2088 .max_ap_intf = 1,
2089 .eeprom_size = EEPROM_SIZE,
2090 .rf_size = RF_SIZE,
2091 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2092 .extra_tx_headroom = 0,
04d0362e
GW		 2093 .rx = &rt2500pci_queue_rx,
2094 .tx = &rt2500pci_queue_tx,
2095 .bcn = &rt2500pci_queue_bcn,
2096 .atim = &rt2500pci_queue_atim,
2097 .lib = &rt2500pci_rt2x00_ops,
2098 .hw = &rt2500pci_mac80211_ops,
95ea3627 2099#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2100 .debugfs = &rt2500pci_rt2x00debug,
95ea3627
ID		 2101#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2102};
2103
2104/*
2105 * RT2500pci module information.
2106 */
a3aa1884 2107static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
e01ae27f 2108 { PCI_DEVICE(0x1814, 0x0201) },
95ea3627
ID		 2109 { 0, }
2110};
2111
2112MODULE_AUTHOR(DRV_PROJECT);
2113MODULE_VERSION(DRV_VERSION);
2114MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2115MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2116MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2117MODULE_LICENSE("GPL");
2118
e01ae27f
GW		 2119static int rt2500pci_probe(struct pci_dev *pci_dev,
2120 const struct pci_device_id *id)
2121{
2122 return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2123}
2124
95ea3627 2125static struct pci_driver rt2500pci_driver = {
2360157c 2126 .name = KBUILD_MODNAME,
95ea3627 2127 .id_table = rt2500pci_device_table,
e01ae27f 2128 .probe = rt2500pci_probe,
69202359 2129 .remove = rt2x00pci_remove,
95ea3627
ID		 2130 .suspend = rt2x00pci_suspend,
2131 .resume = rt2x00pci_resume,
2132};
2133
5b0a3b7e 2134module_pci_driver(rt2500pci_driver);
Ubuntu Hirsute Linux kernel mirror