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rt2x00: Replace statically allocated DMA buffers with mapped skb's.
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2500PCI_RFKILL
235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
dcf5475b 244#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627 245
a9450b70 246#ifdef CONFIG_RT2500PCI_LEDS
a2e1d52a 247static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
475433be
ID		 280
281static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2500pci_brightness_set;
288 led->led_dev.blink_set = rt2500pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
a9450b70
ID		 291#endif /* CONFIG_RT2500PCI_LEDS */
292
95ea3627
ID		 293/*
294 * Configuration handlers.
295 */
3a643d24
ID		 296static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
297 const unsigned int filter_flags)
298{
299 u32 reg;
300
301 /*
302 * Start configuration steps.
303 * Note that the version error will always be dropped
304 * and broadcast frames will always be accepted since
305 * there is no filter for it at this time.
306 */
307 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
308 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
309 !(filter_flags & FIF_FCSFAIL));
310 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
311 !(filter_flags & FIF_PLCPFAIL));
312 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
313 !(filter_flags & FIF_CONTROL));
314 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
315 !(filter_flags & FIF_PROMISC_IN_BSS));
316 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 317 !(filter_flags & FIF_PROMISC_IN_BSS) &&
318 !rt2x00dev->intf_ap_count);
3a643d24
ID		 319 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
320 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
321 !(filter_flags & FIF_ALLMULTI));
322 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
323 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
324}
325
6bb40dd1
ID		 326static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327 struct rt2x00_intf *intf,
328 struct rt2x00intf_conf *conf,
329 const unsigned int flags)
95ea3627 330{
e58c6aca 331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
6bb40dd1 332 unsigned int bcn_preload;
95ea3627
ID		 333 u32 reg;
334
6bb40dd1 335 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 336 /*
337 * Enable beacon config
338 */
339 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
340 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
341 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
342 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
343 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 344
6bb40dd1
ID		 345 /*
346 * Enable synchronisation.
347 */
348 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 349 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 350 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 351 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 352 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
353 }
354
355 if (flags & CONFIG_UPDATE_MAC)
356 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
357 conf->mac, sizeof(conf->mac));
358
359 if (flags & CONFIG_UPDATE_BSSID)
360 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
361 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 362}
363
3a643d24
ID		 364static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
365 struct rt2x00lib_erp *erp)
95ea3627 366{
5c58ee51 367 int preamble_mask;
95ea3627 368 u32 reg;
95ea3627 369
5c58ee51
ID		 370 /*
371 * When short preamble is enabled, we should set bit 0x08
372 */
72810379 373 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 374
375 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 376 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
377 erp->ack_timeout);
378 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
379 erp->ack_consume_time);
95ea3627
ID		 380 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
381
95ea3627 382 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 383 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627
ID		 384 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
385 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
386 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
387
388 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 389 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 390 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
391 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
392 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 395 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 396 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
398 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
399
400 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 401 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 402 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
403 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
404 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
405}
406
407static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 408 const int basic_rate_mask)
95ea3627 409{
5c58ee51 410 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 411}
412
413static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 414 struct rf_channel *rf, const int txpower)
95ea3627 415{
95ea3627
ID		 416 u8 r70;
417
95ea3627
ID		 418 /*
419 * Set TXpower.
420 */
5c58ee51 421 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 422
423 /*
424 * Switch on tuning bits.
425 * For RT2523 devices we do not need to update the R1 register.
426 */
427 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 428 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
429 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 430
431 /*
432 * For RT2525 we should first set the channel to half band higher.
433 */
434 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
435 static const u32 vals[] = {
436 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
437 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
438 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
439 0x00080d2e, 0x00080d3a
440 };
441
5c58ee51
ID		 442 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
443 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
444 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
445 if (rf->rf4)
446 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 447 }
448
5c58ee51
ID		 449 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
450 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
451 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
452 if (rf->rf4)
453 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 454
455 /*
456 * Channel 14 requires the Japan filter bit to be set.
457 */
458 r70 = 0x46;
5c58ee51 459 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 460 rt2500pci_bbp_write(rt2x00dev, 70, r70);
461
462 msleep(1);
463
464 /*
465 * Switch off tuning bits.
466 * For RT2523 devices we do not need to update the R1 register.
467 */
468 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 469 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
470 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 471 }
472
5c58ee51
ID		 473 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
474 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 475
476 /*
477 * Clear false CRC during channel switch.
478 */
5c58ee51 479 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 480}
481
482static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
483 const int txpower)
484{
485 u32 rf3;
486
487 rt2x00_rf_read(rt2x00dev, 3, &rf3);
488 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
489 rt2500pci_rf_write(rt2x00dev, 3, rf3);
490}
491
492static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 493 struct antenna_setup *ant)
95ea3627
ID		 494{
495 u32 reg;
496 u8 r14;
497 u8 r2;
498
a4fe07d9
ID		 499 /*
500 * We should never come here because rt2x00lib is supposed
501 * to catch this and send us the correct antenna explicitely.
502 */
503 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
504 ant->tx == ANTENNA_SW_DIVERSITY);
505
95ea3627
ID		 506 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
507 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
508 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
509
510 /*
511 * Configure the TX antenna.
512 */
addc81bd 513 switch (ant->tx) {
95ea3627
ID		 514 case ANTENNA_A:
515 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
516 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
517 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
518 break;
519 case ANTENNA_B:
a4fe07d9 520 default:
95ea3627
ID		 521 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
522 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
523 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
524 break;
525 }
526
527 /*
528 * Configure the RX antenna.
529 */
addc81bd 530 switch (ant->rx) {
95ea3627
ID		 531 case ANTENNA_A:
532 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
533 break;
534 case ANTENNA_B:
a4fe07d9 535 default:
95ea3627
ID		 536 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
537 break;
538 }
539
540 /*
541 * RT2525E and RT5222 need to flip TX I/Q
542 */
543 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
544 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
545 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
546 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
547 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
548
549 /*
550 * RT2525E does not need RX I/Q Flip.
551 */
552 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
553 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
554 } else {
555 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
556 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
557 }
558
559 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
560 rt2500pci_bbp_write(rt2x00dev, 14, r14);
561 rt2500pci_bbp_write(rt2x00dev, 2, r2);
562}
563
564static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 565 struct rt2x00lib_conf *libconf)
95ea3627
ID		 566{
567 u32 reg;
568
569 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 570 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 571 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
572
573 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 574 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
575 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 576 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
577
578 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 579 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
580 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 581 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
582
583 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
584 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
585 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
586 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
587
588 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 589 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
590 libconf->conf->beacon_int * 16);
591 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
592 libconf->conf->beacon_int * 16);
95ea3627
ID		 593 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
594}
595
596static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 597 struct rt2x00lib_conf *libconf,
598 const unsigned int flags)
95ea3627 599{
95ea3627 600 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 601 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 602 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 603 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
604 libconf->conf->power_level);
95ea3627 605 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 606 rt2500pci_config_txpower(rt2x00dev,
607 libconf->conf->power_level);
95ea3627 608 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 609 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 610 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 611 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 612}
613
95ea3627
ID		 614/*
615 * Link tuning
616 */
ebcf26da
ID		 617static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
618 struct link_qual *qual)
95ea3627
ID		 619{
620 u32 reg;
621
622 /*
623 * Update FCS error count from register.
624 */
625 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 626 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 627
628 /*
629 * Update False CCA count from register.
630 */
631 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 632 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 633}
634
635static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
636{
637 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
638 rt2x00dev->link.vgc_level = 0x48;
639}
640
641static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
642{
643 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
644 u8 r17;
645
646 /*
647 * To prevent collisions with MAC ASIC on chipsets
648 * up to version C the link tuning should halt after 20
6bb40dd1 649 * seconds while being associated.
95ea3627 650 */
755a957d 651 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
6bb40dd1 652 rt2x00dev->intf_associated &&
95ea3627
ID		 653 rt2x00dev->link.count > 20)
654 return;
655
656 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
657
658 /*
659 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 660 * to the dynamic CCA tuning. Chipset version D and higher
661 * should go straight to dynamic CCA tuning when they
662 * are not associated.
95ea3627 663 */
6bb40dd1
ID		 664 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
665 !rt2x00dev->intf_associated)
95ea3627
ID		 666 goto dynamic_cca_tune;
667
668 /*
669 * A too low RSSI will cause too much false CCA which will
670 * then corrupt the R17 tuning. To remidy this the tuning should
671 * be stopped (While making sure the R17 value will not exceed limits)
672 */
673 if (rssi < -80 && rt2x00dev->link.count > 20) {
674 if (r17 >= 0x41) {
675 r17 = rt2x00dev->link.vgc_level;
676 rt2500pci_bbp_write(rt2x00dev, 17, r17);
677 }
678 return;
679 }
680
681 /*
682 * Special big-R17 for short distance
683 */
684 if (rssi >= -58) {
685 if (r17 != 0x50)
686 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
687 return;
688 }
689
690 /*
691 * Special mid-R17 for middle distance
692 */
693 if (rssi >= -74) {
694 if (r17 != 0x41)
695 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
696 return;
697 }
698
699 /*
700 * Leave short or middle distance condition, restore r17
701 * to the dynamic tuning range.
702 */
703 if (r17 >= 0x41) {
704 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
705 return;
706 }
707
708dynamic_cca_tune:
709
710 /*
711 * R17 is inside the dynamic tuning range,
712 * start tuning the link based on the false cca counter.
713 */
ebcf26da 714 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 715 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
716 rt2x00dev->link.vgc_level = r17;
ebcf26da 717 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 718 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
719 rt2x00dev->link.vgc_level = r17;
720 }
721}
722
723/*
724 * Initialization functions.
725 */
837e7f24 726static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 727 struct queue_entry *entry)
95ea3627 728{
b8be63ff 729 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 730 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 731 u32 word;
732
b8be63ff 733 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 734 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
b8be63ff 735 rt2x00_desc_write(entry_priv->desc, 1, word);
95ea3627 736
b8be63ff 737 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 738 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 739 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 740}
741
837e7f24 742static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 743 struct queue_entry *entry)
95ea3627 744{
b8be63ff 745 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 746 u32 word;
747
b8be63ff 748 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 749 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
750 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 751 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 752}
753
181d6902 754static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 755{
b8be63ff 756 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 757 u32 reg;
758
95ea3627
ID		 759 /*
760 * Initialize registers.
761 */
762 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 763 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
765 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
766 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 767 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
768
b8be63ff 769 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 770 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 771 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 772 entry_priv->desc_dma);
95ea3627
ID		 773 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
774
b8be63ff 775 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 776 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 777 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 778 entry_priv->desc_dma);
95ea3627
ID		 779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
780
b8be63ff 781 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 784 entry_priv->desc_dma);
95ea3627
ID		 785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786
b8be63ff 787 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 790 entry_priv->desc_dma);
95ea3627
ID		 791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
792
793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
794 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
797
b8be63ff 798 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 799 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 800 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801 entry_priv->desc_dma);
95ea3627
ID		 802 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
803
804 return 0;
805}
806
807static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
808{
809 u32 reg;
810
811 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
813 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
814 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
815
816 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
817 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
818 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
819 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
820 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
821
822 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
823 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
824 rt2x00dev->rx->data_size / 128);
825 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
826
827 /*
828 * Always use CWmin and CWmax set in descriptor.
829 */
830 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
831 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
832 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
833
834 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
835
836 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
837 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
838 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
839 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
840 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
841 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
842 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
843 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
844 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
845 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
846
847 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
848 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
849 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
850 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
851 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
852 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
853
854 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
855 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
856 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
857 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
858 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
859 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
860
861 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
862 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
863 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
864 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
865 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
866 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
867
868 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
869 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
870 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
871 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
872 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
873 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
874 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
875 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
876 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
877 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
878
879 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
880 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
881 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
882 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
883 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
884 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
885 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
886 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
887 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
888
889 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
890
891 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
892 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
893
894 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
895 return -EBUSY;
896
897 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
898 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
899
900 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
901 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
902 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
903
904 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
905 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
906 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
907 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
908 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
909 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
910 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
911 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
912
913 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
914
915 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
916
917 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
918 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
919 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
920 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
921 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
922
923 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
924 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
925 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
926 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
927
928 /*
929 * We must clear the FCS and FIFO error count.
930 * These registers are cleared on read,
931 * so we may pass a useless variable to store the value.
932 */
933 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
934 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
935
936 return 0;
937}
938
2b08da3f 939static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 940{
941 unsigned int i;
95ea3627
ID		 942 u8 value;
943
944 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
945 rt2500pci_bbp_read(rt2x00dev, 0, &value);
946 if ((value != 0xff) && (value != 0x00))
2b08da3f 947 return 0;
95ea3627
ID		 948 udelay(REGISTER_BUSY_DELAY);
949 }
950
951 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
952 return -EACCES;
2b08da3f
ID		 953}
954
955static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
956{
957 unsigned int i;
958 u16 eeprom;
959 u8 reg_id;
960 u8 value;
961
962 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
963 return -EACCES;
95ea3627 964
95ea3627
ID		 965 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
966 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
967 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
968 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
969 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
970 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
971 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
972 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
973 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
974 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
975 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
976 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
977 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
978 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
979 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
980 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
981 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
982 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
983 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
984 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
985 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
986 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
987 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
988 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
989 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
990 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
991 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
992 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
993 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
994 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
995
95ea3627
ID		 996 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
997 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
998
999 if (eeprom != 0xffff && eeprom != 0x0000) {
1000 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1001 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1002 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1003 }
1004 }
95ea3627
ID		 1005
1006 return 0;
1007}
1008
1009/*
1010 * Device state switch handlers.
1011 */
1012static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1013 enum dev_state state)
1014{
1015 u32 reg;
1016
1017 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1018 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 1019 (state == STATE_RADIO_RX_OFF) ||
1020 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1021 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1022}
1023
1024static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1025 enum dev_state state)
1026{
1027 int mask = (state == STATE_RADIO_IRQ_OFF);
1028 u32 reg;
1029
1030 /*
1031 * When interrupts are being enabled, the interrupt registers
1032 * should clear the register to assure a clean state.
1033 */
1034 if (state == STATE_RADIO_IRQ_ON) {
1035 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1036 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1037 }
1038
1039 /*
1040 * Only toggle the interrupts bits we are going to use.
1041 * Non-checked interrupt bits are disabled by default.
1042 */
1043 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1044 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1045 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1046 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1047 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1048 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1049 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1050}
1051
1052static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1053{
1054 /*
1055 * Initialize all registers.
1056 */
2b08da3f
ID		 1057 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1058 rt2500pci_init_registers(rt2x00dev) ||
1059 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1060 return -EIO;
95ea3627 1061
95ea3627
ID		 1062 return 0;
1063}
1064
1065static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1066{
1067 u32 reg;
1068
95ea3627
ID		 1069 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1070
1071 /*
1072 * Disable synchronisation.
1073 */
1074 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1075
1076 /*
1077 * Cancel RX and TX.
1078 */
1079 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1080 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1081 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
95ea3627
ID		 1082}
1083
1084static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1085 enum dev_state state)
1086{
1087 u32 reg;
1088 unsigned int i;
1089 char put_to_sleep;
1090 char bbp_state;
1091 char rf_state;
1092
1093 put_to_sleep = (state != STATE_AWAKE);
1094
1095 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1096 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1097 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1098 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1099 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1100 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1101
1102 /*
1103 * Device is not guaranteed to be in the requested state yet.
1104 * We must wait until the register indicates that the
1105 * device has entered the correct state.
1106 */
1107 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1108 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1109 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1110 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1111 if (bbp_state == state && rf_state == state)
1112 return 0;
1113 msleep(10);
1114 }
1115
95ea3627
ID		 1116 return -EBUSY;
1117}
1118
1119static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1120 enum dev_state state)
1121{
1122 int retval = 0;
1123
1124 switch (state) {
1125 case STATE_RADIO_ON:
1126 retval = rt2500pci_enable_radio(rt2x00dev);
1127 break;
1128 case STATE_RADIO_OFF:
1129 rt2500pci_disable_radio(rt2x00dev);
1130 break;
1131 case STATE_RADIO_RX_ON:
61667d8d 1132 case STATE_RADIO_RX_ON_LINK:
95ea3627 1133 case STATE_RADIO_RX_OFF:
61667d8d 1134 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1135 rt2500pci_toggle_rx(rt2x00dev, state);
1136 break;
1137 case STATE_RADIO_IRQ_ON:
1138 case STATE_RADIO_IRQ_OFF:
1139 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1140 break;
1141 case STATE_DEEP_SLEEP:
1142 case STATE_SLEEP:
1143 case STATE_STANDBY:
1144 case STATE_AWAKE:
1145 retval = rt2500pci_set_state(rt2x00dev, state);
1146 break;
1147 default:
1148 retval = -ENOTSUPP;
1149 break;
1150 }
1151
2b08da3f
ID		 1152 if (unlikely(retval))
1153 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1154 state, retval);
1155
95ea3627
ID		 1156 return retval;
1157}
1158
1159/*
1160 * TX descriptor initialization
1161 */
1162static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1163 struct sk_buff *skb,
61486e0f 1164 struct txentry_desc *txdesc)
95ea3627 1165{
181d6902 1166 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1167 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1168 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1169 u32 word;
1170
1171 /*
1172 * Start writing the descriptor words.
1173 */
4de36fe5 1174 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1175 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1176 rt2x00_desc_write(entry_priv->desc, 1, word);
1177
95ea3627
ID		 1178 rt2x00_desc_read(txd, 2, &word);
1179 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1180 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1181 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1182 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1183 rt2x00_desc_write(txd, 2, word);
1184
1185 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1186 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1187 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1190 rt2x00_desc_write(txd, 3, word);
1191
1192 rt2x00_desc_read(txd, 10, &word);
1193 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1194 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1195 rt2x00_desc_write(txd, 10, word);
1196
1197 rt2x00_desc_read(txd, 0, &word);
1198 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1199 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1200 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1201 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1202 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1203 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1204 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1205 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1206 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902 1207 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
95ea3627 1208 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1209 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1210 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1211 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627
ID		 1212 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1213 rt2x00_desc_write(txd, 0, word);
1214}
1215
1216/*
1217 * TX data initialization
1218 */
1219static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1220 const enum data_queue_qid queue)
95ea3627
ID		 1221{
1222 u32 reg;
1223
e58c6aca 1224 if (queue == QID_BEACON) {
95ea3627
ID		 1225 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1226 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1227 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1228 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1229 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1230 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1231 }
1232 return;
1233 }
1234
1235 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1236 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1237 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1238 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1239 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1240}
1241
1242/*
1243 * RX control handlers
1244 */
181d6902
ID		 1245static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1246 struct rxdone_entry_desc *rxdesc)
95ea3627 1247{
b8be63ff 1248 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1249 u32 word0;
1250 u32 word2;
1251
b8be63ff
ID		 1252 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1253 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1254
4150c572 1255 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1256 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1257 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1258 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1259
89993890
ID		 1260 /*
1261 * Obtain the status about this packet.
1262 * When frame was received with an OFDM bitrate,
1263 * the signal is the PLCP value. If it was received with
1264 * a CCK bitrate the signal is the rate in 100kbit/s.
1265 */
181d6902
ID		 1266 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1267 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1268 entry->queue->rt2x00dev->rssi_offset;
181d6902 1269 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1270
19d30e02
ID		 1271 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1272 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1273 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1274 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1275}
1276
1277/*
1278 * Interrupt functions.
1279 */
181d6902 1280static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1281 const enum data_queue_qid queue_idx)
95ea3627 1282{
181d6902 1283 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1284 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1285 struct queue_entry *entry;
1286 struct txdone_entry_desc txdesc;
95ea3627 1287 u32 word;
95ea3627 1288
181d6902
ID		 1289 while (!rt2x00queue_empty(queue)) {
1290 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1291 entry_priv = entry->priv_data;
1292 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1293
1294 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1295 !rt2x00_get_field32(word, TXD_W0_VALID))
1296 break;
1297
1298 /*
1299 * Obtain the status about this packet.
1300 */
fb55f4d1
ID		 1301 txdesc.flags = 0;
1302 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1303 case 0: /* Success */
1304 case 1: /* Success with retry */
1305 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1306 break;
1307 case 2: /* Failure, excessive retries */
1308 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1309 /* Don't break, this is a failed frame! */
1310 default: /* Failure */
1311 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1312 }
181d6902 1313 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1314
181d6902 1315 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1316 }
95ea3627
ID		 1317}
1318
1319static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1320{
1321 struct rt2x00_dev *rt2x00dev = dev_instance;
1322 u32 reg;
1323
1324 /*
1325 * Get the interrupt sources & saved to local variable.
1326 * Write register value back to clear pending interrupts.
1327 */
1328 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1329 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1330
1331 if (!reg)
1332 return IRQ_NONE;
1333
1334 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1335 return IRQ_HANDLED;
1336
1337 /*
1338 * Handle interrupts, walk through all bits
1339 * and run the tasks, the bits are checked in order of
1340 * priority.
1341 */
1342
1343 /*
1344 * 1 - Beacon timer expired interrupt.
1345 */
1346 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1347 rt2x00lib_beacondone(rt2x00dev);
1348
1349 /*
1350 * 2 - Rx ring done interrupt.
1351 */
1352 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1353 rt2x00pci_rxdone(rt2x00dev);
1354
1355 /*
1356 * 3 - Atim ring transmit done interrupt.
1357 */
1358 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1359 rt2500pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1360
1361 /*
1362 * 4 - Priority ring transmit done interrupt.
1363 */
1364 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1365 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1366
1367 /*
1368 * 5 - Tx ring transmit done interrupt.
1369 */
1370 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1371 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1372
1373 return IRQ_HANDLED;
1374}
1375
1376/*
1377 * Device probe functions.
1378 */
1379static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1380{
1381 struct eeprom_93cx6 eeprom;
1382 u32 reg;
1383 u16 word;
1384 u8 *mac;
1385
1386 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1387
1388 eeprom.data = rt2x00dev;
1389 eeprom.register_read = rt2500pci_eepromregister_read;
1390 eeprom.register_write = rt2500pci_eepromregister_write;
1391 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1392 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1393 eeprom.reg_data_in = 0;
1394 eeprom.reg_data_out = 0;
1395 eeprom.reg_data_clock = 0;
1396 eeprom.reg_chip_select = 0;
1397
1398 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1399 EEPROM_SIZE / sizeof(u16));
1400
1401 /*
1402 * Start validation of the data that has been read.
1403 */
1404 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1405 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1406 DECLARE_MAC_BUF(macbuf);
1407
95ea3627 1408 random_ether_addr(mac);
0795af57
JP		 1409 EEPROM(rt2x00dev, "MAC: %s\n",
1410 print_mac(macbuf, mac));
95ea3627
ID		 1411 }
1412
1413 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1414 if (word == 0xffff) {
1415 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1416 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1417 ANTENNA_SW_DIVERSITY);
1418 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1419 ANTENNA_SW_DIVERSITY);
1420 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1421 LED_MODE_DEFAULT);
95ea3627
ID		 1422 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1423 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1424 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1425 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1426 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1427 }
1428
1429 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1430 if (word == 0xffff) {
1431 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1432 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1433 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1434 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1435 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1436 }
1437
1438 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1439 if (word == 0xffff) {
1440 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1441 DEFAULT_RSSI_OFFSET);
1442 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1443 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1444 }
1445
1446 return 0;
1447}
1448
1449static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1450{
1451 u32 reg;
1452 u16 value;
1453 u16 eeprom;
1454
1455 /*
1456 * Read EEPROM word for configuration.
1457 */
1458 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1459
1460 /*
1461 * Identify RF chipset.
1462 */
1463 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1464 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1465 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1466
1467 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1468 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1469 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1470 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1471 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1472 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1473 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1474 return -ENODEV;
1475 }
1476
1477 /*
1478 * Identify default antenna configuration.
1479 */
addc81bd 1480 rt2x00dev->default_ant.tx =
95ea3627 1481 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1482 rt2x00dev->default_ant.rx =
95ea3627
ID		 1483 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1484
1485 /*
1486 * Store led mode, for correct led behaviour.
1487 */
a9450b70
ID		 1488#ifdef CONFIG_RT2500PCI_LEDS
1489 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1490
475433be
ID		 1491 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1492 if (value == LED_MODE_TXRX_ACTIVITY)
1493 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1494 LED_TYPE_ACTIVITY);
a9450b70 1495#endif /* CONFIG_RT2500PCI_LEDS */
95ea3627
ID		 1496
1497 /*
1498 * Detect if this device has an hardware controlled radio.
1499 */
81873e9c 1500#ifdef CONFIG_RT2500PCI_RFKILL
95ea3627 1501 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1502 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1503#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 1504
1505 /*
1506 * Check if the BBP tuning should be enabled.
1507 */
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1509
1510 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1511 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1512
1513 /*
1514 * Read the RSSI <-> dBm offset information.
1515 */
1516 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1517 rt2x00dev->rssi_offset =
1518 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1519
1520 return 0;
1521}
1522
1523/*
1524 * RF value list for RF2522
1525 * Supports: 2.4 GHz
1526 */
1527static const struct rf_channel rf_vals_bg_2522[] = {
1528 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1529 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1530 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1531 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1532 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1533 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1534 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1535 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1536 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1537 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1538 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1539 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1540 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1541 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1542};
1543
1544/*
1545 * RF value list for RF2523
1546 * Supports: 2.4 GHz
1547 */
1548static const struct rf_channel rf_vals_bg_2523[] = {
1549 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1550 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1551 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1552 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1553 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1554 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1555 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1556 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1557 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1558 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1559 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1560 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1561 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1562 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1563};
1564
1565/*
1566 * RF value list for RF2524
1567 * Supports: 2.4 GHz
1568 */
1569static const struct rf_channel rf_vals_bg_2524[] = {
1570 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1571 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1572 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1573 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1574 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1575 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1576 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1577 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1578 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1579 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1580 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1581 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1582 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1583 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1584};
1585
1586/*
1587 * RF value list for RF2525
1588 * Supports: 2.4 GHz
1589 */
1590static const struct rf_channel rf_vals_bg_2525[] = {
1591 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1592 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1593 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1594 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1595 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1596 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1597 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1598 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1599 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1600 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1601 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1602 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1603 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1604 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1605};
1606
1607/*
1608 * RF value list for RF2525e
1609 * Supports: 2.4 GHz
1610 */
1611static const struct rf_channel rf_vals_bg_2525e[] = {
1612 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1613 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1614 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1615 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1616 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1617 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1618 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1619 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1620 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1621 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1622 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1623 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1624 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1625 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1626};
1627
1628/*
1629 * RF value list for RF5222
1630 * Supports: 2.4 GHz & 5.2 GHz
1631 */
1632static const struct rf_channel rf_vals_5222[] = {
1633 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1634 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1635 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1636 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1637 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1638 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1639 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1640 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1641 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1642 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1643 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1644 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1645 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1646 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1647
1648 /* 802.11 UNI / HyperLan 2 */
1649 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1650 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1651 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1652 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1653 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1654 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1655 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1656 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1657
1658 /* 802.11 HyperLan 2 */
1659 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1660 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1661 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1662 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1663 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1664 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1665 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1666 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1667 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1668 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1669
1670 /* 802.11 UNII */
1671 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1672 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1673 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1674 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1675 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1676};
1677
1678static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1679{
1680 struct hw_mode_spec *spec = &rt2x00dev->spec;
1681 u8 *txpower;
1682 unsigned int i;
1683
1684 /*
1685 * Initialize all hw fields.
1686 */
566bfe5a
BR		 1687 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1688 IEEE80211_HW_SIGNAL_DBM;
1689
95ea3627 1690 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 1691
14a3bf89 1692 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1693 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1694 rt2x00_eeprom_addr(rt2x00dev,
1695 EEPROM_MAC_ADDR_0));
1696
1697 /*
1698 * Convert tx_power array in eeprom.
1699 */
1700 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1701 for (i = 0; i < 14; i++)
1702 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1703
1704 /*
1705 * Initialize hw_mode information.
1706 */
31562e80
ID		 1707 spec->supported_bands = SUPPORT_BAND_2GHZ;
1708 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1709 spec->tx_power_a = NULL;
1710 spec->tx_power_bg = txpower;
1711 spec->tx_power_default = DEFAULT_TXPOWER;
1712
1713 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1714 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1715 spec->channels = rf_vals_bg_2522;
1716 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1717 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1718 spec->channels = rf_vals_bg_2523;
1719 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1720 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1721 spec->channels = rf_vals_bg_2524;
1722 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1723 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1724 spec->channels = rf_vals_bg_2525;
1725 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1726 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1727 spec->channels = rf_vals_bg_2525e;
1728 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
31562e80 1729 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1730 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1731 spec->channels = rf_vals_5222;
95ea3627
ID		 1732 }
1733}
1734
1735static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1736{
1737 int retval;
1738
1739 /*
1740 * Allocate eeprom data.
1741 */
1742 retval = rt2500pci_validate_eeprom(rt2x00dev);
1743 if (retval)
1744 return retval;
1745
1746 retval = rt2500pci_init_eeprom(rt2x00dev);
1747 if (retval)
1748 return retval;
1749
1750 /*
1751 * Initialize hw specifications.
1752 */
1753 rt2500pci_probe_hw_mode(rt2x00dev);
1754
1755 /*
c4da0048 1756 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1757 */
181d6902 1758 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1759 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1760
1761 /*
1762 * Set the rssi offset.
1763 */
1764 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1765
1766 return 0;
1767}
1768
1769/*
1770 * IEEE80211 stack callback functions.
1771 */
1772static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1773 u32 short_retry, u32 long_retry)
1774{
1775 struct rt2x00_dev *rt2x00dev = hw->priv;
1776 u32 reg;
1777
1778 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1779 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1780 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1781 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1782
1783 return 0;
1784}
1785
1786static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1787{
1788 struct rt2x00_dev *rt2x00dev = hw->priv;
1789 u64 tsf;
1790 u32 reg;
1791
1792 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1793 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1794 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1795 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1796
1797 return tsf;
1798}
1799
e039fa4a 1800static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
5957da4c
ID		 1801{
1802 struct rt2x00_dev *rt2x00dev = hw->priv;
e039fa4a
JB		 1803 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1804 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
b8be63ff 1805 struct queue_entry_priv_pci *entry_priv;
5957da4c 1806 struct skb_frame_desc *skbdesc;
7050ec82 1807 struct txentry_desc txdesc;
8af244cc 1808 u32 reg;
5957da4c
ID		 1809
1810 if (unlikely(!intf->beacon))
1811 return -ENOBUFS;
1812
b8be63ff 1813 entry_priv = intf->beacon->priv_data;
5957da4c 1814
7050ec82
ID		 1815 /*
1816 * Copy all TX descriptor information into txdesc,
1817 * after that we are free to use the skb->cb array
1818 * for our information.
1819 */
1820 intf->beacon->skb = skb;
e039fa4a 1821 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
7050ec82 1822
5957da4c
ID		 1823 /*
1824 * Fill in skb descriptor
1825 */
1826 skbdesc = get_skb_frame_desc(skb);
1827 memset(skbdesc, 0, sizeof(*skbdesc));
b8be63ff 1828 skbdesc->desc = entry_priv->desc;
5957da4c
ID		 1829 skbdesc->desc_len = intf->beacon->queue->desc_size;
1830 skbdesc->entry = intf->beacon;
1831
8af244cc
ID		 1832 /*
1833 * Disable beaconing while we are reloading the beacon data,
1834 * otherwise we might be sending out invalid data.
1835 */
1836 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1837 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1838 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1839 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1840 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1841
5957da4c
ID		 1842 /*
1843 * Enable beacon generation.
1844 * Write entire beacon with descriptor to register,
1845 * and kick the beacon generator.
1846 */
c4da0048 1847 rt2x00queue_map_txskb(rt2x00dev, intf->beacon->skb);
7050ec82 1848 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
e58c6aca 1849 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
5957da4c
ID		 1850
1851 return 0;
1852}
1853
95ea3627
ID		 1854static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1855{
1856 struct rt2x00_dev *rt2x00dev = hw->priv;
1857 u32 reg;
1858
1859 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1860 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1861}
1862
1863static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1864 .tx = rt2x00mac_tx,
4150c572
JB		 1865 .start = rt2x00mac_start,
1866 .stop = rt2x00mac_stop,
95ea3627
ID		 1867 .add_interface = rt2x00mac_add_interface,
1868 .remove_interface = rt2x00mac_remove_interface,
1869 .config = rt2x00mac_config,
1870 .config_interface = rt2x00mac_config_interface,
3a643d24 1871 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1872 .get_stats = rt2x00mac_get_stats,
1873 .set_retry_limit = rt2500pci_set_retry_limit,
471b3efd 1874 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1875 .conf_tx = rt2x00mac_conf_tx,
1876 .get_tx_stats = rt2x00mac_get_tx_stats,
1877 .get_tsf = rt2500pci_get_tsf,
5957da4c 1878 .beacon_update = rt2500pci_beacon_update,
95ea3627
ID		 1879 .tx_last_beacon = rt2500pci_tx_last_beacon,
1880};
1881
1882static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1883 .irq_handler = rt2500pci_interrupt,
1884 .probe_hw = rt2500pci_probe_hw,
1885 .initialize = rt2x00pci_initialize,
1886 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1887 .init_rxentry = rt2500pci_init_rxentry,
1888 .init_txentry = rt2500pci_init_txentry,
95ea3627 1889 .set_device_state = rt2500pci_set_device_state,
95ea3627 1890 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 1891 .link_stats = rt2500pci_link_stats,
1892 .reset_tuner = rt2500pci_reset_tuner,
1893 .link_tuner = rt2500pci_link_tuner,
1894 .write_tx_desc = rt2500pci_write_tx_desc,
1895 .write_tx_data = rt2x00pci_write_tx_data,
1896 .kick_tx_queue = rt2500pci_kick_tx_queue,
1897 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1898 .config_filter = rt2500pci_config_filter,
6bb40dd1 1899 .config_intf = rt2500pci_config_intf,
72810379 1900 .config_erp = rt2500pci_config_erp,
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ID		 1901 .config = rt2500pci_config,
1902};
1903
181d6902
ID		 1904static const struct data_queue_desc rt2500pci_queue_rx = {
1905 .entry_num = RX_ENTRIES,
1906 .data_size = DATA_FRAME_SIZE,
1907 .desc_size = RXD_DESC_SIZE,
b8be63ff 1908 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1909};
1910
1911static const struct data_queue_desc rt2500pci_queue_tx = {
1912 .entry_num = TX_ENTRIES,
1913 .data_size = DATA_FRAME_SIZE,
1914 .desc_size = TXD_DESC_SIZE,
b8be63ff 1915 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1916};
1917
1918static const struct data_queue_desc rt2500pci_queue_bcn = {
1919 .entry_num = BEACON_ENTRIES,
1920 .data_size = MGMT_FRAME_SIZE,
1921 .desc_size = TXD_DESC_SIZE,
b8be63ff 1922 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1923};
1924
1925static const struct data_queue_desc rt2500pci_queue_atim = {
1926 .entry_num = ATIM_ENTRIES,
1927 .data_size = DATA_FRAME_SIZE,
1928 .desc_size = TXD_DESC_SIZE,
b8be63ff 1929 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1930};
1931
95ea3627 1932static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1933 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1934 .max_sta_intf = 1,
1935 .max_ap_intf = 1,
95ea3627
ID		 1936 .eeprom_size = EEPROM_SIZE,
1937 .rf_size = RF_SIZE,
61448f88 1938 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 1939 .rx = &rt2500pci_queue_rx,
1940 .tx = &rt2500pci_queue_tx,
1941 .bcn = &rt2500pci_queue_bcn,
1942 .atim = &rt2500pci_queue_atim,
95ea3627
ID		 1943 .lib = &rt2500pci_rt2x00_ops,
1944 .hw = &rt2500pci_mac80211_ops,
1945#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1946 .debugfs = &rt2500pci_rt2x00debug,
1947#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1948};
1949
1950/*
1951 * RT2500pci module information.
1952 */
1953static struct pci_device_id rt2500pci_device_table[] = {
1954 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1955 { 0, }
1956};
1957
1958MODULE_AUTHOR(DRV_PROJECT);
1959MODULE_VERSION(DRV_VERSION);
1960MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1961MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1962MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1963MODULE_LICENSE("GPL");
1964
1965static struct pci_driver rt2500pci_driver = {
2360157c 1966 .name = KBUILD_MODNAME,
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ID		 1967 .id_table = rt2500pci_device_table,
1968 .probe = rt2x00pci_probe,
1969 .remove = __devexit_p(rt2x00pci_remove),
1970 .suspend = rt2x00pci_suspend,
1971 .resume = rt2x00pci_resume,
1972};
1973
1974static int __init rt2500pci_init(void)
1975{
1976 return pci_register_driver(&rt2500pci_driver);
1977}
1978
1979static void __exit rt2500pci_exit(void)
1980{
1981 pci_unregister_driver(&rt2500pci_driver);
1982}
1983
1984module_init(rt2500pci_init);
1985module_exit(rt2500pci_exit);
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