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[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
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95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2500pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
58169529 234#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627
ID		 235static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2500pci_rfkill_poll NULL
58169529 244#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627 245
771fd565 246#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 247static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
475433be
ID		 280
281static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2500pci_brightness_set;
288 led->led_dev.blink_set = rt2500pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
771fd565 291#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 292
95ea3627
ID		 293/*
294 * Configuration handlers.
295 */
3a643d24
ID		 296static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
297 const unsigned int filter_flags)
298{
299 u32 reg;
300
301 /*
302 * Start configuration steps.
303 * Note that the version error will always be dropped
304 * and broadcast frames will always be accepted since
305 * there is no filter for it at this time.
306 */
307 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
308 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
309 !(filter_flags & FIF_FCSFAIL));
310 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
311 !(filter_flags & FIF_PLCPFAIL));
312 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
313 !(filter_flags & FIF_CONTROL));
314 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
315 !(filter_flags & FIF_PROMISC_IN_BSS));
316 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 317 !(filter_flags & FIF_PROMISC_IN_BSS) &&
318 !rt2x00dev->intf_ap_count);
3a643d24
ID		 319 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
320 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
321 !(filter_flags & FIF_ALLMULTI));
322 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
323 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
324}
325
6bb40dd1
ID		 326static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327 struct rt2x00_intf *intf,
328 struct rt2x00intf_conf *conf,
329 const unsigned int flags)
95ea3627 330{
e58c6aca 331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
6bb40dd1 332 unsigned int bcn_preload;
95ea3627
ID		 333 u32 reg;
334
6bb40dd1 335 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 336 /*
337 * Enable beacon config
338 */
339 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
340 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
341 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
342 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
343 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 344
6bb40dd1
ID		 345 /*
346 * Enable synchronisation.
347 */
348 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 349 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 350 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 351 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 352 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
353 }
354
355 if (flags & CONFIG_UPDATE_MAC)
356 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
357 conf->mac, sizeof(conf->mac));
358
359 if (flags & CONFIG_UPDATE_BSSID)
360 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
361 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 362}
363
3a643d24
ID		 364static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
365 struct rt2x00lib_erp *erp)
95ea3627 366{
5c58ee51 367 int preamble_mask;
95ea3627 368 u32 reg;
95ea3627 369
5c58ee51
ID		 370 /*
371 * When short preamble is enabled, we should set bit 0x08
372 */
72810379 373 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 374
375 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 376 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
377 erp->ack_timeout);
378 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
379 erp->ack_consume_time);
95ea3627
ID		 380 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
381
95ea3627 382 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 383 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627
ID		 384 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
385 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
386 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
387
388 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 389 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 390 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
391 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
392 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 395 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 396 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
398 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
399
400 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 401 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 402 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
403 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
404 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
405}
406
407static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 408 const int basic_rate_mask)
95ea3627 409{
5c58ee51 410 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 411}
412
413static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 414 struct rf_channel *rf, const int txpower)
95ea3627 415{
95ea3627
ID		 416 u8 r70;
417
95ea3627
ID		 418 /*
419 * Set TXpower.
420 */
5c58ee51 421 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 422
423 /*
424 * Switch on tuning bits.
425 * For RT2523 devices we do not need to update the R1 register.
426 */
427 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
5c58ee51
ID		 428 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
429 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 430
431 /*
432 * For RT2525 we should first set the channel to half band higher.
433 */
434 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
435 static const u32 vals[] = {
436 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
437 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
438 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
439 0x00080d2e, 0x00080d3a
440 };
441
5c58ee51
ID		 442 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
443 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
444 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
445 if (rf->rf4)
446 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 447 }
448
5c58ee51
ID		 449 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
450 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
451 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
452 if (rf->rf4)
453 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 454
455 /*
456 * Channel 14 requires the Japan filter bit to be set.
457 */
458 r70 = 0x46;
5c58ee51 459 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 460 rt2500pci_bbp_write(rt2x00dev, 70, r70);
461
462 msleep(1);
463
464 /*
465 * Switch off tuning bits.
466 * For RT2523 devices we do not need to update the R1 register.
467 */
468 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
5c58ee51
ID		 469 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
470 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 471 }
472
5c58ee51
ID		 473 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
474 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 475
476 /*
477 * Clear false CRC during channel switch.
478 */
5c58ee51 479 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 480}
481
482static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
483 const int txpower)
484{
485 u32 rf3;
486
487 rt2x00_rf_read(rt2x00dev, 3, &rf3);
488 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
489 rt2500pci_rf_write(rt2x00dev, 3, rf3);
490}
491
492static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 493 struct antenna_setup *ant)
95ea3627
ID		 494{
495 u32 reg;
496 u8 r14;
497 u8 r2;
498
a4fe07d9
ID		 499 /*
500 * We should never come here because rt2x00lib is supposed
501 * to catch this and send us the correct antenna explicitely.
502 */
503 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
504 ant->tx == ANTENNA_SW_DIVERSITY);
505
95ea3627
ID		 506 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
507 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
508 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
509
510 /*
511 * Configure the TX antenna.
512 */
addc81bd 513 switch (ant->tx) {
95ea3627
ID		 514 case ANTENNA_A:
515 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
516 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
517 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
518 break;
519 case ANTENNA_B:
a4fe07d9 520 default:
95ea3627
ID		 521 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
522 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
523 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
524 break;
525 }
526
527 /*
528 * Configure the RX antenna.
529 */
addc81bd 530 switch (ant->rx) {
95ea3627
ID		 531 case ANTENNA_A:
532 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
533 break;
534 case ANTENNA_B:
a4fe07d9 535 default:
95ea3627
ID		 536 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
537 break;
538 }
539
540 /*
541 * RT2525E and RT5222 need to flip TX I/Q
542 */
543 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
544 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
545 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
546 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
547 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
548
549 /*
550 * RT2525E does not need RX I/Q Flip.
551 */
552 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
553 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
554 } else {
555 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
556 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
557 }
558
559 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
560 rt2500pci_bbp_write(rt2x00dev, 14, r14);
561 rt2500pci_bbp_write(rt2x00dev, 2, r2);
562}
563
564static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 565 struct rt2x00lib_conf *libconf)
95ea3627
ID		 566{
567 u32 reg;
568
569 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 570 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 571 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
572
573 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 574 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
575 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 576 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
577
578 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 579 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
580 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 581 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
582
583 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
584 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
585 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
586 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
587
588 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 589 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
590 libconf->conf->beacon_int * 16);
591 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
592 libconf->conf->beacon_int * 16);
95ea3627
ID		 593 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
594}
595
596static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 597 struct rt2x00lib_conf *libconf,
598 const unsigned int flags)
95ea3627 599{
95ea3627 600 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 601 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 602 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 603 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
604 libconf->conf->power_level);
95ea3627 605 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51
ID		 606 rt2500pci_config_txpower(rt2x00dev,
607 libconf->conf->power_level);
95ea3627 608 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 609 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 610 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 611 rt2500pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 612}
613
95ea3627
ID		 614/*
615 * Link tuning
616 */
ebcf26da
ID		 617static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
618 struct link_qual *qual)
95ea3627
ID		 619{
620 u32 reg;
621
622 /*
623 * Update FCS error count from register.
624 */
625 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 626 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 627
628 /*
629 * Update False CCA count from register.
630 */
631 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 632 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 633}
634
635static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
636{
637 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
638 rt2x00dev->link.vgc_level = 0x48;
639}
640
641static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
642{
643 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
644 u8 r17;
645
646 /*
647 * To prevent collisions with MAC ASIC on chipsets
648 * up to version C the link tuning should halt after 20
6bb40dd1 649 * seconds while being associated.
95ea3627 650 */
755a957d 651 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
6bb40dd1 652 rt2x00dev->intf_associated &&
95ea3627
ID		 653 rt2x00dev->link.count > 20)
654 return;
655
656 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
657
658 /*
659 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 660 * to the dynamic CCA tuning. Chipset version D and higher
661 * should go straight to dynamic CCA tuning when they
662 * are not associated.
95ea3627 663 */
6bb40dd1
ID		 664 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
665 !rt2x00dev->intf_associated)
95ea3627
ID		 666 goto dynamic_cca_tune;
667
668 /*
669 * A too low RSSI will cause too much false CCA which will
670 * then corrupt the R17 tuning. To remidy this the tuning should
671 * be stopped (While making sure the R17 value will not exceed limits)
672 */
673 if (rssi < -80 && rt2x00dev->link.count > 20) {
674 if (r17 >= 0x41) {
675 r17 = rt2x00dev->link.vgc_level;
676 rt2500pci_bbp_write(rt2x00dev, 17, r17);
677 }
678 return;
679 }
680
681 /*
682 * Special big-R17 for short distance
683 */
684 if (rssi >= -58) {
685 if (r17 != 0x50)
686 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
687 return;
688 }
689
690 /*
691 * Special mid-R17 for middle distance
692 */
693 if (rssi >= -74) {
694 if (r17 != 0x41)
695 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
696 return;
697 }
698
699 /*
700 * Leave short or middle distance condition, restore r17
701 * to the dynamic tuning range.
702 */
703 if (r17 >= 0x41) {
704 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
705 return;
706 }
707
708dynamic_cca_tune:
709
710 /*
711 * R17 is inside the dynamic tuning range,
712 * start tuning the link based on the false cca counter.
713 */
ebcf26da 714 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
95ea3627
ID		 715 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
716 rt2x00dev->link.vgc_level = r17;
ebcf26da 717 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
95ea3627
ID		 718 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
719 rt2x00dev->link.vgc_level = r17;
720 }
721}
722
723/*
724 * Initialization functions.
725 */
837e7f24 726static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 727 struct queue_entry *entry)
95ea3627 728{
b8be63ff 729 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 730 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 731 u32 word;
732
b8be63ff 733 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 734 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
b8be63ff 735 rt2x00_desc_write(entry_priv->desc, 1, word);
95ea3627 736
b8be63ff 737 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 738 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 739 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 740}
741
837e7f24 742static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 743 struct queue_entry *entry)
95ea3627 744{
b8be63ff 745 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 746 u32 word;
747
b8be63ff 748 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 749 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
750 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 751 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 752}
753
181d6902 754static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 755{
b8be63ff 756 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 757 u32 reg;
758
95ea3627
ID		 759 /*
760 * Initialize registers.
761 */
762 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 763 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
764 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
765 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
766 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 767 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
768
b8be63ff 769 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 770 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 771 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 772 entry_priv->desc_dma);
95ea3627
ID		 773 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
774
b8be63ff 775 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 776 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 777 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 778 entry_priv->desc_dma);
95ea3627
ID		 779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
780
b8be63ff 781 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 784 entry_priv->desc_dma);
95ea3627
ID		 785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786
b8be63ff 787 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 790 entry_priv->desc_dma);
95ea3627
ID		 791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
792
793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
794 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
797
b8be63ff 798 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 799 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 800 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801 entry_priv->desc_dma);
95ea3627
ID		 802 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
803
804 return 0;
805}
806
807static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
808{
809 u32 reg;
810
811 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
813 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
814 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
815
816 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
817 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
818 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
819 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
820 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
821
822 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
823 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
824 rt2x00dev->rx->data_size / 128);
825 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
826
827 /*
828 * Always use CWmin and CWmax set in descriptor.
829 */
830 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
831 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
832 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
833
1f909162
ID		 834 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
835 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
836 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
837 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
838 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
839 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
840 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
841 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
842 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
843 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
844
95ea3627
ID		 845 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
846
847 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
849 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
850 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
851 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
852 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
853 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
854 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
855 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
856 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
857
858 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
859 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
860 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
861 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
862 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
863 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
864
865 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
866 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
867 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
868 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
869 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
870 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
871
872 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
873 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
874 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
875 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
876 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
877 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
878
879 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
881 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
882 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
883 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
884 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
885 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
886 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
887 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
888 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
889
890 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
891 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
892 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
893 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
894 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
895 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
896 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
897 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
898 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
899
900 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
901
902 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
903 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
904
905 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
906 return -EBUSY;
907
908 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
909 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
910
911 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
912 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
913 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
914
915 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
916 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
917 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
918 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
919 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
920 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
921 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
922 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
923
924 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
925
926 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
927
928 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
929 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
930 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
931 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
932 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
933
934 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
935 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
936 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
937 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
938
939 /*
940 * We must clear the FCS and FIFO error count.
941 * These registers are cleared on read,
942 * so we may pass a useless variable to store the value.
943 */
944 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
945 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
946
947 return 0;
948}
949
2b08da3f 950static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 951{
952 unsigned int i;
95ea3627
ID		 953 u8 value;
954
955 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
956 rt2500pci_bbp_read(rt2x00dev, 0, &value);
957 if ((value != 0xff) && (value != 0x00))
2b08da3f 958 return 0;
95ea3627
ID		 959 udelay(REGISTER_BUSY_DELAY);
960 }
961
962 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
963 return -EACCES;
2b08da3f
ID		 964}
965
966static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
967{
968 unsigned int i;
969 u16 eeprom;
970 u8 reg_id;
971 u8 value;
972
973 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974 return -EACCES;
95ea3627 975
95ea3627
ID		 976 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
977 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
978 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
979 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
980 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
981 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
982 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
983 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
984 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
986 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
987 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
988 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
989 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
990 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
991 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
992 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
993 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
994 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
995 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
996 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
997 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
998 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
999 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1000 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1001 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1003 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1004 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1005 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1006
95ea3627
ID		 1007 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1008 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1009
1010 if (eeprom != 0xffff && eeprom != 0x0000) {
1011 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1012 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1013 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1014 }
1015 }
95ea3627
ID		 1016
1017 return 0;
1018}
1019
1020/*
1021 * Device state switch handlers.
1022 */
1023static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1024 enum dev_state state)
1025{
1026 u32 reg;
1027
1028 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1029 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 1030 (state == STATE_RADIO_RX_OFF) ||
1031 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1032 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1033}
1034
1035static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1036 enum dev_state state)
1037{
1038 int mask = (state == STATE_RADIO_IRQ_OFF);
1039 u32 reg;
1040
1041 /*
1042 * When interrupts are being enabled, the interrupt registers
1043 * should clear the register to assure a clean state.
1044 */
1045 if (state == STATE_RADIO_IRQ_ON) {
1046 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1047 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1048 }
1049
1050 /*
1051 * Only toggle the interrupts bits we are going to use.
1052 * Non-checked interrupt bits are disabled by default.
1053 */
1054 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1055 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1056 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1057 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1058 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1059 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1060 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1061}
1062
1063static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1064{
1065 /*
1066 * Initialize all registers.
1067 */
2b08da3f
ID		 1068 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1069 rt2500pci_init_registers(rt2x00dev) ||
1070 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1071 return -EIO;
95ea3627 1072
95ea3627
ID		 1073 return 0;
1074}
1075
1076static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1077{
1078 u32 reg;
1079
95ea3627
ID		 1080 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1081
1082 /*
1083 * Disable synchronisation.
1084 */
1085 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1086
1087 /*
1088 * Cancel RX and TX.
1089 */
1090 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1091 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1092 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
95ea3627
ID		 1093}
1094
1095static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1096 enum dev_state state)
1097{
1098 u32 reg;
1099 unsigned int i;
1100 char put_to_sleep;
1101 char bbp_state;
1102 char rf_state;
1103
1104 put_to_sleep = (state != STATE_AWAKE);
1105
1106 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1107 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1108 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1109 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1110 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1111 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1112
1113 /*
1114 * Device is not guaranteed to be in the requested state yet.
1115 * We must wait until the register indicates that the
1116 * device has entered the correct state.
1117 */
1118 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1119 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1120 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1121 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1122 if (bbp_state == state && rf_state == state)
1123 return 0;
1124 msleep(10);
1125 }
1126
95ea3627
ID		 1127 return -EBUSY;
1128}
1129
1130static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1131 enum dev_state state)
1132{
1133 int retval = 0;
1134
1135 switch (state) {
1136 case STATE_RADIO_ON:
1137 retval = rt2500pci_enable_radio(rt2x00dev);
1138 break;
1139 case STATE_RADIO_OFF:
1140 rt2500pci_disable_radio(rt2x00dev);
1141 break;
1142 case STATE_RADIO_RX_ON:
61667d8d 1143 case STATE_RADIO_RX_ON_LINK:
95ea3627 1144 case STATE_RADIO_RX_OFF:
61667d8d 1145 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1146 rt2500pci_toggle_rx(rt2x00dev, state);
1147 break;
1148 case STATE_RADIO_IRQ_ON:
1149 case STATE_RADIO_IRQ_OFF:
1150 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1151 break;
1152 case STATE_DEEP_SLEEP:
1153 case STATE_SLEEP:
1154 case STATE_STANDBY:
1155 case STATE_AWAKE:
1156 retval = rt2500pci_set_state(rt2x00dev, state);
1157 break;
1158 default:
1159 retval = -ENOTSUPP;
1160 break;
1161 }
1162
2b08da3f
ID		 1163 if (unlikely(retval))
1164 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1165 state, retval);
1166
95ea3627
ID		 1167 return retval;
1168}
1169
1170/*
1171 * TX descriptor initialization
1172 */
1173static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1174 struct sk_buff *skb,
61486e0f 1175 struct txentry_desc *txdesc)
95ea3627 1176{
181d6902 1177 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1178 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1179 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1180 u32 word;
1181
1182 /*
1183 * Start writing the descriptor words.
1184 */
4de36fe5 1185 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1186 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1187 rt2x00_desc_write(entry_priv->desc, 1, word);
1188
95ea3627
ID		 1189 rt2x00_desc_read(txd, 2, &word);
1190 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
181d6902
ID		 1191 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1192 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1193 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
95ea3627
ID		 1194 rt2x00_desc_write(txd, 2, word);
1195
1196 rt2x00_desc_read(txd, 3, &word);
181d6902
ID		 1197 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1198 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1199 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1200 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1201 rt2x00_desc_write(txd, 3, word);
1202
1203 rt2x00_desc_read(txd, 10, &word);
1204 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1205 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1206 rt2x00_desc_write(txd, 10, word);
1207
1208 rt2x00_desc_read(txd, 0, &word);
1209 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1210 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1211 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1212 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1213 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1214 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1215 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1216 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1217 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902 1218 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
95ea3627 1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
181d6902 1220 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1221 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1222 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
bf4634af 1223 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627
ID		 1224 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1225 rt2x00_desc_write(txd, 0, word);
1226}
1227
1228/*
1229 * TX data initialization
1230 */
bd88a781
ID		 1231static void rt2500pci_write_beacon(struct queue_entry *entry)
1232{
1233 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1234 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1235 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1236 u32 word;
1237 u32 reg;
1238
1239 /*
1240 * Disable beaconing while we are reloading the beacon data,
1241 * otherwise we might be sending out invalid data.
1242 */
1243 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1244 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1245 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1246 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1247 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1248
1249 /*
1250 * Replace rt2x00lib allocated descriptor with the
1251 * pointer to the _real_ hardware descriptor.
1252 * After that, map the beacon to DMA and update the
1253 * descriptor.
1254 */
1255 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1256 skbdesc->desc = entry_priv->desc;
1257
1258 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1259
1260 rt2x00_desc_read(entry_priv->desc, 1, &word);
1261 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1262 rt2x00_desc_write(entry_priv->desc, 1, word);
1263}
1264
95ea3627 1265static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1266 const enum data_queue_qid queue)
95ea3627
ID		 1267{
1268 u32 reg;
1269
e58c6aca 1270 if (queue == QID_BEACON) {
95ea3627
ID		 1271 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1272 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1273 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1274 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1275 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1276 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1277 }
1278 return;
1279 }
1280
1281 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1282 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1283 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1284 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1285 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1286}
1287
1288/*
1289 * RX control handlers
1290 */
181d6902
ID		 1291static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1292 struct rxdone_entry_desc *rxdesc)
95ea3627 1293{
b8be63ff 1294 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1295 u32 word0;
1296 u32 word2;
1297
b8be63ff
ID		 1298 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1299 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1300
4150c572 1301 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1302 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1303 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1304 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1305
89993890
ID		 1306 /*
1307 * Obtain the status about this packet.
1308 * When frame was received with an OFDM bitrate,
1309 * the signal is the PLCP value. If it was received with
1310 * a CCK bitrate the signal is the rate in 100kbit/s.
1311 */
181d6902
ID		 1312 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1313 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1314 entry->queue->rt2x00dev->rssi_offset;
181d6902 1315 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1316
19d30e02
ID		 1317 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1318 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1319 else
1320 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1321 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1322 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1323}
1324
1325/*
1326 * Interrupt functions.
1327 */
181d6902 1328static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1329 const enum data_queue_qid queue_idx)
95ea3627 1330{
181d6902 1331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1332 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1333 struct queue_entry *entry;
1334 struct txdone_entry_desc txdesc;
95ea3627 1335 u32 word;
95ea3627 1336
181d6902
ID		 1337 while (!rt2x00queue_empty(queue)) {
1338 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1339 entry_priv = entry->priv_data;
1340 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1341
1342 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1343 !rt2x00_get_field32(word, TXD_W0_VALID))
1344 break;
1345
1346 /*
1347 * Obtain the status about this packet.
1348 */
fb55f4d1
ID		 1349 txdesc.flags = 0;
1350 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1351 case 0: /* Success */
1352 case 1: /* Success with retry */
1353 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1354 break;
1355 case 2: /* Failure, excessive retries */
1356 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1357 /* Don't break, this is a failed frame! */
1358 default: /* Failure */
1359 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1360 }
181d6902 1361 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1362
d74f5ba4 1363 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1364 }
95ea3627
ID		 1365}
1366
1367static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1368{
1369 struct rt2x00_dev *rt2x00dev = dev_instance;
1370 u32 reg;
1371
1372 /*
1373 * Get the interrupt sources & saved to local variable.
1374 * Write register value back to clear pending interrupts.
1375 */
1376 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1377 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1378
1379 if (!reg)
1380 return IRQ_NONE;
1381
0262ab0d 1382 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 1383 return IRQ_HANDLED;
1384
1385 /*
1386 * Handle interrupts, walk through all bits
1387 * and run the tasks, the bits are checked in order of
1388 * priority.
1389 */
1390
1391 /*
1392 * 1 - Beacon timer expired interrupt.
1393 */
1394 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1395 rt2x00lib_beacondone(rt2x00dev);
1396
1397 /*
1398 * 2 - Rx ring done interrupt.
1399 */
1400 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1401 rt2x00pci_rxdone(rt2x00dev);
1402
1403 /*
1404 * 3 - Atim ring transmit done interrupt.
1405 */
1406 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1407 rt2500pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1408
1409 /*
1410 * 4 - Priority ring transmit done interrupt.
1411 */
1412 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1413 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1414
1415 /*
1416 * 5 - Tx ring transmit done interrupt.
1417 */
1418 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1419 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1420
1421 return IRQ_HANDLED;
1422}
1423
1424/*
1425 * Device probe functions.
1426 */
1427static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1428{
1429 struct eeprom_93cx6 eeprom;
1430 u32 reg;
1431 u16 word;
1432 u8 *mac;
1433
1434 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1435
1436 eeprom.data = rt2x00dev;
1437 eeprom.register_read = rt2500pci_eepromregister_read;
1438 eeprom.register_write = rt2500pci_eepromregister_write;
1439 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1440 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1441 eeprom.reg_data_in = 0;
1442 eeprom.reg_data_out = 0;
1443 eeprom.reg_data_clock = 0;
1444 eeprom.reg_chip_select = 0;
1445
1446 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1447 EEPROM_SIZE / sizeof(u16));
1448
1449 /*
1450 * Start validation of the data that has been read.
1451 */
1452 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1453 if (!is_valid_ether_addr(mac)) {
1454 random_ether_addr(mac);
e174961c 1455 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1456 }
1457
1458 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1459 if (word == 0xffff) {
1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1461 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1462 ANTENNA_SW_DIVERSITY);
1463 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1464 ANTENNA_SW_DIVERSITY);
1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1466 LED_MODE_DEFAULT);
95ea3627
ID		 1467 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1468 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1469 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1470 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1471 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1472 }
1473
1474 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1475 if (word == 0xffff) {
1476 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1477 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1478 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1479 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1480 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1481 }
1482
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1484 if (word == 0xffff) {
1485 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1486 DEFAULT_RSSI_OFFSET);
1487 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1488 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1489 }
1490
1491 return 0;
1492}
1493
1494static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1495{
1496 u32 reg;
1497 u16 value;
1498 u16 eeprom;
1499
1500 /*
1501 * Read EEPROM word for configuration.
1502 */
1503 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1504
1505 /*
1506 * Identify RF chipset.
1507 */
1508 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1509 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1510 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1511
1512 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1513 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1514 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1515 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1516 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1517 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1518 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1519 return -ENODEV;
1520 }
1521
1522 /*
1523 * Identify default antenna configuration.
1524 */
addc81bd 1525 rt2x00dev->default_ant.tx =
95ea3627 1526 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1527 rt2x00dev->default_ant.rx =
95ea3627
ID		 1528 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1529
1530 /*
1531 * Store led mode, for correct led behaviour.
1532 */
771fd565 1533#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1534 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1535
475433be
ID		 1536 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1537 if (value == LED_MODE_TXRX_ACTIVITY)
1538 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1539 LED_TYPE_ACTIVITY);
771fd565 1540#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1541
1542 /*
1543 * Detect if this device has an hardware controlled radio.
1544 */
58169529 1545#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627 1546 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1547 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
58169529 1548#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627
ID		 1549
1550 /*
1551 * Check if the BBP tuning should be enabled.
1552 */
1553 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1554
1555 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1556 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1557
1558 /*
1559 * Read the RSSI <-> dBm offset information.
1560 */
1561 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1562 rt2x00dev->rssi_offset =
1563 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1564
1565 return 0;
1566}
1567
1568/*
1569 * RF value list for RF2522
1570 * Supports: 2.4 GHz
1571 */
1572static const struct rf_channel rf_vals_bg_2522[] = {
1573 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1574 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1575 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1576 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1577 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1578 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1579 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1580 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1581 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1582 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1583 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1584 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1585 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1586 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1587};
1588
1589/*
1590 * RF value list for RF2523
1591 * Supports: 2.4 GHz
1592 */
1593static const struct rf_channel rf_vals_bg_2523[] = {
1594 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1595 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1596 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1597 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1598 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1599 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1600 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1601 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1602 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1603 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1604 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1605 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1606 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1607 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1608};
1609
1610/*
1611 * RF value list for RF2524
1612 * Supports: 2.4 GHz
1613 */
1614static const struct rf_channel rf_vals_bg_2524[] = {
1615 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1616 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1617 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1618 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1619 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1620 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1621 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1622 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1623 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1624 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1625 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1626 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1627 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1628 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1629};
1630
1631/*
1632 * RF value list for RF2525
1633 * Supports: 2.4 GHz
1634 */
1635static const struct rf_channel rf_vals_bg_2525[] = {
1636 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1637 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1638 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1639 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1640 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1641 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1642 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1643 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1644 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1645 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1646 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1647 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1648 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1649 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1650};
1651
1652/*
1653 * RF value list for RF2525e
1654 * Supports: 2.4 GHz
1655 */
1656static const struct rf_channel rf_vals_bg_2525e[] = {
1657 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1658 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1659 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1660 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1661 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1662 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1663 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1664 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1665 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1666 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1667 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1668 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1669 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1670 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1671};
1672
1673/*
1674 * RF value list for RF5222
1675 * Supports: 2.4 GHz & 5.2 GHz
1676 */
1677static const struct rf_channel rf_vals_5222[] = {
1678 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1679 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1680 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1681 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1682 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1683 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1684 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1685 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1686 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1687 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1688 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1689 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1690 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1691 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1692
1693 /* 802.11 UNI / HyperLan 2 */
1694 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1695 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1696 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1697 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1698 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1699 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1700 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1701 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1702
1703 /* 802.11 HyperLan 2 */
1704 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1705 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1706 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1707 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1708 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1709 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1710 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1711 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1712 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1713 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1714
1715 /* 802.11 UNII */
1716 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1717 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1718 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1719 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1720 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1721};
1722
8c5e7a5f 1723static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1724{
1725 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1726 struct channel_info *info;
1727 char *tx_power;
95ea3627
ID		 1728 unsigned int i;
1729
1730 /*
1731 * Initialize all hw fields.
1732 */
566bfe5a
BR		 1733 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1734 IEEE80211_HW_SIGNAL_DBM;
1735
95ea3627 1736 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 1737
14a3bf89 1738 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1739 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1740 rt2x00_eeprom_addr(rt2x00dev,
1741 EEPROM_MAC_ADDR_0));
1742
95ea3627
ID		 1743 /*
1744 * Initialize hw_mode information.
1745 */
31562e80
ID		 1746 spec->supported_bands = SUPPORT_BAND_2GHZ;
1747 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1748
1749 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1750 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1751 spec->channels = rf_vals_bg_2522;
1752 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1753 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1754 spec->channels = rf_vals_bg_2523;
1755 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1756 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1757 spec->channels = rf_vals_bg_2524;
1758 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1759 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1760 spec->channels = rf_vals_bg_2525;
1761 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1762 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1763 spec->channels = rf_vals_bg_2525e;
1764 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
31562e80 1765 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1766 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1767 spec->channels = rf_vals_5222;
95ea3627 1768 }
8c5e7a5f
ID		 1769
1770 /*
1771 * Create channel information array
1772 */
1773 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1774 if (!info)
1775 return -ENOMEM;
1776
1777 spec->channels_info = info;
1778
1779 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1780 for (i = 0; i < 14; i++)
1781 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1782
1783 if (spec->num_channels > 14) {
1784 for (i = 14; i < spec->num_channels; i++)
1785 info[i].tx_power1 = DEFAULT_TXPOWER;
1786 }
1787
1788 return 0;
95ea3627
ID		 1789}
1790
1791static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1792{
1793 int retval;
1794
1795 /*
1796 * Allocate eeprom data.
1797 */
1798 retval = rt2500pci_validate_eeprom(rt2x00dev);
1799 if (retval)
1800 return retval;
1801
1802 retval = rt2500pci_init_eeprom(rt2x00dev);
1803 if (retval)
1804 return retval;
1805
1806 /*
1807 * Initialize hw specifications.
1808 */
8c5e7a5f
ID		 1809 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1810 if (retval)
1811 return retval;
95ea3627
ID		 1812
1813 /*
c4da0048 1814 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1815 */
181d6902 1816 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1817 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1818
1819 /*
1820 * Set the rssi offset.
1821 */
1822 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1823
1824 return 0;
1825}
1826
1827/*
1828 * IEEE80211 stack callback functions.
1829 */
1830static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1831 u32 short_retry, u32 long_retry)
1832{
1833 struct rt2x00_dev *rt2x00dev = hw->priv;
1834 u32 reg;
1835
1836 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1837 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1838 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1839 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1840
1841 return 0;
1842}
1843
1844static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1845{
1846 struct rt2x00_dev *rt2x00dev = hw->priv;
1847 u64 tsf;
1848 u32 reg;
1849
1850 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1851 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1852 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1853 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1854
1855 return tsf;
1856}
1857
95ea3627
ID		 1858static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1859{
1860 struct rt2x00_dev *rt2x00dev = hw->priv;
1861 u32 reg;
1862
1863 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1864 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1865}
1866
1867static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1868 .tx = rt2x00mac_tx,
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JB		 1869 .start = rt2x00mac_start,
1870 .stop = rt2x00mac_stop,
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ID		 1871 .add_interface = rt2x00mac_add_interface,
1872 .remove_interface = rt2x00mac_remove_interface,
1873 .config = rt2x00mac_config,
1874 .config_interface = rt2x00mac_config_interface,
3a643d24 1875 .configure_filter = rt2x00mac_configure_filter,
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ID		 1876 .get_stats = rt2x00mac_get_stats,
1877 .set_retry_limit = rt2500pci_set_retry_limit,
471b3efd 1878 .bss_info_changed = rt2x00mac_bss_info_changed,
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ID		 1879 .conf_tx = rt2x00mac_conf_tx,
1880 .get_tx_stats = rt2x00mac_get_tx_stats,
1881 .get_tsf = rt2500pci_get_tsf,
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ID		 1882 .tx_last_beacon = rt2500pci_tx_last_beacon,
1883};
1884
1885static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1886 .irq_handler = rt2500pci_interrupt,
1887 .probe_hw = rt2500pci_probe_hw,
1888 .initialize = rt2x00pci_initialize,
1889 .uninitialize = rt2x00pci_uninitialize,
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ID		 1890 .init_rxentry = rt2500pci_init_rxentry,
1891 .init_txentry = rt2500pci_init_txentry,
95ea3627 1892 .set_device_state = rt2500pci_set_device_state,
95ea3627 1893 .rfkill_poll = rt2500pci_rfkill_poll,
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ID		 1894 .link_stats = rt2500pci_link_stats,
1895 .reset_tuner = rt2500pci_reset_tuner,
1896 .link_tuner = rt2500pci_link_tuner,
1897 .write_tx_desc = rt2500pci_write_tx_desc,
1898 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 1899 .write_beacon = rt2500pci_write_beacon,
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ID		 1900 .kick_tx_queue = rt2500pci_kick_tx_queue,
1901 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 1902 .config_filter = rt2500pci_config_filter,
6bb40dd1 1903 .config_intf = rt2500pci_config_intf,
72810379 1904 .config_erp = rt2500pci_config_erp,
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ID		 1905 .config = rt2500pci_config,
1906};
1907
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ID		 1908static const struct data_queue_desc rt2500pci_queue_rx = {
1909 .entry_num = RX_ENTRIES,
1910 .data_size = DATA_FRAME_SIZE,
1911 .desc_size = RXD_DESC_SIZE,
b8be63ff 1912 .priv_size = sizeof(struct queue_entry_priv_pci),
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ID		 1913};
1914
1915static const struct data_queue_desc rt2500pci_queue_tx = {
1916 .entry_num = TX_ENTRIES,
1917 .data_size = DATA_FRAME_SIZE,
1918 .desc_size = TXD_DESC_SIZE,
b8be63ff 1919 .priv_size = sizeof(struct queue_entry_priv_pci),
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ID		 1920};
1921
1922static const struct data_queue_desc rt2500pci_queue_bcn = {
1923 .entry_num = BEACON_ENTRIES,
1924 .data_size = MGMT_FRAME_SIZE,
1925 .desc_size = TXD_DESC_SIZE,
b8be63ff 1926 .priv_size = sizeof(struct queue_entry_priv_pci),
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ID		 1927};
1928
1929static const struct data_queue_desc rt2500pci_queue_atim = {
1930 .entry_num = ATIM_ENTRIES,
1931 .data_size = DATA_FRAME_SIZE,
1932 .desc_size = TXD_DESC_SIZE,
b8be63ff 1933 .priv_size = sizeof(struct queue_entry_priv_pci),
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ID		 1934};
1935
95ea3627 1936static const struct rt2x00_ops rt2500pci_ops = {
2360157c 1937 .name = KBUILD_MODNAME,
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ID		 1938 .max_sta_intf = 1,
1939 .max_ap_intf = 1,
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ID		 1940 .eeprom_size = EEPROM_SIZE,
1941 .rf_size = RF_SIZE,
61448f88 1942 .tx_queues = NUM_TX_QUEUES,
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ID		 1943 .rx = &rt2500pci_queue_rx,
1944 .tx = &rt2500pci_queue_tx,
1945 .bcn = &rt2500pci_queue_bcn,
1946 .atim = &rt2500pci_queue_atim,
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ID		 1947 .lib = &rt2500pci_rt2x00_ops,
1948 .hw = &rt2500pci_mac80211_ops,
1949#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1950 .debugfs = &rt2500pci_rt2x00debug,
1951#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1952};
1953
1954/*
1955 * RT2500pci module information.
1956 */
1957static struct pci_device_id rt2500pci_device_table[] = {
1958 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1959 { 0, }
1960};
1961
1962MODULE_AUTHOR(DRV_PROJECT);
1963MODULE_VERSION(DRV_VERSION);
1964MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1965MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1966MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1967MODULE_LICENSE("GPL");
1968
1969static struct pci_driver rt2500pci_driver = {
2360157c 1970 .name = KBUILD_MODNAME,
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ID		 1971 .id_table = rt2500pci_device_table,
1972 .probe = rt2x00pci_probe,
1973 .remove = __devexit_p(rt2x00pci_remove),
1974 .suspend = rt2x00pci_suspend,
1975 .resume = rt2x00pci_resume,
1976};
1977
1978static int __init rt2500pci_init(void)
1979{
1980 return pci_register_driver(&rt2500pci_driver);
1981}
1982
1983static void __exit rt2500pci_exit(void)
1984{
1985 pci_unregister_driver(&rt2500pci_driver);
1986}
1987
1988module_init(rt2500pci_init);
1989module_exit(rt2500pci_exit);
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