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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2500pci | |
23 | Abstract: Data structures and registers for the rt2500pci module. | |
24 | Supported chipsets: RT2560. | |
25 | */ | |
26 | ||
27 | #ifndef RT2500PCI_H | |
28 | #define RT2500PCI_H | |
29 | ||
30 | /* | |
31 | * RF chip defines. | |
32 | */ | |
33 | #define RF2522 0x0000 | |
34 | #define RF2523 0x0001 | |
35 | #define RF2524 0x0002 | |
36 | #define RF2525 0x0003 | |
37 | #define RF2525E 0x0004 | |
38 | #define RF5222 0x0010 | |
39 | ||
40 | /* | |
41 | * RT2560 version | |
42 | */ | |
43 | #define RT2560_VERSION_B 2 | |
44 | #define RT2560_VERSION_C 3 | |
45 | #define RT2560_VERSION_D 4 | |
46 | ||
47 | /* | |
48 | * Signal information. | |
49 | * Defaul offset is required for RSSI <-> dBm conversion. | |
50 | */ | |
95ea3627 ID |
51 | #define DEFAULT_RSSI_OFFSET 121 |
52 | ||
53 | /* | |
54 | * Register layout information. | |
55 | */ | |
56 | #define CSR_REG_BASE 0x0000 | |
57 | #define CSR_REG_SIZE 0x0174 | |
58 | #define EEPROM_BASE 0x0000 | |
59 | #define EEPROM_SIZE 0x0200 | |
743b97ca | 60 | #define BBP_BASE 0x0000 |
95ea3627 | 61 | #define BBP_SIZE 0x0040 |
743b97ca | 62 | #define RF_BASE 0x0000 |
95ea3627 ID |
63 | #define RF_SIZE 0x0014 |
64 | ||
61448f88 GW |
65 | /* |
66 | * Number of TX queues. | |
67 | */ | |
68 | #define NUM_TX_QUEUES 2 | |
69 | ||
95ea3627 ID |
70 | /* |
71 | * Control/Status Registers(CSR). | |
72 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * CSR0: ASIC revision number. | |
77 | */ | |
78 | #define CSR0 0x0000 | |
79 | ||
80 | /* | |
81 | * CSR1: System control register. | |
82 | * SOFT_RESET: Software reset, 1: reset, 0: normal. | |
83 | * BBP_RESET: Hardware reset, 1: reset, 0, release. | |
84 | * HOST_READY: Host ready after initialization. | |
85 | */ | |
86 | #define CSR1 0x0004 | |
87 | #define CSR1_SOFT_RESET FIELD32(0x00000001) | |
88 | #define CSR1_BBP_RESET FIELD32(0x00000002) | |
89 | #define CSR1_HOST_READY FIELD32(0x00000004) | |
90 | ||
91 | /* | |
92 | * CSR2: System admin status register (invalid). | |
93 | */ | |
94 | #define CSR2 0x0008 | |
95 | ||
96 | /* | |
97 | * CSR3: STA MAC address register 0. | |
98 | */ | |
99 | #define CSR3 0x000c | |
100 | #define CSR3_BYTE0 FIELD32(0x000000ff) | |
101 | #define CSR3_BYTE1 FIELD32(0x0000ff00) | |
102 | #define CSR3_BYTE2 FIELD32(0x00ff0000) | |
103 | #define CSR3_BYTE3 FIELD32(0xff000000) | |
104 | ||
105 | /* | |
106 | * CSR4: STA MAC address register 1. | |
107 | */ | |
108 | #define CSR4 0x0010 | |
109 | #define CSR4_BYTE4 FIELD32(0x000000ff) | |
110 | #define CSR4_BYTE5 FIELD32(0x0000ff00) | |
111 | ||
112 | /* | |
113 | * CSR5: BSSID register 0. | |
114 | */ | |
115 | #define CSR5 0x0014 | |
116 | #define CSR5_BYTE0 FIELD32(0x000000ff) | |
117 | #define CSR5_BYTE1 FIELD32(0x0000ff00) | |
118 | #define CSR5_BYTE2 FIELD32(0x00ff0000) | |
119 | #define CSR5_BYTE3 FIELD32(0xff000000) | |
120 | ||
121 | /* | |
122 | * CSR6: BSSID register 1. | |
123 | */ | |
124 | #define CSR6 0x0018 | |
125 | #define CSR6_BYTE4 FIELD32(0x000000ff) | |
126 | #define CSR6_BYTE5 FIELD32(0x0000ff00) | |
127 | ||
128 | /* | |
129 | * CSR7: Interrupt source register. | |
130 | * Write 1 to clear. | |
131 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
132 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
133 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
134 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
135 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
136 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
137 | * RXDONE: Receive done interrupt. | |
138 | * DECRYPTION_DONE: Decryption done interrupt. | |
139 | * ENCRYPTION_DONE: Encryption done interrupt. | |
140 | * UART1_TX_TRESHOLD: UART1 TX reaches threshold. | |
141 | * UART1_RX_TRESHOLD: UART1 RX reaches threshold. | |
142 | * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. | |
143 | * UART1_TX_BUFF_ERROR: UART1 TX buffer error. | |
144 | * UART1_RX_BUFF_ERROR: UART1 RX buffer error. | |
145 | * UART2_TX_TRESHOLD: UART2 TX reaches threshold. | |
146 | * UART2_RX_TRESHOLD: UART2 RX reaches threshold. | |
147 | * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. | |
148 | * UART2_TX_BUFF_ERROR: UART2 TX buffer error. | |
149 | * UART2_RX_BUFF_ERROR: UART2 RX buffer error. | |
150 | * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). | |
151 | ||
152 | */ | |
153 | #define CSR7 0x001c | |
154 | #define CSR7_TBCN_EXPIRE FIELD32(0x00000001) | |
155 | #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) | |
156 | #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) | |
157 | #define CSR7_TXDONE_TXRING FIELD32(0x00000008) | |
158 | #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) | |
159 | #define CSR7_TXDONE_PRIORING FIELD32(0x00000020) | |
160 | #define CSR7_RXDONE FIELD32(0x00000040) | |
161 | #define CSR7_DECRYPTION_DONE FIELD32(0x00000080) | |
162 | #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100) | |
163 | #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200) | |
164 | #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400) | |
165 | #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800) | |
166 | #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000) | |
167 | #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000) | |
168 | #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000) | |
169 | #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000) | |
170 | #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000) | |
171 | #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000) | |
172 | #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000) | |
173 | #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000) | |
174 | ||
175 | /* | |
176 | * CSR8: Interrupt mask register. | |
177 | * Write 1 to mask interrupt. | |
178 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
179 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
180 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
181 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
182 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
183 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
184 | * RXDONE: Receive done interrupt. | |
185 | * DECRYPTION_DONE: Decryption done interrupt. | |
186 | * ENCRYPTION_DONE: Encryption done interrupt. | |
187 | * UART1_TX_TRESHOLD: UART1 TX reaches threshold. | |
188 | * UART1_RX_TRESHOLD: UART1 RX reaches threshold. | |
189 | * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. | |
190 | * UART1_TX_BUFF_ERROR: UART1 TX buffer error. | |
191 | * UART1_RX_BUFF_ERROR: UART1 RX buffer error. | |
192 | * UART2_TX_TRESHOLD: UART2 TX reaches threshold. | |
193 | * UART2_RX_TRESHOLD: UART2 RX reaches threshold. | |
194 | * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. | |
195 | * UART2_TX_BUFF_ERROR: UART2 TX buffer error. | |
196 | * UART2_RX_BUFF_ERROR: UART2 RX buffer error. | |
197 | * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). | |
198 | */ | |
199 | #define CSR8 0x0020 | |
200 | #define CSR8_TBCN_EXPIRE FIELD32(0x00000001) | |
201 | #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) | |
202 | #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) | |
203 | #define CSR8_TXDONE_TXRING FIELD32(0x00000008) | |
204 | #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) | |
205 | #define CSR8_TXDONE_PRIORING FIELD32(0x00000020) | |
206 | #define CSR8_RXDONE FIELD32(0x00000040) | |
207 | #define CSR8_DECRYPTION_DONE FIELD32(0x00000080) | |
208 | #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100) | |
209 | #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200) | |
210 | #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400) | |
211 | #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800) | |
212 | #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000) | |
213 | #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000) | |
214 | #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000) | |
215 | #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000) | |
216 | #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000) | |
217 | #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000) | |
218 | #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000) | |
219 | #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000) | |
220 | ||
221 | /* | |
222 | * CSR9: Maximum frame length register. | |
223 | * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. | |
224 | */ | |
225 | #define CSR9 0x0024 | |
226 | #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) | |
227 | ||
228 | /* | |
229 | * SECCSR0: WEP control register. | |
230 | * KICK_DECRYPT: Kick decryption engine, self-clear. | |
231 | * ONE_SHOT: 0: ring mode, 1: One shot only mode. | |
232 | * DESC_ADDRESS: Descriptor physical address of frame. | |
233 | */ | |
234 | #define SECCSR0 0x0028 | |
235 | #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001) | |
236 | #define SECCSR0_ONE_SHOT FIELD32(0x00000002) | |
237 | #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc) | |
238 | ||
239 | /* | |
240 | * CSR11: Back-off control register. | |
241 | * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). | |
242 | * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). | |
243 | * SLOT_TIME: Slot time, default is 20us for 802.11b | |
244 | * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD. | |
245 | * LONG_RETRY: Long retry count. | |
246 | * SHORT_RETRY: Short retry count. | |
247 | */ | |
248 | #define CSR11 0x002c | |
249 | #define CSR11_CWMIN FIELD32(0x0000000f) | |
250 | #define CSR11_CWMAX FIELD32(0x000000f0) | |
251 | #define CSR11_SLOT_TIME FIELD32(0x00001f00) | |
252 | #define CSR11_CW_SELECT FIELD32(0x00002000) | |
253 | #define CSR11_LONG_RETRY FIELD32(0x00ff0000) | |
254 | #define CSR11_SHORT_RETRY FIELD32(0xff000000) | |
255 | ||
256 | /* | |
257 | * CSR12: Synchronization configuration register 0. | |
258 | * All units in 1/16 TU. | |
259 | * BEACON_INTERVAL: Beacon interval, default is 100 TU. | |
260 | * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU. | |
261 | */ | |
262 | #define CSR12 0x0030 | |
263 | #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) | |
264 | #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) | |
265 | ||
266 | /* | |
267 | * CSR13: Synchronization configuration register 1. | |
268 | * All units in 1/16 TU. | |
269 | * ATIMW_DURATION: Atim window duration. | |
270 | * CFP_PERIOD: Cfp period, default is 0 TU. | |
271 | */ | |
272 | #define CSR13 0x0034 | |
273 | #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) | |
274 | #define CSR13_CFP_PERIOD FIELD32(0x00ff0000) | |
275 | ||
276 | /* | |
277 | * CSR14: Synchronization control register. | |
278 | * TSF_COUNT: Enable tsf auto counting. | |
279 | * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. | |
280 | * TBCN: Enable tbcn with reload value. | |
281 | * TCFP: Enable tcfp & cfp / cp switching. | |
282 | * TATIMW: Enable tatimw & atim window switching. | |
283 | * BEACON_GEN: Enable beacon generator. | |
284 | * CFP_COUNT_PRELOAD: Cfp count preload value. | |
285 | * TBCM_PRELOAD: Tbcn preload value in units of 64us. | |
286 | */ | |
287 | #define CSR14 0x0038 | |
288 | #define CSR14_TSF_COUNT FIELD32(0x00000001) | |
289 | #define CSR14_TSF_SYNC FIELD32(0x00000006) | |
290 | #define CSR14_TBCN FIELD32(0x00000008) | |
291 | #define CSR14_TCFP FIELD32(0x00000010) | |
292 | #define CSR14_TATIMW FIELD32(0x00000020) | |
293 | #define CSR14_BEACON_GEN FIELD32(0x00000040) | |
294 | #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) | |
295 | #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) | |
296 | ||
297 | /* | |
298 | * CSR15: Synchronization status register. | |
299 | * CFP: ASIC is in contention-free period. | |
300 | * ATIMW: ASIC is in ATIM window. | |
301 | * BEACON_SENT: Beacon is send. | |
302 | */ | |
303 | #define CSR15 0x003c | |
304 | #define CSR15_CFP FIELD32(0x00000001) | |
305 | #define CSR15_ATIMW FIELD32(0x00000002) | |
306 | #define CSR15_BEACON_SENT FIELD32(0x00000004) | |
307 | ||
308 | /* | |
309 | * CSR16: TSF timer register 0. | |
310 | */ | |
311 | #define CSR16 0x0040 | |
312 | #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) | |
313 | ||
314 | /* | |
315 | * CSR17: TSF timer register 1. | |
316 | */ | |
317 | #define CSR17 0x0044 | |
318 | #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) | |
319 | ||
320 | /* | |
321 | * CSR18: IFS timer register 0. | |
322 | * SIFS: Sifs, default is 10 us. | |
323 | * PIFS: Pifs, default is 30 us. | |
324 | */ | |
325 | #define CSR18 0x0048 | |
326 | #define CSR18_SIFS FIELD32(0x000001ff) | |
327 | #define CSR18_PIFS FIELD32(0x001f0000) | |
328 | ||
329 | /* | |
330 | * CSR19: IFS timer register 1. | |
331 | * DIFS: Difs, default is 50 us. | |
332 | * EIFS: Eifs, default is 364 us. | |
333 | */ | |
334 | #define CSR19 0x004c | |
335 | #define CSR19_DIFS FIELD32(0x0000ffff) | |
336 | #define CSR19_EIFS FIELD32(0xffff0000) | |
337 | ||
338 | /* | |
339 | * CSR20: Wakeup timer register. | |
340 | * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. | |
341 | * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. | |
342 | * AUTOWAKE: Enable auto wakeup / sleep mechanism. | |
343 | */ | |
344 | #define CSR20 0x0050 | |
345 | #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) | |
346 | #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) | |
347 | #define CSR20_AUTOWAKE FIELD32(0x01000000) | |
348 | ||
349 | /* | |
350 | * CSR21: EEPROM control register. | |
351 | * RELOAD: Write 1 to reload eeprom content. | |
352 | * TYPE_93C46: 1: 93c46, 0:93c66. | |
353 | */ | |
354 | #define CSR21 0x0054 | |
355 | #define CSR21_RELOAD FIELD32(0x00000001) | |
356 | #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) | |
357 | #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) | |
358 | #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) | |
359 | #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) | |
360 | #define CSR21_TYPE_93C46 FIELD32(0x00000020) | |
361 | ||
362 | /* | |
363 | * CSR22: CFP control register. | |
364 | * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. | |
365 | * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. | |
366 | */ | |
367 | #define CSR22 0x0058 | |
368 | #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) | |
369 | #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) | |
370 | ||
371 | /* | |
372 | * Transmit related CSRs. | |
373 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
374 | */ | |
375 | ||
376 | /* | |
377 | * TXCSR0: TX Control Register. | |
378 | * KICK_TX: Kick tx ring. | |
379 | * KICK_ATIM: Kick atim ring. | |
380 | * KICK_PRIO: Kick priority ring. | |
381 | * ABORT: Abort all transmit related ring operation. | |
382 | */ | |
383 | #define TXCSR0 0x0060 | |
384 | #define TXCSR0_KICK_TX FIELD32(0x00000001) | |
385 | #define TXCSR0_KICK_ATIM FIELD32(0x00000002) | |
386 | #define TXCSR0_KICK_PRIO FIELD32(0x00000004) | |
387 | #define TXCSR0_ABORT FIELD32(0x00000008) | |
388 | ||
389 | /* | |
390 | * TXCSR1: TX Configuration Register. | |
391 | * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. | |
392 | * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. | |
393 | * TSF_OFFSET: Insert tsf offset. | |
394 | * AUTORESPONDER: Enable auto responder which include ack & cts. | |
395 | */ | |
396 | #define TXCSR1 0x0064 | |
397 | #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) | |
398 | #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) | |
399 | #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) | |
400 | #define TXCSR1_AUTORESPONDER FIELD32(0x01000000) | |
401 | ||
402 | /* | |
403 | * TXCSR2: Tx descriptor configuration register. | |
404 | * TXD_SIZE: Tx descriptor size, default is 48. | |
405 | * NUM_TXD: Number of tx entries in ring. | |
406 | * NUM_ATIM: Number of atim entries in ring. | |
407 | * NUM_PRIO: Number of priority entries in ring. | |
408 | */ | |
409 | #define TXCSR2 0x0068 | |
410 | #define TXCSR2_TXD_SIZE FIELD32(0x000000ff) | |
411 | #define TXCSR2_NUM_TXD FIELD32(0x0000ff00) | |
412 | #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) | |
413 | #define TXCSR2_NUM_PRIO FIELD32(0xff000000) | |
414 | ||
415 | /* | |
416 | * TXCSR3: TX Ring Base address register. | |
417 | */ | |
418 | #define TXCSR3 0x006c | |
419 | #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) | |
420 | ||
421 | /* | |
422 | * TXCSR4: TX Atim Ring Base address register. | |
423 | */ | |
424 | #define TXCSR4 0x0070 | |
425 | #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) | |
426 | ||
427 | /* | |
428 | * TXCSR5: TX Prio Ring Base address register. | |
429 | */ | |
430 | #define TXCSR5 0x0074 | |
431 | #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) | |
432 | ||
433 | /* | |
434 | * TXCSR6: Beacon Base address register. | |
435 | */ | |
436 | #define TXCSR6 0x0078 | |
437 | #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) | |
438 | ||
439 | /* | |
440 | * TXCSR7: Auto responder control register. | |
441 | * AR_POWERMANAGEMENT: Auto responder power management bit. | |
442 | */ | |
443 | #define TXCSR7 0x007c | |
444 | #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) | |
445 | ||
446 | /* | |
447 | * TXCSR8: CCK Tx BBP register. | |
448 | */ | |
449 | #define TXCSR8 0x0098 | |
450 | #define TXCSR8_BBP_ID0 FIELD32(0x0000007f) | |
451 | #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080) | |
452 | #define TXCSR8_BBP_ID1 FIELD32(0x00007f00) | |
453 | #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000) | |
454 | #define TXCSR8_BBP_ID2 FIELD32(0x007f0000) | |
455 | #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000) | |
456 | #define TXCSR8_BBP_ID3 FIELD32(0x7f000000) | |
457 | #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000) | |
458 | ||
459 | /* | |
460 | * TXCSR9: OFDM TX BBP registers | |
461 | * OFDM_SIGNAL: BBP rate field address for OFDM. | |
462 | * OFDM_SERVICE: BBP service field address for OFDM. | |
463 | * OFDM_LENGTH_LOW: BBP length low byte address for OFDM. | |
464 | * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM. | |
465 | */ | |
466 | #define TXCSR9 0x0094 | |
467 | #define TXCSR9_OFDM_RATE FIELD32(0x000000ff) | |
468 | #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00) | |
469 | #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000) | |
470 | #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000) | |
471 | ||
472 | /* | |
473 | * Receive related CSRs. | |
474 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
475 | */ | |
476 | ||
477 | /* | |
478 | * RXCSR0: RX Control Register. | |
479 | * DISABLE_RX: Disable rx engine. | |
480 | * DROP_CRC: Drop crc error. | |
481 | * DROP_PHYSICAL: Drop physical error. | |
482 | * DROP_CONTROL: Drop control frame. | |
483 | * DROP_NOT_TO_ME: Drop not to me unicast frame. | |
484 | * DROP_TODS: Drop frame tods bit is true. | |
485 | * DROP_VERSION_ERROR: Drop version error frame. | |
486 | * PASS_CRC: Pass all packets with crc attached. | |
487 | * PASS_CRC: Pass all packets with crc attached. | |
488 | * PASS_PLCP: Pass all packets with 4 bytes PLCP attached. | |
489 | * DROP_MCAST: Drop multicast frames. | |
490 | * DROP_BCAST: Drop broadcast frames. | |
491 | * ENABLE_QOS: Accept QOS data frame and parse QOS field. | |
492 | */ | |
493 | #define RXCSR0 0x0080 | |
494 | #define RXCSR0_DISABLE_RX FIELD32(0x00000001) | |
495 | #define RXCSR0_DROP_CRC FIELD32(0x00000002) | |
496 | #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) | |
497 | #define RXCSR0_DROP_CONTROL FIELD32(0x00000008) | |
498 | #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) | |
499 | #define RXCSR0_DROP_TODS FIELD32(0x00000020) | |
500 | #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) | |
501 | #define RXCSR0_PASS_CRC FIELD32(0x00000080) | |
502 | #define RXCSR0_PASS_PLCP FIELD32(0x00000100) | |
503 | #define RXCSR0_DROP_MCAST FIELD32(0x00000200) | |
504 | #define RXCSR0_DROP_BCAST FIELD32(0x00000400) | |
505 | #define RXCSR0_ENABLE_QOS FIELD32(0x00000800) | |
506 | ||
507 | /* | |
508 | * RXCSR1: RX descriptor configuration register. | |
509 | * RXD_SIZE: Rx descriptor size, default is 32b. | |
510 | * NUM_RXD: Number of rx entries in ring. | |
511 | */ | |
512 | #define RXCSR1 0x0084 | |
513 | #define RXCSR1_RXD_SIZE FIELD32(0x000000ff) | |
514 | #define RXCSR1_NUM_RXD FIELD32(0x0000ff00) | |
515 | ||
516 | /* | |
517 | * RXCSR2: RX Ring base address register. | |
518 | */ | |
519 | #define RXCSR2 0x0088 | |
520 | #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) | |
521 | ||
522 | /* | |
523 | * RXCSR3: BBP ID register for Rx operation. | |
524 | * BBP_ID#: BBP register # id. | |
525 | * BBP_ID#_VALID: BBP register # id is valid or not. | |
526 | */ | |
527 | #define RXCSR3 0x0090 | |
528 | #define RXCSR3_BBP_ID0 FIELD32(0x0000007f) | |
529 | #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) | |
530 | #define RXCSR3_BBP_ID1 FIELD32(0x00007f00) | |
531 | #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) | |
532 | #define RXCSR3_BBP_ID2 FIELD32(0x007f0000) | |
533 | #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) | |
534 | #define RXCSR3_BBP_ID3 FIELD32(0x7f000000) | |
535 | #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) | |
536 | ||
537 | /* | |
538 | * ARCSR1: Auto Responder PLCP config register 1. | |
539 | * AR_BBP_DATA#: Auto responder BBP register # data. | |
540 | * AR_BBP_ID#: Auto responder BBP register # Id. | |
541 | */ | |
542 | #define ARCSR1 0x009c | |
543 | #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) | |
544 | #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) | |
545 | #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) | |
546 | #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) | |
547 | ||
548 | /* | |
549 | * Miscellaneous Registers. | |
550 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
551 | ||
552 | */ | |
553 | ||
554 | /* | |
555 | * PCICSR: PCI control register. | |
556 | * BIG_ENDIAN: 1: big endian, 0: little endian. | |
557 | * RX_TRESHOLD: Rx threshold in dw to start pci access | |
558 | * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. | |
559 | * TX_TRESHOLD: Tx threshold in dw to start pci access | |
560 | * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. | |
561 | * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. | |
562 | * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. | |
563 | * READ_MULTIPLE: Enable memory read multiple. | |
564 | * WRITE_INVALID: Enable memory write & invalid. | |
565 | */ | |
566 | #define PCICSR 0x008c | |
567 | #define PCICSR_BIG_ENDIAN FIELD32(0x00000001) | |
568 | #define PCICSR_RX_TRESHOLD FIELD32(0x00000006) | |
569 | #define PCICSR_TX_TRESHOLD FIELD32(0x00000018) | |
570 | #define PCICSR_BURST_LENTH FIELD32(0x00000060) | |
571 | #define PCICSR_ENABLE_CLK FIELD32(0x00000080) | |
572 | #define PCICSR_READ_MULTIPLE FIELD32(0x00000100) | |
573 | #define PCICSR_WRITE_INVALID FIELD32(0x00000200) | |
574 | ||
575 | /* | |
576 | * CNT0: FCS error count. | |
577 | * FCS_ERROR: FCS error count, cleared when read. | |
578 | */ | |
579 | #define CNT0 0x00a0 | |
580 | #define CNT0_FCS_ERROR FIELD32(0x0000ffff) | |
581 | ||
582 | /* | |
583 | * Statistic Register. | |
584 | * CNT1: PLCP error count. | |
585 | * CNT2: Long error count. | |
586 | */ | |
587 | #define TIMECSR2 0x00a8 | |
588 | #define CNT1 0x00ac | |
589 | #define CNT2 0x00b0 | |
590 | #define TIMECSR3 0x00b4 | |
591 | ||
592 | /* | |
593 | * CNT3: CCA false alarm count. | |
594 | */ | |
595 | #define CNT3 0x00b8 | |
596 | #define CNT3_FALSE_CCA FIELD32(0x0000ffff) | |
597 | ||
598 | /* | |
599 | * Statistic Register. | |
600 | * CNT4: Rx FIFO overflow count. | |
601 | * CNT5: Tx FIFO underrun count. | |
602 | */ | |
603 | #define CNT4 0x00bc | |
604 | #define CNT5 0x00c0 | |
605 | ||
606 | /* | |
607 | * Baseband Control Register. | |
608 | */ | |
609 | ||
610 | /* | |
611 | * PWRCSR0: Power mode configuration register. | |
612 | */ | |
613 | #define PWRCSR0 0x00c4 | |
614 | ||
615 | /* | |
616 | * Power state transition time registers. | |
617 | */ | |
618 | #define PSCSR0 0x00c8 | |
619 | #define PSCSR1 0x00cc | |
620 | #define PSCSR2 0x00d0 | |
621 | #define PSCSR3 0x00d4 | |
622 | ||
623 | /* | |
624 | * PWRCSR1: Manual power control / status register. | |
625 | * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. | |
626 | * SET_STATE: Set state. Write 1 to trigger, self cleared. | |
627 | * BBP_DESIRE_STATE: BBP desired state. | |
628 | * RF_DESIRE_STATE: RF desired state. | |
629 | * BBP_CURR_STATE: BBP current state. | |
630 | * RF_CURR_STATE: RF current state. | |
631 | * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. | |
632 | */ | |
633 | #define PWRCSR1 0x00d8 | |
634 | #define PWRCSR1_SET_STATE FIELD32(0x00000001) | |
635 | #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) | |
636 | #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) | |
637 | #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) | |
638 | #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) | |
639 | #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) | |
640 | ||
641 | /* | |
642 | * TIMECSR: Timer control register. | |
643 | * US_COUNT: 1 us timer count in units of clock cycles. | |
644 | * US_64_COUNT: 64 us timer count in units of 1 us timer. | |
645 | * BEACON_EXPECT: Beacon expect window. | |
646 | */ | |
647 | #define TIMECSR 0x00dc | |
648 | #define TIMECSR_US_COUNT FIELD32(0x000000ff) | |
649 | #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) | |
650 | #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) | |
651 | ||
652 | /* | |
653 | * MACCSR0: MAC configuration register 0. | |
654 | */ | |
655 | #define MACCSR0 0x00e0 | |
656 | ||
657 | /* | |
658 | * MACCSR1: MAC configuration register 1. | |
659 | * KICK_RX: Kick one-shot rx in one-shot rx mode. | |
660 | * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. | |
661 | * BBPRX_RESET_MODE: Ralink bbp rx reset mode. | |
662 | * AUTO_TXBBP: Auto tx logic access bbp control register. | |
663 | * AUTO_RXBBP: Auto rx logic access bbp control register. | |
664 | * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. | |
665 | * INTERSIL_IF: Intersil if calibration pin. | |
666 | */ | |
667 | #define MACCSR1 0x00e4 | |
668 | #define MACCSR1_KICK_RX FIELD32(0x00000001) | |
669 | #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) | |
670 | #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) | |
671 | #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) | |
672 | #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) | |
673 | #define MACCSR1_LOOPBACK FIELD32(0x00000060) | |
674 | #define MACCSR1_INTERSIL_IF FIELD32(0x00000080) | |
675 | ||
676 | /* | |
677 | * RALINKCSR: Ralink Rx auto-reset BBCR. | |
678 | * AR_BBP_DATA#: Auto reset BBP register # data. | |
679 | * AR_BBP_ID#: Auto reset BBP register # id. | |
680 | */ | |
681 | #define RALINKCSR 0x00e8 | |
682 | #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) | |
683 | #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00) | |
684 | #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000) | |
685 | #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) | |
686 | #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000) | |
687 | #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000) | |
688 | ||
689 | /* | |
690 | * BCNCSR: Beacon interval control register. | |
691 | * CHANGE: Write one to change beacon interval. | |
692 | * DELTATIME: The delta time value. | |
693 | * NUM_BEACON: Number of beacon according to mode. | |
694 | * MODE: Please refer to asic specs. | |
695 | * PLUS: Plus or minus delta time value. | |
696 | */ | |
697 | #define BCNCSR 0x00ec | |
698 | #define BCNCSR_CHANGE FIELD32(0x00000001) | |
699 | #define BCNCSR_DELTATIME FIELD32(0x0000001e) | |
700 | #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) | |
701 | #define BCNCSR_MODE FIELD32(0x00006000) | |
702 | #define BCNCSR_PLUS FIELD32(0x00008000) | |
703 | ||
704 | /* | |
705 | * BBP / RF / IF Control Register. | |
706 | */ | |
707 | ||
708 | /* | |
709 | * BBPCSR: BBP serial control register. | |
710 | * VALUE: Register value to program into BBP. | |
711 | * REGNUM: Selected BBP register. | |
712 | * BUSY: 1: asic is busy execute BBP programming. | |
713 | * WRITE_CONTROL: 1: write BBP, 0: read BBP. | |
714 | */ | |
715 | #define BBPCSR 0x00f0 | |
716 | #define BBPCSR_VALUE FIELD32(0x000000ff) | |
717 | #define BBPCSR_REGNUM FIELD32(0x00007f00) | |
718 | #define BBPCSR_BUSY FIELD32(0x00008000) | |
719 | #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) | |
720 | ||
721 | /* | |
722 | * RFCSR: RF serial control register. | |
723 | * VALUE: Register value + id to program into rf/if. | |
724 | * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). | |
725 | * IF_SELECT: Chip to program: 0: rf, 1: if. | |
726 | * PLL_LD: Rf pll_ld status. | |
727 | * BUSY: 1: asic is busy execute rf programming. | |
728 | */ | |
729 | #define RFCSR 0x00f4 | |
730 | #define RFCSR_VALUE FIELD32(0x00ffffff) | |
731 | #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) | |
732 | #define RFCSR_IF_SELECT FIELD32(0x20000000) | |
733 | #define RFCSR_PLL_LD FIELD32(0x40000000) | |
734 | #define RFCSR_BUSY FIELD32(0x80000000) | |
735 | ||
736 | /* | |
737 | * LEDCSR: LED control register. | |
738 | * ON_PERIOD: On period, default 70ms. | |
739 | * OFF_PERIOD: Off period, default 30ms. | |
740 | * LINK: 0: linkoff, 1: linkup. | |
741 | * ACTIVITY: 0: idle, 1: active. | |
742 | * LINK_POLARITY: 0: active low, 1: active high. | |
743 | * ACTIVITY_POLARITY: 0: active low, 1: active high. | |
744 | * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF. | |
745 | */ | |
746 | #define LEDCSR 0x00f8 | |
747 | #define LEDCSR_ON_PERIOD FIELD32(0x000000ff) | |
748 | #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) | |
749 | #define LEDCSR_LINK FIELD32(0x00010000) | |
750 | #define LEDCSR_ACTIVITY FIELD32(0x00020000) | |
751 | #define LEDCSR_LINK_POLARITY FIELD32(0x00040000) | |
752 | #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000) | |
753 | #define LEDCSR_LED_DEFAULT FIELD32(0x00100000) | |
754 | ||
755 | /* | |
84263b0c | 756 | * SECCSR3: AES control register. |
95ea3627 ID |
757 | */ |
758 | #define SECCSR3 0x00fc | |
759 | ||
760 | /* | |
761 | * ASIC pointer information. | |
762 | * RXPTR: Current RX ring address. | |
763 | * TXPTR: Current Tx ring address. | |
764 | * PRIPTR: Current Priority ring address. | |
765 | * ATIMPTR: Current ATIM ring address. | |
766 | */ | |
767 | #define RXPTR 0x0100 | |
768 | #define TXPTR 0x0104 | |
769 | #define PRIPTR 0x0108 | |
770 | #define ATIMPTR 0x010c | |
771 | ||
772 | /* | |
773 | * TXACKCSR0: TX ACK timeout. | |
774 | */ | |
775 | #define TXACKCSR0 0x0110 | |
776 | ||
777 | /* | |
778 | * ACK timeout count registers. | |
779 | * ACKCNT0: TX ACK timeout count. | |
780 | * ACKCNT1: RX ACK timeout count. | |
781 | */ | |
782 | #define ACKCNT0 0x0114 | |
783 | #define ACKCNT1 0x0118 | |
784 | ||
785 | /* | |
786 | * GPIO and others. | |
787 | */ | |
788 | ||
789 | /* | |
790 | * GPIOCSR: GPIO control register. | |
791 | */ | |
792 | #define GPIOCSR 0x0120 | |
793 | #define GPIOCSR_BIT0 FIELD32(0x00000001) | |
794 | #define GPIOCSR_BIT1 FIELD32(0x00000002) | |
795 | #define GPIOCSR_BIT2 FIELD32(0x00000004) | |
796 | #define GPIOCSR_BIT3 FIELD32(0x00000008) | |
797 | #define GPIOCSR_BIT4 FIELD32(0x00000010) | |
798 | #define GPIOCSR_BIT5 FIELD32(0x00000020) | |
799 | #define GPIOCSR_BIT6 FIELD32(0x00000040) | |
800 | #define GPIOCSR_BIT7 FIELD32(0x00000080) | |
801 | #define GPIOCSR_DIR0 FIELD32(0x00000100) | |
802 | #define GPIOCSR_DIR1 FIELD32(0x00000200) | |
803 | #define GPIOCSR_DIR2 FIELD32(0x00000400) | |
804 | #define GPIOCSR_DIR3 FIELD32(0x00000800) | |
805 | #define GPIOCSR_DIR4 FIELD32(0x00001000) | |
806 | #define GPIOCSR_DIR5 FIELD32(0x00002000) | |
807 | #define GPIOCSR_DIR6 FIELD32(0x00004000) | |
808 | #define GPIOCSR_DIR7 FIELD32(0x00008000) | |
809 | ||
810 | /* | |
811 | * FIFO pointer registers. | |
812 | * FIFOCSR0: TX FIFO pointer. | |
813 | * FIFOCSR1: RX FIFO pointer. | |
814 | */ | |
815 | #define FIFOCSR0 0x0128 | |
816 | #define FIFOCSR1 0x012c | |
817 | ||
818 | /* | |
819 | * BCNCSR1: Tx BEACON offset time control register. | |
820 | * PRELOAD: Beacon timer offset in units of usec. | |
821 | * BEACON_CWMIN: 2^CwMin. | |
822 | */ | |
823 | #define BCNCSR1 0x0130 | |
824 | #define BCNCSR1_PRELOAD FIELD32(0x0000ffff) | |
825 | #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000) | |
826 | ||
827 | /* | |
828 | * MACCSR2: TX_PE to RX_PE turn-around time control register | |
829 | * DELAY: RX_PE low width, in units of pci clock cycle. | |
830 | */ | |
831 | #define MACCSR2 0x0134 | |
832 | #define MACCSR2_DELAY FIELD32(0x000000ff) | |
833 | ||
834 | /* | |
835 | * TESTCSR: TEST mode selection register. | |
836 | */ | |
837 | #define TESTCSR 0x0138 | |
838 | ||
839 | /* | |
840 | * ARCSR2: 1 Mbps ACK/CTS PLCP. | |
841 | */ | |
842 | #define ARCSR2 0x013c | |
843 | #define ARCSR2_SIGNAL FIELD32(0x000000ff) | |
844 | #define ARCSR2_SERVICE FIELD32(0x0000ff00) | |
845 | #define ARCSR2_LENGTH FIELD32(0xffff0000) | |
846 | ||
847 | /* | |
848 | * ARCSR3: 2 Mbps ACK/CTS PLCP. | |
849 | */ | |
850 | #define ARCSR3 0x0140 | |
851 | #define ARCSR3_SIGNAL FIELD32(0x000000ff) | |
852 | #define ARCSR3_SERVICE FIELD32(0x0000ff00) | |
853 | #define ARCSR3_LENGTH FIELD32(0xffff0000) | |
854 | ||
855 | /* | |
856 | * ARCSR4: 5.5 Mbps ACK/CTS PLCP. | |
857 | */ | |
858 | #define ARCSR4 0x0144 | |
859 | #define ARCSR4_SIGNAL FIELD32(0x000000ff) | |
860 | #define ARCSR4_SERVICE FIELD32(0x0000ff00) | |
861 | #define ARCSR4_LENGTH FIELD32(0xffff0000) | |
862 | ||
863 | /* | |
864 | * ARCSR5: 11 Mbps ACK/CTS PLCP. | |
865 | */ | |
866 | #define ARCSR5 0x0148 | |
867 | #define ARCSR5_SIGNAL FIELD32(0x000000ff) | |
868 | #define ARCSR5_SERVICE FIELD32(0x0000ff00) | |
869 | #define ARCSR5_LENGTH FIELD32(0xffff0000) | |
870 | ||
871 | /* | |
872 | * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps. | |
873 | */ | |
874 | #define ARTCSR0 0x014c | |
875 | #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff) | |
876 | #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00) | |
877 | #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000) | |
878 | #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000) | |
879 | ||
880 | ||
881 | /* | |
882 | * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. | |
883 | */ | |
884 | #define ARTCSR1 0x0150 | |
885 | #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff) | |
886 | #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00) | |
887 | #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000) | |
888 | #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000) | |
889 | ||
890 | /* | |
891 | * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. | |
892 | */ | |
893 | #define ARTCSR2 0x0154 | |
894 | #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff) | |
895 | #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00) | |
896 | #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000) | |
897 | #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000) | |
898 | ||
899 | /* | |
84263b0c | 900 | * SECCSR1: WEP control register. |
95ea3627 ID |
901 | * KICK_ENCRYPT: Kick encryption engine, self-clear. |
902 | * ONE_SHOT: 0: ring mode, 1: One shot only mode. | |
903 | * DESC_ADDRESS: Descriptor physical address of frame. | |
904 | */ | |
905 | #define SECCSR1 0x0158 | |
906 | #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001) | |
907 | #define SECCSR1_ONE_SHOT FIELD32(0x00000002) | |
908 | #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc) | |
909 | ||
910 | /* | |
911 | * BBPCSR1: BBP TX configuration. | |
912 | */ | |
913 | #define BBPCSR1 0x015c | |
914 | #define BBPCSR1_CCK FIELD32(0x00000003) | |
915 | #define BBPCSR1_CCK_FLIP FIELD32(0x00000004) | |
916 | #define BBPCSR1_OFDM FIELD32(0x00030000) | |
917 | #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000) | |
918 | ||
919 | /* | |
920 | * Dual band configuration registers. | |
921 | * DBANDCSR0: Dual band configuration register 0. | |
922 | * DBANDCSR1: Dual band configuration register 1. | |
923 | */ | |
924 | #define DBANDCSR0 0x0160 | |
925 | #define DBANDCSR1 0x0164 | |
926 | ||
927 | /* | |
928 | * BBPPCSR: BBP Pin control register. | |
929 | */ | |
930 | #define BBPPCSR 0x0168 | |
931 | ||
932 | /* | |
933 | * MAC special debug mode selection registers. | |
934 | * DBGSEL0: MAC special debug mode selection register 0. | |
935 | * DBGSEL1: MAC special debug mode selection register 1. | |
936 | */ | |
937 | #define DBGSEL0 0x016c | |
938 | #define DBGSEL1 0x0170 | |
939 | ||
940 | /* | |
941 | * BISTCSR: BBP BIST register. | |
942 | */ | |
943 | #define BISTCSR 0x0174 | |
944 | ||
945 | /* | |
946 | * Multicast filter registers. | |
947 | * MCAST0: Multicast filter register 0. | |
948 | * MCAST1: Multicast filter register 1. | |
949 | */ | |
950 | #define MCAST0 0x0178 | |
951 | #define MCAST1 0x017c | |
952 | ||
953 | /* | |
954 | * UART registers. | |
955 | * UARTCSR0: UART1 TX register. | |
956 | * UARTCSR1: UART1 RX register. | |
957 | * UARTCSR3: UART1 frame control register. | |
958 | * UARTCSR4: UART1 buffer control register. | |
959 | * UART2CSR0: UART2 TX register. | |
960 | * UART2CSR1: UART2 RX register. | |
961 | * UART2CSR3: UART2 frame control register. | |
962 | * UART2CSR4: UART2 buffer control register. | |
963 | */ | |
964 | #define UARTCSR0 0x0180 | |
965 | #define UARTCSR1 0x0184 | |
966 | #define UARTCSR3 0x0188 | |
967 | #define UARTCSR4 0x018c | |
968 | #define UART2CSR0 0x0190 | |
969 | #define UART2CSR1 0x0194 | |
970 | #define UART2CSR3 0x0198 | |
971 | #define UART2CSR4 0x019c | |
972 | ||
973 | /* | |
974 | * BBP registers. | |
975 | * The wordsize of the BBP is 8 bits. | |
976 | */ | |
977 | ||
978 | /* | |
979 | * R2: TX antenna control | |
980 | */ | |
981 | #define BBP_R2_TX_ANTENNA FIELD8(0x03) | |
982 | #define BBP_R2_TX_IQ_FLIP FIELD8(0x04) | |
983 | ||
984 | /* | |
985 | * R14: RX antenna control | |
986 | */ | |
987 | #define BBP_R14_RX_ANTENNA FIELD8(0x03) | |
988 | #define BBP_R14_RX_IQ_FLIP FIELD8(0x04) | |
989 | ||
990 | /* | |
991 | * BBP_R70 | |
992 | */ | |
993 | #define BBP_R70_JAPAN_FILTER FIELD8(0x08) | |
994 | ||
995 | /* | |
996 | * RF registers | |
997 | */ | |
998 | ||
999 | /* | |
1000 | * RF 1 | |
1001 | */ | |
1002 | #define RF1_TUNER FIELD32(0x00020000) | |
1003 | ||
1004 | /* | |
1005 | * RF 3 | |
1006 | */ | |
1007 | #define RF3_TUNER FIELD32(0x00000100) | |
1008 | #define RF3_TXPOWER FIELD32(0x00003e00) | |
1009 | ||
1010 | /* | |
1011 | * EEPROM content. | |
1012 | * The wordsize of the EEPROM is 16 bits. | |
1013 | */ | |
1014 | ||
1015 | /* | |
1016 | * HW MAC address. | |
1017 | */ | |
1018 | #define EEPROM_MAC_ADDR_0 0x0002 | |
1019 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
1020 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
1021 | #define EEPROM_MAC_ADDR1 0x0003 | |
1022 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
1023 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
1024 | #define EEPROM_MAC_ADDR_2 0x0004 | |
1025 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
1026 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
1027 | ||
1028 | /* | |
1029 | * EEPROM antenna. | |
1030 | * ANTENNA_NUM: Number of antenna's. | |
1031 | * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
1032 | * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
1033 | * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. | |
1034 | * DYN_TXAGC: Dynamic TX AGC control. | |
1035 | * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. | |
1036 | * RF_TYPE: Rf_type of this adapter. | |
1037 | */ | |
1038 | #define EEPROM_ANTENNA 0x10 | |
1039 | #define EEPROM_ANTENNA_NUM FIELD16(0x0003) | |
1040 | #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) | |
1041 | #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) | |
1042 | #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0) | |
1043 | #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) | |
1044 | #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) | |
1045 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) | |
1046 | ||
1047 | /* | |
1048 | * EEPROM NIC config. | |
1049 | * CARDBUS_ACCEL: 0: enable, 1: disable. | |
1050 | * DYN_BBP_TUNE: 0: enable, 1: disable. | |
1051 | * CCK_TX_POWER: CCK TX power compensation. | |
1052 | */ | |
1053 | #define EEPROM_NIC 0x11 | |
1054 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001) | |
1055 | #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002) | |
1056 | #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c) | |
1057 | ||
1058 | /* | |
1059 | * EEPROM geography. | |
1060 | * GEO: Default geography setting for device. | |
1061 | */ | |
1062 | #define EEPROM_GEOGRAPHY 0x12 | |
1063 | #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00) | |
1064 | ||
1065 | /* | |
1066 | * EEPROM BBP. | |
1067 | */ | |
1068 | #define EEPROM_BBP_START 0x13 | |
1069 | #define EEPROM_BBP_SIZE 16 | |
1070 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
1071 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
1072 | ||
1073 | /* | |
1074 | * EEPROM TXPOWER | |
1075 | */ | |
1076 | #define EEPROM_TXPOWER_START 0x23 | |
1077 | #define EEPROM_TXPOWER_SIZE 7 | |
1078 | #define EEPROM_TXPOWER_1 FIELD16(0x00ff) | |
1079 | #define EEPROM_TXPOWER_2 FIELD16(0xff00) | |
1080 | ||
1081 | /* | |
1082 | * RSSI <-> dBm offset calibration | |
1083 | */ | |
1084 | #define EEPROM_CALIBRATE_OFFSET 0x3e | |
1085 | #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff) | |
1086 | ||
1087 | /* | |
1088 | * DMA descriptor defines. | |
1089 | */ | |
4bd7c452 ID |
1090 | #define TXD_DESC_SIZE ( 11 * sizeof(__le32) ) |
1091 | #define RXD_DESC_SIZE ( 11 * sizeof(__le32) ) | |
95ea3627 ID |
1092 | |
1093 | /* | |
1094 | * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. | |
1095 | */ | |
1096 | ||
1097 | /* | |
1098 | * Word0 | |
1099 | */ | |
1100 | #define TXD_W0_OWNER_NIC FIELD32(0x00000001) | |
1101 | #define TXD_W0_VALID FIELD32(0x00000002) | |
1102 | #define TXD_W0_RESULT FIELD32(0x0000001c) | |
1103 | #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) | |
1104 | #define TXD_W0_MORE_FRAG FIELD32(0x00000100) | |
1105 | #define TXD_W0_ACK FIELD32(0x00000200) | |
1106 | #define TXD_W0_TIMESTAMP FIELD32(0x00000400) | |
1107 | #define TXD_W0_OFDM FIELD32(0x00000800) | |
1108 | #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000) | |
1109 | #define TXD_W0_IFS FIELD32(0x00006000) | |
1110 | #define TXD_W0_RETRY_MODE FIELD32(0x00008000) | |
1111 | #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
1112 | #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
1113 | ||
1114 | /* | |
1115 | * Word1 | |
1116 | */ | |
1117 | #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
1118 | ||
1119 | /* | |
1120 | * Word2 | |
1121 | */ | |
1122 | #define TXD_W2_IV_OFFSET FIELD32(0x0000003f) | |
1123 | #define TXD_W2_AIFS FIELD32(0x000000c0) | |
1124 | #define TXD_W2_CWMIN FIELD32(0x00000f00) | |
1125 | #define TXD_W2_CWMAX FIELD32(0x0000f000) | |
1126 | ||
1127 | /* | |
1128 | * Word3: PLCP information | |
1129 | */ | |
1130 | #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) | |
1131 | #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00) | |
1132 | #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000) | |
1133 | #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000) | |
1134 | ||
1135 | /* | |
1136 | * Word4 | |
1137 | */ | |
1138 | #define TXD_W4_IV FIELD32(0xffffffff) | |
1139 | ||
1140 | /* | |
1141 | * Word5 | |
1142 | */ | |
1143 | #define TXD_W5_EIV FIELD32(0xffffffff) | |
1144 | ||
1145 | /* | |
1146 | * Word6-9: Key | |
1147 | */ | |
1148 | #define TXD_W6_KEY FIELD32(0xffffffff) | |
1149 | #define TXD_W7_KEY FIELD32(0xffffffff) | |
1150 | #define TXD_W8_KEY FIELD32(0xffffffff) | |
1151 | #define TXD_W9_KEY FIELD32(0xffffffff) | |
1152 | ||
1153 | /* | |
1154 | * Word10 | |
1155 | */ | |
1156 | #define TXD_W10_RTS FIELD32(0x00000001) | |
1157 | #define TXD_W10_TX_RATE FIELD32(0x000000fe) | |
1158 | ||
1159 | /* | |
1160 | * RX descriptor format for RX Ring. | |
1161 | */ | |
1162 | ||
1163 | /* | |
1164 | * Word0 | |
1165 | */ | |
1166 | #define RXD_W0_OWNER_NIC FIELD32(0x00000001) | |
1167 | #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) | |
1168 | #define RXD_W0_MULTICAST FIELD32(0x00000004) | |
1169 | #define RXD_W0_BROADCAST FIELD32(0x00000008) | |
1170 | #define RXD_W0_MY_BSS FIELD32(0x00000010) | |
1171 | #define RXD_W0_CRC_ERROR FIELD32(0x00000020) | |
1172 | #define RXD_W0_OFDM FIELD32(0x00000040) | |
1173 | #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) | |
1174 | #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100) | |
1175 | #define RXD_W0_ICV_ERROR FIELD32(0x00000200) | |
1176 | #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00) | |
1177 | #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
1178 | #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
1179 | ||
1180 | /* | |
1181 | * Word1 | |
1182 | */ | |
1183 | #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
1184 | ||
1185 | /* | |
1186 | * Word2 | |
1187 | */ | |
1188 | #define RXD_W2_SIGNAL FIELD32(0x000000ff) | |
1189 | #define RXD_W2_RSSI FIELD32(0x0000ff00) | |
1190 | #define RXD_W2_TA FIELD32(0xffff0000) | |
1191 | ||
1192 | /* | |
1193 | * Word3 | |
1194 | */ | |
1195 | #define RXD_W3_TA FIELD32(0xffffffff) | |
1196 | ||
1197 | /* | |
1198 | * Word4 | |
1199 | */ | |
1200 | #define RXD_W4_IV FIELD32(0xffffffff) | |
1201 | ||
1202 | /* | |
1203 | * Word5 | |
1204 | */ | |
1205 | #define RXD_W5_EIV FIELD32(0xffffffff) | |
1206 | ||
1207 | /* | |
1208 | * Word6-9: Key | |
1209 | */ | |
1210 | #define RXD_W6_KEY FIELD32(0xffffffff) | |
1211 | #define RXD_W7_KEY FIELD32(0xffffffff) | |
1212 | #define RXD_W8_KEY FIELD32(0xffffffff) | |
1213 | #define RXD_W9_KEY FIELD32(0xffffffff) | |
1214 | ||
1215 | /* | |
1216 | * Word10 | |
1217 | */ | |
1218 | #define RXD_W10_DROP FIELD32(0x00000001) | |
1219 | ||
1220 | /* | |
de99ff82 ID |
1221 | * Macro's for converting txpower from EEPROM to mac80211 value |
1222 | * and from mac80211 value to register value. | |
95ea3627 ID |
1223 | */ |
1224 | #define MIN_TXPOWER 0 | |
1225 | #define MAX_TXPOWER 31 | |
1226 | #define DEFAULT_TXPOWER 24 | |
1227 | ||
8c5e7a5f ID |
1228 | #define TXPOWER_FROM_DEV(__txpower) \ |
1229 | (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
1230 | ||
1231 | #define TXPOWER_TO_DEV(__txpower) \ | |
1232 | clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) | |
95ea3627 ID |
1233 | |
1234 | #endif /* RT2500PCI_H */ |