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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt2500pci | |
23 | Abstract: Data structures and registers for the rt2500pci module. | |
24 | Supported chipsets: RT2560. | |
25 | */ | |
26 | ||
27 | #ifndef RT2500PCI_H | |
28 | #define RT2500PCI_H | |
29 | ||
30 | /* | |
31 | * RF chip defines. | |
32 | */ | |
33 | #define RF2522 0x0000 | |
34 | #define RF2523 0x0001 | |
35 | #define RF2524 0x0002 | |
36 | #define RF2525 0x0003 | |
37 | #define RF2525E 0x0004 | |
38 | #define RF5222 0x0010 | |
39 | ||
40 | /* | |
41 | * RT2560 version | |
42 | */ | |
43 | #define RT2560_VERSION_B 2 | |
44 | #define RT2560_VERSION_C 3 | |
45 | #define RT2560_VERSION_D 4 | |
46 | ||
47 | /* | |
48 | * Signal information. | |
49 | * Defaul offset is required for RSSI <-> dBm conversion. | |
50 | */ | |
95ea3627 ID |
51 | #define DEFAULT_RSSI_OFFSET 121 |
52 | ||
53 | /* | |
54 | * Register layout information. | |
55 | */ | |
56 | #define CSR_REG_BASE 0x0000 | |
57 | #define CSR_REG_SIZE 0x0174 | |
58 | #define EEPROM_BASE 0x0000 | |
59 | #define EEPROM_SIZE 0x0200 | |
60 | #define BBP_SIZE 0x0040 | |
61 | #define RF_SIZE 0x0014 | |
62 | ||
61448f88 GW |
63 | /* |
64 | * Number of TX queues. | |
65 | */ | |
66 | #define NUM_TX_QUEUES 2 | |
67 | ||
95ea3627 ID |
68 | /* |
69 | * Control/Status Registers(CSR). | |
70 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
71 | */ | |
72 | ||
73 | /* | |
74 | * CSR0: ASIC revision number. | |
75 | */ | |
76 | #define CSR0 0x0000 | |
77 | ||
78 | /* | |
79 | * CSR1: System control register. | |
80 | * SOFT_RESET: Software reset, 1: reset, 0: normal. | |
81 | * BBP_RESET: Hardware reset, 1: reset, 0, release. | |
82 | * HOST_READY: Host ready after initialization. | |
83 | */ | |
84 | #define CSR1 0x0004 | |
85 | #define CSR1_SOFT_RESET FIELD32(0x00000001) | |
86 | #define CSR1_BBP_RESET FIELD32(0x00000002) | |
87 | #define CSR1_HOST_READY FIELD32(0x00000004) | |
88 | ||
89 | /* | |
90 | * CSR2: System admin status register (invalid). | |
91 | */ | |
92 | #define CSR2 0x0008 | |
93 | ||
94 | /* | |
95 | * CSR3: STA MAC address register 0. | |
96 | */ | |
97 | #define CSR3 0x000c | |
98 | #define CSR3_BYTE0 FIELD32(0x000000ff) | |
99 | #define CSR3_BYTE1 FIELD32(0x0000ff00) | |
100 | #define CSR3_BYTE2 FIELD32(0x00ff0000) | |
101 | #define CSR3_BYTE3 FIELD32(0xff000000) | |
102 | ||
103 | /* | |
104 | * CSR4: STA MAC address register 1. | |
105 | */ | |
106 | #define CSR4 0x0010 | |
107 | #define CSR4_BYTE4 FIELD32(0x000000ff) | |
108 | #define CSR4_BYTE5 FIELD32(0x0000ff00) | |
109 | ||
110 | /* | |
111 | * CSR5: BSSID register 0. | |
112 | */ | |
113 | #define CSR5 0x0014 | |
114 | #define CSR5_BYTE0 FIELD32(0x000000ff) | |
115 | #define CSR5_BYTE1 FIELD32(0x0000ff00) | |
116 | #define CSR5_BYTE2 FIELD32(0x00ff0000) | |
117 | #define CSR5_BYTE3 FIELD32(0xff000000) | |
118 | ||
119 | /* | |
120 | * CSR6: BSSID register 1. | |
121 | */ | |
122 | #define CSR6 0x0018 | |
123 | #define CSR6_BYTE4 FIELD32(0x000000ff) | |
124 | #define CSR6_BYTE5 FIELD32(0x0000ff00) | |
125 | ||
126 | /* | |
127 | * CSR7: Interrupt source register. | |
128 | * Write 1 to clear. | |
129 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
130 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
131 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
132 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
133 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
134 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
135 | * RXDONE: Receive done interrupt. | |
136 | * DECRYPTION_DONE: Decryption done interrupt. | |
137 | * ENCRYPTION_DONE: Encryption done interrupt. | |
138 | * UART1_TX_TRESHOLD: UART1 TX reaches threshold. | |
139 | * UART1_RX_TRESHOLD: UART1 RX reaches threshold. | |
140 | * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. | |
141 | * UART1_TX_BUFF_ERROR: UART1 TX buffer error. | |
142 | * UART1_RX_BUFF_ERROR: UART1 RX buffer error. | |
143 | * UART2_TX_TRESHOLD: UART2 TX reaches threshold. | |
144 | * UART2_RX_TRESHOLD: UART2 RX reaches threshold. | |
145 | * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. | |
146 | * UART2_TX_BUFF_ERROR: UART2 TX buffer error. | |
147 | * UART2_RX_BUFF_ERROR: UART2 RX buffer error. | |
148 | * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). | |
149 | ||
150 | */ | |
151 | #define CSR7 0x001c | |
152 | #define CSR7_TBCN_EXPIRE FIELD32(0x00000001) | |
153 | #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) | |
154 | #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) | |
155 | #define CSR7_TXDONE_TXRING FIELD32(0x00000008) | |
156 | #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) | |
157 | #define CSR7_TXDONE_PRIORING FIELD32(0x00000020) | |
158 | #define CSR7_RXDONE FIELD32(0x00000040) | |
159 | #define CSR7_DECRYPTION_DONE FIELD32(0x00000080) | |
160 | #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100) | |
161 | #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200) | |
162 | #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400) | |
163 | #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800) | |
164 | #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000) | |
165 | #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000) | |
166 | #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000) | |
167 | #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000) | |
168 | #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000) | |
169 | #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000) | |
170 | #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000) | |
171 | #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000) | |
172 | ||
173 | /* | |
174 | * CSR8: Interrupt mask register. | |
175 | * Write 1 to mask interrupt. | |
176 | * TBCN_EXPIRE: Beacon timer expired interrupt. | |
177 | * TWAKE_EXPIRE: Wakeup timer expired interrupt. | |
178 | * TATIMW_EXPIRE: Timer of atim window expired interrupt. | |
179 | * TXDONE_TXRING: Tx ring transmit done interrupt. | |
180 | * TXDONE_ATIMRING: Atim ring transmit done interrupt. | |
181 | * TXDONE_PRIORING: Priority ring transmit done interrupt. | |
182 | * RXDONE: Receive done interrupt. | |
183 | * DECRYPTION_DONE: Decryption done interrupt. | |
184 | * ENCRYPTION_DONE: Encryption done interrupt. | |
185 | * UART1_TX_TRESHOLD: UART1 TX reaches threshold. | |
186 | * UART1_RX_TRESHOLD: UART1 RX reaches threshold. | |
187 | * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. | |
188 | * UART1_TX_BUFF_ERROR: UART1 TX buffer error. | |
189 | * UART1_RX_BUFF_ERROR: UART1 RX buffer error. | |
190 | * UART2_TX_TRESHOLD: UART2 TX reaches threshold. | |
191 | * UART2_RX_TRESHOLD: UART2 RX reaches threshold. | |
192 | * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. | |
193 | * UART2_TX_BUFF_ERROR: UART2 TX buffer error. | |
194 | * UART2_RX_BUFF_ERROR: UART2 RX buffer error. | |
195 | * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). | |
196 | */ | |
197 | #define CSR8 0x0020 | |
198 | #define CSR8_TBCN_EXPIRE FIELD32(0x00000001) | |
199 | #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) | |
200 | #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) | |
201 | #define CSR8_TXDONE_TXRING FIELD32(0x00000008) | |
202 | #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) | |
203 | #define CSR8_TXDONE_PRIORING FIELD32(0x00000020) | |
204 | #define CSR8_RXDONE FIELD32(0x00000040) | |
205 | #define CSR8_DECRYPTION_DONE FIELD32(0x00000080) | |
206 | #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100) | |
207 | #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200) | |
208 | #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400) | |
209 | #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800) | |
210 | #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000) | |
211 | #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000) | |
212 | #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000) | |
213 | #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000) | |
214 | #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000) | |
215 | #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000) | |
216 | #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000) | |
217 | #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000) | |
218 | ||
219 | /* | |
220 | * CSR9: Maximum frame length register. | |
221 | * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. | |
222 | */ | |
223 | #define CSR9 0x0024 | |
224 | #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) | |
225 | ||
226 | /* | |
227 | * SECCSR0: WEP control register. | |
228 | * KICK_DECRYPT: Kick decryption engine, self-clear. | |
229 | * ONE_SHOT: 0: ring mode, 1: One shot only mode. | |
230 | * DESC_ADDRESS: Descriptor physical address of frame. | |
231 | */ | |
232 | #define SECCSR0 0x0028 | |
233 | #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001) | |
234 | #define SECCSR0_ONE_SHOT FIELD32(0x00000002) | |
235 | #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc) | |
236 | ||
237 | /* | |
238 | * CSR11: Back-off control register. | |
239 | * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). | |
240 | * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). | |
241 | * SLOT_TIME: Slot time, default is 20us for 802.11b | |
242 | * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD. | |
243 | * LONG_RETRY: Long retry count. | |
244 | * SHORT_RETRY: Short retry count. | |
245 | */ | |
246 | #define CSR11 0x002c | |
247 | #define CSR11_CWMIN FIELD32(0x0000000f) | |
248 | #define CSR11_CWMAX FIELD32(0x000000f0) | |
249 | #define CSR11_SLOT_TIME FIELD32(0x00001f00) | |
250 | #define CSR11_CW_SELECT FIELD32(0x00002000) | |
251 | #define CSR11_LONG_RETRY FIELD32(0x00ff0000) | |
252 | #define CSR11_SHORT_RETRY FIELD32(0xff000000) | |
253 | ||
254 | /* | |
255 | * CSR12: Synchronization configuration register 0. | |
256 | * All units in 1/16 TU. | |
257 | * BEACON_INTERVAL: Beacon interval, default is 100 TU. | |
258 | * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU. | |
259 | */ | |
260 | #define CSR12 0x0030 | |
261 | #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) | |
262 | #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) | |
263 | ||
264 | /* | |
265 | * CSR13: Synchronization configuration register 1. | |
266 | * All units in 1/16 TU. | |
267 | * ATIMW_DURATION: Atim window duration. | |
268 | * CFP_PERIOD: Cfp period, default is 0 TU. | |
269 | */ | |
270 | #define CSR13 0x0034 | |
271 | #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) | |
272 | #define CSR13_CFP_PERIOD FIELD32(0x00ff0000) | |
273 | ||
274 | /* | |
275 | * CSR14: Synchronization control register. | |
276 | * TSF_COUNT: Enable tsf auto counting. | |
277 | * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. | |
278 | * TBCN: Enable tbcn with reload value. | |
279 | * TCFP: Enable tcfp & cfp / cp switching. | |
280 | * TATIMW: Enable tatimw & atim window switching. | |
281 | * BEACON_GEN: Enable beacon generator. | |
282 | * CFP_COUNT_PRELOAD: Cfp count preload value. | |
283 | * TBCM_PRELOAD: Tbcn preload value in units of 64us. | |
284 | */ | |
285 | #define CSR14 0x0038 | |
286 | #define CSR14_TSF_COUNT FIELD32(0x00000001) | |
287 | #define CSR14_TSF_SYNC FIELD32(0x00000006) | |
288 | #define CSR14_TBCN FIELD32(0x00000008) | |
289 | #define CSR14_TCFP FIELD32(0x00000010) | |
290 | #define CSR14_TATIMW FIELD32(0x00000020) | |
291 | #define CSR14_BEACON_GEN FIELD32(0x00000040) | |
292 | #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) | |
293 | #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) | |
294 | ||
295 | /* | |
296 | * CSR15: Synchronization status register. | |
297 | * CFP: ASIC is in contention-free period. | |
298 | * ATIMW: ASIC is in ATIM window. | |
299 | * BEACON_SENT: Beacon is send. | |
300 | */ | |
301 | #define CSR15 0x003c | |
302 | #define CSR15_CFP FIELD32(0x00000001) | |
303 | #define CSR15_ATIMW FIELD32(0x00000002) | |
304 | #define CSR15_BEACON_SENT FIELD32(0x00000004) | |
305 | ||
306 | /* | |
307 | * CSR16: TSF timer register 0. | |
308 | */ | |
309 | #define CSR16 0x0040 | |
310 | #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) | |
311 | ||
312 | /* | |
313 | * CSR17: TSF timer register 1. | |
314 | */ | |
315 | #define CSR17 0x0044 | |
316 | #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) | |
317 | ||
318 | /* | |
319 | * CSR18: IFS timer register 0. | |
320 | * SIFS: Sifs, default is 10 us. | |
321 | * PIFS: Pifs, default is 30 us. | |
322 | */ | |
323 | #define CSR18 0x0048 | |
324 | #define CSR18_SIFS FIELD32(0x000001ff) | |
325 | #define CSR18_PIFS FIELD32(0x001f0000) | |
326 | ||
327 | /* | |
328 | * CSR19: IFS timer register 1. | |
329 | * DIFS: Difs, default is 50 us. | |
330 | * EIFS: Eifs, default is 364 us. | |
331 | */ | |
332 | #define CSR19 0x004c | |
333 | #define CSR19_DIFS FIELD32(0x0000ffff) | |
334 | #define CSR19_EIFS FIELD32(0xffff0000) | |
335 | ||
336 | /* | |
337 | * CSR20: Wakeup timer register. | |
338 | * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. | |
339 | * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. | |
340 | * AUTOWAKE: Enable auto wakeup / sleep mechanism. | |
341 | */ | |
342 | #define CSR20 0x0050 | |
343 | #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) | |
344 | #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) | |
345 | #define CSR20_AUTOWAKE FIELD32(0x01000000) | |
346 | ||
347 | /* | |
348 | * CSR21: EEPROM control register. | |
349 | * RELOAD: Write 1 to reload eeprom content. | |
350 | * TYPE_93C46: 1: 93c46, 0:93c66. | |
351 | */ | |
352 | #define CSR21 0x0054 | |
353 | #define CSR21_RELOAD FIELD32(0x00000001) | |
354 | #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) | |
355 | #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) | |
356 | #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) | |
357 | #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) | |
358 | #define CSR21_TYPE_93C46 FIELD32(0x00000020) | |
359 | ||
360 | /* | |
361 | * CSR22: CFP control register. | |
362 | * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. | |
363 | * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. | |
364 | */ | |
365 | #define CSR22 0x0058 | |
366 | #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) | |
367 | #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) | |
368 | ||
369 | /* | |
370 | * Transmit related CSRs. | |
371 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
372 | */ | |
373 | ||
374 | /* | |
375 | * TXCSR0: TX Control Register. | |
376 | * KICK_TX: Kick tx ring. | |
377 | * KICK_ATIM: Kick atim ring. | |
378 | * KICK_PRIO: Kick priority ring. | |
379 | * ABORT: Abort all transmit related ring operation. | |
380 | */ | |
381 | #define TXCSR0 0x0060 | |
382 | #define TXCSR0_KICK_TX FIELD32(0x00000001) | |
383 | #define TXCSR0_KICK_ATIM FIELD32(0x00000002) | |
384 | #define TXCSR0_KICK_PRIO FIELD32(0x00000004) | |
385 | #define TXCSR0_ABORT FIELD32(0x00000008) | |
386 | ||
387 | /* | |
388 | * TXCSR1: TX Configuration Register. | |
389 | * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. | |
390 | * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. | |
391 | * TSF_OFFSET: Insert tsf offset. | |
392 | * AUTORESPONDER: Enable auto responder which include ack & cts. | |
393 | */ | |
394 | #define TXCSR1 0x0064 | |
395 | #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) | |
396 | #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) | |
397 | #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) | |
398 | #define TXCSR1_AUTORESPONDER FIELD32(0x01000000) | |
399 | ||
400 | /* | |
401 | * TXCSR2: Tx descriptor configuration register. | |
402 | * TXD_SIZE: Tx descriptor size, default is 48. | |
403 | * NUM_TXD: Number of tx entries in ring. | |
404 | * NUM_ATIM: Number of atim entries in ring. | |
405 | * NUM_PRIO: Number of priority entries in ring. | |
406 | */ | |
407 | #define TXCSR2 0x0068 | |
408 | #define TXCSR2_TXD_SIZE FIELD32(0x000000ff) | |
409 | #define TXCSR2_NUM_TXD FIELD32(0x0000ff00) | |
410 | #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) | |
411 | #define TXCSR2_NUM_PRIO FIELD32(0xff000000) | |
412 | ||
413 | /* | |
414 | * TXCSR3: TX Ring Base address register. | |
415 | */ | |
416 | #define TXCSR3 0x006c | |
417 | #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) | |
418 | ||
419 | /* | |
420 | * TXCSR4: TX Atim Ring Base address register. | |
421 | */ | |
422 | #define TXCSR4 0x0070 | |
423 | #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) | |
424 | ||
425 | /* | |
426 | * TXCSR5: TX Prio Ring Base address register. | |
427 | */ | |
428 | #define TXCSR5 0x0074 | |
429 | #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) | |
430 | ||
431 | /* | |
432 | * TXCSR6: Beacon Base address register. | |
433 | */ | |
434 | #define TXCSR6 0x0078 | |
435 | #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) | |
436 | ||
437 | /* | |
438 | * TXCSR7: Auto responder control register. | |
439 | * AR_POWERMANAGEMENT: Auto responder power management bit. | |
440 | */ | |
441 | #define TXCSR7 0x007c | |
442 | #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) | |
443 | ||
444 | /* | |
445 | * TXCSR8: CCK Tx BBP register. | |
446 | */ | |
447 | #define TXCSR8 0x0098 | |
448 | #define TXCSR8_BBP_ID0 FIELD32(0x0000007f) | |
449 | #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080) | |
450 | #define TXCSR8_BBP_ID1 FIELD32(0x00007f00) | |
451 | #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000) | |
452 | #define TXCSR8_BBP_ID2 FIELD32(0x007f0000) | |
453 | #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000) | |
454 | #define TXCSR8_BBP_ID3 FIELD32(0x7f000000) | |
455 | #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000) | |
456 | ||
457 | /* | |
458 | * TXCSR9: OFDM TX BBP registers | |
459 | * OFDM_SIGNAL: BBP rate field address for OFDM. | |
460 | * OFDM_SERVICE: BBP service field address for OFDM. | |
461 | * OFDM_LENGTH_LOW: BBP length low byte address for OFDM. | |
462 | * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM. | |
463 | */ | |
464 | #define TXCSR9 0x0094 | |
465 | #define TXCSR9_OFDM_RATE FIELD32(0x000000ff) | |
466 | #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00) | |
467 | #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000) | |
468 | #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000) | |
469 | ||
470 | /* | |
471 | * Receive related CSRs. | |
472 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
473 | */ | |
474 | ||
475 | /* | |
476 | * RXCSR0: RX Control Register. | |
477 | * DISABLE_RX: Disable rx engine. | |
478 | * DROP_CRC: Drop crc error. | |
479 | * DROP_PHYSICAL: Drop physical error. | |
480 | * DROP_CONTROL: Drop control frame. | |
481 | * DROP_NOT_TO_ME: Drop not to me unicast frame. | |
482 | * DROP_TODS: Drop frame tods bit is true. | |
483 | * DROP_VERSION_ERROR: Drop version error frame. | |
484 | * PASS_CRC: Pass all packets with crc attached. | |
485 | * PASS_CRC: Pass all packets with crc attached. | |
486 | * PASS_PLCP: Pass all packets with 4 bytes PLCP attached. | |
487 | * DROP_MCAST: Drop multicast frames. | |
488 | * DROP_BCAST: Drop broadcast frames. | |
489 | * ENABLE_QOS: Accept QOS data frame and parse QOS field. | |
490 | */ | |
491 | #define RXCSR0 0x0080 | |
492 | #define RXCSR0_DISABLE_RX FIELD32(0x00000001) | |
493 | #define RXCSR0_DROP_CRC FIELD32(0x00000002) | |
494 | #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) | |
495 | #define RXCSR0_DROP_CONTROL FIELD32(0x00000008) | |
496 | #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) | |
497 | #define RXCSR0_DROP_TODS FIELD32(0x00000020) | |
498 | #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) | |
499 | #define RXCSR0_PASS_CRC FIELD32(0x00000080) | |
500 | #define RXCSR0_PASS_PLCP FIELD32(0x00000100) | |
501 | #define RXCSR0_DROP_MCAST FIELD32(0x00000200) | |
502 | #define RXCSR0_DROP_BCAST FIELD32(0x00000400) | |
503 | #define RXCSR0_ENABLE_QOS FIELD32(0x00000800) | |
504 | ||
505 | /* | |
506 | * RXCSR1: RX descriptor configuration register. | |
507 | * RXD_SIZE: Rx descriptor size, default is 32b. | |
508 | * NUM_RXD: Number of rx entries in ring. | |
509 | */ | |
510 | #define RXCSR1 0x0084 | |
511 | #define RXCSR1_RXD_SIZE FIELD32(0x000000ff) | |
512 | #define RXCSR1_NUM_RXD FIELD32(0x0000ff00) | |
513 | ||
514 | /* | |
515 | * RXCSR2: RX Ring base address register. | |
516 | */ | |
517 | #define RXCSR2 0x0088 | |
518 | #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) | |
519 | ||
520 | /* | |
521 | * RXCSR3: BBP ID register for Rx operation. | |
522 | * BBP_ID#: BBP register # id. | |
523 | * BBP_ID#_VALID: BBP register # id is valid or not. | |
524 | */ | |
525 | #define RXCSR3 0x0090 | |
526 | #define RXCSR3_BBP_ID0 FIELD32(0x0000007f) | |
527 | #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) | |
528 | #define RXCSR3_BBP_ID1 FIELD32(0x00007f00) | |
529 | #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) | |
530 | #define RXCSR3_BBP_ID2 FIELD32(0x007f0000) | |
531 | #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) | |
532 | #define RXCSR3_BBP_ID3 FIELD32(0x7f000000) | |
533 | #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) | |
534 | ||
535 | /* | |
536 | * ARCSR1: Auto Responder PLCP config register 1. | |
537 | * AR_BBP_DATA#: Auto responder BBP register # data. | |
538 | * AR_BBP_ID#: Auto responder BBP register # Id. | |
539 | */ | |
540 | #define ARCSR1 0x009c | |
541 | #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) | |
542 | #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) | |
543 | #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) | |
544 | #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) | |
545 | ||
546 | /* | |
547 | * Miscellaneous Registers. | |
548 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
549 | ||
550 | */ | |
551 | ||
552 | /* | |
553 | * PCICSR: PCI control register. | |
554 | * BIG_ENDIAN: 1: big endian, 0: little endian. | |
555 | * RX_TRESHOLD: Rx threshold in dw to start pci access | |
556 | * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. | |
557 | * TX_TRESHOLD: Tx threshold in dw to start pci access | |
558 | * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. | |
559 | * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. | |
560 | * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. | |
561 | * READ_MULTIPLE: Enable memory read multiple. | |
562 | * WRITE_INVALID: Enable memory write & invalid. | |
563 | */ | |
564 | #define PCICSR 0x008c | |
565 | #define PCICSR_BIG_ENDIAN FIELD32(0x00000001) | |
566 | #define PCICSR_RX_TRESHOLD FIELD32(0x00000006) | |
567 | #define PCICSR_TX_TRESHOLD FIELD32(0x00000018) | |
568 | #define PCICSR_BURST_LENTH FIELD32(0x00000060) | |
569 | #define PCICSR_ENABLE_CLK FIELD32(0x00000080) | |
570 | #define PCICSR_READ_MULTIPLE FIELD32(0x00000100) | |
571 | #define PCICSR_WRITE_INVALID FIELD32(0x00000200) | |
572 | ||
573 | /* | |
574 | * CNT0: FCS error count. | |
575 | * FCS_ERROR: FCS error count, cleared when read. | |
576 | */ | |
577 | #define CNT0 0x00a0 | |
578 | #define CNT0_FCS_ERROR FIELD32(0x0000ffff) | |
579 | ||
580 | /* | |
581 | * Statistic Register. | |
582 | * CNT1: PLCP error count. | |
583 | * CNT2: Long error count. | |
584 | */ | |
585 | #define TIMECSR2 0x00a8 | |
586 | #define CNT1 0x00ac | |
587 | #define CNT2 0x00b0 | |
588 | #define TIMECSR3 0x00b4 | |
589 | ||
590 | /* | |
591 | * CNT3: CCA false alarm count. | |
592 | */ | |
593 | #define CNT3 0x00b8 | |
594 | #define CNT3_FALSE_CCA FIELD32(0x0000ffff) | |
595 | ||
596 | /* | |
597 | * Statistic Register. | |
598 | * CNT4: Rx FIFO overflow count. | |
599 | * CNT5: Tx FIFO underrun count. | |
600 | */ | |
601 | #define CNT4 0x00bc | |
602 | #define CNT5 0x00c0 | |
603 | ||
604 | /* | |
605 | * Baseband Control Register. | |
606 | */ | |
607 | ||
608 | /* | |
609 | * PWRCSR0: Power mode configuration register. | |
610 | */ | |
611 | #define PWRCSR0 0x00c4 | |
612 | ||
613 | /* | |
614 | * Power state transition time registers. | |
615 | */ | |
616 | #define PSCSR0 0x00c8 | |
617 | #define PSCSR1 0x00cc | |
618 | #define PSCSR2 0x00d0 | |
619 | #define PSCSR3 0x00d4 | |
620 | ||
621 | /* | |
622 | * PWRCSR1: Manual power control / status register. | |
623 | * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. | |
624 | * SET_STATE: Set state. Write 1 to trigger, self cleared. | |
625 | * BBP_DESIRE_STATE: BBP desired state. | |
626 | * RF_DESIRE_STATE: RF desired state. | |
627 | * BBP_CURR_STATE: BBP current state. | |
628 | * RF_CURR_STATE: RF current state. | |
629 | * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. | |
630 | */ | |
631 | #define PWRCSR1 0x00d8 | |
632 | #define PWRCSR1_SET_STATE FIELD32(0x00000001) | |
633 | #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) | |
634 | #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) | |
635 | #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) | |
636 | #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) | |
637 | #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) | |
638 | ||
639 | /* | |
640 | * TIMECSR: Timer control register. | |
641 | * US_COUNT: 1 us timer count in units of clock cycles. | |
642 | * US_64_COUNT: 64 us timer count in units of 1 us timer. | |
643 | * BEACON_EXPECT: Beacon expect window. | |
644 | */ | |
645 | #define TIMECSR 0x00dc | |
646 | #define TIMECSR_US_COUNT FIELD32(0x000000ff) | |
647 | #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) | |
648 | #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) | |
649 | ||
650 | /* | |
651 | * MACCSR0: MAC configuration register 0. | |
652 | */ | |
653 | #define MACCSR0 0x00e0 | |
654 | ||
655 | /* | |
656 | * MACCSR1: MAC configuration register 1. | |
657 | * KICK_RX: Kick one-shot rx in one-shot rx mode. | |
658 | * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. | |
659 | * BBPRX_RESET_MODE: Ralink bbp rx reset mode. | |
660 | * AUTO_TXBBP: Auto tx logic access bbp control register. | |
661 | * AUTO_RXBBP: Auto rx logic access bbp control register. | |
662 | * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. | |
663 | * INTERSIL_IF: Intersil if calibration pin. | |
664 | */ | |
665 | #define MACCSR1 0x00e4 | |
666 | #define MACCSR1_KICK_RX FIELD32(0x00000001) | |
667 | #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) | |
668 | #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) | |
669 | #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) | |
670 | #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) | |
671 | #define MACCSR1_LOOPBACK FIELD32(0x00000060) | |
672 | #define MACCSR1_INTERSIL_IF FIELD32(0x00000080) | |
673 | ||
674 | /* | |
675 | * RALINKCSR: Ralink Rx auto-reset BBCR. | |
676 | * AR_BBP_DATA#: Auto reset BBP register # data. | |
677 | * AR_BBP_ID#: Auto reset BBP register # id. | |
678 | */ | |
679 | #define RALINKCSR 0x00e8 | |
680 | #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) | |
681 | #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00) | |
682 | #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000) | |
683 | #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) | |
684 | #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000) | |
685 | #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000) | |
686 | ||
687 | /* | |
688 | * BCNCSR: Beacon interval control register. | |
689 | * CHANGE: Write one to change beacon interval. | |
690 | * DELTATIME: The delta time value. | |
691 | * NUM_BEACON: Number of beacon according to mode. | |
692 | * MODE: Please refer to asic specs. | |
693 | * PLUS: Plus or minus delta time value. | |
694 | */ | |
695 | #define BCNCSR 0x00ec | |
696 | #define BCNCSR_CHANGE FIELD32(0x00000001) | |
697 | #define BCNCSR_DELTATIME FIELD32(0x0000001e) | |
698 | #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) | |
699 | #define BCNCSR_MODE FIELD32(0x00006000) | |
700 | #define BCNCSR_PLUS FIELD32(0x00008000) | |
701 | ||
702 | /* | |
703 | * BBP / RF / IF Control Register. | |
704 | */ | |
705 | ||
706 | /* | |
707 | * BBPCSR: BBP serial control register. | |
708 | * VALUE: Register value to program into BBP. | |
709 | * REGNUM: Selected BBP register. | |
710 | * BUSY: 1: asic is busy execute BBP programming. | |
711 | * WRITE_CONTROL: 1: write BBP, 0: read BBP. | |
712 | */ | |
713 | #define BBPCSR 0x00f0 | |
714 | #define BBPCSR_VALUE FIELD32(0x000000ff) | |
715 | #define BBPCSR_REGNUM FIELD32(0x00007f00) | |
716 | #define BBPCSR_BUSY FIELD32(0x00008000) | |
717 | #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) | |
718 | ||
719 | /* | |
720 | * RFCSR: RF serial control register. | |
721 | * VALUE: Register value + id to program into rf/if. | |
722 | * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). | |
723 | * IF_SELECT: Chip to program: 0: rf, 1: if. | |
724 | * PLL_LD: Rf pll_ld status. | |
725 | * BUSY: 1: asic is busy execute rf programming. | |
726 | */ | |
727 | #define RFCSR 0x00f4 | |
728 | #define RFCSR_VALUE FIELD32(0x00ffffff) | |
729 | #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) | |
730 | #define RFCSR_IF_SELECT FIELD32(0x20000000) | |
731 | #define RFCSR_PLL_LD FIELD32(0x40000000) | |
732 | #define RFCSR_BUSY FIELD32(0x80000000) | |
733 | ||
734 | /* | |
735 | * LEDCSR: LED control register. | |
736 | * ON_PERIOD: On period, default 70ms. | |
737 | * OFF_PERIOD: Off period, default 30ms. | |
738 | * LINK: 0: linkoff, 1: linkup. | |
739 | * ACTIVITY: 0: idle, 1: active. | |
740 | * LINK_POLARITY: 0: active low, 1: active high. | |
741 | * ACTIVITY_POLARITY: 0: active low, 1: active high. | |
742 | * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF. | |
743 | */ | |
744 | #define LEDCSR 0x00f8 | |
745 | #define LEDCSR_ON_PERIOD FIELD32(0x000000ff) | |
746 | #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) | |
747 | #define LEDCSR_LINK FIELD32(0x00010000) | |
748 | #define LEDCSR_ACTIVITY FIELD32(0x00020000) | |
749 | #define LEDCSR_LINK_POLARITY FIELD32(0x00040000) | |
750 | #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000) | |
751 | #define LEDCSR_LED_DEFAULT FIELD32(0x00100000) | |
752 | ||
753 | /* | |
84263b0c | 754 | * SECCSR3: AES control register. |
95ea3627 ID |
755 | */ |
756 | #define SECCSR3 0x00fc | |
757 | ||
758 | /* | |
759 | * ASIC pointer information. | |
760 | * RXPTR: Current RX ring address. | |
761 | * TXPTR: Current Tx ring address. | |
762 | * PRIPTR: Current Priority ring address. | |
763 | * ATIMPTR: Current ATIM ring address. | |
764 | */ | |
765 | #define RXPTR 0x0100 | |
766 | #define TXPTR 0x0104 | |
767 | #define PRIPTR 0x0108 | |
768 | #define ATIMPTR 0x010c | |
769 | ||
770 | /* | |
771 | * TXACKCSR0: TX ACK timeout. | |
772 | */ | |
773 | #define TXACKCSR0 0x0110 | |
774 | ||
775 | /* | |
776 | * ACK timeout count registers. | |
777 | * ACKCNT0: TX ACK timeout count. | |
778 | * ACKCNT1: RX ACK timeout count. | |
779 | */ | |
780 | #define ACKCNT0 0x0114 | |
781 | #define ACKCNT1 0x0118 | |
782 | ||
783 | /* | |
784 | * GPIO and others. | |
785 | */ | |
786 | ||
787 | /* | |
788 | * GPIOCSR: GPIO control register. | |
789 | */ | |
790 | #define GPIOCSR 0x0120 | |
791 | #define GPIOCSR_BIT0 FIELD32(0x00000001) | |
792 | #define GPIOCSR_BIT1 FIELD32(0x00000002) | |
793 | #define GPIOCSR_BIT2 FIELD32(0x00000004) | |
794 | #define GPIOCSR_BIT3 FIELD32(0x00000008) | |
795 | #define GPIOCSR_BIT4 FIELD32(0x00000010) | |
796 | #define GPIOCSR_BIT5 FIELD32(0x00000020) | |
797 | #define GPIOCSR_BIT6 FIELD32(0x00000040) | |
798 | #define GPIOCSR_BIT7 FIELD32(0x00000080) | |
799 | #define GPIOCSR_DIR0 FIELD32(0x00000100) | |
800 | #define GPIOCSR_DIR1 FIELD32(0x00000200) | |
801 | #define GPIOCSR_DIR2 FIELD32(0x00000400) | |
802 | #define GPIOCSR_DIR3 FIELD32(0x00000800) | |
803 | #define GPIOCSR_DIR4 FIELD32(0x00001000) | |
804 | #define GPIOCSR_DIR5 FIELD32(0x00002000) | |
805 | #define GPIOCSR_DIR6 FIELD32(0x00004000) | |
806 | #define GPIOCSR_DIR7 FIELD32(0x00008000) | |
807 | ||
808 | /* | |
809 | * FIFO pointer registers. | |
810 | * FIFOCSR0: TX FIFO pointer. | |
811 | * FIFOCSR1: RX FIFO pointer. | |
812 | */ | |
813 | #define FIFOCSR0 0x0128 | |
814 | #define FIFOCSR1 0x012c | |
815 | ||
816 | /* | |
817 | * BCNCSR1: Tx BEACON offset time control register. | |
818 | * PRELOAD: Beacon timer offset in units of usec. | |
819 | * BEACON_CWMIN: 2^CwMin. | |
820 | */ | |
821 | #define BCNCSR1 0x0130 | |
822 | #define BCNCSR1_PRELOAD FIELD32(0x0000ffff) | |
823 | #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000) | |
824 | ||
825 | /* | |
826 | * MACCSR2: TX_PE to RX_PE turn-around time control register | |
827 | * DELAY: RX_PE low width, in units of pci clock cycle. | |
828 | */ | |
829 | #define MACCSR2 0x0134 | |
830 | #define MACCSR2_DELAY FIELD32(0x000000ff) | |
831 | ||
832 | /* | |
833 | * TESTCSR: TEST mode selection register. | |
834 | */ | |
835 | #define TESTCSR 0x0138 | |
836 | ||
837 | /* | |
838 | * ARCSR2: 1 Mbps ACK/CTS PLCP. | |
839 | */ | |
840 | #define ARCSR2 0x013c | |
841 | #define ARCSR2_SIGNAL FIELD32(0x000000ff) | |
842 | #define ARCSR2_SERVICE FIELD32(0x0000ff00) | |
843 | #define ARCSR2_LENGTH FIELD32(0xffff0000) | |
844 | ||
845 | /* | |
846 | * ARCSR3: 2 Mbps ACK/CTS PLCP. | |
847 | */ | |
848 | #define ARCSR3 0x0140 | |
849 | #define ARCSR3_SIGNAL FIELD32(0x000000ff) | |
850 | #define ARCSR3_SERVICE FIELD32(0x0000ff00) | |
851 | #define ARCSR3_LENGTH FIELD32(0xffff0000) | |
852 | ||
853 | /* | |
854 | * ARCSR4: 5.5 Mbps ACK/CTS PLCP. | |
855 | */ | |
856 | #define ARCSR4 0x0144 | |
857 | #define ARCSR4_SIGNAL FIELD32(0x000000ff) | |
858 | #define ARCSR4_SERVICE FIELD32(0x0000ff00) | |
859 | #define ARCSR4_LENGTH FIELD32(0xffff0000) | |
860 | ||
861 | /* | |
862 | * ARCSR5: 11 Mbps ACK/CTS PLCP. | |
863 | */ | |
864 | #define ARCSR5 0x0148 | |
865 | #define ARCSR5_SIGNAL FIELD32(0x000000ff) | |
866 | #define ARCSR5_SERVICE FIELD32(0x0000ff00) | |
867 | #define ARCSR5_LENGTH FIELD32(0xffff0000) | |
868 | ||
869 | /* | |
870 | * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps. | |
871 | */ | |
872 | #define ARTCSR0 0x014c | |
873 | #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff) | |
874 | #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00) | |
875 | #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000) | |
876 | #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000) | |
877 | ||
878 | ||
879 | /* | |
880 | * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. | |
881 | */ | |
882 | #define ARTCSR1 0x0150 | |
883 | #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff) | |
884 | #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00) | |
885 | #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000) | |
886 | #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000) | |
887 | ||
888 | /* | |
889 | * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. | |
890 | */ | |
891 | #define ARTCSR2 0x0154 | |
892 | #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff) | |
893 | #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00) | |
894 | #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000) | |
895 | #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000) | |
896 | ||
897 | /* | |
84263b0c | 898 | * SECCSR1: WEP control register. |
95ea3627 ID |
899 | * KICK_ENCRYPT: Kick encryption engine, self-clear. |
900 | * ONE_SHOT: 0: ring mode, 1: One shot only mode. | |
901 | * DESC_ADDRESS: Descriptor physical address of frame. | |
902 | */ | |
903 | #define SECCSR1 0x0158 | |
904 | #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001) | |
905 | #define SECCSR1_ONE_SHOT FIELD32(0x00000002) | |
906 | #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc) | |
907 | ||
908 | /* | |
909 | * BBPCSR1: BBP TX configuration. | |
910 | */ | |
911 | #define BBPCSR1 0x015c | |
912 | #define BBPCSR1_CCK FIELD32(0x00000003) | |
913 | #define BBPCSR1_CCK_FLIP FIELD32(0x00000004) | |
914 | #define BBPCSR1_OFDM FIELD32(0x00030000) | |
915 | #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000) | |
916 | ||
917 | /* | |
918 | * Dual band configuration registers. | |
919 | * DBANDCSR0: Dual band configuration register 0. | |
920 | * DBANDCSR1: Dual band configuration register 1. | |
921 | */ | |
922 | #define DBANDCSR0 0x0160 | |
923 | #define DBANDCSR1 0x0164 | |
924 | ||
925 | /* | |
926 | * BBPPCSR: BBP Pin control register. | |
927 | */ | |
928 | #define BBPPCSR 0x0168 | |
929 | ||
930 | /* | |
931 | * MAC special debug mode selection registers. | |
932 | * DBGSEL0: MAC special debug mode selection register 0. | |
933 | * DBGSEL1: MAC special debug mode selection register 1. | |
934 | */ | |
935 | #define DBGSEL0 0x016c | |
936 | #define DBGSEL1 0x0170 | |
937 | ||
938 | /* | |
939 | * BISTCSR: BBP BIST register. | |
940 | */ | |
941 | #define BISTCSR 0x0174 | |
942 | ||
943 | /* | |
944 | * Multicast filter registers. | |
945 | * MCAST0: Multicast filter register 0. | |
946 | * MCAST1: Multicast filter register 1. | |
947 | */ | |
948 | #define MCAST0 0x0178 | |
949 | #define MCAST1 0x017c | |
950 | ||
951 | /* | |
952 | * UART registers. | |
953 | * UARTCSR0: UART1 TX register. | |
954 | * UARTCSR1: UART1 RX register. | |
955 | * UARTCSR3: UART1 frame control register. | |
956 | * UARTCSR4: UART1 buffer control register. | |
957 | * UART2CSR0: UART2 TX register. | |
958 | * UART2CSR1: UART2 RX register. | |
959 | * UART2CSR3: UART2 frame control register. | |
960 | * UART2CSR4: UART2 buffer control register. | |
961 | */ | |
962 | #define UARTCSR0 0x0180 | |
963 | #define UARTCSR1 0x0184 | |
964 | #define UARTCSR3 0x0188 | |
965 | #define UARTCSR4 0x018c | |
966 | #define UART2CSR0 0x0190 | |
967 | #define UART2CSR1 0x0194 | |
968 | #define UART2CSR3 0x0198 | |
969 | #define UART2CSR4 0x019c | |
970 | ||
971 | /* | |
972 | * BBP registers. | |
973 | * The wordsize of the BBP is 8 bits. | |
974 | */ | |
975 | ||
976 | /* | |
977 | * R2: TX antenna control | |
978 | */ | |
979 | #define BBP_R2_TX_ANTENNA FIELD8(0x03) | |
980 | #define BBP_R2_TX_IQ_FLIP FIELD8(0x04) | |
981 | ||
982 | /* | |
983 | * R14: RX antenna control | |
984 | */ | |
985 | #define BBP_R14_RX_ANTENNA FIELD8(0x03) | |
986 | #define BBP_R14_RX_IQ_FLIP FIELD8(0x04) | |
987 | ||
988 | /* | |
989 | * BBP_R70 | |
990 | */ | |
991 | #define BBP_R70_JAPAN_FILTER FIELD8(0x08) | |
992 | ||
993 | /* | |
994 | * RF registers | |
995 | */ | |
996 | ||
997 | /* | |
998 | * RF 1 | |
999 | */ | |
1000 | #define RF1_TUNER FIELD32(0x00020000) | |
1001 | ||
1002 | /* | |
1003 | * RF 3 | |
1004 | */ | |
1005 | #define RF3_TUNER FIELD32(0x00000100) | |
1006 | #define RF3_TXPOWER FIELD32(0x00003e00) | |
1007 | ||
1008 | /* | |
1009 | * EEPROM content. | |
1010 | * The wordsize of the EEPROM is 16 bits. | |
1011 | */ | |
1012 | ||
1013 | /* | |
1014 | * HW MAC address. | |
1015 | */ | |
1016 | #define EEPROM_MAC_ADDR_0 0x0002 | |
1017 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
1018 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
1019 | #define EEPROM_MAC_ADDR1 0x0003 | |
1020 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
1021 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
1022 | #define EEPROM_MAC_ADDR_2 0x0004 | |
1023 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
1024 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
1025 | ||
1026 | /* | |
1027 | * EEPROM antenna. | |
1028 | * ANTENNA_NUM: Number of antenna's. | |
1029 | * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
1030 | * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
1031 | * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. | |
1032 | * DYN_TXAGC: Dynamic TX AGC control. | |
1033 | * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. | |
1034 | * RF_TYPE: Rf_type of this adapter. | |
1035 | */ | |
1036 | #define EEPROM_ANTENNA 0x10 | |
1037 | #define EEPROM_ANTENNA_NUM FIELD16(0x0003) | |
1038 | #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) | |
1039 | #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) | |
1040 | #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0) | |
1041 | #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) | |
1042 | #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) | |
1043 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) | |
1044 | ||
1045 | /* | |
1046 | * EEPROM NIC config. | |
1047 | * CARDBUS_ACCEL: 0: enable, 1: disable. | |
1048 | * DYN_BBP_TUNE: 0: enable, 1: disable. | |
1049 | * CCK_TX_POWER: CCK TX power compensation. | |
1050 | */ | |
1051 | #define EEPROM_NIC 0x11 | |
1052 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001) | |
1053 | #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002) | |
1054 | #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c) | |
1055 | ||
1056 | /* | |
1057 | * EEPROM geography. | |
1058 | * GEO: Default geography setting for device. | |
1059 | */ | |
1060 | #define EEPROM_GEOGRAPHY 0x12 | |
1061 | #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00) | |
1062 | ||
1063 | /* | |
1064 | * EEPROM BBP. | |
1065 | */ | |
1066 | #define EEPROM_BBP_START 0x13 | |
1067 | #define EEPROM_BBP_SIZE 16 | |
1068 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
1069 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
1070 | ||
1071 | /* | |
1072 | * EEPROM TXPOWER | |
1073 | */ | |
1074 | #define EEPROM_TXPOWER_START 0x23 | |
1075 | #define EEPROM_TXPOWER_SIZE 7 | |
1076 | #define EEPROM_TXPOWER_1 FIELD16(0x00ff) | |
1077 | #define EEPROM_TXPOWER_2 FIELD16(0xff00) | |
1078 | ||
1079 | /* | |
1080 | * RSSI <-> dBm offset calibration | |
1081 | */ | |
1082 | #define EEPROM_CALIBRATE_OFFSET 0x3e | |
1083 | #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff) | |
1084 | ||
1085 | /* | |
1086 | * DMA descriptor defines. | |
1087 | */ | |
4bd7c452 ID |
1088 | #define TXD_DESC_SIZE ( 11 * sizeof(__le32) ) |
1089 | #define RXD_DESC_SIZE ( 11 * sizeof(__le32) ) | |
95ea3627 ID |
1090 | |
1091 | /* | |
1092 | * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. | |
1093 | */ | |
1094 | ||
1095 | /* | |
1096 | * Word0 | |
1097 | */ | |
1098 | #define TXD_W0_OWNER_NIC FIELD32(0x00000001) | |
1099 | #define TXD_W0_VALID FIELD32(0x00000002) | |
1100 | #define TXD_W0_RESULT FIELD32(0x0000001c) | |
1101 | #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) | |
1102 | #define TXD_W0_MORE_FRAG FIELD32(0x00000100) | |
1103 | #define TXD_W0_ACK FIELD32(0x00000200) | |
1104 | #define TXD_W0_TIMESTAMP FIELD32(0x00000400) | |
1105 | #define TXD_W0_OFDM FIELD32(0x00000800) | |
1106 | #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000) | |
1107 | #define TXD_W0_IFS FIELD32(0x00006000) | |
1108 | #define TXD_W0_RETRY_MODE FIELD32(0x00008000) | |
1109 | #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
1110 | #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
1111 | ||
1112 | /* | |
1113 | * Word1 | |
1114 | */ | |
1115 | #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
1116 | ||
1117 | /* | |
1118 | * Word2 | |
1119 | */ | |
1120 | #define TXD_W2_IV_OFFSET FIELD32(0x0000003f) | |
1121 | #define TXD_W2_AIFS FIELD32(0x000000c0) | |
1122 | #define TXD_W2_CWMIN FIELD32(0x00000f00) | |
1123 | #define TXD_W2_CWMAX FIELD32(0x0000f000) | |
1124 | ||
1125 | /* | |
1126 | * Word3: PLCP information | |
1127 | */ | |
1128 | #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) | |
1129 | #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00) | |
1130 | #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000) | |
1131 | #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000) | |
1132 | ||
1133 | /* | |
1134 | * Word4 | |
1135 | */ | |
1136 | #define TXD_W4_IV FIELD32(0xffffffff) | |
1137 | ||
1138 | /* | |
1139 | * Word5 | |
1140 | */ | |
1141 | #define TXD_W5_EIV FIELD32(0xffffffff) | |
1142 | ||
1143 | /* | |
1144 | * Word6-9: Key | |
1145 | */ | |
1146 | #define TXD_W6_KEY FIELD32(0xffffffff) | |
1147 | #define TXD_W7_KEY FIELD32(0xffffffff) | |
1148 | #define TXD_W8_KEY FIELD32(0xffffffff) | |
1149 | #define TXD_W9_KEY FIELD32(0xffffffff) | |
1150 | ||
1151 | /* | |
1152 | * Word10 | |
1153 | */ | |
1154 | #define TXD_W10_RTS FIELD32(0x00000001) | |
1155 | #define TXD_W10_TX_RATE FIELD32(0x000000fe) | |
1156 | ||
1157 | /* | |
1158 | * RX descriptor format for RX Ring. | |
1159 | */ | |
1160 | ||
1161 | /* | |
1162 | * Word0 | |
1163 | */ | |
1164 | #define RXD_W0_OWNER_NIC FIELD32(0x00000001) | |
1165 | #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) | |
1166 | #define RXD_W0_MULTICAST FIELD32(0x00000004) | |
1167 | #define RXD_W0_BROADCAST FIELD32(0x00000008) | |
1168 | #define RXD_W0_MY_BSS FIELD32(0x00000010) | |
1169 | #define RXD_W0_CRC_ERROR FIELD32(0x00000020) | |
1170 | #define RXD_W0_OFDM FIELD32(0x00000040) | |
1171 | #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) | |
1172 | #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100) | |
1173 | #define RXD_W0_ICV_ERROR FIELD32(0x00000200) | |
1174 | #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00) | |
1175 | #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
1176 | #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
1177 | ||
1178 | /* | |
1179 | * Word1 | |
1180 | */ | |
1181 | #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) | |
1182 | ||
1183 | /* | |
1184 | * Word2 | |
1185 | */ | |
1186 | #define RXD_W2_SIGNAL FIELD32(0x000000ff) | |
1187 | #define RXD_W2_RSSI FIELD32(0x0000ff00) | |
1188 | #define RXD_W2_TA FIELD32(0xffff0000) | |
1189 | ||
1190 | /* | |
1191 | * Word3 | |
1192 | */ | |
1193 | #define RXD_W3_TA FIELD32(0xffffffff) | |
1194 | ||
1195 | /* | |
1196 | * Word4 | |
1197 | */ | |
1198 | #define RXD_W4_IV FIELD32(0xffffffff) | |
1199 | ||
1200 | /* | |
1201 | * Word5 | |
1202 | */ | |
1203 | #define RXD_W5_EIV FIELD32(0xffffffff) | |
1204 | ||
1205 | /* | |
1206 | * Word6-9: Key | |
1207 | */ | |
1208 | #define RXD_W6_KEY FIELD32(0xffffffff) | |
1209 | #define RXD_W7_KEY FIELD32(0xffffffff) | |
1210 | #define RXD_W8_KEY FIELD32(0xffffffff) | |
1211 | #define RXD_W9_KEY FIELD32(0xffffffff) | |
1212 | ||
1213 | /* | |
1214 | * Word10 | |
1215 | */ | |
1216 | #define RXD_W10_DROP FIELD32(0x00000001) | |
1217 | ||
1218 | /* | |
de99ff82 ID |
1219 | * Macro's for converting txpower from EEPROM to mac80211 value |
1220 | * and from mac80211 value to register value. | |
95ea3627 ID |
1221 | */ |
1222 | #define MIN_TXPOWER 0 | |
1223 | #define MAX_TXPOWER 31 | |
1224 | #define DEFAULT_TXPOWER 24 | |
1225 | ||
1226 | #define TXPOWER_FROM_DEV(__txpower) \ | |
1227 | ({ \ | |
1228 | ((__txpower) > MAX_TXPOWER) ? \ | |
1229 | DEFAULT_TXPOWER : (__txpower); \ | |
1230 | }) | |
1231 | ||
1232 | #define TXPOWER_TO_DEV(__txpower) \ | |
1233 | ({ \ | |
1234 | ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \ | |
1235 | (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \ | |
1236 | (__txpower)); \ | |
1237 | }) | |
1238 | ||
1239 | #endif /* RT2500PCI_H */ |