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rt2x00: Properly reserve room for descriptors in skbs.
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500usb.c
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95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500usb
23 Abstract: rt2500usb device specific routines.
24 Supported chipsets: RT2570.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
95ea3627
ID		 33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2500usb.h"
38
dddfb478
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
f1dd2b23 42static int modparam_nohwcrypt = 0;
dddfb478
ID		 43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2500usb_register_read and rt2500usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * If the csr_mutex is already held then the _lock variants must
3d82346c 59 * be used instead.
95ea3627 60 */
0e14f6d3 61static inline void rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 62 const unsigned int offset,
63 u16 *value)
64{
65 __le16 reg;
66 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 68 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 69 *value = le16_to_cpu(reg);
70}
71
3d82346c
AB		 72static inline void rt2500usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 u16 *value)
75{
76 __le16 reg;
77 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 79 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 80 *value = le16_to_cpu(reg);
81}
82
0e14f6d3 83static inline void rt2500usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset,
85 void *value, const u16 length)
86{
95ea3627
ID		 87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
88 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 89 value, length,
90 REGISTER_TIMEOUT16(length));
95ea3627
ID		 91}
92
0e14f6d3 93static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int offset,
95 u16 value)
96{
97 __le16 reg = cpu_to_le16(value);
98 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
99 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 100 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 101}
102
3d82346c
AB		 103static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
104 const unsigned int offset,
105 u16 value)
106{
107 __le16 reg = cpu_to_le16(value);
108 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
109 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 110 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 111}
112
0e14f6d3 113static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int offset,
115 void *value, const u16 length)
116{
95ea3627
ID		 117 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
118 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 119 value, length,
120 REGISTER_TIMEOUT16(length));
95ea3627
ID		 121}
122
c9c3b1a5
ID		 123static int rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
124 const unsigned int offset,
125 struct rt2x00_field16 field,
126 u16 *reg)
95ea3627 127{
95ea3627
ID		 128 unsigned int i;
129
130 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
c9c3b1a5
ID		 131 rt2500usb_register_read_lock(rt2x00dev, offset, reg);
132 if (!rt2x00_get_field16(*reg, field))
133 return 1;
95ea3627
ID		 134 udelay(REGISTER_BUSY_DELAY);
135 }
136
c9c3b1a5
ID		 137 ERROR(rt2x00dev, "Indirect register access failed: "
138 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
139 *reg = ~0;
140
141 return 0;
95ea3627
ID		 142}
143
c9c3b1a5
ID		 144#define WAIT_FOR_BBP(__dev, __reg) \
145 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
146#define WAIT_FOR_RF(__dev, __reg) \
147 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
148
0e14f6d3 149static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 150 const unsigned int word, const u8 value)
151{
152 u16 reg;
153
8ff48a8b 154 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 155
95ea3627 156 /*
c9c3b1a5
ID		 157 * Wait until the BBP becomes available, afterwards we
158 * can safely write the new data into the register.
95ea3627 159 */
c9c3b1a5
ID		 160 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
161 reg = 0;
162 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
163 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
164 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
3d82346c 165
c9c3b1a5
ID		 166 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
167 }
99ade259 168
8ff48a8b 169 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 170}
171
0e14f6d3 172static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 173 const unsigned int word, u8 *value)
174{
175 u16 reg;
176
8ff48a8b 177 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 178
95ea3627 179 /*
c9c3b1a5
ID		 180 * Wait until the BBP becomes available, afterwards we
181 * can safely write the read request into the register.
182 * After the data has been written, we wait until hardware
183 * returns the correct value, if at any time the register
184 * doesn't become available in time, reg will be 0xffffffff
185 * which means we return 0xff to the caller.
95ea3627 186 */
c9c3b1a5
ID		 187 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
188 reg = 0;
189 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
190 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
95ea3627 191
c9c3b1a5 192 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
95ea3627 193
c9c3b1a5
ID		 194 if (WAIT_FOR_BBP(rt2x00dev, &reg))
195 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg);
196 }
95ea3627 197
95ea3627 198 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
3d82346c 199
8ff48a8b 200 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 201}
202
0e14f6d3 203static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 204 const unsigned int word, const u32 value)
205{
206 u16 reg;
95ea3627 207
8ff48a8b 208 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 209
c9c3b1a5
ID		 210 /*
211 * Wait until the RF becomes available, afterwards we
212 * can safely write the new data into the register.
213 */
214 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
215 reg = 0;
216 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
217 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
218
219 reg = 0;
220 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
221 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
222 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
223 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
224
225 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg);
226 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 227 }
228
8ff48a8b 229 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
743b97ca
ID		 233static void _rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
234 const unsigned int offset,
235 u32 *value)
95ea3627 236{
743b97ca 237 rt2500usb_register_read(rt2x00dev, offset, (u16 *)value);
95ea3627
ID		 238}
239
743b97ca
ID		 240static void _rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
241 const unsigned int offset,
242 u32 value)
95ea3627 243{
743b97ca 244 rt2500usb_register_write(rt2x00dev, offset, value);
95ea3627
ID		 245}
246
247static const struct rt2x00debug rt2500usb_rt2x00debug = {
248 .owner = THIS_MODULE,
249 .csr = {
743b97ca
ID		 250 .read = _rt2500usb_register_read,
251 .write = _rt2500usb_register_write,
252 .flags = RT2X00DEBUGFS_OFFSET,
253 .word_base = CSR_REG_BASE,
95ea3627
ID		 254 .word_size = sizeof(u16),
255 .word_count = CSR_REG_SIZE / sizeof(u16),
256 },
257 .eeprom = {
258 .read = rt2x00_eeprom_read,
259 .write = rt2x00_eeprom_write,
743b97ca 260 .word_base = EEPROM_BASE,
95ea3627
ID		 261 .word_size = sizeof(u16),
262 .word_count = EEPROM_SIZE / sizeof(u16),
263 },
264 .bbp = {
265 .read = rt2500usb_bbp_read,
266 .write = rt2500usb_bbp_write,
743b97ca 267 .word_base = BBP_BASE,
95ea3627
ID		 268 .word_size = sizeof(u8),
269 .word_count = BBP_SIZE / sizeof(u8),
270 },
271 .rf = {
272 .read = rt2x00_rf_read,
273 .write = rt2500usb_rf_write,
743b97ca 274 .word_base = RF_BASE,
95ea3627
ID		 275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
7396faf4
ID		 281static int rt2500usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282{
283 u16 reg;
284
285 rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg);
286 return rt2x00_get_field32(reg, MAC_CSR19_BIT7);
287}
7396faf4 288
771fd565 289#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 290static void rt2500usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 291 enum led_brightness brightness)
292{
293 struct rt2x00_led *led =
294 container_of(led_cdev, struct rt2x00_led, led_dev);
295 unsigned int enabled = brightness != LED_OFF;
a2e1d52a 296 u16 reg;
a9450b70 297
a2e1d52a 298 rt2500usb_register_read(led->rt2x00dev, MAC_CSR20, &reg);
47b10cd1 299
a2e1d52a
ID		 300 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
301 rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled);
302 else if (led->type == LED_TYPE_ACTIVITY)
303 rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled);
304
305 rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg);
306}
307
308static int rt2500usb_blink_set(struct led_classdev *led_cdev,
309 unsigned long *delay_on,
310 unsigned long *delay_off)
311{
312 struct rt2x00_led *led =
313 container_of(led_cdev, struct rt2x00_led, led_dev);
314 u16 reg;
315
316 rt2500usb_register_read(led->rt2x00dev, MAC_CSR21, &reg);
317 rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on);
318 rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off);
319 rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg);
a9450b70 320
a2e1d52a 321 return 0;
a9450b70 322}
475433be
ID		 323
324static void rt2500usb_init_led(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_led *led,
326 enum led_type type)
327{
328 led->rt2x00dev = rt2x00dev;
329 led->type = type;
330 led->led_dev.brightness_set = rt2500usb_brightness_set;
331 led->led_dev.blink_set = rt2500usb_blink_set;
332 led->flags = LED_INITIALIZED;
333}
771fd565 334#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 335
95ea3627
ID		 336/*
337 * Configuration handlers.
338 */
dddfb478
ID		 339
340/*
341 * rt2500usb does not differentiate between shared and pairwise
342 * keys, so we should use the same function for both key types.
343 */
344static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
345 struct rt2x00lib_crypto *crypto,
346 struct ieee80211_key_conf *key)
347{
348 int timeout;
349 u32 mask;
350 u16 reg;
351
352 if (crypto->cmd == SET_KEY) {
353 /*
354 * Pairwise key will always be entry 0, but this
355 * could collide with a shared key on the same
356 * position...
357 */
358 mask = TXRX_CSR0_KEY_ID.bit_mask;
359
360 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
361 reg &= mask;
362
363 if (reg && reg == mask)
364 return -ENOSPC;
365
366 reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
367
368 key->hw_key_idx += reg ? ffz(reg) : 0;
369
370 /*
371 * The encryption key doesn't fit within the CSR cache,
3ad2f3fb 372 * this means we should allocate it separately and use
dddfb478
ID		 373 * rt2x00usb_vendor_request() to send the key to the hardware.
374 */
375 reg = KEY_ENTRY(key->hw_key_idx);
376 timeout = REGISTER_TIMEOUT32(sizeof(crypto->key));
377 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
378 USB_VENDOR_REQUEST_OUT, reg,
379 crypto->key,
380 sizeof(crypto->key),
381 timeout);
382
383 /*
384 * The driver does not support the IV/EIV generation
f3d340c1 385 * in hardware. However it demands the data to be provided
3ad2f3fb 386 * both separately as well as inside the frame.
f3d340c1
ID		 387 * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib
388 * to ensure rt2x00lib will not strip the data from the
389 * frame after the copy, now we must tell mac80211
dddfb478
ID		 390 * to generate the IV/EIV data.
391 */
392 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
393 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
394 }
395
396 /*
397 * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
398 * a particular key is valid.
399 */
400 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
401 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
402 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
403
404 mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
405 if (crypto->cmd == SET_KEY)
406 mask |= 1 << key->hw_key_idx;
407 else if (crypto->cmd == DISABLE_KEY)
408 mask &= ~(1 << key->hw_key_idx);
409 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
410 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
411
412 return 0;
413}
414
3a643d24
ID		 415static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
416 const unsigned int filter_flags)
417{
418 u16 reg;
419
420 /*
421 * Start configuration steps.
422 * Note that the version error will always be dropped
423 * and broadcast frames will always be accepted since
424 * there is no filter for it at this time.
425 */
426 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
427 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
428 !(filter_flags & FIF_FCSFAIL));
429 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
430 !(filter_flags & FIF_PLCPFAIL));
431 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
432 !(filter_flags & FIF_CONTROL));
433 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
434 !(filter_flags & FIF_PROMISC_IN_BSS));
435 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
e0b005fa
ID		 436 !(filter_flags & FIF_PROMISC_IN_BSS) &&
437 !rt2x00dev->intf_ap_count);
3a643d24
ID		 438 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
439 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
440 !(filter_flags & FIF_ALLMULTI));
441 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
442 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
443}
444
6bb40dd1
ID		 445static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
446 struct rt2x00_intf *intf,
447 struct rt2x00intf_conf *conf,
448 const unsigned int flags)
95ea3627 449{
6bb40dd1 450 unsigned int bcn_preload;
95ea3627
ID		 451 u16 reg;
452
6bb40dd1 453 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 454 /*
455 * Enable beacon config
456 */
bad13639 457 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 458 rt2500usb_register_read(rt2x00dev, TXRX_CSR20, &reg);
459 rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6);
460 rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW,
05c914fe 461 2 * (conf->type != NL80211_IFTYPE_STATION));
6bb40dd1 462 rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
95ea3627 463
6bb40dd1
ID		 464 /*
465 * Enable synchronisation.
466 */
467 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
468 rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
469 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
470
471 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
fd3c91c5 472 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
6bb40dd1 473 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
fd3c91c5 474 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
6bb40dd1
ID		 475 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
476 }
95ea3627 477
6bb40dd1
ID		 478 if (flags & CONFIG_UPDATE_MAC)
479 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, conf->mac,
480 (3 * sizeof(__le16)));
481
482 if (flags & CONFIG_UPDATE_BSSID)
483 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, conf->bssid,
484 (3 * sizeof(__le16)));
95ea3627
ID		 485}
486
3a643d24
ID		 487static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
488 struct rt2x00lib_erp *erp)
95ea3627 489{
95ea3627 490 u16 reg;
95ea3627 491
95ea3627 492 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);
4f5af6eb 493 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
72810379 494 !!erp->short_preamble);
95ea3627 495 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
95ea3627 496
e4ea1c40 497 rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates);
95ea3627 498
8a566afe
ID		 499 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
500 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4);
501 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
502
e4ea1c40
ID		 503 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
504 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
505 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
95ea3627
ID		 506}
507
e4ea1c40
ID		 508static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
509 struct antenna_setup *ant)
95ea3627
ID		 510{
511 u8 r2;
512 u8 r14;
513 u16 csr5;
514 u16 csr6;
515
a4fe07d9
ID		 516 /*
517 * We should never come here because rt2x00lib is supposed
518 * to catch this and send us the correct antenna explicitely.
519 */
520 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
521 ant->tx == ANTENNA_SW_DIVERSITY);
522
95ea3627
ID		 523 rt2500usb_bbp_read(rt2x00dev, 2, &r2);
524 rt2500usb_bbp_read(rt2x00dev, 14, &r14);
525 rt2500usb_register_read(rt2x00dev, PHY_CSR5, &csr5);
526 rt2500usb_register_read(rt2x00dev, PHY_CSR6, &csr6);
527
528 /*
529 * Configure the TX antenna.
530 */
addc81bd 531 switch (ant->tx) {
95ea3627
ID		 532 case ANTENNA_HW_DIVERSITY:
533 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
534 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
535 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
536 break;
537 case ANTENNA_A:
538 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
539 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
540 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
541 break;
542 case ANTENNA_B:
a4fe07d9 543 default:
95ea3627
ID		 544 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
545 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
546 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
547 break;
548 }
549
550 /*
551 * Configure the RX antenna.
552 */
addc81bd 553 switch (ant->rx) {
95ea3627
ID		 554 case ANTENNA_HW_DIVERSITY:
555 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
556 break;
557 case ANTENNA_A:
558 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
559 break;
560 case ANTENNA_B:
a4fe07d9 561 default:
95ea3627
ID		 562 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
563 break;
564 }
565
566 /*
567 * RT2525E and RT5222 need to flip TX I/Q
568 */
5122d898 569 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 570 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
571 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
572 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
573
574 /*
575 * RT2525E does not need RX I/Q Flip.
576 */
5122d898 577 if (rt2x00_rf(rt2x00dev, RF2525E))
95ea3627
ID		 578 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
579 } else {
580 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
581 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
582 }
583
584 rt2500usb_bbp_write(rt2x00dev, 2, r2);
585 rt2500usb_bbp_write(rt2x00dev, 14, r14);
586 rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
587 rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
588}
589
e4ea1c40
ID		 590static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
591 struct rf_channel *rf, const int txpower)
592{
593 /*
594 * Set TXpower.
595 */
596 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
597
598 /*
599 * For RT2525E we should first set the channel to half band higher.
600 */
5122d898 601 if (rt2x00_rf(rt2x00dev, RF2525E)) {
e4ea1c40
ID		 602 static const u32 vals[] = {
603 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
604 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
605 0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
606 0x00000902, 0x00000906
607 };
608
609 rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
610 if (rf->rf4)
611 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
612 }
613
614 rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
615 rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
616 rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
617 if (rf->rf4)
618 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
619}
620
621static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
622 const int txpower)
623{
624 u32 rf3;
625
626 rt2x00_rf_read(rt2x00dev, 3, &rf3);
627 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
628 rt2500usb_rf_write(rt2x00dev, 3, rf3);
629}
630
7d7f19cc
ID		 631static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
632 struct rt2x00lib_conf *libconf)
633{
634 enum dev_state state =
635 (libconf->conf->flags & IEEE80211_CONF_PS) ?
636 STATE_SLEEP : STATE_AWAKE;
637 u16 reg;
638
639 if (state == STATE_SLEEP) {
640 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
641 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
6b347bff 642 rt2x00dev->beacon_int - 20);
7d7f19cc
ID		 643 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
644 libconf->conf->listen_interval - 1);
645
646 /* We must first disable autowake before it can be enabled */
647 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
648 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
649
650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
5731858d
GW		 652 } else {
653 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
654 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
655 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
7d7f19cc
ID		 656 }
657
658 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
659}
660
95ea3627 661static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 662 struct rt2x00lib_conf *libconf,
663 const unsigned int flags)
95ea3627 664{
e4ea1c40 665 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 666 rt2500usb_config_channel(rt2x00dev, &libconf->rf,
667 libconf->conf->power_level);
e4ea1c40
ID		 668 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
669 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 670 rt2500usb_config_txpower(rt2x00dev,
671 libconf->conf->power_level);
7d7f19cc
ID		 672 if (flags & IEEE80211_CONF_CHANGE_PS)
673 rt2500usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 674}
675
95ea3627
ID		 676/*
677 * Link tuning
678 */
ebcf26da
ID		 679static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev,
680 struct link_qual *qual)
95ea3627
ID		 681{
682 u16 reg;
683
684 /*
685 * Update FCS error count from register.
686 */
687 rt2500usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 688 qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 689
690 /*
691 * Update False CCA count from register.
692 */
693 rt2500usb_register_read(rt2x00dev, STA_CSR3, &reg);
ebcf26da 694 qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
95ea3627
ID		 695}
696
5352ff65
ID		 697static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
698 struct link_qual *qual)
95ea3627
ID		 699{
700 u16 eeprom;
701 u16 value;
702
703 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &eeprom);
704 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
705 rt2500usb_bbp_write(rt2x00dev, 24, value);
706
707 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &eeprom);
708 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
709 rt2500usb_bbp_write(rt2x00dev, 25, value);
710
711 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &eeprom);
712 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
713 rt2500usb_bbp_write(rt2x00dev, 61, value);
714
715 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &eeprom);
716 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
717 rt2500usb_bbp_write(rt2x00dev, 17, value);
718
5352ff65 719 qual->vgc_level = value;
95ea3627
ID		 720}
721
95ea3627
ID		 722/*
723 * Initialization functions.
724 */
725static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
726{
727 u16 reg;
728
729 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
730 USB_MODE_TEST, REGISTER_TIMEOUT);
731 rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
732 0x00f0, REGISTER_TIMEOUT);
733
734 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
735 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
736 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
737
738 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
739 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
740
741 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
742 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
743 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
744 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
745 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
746
747 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
748 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
749 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
750 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
751 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
752
753 rt2500usb_register_read(rt2x00dev, TXRX_CSR5, &reg);
754 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
755 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
756 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
757 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
758 rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
759
760 rt2500usb_register_read(rt2x00dev, TXRX_CSR6, &reg);
761 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
762 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
763 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
764 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
765 rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
766
767 rt2500usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
768 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
769 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
770 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
771 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
772 rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
773
774 rt2500usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
775 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
776 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
777 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
778 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
779 rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
780
1f909162
ID		 781 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
782 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
783 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0);
784 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
785 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
786 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
787
95ea3627
ID		 788 rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
789 rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
790
791 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
792 return -EBUSY;
793
794 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
795 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
796 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
797 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
798 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
799
5122d898 800 if (rt2x00_rev(rt2x00dev) >= RT2570_VERSION_C) {
95ea3627 801 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg);
ddc827f9 802 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
95ea3627 803 } else {
ddc827f9
ID		 804 reg = 0;
805 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1);
806 rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3);
95ea3627
ID		 807 }
808 rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
809
810 rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
811 rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
812 rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
813 rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
814
815 rt2500usb_register_read(rt2x00dev, MAC_CSR8, &reg);
816 rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
817 rt2x00dev->rx->data_size);
818 rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
819
820 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
821 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
dddfb478 822 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
95ea3627
ID		 823 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
824
825 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
826 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
827 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
828
829 rt2500usb_register_read(rt2x00dev, PHY_CSR4, &reg);
830 rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
831 rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
832
833 rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
834 rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
835 rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
836
837 return 0;
838}
839
2b08da3f 840static int rt2500usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 841{
842 unsigned int i;
95ea3627 843 u8 value;
95ea3627
ID		 844
845 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
846 rt2500usb_bbp_read(rt2x00dev, 0, &value);
847 if ((value != 0xff) && (value != 0x00))
2b08da3f 848 return 0;
95ea3627
ID		 849 udelay(REGISTER_BUSY_DELAY);
850 }
851
852 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
853 return -EACCES;
2b08da3f
ID		 854}
855
856static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
857{
858 unsigned int i;
859 u16 eeprom;
860 u8 value;
861 u8 reg_id;
862
863 if (unlikely(rt2500usb_wait_bbp_ready(rt2x00dev)))
864 return -EACCES;
95ea3627 865
95ea3627
ID		 866 rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
867 rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
868 rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
869 rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
870 rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
871 rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
872 rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
873 rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
874 rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
875 rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
876 rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
877 rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
878 rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
879 rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
880 rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
881 rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
882 rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
883 rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
884 rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
885 rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
886 rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
887 rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
888 rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
889 rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
890 rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
891 rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
892 rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
893 rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
894 rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
895 rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
896 rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
897
95ea3627
ID		 898 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
899 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
900
901 if (eeprom != 0xffff && eeprom != 0x0000) {
902 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
903 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 904 rt2500usb_bbp_write(rt2x00dev, reg_id, value);
905 }
906 }
95ea3627
ID		 907
908 return 0;
909}
910
911/*
912 * Device state switch handlers.
913 */
914static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
915 enum dev_state state)
916{
917 u16 reg;
918
919 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
920 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
2b08da3f
ID		 921 (state == STATE_RADIO_RX_OFF) ||
922 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 923 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
924}
925
926static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
927{
928 /*
929 * Initialize all registers.
930 */
2b08da3f
ID		 931 if (unlikely(rt2500usb_init_registers(rt2x00dev) ||
932 rt2500usb_init_bbp(rt2x00dev)))
95ea3627 933 return -EIO;
95ea3627 934
95ea3627
ID		 935 return 0;
936}
937
938static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
939{
95ea3627
ID		 940 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
941 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
942
943 /*
944 * Disable synchronisation.
945 */
946 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
947
948 rt2x00usb_disable_radio(rt2x00dev);
949}
950
951static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
952 enum dev_state state)
953{
954 u16 reg;
955 u16 reg2;
956 unsigned int i;
957 char put_to_sleep;
958 char bbp_state;
959 char rf_state;
960
961 put_to_sleep = (state != STATE_AWAKE);
962
963 reg = 0;
964 rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
965 rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
966 rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
967 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
968 rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
969 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
970
971 /*
972 * Device is not guaranteed to be in the requested state yet.
973 * We must wait until the register indicates that the
974 * device has entered the correct state.
975 */
976 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
977 rt2500usb_register_read(rt2x00dev, MAC_CSR17, &reg2);
978 bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
979 rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
980 if (bbp_state == state && rf_state == state)
981 return 0;
982 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
983 msleep(30);
984 }
985
95ea3627
ID		 986 return -EBUSY;
987}
988
989static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
990 enum dev_state state)
991{
992 int retval = 0;
993
994 switch (state) {
995 case STATE_RADIO_ON:
996 retval = rt2500usb_enable_radio(rt2x00dev);
997 break;
998 case STATE_RADIO_OFF:
999 rt2500usb_disable_radio(rt2x00dev);
1000 break;
1001 case STATE_RADIO_RX_ON:
61667d8d 1002 case STATE_RADIO_RX_ON_LINK:
95ea3627 1003 case STATE_RADIO_RX_OFF:
61667d8d 1004 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1005 rt2500usb_toggle_rx(rt2x00dev, state);
1006 break;
1007 case STATE_RADIO_IRQ_ON:
1008 case STATE_RADIO_IRQ_OFF:
1009 /* No support, but no error either */
95ea3627
ID		 1010 break;
1011 case STATE_DEEP_SLEEP:
1012 case STATE_SLEEP:
1013 case STATE_STANDBY:
1014 case STATE_AWAKE:
1015 retval = rt2500usb_set_state(rt2x00dev, state);
1016 break;
1017 default:
1018 retval = -ENOTSUPP;
1019 break;
1020 }
1021
2b08da3f
ID		 1022 if (unlikely(retval))
1023 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1024 state, retval);
1025
95ea3627
ID		 1026 return retval;
1027}
1028
1029/*
1030 * TX descriptor initialization
1031 */
1032static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1033 struct sk_buff *skb,
61486e0f 1034 struct txentry_desc *txdesc)
95ea3627 1035{
181d6902 1036 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
0b8004aa 1037 __le32 *txd = (__le32 *) skb->data;
95ea3627
ID		 1038 u32 word;
1039
1040 /*
1041 * Start writing the descriptor words.
1042 */
e01f1ec3
GW		 1043 rt2x00_desc_read(txd, 0, &word);
1044 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
1045 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1046 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1047 rt2x00_set_field32(&word, TXD_W0_ACK,
1048 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1049 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1050 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1051 rt2x00_set_field32(&word, TXD_W0_OFDM,
1052 (txdesc->rate_mode == RATE_MODE_OFDM));
1053 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1054 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1055 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1056 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1057 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1058 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
1059 rt2x00_desc_write(txd, 0, word);
1060
95ea3627 1061 rt2x00_desc_read(txd, 1, &word);
dddfb478 1062 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
181d6902
ID		 1063 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
1064 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1065 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1066 rt2x00_desc_write(txd, 1, word);
1067
1068 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1069 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1070 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1071 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1072 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1073 rt2x00_desc_write(txd, 2, word);
1074
dddfb478
ID		 1075 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1076 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1077 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1078 }
1079
85b7a8b3
GW		 1080 /*
1081 * Register descriptor details in skb frame descriptor.
1082 */
0b8004aa 1083 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
85b7a8b3
GW		 1084 skbdesc->desc = txd;
1085 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1086}
1087
bd88a781
ID		 1088/*
1089 * TX data initialization
1090 */
1091static void rt2500usb_beacondone(struct urb *urb);
1092
f224f4ef
GW		 1093static void rt2500usb_write_beacon(struct queue_entry *entry,
1094 struct txentry_desc *txdesc)
bd88a781
ID		 1095{
1096 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1097 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1098 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
f1ca2167 1099 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
bd88a781 1100 int length;
d61cb266 1101 u16 reg, reg0;
bd88a781 1102
bd88a781
ID		 1103 /*
1104 * Disable beaconing while we are reloading the beacon data,
1105 * otherwise we might be sending out invalid data.
1106 */
1107 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
bd88a781
ID		 1108 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1109 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1110
0b8004aa
GW		 1111 /*
1112 * Add space for the descriptor in front of the skb.
1113 */
1114 skb_push(entry->skb, TXD_DESC_SIZE);
1115 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1116
5c3b685c
GW		 1117 /*
1118 * Write the TX descriptor for the beacon.
1119 */
1120 rt2500usb_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1121
1122 /*
1123 * Dump beacon to userspace through debugfs.
1124 */
1125 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1126
bd88a781
ID		 1127 /*
1128 * USB devices cannot blindly pass the skb->len as the
1129 * length of the data to usb_fill_bulk_urb. Pass the skb
1130 * to the driver to determine what the length should be.
1131 */
f1ca2167 1132 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
bd88a781
ID		 1133
1134 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
1135 entry->skb->data, length, rt2500usb_beacondone,
1136 entry);
1137
1138 /*
1139 * Second we need to create the guardian byte.
1140 * We only need a single byte, so lets recycle
1141 * the 'flags' field we are not using for beacons.
1142 */
1143 bcn_priv->guardian_data = 0;
1144 usb_fill_bulk_urb(bcn_priv->guardian_urb, usb_dev, pipe,
1145 &bcn_priv->guardian_data, 1, rt2500usb_beacondone,
1146 entry);
1147
1148 /*
1149 * Send out the guardian byte.
1150 */
1151 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
d61cb266
GW		 1152
1153 /*
1154 * Enable beaconing again.
1155 */
1156 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1157 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
1158 reg0 = reg;
1159 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1160 /*
1161 * Beacon generation will fail initially.
1162 * To prevent this we need to change the TXRX_CSR19
1163 * register several times (reg0 is the same as reg
1164 * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
1165 * and 1 in reg).
1166 */
1167 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1168 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1169 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1170 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1171 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
bd88a781
ID		 1172}
1173
f1ca2167 1174static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1175{
1176 int length;
1177
1178 /*
1179 * The length _must_ be a multiple of 2,
1180 * but it must _not_ be a multiple of the USB packet size.
1181 */
f1ca2167
ID		 1182 length = roundup(entry->skb->len, 2);
1183 length += (2 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1184
1185 return length;
1186}
1187
95ea3627
ID		 1188/*
1189 * RX control handlers
1190 */
181d6902
ID		 1191static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1192 struct rxdone_entry_desc *rxdesc)
95ea3627 1193{
dddfb478 1194 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1195 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
181d6902
ID		 1196 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1197 __le32 *rxd =
1198 (__le32 *)(entry->skb->data +
b8be63ff
ID		 1199 (entry_priv->urb->actual_length -
1200 entry->queue->desc_size));
95ea3627
ID		 1201 u32 word0;
1202 u32 word1;
1203
f855c10b 1204 /*
a26cbc65
GW		 1205 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1206 * frame data in rt2x00usb.
f855c10b 1207 */
a26cbc65 1208 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1209 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1210
1211 /*
70a96109 1212 * It is now safe to read the descriptor on all architectures.
f855c10b 1213 */
95ea3627
ID		 1214 rt2x00_desc_read(rxd, 0, &word0);
1215 rt2x00_desc_read(rxd, 1, &word1);
1216
4150c572 1217 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1218 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1219 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1220 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1221
78b8f3b0
GW		 1222 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
1223 if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1224 rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
dddfb478
ID		 1225
1226 if (rxdesc->cipher != CIPHER_NONE) {
1227 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1228 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1229 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1230
dddfb478
ID		 1231 /* ICV is located at the end of frame */
1232
f3d340c1 1233 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
dddfb478
ID		 1234 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1235 rxdesc->flags |= RX_FLAG_DECRYPTED;
1236 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1237 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1238 }
1239
95ea3627
ID		 1240 /*
1241 * Obtain the status about this packet.
89993890
ID		 1242 * When frame was received with an OFDM bitrate,
1243 * the signal is the PLCP value. If it was received with
1244 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1245 */
181d6902 1246 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
dddfb478
ID		 1247 rxdesc->rssi =
1248 rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
181d6902 1249 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1250
19d30e02
ID		 1251 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1252 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1253 else
1254 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1255 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1256 rxdesc->dev_flags |= RXDONE_MY_BSS;
7d1de806 1257
2ae23854
MN		 1258 /*
1259 * Adjust the skb memory window to the frame boundaries.
1260 */
2ae23854 1261 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1262}
1263
1264/*
1265 * Interrupt functions.
1266 */
1267static void rt2500usb_beacondone(struct urb *urb)
1268{
181d6902 1269 struct queue_entry *entry = (struct queue_entry *)urb->context;
b8be63ff 1270 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
95ea3627 1271
0262ab0d 1272 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags))
95ea3627
ID		 1273 return;
1274
1275 /*
1276 * Check if this was the guardian beacon,
1277 * if that was the case we need to send the real beacon now.
1278 * Otherwise we should free the sk_buffer, the device
1279 * should be doing the rest of the work now.
1280 */
b8be63ff
ID		 1281 if (bcn_priv->guardian_urb == urb) {
1282 usb_submit_urb(bcn_priv->urb, GFP_ATOMIC);
1283 } else if (bcn_priv->urb == urb) {
181d6902
ID		 1284 dev_kfree_skb(entry->skb);
1285 entry->skb = NULL;
95ea3627
ID		 1286 }
1287}
1288
1289/*
1290 * Device probe functions.
1291 */
1292static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1293{
1294 u16 word;
1295 u8 *mac;
6bb40dd1 1296 u8 bbp;
95ea3627
ID		 1297
1298 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1299
1300 /*
1301 * Start validation of the data that has been read.
1302 */
1303 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1304 if (!is_valid_ether_addr(mac)) {
1305 random_ether_addr(mac);
e174961c 1306 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1307 }
1308
1309 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1310 if (word == 0xffff) {
1311 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1312 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1313 ANTENNA_SW_DIVERSITY);
1314 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1315 ANTENNA_SW_DIVERSITY);
1316 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1317 LED_MODE_DEFAULT);
95ea3627
ID		 1318 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1319 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1320 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1321 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1322 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1323 }
1324
1325 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1326 if (word == 0xffff) {
1327 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1328 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1329 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1330 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1331 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1332 }
1333
1334 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1335 if (word == 0xffff) {
1336 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1337 DEFAULT_RSSI_OFFSET);
1338 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1339 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1340 }
1341
1342 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &word);
1343 if (word == 0xffff) {
1344 rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
1345 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
1346 EEPROM(rt2x00dev, "BBPtune: 0x%04x\n", word);
1347 }
1348
6bb40dd1
ID		 1349 /*
1350 * Switch lower vgc bound to current BBP R17 value,
1351 * lower the value a bit for better quality.
1352 */
1353 rt2500usb_bbp_read(rt2x00dev, 17, &bbp);
1354 bbp -= 6;
1355
95ea3627
ID		 1356 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &word);
1357 if (word == 0xffff) {
1358 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
6bb40dd1 1359 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
95ea3627
ID		 1360 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
1361 EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
8d8acd46
ID		 1362 } else {
1363 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
1364 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
95ea3627
ID		 1365 }
1366
1367 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word);
1368 if (word == 0xffff) {
1369 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
1370 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
1371 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
1372 EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
1373 }
1374
1375 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word);
1376 if (word == 0xffff) {
1377 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
1378 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
1379 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
1380 EEPROM(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
1381 }
1382
1383 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &word);
1384 if (word == 0xffff) {
1385 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
1386 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
1387 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
1388 EEPROM(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
1389 }
1390
1391 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &word);
1392 if (word == 0xffff) {
1393 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
1394 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
1395 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
1396 EEPROM(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
1397 }
1398
1399 return 0;
1400}
1401
1402static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1403{
1404 u16 reg;
1405 u16 value;
1406 u16 eeprom;
1407
1408 /*
1409 * Read EEPROM word for configuration.
1410 */
1411 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1412
1413 /*
1414 * Identify RF chipset.
1415 */
1416 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1417 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1418 rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
1419
49e721ec 1420 if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) {
95ea3627
ID		 1421 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1422 return -ENODEV;
1423 }
1424
5122d898
GW		 1425 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1426 !rt2x00_rf(rt2x00dev, RF2523) &&
1427 !rt2x00_rf(rt2x00dev, RF2524) &&
1428 !rt2x00_rf(rt2x00dev, RF2525) &&
1429 !rt2x00_rf(rt2x00dev, RF2525E) &&
1430 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1431 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1432 return -ENODEV;
1433 }
1434
1435 /*
1436 * Identify default antenna configuration.
1437 */
addc81bd 1438 rt2x00dev->default_ant.tx =
95ea3627 1439 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1440 rt2x00dev->default_ant.rx =
95ea3627
ID		 1441 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1442
addc81bd
ID		 1443 /*
1444 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1445 * I am not 100% sure about this, but the legacy drivers do not
1446 * indicate antenna swapping in software is required when
1447 * diversity is enabled.
1448 */
1449 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1450 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1451 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1452 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1453
95ea3627
ID		 1454 /*
1455 * Store led mode, for correct led behaviour.
1456 */
771fd565 1457#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1458 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1459
475433be 1460 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1461 if (value == LED_MODE_TXRX_ACTIVITY ||
1462 value == LED_MODE_DEFAULT ||
1463 value == LED_MODE_ASUS)
475433be
ID		 1464 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1465 LED_TYPE_ACTIVITY);
771fd565 1466#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627 1467
7396faf4
ID		 1468 /*
1469 * Detect if this device has an hardware controlled radio.
1470 */
7396faf4
ID		 1471 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1472 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1473
95ea3627
ID		 1474 /*
1475 * Check if the BBP tuning should be disabled.
1476 */
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1478 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1479 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1480
1481 /*
1482 * Read the RSSI <-> dBm offset information.
1483 */
1484 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1485 rt2x00dev->rssi_offset =
1486 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1487
1488 return 0;
1489}
1490
1491/*
1492 * RF value list for RF2522
1493 * Supports: 2.4 GHz
1494 */
1495static const struct rf_channel rf_vals_bg_2522[] = {
1496 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1497 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1498 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1499 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1500 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1501 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1502 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1503 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1504 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1505 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1506 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1507 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1508 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1509 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1510};
1511
1512/*
1513 * RF value list for RF2523
1514 * Supports: 2.4 GHz
1515 */
1516static const struct rf_channel rf_vals_bg_2523[] = {
1517 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1518 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1519 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1520 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1521 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1522 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1523 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1524 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1525 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1526 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1527 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1528 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1529 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1530 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1531};
1532
1533/*
1534 * RF value list for RF2524
1535 * Supports: 2.4 GHz
1536 */
1537static const struct rf_channel rf_vals_bg_2524[] = {
1538 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1539 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1540 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1541 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1542 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1543 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1544 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1545 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1546 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1547 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1548 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1549 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1550 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1551 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1552};
1553
1554/*
1555 * RF value list for RF2525
1556 * Supports: 2.4 GHz
1557 */
1558static const struct rf_channel rf_vals_bg_2525[] = {
1559 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1560 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1561 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1562 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1563 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1564 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1565 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1566 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1567 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1568 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1569 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1570 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1571 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1572 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1573};
1574
1575/*
1576 * RF value list for RF2525e
1577 * Supports: 2.4 GHz
1578 */
1579static const struct rf_channel rf_vals_bg_2525e[] = {
1580 { 1, 0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
1581 { 2, 0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
1582 { 3, 0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
1583 { 4, 0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
1584 { 5, 0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
1585 { 6, 0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
1586 { 7, 0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
1587 { 8, 0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
1588 { 9, 0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
1589 { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
1590 { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
1591 { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
1592 { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
1593 { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
1594};
1595
1596/*
1597 * RF value list for RF5222
1598 * Supports: 2.4 GHz & 5.2 GHz
1599 */
1600static const struct rf_channel rf_vals_5222[] = {
1601 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1602 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1603 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1604 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1605 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1606 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1607 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1608 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1609 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1610 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1611 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1612 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1613 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1614 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1615
1616 /* 802.11 UNI / HyperLan 2 */
1617 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1618 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1619 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1620 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1621 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1622 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1623 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1624 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1625
1626 /* 802.11 HyperLan 2 */
1627 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1628 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1629 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1630 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1631 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1632 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1633 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1634 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1635 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1636 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1637
1638 /* 802.11 UNII */
1639 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1640 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1641 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1642 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1643 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1644};
1645
8c5e7a5f 1646static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1647{
1648 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1649 struct channel_info *info;
1650 char *tx_power;
95ea3627
ID		 1651 unsigned int i;
1652
1653 /*
1654 * Initialize all hw fields.
1655 */
1656 rt2x00dev->hw->flags =
95ea3627 1657 IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a 1658 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1659 IEEE80211_HW_SIGNAL_DBM |
1660 IEEE80211_HW_SUPPORTS_PS |
1661 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1662
14a3bf89 1663 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1664 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1665 rt2x00_eeprom_addr(rt2x00dev,
1666 EEPROM_MAC_ADDR_0));
1667
95ea3627
ID		 1668 /*
1669 * Initialize hw_mode information.
1670 */
31562e80
ID		 1671 spec->supported_bands = SUPPORT_BAND_2GHZ;
1672 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1673
5122d898 1674 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1675 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1676 spec->channels = rf_vals_bg_2522;
5122d898 1677 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1678 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1679 spec->channels = rf_vals_bg_2523;
5122d898 1680 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1681 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1682 spec->channels = rf_vals_bg_2524;
5122d898 1683 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1684 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1685 spec->channels = rf_vals_bg_2525;
5122d898 1686 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1687 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1688 spec->channels = rf_vals_bg_2525e;
5122d898 1689 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1690 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1691 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1692 spec->channels = rf_vals_5222;
95ea3627 1693 }
8c5e7a5f
ID		 1694
1695 /*
1696 * Create channel information array
1697 */
1698 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1699 if (!info)
1700 return -ENOMEM;
1701
1702 spec->channels_info = info;
1703
1704 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1705 for (i = 0; i < 14; i++)
1706 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1707
1708 if (spec->num_channels > 14) {
1709 for (i = 14; i < spec->num_channels; i++)
1710 info[i].tx_power1 = DEFAULT_TXPOWER;
1711 }
1712
1713 return 0;
95ea3627
ID		 1714}
1715
1716static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1717{
1718 int retval;
1719
1720 /*
1721 * Allocate eeprom data.
1722 */
1723 retval = rt2500usb_validate_eeprom(rt2x00dev);
1724 if (retval)
1725 return retval;
1726
1727 retval = rt2500usb_init_eeprom(rt2x00dev);
1728 if (retval)
1729 return retval;
1730
1731 /*
1732 * Initialize hw specifications.
1733 */
8c5e7a5f
ID		 1734 retval = rt2500usb_probe_hw_mode(rt2x00dev);
1735 if (retval)
1736 return retval;
95ea3627
ID		 1737
1738 /*
181d6902 1739 * This device requires the atim queue
95ea3627 1740 */
181d6902
ID		 1741 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1742 __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
dddfb478
ID		 1743 if (!modparam_nohwcrypt) {
1744 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
3f787bd6 1745 __set_bit(DRIVER_REQUIRE_COPY_IV, &rt2x00dev->flags);
dddfb478 1746 }
d06193f3 1747 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 1748
1749 /*
1750 * Set the rssi offset.
1751 */
1752 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1753
1754 return 0;
1755}
1756
95ea3627
ID		 1757static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1758 .tx = rt2x00mac_tx,
4150c572
JB		 1759 .start = rt2x00mac_start,
1760 .stop = rt2x00mac_stop,
95ea3627
ID		 1761 .add_interface = rt2x00mac_add_interface,
1762 .remove_interface = rt2x00mac_remove_interface,
1763 .config = rt2x00mac_config,
3a643d24 1764 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1765 .set_tim = rt2x00mac_set_tim,
dddfb478 1766 .set_key = rt2x00mac_set_key,
95ea3627 1767 .get_stats = rt2x00mac_get_stats,
471b3efd 1768 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1769 .conf_tx = rt2x00mac_conf_tx,
e47a5cdd 1770 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1771};
1772
1773static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1774 .probe_hw = rt2500usb_probe_hw,
1775 .initialize = rt2x00usb_initialize,
1776 .uninitialize = rt2x00usb_uninitialize,
798b7adb 1777 .clear_entry = rt2x00usb_clear_entry,
95ea3627 1778 .set_device_state = rt2500usb_set_device_state,
7396faf4 1779 .rfkill_poll = rt2500usb_rfkill_poll,
95ea3627
ID		 1780 .link_stats = rt2500usb_link_stats,
1781 .reset_tuner = rt2500usb_reset_tuner,
95ea3627
ID		 1782 .write_tx_desc = rt2500usb_write_tx_desc,
1783 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 1784 .write_beacon = rt2500usb_write_beacon,
dd9fa2d2 1785 .get_tx_data_len = rt2500usb_get_tx_data_len,
d61cb266 1786 .kick_tx_queue = rt2x00usb_kick_tx_queue,
a2c9b652 1787 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 1788 .fill_rxdone = rt2500usb_fill_rxdone,
dddfb478
ID		 1789 .config_shared_key = rt2500usb_config_key,
1790 .config_pairwise_key = rt2500usb_config_key,
3a643d24 1791 .config_filter = rt2500usb_config_filter,
6bb40dd1 1792 .config_intf = rt2500usb_config_intf,
72810379 1793 .config_erp = rt2500usb_config_erp,
e4ea1c40 1794 .config_ant = rt2500usb_config_ant,
95ea3627
ID		 1795 .config = rt2500usb_config,
1796};
1797
181d6902
ID		 1798static const struct data_queue_desc rt2500usb_queue_rx = {
1799 .entry_num = RX_ENTRIES,
1800 .data_size = DATA_FRAME_SIZE,
1801 .desc_size = RXD_DESC_SIZE,
b8be63ff 1802 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1803};
1804
1805static const struct data_queue_desc rt2500usb_queue_tx = {
1806 .entry_num = TX_ENTRIES,
1807 .data_size = DATA_FRAME_SIZE,
1808 .desc_size = TXD_DESC_SIZE,
b8be63ff 1809 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1810};
1811
1812static const struct data_queue_desc rt2500usb_queue_bcn = {
1813 .entry_num = BEACON_ENTRIES,
1814 .data_size = MGMT_FRAME_SIZE,
1815 .desc_size = TXD_DESC_SIZE,
1816 .priv_size = sizeof(struct queue_entry_priv_usb_bcn),
1817};
1818
1819static const struct data_queue_desc rt2500usb_queue_atim = {
1820 .entry_num = ATIM_ENTRIES,
1821 .data_size = DATA_FRAME_SIZE,
1822 .desc_size = TXD_DESC_SIZE,
b8be63ff 1823 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1824};
1825
95ea3627 1826static const struct rt2x00_ops rt2500usb_ops = {
04d0362e
GW		 1827 .name = KBUILD_MODNAME,
1828 .max_sta_intf = 1,
1829 .max_ap_intf = 1,
1830 .eeprom_size = EEPROM_SIZE,
1831 .rf_size = RF_SIZE,
1832 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1833 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 1834 .rx = &rt2500usb_queue_rx,
1835 .tx = &rt2500usb_queue_tx,
1836 .bcn = &rt2500usb_queue_bcn,
1837 .atim = &rt2500usb_queue_atim,
1838 .lib = &rt2500usb_rt2x00_ops,
1839 .hw = &rt2500usb_mac80211_ops,
95ea3627 1840#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1841 .debugfs = &rt2500usb_rt2x00debug,
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ID		 1842#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1843};
1844
1845/*
1846 * rt2500usb module information.
1847 */
1848static struct usb_device_id rt2500usb_device_table[] = {
1849 /* ASUS */
1850 { USB_DEVICE(0x0b05, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
1851 { USB_DEVICE(0x0b05, 0x1707), USB_DEVICE_DATA(&rt2500usb_ops) },
1852 /* Belkin */
1853 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt2500usb_ops) },
1854 { USB_DEVICE(0x050d, 0x7051), USB_DEVICE_DATA(&rt2500usb_ops) },
1855 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt2500usb_ops) },
1856 /* Cisco Systems */
1857 { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) },
1858 { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) },
1859 { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) },
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XVP		 1860 /* CNet */
1861 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1862 /* Conceptronic */
1863 { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) },
1864 /* D-LINK */
1865 { USB_DEVICE(0x2001, 0x3c00), USB_DEVICE_DATA(&rt2500usb_ops) },
1866 /* Gigabyte */
1867 { USB_DEVICE(0x1044, 0x8001), USB_DEVICE_DATA(&rt2500usb_ops) },
1868 { USB_DEVICE(0x1044, 0x8007), USB_DEVICE_DATA(&rt2500usb_ops) },
1869 /* Hercules */
1870 { USB_DEVICE(0x06f8, 0xe000), USB_DEVICE_DATA(&rt2500usb_ops) },
1871 /* Melco */
db433feb 1872 { USB_DEVICE(0x0411, 0x005e), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1873 { USB_DEVICE(0x0411, 0x0066), USB_DEVICE_DATA(&rt2500usb_ops) },
1874 { USB_DEVICE(0x0411, 0x0067), USB_DEVICE_DATA(&rt2500usb_ops) },
1875 { USB_DEVICE(0x0411, 0x008b), USB_DEVICE_DATA(&rt2500usb_ops) },
1876 { USB_DEVICE(0x0411, 0x0097), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1877 /* MSI */
1878 { USB_DEVICE(0x0db0, 0x6861), USB_DEVICE_DATA(&rt2500usb_ops) },
1879 { USB_DEVICE(0x0db0, 0x6865), USB_DEVICE_DATA(&rt2500usb_ops) },
1880 { USB_DEVICE(0x0db0, 0x6869), USB_DEVICE_DATA(&rt2500usb_ops) },
1881 /* Ralink */
1882 { USB_DEVICE(0x148f, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
1883 { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) },
1884 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) },
1885 { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
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XVP		 1886 /* Sagem */
1887 { USB_DEVICE(0x079b, 0x004b), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1888 /* Siemens */
1889 { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) },
1890 /* SMC */
1891 { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) },
1892 /* Spairon */
1893 { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) },
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XVP		 1894 /* SURECOM */
1895 { USB_DEVICE(0x0769, 0x11f3), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1896 /* Trust */
1897 { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
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XVP		 1898 /* VTech */
1899 { USB_DEVICE(0x0f88, 0x3012), USB_DEVICE_DATA(&rt2500usb_ops) },
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ID		 1900 /* Zinwell */
1901 { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) },
1902 { 0, }
1903};
1904
1905MODULE_AUTHOR(DRV_PROJECT);
1906MODULE_VERSION(DRV_VERSION);
1907MODULE_DESCRIPTION("Ralink RT2500 USB Wireless LAN driver.");
1908MODULE_SUPPORTED_DEVICE("Ralink RT2570 USB chipset based cards");
1909MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
1910MODULE_LICENSE("GPL");
1911
1912static struct usb_driver rt2500usb_driver = {
2360157c 1913 .name = KBUILD_MODNAME,
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ID		 1914 .id_table = rt2500usb_device_table,
1915 .probe = rt2x00usb_probe,
1916 .disconnect = rt2x00usb_disconnect,
1917 .suspend = rt2x00usb_suspend,
1918 .resume = rt2x00usb_resume,
1919};
1920
1921static int __init rt2500usb_init(void)
1922{
1923 return usb_register(&rt2500usb_driver);
1924}
1925
1926static void __exit rt2500usb_exit(void)
1927{
1928 usb_deregister(&rt2500usb_driver);
1929}
1930
1931module_init(rt2500usb_init);
1932module_exit(rt2500usb_exit);
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