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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500usb.c
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95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500usb
23 Abstract: rt2500usb device specific routines.
24 Supported chipsets: RT2570.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
95ea3627
ID		 33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2500usb.h"
38
dddfb478
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
f1dd2b23 42static int modparam_nohwcrypt = 0;
dddfb478
ID		 43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2500usb_register_read and rt2500usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * If the csr_mutex is already held then the _lock variants must
3d82346c 59 * be used instead.
95ea3627 60 */
0e14f6d3 61static inline void rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 62 const unsigned int offset,
63 u16 *value)
64{
65 __le16 reg;
66 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 68 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 69 *value = le16_to_cpu(reg);
70}
71
3d82346c
AB		 72static inline void rt2500usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 u16 *value)
75{
76 __le16 reg;
77 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 79 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 80 *value = le16_to_cpu(reg);
81}
82
0e14f6d3 83static inline void rt2500usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset,
85 void *value, const u16 length)
86{
95ea3627
ID		 87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
88 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 89 value, length,
90 REGISTER_TIMEOUT16(length));
95ea3627
ID		 91}
92
0e14f6d3 93static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int offset,
95 u16 value)
96{
97 __le16 reg = cpu_to_le16(value);
98 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
99 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 100 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 101}
102
3d82346c
AB		 103static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
104 const unsigned int offset,
105 u16 value)
106{
107 __le16 reg = cpu_to_le16(value);
108 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
109 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 110 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 111}
112
0e14f6d3 113static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int offset,
115 void *value, const u16 length)
116{
95ea3627
ID		 117 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
118 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 119 value, length,
120 REGISTER_TIMEOUT16(length));
95ea3627
ID		 121}
122
c9c3b1a5
ID		 123static int rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
124 const unsigned int offset,
125 struct rt2x00_field16 field,
126 u16 *reg)
95ea3627 127{
95ea3627
ID		 128 unsigned int i;
129
130 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
c9c3b1a5
ID		 131 rt2500usb_register_read_lock(rt2x00dev, offset, reg);
132 if (!rt2x00_get_field16(*reg, field))
133 return 1;
95ea3627
ID		 134 udelay(REGISTER_BUSY_DELAY);
135 }
136
c9c3b1a5
ID		 137 ERROR(rt2x00dev, "Indirect register access failed: "
138 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
139 *reg = ~0;
140
141 return 0;
95ea3627
ID		 142}
143
c9c3b1a5
ID		 144#define WAIT_FOR_BBP(__dev, __reg) \
145 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
146#define WAIT_FOR_RF(__dev, __reg) \
147 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
148
0e14f6d3 149static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 150 const unsigned int word, const u8 value)
151{
152 u16 reg;
153
8ff48a8b 154 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 155
95ea3627 156 /*
c9c3b1a5
ID		 157 * Wait until the BBP becomes available, afterwards we
158 * can safely write the new data into the register.
95ea3627 159 */
c9c3b1a5
ID		 160 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
161 reg = 0;
162 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
163 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
164 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
3d82346c 165
c9c3b1a5
ID		 166 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
167 }
99ade259 168
8ff48a8b 169 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 170}
171
0e14f6d3 172static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 173 const unsigned int word, u8 *value)
174{
175 u16 reg;
176
8ff48a8b 177 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 178
95ea3627 179 /*
c9c3b1a5
ID		 180 * Wait until the BBP becomes available, afterwards we
181 * can safely write the read request into the register.
182 * After the data has been written, we wait until hardware
183 * returns the correct value, if at any time the register
184 * doesn't become available in time, reg will be 0xffffffff
185 * which means we return 0xff to the caller.
95ea3627 186 */
c9c3b1a5
ID		 187 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
188 reg = 0;
189 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
190 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
95ea3627 191
c9c3b1a5 192 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
95ea3627 193
c9c3b1a5
ID		 194 if (WAIT_FOR_BBP(rt2x00dev, &reg))
195 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg);
196 }
95ea3627 197
95ea3627 198 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
3d82346c 199
8ff48a8b 200 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 201}
202
0e14f6d3 203static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 204 const unsigned int word, const u32 value)
205{
206 u16 reg;
95ea3627 207
8ff48a8b 208 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 209
c9c3b1a5
ID		 210 /*
211 * Wait until the RF becomes available, afterwards we
212 * can safely write the new data into the register.
213 */
214 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
215 reg = 0;
216 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
217 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
218
219 reg = 0;
220 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
221 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
222 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
223 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
224
225 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg);
226 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 227 }
228
8ff48a8b 229 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
743b97ca
ID		 233static void _rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
234 const unsigned int offset,
235 u32 *value)
95ea3627 236{
743b97ca 237 rt2500usb_register_read(rt2x00dev, offset, (u16 *)value);
95ea3627
ID		 238}
239
743b97ca
ID		 240static void _rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
241 const unsigned int offset,
242 u32 value)
95ea3627 243{
743b97ca 244 rt2500usb_register_write(rt2x00dev, offset, value);
95ea3627
ID		 245}
246
247static const struct rt2x00debug rt2500usb_rt2x00debug = {
248 .owner = THIS_MODULE,
249 .csr = {
743b97ca
ID		 250 .read = _rt2500usb_register_read,
251 .write = _rt2500usb_register_write,
252 .flags = RT2X00DEBUGFS_OFFSET,
253 .word_base = CSR_REG_BASE,
95ea3627
ID		 254 .word_size = sizeof(u16),
255 .word_count = CSR_REG_SIZE / sizeof(u16),
256 },
257 .eeprom = {
258 .read = rt2x00_eeprom_read,
259 .write = rt2x00_eeprom_write,
743b97ca 260 .word_base = EEPROM_BASE,
95ea3627
ID		 261 .word_size = sizeof(u16),
262 .word_count = EEPROM_SIZE / sizeof(u16),
263 },
264 .bbp = {
265 .read = rt2500usb_bbp_read,
266 .write = rt2500usb_bbp_write,
743b97ca 267 .word_base = BBP_BASE,
95ea3627
ID		 268 .word_size = sizeof(u8),
269 .word_count = BBP_SIZE / sizeof(u8),
270 },
271 .rf = {
272 .read = rt2x00_rf_read,
273 .write = rt2500usb_rf_write,
743b97ca 274 .word_base = RF_BASE,
95ea3627
ID		 275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
7396faf4
ID		 281static int rt2500usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282{
283 u16 reg;
284
285 rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg);
286 return rt2x00_get_field32(reg, MAC_CSR19_BIT7);
287}
7396faf4 288
771fd565 289#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 290static void rt2500usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 291 enum led_brightness brightness)
292{
293 struct rt2x00_led *led =
294 container_of(led_cdev, struct rt2x00_led, led_dev);
295 unsigned int enabled = brightness != LED_OFF;
a2e1d52a 296 u16 reg;
a9450b70 297
a2e1d52a 298 rt2500usb_register_read(led->rt2x00dev, MAC_CSR20, &reg);
47b10cd1 299
a2e1d52a
ID		 300 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
301 rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled);
302 else if (led->type == LED_TYPE_ACTIVITY)
303 rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled);
304
305 rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg);
306}
307
308static int rt2500usb_blink_set(struct led_classdev *led_cdev,
309 unsigned long *delay_on,
310 unsigned long *delay_off)
311{
312 struct rt2x00_led *led =
313 container_of(led_cdev, struct rt2x00_led, led_dev);
314 u16 reg;
315
316 rt2500usb_register_read(led->rt2x00dev, MAC_CSR21, &reg);
317 rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on);
318 rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off);
319 rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg);
a9450b70 320
a2e1d52a 321 return 0;
a9450b70 322}
475433be
ID		 323
324static void rt2500usb_init_led(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_led *led,
326 enum led_type type)
327{
328 led->rt2x00dev = rt2x00dev;
329 led->type = type;
330 led->led_dev.brightness_set = rt2500usb_brightness_set;
331 led->led_dev.blink_set = rt2500usb_blink_set;
332 led->flags = LED_INITIALIZED;
333}
771fd565 334#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 335
95ea3627
ID		 336/*
337 * Configuration handlers.
338 */
dddfb478
ID		 339
340/*
341 * rt2500usb does not differentiate between shared and pairwise
342 * keys, so we should use the same function for both key types.
343 */
344static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
345 struct rt2x00lib_crypto *crypto,
346 struct ieee80211_key_conf *key)
347{
348 int timeout;
349 u32 mask;
350 u16 reg;
351
352 if (crypto->cmd == SET_KEY) {
353 /*
354 * Pairwise key will always be entry 0, but this
355 * could collide with a shared key on the same
356 * position...
357 */
358 mask = TXRX_CSR0_KEY_ID.bit_mask;
359
360 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
361 reg &= mask;
362
363 if (reg && reg == mask)
364 return -ENOSPC;
365
366 reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
367
368 key->hw_key_idx += reg ? ffz(reg) : 0;
369
370 /*
371 * The encryption key doesn't fit within the CSR cache,
3ad2f3fb 372 * this means we should allocate it separately and use
dddfb478
ID		 373 * rt2x00usb_vendor_request() to send the key to the hardware.
374 */
375 reg = KEY_ENTRY(key->hw_key_idx);
376 timeout = REGISTER_TIMEOUT32(sizeof(crypto->key));
377 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
378 USB_VENDOR_REQUEST_OUT, reg,
379 crypto->key,
380 sizeof(crypto->key),
381 timeout);
382
383 /*
384 * The driver does not support the IV/EIV generation
f3d340c1 385 * in hardware. However it demands the data to be provided
3ad2f3fb 386 * both separately as well as inside the frame.
f3d340c1
ID		 387 * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib
388 * to ensure rt2x00lib will not strip the data from the
389 * frame after the copy, now we must tell mac80211
dddfb478
ID		 390 * to generate the IV/EIV data.
391 */
392 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
393 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
394 }
395
396 /*
397 * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
398 * a particular key is valid.
399 */
400 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
401 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
402 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
403
404 mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
405 if (crypto->cmd == SET_KEY)
406 mask |= 1 << key->hw_key_idx;
407 else if (crypto->cmd == DISABLE_KEY)
408 mask &= ~(1 << key->hw_key_idx);
409 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
410 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
411
412 return 0;
413}
414
3a643d24
ID		 415static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
416 const unsigned int filter_flags)
417{
418 u16 reg;
419
420 /*
421 * Start configuration steps.
422 * Note that the version error will always be dropped
423 * and broadcast frames will always be accepted since
424 * there is no filter for it at this time.
425 */
426 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
427 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
428 !(filter_flags & FIF_FCSFAIL));
429 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
430 !(filter_flags & FIF_PLCPFAIL));
431 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
432 !(filter_flags & FIF_CONTROL));
433 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
434 !(filter_flags & FIF_PROMISC_IN_BSS));
435 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
e0b005fa
ID		 436 !(filter_flags & FIF_PROMISC_IN_BSS) &&
437 !rt2x00dev->intf_ap_count);
3a643d24
ID		 438 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
439 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
440 !(filter_flags & FIF_ALLMULTI));
441 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
442 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
443}
444
6bb40dd1
ID		 445static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
446 struct rt2x00_intf *intf,
447 struct rt2x00intf_conf *conf,
448 const unsigned int flags)
95ea3627 449{
6bb40dd1 450 unsigned int bcn_preload;
95ea3627
ID		 451 u16 reg;
452
6bb40dd1 453 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 454 /*
455 * Enable beacon config
456 */
bad13639 457 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 458 rt2500usb_register_read(rt2x00dev, TXRX_CSR20, &reg);
459 rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6);
460 rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW,
05c914fe 461 2 * (conf->type != NL80211_IFTYPE_STATION));
6bb40dd1 462 rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
95ea3627 463
6bb40dd1
ID		 464 /*
465 * Enable synchronisation.
466 */
467 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
468 rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
469 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
470
471 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
fd3c91c5 472 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
6bb40dd1 473 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
fd3c91c5 474 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
6bb40dd1
ID		 475 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
476 }
95ea3627 477
6bb40dd1
ID		 478 if (flags & CONFIG_UPDATE_MAC)
479 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, conf->mac,
480 (3 * sizeof(__le16)));
481
482 if (flags & CONFIG_UPDATE_BSSID)
483 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, conf->bssid,
484 (3 * sizeof(__le16)));
95ea3627
ID		 485}
486
3a643d24
ID		 487static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
488 struct rt2x00lib_erp *erp)
95ea3627 489{
95ea3627 490 u16 reg;
95ea3627 491
95ea3627 492 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);
4f5af6eb 493 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
72810379 494 !!erp->short_preamble);
95ea3627 495 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
95ea3627 496
e4ea1c40 497 rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates);
95ea3627 498
8a566afe
ID		 499 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
500 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4);
501 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
502
e4ea1c40
ID		 503 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
504 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
505 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
95ea3627
ID		 506}
507
e4ea1c40
ID		 508static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
509 struct antenna_setup *ant)
95ea3627
ID		 510{
511 u8 r2;
512 u8 r14;
513 u16 csr5;
514 u16 csr6;
515
a4fe07d9
ID		 516 /*
517 * We should never come here because rt2x00lib is supposed
518 * to catch this and send us the correct antenna explicitely.
519 */
520 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
521 ant->tx == ANTENNA_SW_DIVERSITY);
522
95ea3627
ID		 523 rt2500usb_bbp_read(rt2x00dev, 2, &r2);
524 rt2500usb_bbp_read(rt2x00dev, 14, &r14);
525 rt2500usb_register_read(rt2x00dev, PHY_CSR5, &csr5);
526 rt2500usb_register_read(rt2x00dev, PHY_CSR6, &csr6);
527
528 /*
529 * Configure the TX antenna.
530 */
addc81bd 531 switch (ant->tx) {
95ea3627
ID		 532 case ANTENNA_HW_DIVERSITY:
533 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
534 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
535 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
536 break;
537 case ANTENNA_A:
538 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
539 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
540 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
541 break;
542 case ANTENNA_B:
a4fe07d9 543 default:
95ea3627
ID		 544 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
545 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
546 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
547 break;
548 }
549
550 /*
551 * Configure the RX antenna.
552 */
addc81bd 553 switch (ant->rx) {
95ea3627
ID		 554 case ANTENNA_HW_DIVERSITY:
555 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
556 break;
557 case ANTENNA_A:
558 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
559 break;
560 case ANTENNA_B:
a4fe07d9 561 default:
95ea3627
ID		 562 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
563 break;
564 }
565
566 /*
567 * RT2525E and RT5222 need to flip TX I/Q
568 */
5122d898 569 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 570 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
571 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
572 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
573
574 /*
575 * RT2525E does not need RX I/Q Flip.
576 */
5122d898 577 if (rt2x00_rf(rt2x00dev, RF2525E))
95ea3627
ID		 578 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
579 } else {
580 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
581 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
582 }
583
584 rt2500usb_bbp_write(rt2x00dev, 2, r2);
585 rt2500usb_bbp_write(rt2x00dev, 14, r14);
586 rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
587 rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
588}
589
e4ea1c40
ID		 590static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
591 struct rf_channel *rf, const int txpower)
592{
593 /*
594 * Set TXpower.
595 */
596 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
597
598 /*
599 * For RT2525E we should first set the channel to half band higher.
600 */
5122d898 601 if (rt2x00_rf(rt2x00dev, RF2525E)) {
e4ea1c40
ID		 602 static const u32 vals[] = {
603 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
604 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
605 0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
606 0x00000902, 0x00000906
607 };
608
609 rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
610 if (rf->rf4)
611 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
612 }
613
614 rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
615 rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
616 rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
617 if (rf->rf4)
618 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
619}
620
621static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
622 const int txpower)
623{
624 u32 rf3;
625
626 rt2x00_rf_read(rt2x00dev, 3, &rf3);
627 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
628 rt2500usb_rf_write(rt2x00dev, 3, rf3);
629}
630
7d7f19cc
ID		 631static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
632 struct rt2x00lib_conf *libconf)
633{
634 enum dev_state state =
635 (libconf->conf->flags & IEEE80211_CONF_PS) ?
636 STATE_SLEEP : STATE_AWAKE;
637 u16 reg;
638
639 if (state == STATE_SLEEP) {
640 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
641 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
6b347bff 642 rt2x00dev->beacon_int - 20);
7d7f19cc
ID		 643 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
644 libconf->conf->listen_interval - 1);
645
646 /* We must first disable autowake before it can be enabled */
647 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
648 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
649
650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
652 }
653
654 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
655}
656
95ea3627 657static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 658 struct rt2x00lib_conf *libconf,
659 const unsigned int flags)
95ea3627 660{
e4ea1c40 661 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 662 rt2500usb_config_channel(rt2x00dev, &libconf->rf,
663 libconf->conf->power_level);
e4ea1c40
ID		 664 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
665 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 666 rt2500usb_config_txpower(rt2x00dev,
667 libconf->conf->power_level);
7d7f19cc
ID		 668 if (flags & IEEE80211_CONF_CHANGE_PS)
669 rt2500usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 670}
671
95ea3627
ID		 672/*
673 * Link tuning
674 */
ebcf26da
ID		 675static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev,
676 struct link_qual *qual)
95ea3627
ID		 677{
678 u16 reg;
679
680 /*
681 * Update FCS error count from register.
682 */
683 rt2500usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 684 qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 685
686 /*
687 * Update False CCA count from register.
688 */
689 rt2500usb_register_read(rt2x00dev, STA_CSR3, &reg);
ebcf26da 690 qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
95ea3627
ID		 691}
692
5352ff65
ID		 693static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
694 struct link_qual *qual)
95ea3627
ID		 695{
696 u16 eeprom;
697 u16 value;
698
699 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &eeprom);
700 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
701 rt2500usb_bbp_write(rt2x00dev, 24, value);
702
703 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &eeprom);
704 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
705 rt2500usb_bbp_write(rt2x00dev, 25, value);
706
707 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &eeprom);
708 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
709 rt2500usb_bbp_write(rt2x00dev, 61, value);
710
711 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &eeprom);
712 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
713 rt2500usb_bbp_write(rt2x00dev, 17, value);
714
5352ff65 715 qual->vgc_level = value;
95ea3627
ID		 716}
717
95ea3627
ID		 718/*
719 * Initialization functions.
720 */
721static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
722{
723 u16 reg;
724
725 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
726 USB_MODE_TEST, REGISTER_TIMEOUT);
727 rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
728 0x00f0, REGISTER_TIMEOUT);
729
730 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
731 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
732 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
733
734 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
735 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
736
737 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
738 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
739 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
740 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
741 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
742
743 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
744 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
745 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
746 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
747 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
748
749 rt2500usb_register_read(rt2x00dev, TXRX_CSR5, &reg);
750 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
751 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
752 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
753 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
754 rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
755
756 rt2500usb_register_read(rt2x00dev, TXRX_CSR6, &reg);
757 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
758 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
759 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
760 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
761 rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
762
763 rt2500usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
764 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
765 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
766 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
767 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
768 rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
769
770 rt2500usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
771 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
772 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
773 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
774 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
775 rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
776
1f909162
ID		 777 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
778 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
779 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0);
780 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
781 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
782 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
783
95ea3627
ID		 784 rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
785 rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
786
787 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
788 return -EBUSY;
789
790 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
791 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
792 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
793 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
794 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
795
5122d898 796 if (rt2x00_rev(rt2x00dev) >= RT2570_VERSION_C) {
95ea3627 797 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg);
ddc827f9 798 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
95ea3627 799 } else {
ddc827f9
ID		 800 reg = 0;
801 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1);
802 rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3);
95ea3627
ID		 803 }
804 rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
805
806 rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
807 rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
808 rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
809 rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
810
811 rt2500usb_register_read(rt2x00dev, MAC_CSR8, &reg);
812 rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
813 rt2x00dev->rx->data_size);
814 rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
815
816 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
817 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
dddfb478 818 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
95ea3627
ID		 819 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
820
821 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
822 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
823 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
824
825 rt2500usb_register_read(rt2x00dev, PHY_CSR4, &reg);
826 rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
827 rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
828
829 rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
830 rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
831 rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
832
833 return 0;
834}
835
2b08da3f 836static int rt2500usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 837{
838 unsigned int i;
95ea3627 839 u8 value;
95ea3627
ID		 840
841 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
842 rt2500usb_bbp_read(rt2x00dev, 0, &value);
843 if ((value != 0xff) && (value != 0x00))
2b08da3f 844 return 0;
95ea3627
ID		 845 udelay(REGISTER_BUSY_DELAY);
846 }
847
848 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
849 return -EACCES;
2b08da3f
ID		 850}
851
852static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
853{
854 unsigned int i;
855 u16 eeprom;
856 u8 value;
857 u8 reg_id;
858
859 if (unlikely(rt2500usb_wait_bbp_ready(rt2x00dev)))
860 return -EACCES;
95ea3627 861
95ea3627
ID		 862 rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
863 rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
864 rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
865 rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
866 rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
867 rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
868 rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
869 rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
870 rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
871 rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
872 rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
873 rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
874 rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
875 rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
876 rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
877 rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
878 rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
879 rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
880 rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
881 rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
882 rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
883 rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
884 rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
885 rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
886 rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
887 rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
888 rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
889 rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
890 rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
891 rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
892 rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
893
95ea3627
ID		 894 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
895 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
896
897 if (eeprom != 0xffff && eeprom != 0x0000) {
898 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
899 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 900 rt2500usb_bbp_write(rt2x00dev, reg_id, value);
901 }
902 }
95ea3627
ID		 903
904 return 0;
905}
906
907/*
908 * Device state switch handlers.
909 */
910static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
911 enum dev_state state)
912{
913 u16 reg;
914
915 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
916 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
2b08da3f
ID		 917 (state == STATE_RADIO_RX_OFF) ||
918 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 919 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
920}
921
922static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
923{
924 /*
925 * Initialize all registers.
926 */
2b08da3f
ID		 927 if (unlikely(rt2500usb_init_registers(rt2x00dev) ||
928 rt2500usb_init_bbp(rt2x00dev)))
95ea3627 929 return -EIO;
95ea3627 930
95ea3627
ID		 931 return 0;
932}
933
934static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
935{
95ea3627
ID		 936 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
937 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
938
939 /*
940 * Disable synchronisation.
941 */
942 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
943
944 rt2x00usb_disable_radio(rt2x00dev);
945}
946
947static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
948 enum dev_state state)
949{
950 u16 reg;
951 u16 reg2;
952 unsigned int i;
953 char put_to_sleep;
954 char bbp_state;
955 char rf_state;
956
957 put_to_sleep = (state != STATE_AWAKE);
958
959 reg = 0;
960 rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
961 rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
962 rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
963 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
964 rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
965 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
966
967 /*
968 * Device is not guaranteed to be in the requested state yet.
969 * We must wait until the register indicates that the
970 * device has entered the correct state.
971 */
972 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
973 rt2500usb_register_read(rt2x00dev, MAC_CSR17, &reg2);
974 bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
975 rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
976 if (bbp_state == state && rf_state == state)
977 return 0;
978 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
979 msleep(30);
980 }
981
95ea3627
ID		 982 return -EBUSY;
983}
984
985static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
986 enum dev_state state)
987{
988 int retval = 0;
989
990 switch (state) {
991 case STATE_RADIO_ON:
992 retval = rt2500usb_enable_radio(rt2x00dev);
993 break;
994 case STATE_RADIO_OFF:
995 rt2500usb_disable_radio(rt2x00dev);
996 break;
997 case STATE_RADIO_RX_ON:
61667d8d 998 case STATE_RADIO_RX_ON_LINK:
95ea3627 999 case STATE_RADIO_RX_OFF:
61667d8d 1000 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1001 rt2500usb_toggle_rx(rt2x00dev, state);
1002 break;
1003 case STATE_RADIO_IRQ_ON:
1004 case STATE_RADIO_IRQ_OFF:
1005 /* No support, but no error either */
95ea3627
ID		 1006 break;
1007 case STATE_DEEP_SLEEP:
1008 case STATE_SLEEP:
1009 case STATE_STANDBY:
1010 case STATE_AWAKE:
1011 retval = rt2500usb_set_state(rt2x00dev, state);
1012 break;
1013 default:
1014 retval = -ENOTSUPP;
1015 break;
1016 }
1017
2b08da3f
ID		 1018 if (unlikely(retval))
1019 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1020 state, retval);
1021
95ea3627
ID		 1022 return retval;
1023}
1024
1025/*
1026 * TX descriptor initialization
1027 */
1028static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1029 struct sk_buff *skb,
61486e0f 1030 struct txentry_desc *txdesc)
95ea3627 1031{
181d6902 1032 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1033 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1034 u32 word;
1035
1036 /*
1037 * Start writing the descriptor words.
1038 */
1039 rt2x00_desc_read(txd, 1, &word);
dddfb478 1040 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
181d6902
ID		 1041 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
1042 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1043 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1044 rt2x00_desc_write(txd, 1, word);
1045
1046 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1047 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1048 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1049 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1050 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1051 rt2x00_desc_write(txd, 2, word);
1052
dddfb478
ID		 1053 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1054 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1055 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1056 }
1057
95ea3627 1058 rt2x00_desc_read(txd, 0, &word);
61486e0f 1059 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
95ea3627 1060 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1061 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1062 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1063 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1064 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1065 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1066 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1067 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1068 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
61486e0f 1069 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
181d6902 1070 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1abc3656 1071 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
f1dd2b23 1072 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
dddfb478 1073 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
95ea3627
ID		 1074 rt2x00_desc_write(txd, 0, word);
1075}
1076
bd88a781
ID		 1077/*
1078 * TX data initialization
1079 */
1080static void rt2500usb_beacondone(struct urb *urb);
1081
1082static void rt2500usb_write_beacon(struct queue_entry *entry)
1083{
1084 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1085 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1086 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
1087 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
f1ca2167 1088 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
bd88a781
ID		 1089 int length;
1090 u16 reg;
1091
1092 /*
1093 * Add the descriptor in front of the skb.
1094 */
1095 skb_push(entry->skb, entry->queue->desc_size);
1096 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1097 skbdesc->desc = entry->skb->data;
1098
1099 /*
1100 * Disable beaconing while we are reloading the beacon data,
1101 * otherwise we might be sending out invalid data.
1102 */
1103 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
bd88a781
ID		 1104 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1105 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1106
1107 /*
1108 * USB devices cannot blindly pass the skb->len as the
1109 * length of the data to usb_fill_bulk_urb. Pass the skb
1110 * to the driver to determine what the length should be.
1111 */
f1ca2167 1112 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
bd88a781
ID		 1113
1114 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
1115 entry->skb->data, length, rt2500usb_beacondone,
1116 entry);
1117
1118 /*
1119 * Second we need to create the guardian byte.
1120 * We only need a single byte, so lets recycle
1121 * the 'flags' field we are not using for beacons.
1122 */
1123 bcn_priv->guardian_data = 0;
1124 usb_fill_bulk_urb(bcn_priv->guardian_urb, usb_dev, pipe,
1125 &bcn_priv->guardian_data, 1, rt2500usb_beacondone,
1126 entry);
1127
1128 /*
1129 * Send out the guardian byte.
1130 */
1131 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
1132}
1133
f1ca2167 1134static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1135{
1136 int length;
1137
1138 /*
1139 * The length _must_ be a multiple of 2,
1140 * but it must _not_ be a multiple of the USB packet size.
1141 */
f1ca2167
ID		 1142 length = roundup(entry->skb->len, 2);
1143 length += (2 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1144
1145 return length;
1146}
1147
95ea3627 1148static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1149 const enum data_queue_qid queue)
95ea3627 1150{
d6756d0d 1151 u16 reg, reg0;
95ea3627 1152
f019d514
ID		 1153 if (queue != QID_BEACON) {
1154 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1155 return;
f019d514 1156 }
95ea3627
ID		 1157
1158 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
1159 if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) {
8af244cc
ID		 1160 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1161 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
d6756d0d 1162 reg0 = reg;
95ea3627
ID		 1163 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1164 /*
1165 * Beacon generation will fail initially.
d6756d0d
IP		 1166 * To prevent this we need to change the TXRX_CSR19
1167 * register several times (reg0 is the same as reg
1168 * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
1169 * and 1 in reg).
95ea3627
ID		 1170 */
1171 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
d6756d0d 1172 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
95ea3627 1173 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
d6756d0d 1174 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
95ea3627
ID		 1175 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1176 }
1177}
1178
1179/*
1180 * RX control handlers
1181 */
181d6902
ID		 1182static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1183 struct rxdone_entry_desc *rxdesc)
95ea3627 1184{
dddfb478 1185 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1186 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
181d6902
ID		 1187 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1188 __le32 *rxd =
1189 (__le32 *)(entry->skb->data +
b8be63ff
ID		 1190 (entry_priv->urb->actual_length -
1191 entry->queue->desc_size));
95ea3627
ID		 1192 u32 word0;
1193 u32 word1;
1194
f855c10b 1195 /*
a26cbc65
GW		 1196 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1197 * frame data in rt2x00usb.
f855c10b 1198 */
a26cbc65 1199 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1200 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1201
1202 /*
70a96109 1203 * It is now safe to read the descriptor on all architectures.
f855c10b 1204 */
95ea3627
ID		 1205 rt2x00_desc_read(rxd, 0, &word0);
1206 rt2x00_desc_read(rxd, 1, &word1);
1207
4150c572 1208 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1209 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1210 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1211 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1212
dddfb478
ID		 1213 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1214 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
1215 if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1216 rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
1217 }
1218
1219 if (rxdesc->cipher != CIPHER_NONE) {
1220 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1221 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1222 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1223
dddfb478
ID		 1224 /* ICV is located at the end of frame */
1225
f3d340c1 1226 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
dddfb478
ID		 1227 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1228 rxdesc->flags |= RX_FLAG_DECRYPTED;
1229 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1230 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1231 }
1232
95ea3627
ID		 1233 /*
1234 * Obtain the status about this packet.
89993890
ID		 1235 * When frame was received with an OFDM bitrate,
1236 * the signal is the PLCP value. If it was received with
1237 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1238 */
181d6902 1239 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
dddfb478
ID		 1240 rxdesc->rssi =
1241 rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
181d6902 1242 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1243
19d30e02
ID		 1244 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1245 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1246 else
1247 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1248 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1249 rxdesc->dev_flags |= RXDONE_MY_BSS;
7d1de806 1250
2ae23854
MN		 1251 /*
1252 * Adjust the skb memory window to the frame boundaries.
1253 */
2ae23854 1254 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1255}
1256
1257/*
1258 * Interrupt functions.
1259 */
1260static void rt2500usb_beacondone(struct urb *urb)
1261{
181d6902 1262 struct queue_entry *entry = (struct queue_entry *)urb->context;
b8be63ff 1263 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
95ea3627 1264
0262ab0d 1265 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags))
95ea3627
ID		 1266 return;
1267
1268 /*
1269 * Check if this was the guardian beacon,
1270 * if that was the case we need to send the real beacon now.
1271 * Otherwise we should free the sk_buffer, the device
1272 * should be doing the rest of the work now.
1273 */
b8be63ff
ID		 1274 if (bcn_priv->guardian_urb == urb) {
1275 usb_submit_urb(bcn_priv->urb, GFP_ATOMIC);
1276 } else if (bcn_priv->urb == urb) {
181d6902
ID		 1277 dev_kfree_skb(entry->skb);
1278 entry->skb = NULL;
95ea3627
ID		 1279 }
1280}
1281
1282/*
1283 * Device probe functions.
1284 */
1285static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1286{
1287 u16 word;
1288 u8 *mac;
6bb40dd1 1289 u8 bbp;
95ea3627
ID		 1290
1291 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1292
1293 /*
1294 * Start validation of the data that has been read.
1295 */
1296 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1297 if (!is_valid_ether_addr(mac)) {
1298 random_ether_addr(mac);
e174961c 1299 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1300 }
1301
1302 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1303 if (word == 0xffff) {
1304 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1305 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1306 ANTENNA_SW_DIVERSITY);
1307 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1308 ANTENNA_SW_DIVERSITY);
1309 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1310 LED_MODE_DEFAULT);
95ea3627
ID		 1311 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1312 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1313 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1314 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1315 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1316 }
1317
1318 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1319 if (word == 0xffff) {
1320 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1321 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1322 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1323 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1324 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1325 }
1326
1327 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1328 if (word == 0xffff) {
1329 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1330 DEFAULT_RSSI_OFFSET);
1331 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1332 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1333 }
1334
1335 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &word);
1336 if (word == 0xffff) {
1337 rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
1338 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
1339 EEPROM(rt2x00dev, "BBPtune: 0x%04x\n", word);
1340 }
1341
6bb40dd1
ID		 1342 /*
1343 * Switch lower vgc bound to current BBP R17 value,
1344 * lower the value a bit for better quality.
1345 */
1346 rt2500usb_bbp_read(rt2x00dev, 17, &bbp);
1347 bbp -= 6;
1348
95ea3627
ID		 1349 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &word);
1350 if (word == 0xffff) {
1351 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
6bb40dd1 1352 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
95ea3627
ID		 1353 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
1354 EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
8d8acd46
ID		 1355 } else {
1356 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
1357 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
95ea3627
ID		 1358 }
1359
1360 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word);
1361 if (word == 0xffff) {
1362 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
1363 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
1364 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
1365 EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
1366 }
1367
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word);
1369 if (word == 0xffff) {
1370 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
1371 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
1372 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
1373 EEPROM(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
1374 }
1375
1376 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &word);
1377 if (word == 0xffff) {
1378 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
1379 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
1380 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
1381 EEPROM(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
1382 }
1383
1384 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &word);
1385 if (word == 0xffff) {
1386 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
1387 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
1388 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
1389 EEPROM(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
1390 }
1391
1392 return 0;
1393}
1394
1395static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1396{
1397 u16 reg;
1398 u16 value;
1399 u16 eeprom;
1400
1401 /*
1402 * Read EEPROM word for configuration.
1403 */
1404 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1405
1406 /*
1407 * Identify RF chipset.
1408 */
1409 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1410 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1411 rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
1412
49e721ec 1413 if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) {
95ea3627
ID		 1414 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1415 return -ENODEV;
1416 }
1417
5122d898
GW		 1418 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1419 !rt2x00_rf(rt2x00dev, RF2523) &&
1420 !rt2x00_rf(rt2x00dev, RF2524) &&
1421 !rt2x00_rf(rt2x00dev, RF2525) &&
1422 !rt2x00_rf(rt2x00dev, RF2525E) &&
1423 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1424 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1425 return -ENODEV;
1426 }
1427
1428 /*
1429 * Identify default antenna configuration.
1430 */
addc81bd 1431 rt2x00dev->default_ant.tx =
95ea3627 1432 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1433 rt2x00dev->default_ant.rx =
95ea3627
ID		 1434 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1435
addc81bd
ID		 1436 /*
1437 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1438 * I am not 100% sure about this, but the legacy drivers do not
1439 * indicate antenna swapping in software is required when
1440 * diversity is enabled.
1441 */
1442 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1443 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1444 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1445 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1446
95ea3627
ID		 1447 /*
1448 * Store led mode, for correct led behaviour.
1449 */
771fd565 1450#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1451 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1452
475433be 1453 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1454 if (value == LED_MODE_TXRX_ACTIVITY ||
1455 value == LED_MODE_DEFAULT ||
1456 value == LED_MODE_ASUS)
475433be
ID		 1457 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1458 LED_TYPE_ACTIVITY);
771fd565 1459#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627 1460
7396faf4
ID		 1461 /*
1462 * Detect if this device has an hardware controlled radio.
1463 */
7396faf4
ID		 1464 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1465 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1466
95ea3627
ID		 1467 /*
1468 * Check if the BBP tuning should be disabled.
1469 */
1470 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1471 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1472 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1473
1474 /*
1475 * Read the RSSI <-> dBm offset information.
1476 */
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1478 rt2x00dev->rssi_offset =
1479 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1480
1481 return 0;
1482}
1483
1484/*
1485 * RF value list for RF2522
1486 * Supports: 2.4 GHz
1487 */
1488static const struct rf_channel rf_vals_bg_2522[] = {
1489 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1490 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1491 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1492 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1493 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1494 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1495 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1496 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1497 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1498 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1499 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1500 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1501 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1502 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1503};
1504
1505/*
1506 * RF value list for RF2523
1507 * Supports: 2.4 GHz
1508 */
1509static const struct rf_channel rf_vals_bg_2523[] = {
1510 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1511 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1512 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1513 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1514 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1515 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1516 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1517 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1518 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1519 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1520 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1521 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1522 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1523 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1524};
1525
1526/*
1527 * RF value list for RF2524
1528 * Supports: 2.4 GHz
1529 */
1530static const struct rf_channel rf_vals_bg_2524[] = {
1531 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1532 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1533 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1534 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1535 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1536 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1537 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1538 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1539 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1540 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1541 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1542 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1543 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1544 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1545};
1546
1547/*
1548 * RF value list for RF2525
1549 * Supports: 2.4 GHz
1550 */
1551static const struct rf_channel rf_vals_bg_2525[] = {
1552 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1553 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1554 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1555 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1556 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1557 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1558 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1559 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1560 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1561 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1562 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1563 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1564 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1565 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1566};
1567
1568/*
1569 * RF value list for RF2525e
1570 * Supports: 2.4 GHz
1571 */
1572static const struct rf_channel rf_vals_bg_2525e[] = {
1573 { 1, 0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
1574 { 2, 0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
1575 { 3, 0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
1576 { 4, 0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
1577 { 5, 0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
1578 { 6, 0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
1579 { 7, 0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
1580 { 8, 0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
1581 { 9, 0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
1582 { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
1583 { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
1584 { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
1585 { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
1586 { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
1587};
1588
1589/*
1590 * RF value list for RF5222
1591 * Supports: 2.4 GHz & 5.2 GHz
1592 */
1593static const struct rf_channel rf_vals_5222[] = {
1594 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1595 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1596 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1597 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1598 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1599 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1600 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1601 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1602 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1603 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1604 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1605 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1606 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1607 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1608
1609 /* 802.11 UNI / HyperLan 2 */
1610 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1611 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1612 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1613 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1614 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1615 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1616 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1617 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1618
1619 /* 802.11 HyperLan 2 */
1620 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1621 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1622 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1623 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1624 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1625 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1626 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1627 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1628 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1629 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1630
1631 /* 802.11 UNII */
1632 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1633 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1634 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1635 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1636 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1637};
1638
8c5e7a5f 1639static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1640{
1641 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1642 struct channel_info *info;
1643 char *tx_power;
95ea3627
ID		 1644 unsigned int i;
1645
1646 /*
1647 * Initialize all hw fields.
1648 */
1649 rt2x00dev->hw->flags =
95ea3627 1650 IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a 1651 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1652 IEEE80211_HW_SIGNAL_DBM |
1653 IEEE80211_HW_SUPPORTS_PS |
1654 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1655
14a3bf89 1656 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1657 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1658 rt2x00_eeprom_addr(rt2x00dev,
1659 EEPROM_MAC_ADDR_0));
1660
95ea3627
ID		 1661 /*
1662 * Initialize hw_mode information.
1663 */
31562e80
ID		 1664 spec->supported_bands = SUPPORT_BAND_2GHZ;
1665 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1666
5122d898 1667 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1668 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1669 spec->channels = rf_vals_bg_2522;
5122d898 1670 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1671 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1672 spec->channels = rf_vals_bg_2523;
5122d898 1673 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1674 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1675 spec->channels = rf_vals_bg_2524;
5122d898 1676 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1677 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1678 spec->channels = rf_vals_bg_2525;
5122d898 1679 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1680 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1681 spec->channels = rf_vals_bg_2525e;
5122d898 1682 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1683 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1684 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1685 spec->channels = rf_vals_5222;
95ea3627 1686 }
8c5e7a5f
ID		 1687
1688 /*
1689 * Create channel information array
1690 */
1691 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1692 if (!info)
1693 return -ENOMEM;
1694
1695 spec->channels_info = info;
1696
1697 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1698 for (i = 0; i < 14; i++)
1699 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1700
1701 if (spec->num_channels > 14) {
1702 for (i = 14; i < spec->num_channels; i++)
1703 info[i].tx_power1 = DEFAULT_TXPOWER;
1704 }
1705
1706 return 0;
95ea3627
ID		 1707}
1708
1709static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1710{
1711 int retval;
1712
1713 /*
1714 * Allocate eeprom data.
1715 */
1716 retval = rt2500usb_validate_eeprom(rt2x00dev);
1717 if (retval)
1718 return retval;
1719
1720 retval = rt2500usb_init_eeprom(rt2x00dev);
1721 if (retval)
1722 return retval;
1723
1724 /*
1725 * Initialize hw specifications.
1726 */
8c5e7a5f
ID		 1727 retval = rt2500usb_probe_hw_mode(rt2x00dev);
1728 if (retval)
1729 return retval;
95ea3627
ID		 1730
1731 /*
181d6902 1732 * This device requires the atim queue
95ea3627 1733 */
181d6902
ID		 1734 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1735 __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
dddfb478
ID		 1736 if (!modparam_nohwcrypt) {
1737 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
3f787bd6 1738 __set_bit(DRIVER_REQUIRE_COPY_IV, &rt2x00dev->flags);
dddfb478 1739 }
d06193f3 1740 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 1741
1742 /*
1743 * Set the rssi offset.
1744 */
1745 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1746
1747 return 0;
1748}
1749
95ea3627
ID		 1750static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1751 .tx = rt2x00mac_tx,
4150c572
JB		 1752 .start = rt2x00mac_start,
1753 .stop = rt2x00mac_stop,
95ea3627
ID		 1754 .add_interface = rt2x00mac_add_interface,
1755 .remove_interface = rt2x00mac_remove_interface,
1756 .config = rt2x00mac_config,
3a643d24 1757 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1758 .set_tim = rt2x00mac_set_tim,
dddfb478 1759 .set_key = rt2x00mac_set_key,
95ea3627 1760 .get_stats = rt2x00mac_get_stats,
471b3efd 1761 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1762 .conf_tx = rt2x00mac_conf_tx,
e47a5cdd 1763 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 1764};
1765
1766static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1767 .probe_hw = rt2500usb_probe_hw,
1768 .initialize = rt2x00usb_initialize,
1769 .uninitialize = rt2x00usb_uninitialize,
798b7adb 1770 .clear_entry = rt2x00usb_clear_entry,
95ea3627 1771 .set_device_state = rt2500usb_set_device_state,
7396faf4 1772 .rfkill_poll = rt2500usb_rfkill_poll,
95ea3627
ID		 1773 .link_stats = rt2500usb_link_stats,
1774 .reset_tuner = rt2500usb_reset_tuner,
95ea3627
ID		 1775 .write_tx_desc = rt2500usb_write_tx_desc,
1776 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 1777 .write_beacon = rt2500usb_write_beacon,
dd9fa2d2 1778 .get_tx_data_len = rt2500usb_get_tx_data_len,
95ea3627 1779 .kick_tx_queue = rt2500usb_kick_tx_queue,
a2c9b652 1780 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 1781 .fill_rxdone = rt2500usb_fill_rxdone,
dddfb478
ID		 1782 .config_shared_key = rt2500usb_config_key,
1783 .config_pairwise_key = rt2500usb_config_key,
3a643d24 1784 .config_filter = rt2500usb_config_filter,
6bb40dd1 1785 .config_intf = rt2500usb_config_intf,
72810379 1786 .config_erp = rt2500usb_config_erp,
e4ea1c40 1787 .config_ant = rt2500usb_config_ant,
95ea3627
ID		 1788 .config = rt2500usb_config,
1789};
1790
181d6902
ID		 1791static const struct data_queue_desc rt2500usb_queue_rx = {
1792 .entry_num = RX_ENTRIES,
1793 .data_size = DATA_FRAME_SIZE,
1794 .desc_size = RXD_DESC_SIZE,
b8be63ff 1795 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1796};
1797
1798static const struct data_queue_desc rt2500usb_queue_tx = {
1799 .entry_num = TX_ENTRIES,
1800 .data_size = DATA_FRAME_SIZE,
1801 .desc_size = TXD_DESC_SIZE,
b8be63ff 1802 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1803};
1804
1805static const struct data_queue_desc rt2500usb_queue_bcn = {
1806 .entry_num = BEACON_ENTRIES,
1807 .data_size = MGMT_FRAME_SIZE,
1808 .desc_size = TXD_DESC_SIZE,
1809 .priv_size = sizeof(struct queue_entry_priv_usb_bcn),
1810};
1811
1812static const struct data_queue_desc rt2500usb_queue_atim = {
1813 .entry_num = ATIM_ENTRIES,
1814 .data_size = DATA_FRAME_SIZE,
1815 .desc_size = TXD_DESC_SIZE,
b8be63ff 1816 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1817};
1818
95ea3627 1819static const struct rt2x00_ops rt2500usb_ops = {
04d0362e
GW		 1820 .name = KBUILD_MODNAME,
1821 .max_sta_intf = 1,
1822 .max_ap_intf = 1,
1823 .eeprom_size = EEPROM_SIZE,
1824 .rf_size = RF_SIZE,
1825 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1826 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 1827 .rx = &rt2500usb_queue_rx,
1828 .tx = &rt2500usb_queue_tx,
1829 .bcn = &rt2500usb_queue_bcn,
1830 .atim = &rt2500usb_queue_atim,
1831 .lib = &rt2500usb_rt2x00_ops,
1832 .hw = &rt2500usb_mac80211_ops,
95ea3627 1833#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1834 .debugfs = &rt2500usb_rt2x00debug,
95ea3627
ID		 1835#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1836};
1837
1838/*
1839 * rt2500usb module information.
1840 */
1841static struct usb_device_id rt2500usb_device_table[] = {
1842 /* ASUS */
1843 { USB_DEVICE(0x0b05, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
1844 { USB_DEVICE(0x0b05, 0x1707), USB_DEVICE_DATA(&rt2500usb_ops) },
1845 /* Belkin */
1846 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt2500usb_ops) },
1847 { USB_DEVICE(0x050d, 0x7051), USB_DEVICE_DATA(&rt2500usb_ops) },
1848 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt2500usb_ops) },
1849 /* Cisco Systems */
1850 { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) },
1851 { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) },
1852 { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) },
9eb77ab0
XVP		 1853 /* CNet */
1854 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1855 /* Conceptronic */
1856 { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) },
1857 /* D-LINK */
1858 { USB_DEVICE(0x2001, 0x3c00), USB_DEVICE_DATA(&rt2500usb_ops) },
1859 /* Gigabyte */
1860 { USB_DEVICE(0x1044, 0x8001), USB_DEVICE_DATA(&rt2500usb_ops) },
1861 { USB_DEVICE(0x1044, 0x8007), USB_DEVICE_DATA(&rt2500usb_ops) },
1862 /* Hercules */
1863 { USB_DEVICE(0x06f8, 0xe000), USB_DEVICE_DATA(&rt2500usb_ops) },
1864 /* Melco */
db433feb 1865 { USB_DEVICE(0x0411, 0x005e), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1866 { USB_DEVICE(0x0411, 0x0066), USB_DEVICE_DATA(&rt2500usb_ops) },
1867 { USB_DEVICE(0x0411, 0x0067), USB_DEVICE_DATA(&rt2500usb_ops) },
1868 { USB_DEVICE(0x0411, 0x008b), USB_DEVICE_DATA(&rt2500usb_ops) },
1869 { USB_DEVICE(0x0411, 0x0097), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1870 /* MSI */
1871 { USB_DEVICE(0x0db0, 0x6861), USB_DEVICE_DATA(&rt2500usb_ops) },
1872 { USB_DEVICE(0x0db0, 0x6865), USB_DEVICE_DATA(&rt2500usb_ops) },
1873 { USB_DEVICE(0x0db0, 0x6869), USB_DEVICE_DATA(&rt2500usb_ops) },
1874 /* Ralink */
1875 { USB_DEVICE(0x148f, 0x1706), USB_DEVICE_DATA(&rt2500usb_ops) },
1876 { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) },
1877 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) },
1878 { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
9eb77ab0
XVP		 1879 /* Sagem */
1880 { USB_DEVICE(0x079b, 0x004b), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1881 /* Siemens */
1882 { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) },
1883 /* SMC */
1884 { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) },
1885 /* Spairon */
1886 { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) },
9eb77ab0
XVP		 1887 /* SURECOM */
1888 { USB_DEVICE(0x0769, 0x11f3), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1889 /* Trust */
1890 { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) },
9eb77ab0
XVP		 1891 /* VTech */
1892 { USB_DEVICE(0x0f88, 0x3012), USB_DEVICE_DATA(&rt2500usb_ops) },
95ea3627
ID		 1893 /* Zinwell */
1894 { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) },
1895 { 0, }
1896};
1897
1898MODULE_AUTHOR(DRV_PROJECT);
1899MODULE_VERSION(DRV_VERSION);
1900MODULE_DESCRIPTION("Ralink RT2500 USB Wireless LAN driver.");
1901MODULE_SUPPORTED_DEVICE("Ralink RT2570 USB chipset based cards");
1902MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
1903MODULE_LICENSE("GPL");
1904
1905static struct usb_driver rt2500usb_driver = {
2360157c 1906 .name = KBUILD_MODNAME,
95ea3627
ID		 1907 .id_table = rt2500usb_device_table,
1908 .probe = rt2x00usb_probe,
1909 .disconnect = rt2x00usb_disconnect,
1910 .suspend = rt2x00usb_suspend,
1911 .resume = rt2x00usb_resume,
1912};
1913
1914static int __init rt2500usb_init(void)
1915{
1916 return usb_register(&rt2500usb_driver);
1917}
1918
1919static void __exit rt2500usb_exit(void)
1920{
1921 usb_deregister(&rt2500usb_driver);
1922}
1923
1924module_init(rt2500usb_init);
1925module_exit(rt2500usb_exit);
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