]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/rt2x00/rt2500usb.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
module_param: make bool parameters really bool (net & drivers/net)
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2500usb.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500usb
23 Abstract: rt2500usb device specific routines.
24 Supported chipsets: RT2570.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
95ea3627
ID		 33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2500usb.h"
38
dddfb478
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
eb939922 42static bool modparam_nohwcrypt;
dddfb478
ID		 43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2500usb_register_read and rt2500usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * If the csr_mutex is already held then the _lock variants must
3d82346c 59 * be used instead.
95ea3627 60 */
0e14f6d3 61static inline void rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 62 const unsigned int offset,
63 u16 *value)
64{
65 __le16 reg;
66 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 68 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 69 *value = le16_to_cpu(reg);
70}
71
3d82346c
AB		 72static inline void rt2500usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 u16 *value)
75{
76 __le16 reg;
77 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
c9c3b1a5 79 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 80 *value = le16_to_cpu(reg);
81}
82
0e14f6d3 83static inline void rt2500usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset,
85 void *value, const u16 length)
86{
95ea3627
ID		 87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
88 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 89 value, length,
90 REGISTER_TIMEOUT16(length));
95ea3627
ID		 91}
92
0e14f6d3 93static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int offset,
95 u16 value)
96{
97 __le16 reg = cpu_to_le16(value);
98 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
99 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 100 &reg, sizeof(reg), REGISTER_TIMEOUT);
95ea3627
ID		 101}
102
3d82346c
AB		 103static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
104 const unsigned int offset,
105 u16 value)
106{
107 __le16 reg = cpu_to_le16(value);
108 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
109 USB_VENDOR_REQUEST_OUT, offset,
c9c3b1a5 110 &reg, sizeof(reg), REGISTER_TIMEOUT);
3d82346c
AB		 111}
112
0e14f6d3 113static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int offset,
115 void *value, const u16 length)
116{
95ea3627
ID		 117 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
118 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 119 value, length,
120 REGISTER_TIMEOUT16(length));
95ea3627
ID		 121}
122
c9c3b1a5
ID		 123static int rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
124 const unsigned int offset,
125 struct rt2x00_field16 field,
126 u16 *reg)
95ea3627 127{
95ea3627
ID		 128 unsigned int i;
129
130 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
c9c3b1a5
ID		 131 rt2500usb_register_read_lock(rt2x00dev, offset, reg);
132 if (!rt2x00_get_field16(*reg, field))
133 return 1;
95ea3627
ID		 134 udelay(REGISTER_BUSY_DELAY);
135 }
136
c9c3b1a5
ID		 137 ERROR(rt2x00dev, "Indirect register access failed: "
138 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
139 *reg = ~0;
140
141 return 0;
95ea3627
ID		 142}
143
c9c3b1a5
ID		 144#define WAIT_FOR_BBP(__dev, __reg) \
145 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
146#define WAIT_FOR_RF(__dev, __reg) \
147 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
148
0e14f6d3 149static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 150 const unsigned int word, const u8 value)
151{
152 u16 reg;
153
8ff48a8b 154 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 155
95ea3627 156 /*
c9c3b1a5
ID		 157 * Wait until the BBP becomes available, afterwards we
158 * can safely write the new data into the register.
95ea3627 159 */
c9c3b1a5
ID		 160 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
161 reg = 0;
162 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
163 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
164 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
3d82346c 165
c9c3b1a5
ID		 166 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
167 }
99ade259 168
8ff48a8b 169 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 170}
171
0e14f6d3 172static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 173 const unsigned int word, u8 *value)
174{
175 u16 reg;
176
8ff48a8b 177 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 178
95ea3627 179 /*
c9c3b1a5
ID		 180 * Wait until the BBP becomes available, afterwards we
181 * can safely write the read request into the register.
182 * After the data has been written, we wait until hardware
183 * returns the correct value, if at any time the register
184 * doesn't become available in time, reg will be 0xffffffff
185 * which means we return 0xff to the caller.
95ea3627 186 */
c9c3b1a5
ID		 187 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
188 reg = 0;
189 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
190 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
95ea3627 191
c9c3b1a5 192 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
95ea3627 193
c9c3b1a5
ID		 194 if (WAIT_FOR_BBP(rt2x00dev, &reg))
195 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg);
196 }
95ea3627 197
95ea3627 198 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
3d82346c 199
8ff48a8b 200 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 201}
202
0e14f6d3 203static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 204 const unsigned int word, const u32 value)
205{
206 u16 reg;
95ea3627 207
8ff48a8b 208 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 209
c9c3b1a5
ID		 210 /*
211 * Wait until the RF becomes available, afterwards we
212 * can safely write the new data into the register.
213 */
214 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
215 reg = 0;
216 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
217 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
218
219 reg = 0;
220 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
221 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
222 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
223 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
224
225 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg);
226 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 227 }
228
8ff48a8b 229 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
743b97ca
ID		 233static void _rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
234 const unsigned int offset,
235 u32 *value)
95ea3627 236{
743b97ca 237 rt2500usb_register_read(rt2x00dev, offset, (u16 *)value);
95ea3627
ID		 238}
239
743b97ca
ID		 240static void _rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
241 const unsigned int offset,
242 u32 value)
95ea3627 243{
743b97ca 244 rt2500usb_register_write(rt2x00dev, offset, value);
95ea3627
ID		 245}
246
247static const struct rt2x00debug rt2500usb_rt2x00debug = {
248 .owner = THIS_MODULE,
249 .csr = {
743b97ca
ID		 250 .read = _rt2500usb_register_read,
251 .write = _rt2500usb_register_write,
252 .flags = RT2X00DEBUGFS_OFFSET,
253 .word_base = CSR_REG_BASE,
95ea3627
ID		 254 .word_size = sizeof(u16),
255 .word_count = CSR_REG_SIZE / sizeof(u16),
256 },
257 .eeprom = {
258 .read = rt2x00_eeprom_read,
259 .write = rt2x00_eeprom_write,
743b97ca 260 .word_base = EEPROM_BASE,
95ea3627
ID		 261 .word_size = sizeof(u16),
262 .word_count = EEPROM_SIZE / sizeof(u16),
263 },
264 .bbp = {
265 .read = rt2500usb_bbp_read,
266 .write = rt2500usb_bbp_write,
743b97ca 267 .word_base = BBP_BASE,
95ea3627
ID		 268 .word_size = sizeof(u8),
269 .word_count = BBP_SIZE / sizeof(u8),
270 },
271 .rf = {
272 .read = rt2x00_rf_read,
273 .write = rt2500usb_rf_write,
743b97ca 274 .word_base = RF_BASE,
95ea3627
ID		 275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
7396faf4
ID		 281static int rt2500usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282{
283 u16 reg;
284
285 rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg);
286 return rt2x00_get_field32(reg, MAC_CSR19_BIT7);
287}
7396faf4 288
771fd565 289#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 290static void rt2500usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 291 enum led_brightness brightness)
292{
293 struct rt2x00_led *led =
294 container_of(led_cdev, struct rt2x00_led, led_dev);
295 unsigned int enabled = brightness != LED_OFF;
a2e1d52a 296 u16 reg;
a9450b70 297
a2e1d52a 298 rt2500usb_register_read(led->rt2x00dev, MAC_CSR20, &reg);
47b10cd1 299
a2e1d52a
ID		 300 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
301 rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled);
302 else if (led->type == LED_TYPE_ACTIVITY)
303 rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled);
304
305 rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg);
306}
307
308static int rt2500usb_blink_set(struct led_classdev *led_cdev,
309 unsigned long *delay_on,
310 unsigned long *delay_off)
311{
312 struct rt2x00_led *led =
313 container_of(led_cdev, struct rt2x00_led, led_dev);
314 u16 reg;
315
316 rt2500usb_register_read(led->rt2x00dev, MAC_CSR21, &reg);
317 rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on);
318 rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off);
319 rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg);
a9450b70 320
a2e1d52a 321 return 0;
a9450b70 322}
475433be
ID		 323
324static void rt2500usb_init_led(struct rt2x00_dev *rt2x00dev,
325 struct rt2x00_led *led,
326 enum led_type type)
327{
328 led->rt2x00dev = rt2x00dev;
329 led->type = type;
330 led->led_dev.brightness_set = rt2500usb_brightness_set;
331 led->led_dev.blink_set = rt2500usb_blink_set;
332 led->flags = LED_INITIALIZED;
333}
771fd565 334#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 335
95ea3627
ID		 336/*
337 * Configuration handlers.
338 */
dddfb478
ID		 339
340/*
341 * rt2500usb does not differentiate between shared and pairwise
342 * keys, so we should use the same function for both key types.
343 */
344static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
345 struct rt2x00lib_crypto *crypto,
346 struct ieee80211_key_conf *key)
347{
dddfb478
ID		 348 u32 mask;
349 u16 reg;
75f64dd5 350 enum cipher curr_cipher;
dddfb478
ID		 351
352 if (crypto->cmd == SET_KEY) {
98ec6218
SG		 353 /*
354 * Disallow to set WEP key other than with index 0,
355 * it is known that not work at least on some hardware.
356 * SW crypto will be used in that case.
357 */
97359d12
JB		 358 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
359 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
360 key->keyidx != 0)
98ec6218
SG		 361 return -EOPNOTSUPP;
362
dddfb478
ID		 363 /*
364 * Pairwise key will always be entry 0, but this
365 * could collide with a shared key on the same
366 * position...
367 */
368 mask = TXRX_CSR0_KEY_ID.bit_mask;
369
370 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
75f64dd5 371 curr_cipher = rt2x00_get_field16(reg, TXRX_CSR0_ALGORITHM);
dddfb478
ID		 372 reg &= mask;
373
374 if (reg && reg == mask)
375 return -ENOSPC;
376
377 reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
378
379 key->hw_key_idx += reg ? ffz(reg) : 0;
75f64dd5
OZ		 380 /*
381 * Hardware requires that all keys use the same cipher
382 * (e.g. TKIP-only, AES-only, but not TKIP+AES).
383 * If this is not the first key, compare the cipher with the
384 * first one and fall back to SW crypto if not the same.
385 */
386 if (key->hw_key_idx > 0 && crypto->cipher != curr_cipher)
387 return -EOPNOTSUPP;
dddfb478 388
1279f5ed 389 rt2500usb_register_multiwrite(rt2x00dev, KEY_ENTRY(key->hw_key_idx),
96b61baf 390 crypto->key, sizeof(crypto->key));
dddfb478
ID		 391
392 /*
393 * The driver does not support the IV/EIV generation
f3d340c1 394 * in hardware. However it demands the data to be provided
3ad2f3fb 395 * both separately as well as inside the frame.
f3d340c1
ID		 396 * We already provided the CONFIG_CRYPTO_COPY_IV to rt2x00lib
397 * to ensure rt2x00lib will not strip the data from the
398 * frame after the copy, now we must tell mac80211
dddfb478
ID		 399 * to generate the IV/EIV data.
400 */
401 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
402 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
403 }
404
405 /*
406 * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
407 * a particular key is valid.
408 */
409 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
410 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
411 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
412
413 mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
414 if (crypto->cmd == SET_KEY)
415 mask |= 1 << key->hw_key_idx;
416 else if (crypto->cmd == DISABLE_KEY)
417 mask &= ~(1 << key->hw_key_idx);
418 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
419 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
420
421 return 0;
422}
423
3a643d24
ID		 424static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
425 const unsigned int filter_flags)
426{
427 u16 reg;
428
429 /*
430 * Start configuration steps.
431 * Note that the version error will always be dropped
432 * and broadcast frames will always be accepted since
433 * there is no filter for it at this time.
434 */
435 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
436 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
437 !(filter_flags & FIF_FCSFAIL));
438 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
439 !(filter_flags & FIF_PLCPFAIL));
440 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
441 !(filter_flags & FIF_CONTROL));
442 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
443 !(filter_flags & FIF_PROMISC_IN_BSS));
444 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
e0b005fa
ID		 445 !(filter_flags & FIF_PROMISC_IN_BSS) &&
446 !rt2x00dev->intf_ap_count);
3a643d24
ID		 447 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
448 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
449 !(filter_flags & FIF_ALLMULTI));
450 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
451 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
452}
453
6bb40dd1
ID		 454static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
455 struct rt2x00_intf *intf,
456 struct rt2x00intf_conf *conf,
457 const unsigned int flags)
95ea3627 458{
6bb40dd1 459 unsigned int bcn_preload;
95ea3627
ID		 460 u16 reg;
461
6bb40dd1 462 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 463 /*
464 * Enable beacon config
465 */
bad13639 466 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 467 rt2500usb_register_read(rt2x00dev, TXRX_CSR20, &reg);
468 rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6);
469 rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW,
05c914fe 470 2 * (conf->type != NL80211_IFTYPE_STATION));
6bb40dd1 471 rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
95ea3627 472
6bb40dd1
ID		 473 /*
474 * Enable synchronisation.
475 */
476 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
477 rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
478 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
479
480 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
6bb40dd1
ID		 481 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
482 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
483 }
95ea3627 484
6bb40dd1
ID		 485 if (flags & CONFIG_UPDATE_MAC)
486 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, conf->mac,
487 (3 * sizeof(__le16)));
488
489 if (flags & CONFIG_UPDATE_BSSID)
490 rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, conf->bssid,
491 (3 * sizeof(__le16)));
95ea3627
ID		 492}
493
3a643d24 494static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 495 struct rt2x00lib_erp *erp,
496 u32 changed)
95ea3627 497{
95ea3627 498 u16 reg;
95ea3627 499
02044643
HS		 500 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
501 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);
502 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
503 !!erp->short_preamble);
504 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
505 }
95ea3627 506
02044643
HS		 507 if (changed & BSS_CHANGED_BASIC_RATES)
508 rt2500usb_register_write(rt2x00dev, TXRX_CSR11,
509 erp->basic_rates);
95ea3627 510
02044643
HS		 511 if (changed & BSS_CHANGED_BEACON_INT) {
512 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
513 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,
514 erp->beacon_int * 4);
515 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
516 }
8a566afe 517
02044643
HS		 518 if (changed & BSS_CHANGED_ERP_SLOT) {
519 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
520 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
521 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
522 }
95ea3627
ID		 523}
524
e4ea1c40
ID		 525static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,
526 struct antenna_setup *ant)
95ea3627
ID		 527{
528 u8 r2;
529 u8 r14;
530 u16 csr5;
531 u16 csr6;
532
a4fe07d9
ID		 533 /*
534 * We should never come here because rt2x00lib is supposed
535 * to catch this and send us the correct antenna explicitely.
536 */
537 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
538 ant->tx == ANTENNA_SW_DIVERSITY);
539
95ea3627
ID		 540 rt2500usb_bbp_read(rt2x00dev, 2, &r2);
541 rt2500usb_bbp_read(rt2x00dev, 14, &r14);
542 rt2500usb_register_read(rt2x00dev, PHY_CSR5, &csr5);
543 rt2500usb_register_read(rt2x00dev, PHY_CSR6, &csr6);
544
545 /*
546 * Configure the TX antenna.
547 */
addc81bd 548 switch (ant->tx) {
95ea3627
ID		 549 case ANTENNA_HW_DIVERSITY:
550 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
551 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
552 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
553 break;
554 case ANTENNA_A:
555 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
556 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
557 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
558 break;
559 case ANTENNA_B:
a4fe07d9 560 default:
95ea3627
ID		 561 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
562 rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
563 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
564 break;
565 }
566
567 /*
568 * Configure the RX antenna.
569 */
addc81bd 570 switch (ant->rx) {
95ea3627
ID		 571 case ANTENNA_HW_DIVERSITY:
572 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
573 break;
574 case ANTENNA_A:
575 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
576 break;
577 case ANTENNA_B:
a4fe07d9 578 default:
95ea3627
ID		 579 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
580 break;
581 }
582
583 /*
584 * RT2525E and RT5222 need to flip TX I/Q
585 */
5122d898 586 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 587 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
588 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
589 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
590
591 /*
592 * RT2525E does not need RX I/Q Flip.
593 */
5122d898 594 if (rt2x00_rf(rt2x00dev, RF2525E))
95ea3627
ID		 595 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
596 } else {
597 rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
598 rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
599 }
600
601 rt2500usb_bbp_write(rt2x00dev, 2, r2);
602 rt2500usb_bbp_write(rt2x00dev, 14, r14);
603 rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
604 rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
605}
606
e4ea1c40
ID		 607static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
608 struct rf_channel *rf, const int txpower)
609{
610 /*
611 * Set TXpower.
612 */
613 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
614
615 /*
616 * For RT2525E we should first set the channel to half band higher.
617 */
5122d898 618 if (rt2x00_rf(rt2x00dev, RF2525E)) {
e4ea1c40
ID		 619 static const u32 vals[] = {
620 0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
621 0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
622 0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
623 0x00000902, 0x00000906
624 };
625
626 rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
627 if (rf->rf4)
628 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
629 }
630
631 rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
632 rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
633 rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
634 if (rf->rf4)
635 rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
636}
637
638static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
639 const int txpower)
640{
641 u32 rf3;
642
643 rt2x00_rf_read(rt2x00dev, 3, &rf3);
644 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
645 rt2500usb_rf_write(rt2x00dev, 3, rf3);
646}
647
7d7f19cc
ID		 648static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
649 struct rt2x00lib_conf *libconf)
650{
651 enum dev_state state =
652 (libconf->conf->flags & IEEE80211_CONF_PS) ?
653 STATE_SLEEP : STATE_AWAKE;
654 u16 reg;
655
656 if (state == STATE_SLEEP) {
657 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
658 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
6b347bff 659 rt2x00dev->beacon_int - 20);
7d7f19cc
ID		 660 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
661 libconf->conf->listen_interval - 1);
662
663 /* We must first disable autowake before it can be enabled */
664 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
665 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
666
667 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
668 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
5731858d
GW		 669 } else {
670 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
671 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
672 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
7d7f19cc
ID		 673 }
674
675 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
676}
677
95ea3627 678static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 679 struct rt2x00lib_conf *libconf,
680 const unsigned int flags)
95ea3627 681{
e4ea1c40 682 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 683 rt2500usb_config_channel(rt2x00dev, &libconf->rf,
684 libconf->conf->power_level);
e4ea1c40
ID		 685 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
686 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 687 rt2500usb_config_txpower(rt2x00dev,
688 libconf->conf->power_level);
7d7f19cc
ID		 689 if (flags & IEEE80211_CONF_CHANGE_PS)
690 rt2500usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 691}
692
95ea3627
ID		 693/*
694 * Link tuning
695 */
ebcf26da
ID		 696static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev,
697 struct link_qual *qual)
95ea3627
ID		 698{
699 u16 reg;
700
701 /*
702 * Update FCS error count from register.
703 */
704 rt2500usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 705 qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 706
707 /*
708 * Update False CCA count from register.
709 */
710 rt2500usb_register_read(rt2x00dev, STA_CSR3, &reg);
ebcf26da 711 qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
95ea3627
ID		 712}
713
5352ff65
ID		 714static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
715 struct link_qual *qual)
95ea3627
ID		 716{
717 u16 eeprom;
718 u16 value;
719
720 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &eeprom);
721 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
722 rt2500usb_bbp_write(rt2x00dev, 24, value);
723
724 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &eeprom);
725 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
726 rt2500usb_bbp_write(rt2x00dev, 25, value);
727
728 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &eeprom);
729 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
730 rt2500usb_bbp_write(rt2x00dev, 61, value);
731
732 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &eeprom);
733 value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
734 rt2500usb_bbp_write(rt2x00dev, 17, value);
735
5352ff65 736 qual->vgc_level = value;
95ea3627
ID		 737}
738
5450b7e2
ID		 739/*
740 * Queue handlers.
741 */
742static void rt2500usb_start_queue(struct data_queue *queue)
743{
744 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
745 u16 reg;
746
747 switch (queue->qid) {
748 case QID_RX:
749 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
750 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 0);
751 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
752 break;
753 case QID_BEACON:
754 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
755 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
756 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
757 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
758 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
759 break;
760 default:
761 break;
762 }
763}
764
765static void rt2500usb_stop_queue(struct data_queue *queue)
766{
767 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
768 u16 reg;
769
770 switch (queue->qid) {
771 case QID_RX:
772 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
773 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
774 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
775 break;
776 case QID_BEACON:
777 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
778 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
779 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
780 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
781 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
782 break;
783 default:
784 break;
785 }
5450b7e2
ID		 786}
787
95ea3627
ID		 788/*
789 * Initialization functions.
790 */
791static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
792{
793 u16 reg;
794
795 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
796 USB_MODE_TEST, REGISTER_TIMEOUT);
797 rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
798 0x00f0, REGISTER_TIMEOUT);
799
800 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
801 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
802 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
803
804 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
805 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
806
807 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
808 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
809 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
810 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
811 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
812
813 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
814 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
815 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
816 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
817 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
818
819 rt2500usb_register_read(rt2x00dev, TXRX_CSR5, &reg);
820 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
821 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
822 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
823 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
824 rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
825
826 rt2500usb_register_read(rt2x00dev, TXRX_CSR6, &reg);
827 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
828 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
829 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
830 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
831 rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
832
833 rt2500usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
834 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
835 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
836 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
837 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
838 rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
839
840 rt2500usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
841 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
842 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
843 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
844 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
845 rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
846
1f909162
ID		 847 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
848 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
849 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0);
850 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
851 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
852 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
853
95ea3627
ID		 854 rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
855 rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
856
857 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
858 return -EBUSY;
859
860 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
861 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
862 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
863 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
864 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
865
5122d898 866 if (rt2x00_rev(rt2x00dev) >= RT2570_VERSION_C) {
95ea3627 867 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg);
ddc827f9 868 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0);
95ea3627 869 } else {
ddc827f9
ID		 870 reg = 0;
871 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1);
872 rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3);
95ea3627
ID		 873 }
874 rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
875
876 rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
877 rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
878 rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
879 rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
880
881 rt2500usb_register_read(rt2x00dev, MAC_CSR8, &reg);
882 rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
883 rt2x00dev->rx->data_size);
884 rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
885
886 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
ac59b496 887 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, CIPHER_NONE);
95ea3627 888 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
dddfb478 889 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
95ea3627
ID		 890 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
891
892 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
893 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
894 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
895
896 rt2500usb_register_read(rt2x00dev, PHY_CSR4, &reg);
897 rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
898 rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
899
900 rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
901 rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
902 rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
903
904 return 0;
905}
906
2b08da3f 907static int rt2500usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 908{
909 unsigned int i;
95ea3627 910 u8 value;
95ea3627
ID		 911
912 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
913 rt2500usb_bbp_read(rt2x00dev, 0, &value);
914 if ((value != 0xff) && (value != 0x00))
2b08da3f 915 return 0;
95ea3627
ID		 916 udelay(REGISTER_BUSY_DELAY);
917 }
918
919 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
920 return -EACCES;
2b08da3f
ID		 921}
922
923static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
924{
925 unsigned int i;
926 u16 eeprom;
927 u8 value;
928 u8 reg_id;
929
930 if (unlikely(rt2500usb_wait_bbp_ready(rt2x00dev)))
931 return -EACCES;
95ea3627 932
95ea3627
ID		 933 rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
934 rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
935 rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
936 rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
937 rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
938 rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
939 rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
940 rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
941 rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
942 rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
943 rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
944 rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
945 rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
946 rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
947 rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
948 rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
949 rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
950 rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
951 rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
952 rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
953 rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
954 rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
955 rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
956 rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
957 rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
958 rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
959 rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
960 rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
961 rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
962 rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
963 rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
964
95ea3627
ID		 965 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
966 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
967
968 if (eeprom != 0xffff && eeprom != 0x0000) {
969 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
970 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 971 rt2500usb_bbp_write(rt2x00dev, reg_id, value);
972 }
973 }
95ea3627
ID		 974
975 return 0;
976}
977
978/*
979 * Device state switch handlers.
980 */
95ea3627
ID		 981static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
982{
983 /*
984 * Initialize all registers.
985 */
2b08da3f
ID		 986 if (unlikely(rt2500usb_init_registers(rt2x00dev) ||
987 rt2500usb_init_bbp(rt2x00dev)))
95ea3627 988 return -EIO;
95ea3627 989
95ea3627
ID		 990 return 0;
991}
992
993static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
994{
95ea3627
ID		 995 rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
996 rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
997
998 /*
999 * Disable synchronisation.
1000 */
1001 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
1002
1003 rt2x00usb_disable_radio(rt2x00dev);
1004}
1005
1006static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
1007 enum dev_state state)
1008{
1009 u16 reg;
1010 u16 reg2;
1011 unsigned int i;
1012 char put_to_sleep;
1013 char bbp_state;
1014 char rf_state;
1015
1016 put_to_sleep = (state != STATE_AWAKE);
1017
1018 reg = 0;
1019 rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
1020 rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
1021 rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
1022 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
1023 rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
1024 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
1025
1026 /*
1027 * Device is not guaranteed to be in the requested state yet.
1028 * We must wait until the register indicates that the
1029 * device has entered the correct state.
1030 */
1031 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1032 rt2500usb_register_read(rt2x00dev, MAC_CSR17, &reg2);
1033 bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
1034 rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
1035 if (bbp_state == state && rf_state == state)
1036 return 0;
1037 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
1038 msleep(30);
1039 }
1040
95ea3627
ID		 1041 return -EBUSY;
1042}
1043
1044static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1045 enum dev_state state)
1046{
1047 int retval = 0;
1048
1049 switch (state) {
1050 case STATE_RADIO_ON:
1051 retval = rt2500usb_enable_radio(rt2x00dev);
1052 break;
1053 case STATE_RADIO_OFF:
1054 rt2500usb_disable_radio(rt2x00dev);
1055 break;
2b08da3f
ID		 1056 case STATE_RADIO_IRQ_ON:
1057 case STATE_RADIO_IRQ_OFF:
1058 /* No support, but no error either */
95ea3627
ID		 1059 break;
1060 case STATE_DEEP_SLEEP:
1061 case STATE_SLEEP:
1062 case STATE_STANDBY:
1063 case STATE_AWAKE:
1064 retval = rt2500usb_set_state(rt2x00dev, state);
1065 break;
1066 default:
1067 retval = -ENOTSUPP;
1068 break;
1069 }
1070
2b08da3f
ID		 1071 if (unlikely(retval))
1072 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1073 state, retval);
1074
95ea3627
ID		 1075 return retval;
1076}
1077
1078/*
1079 * TX descriptor initialization
1080 */
93331458 1081static void rt2500usb_write_tx_desc(struct queue_entry *entry,
61486e0f 1082 struct txentry_desc *txdesc)
95ea3627 1083{
93331458
ID		 1084 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1085 __le32 *txd = (__le32 *) entry->skb->data;
95ea3627
ID		 1086 u32 word;
1087
1088 /*
1089 * Start writing the descriptor words.
1090 */
e01f1ec3
GW		 1091 rt2x00_desc_read(txd, 0, &word);
1092 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
1093 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1094 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1095 rt2x00_set_field32(&word, TXD_W0_ACK,
1096 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1097 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1098 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1099 rt2x00_set_field32(&word, TXD_W0_OFDM,
1100 (txdesc->rate_mode == RATE_MODE_OFDM));
1101 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1102 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
2517794b 1103 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
e01f1ec3
GW		 1104 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1105 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1106 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
1107 rt2x00_desc_write(txd, 0, word);
1108
95ea3627 1109 rt2x00_desc_read(txd, 1, &word);
dddfb478 1110 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
2b23cdaa
HS		 1111 rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
1112 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1113 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
95ea3627
ID		 1114 rt2x00_desc_write(txd, 1, word);
1115
1116 rt2x00_desc_read(txd, 2, &word);
26a1d07f
HS		 1117 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1118 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1119 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1120 txdesc->u.plcp.length_low);
1121 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1122 txdesc->u.plcp.length_high);
95ea3627
ID		 1123 rt2x00_desc_write(txd, 2, word);
1124
dddfb478
ID		 1125 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1126 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1127 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1128 }
1129
85b7a8b3
GW		 1130 /*
1131 * Register descriptor details in skb frame descriptor.
1132 */
0b8004aa 1133 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
85b7a8b3
GW		 1134 skbdesc->desc = txd;
1135 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1136}
1137
bd88a781
ID		 1138/*
1139 * TX data initialization
1140 */
1141static void rt2500usb_beacondone(struct urb *urb);
1142
f224f4ef
GW		 1143static void rt2500usb_write_beacon(struct queue_entry *entry,
1144 struct txentry_desc *txdesc)
bd88a781
ID		 1145{
1146 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1147 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1148 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
f1ca2167 1149 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
bd88a781 1150 int length;
d61cb266 1151 u16 reg, reg0;
bd88a781 1152
bd88a781
ID		 1153 /*
1154 * Disable beaconing while we are reloading the beacon data,
1155 * otherwise we might be sending out invalid data.
1156 */
1157 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
bd88a781
ID		 1158 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
1159 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1160
0b8004aa
GW		 1161 /*
1162 * Add space for the descriptor in front of the skb.
1163 */
1164 skb_push(entry->skb, TXD_DESC_SIZE);
1165 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1166
5c3b685c
GW		 1167 /*
1168 * Write the TX descriptor for the beacon.
1169 */
93331458 1170 rt2500usb_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1171
1172 /*
1173 * Dump beacon to userspace through debugfs.
1174 */
1175 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1176
bd88a781
ID		 1177 /*
1178 * USB devices cannot blindly pass the skb->len as the
1179 * length of the data to usb_fill_bulk_urb. Pass the skb
1180 * to the driver to determine what the length should be.
1181 */
f1ca2167 1182 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
bd88a781
ID		 1183
1184 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
1185 entry->skb->data, length, rt2500usb_beacondone,
1186 entry);
1187
1188 /*
1189 * Second we need to create the guardian byte.
1190 * We only need a single byte, so lets recycle
1191 * the 'flags' field we are not using for beacons.
1192 */
1193 bcn_priv->guardian_data = 0;
1194 usb_fill_bulk_urb(bcn_priv->guardian_urb, usb_dev, pipe,
1195 &bcn_priv->guardian_data, 1, rt2500usb_beacondone,
1196 entry);
1197
1198 /*
1199 * Send out the guardian byte.
1200 */
1201 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
d61cb266
GW		 1202
1203 /*
1204 * Enable beaconing again.
1205 */
1206 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1207 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
1208 reg0 = reg;
1209 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1210 /*
1211 * Beacon generation will fail initially.
1212 * To prevent this we need to change the TXRX_CSR19
1213 * register several times (reg0 is the same as reg
1214 * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
1215 * and 1 in reg).
1216 */
1217 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1218 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1219 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1220 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1221 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
bd88a781
ID		 1222}
1223
f1ca2167 1224static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1225{
1226 int length;
1227
1228 /*
1229 * The length _must_ be a multiple of 2,
1230 * but it must _not_ be a multiple of the USB packet size.
1231 */
f1ca2167
ID		 1232 length = roundup(entry->skb->len, 2);
1233 length += (2 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1234
1235 return length;
1236}
1237
95ea3627
ID		 1238/*
1239 * RX control handlers
1240 */
181d6902
ID		 1241static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1242 struct rxdone_entry_desc *rxdesc)
95ea3627 1243{
dddfb478 1244 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1245 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
181d6902
ID		 1246 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1247 __le32 *rxd =
1248 (__le32 *)(entry->skb->data +
b8be63ff
ID		 1249 (entry_priv->urb->actual_length -
1250 entry->queue->desc_size));
95ea3627
ID		 1251 u32 word0;
1252 u32 word1;
1253
f855c10b 1254 /*
a26cbc65
GW		 1255 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1256 * frame data in rt2x00usb.
f855c10b 1257 */
a26cbc65 1258 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1259 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1260
1261 /*
70a96109 1262 * It is now safe to read the descriptor on all architectures.
f855c10b 1263 */
95ea3627
ID		 1264 rt2x00_desc_read(rxd, 0, &word0);
1265 rt2x00_desc_read(rxd, 1, &word1);
1266
4150c572 1267 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1268 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1269 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1270 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1271
78b8f3b0
GW		 1272 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
1273 if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1274 rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
dddfb478
ID		 1275
1276 if (rxdesc->cipher != CIPHER_NONE) {
1277 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1278 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1279 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1280
dddfb478
ID		 1281 /* ICV is located at the end of frame */
1282
f3d340c1 1283 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
dddfb478
ID		 1284 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1285 rxdesc->flags |= RX_FLAG_DECRYPTED;
1286 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1287 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1288 }
1289
95ea3627
ID		 1290 /*
1291 * Obtain the status about this packet.
89993890
ID		 1292 * When frame was received with an OFDM bitrate,
1293 * the signal is the PLCP value. If it was received with
1294 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1295 */
181d6902 1296 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
dddfb478
ID		 1297 rxdesc->rssi =
1298 rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
181d6902 1299 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1300
19d30e02
ID		 1301 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1302 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1303 else
1304 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1305 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1306 rxdesc->dev_flags |= RXDONE_MY_BSS;
7d1de806 1307
2ae23854
MN		 1308 /*
1309 * Adjust the skb memory window to the frame boundaries.
1310 */
2ae23854 1311 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1312}
1313
1314/*
1315 * Interrupt functions.
1316 */
1317static void rt2500usb_beacondone(struct urb *urb)
1318{
181d6902 1319 struct queue_entry *entry = (struct queue_entry *)urb->context;
b8be63ff 1320 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
95ea3627 1321
0262ab0d 1322 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &entry->queue->rt2x00dev->flags))
95ea3627
ID		 1323 return;
1324
1325 /*
1326 * Check if this was the guardian beacon,
1327 * if that was the case we need to send the real beacon now.
1328 * Otherwise we should free the sk_buffer, the device
1329 * should be doing the rest of the work now.
1330 */
b8be63ff
ID		 1331 if (bcn_priv->guardian_urb == urb) {
1332 usb_submit_urb(bcn_priv->urb, GFP_ATOMIC);
1333 } else if (bcn_priv->urb == urb) {
181d6902
ID		 1334 dev_kfree_skb(entry->skb);
1335 entry->skb = NULL;
95ea3627
ID		 1336 }
1337}
1338
1339/*
1340 * Device probe functions.
1341 */
1342static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1343{
1344 u16 word;
1345 u8 *mac;
6bb40dd1 1346 u8 bbp;
95ea3627
ID		 1347
1348 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1349
1350 /*
1351 * Start validation of the data that has been read.
1352 */
1353 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1354 if (!is_valid_ether_addr(mac)) {
1355 random_ether_addr(mac);
e174961c 1356 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1357 }
1358
1359 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1360 if (word == 0xffff) {
1361 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1362 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1363 ANTENNA_SW_DIVERSITY);
1364 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1365 ANTENNA_SW_DIVERSITY);
1366 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1367 LED_MODE_DEFAULT);
95ea3627
ID		 1368 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1369 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1370 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1371 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1372 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1373 }
1374
1375 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1376 if (word == 0xffff) {
1377 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1378 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1379 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1380 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1381 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1382 }
1383
1384 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1385 if (word == 0xffff) {
1386 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1387 DEFAULT_RSSI_OFFSET);
1388 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1389 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1390 }
1391
1392 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &word);
1393 if (word == 0xffff) {
1394 rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
1395 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
1396 EEPROM(rt2x00dev, "BBPtune: 0x%04x\n", word);
1397 }
1398
6bb40dd1
ID		 1399 /*
1400 * Switch lower vgc bound to current BBP R17 value,
1401 * lower the value a bit for better quality.
1402 */
1403 rt2500usb_bbp_read(rt2x00dev, 17, &bbp);
1404 bbp -= 6;
1405
95ea3627
ID		 1406 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &word);
1407 if (word == 0xffff) {
1408 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
6bb40dd1 1409 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
95ea3627
ID		 1410 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
1411 EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
8d8acd46
ID		 1412 } else {
1413 rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp);
1414 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
95ea3627
ID		 1415 }
1416
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word);
1418 if (word == 0xffff) {
1419 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
1420 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
1421 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
1422 EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
1423 }
1424
1425 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word);
1426 if (word == 0xffff) {
1427 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
1428 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
1429 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
1430 EEPROM(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
1431 }
1432
1433 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &word);
1434 if (word == 0xffff) {
1435 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
1436 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
1437 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
1438 EEPROM(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
1439 }
1440
1441 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &word);
1442 if (word == 0xffff) {
1443 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
1444 rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
1445 rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
1446 EEPROM(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
1447 }
1448
1449 return 0;
1450}
1451
1452static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1453{
1454 u16 reg;
1455 u16 value;
1456 u16 eeprom;
1457
1458 /*
1459 * Read EEPROM word for configuration.
1460 */
1461 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1462
1463 /*
1464 * Identify RF chipset.
1465 */
1466 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1467 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1468 rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
1469
49e721ec 1470 if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) {
95ea3627
ID		 1471 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1472 return -ENODEV;
1473 }
1474
5122d898
GW		 1475 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1476 !rt2x00_rf(rt2x00dev, RF2523) &&
1477 !rt2x00_rf(rt2x00dev, RF2524) &&
1478 !rt2x00_rf(rt2x00dev, RF2525) &&
1479 !rt2x00_rf(rt2x00dev, RF2525E) &&
1480 !rt2x00_rf(rt2x00dev, RF5222)) {
95ea3627
ID		 1481 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1482 return -ENODEV;
1483 }
1484
1485 /*
1486 * Identify default antenna configuration.
1487 */
addc81bd 1488 rt2x00dev->default_ant.tx =
95ea3627 1489 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1490 rt2x00dev->default_ant.rx =
95ea3627
ID		 1491 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1492
addc81bd
ID		 1493 /*
1494 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1495 * I am not 100% sure about this, but the legacy drivers do not
1496 * indicate antenna swapping in software is required when
1497 * diversity is enabled.
1498 */
1499 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1500 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1501 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1502 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1503
95ea3627
ID		 1504 /*
1505 * Store led mode, for correct led behaviour.
1506 */
771fd565 1507#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1508 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1509
475433be 1510 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1511 if (value == LED_MODE_TXRX_ACTIVITY ||
1512 value == LED_MODE_DEFAULT ||
1513 value == LED_MODE_ASUS)
475433be
ID		 1514 rt2500usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1515 LED_TYPE_ACTIVITY);
771fd565 1516#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627 1517
7396faf4
ID		 1518 /*
1519 * Detect if this device has an hardware controlled radio.
1520 */
7396faf4 1521 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1522 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7396faf4 1523
95ea3627
ID		 1524 /*
1525 * Read the RSSI <-> dBm offset information.
1526 */
1527 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1528 rt2x00dev->rssi_offset =
1529 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1530
1531 return 0;
1532}
1533
1534/*
1535 * RF value list for RF2522
1536 * Supports: 2.4 GHz
1537 */
1538static const struct rf_channel rf_vals_bg_2522[] = {
1539 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1540 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1541 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1542 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1543 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1544 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1545 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1546 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1547 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1548 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1549 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1550 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1551 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1552 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1553};
1554
1555/*
1556 * RF value list for RF2523
1557 * Supports: 2.4 GHz
1558 */
1559static const struct rf_channel rf_vals_bg_2523[] = {
1560 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1561 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1562 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1563 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1564 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1565 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1566 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1567 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1568 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1569 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1570 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1571 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1572 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1573 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1574};
1575
1576/*
1577 * RF value list for RF2524
1578 * Supports: 2.4 GHz
1579 */
1580static const struct rf_channel rf_vals_bg_2524[] = {
1581 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1582 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1583 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1584 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1585 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1586 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1587 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1588 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1589 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1590 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1591 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1592 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1593 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1594 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1595};
1596
1597/*
1598 * RF value list for RF2525
1599 * Supports: 2.4 GHz
1600 */
1601static const struct rf_channel rf_vals_bg_2525[] = {
1602 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1603 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1604 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1605 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1606 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1607 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1608 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1609 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1610 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1611 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1612 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1613 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1614 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1615 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1616};
1617
1618/*
1619 * RF value list for RF2525e
1620 * Supports: 2.4 GHz
1621 */
1622static const struct rf_channel rf_vals_bg_2525e[] = {
1623 { 1, 0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
1624 { 2, 0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
1625 { 3, 0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
1626 { 4, 0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
1627 { 5, 0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
1628 { 6, 0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
1629 { 7, 0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
1630 { 8, 0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
1631 { 9, 0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
1632 { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
1633 { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
1634 { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
1635 { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
1636 { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
1637};
1638
1639/*
1640 * RF value list for RF5222
1641 * Supports: 2.4 GHz & 5.2 GHz
1642 */
1643static const struct rf_channel rf_vals_5222[] = {
1644 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1645 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1646 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1647 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1648 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1649 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1650 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1651 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1652 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1653 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1654 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1655 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1656 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1657 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1658
1659 /* 802.11 UNI / HyperLan 2 */
1660 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1661 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1662 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1663 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1664 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1665 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1666 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1667 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1668
1669 /* 802.11 HyperLan 2 */
1670 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1671 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1672 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1673 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1674 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1675 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1676 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1677 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1678 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1679 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1680
1681 /* 802.11 UNII */
1682 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1683 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1684 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1685 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1686 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1687};
1688
8c5e7a5f 1689static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1690{
1691 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1692 struct channel_info *info;
1693 char *tx_power;
95ea3627
ID		 1694 unsigned int i;
1695
1696 /*
1697 * Initialize all hw fields.
5a5b6ed6
HS		 1698 *
1699 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
1700 * capable of sending the buffered frames out after the DTIM
1701 * transmission using rt2x00lib_beacondone. This will send out
1702 * multicast and broadcast traffic immediately instead of buffering it
1703 * infinitly and thus dropping it after some time.
95ea3627
ID		 1704 */
1705 rt2x00dev->hw->flags =
95ea3627 1706 IEEE80211_HW_RX_INCLUDES_FCS |
4be8c387
JB		 1707 IEEE80211_HW_SIGNAL_DBM |
1708 IEEE80211_HW_SUPPORTS_PS |
1709 IEEE80211_HW_PS_NULLFUNC_STACK;
566bfe5a 1710
14a3bf89 1711 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1712 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1713 rt2x00_eeprom_addr(rt2x00dev,
1714 EEPROM_MAC_ADDR_0));
1715
95ea3627
ID		 1716 /*
1717 * Initialize hw_mode information.
1718 */
31562e80
ID		 1719 spec->supported_bands = SUPPORT_BAND_2GHZ;
1720 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1721
5122d898 1722 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1723 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1724 spec->channels = rf_vals_bg_2522;
5122d898 1725 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1726 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1727 spec->channels = rf_vals_bg_2523;
5122d898 1728 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1729 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1730 spec->channels = rf_vals_bg_2524;
5122d898 1731 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1732 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1733 spec->channels = rf_vals_bg_2525;
5122d898 1734 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1735 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1736 spec->channels = rf_vals_bg_2525e;
5122d898 1737 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1738 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1739 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1740 spec->channels = rf_vals_5222;
95ea3627 1741 }
8c5e7a5f
ID		 1742
1743 /*
1744 * Create channel information array
1745 */
baeb2ffa 1746 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1747 if (!info)
1748 return -ENOMEM;
1749
1750 spec->channels_info = info;
1751
1752 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1753 for (i = 0; i < 14; i++) {
1754 info[i].max_power = MAX_TXPOWER;
1755 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1756 }
8c5e7a5f
ID		 1757
1758 if (spec->num_channels > 14) {
8d1331b3
ID		 1759 for (i = 14; i < spec->num_channels; i++) {
1760 info[i].max_power = MAX_TXPOWER;
1761 info[i].default_power1 = DEFAULT_TXPOWER;
1762 }
8c5e7a5f
ID		 1763 }
1764
1765 return 0;
95ea3627
ID		 1766}
1767
1768static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1769{
1770 int retval;
1771
1772 /*
1773 * Allocate eeprom data.
1774 */
1775 retval = rt2500usb_validate_eeprom(rt2x00dev);
1776 if (retval)
1777 return retval;
1778
1779 retval = rt2500usb_init_eeprom(rt2x00dev);
1780 if (retval)
1781 return retval;
1782
1783 /*
1784 * Initialize hw specifications.
1785 */
8c5e7a5f
ID		 1786 retval = rt2500usb_probe_hw_mode(rt2x00dev);
1787 if (retval)
1788 return retval;
95ea3627
ID		 1789
1790 /*
181d6902 1791 * This device requires the atim queue
95ea3627 1792 */
7dab73b3
ID		 1793 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1794 __set_bit(REQUIRE_BEACON_GUARD, &rt2x00dev->cap_flags);
dddfb478 1795 if (!modparam_nohwcrypt) {
7dab73b3
ID		 1796 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
1797 __set_bit(REQUIRE_COPY_IV, &rt2x00dev->cap_flags);
dddfb478 1798 }
7dab73b3 1799 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1c0bcf89 1800 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
95ea3627
ID		 1801
1802 /*
1803 * Set the rssi offset.
1804 */
1805 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1806
1807 return 0;
1808}
1809
95ea3627
ID		 1810static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1811 .tx = rt2x00mac_tx,
4150c572
JB		 1812 .start = rt2x00mac_start,
1813 .stop = rt2x00mac_stop,
95ea3627
ID		 1814 .add_interface = rt2x00mac_add_interface,
1815 .remove_interface = rt2x00mac_remove_interface,
1816 .config = rt2x00mac_config,
3a643d24 1817 .configure_filter = rt2x00mac_configure_filter,
930c06f2 1818 .set_tim = rt2x00mac_set_tim,
dddfb478 1819 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 1820 .sw_scan_start = rt2x00mac_sw_scan_start,
1821 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1822 .get_stats = rt2x00mac_get_stats,
471b3efd 1823 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1824 .conf_tx = rt2x00mac_conf_tx,
e47a5cdd 1825 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1826 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 1827 .set_antenna = rt2x00mac_set_antenna,
1828 .get_antenna = rt2x00mac_get_antenna,
e7dee444 1829 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1830 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 1831};
1832
1833static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1834 .probe_hw = rt2500usb_probe_hw,
1835 .initialize = rt2x00usb_initialize,
1836 .uninitialize = rt2x00usb_uninitialize,
798b7adb 1837 .clear_entry = rt2x00usb_clear_entry,
95ea3627 1838 .set_device_state = rt2500usb_set_device_state,
7396faf4 1839 .rfkill_poll = rt2500usb_rfkill_poll,
95ea3627
ID		 1840 .link_stats = rt2500usb_link_stats,
1841 .reset_tuner = rt2500usb_reset_tuner,
c965c74b 1842 .watchdog = rt2x00usb_watchdog,
dbba306f
ID		 1843 .start_queue = rt2500usb_start_queue,
1844 .kick_queue = rt2x00usb_kick_queue,
1845 .stop_queue = rt2500usb_stop_queue,
5be65609 1846 .flush_queue = rt2x00usb_flush_queue,
95ea3627 1847 .write_tx_desc = rt2500usb_write_tx_desc,
bd88a781 1848 .write_beacon = rt2500usb_write_beacon,
dd9fa2d2 1849 .get_tx_data_len = rt2500usb_get_tx_data_len,
95ea3627 1850 .fill_rxdone = rt2500usb_fill_rxdone,
dddfb478
ID		 1851 .config_shared_key = rt2500usb_config_key,
1852 .config_pairwise_key = rt2500usb_config_key,
3a643d24 1853 .config_filter = rt2500usb_config_filter,
6bb40dd1 1854 .config_intf = rt2500usb_config_intf,
72810379 1855 .config_erp = rt2500usb_config_erp,
e4ea1c40 1856 .config_ant = rt2500usb_config_ant,
95ea3627
ID		 1857 .config = rt2500usb_config,
1858};
1859
181d6902 1860static const struct data_queue_desc rt2500usb_queue_rx = {
efd2f271 1861 .entry_num = 32,
181d6902
ID		 1862 .data_size = DATA_FRAME_SIZE,
1863 .desc_size = RXD_DESC_SIZE,
b8be63ff 1864 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1865};
1866
1867static const struct data_queue_desc rt2500usb_queue_tx = {
efd2f271 1868 .entry_num = 32,
181d6902
ID		 1869 .data_size = DATA_FRAME_SIZE,
1870 .desc_size = TXD_DESC_SIZE,
b8be63ff 1871 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1872};
1873
1874static const struct data_queue_desc rt2500usb_queue_bcn = {
efd2f271 1875 .entry_num = 1,
181d6902
ID		 1876 .data_size = MGMT_FRAME_SIZE,
1877 .desc_size = TXD_DESC_SIZE,
1878 .priv_size = sizeof(struct queue_entry_priv_usb_bcn),
1879};
1880
1881static const struct data_queue_desc rt2500usb_queue_atim = {
efd2f271 1882 .entry_num = 8,
181d6902
ID		 1883 .data_size = DATA_FRAME_SIZE,
1884 .desc_size = TXD_DESC_SIZE,
b8be63ff 1885 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 1886};
1887
95ea3627 1888static const struct rt2x00_ops rt2500usb_ops = {
04d0362e
GW		 1889 .name = KBUILD_MODNAME,
1890 .max_sta_intf = 1,
1891 .max_ap_intf = 1,
1892 .eeprom_size = EEPROM_SIZE,
1893 .rf_size = RF_SIZE,
1894 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1895 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 1896 .rx = &rt2500usb_queue_rx,
1897 .tx = &rt2500usb_queue_tx,
1898 .bcn = &rt2500usb_queue_bcn,
1899 .atim = &rt2500usb_queue_atim,
1900 .lib = &rt2500usb_rt2x00_ops,
1901 .hw = &rt2500usb_mac80211_ops,
95ea3627 1902#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1903 .debugfs = &rt2500usb_rt2x00debug,
95ea3627
ID		 1904#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1905};
1906
1907/*
1908 * rt2500usb module information.
1909 */
1910static struct usb_device_id rt2500usb_device_table[] = {
1911 /* ASUS */
e01ae27f
GW		 1912 { USB_DEVICE(0x0b05, 0x1706) },
1913 { USB_DEVICE(0x0b05, 0x1707) },
95ea3627 1914 /* Belkin */
e01ae27f
GW		 1915 { USB_DEVICE(0x050d, 0x7050) },
1916 { USB_DEVICE(0x050d, 0x7051) },
95ea3627 1917 /* Cisco Systems */
e01ae27f
GW		 1918 { USB_DEVICE(0x13b1, 0x000d) },
1919 { USB_DEVICE(0x13b1, 0x0011) },
1920 { USB_DEVICE(0x13b1, 0x001a) },
95ea3627 1921 /* Conceptronic */
e01ae27f 1922 { USB_DEVICE(0x14b2, 0x3c02) },
95ea3627 1923 /* D-LINK */
e01ae27f 1924 { USB_DEVICE(0x2001, 0x3c00) },
95ea3627 1925 /* Gigabyte */
e01ae27f
GW		 1926 { USB_DEVICE(0x1044, 0x8001) },
1927 { USB_DEVICE(0x1044, 0x8007) },
95ea3627 1928 /* Hercules */
e01ae27f 1929 { USB_DEVICE(0x06f8, 0xe000) },
95ea3627 1930 /* Melco */
e01ae27f
GW		 1931 { USB_DEVICE(0x0411, 0x005e) },
1932 { USB_DEVICE(0x0411, 0x0066) },
1933 { USB_DEVICE(0x0411, 0x0067) },
1934 { USB_DEVICE(0x0411, 0x008b) },
1935 { USB_DEVICE(0x0411, 0x0097) },
95ea3627 1936 /* MSI */
e01ae27f
GW		 1937 { USB_DEVICE(0x0db0, 0x6861) },
1938 { USB_DEVICE(0x0db0, 0x6865) },
1939 { USB_DEVICE(0x0db0, 0x6869) },
95ea3627 1940 /* Ralink */
e01ae27f
GW		 1941 { USB_DEVICE(0x148f, 0x1706) },
1942 { USB_DEVICE(0x148f, 0x2570) },
1943 { USB_DEVICE(0x148f, 0x9020) },
9eb77ab0 1944 /* Sagem */
e01ae27f 1945 { USB_DEVICE(0x079b, 0x004b) },
95ea3627 1946 /* Siemens */
e01ae27f 1947 { USB_DEVICE(0x0681, 0x3c06) },
95ea3627 1948 /* SMC */
e01ae27f 1949 { USB_DEVICE(0x0707, 0xee13) },
95ea3627 1950 /* Spairon */
e01ae27f 1951 { USB_DEVICE(0x114b, 0x0110) },
9eb77ab0 1952 /* SURECOM */
e01ae27f 1953 { USB_DEVICE(0x0769, 0x11f3) },
95ea3627 1954 /* Trust */
e01ae27f 1955 { USB_DEVICE(0x0eb0, 0x9020) },
9eb77ab0 1956 /* VTech */
e01ae27f 1957 { USB_DEVICE(0x0f88, 0x3012) },
95ea3627 1958 /* Zinwell */
e01ae27f 1959 { USB_DEVICE(0x5a57, 0x0260) },
95ea3627
ID		 1960 { 0, }
1961};
1962
1963MODULE_AUTHOR(DRV_PROJECT);
1964MODULE_VERSION(DRV_VERSION);
1965MODULE_DESCRIPTION("Ralink RT2500 USB Wireless LAN driver.");
1966MODULE_SUPPORTED_DEVICE("Ralink RT2570 USB chipset based cards");
1967MODULE_DEVICE_TABLE(usb, rt2500usb_device_table);
1968MODULE_LICENSE("GPL");
1969
e01ae27f
GW		 1970static int rt2500usb_probe(struct usb_interface *usb_intf,
1971 const struct usb_device_id *id)
1972{
1973 return rt2x00usb_probe(usb_intf, &rt2500usb_ops);
1974}
1975
95ea3627 1976static struct usb_driver rt2500usb_driver = {
2360157c 1977 .name = KBUILD_MODNAME,
95ea3627 1978 .id_table = rt2500usb_device_table,
e01ae27f 1979 .probe = rt2500usb_probe,
95ea3627
ID		 1980 .disconnect = rt2x00usb_disconnect,
1981 .suspend = rt2x00usb_suspend,
1982 .resume = rt2x00usb_resume,
1983};
1984
1985static int __init rt2500usb_init(void)
1986{
1987 return usb_register(&rt2500usb_driver);
1988}
1989
1990static void __exit rt2500usb_exit(void)
1991{
1992 usb_deregister(&rt2500usb_driver);
1993}
1994
1995module_init(rt2500usb_init);
1996module_exit(rt2500usb_exit);
Ubuntu Artful kernel mirror