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b54f78a8 | 1 | /* |
9c9a0d14 GW |
2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
3 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> | |
4 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
5 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
6 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
7 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
8 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
9 | Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> | |
b54f78a8 BZ |
10 | <http://rt2x00.serialmonkey.com> |
11 | ||
12 | This program is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
16 | ||
17 | This program is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with this program; if not, write to the | |
24 | Free Software Foundation, Inc., | |
25 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
26 | */ | |
27 | ||
28 | /* | |
29 | Module: rt2800 | |
30 | Abstract: Data structures and registers for the rt2800 modules. | |
31 | Supported chipsets: RT2800E, RT2800ED & RT2800U. | |
32 | */ | |
33 | ||
34 | #ifndef RT2800_H | |
35 | #define RT2800_H | |
36 | ||
37 | /* | |
38 | * RF chip defines. | |
39 | * | |
40 | * RF2820 2.4G 2T3R | |
41 | * RF2850 2.4G/5G 2T3R | |
42 | * RF2720 2.4G 1T2R | |
43 | * RF2750 2.4G/5G 1T2R | |
44 | * RF3020 2.4G 1T1R | |
45 | * RF2020 2.4G B/G | |
46 | * RF3021 2.4G 1T2R | |
47 | * RF3022 2.4G 2T2R | |
48 | * RF3052 2.4G 2T2R | |
49 | */ | |
50 | #define RF2820 0x0001 | |
51 | #define RF2850 0x0002 | |
52 | #define RF2720 0x0003 | |
53 | #define RF2750 0x0004 | |
54 | #define RF3020 0x0005 | |
55 | #define RF2020 0x0006 | |
56 | #define RF3021 0x0007 | |
57 | #define RF3022 0x0008 | |
58 | #define RF3052 0x0009 | |
fab799c3 | 59 | #define RF3320 0x000b |
b54f78a8 BZ |
60 | |
61 | /* | |
8d0c9b65 | 62 | * Chipset revisions. |
b54f78a8 | 63 | */ |
8d0c9b65 GW |
64 | #define REV_RT2860C 0x0100 |
65 | #define REV_RT2860D 0x0101 | |
8d0c9b65 GW |
66 | #define REV_RT2872E 0x0200 |
67 | #define REV_RT3070E 0x0200 | |
68 | #define REV_RT3070F 0x0201 | |
69 | #define REV_RT3071E 0x0211 | |
70 | #define REV_RT3090E 0x0211 | |
71 | #define REV_RT3390E 0x0211 | |
b54f78a8 BZ |
72 | |
73 | /* | |
74 | * Signal information. | |
75 | * Default offset is required for RSSI <-> dBm conversion. | |
76 | */ | |
74861922 | 77 | #define DEFAULT_RSSI_OFFSET 120 |
b54f78a8 BZ |
78 | |
79 | /* | |
80 | * Register layout information. | |
81 | */ | |
82 | #define CSR_REG_BASE 0x1000 | |
83 | #define CSR_REG_SIZE 0x0800 | |
84 | #define EEPROM_BASE 0x0000 | |
85 | #define EEPROM_SIZE 0x0110 | |
86 | #define BBP_BASE 0x0000 | |
87 | #define BBP_SIZE 0x0080 | |
88 | #define RF_BASE 0x0004 | |
89 | #define RF_SIZE 0x0010 | |
90 | ||
91 | /* | |
92 | * Number of TX queues. | |
93 | */ | |
94 | #define NUM_TX_QUEUES 4 | |
95 | ||
96 | /* | |
fab799c3 | 97 | * Registers. |
b54f78a8 BZ |
98 | */ |
99 | ||
785c3c06 GW |
100 | /* |
101 | * E2PROM_CSR: PCI EEPROM control register. | |
102 | * RELOAD: Write 1 to reload eeprom content. | |
103 | * TYPE: 0: 93c46, 1:93c66. | |
104 | * LOAD_STATUS: 1:loading, 0:done. | |
105 | */ | |
106 | #define E2PROM_CSR 0x0004 | |
107 | #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) | |
108 | #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) | |
109 | #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) | |
110 | #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) | |
111 | #define E2PROM_CSR_TYPE FIELD32(0x00000030) | |
112 | #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) | |
113 | #define E2PROM_CSR_RELOAD FIELD32(0x00000080) | |
114 | ||
fab799c3 GW |
115 | /* |
116 | * OPT_14: Unknown register used by rt3xxx devices. | |
117 | */ | |
118 | #define OPT_14_CSR 0x0114 | |
119 | #define OPT_14_CSR_BIT0 FIELD32(0x00000001) | |
120 | ||
b54f78a8 BZ |
121 | /* |
122 | * INT_SOURCE_CSR: Interrupt source register. | |
123 | * Write one to clear corresponding bit. | |
0bdab171 | 124 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO |
b54f78a8 BZ |
125 | */ |
126 | #define INT_SOURCE_CSR 0x0200 | |
127 | #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) | |
128 | #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) | |
129 | #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) | |
130 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
131 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
132 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
133 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
134 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
135 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
136 | #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) | |
137 | #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
138 | #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) | |
139 | #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) | |
140 | #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
141 | #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
142 | #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) | |
143 | #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) | |
144 | #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) | |
145 | ||
146 | /* | |
147 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | |
148 | */ | |
149 | #define INT_MASK_CSR 0x0204 | |
150 | #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) | |
151 | #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) | |
152 | #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) | |
153 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
154 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
155 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
156 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
157 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
158 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
159 | #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) | |
160 | #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
161 | #define INT_MASK_CSR_TBTT FIELD32(0x00000800) | |
162 | #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) | |
163 | #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
164 | #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
165 | #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) | |
166 | #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) | |
167 | #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) | |
168 | ||
169 | /* | |
170 | * WPDMA_GLO_CFG | |
171 | */ | |
172 | #define WPDMA_GLO_CFG 0x0208 | |
173 | #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) | |
174 | #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) | |
175 | #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) | |
176 | #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) | |
177 | #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) | |
178 | #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) | |
179 | #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) | |
180 | #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) | |
181 | #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) | |
182 | ||
183 | /* | |
184 | * WPDMA_RST_IDX | |
185 | */ | |
186 | #define WPDMA_RST_IDX 0x020c | |
187 | #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) | |
188 | #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) | |
189 | #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) | |
190 | #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) | |
191 | #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) | |
192 | #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) | |
193 | #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) | |
194 | ||
195 | /* | |
196 | * DELAY_INT_CFG | |
197 | */ | |
198 | #define DELAY_INT_CFG 0x0210 | |
199 | #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) | |
200 | #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) | |
201 | #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) | |
202 | #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) | |
203 | #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) | |
204 | #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) | |
205 | ||
206 | /* | |
207 | * WMM_AIFSN_CFG: Aifsn for each EDCA AC | |
208 | * AIFSN0: AC_BE | |
209 | * AIFSN1: AC_BK | |
a4385213 BZ |
210 | * AIFSN2: AC_VI |
211 | * AIFSN3: AC_VO | |
b54f78a8 BZ |
212 | */ |
213 | #define WMM_AIFSN_CFG 0x0214 | |
214 | #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) | |
215 | #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) | |
216 | #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) | |
217 | #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) | |
218 | ||
219 | /* | |
220 | * WMM_CWMIN_CSR: CWmin for each EDCA AC | |
221 | * CWMIN0: AC_BE | |
222 | * CWMIN1: AC_BK | |
a4385213 BZ |
223 | * CWMIN2: AC_VI |
224 | * CWMIN3: AC_VO | |
b54f78a8 BZ |
225 | */ |
226 | #define WMM_CWMIN_CFG 0x0218 | |
227 | #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) | |
228 | #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) | |
229 | #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) | |
230 | #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) | |
231 | ||
232 | /* | |
233 | * WMM_CWMAX_CSR: CWmax for each EDCA AC | |
234 | * CWMAX0: AC_BE | |
235 | * CWMAX1: AC_BK | |
a4385213 BZ |
236 | * CWMAX2: AC_VI |
237 | * CWMAX3: AC_VO | |
b54f78a8 BZ |
238 | */ |
239 | #define WMM_CWMAX_CFG 0x021c | |
240 | #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) | |
241 | #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) | |
242 | #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) | |
243 | #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) | |
244 | ||
245 | /* | |
246 | * AC_TXOP0: AC_BK/AC_BE TXOP register | |
247 | * AC0TXOP: AC_BK in unit of 32us | |
248 | * AC1TXOP: AC_BE in unit of 32us | |
249 | */ | |
250 | #define WMM_TXOP0_CFG 0x0220 | |
251 | #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) | |
252 | #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) | |
253 | ||
254 | /* | |
255 | * AC_TXOP1: AC_VO/AC_VI TXOP register | |
256 | * AC2TXOP: AC_VI in unit of 32us | |
257 | * AC3TXOP: AC_VO in unit of 32us | |
258 | */ | |
259 | #define WMM_TXOP1_CFG 0x0224 | |
260 | #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) | |
261 | #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) | |
262 | ||
263 | /* | |
264 | * GPIO_CTRL_CFG: | |
265 | */ | |
266 | #define GPIO_CTRL_CFG 0x0228 | |
267 | #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) | |
268 | #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) | |
269 | #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) | |
270 | #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) | |
271 | #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) | |
272 | #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) | |
273 | #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) | |
274 | #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) | |
275 | #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) | |
276 | ||
277 | /* | |
278 | * MCU_CMD_CFG | |
279 | */ | |
280 | #define MCU_CMD_CFG 0x022c | |
281 | ||
282 | /* | |
283 | * AC_BK register offsets | |
284 | */ | |
285 | #define TX_BASE_PTR0 0x0230 | |
286 | #define TX_MAX_CNT0 0x0234 | |
287 | #define TX_CTX_IDX0 0x0238 | |
288 | #define TX_DTX_IDX0 0x023c | |
289 | ||
290 | /* | |
291 | * AC_BE register offsets | |
292 | */ | |
293 | #define TX_BASE_PTR1 0x0240 | |
294 | #define TX_MAX_CNT1 0x0244 | |
295 | #define TX_CTX_IDX1 0x0248 | |
296 | #define TX_DTX_IDX1 0x024c | |
297 | ||
298 | /* | |
299 | * AC_VI register offsets | |
300 | */ | |
301 | #define TX_BASE_PTR2 0x0250 | |
302 | #define TX_MAX_CNT2 0x0254 | |
303 | #define TX_CTX_IDX2 0x0258 | |
304 | #define TX_DTX_IDX2 0x025c | |
305 | ||
306 | /* | |
307 | * AC_VO register offsets | |
308 | */ | |
309 | #define TX_BASE_PTR3 0x0260 | |
310 | #define TX_MAX_CNT3 0x0264 | |
311 | #define TX_CTX_IDX3 0x0268 | |
312 | #define TX_DTX_IDX3 0x026c | |
313 | ||
314 | /* | |
315 | * HCCA register offsets | |
316 | */ | |
317 | #define TX_BASE_PTR4 0x0270 | |
318 | #define TX_MAX_CNT4 0x0274 | |
319 | #define TX_CTX_IDX4 0x0278 | |
320 | #define TX_DTX_IDX4 0x027c | |
321 | ||
322 | /* | |
323 | * MGMT register offsets | |
324 | */ | |
325 | #define TX_BASE_PTR5 0x0280 | |
326 | #define TX_MAX_CNT5 0x0284 | |
327 | #define TX_CTX_IDX5 0x0288 | |
328 | #define TX_DTX_IDX5 0x028c | |
329 | ||
330 | /* | |
331 | * RX register offsets | |
332 | */ | |
333 | #define RX_BASE_PTR 0x0290 | |
334 | #define RX_MAX_CNT 0x0294 | |
335 | #define RX_CRX_IDX 0x0298 | |
336 | #define RX_DRX_IDX 0x029c | |
337 | ||
785c3c06 GW |
338 | /* |
339 | * USB_DMA_CFG | |
340 | * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. | |
341 | * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. | |
342 | * PHY_CLEAR: phy watch dog enable. | |
343 | * TX_CLEAR: Clear USB DMA TX path. | |
344 | * TXOP_HALT: Halt TXOP count down when TX buffer is full. | |
345 | * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. | |
346 | * RX_BULK_EN: Enable USB DMA Rx. | |
347 | * TX_BULK_EN: Enable USB DMA Tx. | |
348 | * EP_OUT_VALID: OUT endpoint data valid. | |
349 | * RX_BUSY: USB DMA RX FSM busy. | |
350 | * TX_BUSY: USB DMA TX FSM busy. | |
351 | */ | |
352 | #define USB_DMA_CFG 0x02a0 | |
353 | #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) | |
354 | #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) | |
355 | #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) | |
356 | #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) | |
357 | #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) | |
358 | #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) | |
359 | #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) | |
360 | #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) | |
361 | #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) | |
362 | #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) | |
363 | #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) | |
364 | ||
365 | /* | |
366 | * US_CYC_CNT | |
367 | */ | |
368 | #define US_CYC_CNT 0x02a4 | |
369 | #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) | |
370 | ||
b54f78a8 BZ |
371 | /* |
372 | * PBF_SYS_CTRL | |
373 | * HOST_RAM_WRITE: enable Host program ram write selection | |
374 | */ | |
375 | #define PBF_SYS_CTRL 0x0400 | |
376 | #define PBF_SYS_CTRL_READY FIELD32(0x00000080) | |
377 | #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) | |
378 | ||
379 | /* | |
380 | * HOST-MCU shared memory | |
381 | */ | |
382 | #define HOST_CMD_CSR 0x0404 | |
383 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) | |
384 | ||
385 | /* | |
386 | * PBF registers | |
387 | * Most are for debug. Driver doesn't touch PBF register. | |
388 | */ | |
389 | #define PBF_CFG 0x0408 | |
390 | #define PBF_MAX_PCNT 0x040c | |
391 | #define PBF_CTRL 0x0410 | |
392 | #define PBF_INT_STA 0x0414 | |
393 | #define PBF_INT_ENA 0x0418 | |
394 | ||
395 | /* | |
396 | * BCN_OFFSET0: | |
397 | */ | |
398 | #define BCN_OFFSET0 0x042c | |
399 | #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) | |
400 | #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) | |
401 | #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) | |
402 | #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) | |
403 | ||
404 | /* | |
405 | * BCN_OFFSET1: | |
406 | */ | |
407 | #define BCN_OFFSET1 0x0430 | |
408 | #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) | |
409 | #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) | |
410 | #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) | |
411 | #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) | |
412 | ||
413 | /* | |
414 | * PBF registers | |
415 | * Most are for debug. Driver doesn't touch PBF register. | |
416 | */ | |
417 | #define TXRXQ_PCNT 0x0438 | |
418 | #define PBF_DBG 0x043c | |
419 | ||
420 | /* | |
421 | * RF registers | |
422 | */ | |
423 | #define RF_CSR_CFG 0x0500 | |
424 | #define RF_CSR_CFG_DATA FIELD32(0x000000ff) | |
425 | #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) | |
426 | #define RF_CSR_CFG_WRITE FIELD32(0x00010000) | |
427 | #define RF_CSR_CFG_BUSY FIELD32(0x00020000) | |
428 | ||
30e84034 BZ |
429 | /* |
430 | * EFUSE_CSR: RT30x0 EEPROM | |
431 | */ | |
432 | #define EFUSE_CTRL 0x0580 | |
433 | #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) | |
434 | #define EFUSE_CTRL_MODE FIELD32(0x000000c0) | |
435 | #define EFUSE_CTRL_KICK FIELD32(0x40000000) | |
436 | #define EFUSE_CTRL_PRESENT FIELD32(0x80000000) | |
437 | ||
438 | /* | |
439 | * EFUSE_DATA0 | |
440 | */ | |
441 | #define EFUSE_DATA0 0x0590 | |
442 | ||
443 | /* | |
444 | * EFUSE_DATA1 | |
445 | */ | |
446 | #define EFUSE_DATA1 0x0594 | |
447 | ||
448 | /* | |
449 | * EFUSE_DATA2 | |
450 | */ | |
451 | #define EFUSE_DATA2 0x0598 | |
452 | ||
453 | /* | |
454 | * EFUSE_DATA3 | |
455 | */ | |
456 | #define EFUSE_DATA3 0x059c | |
457 | ||
fab799c3 GW |
458 | /* |
459 | * LDO_CFG0 | |
460 | */ | |
461 | #define LDO_CFG0 0x05d4 | |
462 | #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) | |
463 | #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) | |
464 | #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) | |
465 | #define LDO_CFG0_BGSEL FIELD32(0x03000000) | |
466 | #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) | |
467 | #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) | |
468 | #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) | |
469 | ||
470 | /* | |
471 | * GPIO_SWITCH | |
472 | */ | |
473 | #define GPIO_SWITCH 0x05dc | |
474 | #define GPIO_SWITCH_0 FIELD32(0x00000001) | |
475 | #define GPIO_SWITCH_1 FIELD32(0x00000002) | |
476 | #define GPIO_SWITCH_2 FIELD32(0x00000004) | |
477 | #define GPIO_SWITCH_3 FIELD32(0x00000008) | |
478 | #define GPIO_SWITCH_4 FIELD32(0x00000010) | |
479 | #define GPIO_SWITCH_5 FIELD32(0x00000020) | |
480 | #define GPIO_SWITCH_6 FIELD32(0x00000040) | |
481 | #define GPIO_SWITCH_7 FIELD32(0x00000080) | |
482 | ||
b54f78a8 BZ |
483 | /* |
484 | * MAC Control/Status Registers(CSR). | |
485 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
486 | */ | |
487 | ||
488 | /* | |
489 | * MAC_CSR0: ASIC revision number. | |
490 | * ASIC_REV: 0 | |
491 | * ASIC_VER: 2860 or 2870 | |
492 | */ | |
493 | #define MAC_CSR0 0x1000 | |
49e721ec GW |
494 | #define MAC_CSR0_REVISION FIELD32(0x0000ffff) |
495 | #define MAC_CSR0_CHIPSET FIELD32(0xffff0000) | |
b54f78a8 BZ |
496 | |
497 | /* | |
498 | * MAC_SYS_CTRL: | |
499 | */ | |
500 | #define MAC_SYS_CTRL 0x1004 | |
501 | #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) | |
502 | #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) | |
503 | #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) | |
504 | #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) | |
505 | #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) | |
506 | #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) | |
507 | #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) | |
508 | #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) | |
509 | ||
510 | /* | |
511 | * MAC_ADDR_DW0: STA MAC register 0 | |
512 | */ | |
513 | #define MAC_ADDR_DW0 0x1008 | |
514 | #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) | |
515 | #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) | |
516 | #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) | |
517 | #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) | |
518 | ||
519 | /* | |
520 | * MAC_ADDR_DW1: STA MAC register 1 | |
521 | * UNICAST_TO_ME_MASK: | |
522 | * Used to mask off bits from byte 5 of the MAC address | |
523 | * to determine the UNICAST_TO_ME bit for RX frames. | |
524 | * The full mask is complemented by BSS_ID_MASK: | |
525 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | |
526 | */ | |
527 | #define MAC_ADDR_DW1 0x100c | |
528 | #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) | |
529 | #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) | |
530 | #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | |
531 | ||
532 | /* | |
533 | * MAC_BSSID_DW0: BSSID register 0 | |
534 | */ | |
535 | #define MAC_BSSID_DW0 0x1010 | |
536 | #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) | |
537 | #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) | |
538 | #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) | |
539 | #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) | |
540 | ||
541 | /* | |
542 | * MAC_BSSID_DW1: BSSID register 1 | |
543 | * BSS_ID_MASK: | |
544 | * 0: 1-BSSID mode (BSS index = 0) | |
545 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | |
546 | * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | |
547 | * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) | |
548 | * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the | |
549 | * BSSID. This will make sure that those bits will be ignored | |
550 | * when determining the MY_BSS of RX frames. | |
551 | */ | |
552 | #define MAC_BSSID_DW1 0x1014 | |
553 | #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) | |
554 | #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) | |
555 | #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) | |
556 | #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) | |
557 | ||
558 | /* | |
559 | * MAX_LEN_CFG: Maximum frame length register. | |
560 | * MAX_MPDU: rt2860b max 16k bytes | |
561 | * MAX_PSDU: Maximum PSDU length | |
562 | * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 | |
563 | */ | |
564 | #define MAX_LEN_CFG 0x1018 | |
565 | #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) | |
566 | #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) | |
567 | #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) | |
568 | #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) | |
569 | ||
570 | /* | |
571 | * BBP_CSR_CFG: BBP serial control register | |
572 | * VALUE: Register value to program into BBP | |
573 | * REG_NUM: Selected BBP register | |
574 | * READ_CONTROL: 0 write BBP, 1 read BBP | |
575 | * BUSY: ASIC is busy executing BBP commands | |
576 | * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks | |
577 | * BBP_RW_MODE: 0 serial, 1 paralell | |
578 | */ | |
579 | #define BBP_CSR_CFG 0x101c | |
580 | #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) | |
581 | #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) | |
582 | #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) | |
583 | #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) | |
584 | #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) | |
585 | #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) | |
586 | ||
587 | /* | |
588 | * RF_CSR_CFG0: RF control register | |
589 | * REGID_AND_VALUE: Register value to program into RF | |
590 | * BITWIDTH: Selected RF register | |
591 | * STANDBYMODE: 0 high when standby, 1 low when standby | |
592 | * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate | |
593 | * BUSY: ASIC is busy executing RF commands | |
594 | */ | |
595 | #define RF_CSR_CFG0 0x1020 | |
596 | #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) | |
597 | #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) | |
598 | #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) | |
599 | #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) | |
600 | #define RF_CSR_CFG0_SEL FIELD32(0x40000000) | |
601 | #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) | |
602 | ||
603 | /* | |
604 | * RF_CSR_CFG1: RF control register | |
605 | * REGID_AND_VALUE: Register value to program into RF | |
606 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | |
607 | * 0: 3 system clock cycle (37.5usec) | |
608 | * 1: 5 system clock cycle (62.5usec) | |
609 | */ | |
610 | #define RF_CSR_CFG1 0x1024 | |
611 | #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) | |
612 | #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) | |
613 | ||
614 | /* | |
615 | * RF_CSR_CFG2: RF control register | |
616 | * VALUE: Register value to program into RF | |
b54f78a8 BZ |
617 | */ |
618 | #define RF_CSR_CFG2 0x1028 | |
619 | #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) | |
620 | ||
621 | /* | |
622 | * LED_CFG: LED control | |
623 | * color LED's: | |
624 | * 0: off | |
625 | * 1: blinking upon TX2 | |
626 | * 2: periodic slow blinking | |
627 | * 3: always on | |
628 | * LED polarity: | |
629 | * 0: active low | |
630 | * 1: active high | |
631 | */ | |
632 | #define LED_CFG 0x102c | |
633 | #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) | |
634 | #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) | |
635 | #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) | |
636 | #define LED_CFG_R_LED_MODE FIELD32(0x03000000) | |
637 | #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) | |
638 | #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) | |
639 | #define LED_CFG_LED_POLAR FIELD32(0x40000000) | |
640 | ||
641 | /* | |
642 | * XIFS_TIME_CFG: MAC timing | |
643 | * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX | |
644 | * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX | |
645 | * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX | |
646 | * when MAC doesn't reference BBP signal BBRXEND | |
647 | * EIFS: unit 1us | |
648 | * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer | |
649 | * | |
650 | */ | |
651 | #define XIFS_TIME_CFG 0x1100 | |
652 | #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) | |
653 | #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) | |
654 | #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) | |
655 | #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) | |
656 | #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) | |
657 | ||
658 | /* | |
659 | * BKOFF_SLOT_CFG: | |
660 | */ | |
661 | #define BKOFF_SLOT_CFG 0x1104 | |
662 | #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) | |
663 | #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) | |
664 | ||
665 | /* | |
666 | * NAV_TIME_CFG: | |
667 | */ | |
668 | #define NAV_TIME_CFG 0x1108 | |
669 | #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) | |
670 | #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) | |
671 | #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) | |
672 | #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) | |
673 | ||
674 | /* | |
675 | * CH_TIME_CFG: count as channel busy | |
676 | */ | |
677 | #define CH_TIME_CFG 0x110c | |
678 | ||
679 | /* | |
680 | * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us | |
681 | */ | |
682 | #define PBF_LIFE_TIMER 0x1110 | |
683 | ||
684 | /* | |
685 | * BCN_TIME_CFG: | |
686 | * BEACON_INTERVAL: in unit of 1/16 TU | |
687 | * TSF_TICKING: Enable TSF auto counting | |
688 | * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode | |
689 | * BEACON_GEN: Enable beacon generator | |
690 | */ | |
691 | #define BCN_TIME_CFG 0x1114 | |
692 | #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) | |
693 | #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) | |
694 | #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) | |
695 | #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) | |
696 | #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) | |
697 | #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) | |
698 | ||
699 | /* | |
700 | * TBTT_SYNC_CFG: | |
701 | */ | |
702 | #define TBTT_SYNC_CFG 0x1118 | |
703 | ||
704 | /* | |
705 | * TSF_TIMER_DW0: Local lsb TSF timer, read-only | |
706 | */ | |
707 | #define TSF_TIMER_DW0 0x111c | |
708 | #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) | |
709 | ||
710 | /* | |
711 | * TSF_TIMER_DW1: Local msb TSF timer, read-only | |
712 | */ | |
713 | #define TSF_TIMER_DW1 0x1120 | |
714 | #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) | |
715 | ||
716 | /* | |
717 | * TBTT_TIMER: TImer remains till next TBTT, read-only | |
718 | */ | |
719 | #define TBTT_TIMER 0x1124 | |
720 | ||
721 | /* | |
722 | * INT_TIMER_CFG: | |
723 | */ | |
724 | #define INT_TIMER_CFG 0x1128 | |
725 | ||
726 | /* | |
727 | * INT_TIMER_EN: GP-timer and pre-tbtt Int enable | |
728 | */ | |
729 | #define INT_TIMER_EN 0x112c | |
730 | ||
731 | /* | |
732 | * CH_IDLE_STA: channel idle time | |
733 | */ | |
734 | #define CH_IDLE_STA 0x1130 | |
735 | ||
736 | /* | |
737 | * CH_BUSY_STA: channel busy time | |
738 | */ | |
739 | #define CH_BUSY_STA 0x1134 | |
740 | ||
741 | /* | |
742 | * MAC_STATUS_CFG: | |
743 | * BBP_RF_BUSY: When set to 0, BBP and RF are stable. | |
744 | * if 1 or higher one of the 2 registers is busy. | |
745 | */ | |
746 | #define MAC_STATUS_CFG 0x1200 | |
747 | #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) | |
748 | ||
749 | /* | |
750 | * PWR_PIN_CFG: | |
751 | */ | |
752 | #define PWR_PIN_CFG 0x1204 | |
753 | ||
754 | /* | |
755 | * AUTOWAKEUP_CFG: Manual power control / status register | |
756 | * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set | |
757 | * AUTOWAKE: 0:sleep, 1:awake | |
758 | */ | |
759 | #define AUTOWAKEUP_CFG 0x1208 | |
760 | #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) | |
761 | #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) | |
762 | #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) | |
763 | ||
764 | /* | |
765 | * EDCA_AC0_CFG: | |
766 | */ | |
767 | #define EDCA_AC0_CFG 0x1300 | |
768 | #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) | |
769 | #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) | |
770 | #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) | |
771 | #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) | |
772 | ||
773 | /* | |
774 | * EDCA_AC1_CFG: | |
775 | */ | |
776 | #define EDCA_AC1_CFG 0x1304 | |
777 | #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) | |
778 | #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) | |
779 | #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) | |
780 | #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) | |
781 | ||
782 | /* | |
783 | * EDCA_AC2_CFG: | |
784 | */ | |
785 | #define EDCA_AC2_CFG 0x1308 | |
786 | #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) | |
787 | #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) | |
788 | #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) | |
789 | #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) | |
790 | ||
791 | /* | |
792 | * EDCA_AC3_CFG: | |
793 | */ | |
794 | #define EDCA_AC3_CFG 0x130c | |
795 | #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) | |
796 | #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) | |
797 | #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) | |
798 | #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) | |
799 | ||
800 | /* | |
801 | * EDCA_TID_AC_MAP: | |
802 | */ | |
803 | #define EDCA_TID_AC_MAP 0x1310 | |
804 | ||
5e846004 HS |
805 | /* |
806 | * TX_PWR_CFG: | |
807 | */ | |
808 | #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) | |
809 | #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) | |
810 | #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) | |
811 | #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) | |
812 | #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) | |
813 | #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) | |
814 | #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) | |
815 | #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) | |
816 | ||
b54f78a8 BZ |
817 | /* |
818 | * TX_PWR_CFG_0: | |
819 | */ | |
820 | #define TX_PWR_CFG_0 0x1314 | |
821 | #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) | |
822 | #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) | |
823 | #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) | |
824 | #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) | |
825 | #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) | |
826 | #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) | |
827 | #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) | |
828 | #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) | |
829 | ||
830 | /* | |
831 | * TX_PWR_CFG_1: | |
832 | */ | |
833 | #define TX_PWR_CFG_1 0x1318 | |
834 | #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) | |
835 | #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) | |
836 | #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) | |
837 | #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) | |
838 | #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) | |
839 | #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) | |
840 | #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) | |
841 | #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) | |
842 | ||
843 | /* | |
844 | * TX_PWR_CFG_2: | |
845 | */ | |
846 | #define TX_PWR_CFG_2 0x131c | |
847 | #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) | |
848 | #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) | |
849 | #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) | |
850 | #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) | |
851 | #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) | |
852 | #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) | |
853 | #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) | |
854 | #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) | |
855 | ||
856 | /* | |
857 | * TX_PWR_CFG_3: | |
858 | */ | |
859 | #define TX_PWR_CFG_3 0x1320 | |
860 | #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) | |
861 | #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) | |
862 | #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) | |
863 | #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) | |
864 | #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) | |
865 | #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) | |
866 | #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) | |
867 | #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) | |
868 | ||
869 | /* | |
870 | * TX_PWR_CFG_4: | |
871 | */ | |
872 | #define TX_PWR_CFG_4 0x1324 | |
873 | #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) | |
874 | #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) | |
875 | #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) | |
876 | #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) | |
877 | ||
878 | /* | |
879 | * TX_PIN_CFG: | |
880 | */ | |
881 | #define TX_PIN_CFG 0x1328 | |
882 | #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) | |
883 | #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) | |
884 | #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) | |
885 | #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) | |
886 | #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) | |
887 | #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) | |
888 | #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) | |
889 | #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) | |
890 | #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) | |
891 | #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) | |
892 | #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) | |
893 | #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) | |
894 | #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) | |
895 | #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) | |
896 | #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) | |
897 | #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) | |
898 | #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) | |
899 | #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) | |
900 | #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) | |
901 | #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) | |
902 | ||
903 | /* | |
904 | * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz | |
905 | */ | |
906 | #define TX_BAND_CFG 0x132c | |
a21ee724 | 907 | #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) |
b54f78a8 BZ |
908 | #define TX_BAND_CFG_A FIELD32(0x00000002) |
909 | #define TX_BAND_CFG_BG FIELD32(0x00000004) | |
910 | ||
911 | /* | |
912 | * TX_SW_CFG0: | |
913 | */ | |
914 | #define TX_SW_CFG0 0x1330 | |
915 | ||
916 | /* | |
917 | * TX_SW_CFG1: | |
918 | */ | |
919 | #define TX_SW_CFG1 0x1334 | |
920 | ||
921 | /* | |
922 | * TX_SW_CFG2: | |
923 | */ | |
924 | #define TX_SW_CFG2 0x1338 | |
925 | ||
926 | /* | |
927 | * TXOP_THRES_CFG: | |
928 | */ | |
929 | #define TXOP_THRES_CFG 0x133c | |
930 | ||
931 | /* | |
932 | * TXOP_CTRL_CFG: | |
933 | */ | |
934 | #define TXOP_CTRL_CFG 0x1340 | |
935 | ||
936 | /* | |
937 | * TX_RTS_CFG: | |
938 | * RTS_THRES: unit:byte | |
939 | * RTS_FBK_EN: enable rts rate fallback | |
940 | */ | |
941 | #define TX_RTS_CFG 0x1344 | |
942 | #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) | |
943 | #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) | |
944 | #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) | |
945 | ||
946 | /* | |
947 | * TX_TIMEOUT_CFG: | |
948 | * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us | |
949 | * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure | |
950 | * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. | |
951 | * it is recommended that: | |
952 | * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) | |
953 | */ | |
954 | #define TX_TIMEOUT_CFG 0x1348 | |
955 | #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) | |
956 | #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) | |
957 | #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) | |
958 | ||
959 | /* | |
960 | * TX_RTY_CFG: | |
961 | * SHORT_RTY_LIMIT: short retry limit | |
962 | * LONG_RTY_LIMIT: long retry limit | |
963 | * LONG_RTY_THRE: Long retry threshoold | |
964 | * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode | |
965 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
966 | * AGG_RTY_MODE: Aggregate MPDU retry mode | |
967 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
968 | * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable | |
969 | */ | |
970 | #define TX_RTY_CFG 0x134c | |
971 | #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) | |
972 | #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) | |
973 | #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) | |
974 | #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) | |
975 | #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) | |
976 | #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) | |
977 | ||
978 | /* | |
979 | * TX_LINK_CFG: | |
980 | * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us | |
981 | * MFB_ENABLE: TX apply remote MFB 1:enable | |
982 | * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable | |
983 | * 0: not apply remote remote unsolicit (MFS=7) | |
984 | * TX_MRQ_EN: MCS request TX enable | |
985 | * TX_RDG_EN: RDG TX enable | |
986 | * TX_CF_ACK_EN: Piggyback CF-ACK enable | |
987 | * REMOTE_MFB: remote MCS feedback | |
988 | * REMOTE_MFS: remote MCS feedback sequence number | |
989 | */ | |
990 | #define TX_LINK_CFG 0x1350 | |
991 | #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) | |
992 | #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) | |
993 | #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) | |
994 | #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) | |
995 | #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) | |
996 | #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) | |
997 | #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) | |
998 | #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) | |
999 | ||
1000 | /* | |
1001 | * HT_FBK_CFG0: | |
1002 | */ | |
1003 | #define HT_FBK_CFG0 0x1354 | |
1004 | #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) | |
1005 | #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) | |
1006 | #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) | |
1007 | #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) | |
1008 | #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) | |
1009 | #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) | |
1010 | #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) | |
1011 | #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) | |
1012 | ||
1013 | /* | |
1014 | * HT_FBK_CFG1: | |
1015 | */ | |
1016 | #define HT_FBK_CFG1 0x1358 | |
1017 | #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) | |
1018 | #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) | |
1019 | #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) | |
1020 | #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) | |
1021 | #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) | |
1022 | #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) | |
1023 | #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) | |
1024 | #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) | |
1025 | ||
1026 | /* | |
1027 | * LG_FBK_CFG0: | |
1028 | */ | |
1029 | #define LG_FBK_CFG0 0x135c | |
1030 | #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) | |
1031 | #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) | |
1032 | #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) | |
1033 | #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) | |
1034 | #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) | |
1035 | #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) | |
1036 | #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) | |
1037 | #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) | |
1038 | ||
1039 | /* | |
1040 | * LG_FBK_CFG1: | |
1041 | */ | |
1042 | #define LG_FBK_CFG1 0x1360 | |
1043 | #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) | |
1044 | #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) | |
1045 | #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) | |
1046 | #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) | |
1047 | ||
1048 | /* | |
1049 | * CCK_PROT_CFG: CCK Protection | |
1050 | * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) | |
1051 | * PROTECT_CTRL: Protection control frame type for CCK TX | |
1052 | * 0:none, 1:RTS/CTS, 2:CTS-to-self | |
1053 | * PROTECT_NAV: TXOP protection type for CCK TX | |
1054 | * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect | |
1055 | * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow | |
1056 | * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow | |
1057 | * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow | |
1058 | * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow | |
1059 | * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow | |
1060 | * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow | |
1061 | * RTS_TH_EN: RTS threshold enable on CCK TX | |
1062 | */ | |
1063 | #define CCK_PROT_CFG 0x1364 | |
1064 | #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1065 | #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1066 | #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1067 | #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1068 | #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1069 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1070 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1071 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1072 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1073 | #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1074 | ||
1075 | /* | |
1076 | * OFDM_PROT_CFG: OFDM Protection | |
1077 | */ | |
1078 | #define OFDM_PROT_CFG 0x1368 | |
1079 | #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1080 | #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1081 | #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1082 | #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1083 | #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1084 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1085 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1086 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1087 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1088 | #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1089 | ||
1090 | /* | |
1091 | * MM20_PROT_CFG: MM20 Protection | |
1092 | */ | |
1093 | #define MM20_PROT_CFG 0x136c | |
1094 | #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1095 | #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1096 | #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1097 | #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1098 | #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1099 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1100 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1101 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1102 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1103 | #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1104 | ||
1105 | /* | |
1106 | * MM40_PROT_CFG: MM40 Protection | |
1107 | */ | |
1108 | #define MM40_PROT_CFG 0x1370 | |
1109 | #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1110 | #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1111 | #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1112 | #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1113 | #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1114 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1115 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1116 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1117 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1118 | #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1119 | ||
1120 | /* | |
1121 | * GF20_PROT_CFG: GF20 Protection | |
1122 | */ | |
1123 | #define GF20_PROT_CFG 0x1374 | |
1124 | #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1125 | #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1126 | #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1127 | #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1128 | #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1129 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1130 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1131 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1132 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1133 | #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1134 | ||
1135 | /* | |
1136 | * GF40_PROT_CFG: GF40 Protection | |
1137 | */ | |
1138 | #define GF40_PROT_CFG 0x1378 | |
1139 | #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1140 | #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
1141 | #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
1142 | #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
1143 | #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1144 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1145 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1146 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1147 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1148 | #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1149 | ||
1150 | /* | |
1151 | * EXP_CTS_TIME: | |
1152 | */ | |
1153 | #define EXP_CTS_TIME 0x137c | |
1154 | ||
1155 | /* | |
1156 | * EXP_ACK_TIME: | |
1157 | */ | |
1158 | #define EXP_ACK_TIME 0x1380 | |
1159 | ||
1160 | /* | |
1161 | * RX_FILTER_CFG: RX configuration register. | |
1162 | */ | |
1163 | #define RX_FILTER_CFG 0x1400 | |
1164 | #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) | |
1165 | #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) | |
1166 | #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) | |
1167 | #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) | |
1168 | #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) | |
1169 | #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) | |
1170 | #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) | |
1171 | #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) | |
1172 | #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) | |
1173 | #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) | |
1174 | #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) | |
1175 | #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) | |
1176 | #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) | |
1177 | #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) | |
1178 | #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) | |
1179 | #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) | |
1180 | #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) | |
1181 | ||
1182 | /* | |
1183 | * AUTO_RSP_CFG: | |
1184 | * AUTORESPONDER: 0: disable, 1: enable | |
1185 | * BAC_ACK_POLICY: 0:long, 1:short preamble | |
1186 | * CTS_40_MMODE: Response CTS 40MHz duplicate mode | |
1187 | * CTS_40_MREF: Response CTS 40MHz duplicate mode | |
1188 | * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble | |
1189 | * DUAL_CTS_EN: Power bit value in control frame | |
1190 | * ACK_CTS_PSM_BIT:Power bit value in control frame | |
1191 | */ | |
1192 | #define AUTO_RSP_CFG 0x1404 | |
1193 | #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) | |
1194 | #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) | |
1195 | #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) | |
1196 | #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) | |
1197 | #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) | |
1198 | #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) | |
1199 | #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) | |
1200 | ||
1201 | /* | |
1202 | * LEGACY_BASIC_RATE: | |
1203 | */ | |
1204 | #define LEGACY_BASIC_RATE 0x1408 | |
1205 | ||
1206 | /* | |
1207 | * HT_BASIC_RATE: | |
1208 | */ | |
1209 | #define HT_BASIC_RATE 0x140c | |
1210 | ||
1211 | /* | |
1212 | * HT_CTRL_CFG: | |
1213 | */ | |
1214 | #define HT_CTRL_CFG 0x1410 | |
1215 | ||
1216 | /* | |
1217 | * SIFS_COST_CFG: | |
1218 | */ | |
1219 | #define SIFS_COST_CFG 0x1414 | |
1220 | ||
1221 | /* | |
1222 | * RX_PARSER_CFG: | |
1223 | * Set NAV for all received frames | |
1224 | */ | |
1225 | #define RX_PARSER_CFG 0x1418 | |
1226 | ||
1227 | /* | |
1228 | * TX_SEC_CNT0: | |
1229 | */ | |
1230 | #define TX_SEC_CNT0 0x1500 | |
1231 | ||
1232 | /* | |
1233 | * RX_SEC_CNT0: | |
1234 | */ | |
1235 | #define RX_SEC_CNT0 0x1504 | |
1236 | ||
1237 | /* | |
1238 | * CCMP_FC_MUTE: | |
1239 | */ | |
1240 | #define CCMP_FC_MUTE 0x1508 | |
1241 | ||
1242 | /* | |
1243 | * TXOP_HLDR_ADDR0: | |
1244 | */ | |
1245 | #define TXOP_HLDR_ADDR0 0x1600 | |
1246 | ||
1247 | /* | |
1248 | * TXOP_HLDR_ADDR1: | |
1249 | */ | |
1250 | #define TXOP_HLDR_ADDR1 0x1604 | |
1251 | ||
1252 | /* | |
1253 | * TXOP_HLDR_ET: | |
1254 | */ | |
1255 | #define TXOP_HLDR_ET 0x1608 | |
1256 | ||
1257 | /* | |
1258 | * QOS_CFPOLL_RA_DW0: | |
1259 | */ | |
1260 | #define QOS_CFPOLL_RA_DW0 0x160c | |
1261 | ||
1262 | /* | |
1263 | * QOS_CFPOLL_RA_DW1: | |
1264 | */ | |
1265 | #define QOS_CFPOLL_RA_DW1 0x1610 | |
1266 | ||
1267 | /* | |
1268 | * QOS_CFPOLL_QC: | |
1269 | */ | |
1270 | #define QOS_CFPOLL_QC 0x1614 | |
1271 | ||
1272 | /* | |
1273 | * RX_STA_CNT0: RX PLCP error count & RX CRC error count | |
1274 | */ | |
1275 | #define RX_STA_CNT0 0x1700 | |
1276 | #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) | |
1277 | #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) | |
1278 | ||
1279 | /* | |
1280 | * RX_STA_CNT1: RX False CCA count & RX LONG frame count | |
1281 | */ | |
1282 | #define RX_STA_CNT1 0x1704 | |
1283 | #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) | |
1284 | #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) | |
1285 | ||
1286 | /* | |
1287 | * RX_STA_CNT2: | |
1288 | */ | |
1289 | #define RX_STA_CNT2 0x1708 | |
1290 | #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) | |
1291 | #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) | |
1292 | ||
1293 | /* | |
1294 | * TX_STA_CNT0: TX Beacon count | |
1295 | */ | |
1296 | #define TX_STA_CNT0 0x170c | |
1297 | #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) | |
1298 | #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) | |
1299 | ||
1300 | /* | |
1301 | * TX_STA_CNT1: TX tx count | |
1302 | */ | |
1303 | #define TX_STA_CNT1 0x1710 | |
1304 | #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) | |
1305 | #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) | |
1306 | ||
1307 | /* | |
1308 | * TX_STA_CNT2: TX tx count | |
1309 | */ | |
1310 | #define TX_STA_CNT2 0x1714 | |
1311 | #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) | |
1312 | #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) | |
1313 | ||
1314 | /* | |
1315 | * TX_STA_FIFO: TX Result for specific PID status fifo register | |
1316 | */ | |
1317 | #define TX_STA_FIFO 0x1718 | |
1318 | #define TX_STA_FIFO_VALID FIELD32(0x00000001) | |
1319 | #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) | |
1320 | #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) | |
1321 | #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) | |
1322 | #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) | |
1323 | #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) | |
1324 | #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) | |
1325 | #define TX_STA_FIFO_MCS FIELD32(0x007f0000) | |
1326 | #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) | |
1327 | ||
1328 | /* | |
1329 | * TX_AGG_CNT: Debug counter | |
1330 | */ | |
1331 | #define TX_AGG_CNT 0x171c | |
1332 | #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) | |
1333 | #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) | |
1334 | ||
1335 | /* | |
1336 | * TX_AGG_CNT0: | |
1337 | */ | |
1338 | #define TX_AGG_CNT0 0x1720 | |
1339 | #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) | |
1340 | #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) | |
1341 | ||
1342 | /* | |
1343 | * TX_AGG_CNT1: | |
1344 | */ | |
1345 | #define TX_AGG_CNT1 0x1724 | |
1346 | #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) | |
1347 | #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) | |
1348 | ||
1349 | /* | |
1350 | * TX_AGG_CNT2: | |
1351 | */ | |
1352 | #define TX_AGG_CNT2 0x1728 | |
1353 | #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) | |
1354 | #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) | |
1355 | ||
1356 | /* | |
1357 | * TX_AGG_CNT3: | |
1358 | */ | |
1359 | #define TX_AGG_CNT3 0x172c | |
1360 | #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) | |
1361 | #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) | |
1362 | ||
1363 | /* | |
1364 | * TX_AGG_CNT4: | |
1365 | */ | |
1366 | #define TX_AGG_CNT4 0x1730 | |
1367 | #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) | |
1368 | #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) | |
1369 | ||
1370 | /* | |
1371 | * TX_AGG_CNT5: | |
1372 | */ | |
1373 | #define TX_AGG_CNT5 0x1734 | |
1374 | #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) | |
1375 | #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) | |
1376 | ||
1377 | /* | |
1378 | * TX_AGG_CNT6: | |
1379 | */ | |
1380 | #define TX_AGG_CNT6 0x1738 | |
1381 | #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) | |
1382 | #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) | |
1383 | ||
1384 | /* | |
1385 | * TX_AGG_CNT7: | |
1386 | */ | |
1387 | #define TX_AGG_CNT7 0x173c | |
1388 | #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) | |
1389 | #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) | |
1390 | ||
1391 | /* | |
1392 | * MPDU_DENSITY_CNT: | |
1393 | * TX_ZERO_DEL: TX zero length delimiter count | |
1394 | * RX_ZERO_DEL: RX zero length delimiter count | |
1395 | */ | |
1396 | #define MPDU_DENSITY_CNT 0x1740 | |
1397 | #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) | |
1398 | #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) | |
1399 | ||
1400 | /* | |
1401 | * Security key table memory. | |
1402 | * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry | |
1403 | * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry | |
1404 | * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry | |
1405 | * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry | |
a4385213 BZ |
1406 | * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry |
1407 | * SHARED_KEY_MODE_BASE: 4-byte * 16-entry | |
b54f78a8 BZ |
1408 | */ |
1409 | #define MAC_WCID_BASE 0x1800 | |
1410 | #define PAIRWISE_KEY_TABLE_BASE 0x4000 | |
1411 | #define MAC_IVEIV_TABLE_BASE 0x6000 | |
1412 | #define MAC_WCID_ATTRIBUTE_BASE 0x6800 | |
1413 | #define SHARED_KEY_TABLE_BASE 0x6c00 | |
1414 | #define SHARED_KEY_MODE_BASE 0x7000 | |
1415 | ||
1416 | #define MAC_WCID_ENTRY(__idx) \ | |
1417 | ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) ) | |
1418 | #define PAIRWISE_KEY_ENTRY(__idx) \ | |
1419 | ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | |
1420 | #define MAC_IVEIV_ENTRY(__idx) \ | |
7988436c | 1421 | ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) ) |
b54f78a8 BZ |
1422 | #define MAC_WCID_ATTR_ENTRY(__idx) \ |
1423 | ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) ) | |
1424 | #define SHARED_KEY_ENTRY(__idx) \ | |
1425 | ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | |
1426 | #define SHARED_KEY_MODE_ENTRY(__idx) \ | |
1427 | ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) ) | |
1428 | ||
1429 | struct mac_wcid_entry { | |
1430 | u8 mac[6]; | |
1431 | u8 reserved[2]; | |
1432 | } __attribute__ ((packed)); | |
1433 | ||
1434 | struct hw_key_entry { | |
1435 | u8 key[16]; | |
1436 | u8 tx_mic[8]; | |
1437 | u8 rx_mic[8]; | |
1438 | } __attribute__ ((packed)); | |
1439 | ||
1440 | struct mac_iveiv_entry { | |
1441 | u8 iv[8]; | |
1442 | } __attribute__ ((packed)); | |
1443 | ||
1444 | /* | |
1445 | * MAC_WCID_ATTRIBUTE: | |
1446 | */ | |
1447 | #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) | |
1448 | #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) | |
1449 | #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) | |
1450 | #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) | |
e4a0ab34 ID |
1451 | #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) |
1452 | #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) | |
1453 | #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) | |
1454 | #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) | |
b54f78a8 BZ |
1455 | |
1456 | /* | |
1457 | * SHARED_KEY_MODE: | |
1458 | */ | |
1459 | #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) | |
1460 | #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) | |
1461 | #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) | |
1462 | #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) | |
1463 | #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) | |
1464 | #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) | |
1465 | #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) | |
1466 | #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) | |
1467 | ||
1468 | /* | |
1469 | * HOST-MCU communication | |
1470 | */ | |
1471 | ||
1472 | /* | |
1473 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | |
1474 | */ | |
1475 | #define H2M_MAILBOX_CSR 0x7010 | |
1476 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | |
1477 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | |
1478 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | |
1479 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | |
1480 | ||
1481 | /* | |
1482 | * H2M_MAILBOX_CID: | |
1483 | */ | |
1484 | #define H2M_MAILBOX_CID 0x7014 | |
1485 | #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) | |
1486 | #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) | |
1487 | #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) | |
1488 | #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) | |
1489 | ||
1490 | /* | |
1491 | * H2M_MAILBOX_STATUS: | |
1492 | */ | |
1493 | #define H2M_MAILBOX_STATUS 0x701c | |
1494 | ||
1495 | /* | |
1496 | * H2M_INT_SRC: | |
1497 | */ | |
1498 | #define H2M_INT_SRC 0x7024 | |
1499 | ||
1500 | /* | |
1501 | * H2M_BBP_AGENT: | |
1502 | */ | |
1503 | #define H2M_BBP_AGENT 0x7028 | |
1504 | ||
1505 | /* | |
1506 | * MCU_LEDCS: LED control for MCU Mailbox. | |
1507 | */ | |
1508 | #define MCU_LEDCS_LED_MODE FIELD8(0x1f) | |
1509 | #define MCU_LEDCS_POLARITY FIELD8(0x01) | |
1510 | ||
1511 | /* | |
1512 | * HW_CS_CTS_BASE: | |
1513 | * Carrier-sense CTS frame base address. | |
1514 | * It's where mac stores carrier-sense frame for carrier-sense function. | |
1515 | */ | |
1516 | #define HW_CS_CTS_BASE 0x7700 | |
1517 | ||
1518 | /* | |
1519 | * HW_DFS_CTS_BASE: | |
a4385213 | 1520 | * DFS CTS frame base address. It's where mac stores CTS frame for DFS. |
b54f78a8 BZ |
1521 | */ |
1522 | #define HW_DFS_CTS_BASE 0x7780 | |
1523 | ||
1524 | /* | |
1525 | * TXRX control registers - base address 0x3000 | |
1526 | */ | |
1527 | ||
1528 | /* | |
1529 | * TXRX_CSR1: | |
1530 | * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. | |
1531 | */ | |
1532 | #define TXRX_CSR1 0x77d0 | |
1533 | ||
1534 | /* | |
1535 | * HW_DEBUG_SETTING_BASE: | |
1536 | * since NULL frame won't be that long (256 byte) | |
1537 | * We steal 16 tail bytes to save debugging settings | |
1538 | */ | |
1539 | #define HW_DEBUG_SETTING_BASE 0x77f0 | |
1540 | #define HW_DEBUG_SETTING_BASE2 0x7770 | |
1541 | ||
1542 | /* | |
1543 | * HW_BEACON_BASE | |
1544 | * In order to support maximum 8 MBSS and its maximum length | |
1545 | * is 512 bytes for each beacon | |
1546 | * Three section discontinue memory segments will be used. | |
1547 | * 1. The original region for BCN 0~3 | |
1548 | * 2. Extract memory from FCE table for BCN 4~5 | |
1549 | * 3. Extract memory from Pair-wise key table for BCN 6~7 | |
1550 | * It occupied those memory of wcid 238~253 for BCN 6 | |
1551 | * and wcid 222~237 for BCN 7 | |
1552 | * | |
1553 | * IMPORTANT NOTE: Not sure why legacy driver does this, | |
1554 | * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. | |
1555 | */ | |
1556 | #define HW_BEACON_BASE0 0x7800 | |
1557 | #define HW_BEACON_BASE1 0x7a00 | |
1558 | #define HW_BEACON_BASE2 0x7c00 | |
1559 | #define HW_BEACON_BASE3 0x7e00 | |
1560 | #define HW_BEACON_BASE4 0x7200 | |
1561 | #define HW_BEACON_BASE5 0x7400 | |
1562 | #define HW_BEACON_BASE6 0x5dc0 | |
1563 | #define HW_BEACON_BASE7 0x5bc0 | |
1564 | ||
1565 | #define HW_BEACON_OFFSET(__index) \ | |
1566 | ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \ | |
1567 | (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \ | |
1568 | (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) ) | |
1569 | ||
1570 | /* | |
1571 | * BBP registers. | |
1572 | * The wordsize of the BBP is 8 bits. | |
1573 | */ | |
1574 | ||
1575 | /* | |
52b58fac HS |
1576 | * BBP 1: TX Antenna & Power |
1577 | * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm, | |
1578 | * 3 - increase tx power by 6dBm | |
b54f78a8 BZ |
1579 | */ |
1580 | #define BBP1_TX_POWER FIELD8(0x07) | |
1581 | #define BBP1_TX_ANTENNA FIELD8(0x18) | |
1582 | ||
1583 | /* | |
1584 | * BBP 3: RX Antenna | |
1585 | */ | |
1586 | #define BBP3_RX_ANTENNA FIELD8(0x18) | |
a21ee724 | 1587 | #define BBP3_HT40_MINUS FIELD8(0x20) |
b54f78a8 BZ |
1588 | |
1589 | /* | |
1590 | * BBP 4: Bandwidth | |
1591 | */ | |
1592 | #define BBP4_TX_BF FIELD8(0x01) | |
1593 | #define BBP4_BANDWIDTH FIELD8(0x18) | |
1594 | ||
fab799c3 GW |
1595 | /* |
1596 | * BBP 138: Unknown | |
1597 | */ | |
1598 | #define BBP138_RX_ADC1 FIELD8(0x02) | |
1599 | #define BBP138_RX_ADC2 FIELD8(0x04) | |
1600 | #define BBP138_TX_DAC1 FIELD8(0x20) | |
1601 | #define BBP138_TX_DAC2 FIELD8(0x40) | |
1602 | ||
b54f78a8 BZ |
1603 | /* |
1604 | * RFCSR registers | |
1605 | * The wordsize of the RFCSR is 8 bits. | |
1606 | */ | |
1607 | ||
e148b4c8 GW |
1608 | /* |
1609 | * RFCSR 1: | |
1610 | */ | |
1611 | #define RFCSR1_RF_BLOCK_EN FIELD8(0x01) | |
1612 | #define RFCSR1_RX0_PD FIELD8(0x04) | |
1613 | #define RFCSR1_TX0_PD FIELD8(0x08) | |
1614 | #define RFCSR1_RX1_PD FIELD8(0x10) | |
1615 | #define RFCSR1_TX1_PD FIELD8(0x20) | |
1616 | ||
b54f78a8 BZ |
1617 | /* |
1618 | * RFCSR 6: | |
1619 | */ | |
fab799c3 GW |
1620 | #define RFCSR6_R1 FIELD8(0x03) |
1621 | #define RFCSR6_R2 FIELD8(0x40) | |
b54f78a8 BZ |
1622 | |
1623 | /* | |
1624 | * RFCSR 7: | |
1625 | */ | |
1626 | #define RFCSR7_RF_TUNING FIELD8(0x01) | |
1627 | ||
1628 | /* | |
1629 | * RFCSR 12: | |
1630 | */ | |
1631 | #define RFCSR12_TX_POWER FIELD8(0x1f) | |
1632 | ||
5a673964 HS |
1633 | /* |
1634 | * RFCSR 13: | |
1635 | */ | |
1636 | #define RFCSR13_TX_POWER FIELD8(0x1f) | |
1637 | ||
e148b4c8 GW |
1638 | /* |
1639 | * RFCSR 15: | |
1640 | */ | |
1641 | #define RFCSR15_TX_LO2_EN FIELD8(0x08) | |
1642 | ||
fab799c3 GW |
1643 | /* |
1644 | * RFCSR 17: | |
1645 | */ | |
e148b4c8 GW |
1646 | #define RFCSR17_TXMIXER_GAIN FIELD8(0x07) |
1647 | #define RFCSR17_TX_LO1_EN FIELD8(0x08) | |
1648 | #define RFCSR17_R FIELD8(0x20) | |
fab799c3 | 1649 | |
e148b4c8 GW |
1650 | /* |
1651 | * RFCSR 20: | |
1652 | */ | |
1653 | #define RFCSR20_RX_LO1_EN FIELD8(0x08) | |
1654 | ||
1655 | /* | |
1656 | * RFCSR 21: | |
1657 | */ | |
1658 | #define RFCSR21_RX_LO2_EN FIELD8(0x08) | |
fab799c3 | 1659 | |
b54f78a8 BZ |
1660 | /* |
1661 | * RFCSR 22: | |
1662 | */ | |
1663 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | |
1664 | ||
1665 | /* | |
1666 | * RFCSR 23: | |
1667 | */ | |
1668 | #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) | |
1669 | ||
e148b4c8 GW |
1670 | /* |
1671 | * RFCSR 27: | |
1672 | */ | |
1673 | #define RFCSR27_R1 FIELD8(0x03) | |
1674 | #define RFCSR27_R2 FIELD8(0x04) | |
1675 | #define RFCSR27_R3 FIELD8(0x30) | |
1676 | #define RFCSR27_R4 FIELD8(0x40) | |
1677 | ||
b54f78a8 BZ |
1678 | /* |
1679 | * RFCSR 30: | |
1680 | */ | |
1681 | #define RFCSR30_RF_CALIBRATION FIELD8(0x80) | |
1682 | ||
1683 | /* | |
1684 | * RF registers | |
1685 | */ | |
1686 | ||
1687 | /* | |
1688 | * RF 2 | |
1689 | */ | |
1690 | #define RF2_ANTENNA_RX2 FIELD32(0x00000040) | |
1691 | #define RF2_ANTENNA_TX1 FIELD32(0x00004000) | |
1692 | #define RF2_ANTENNA_RX1 FIELD32(0x00020000) | |
1693 | ||
1694 | /* | |
1695 | * RF 3 | |
1696 | */ | |
1697 | #define RF3_TXPOWER_G FIELD32(0x00003e00) | |
1698 | #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) | |
1699 | #define RF3_TXPOWER_A FIELD32(0x00003c00) | |
1700 | ||
1701 | /* | |
1702 | * RF 4 | |
1703 | */ | |
1704 | #define RF4_TXPOWER_G FIELD32(0x000007c0) | |
1705 | #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) | |
1706 | #define RF4_TXPOWER_A FIELD32(0x00000780) | |
1707 | #define RF4_FREQ_OFFSET FIELD32(0x001f8000) | |
1708 | #define RF4_HT40 FIELD32(0x00200000) | |
1709 | ||
1710 | /* | |
1711 | * EEPROM content. | |
1712 | * The wordsize of the EEPROM is 16 bits. | |
1713 | */ | |
1714 | ||
1715 | /* | |
1716 | * EEPROM Version | |
1717 | */ | |
1718 | #define EEPROM_VERSION 0x0001 | |
1719 | #define EEPROM_VERSION_FAE FIELD16(0x00ff) | |
1720 | #define EEPROM_VERSION_VERSION FIELD16(0xff00) | |
1721 | ||
1722 | /* | |
1723 | * HW MAC address. | |
1724 | */ | |
1725 | #define EEPROM_MAC_ADDR_0 0x0002 | |
1726 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
1727 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
1728 | #define EEPROM_MAC_ADDR_1 0x0003 | |
1729 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
1730 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
1731 | #define EEPROM_MAC_ADDR_2 0x0004 | |
1732 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
1733 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
1734 | ||
1735 | /* | |
1736 | * EEPROM ANTENNA config | |
1737 | * RXPATH: 1: 1R, 2: 2R, 3: 3R | |
1738 | * TXPATH: 1: 1T, 2: 2T | |
1739 | */ | |
1740 | #define EEPROM_ANTENNA 0x001a | |
1741 | #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f) | |
1742 | #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0) | |
1743 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00) | |
1744 | ||
1745 | /* | |
1746 | * EEPROM NIC config | |
1747 | * CARDBUS_ACCEL: 0 - enable, 1 - disable | |
1748 | */ | |
1749 | #define EEPROM_NIC 0x001b | |
1750 | #define EEPROM_NIC_HW_RADIO FIELD16(0x0001) | |
1751 | #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002) | |
1752 | #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004) | |
1753 | #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008) | |
1754 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010) | |
1755 | #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020) | |
1756 | #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040) | |
1757 | #define EEPROM_NIC_WPS_PBC FIELD16(0x0080) | |
1758 | #define EEPROM_NIC_BW40M_BG FIELD16(0x0100) | |
1759 | #define EEPROM_NIC_BW40M_A FIELD16(0x0200) | |
fab799c3 GW |
1760 | #define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800) |
1761 | #define EEPROM_NIC_DAC_TEST FIELD16(0x8000) | |
b54f78a8 BZ |
1762 | |
1763 | /* | |
1764 | * EEPROM frequency | |
1765 | */ | |
1766 | #define EEPROM_FREQ 0x001d | |
1767 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | |
1768 | #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) | |
1769 | #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) | |
1770 | ||
1771 | /* | |
1772 | * EEPROM LED | |
1773 | * POLARITY_RDY_G: Polarity RDY_G setting. | |
1774 | * POLARITY_RDY_A: Polarity RDY_A setting. | |
1775 | * POLARITY_ACT: Polarity ACT setting. | |
1776 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | |
1777 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | |
1778 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | |
1779 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | |
1780 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | |
1781 | * LED_MODE: Led mode. | |
1782 | */ | |
1783 | #define EEPROM_LED1 0x001e | |
1784 | #define EEPROM_LED2 0x001f | |
1785 | #define EEPROM_LED3 0x0020 | |
1786 | #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) | |
1787 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | |
1788 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | |
1789 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | |
1790 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | |
1791 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | |
1792 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | |
1793 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | |
1794 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | |
1795 | ||
1796 | /* | |
1797 | * EEPROM LNA | |
1798 | */ | |
1799 | #define EEPROM_LNA 0x0022 | |
1800 | #define EEPROM_LNA_BG FIELD16(0x00ff) | |
1801 | #define EEPROM_LNA_A0 FIELD16(0xff00) | |
1802 | ||
1803 | /* | |
1804 | * EEPROM RSSI BG offset | |
1805 | */ | |
1806 | #define EEPROM_RSSI_BG 0x0023 | |
1807 | #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) | |
1808 | #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) | |
1809 | ||
1810 | /* | |
1811 | * EEPROM RSSI BG2 offset | |
1812 | */ | |
1813 | #define EEPROM_RSSI_BG2 0x0024 | |
1814 | #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) | |
1815 | #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) | |
1816 | ||
e148b4c8 GW |
1817 | /* |
1818 | * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). | |
1819 | */ | |
1820 | #define EEPROM_TXMIXER_GAIN_BG 0x0024 | |
1821 | #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) | |
1822 | ||
b54f78a8 BZ |
1823 | /* |
1824 | * EEPROM RSSI A offset | |
1825 | */ | |
1826 | #define EEPROM_RSSI_A 0x0025 | |
1827 | #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) | |
1828 | #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) | |
1829 | ||
1830 | /* | |
1831 | * EEPROM RSSI A2 offset | |
1832 | */ | |
1833 | #define EEPROM_RSSI_A2 0x0026 | |
1834 | #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) | |
1835 | #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) | |
1836 | ||
1837 | /* | |
1838 | * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. | |
1839 | * This is delta in 40MHZ. | |
1840 | * VALUE: Tx Power dalta value (MAX=4) | |
1841 | * TYPE: 1: Plus the delta value, 0: minus the delta value | |
1842 | * TXPOWER: Enable: | |
1843 | */ | |
1844 | #define EEPROM_TXPOWER_DELTA 0x0028 | |
1845 | #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) | |
1846 | #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) | |
1847 | #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) | |
1848 | ||
1849 | /* | |
1850 | * EEPROM TXPOWER 802.11BG | |
1851 | */ | |
1852 | #define EEPROM_TXPOWER_BG1 0x0029 | |
1853 | #define EEPROM_TXPOWER_BG2 0x0030 | |
1854 | #define EEPROM_TXPOWER_BG_SIZE 7 | |
1855 | #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) | |
1856 | #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) | |
1857 | ||
1858 | /* | |
1859 | * EEPROM TXPOWER 802.11A | |
1860 | */ | |
1861 | #define EEPROM_TXPOWER_A1 0x003c | |
1862 | #define EEPROM_TXPOWER_A2 0x0053 | |
1863 | #define EEPROM_TXPOWER_A_SIZE 6 | |
1864 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | |
1865 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | |
1866 | ||
1867 | /* | |
5e846004 | 1868 | * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode |
b54f78a8 BZ |
1869 | */ |
1870 | #define EEPROM_TXPOWER_BYRATE 0x006f | |
5e846004 HS |
1871 | #define EEPROM_TXPOWER_BYRATE_SIZE 9 |
1872 | ||
1873 | #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) | |
1874 | #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) | |
1875 | #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) | |
1876 | #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) | |
b54f78a8 BZ |
1877 | |
1878 | /* | |
1879 | * EEPROM BBP. | |
1880 | */ | |
1881 | #define EEPROM_BBP_START 0x0078 | |
1882 | #define EEPROM_BBP_SIZE 16 | |
1883 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
1884 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
1885 | ||
1886 | /* | |
1887 | * MCU mailbox commands. | |
1888 | */ | |
1889 | #define MCU_SLEEP 0x30 | |
1890 | #define MCU_WAKEUP 0x31 | |
1891 | #define MCU_RADIO_OFF 0x35 | |
1892 | #define MCU_CURRENT 0x36 | |
1893 | #define MCU_LED 0x50 | |
1894 | #define MCU_LED_STRENGTH 0x51 | |
1895 | #define MCU_LED_1 0x52 | |
1896 | #define MCU_LED_2 0x53 | |
1897 | #define MCU_LED_3 0x54 | |
1898 | #define MCU_RADAR 0x60 | |
1899 | #define MCU_BOOT_SIGNAL 0x72 | |
1900 | #define MCU_BBP_SIGNAL 0x80 | |
1901 | #define MCU_POWER_SAVE 0x83 | |
1902 | ||
1903 | /* | |
1904 | * MCU mailbox tokens | |
1905 | */ | |
1906 | #define TOKEN_WAKUP 3 | |
1907 | ||
1908 | /* | |
1909 | * DMA descriptor defines. | |
1910 | */ | |
1911 | #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1912 | #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | |
1913 | ||
1914 | /* | |
1915 | * TX WI structure | |
1916 | */ | |
1917 | ||
1918 | /* | |
1919 | * Word0 | |
1920 | * FRAG: 1 To inform TKIP engine this is a fragment. | |
1921 | * MIMO_PS: The remote peer is in dynamic MIMO-PS mode | |
1922 | * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs | |
1923 | * BW: Channel bandwidth 20MHz or 40 MHz | |
1924 | * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED | |
1925 | */ | |
1926 | #define TXWI_W0_FRAG FIELD32(0x00000001) | |
1927 | #define TXWI_W0_MIMO_PS FIELD32(0x00000002) | |
1928 | #define TXWI_W0_CF_ACK FIELD32(0x00000004) | |
1929 | #define TXWI_W0_TS FIELD32(0x00000008) | |
1930 | #define TXWI_W0_AMPDU FIELD32(0x00000010) | |
1931 | #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) | |
1932 | #define TXWI_W0_TX_OP FIELD32(0x00000300) | |
1933 | #define TXWI_W0_MCS FIELD32(0x007f0000) | |
1934 | #define TXWI_W0_BW FIELD32(0x00800000) | |
1935 | #define TXWI_W0_SHORT_GI FIELD32(0x01000000) | |
1936 | #define TXWI_W0_STBC FIELD32(0x06000000) | |
1937 | #define TXWI_W0_IFS FIELD32(0x08000000) | |
1938 | #define TXWI_W0_PHYMODE FIELD32(0xc0000000) | |
1939 | ||
1940 | /* | |
1941 | * Word1 | |
1942 | */ | |
1943 | #define TXWI_W1_ACK FIELD32(0x00000001) | |
1944 | #define TXWI_W1_NSEQ FIELD32(0x00000002) | |
1945 | #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) | |
1946 | #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) | |
1947 | #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
1948 | #define TXWI_W1_PACKETID FIELD32(0xf0000000) | |
1949 | ||
1950 | /* | |
1951 | * Word2 | |
1952 | */ | |
1953 | #define TXWI_W2_IV FIELD32(0xffffffff) | |
1954 | ||
1955 | /* | |
1956 | * Word3 | |
1957 | */ | |
1958 | #define TXWI_W3_EIV FIELD32(0xffffffff) | |
1959 | ||
1960 | /* | |
1961 | * RX WI structure | |
1962 | */ | |
1963 | ||
1964 | /* | |
1965 | * Word0 | |
1966 | */ | |
1967 | #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) | |
1968 | #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) | |
1969 | #define RXWI_W0_BSSID FIELD32(0x00001c00) | |
1970 | #define RXWI_W0_UDF FIELD32(0x0000e000) | |
1971 | #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
1972 | #define RXWI_W0_TID FIELD32(0xf0000000) | |
1973 | ||
1974 | /* | |
1975 | * Word1 | |
1976 | */ | |
1977 | #define RXWI_W1_FRAG FIELD32(0x0000000f) | |
1978 | #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) | |
1979 | #define RXWI_W1_MCS FIELD32(0x007f0000) | |
1980 | #define RXWI_W1_BW FIELD32(0x00800000) | |
1981 | #define RXWI_W1_SHORT_GI FIELD32(0x01000000) | |
1982 | #define RXWI_W1_STBC FIELD32(0x06000000) | |
1983 | #define RXWI_W1_PHYMODE FIELD32(0xc0000000) | |
1984 | ||
1985 | /* | |
1986 | * Word2 | |
1987 | */ | |
1988 | #define RXWI_W2_RSSI0 FIELD32(0x000000ff) | |
1989 | #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) | |
1990 | #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) | |
1991 | ||
1992 | /* | |
1993 | * Word3 | |
1994 | */ | |
1995 | #define RXWI_W3_SNR0 FIELD32(0x000000ff) | |
1996 | #define RXWI_W3_SNR1 FIELD32(0x0000ff00) | |
1997 | ||
1998 | /* | |
1999 | * Macros for converting txpower from EEPROM to mac80211 value | |
2000 | * and from mac80211 value to register value. | |
2001 | */ | |
2002 | #define MIN_G_TXPOWER 0 | |
2003 | #define MIN_A_TXPOWER -7 | |
2004 | #define MAX_G_TXPOWER 31 | |
2005 | #define MAX_A_TXPOWER 15 | |
2006 | #define DEFAULT_TXPOWER 5 | |
2007 | ||
2008 | #define TXPOWER_G_FROM_DEV(__txpower) \ | |
2009 | ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
2010 | ||
2011 | #define TXPOWER_G_TO_DEV(__txpower) \ | |
2012 | clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) | |
2013 | ||
2014 | #define TXPOWER_A_FROM_DEV(__txpower) \ | |
2015 | ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
2016 | ||
2017 | #define TXPOWER_A_TO_DEV(__txpower) \ | |
2018 | clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) | |
2019 | ||
2020 | #endif /* RT2800_H */ |