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rt2x00: rt2800lib: introduce rt2800_eeprom_read_from_array helper
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
ec9c4989 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
3e38d3da
GJ		 224static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
225 const enum rt2800_eeprom_word word)
226{
227 return rt2x00_eeprom_addr(rt2x00dev, word);
228}
229
230static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
231 const enum rt2800_eeprom_word word, u16 *data)
232{
233 rt2x00_eeprom_read(rt2x00dev, word, data);
234}
235
236static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
237 const enum rt2800_eeprom_word word, u16 data)
238{
239 rt2x00_eeprom_write(rt2x00dev, word, data);
240}
241
022138ca
GJ		 242static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
243 const enum rt2800_eeprom_word array,
244 unsigned int offset,
245 u16 *data)
246{
247 rt2x00_eeprom_read(rt2x00dev, array + offset, data);
248}
249
16ebd608
WH		 250static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
251{
252 u32 reg;
253 int i, count;
254
255 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
256 if (rt2x00_get_field32(reg, WLAN_EN))
257 return 0;
258
259 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
260 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
261 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
262 rt2x00_set_field32(&reg, WLAN_EN, 1);
263 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
264
265 udelay(REGISTER_BUSY_DELAY);
266
267 count = 0;
268 do {
269 /*
270 * Check PLL_LD & XTAL_RDY.
271 */
272 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
273 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
274 if (rt2x00_get_field32(reg, PLL_LD) &&
275 rt2x00_get_field32(reg, XTAL_RDY))
276 break;
277 udelay(REGISTER_BUSY_DELAY);
278 }
279
280 if (i >= REGISTER_BUSY_COUNT) {
281
282 if (count >= 10)
283 return -EIO;
284
285 rt2800_register_write(rt2x00dev, 0x58, 0x018);
286 udelay(REGISTER_BUSY_DELAY);
287 rt2800_register_write(rt2x00dev, 0x58, 0x418);
288 udelay(REGISTER_BUSY_DELAY);
289 rt2800_register_write(rt2x00dev, 0x58, 0x618);
290 udelay(REGISTER_BUSY_DELAY);
291 count++;
292 } else {
293 count = 0;
294 }
295
296 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
297 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
298 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
299 rt2x00_set_field32(&reg, WLAN_RESET, 1);
300 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
301 udelay(10);
302 rt2x00_set_field32(&reg, WLAN_RESET, 0);
303 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
304 udelay(10);
305 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
306 } while (count != 0);
307
308 return 0;
309}
310
89297425
BZ		 311void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
312 const u8 command, const u8 token,
313 const u8 arg0, const u8 arg1)
314{
315 u32 reg;
316
ee303e54 317 /*
cea90e55 318 * SOC devices don't support MCU requests.
ee303e54 319 */
cea90e55 320 if (rt2x00_is_soc(rt2x00dev))
ee303e54 321 return;
89297425
BZ		 322
323 mutex_lock(&rt2x00dev->csr_mutex);
324
325 /*
326 * Wait until the MCU becomes available, afterwards we
327 * can safely write the new data into the register.
328 */
329 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
330 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
331 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
332 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
333 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
334 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
335
336 reg = 0;
337 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
338 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
339 }
340
341 mutex_unlock(&rt2x00dev->csr_mutex);
342}
343EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 344
5ffddc49
ID		 345int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
346{
347 unsigned int i = 0;
348 u32 reg;
349
350 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
351 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
352 if (reg && reg != ~0)
353 return 0;
354 msleep(1);
355 }
356
ec9c4989 357 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 358 return -EBUSY;
359}
360EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
361
67a4c1e2
GW		 362int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
363{
364 unsigned int i;
365 u32 reg;
366
08e53100
HS		 367 /*
368 * Some devices are really slow to respond here. Wait a whole second
369 * before timing out.
370 */
67a4c1e2
GW		 371 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
372 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
373 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
374 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
375 return 0;
376
08e53100 377 msleep(10);
67a4c1e2
GW		 378 }
379
ec9c4989 380 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 381 return -EACCES;
382}
383EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
384
f7b395e9
JK		 385void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
386{
387 u32 reg;
388
389 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
390 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
391 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
395 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
396}
397EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
398
f31c9a8c
ID		 399static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
400{
401 u16 fw_crc;
402 u16 crc;
403
404 /*
405 * The last 2 bytes in the firmware array are the crc checksum itself,
406 * this means that we should never pass those 2 bytes to the crc
407 * algorithm.
408 */
409 fw_crc = (data[len - 2] << 8 | data[len - 1]);
410
411 /*
412 * Use the crc ccitt algorithm.
413 * This will return the same value as the legacy driver which
414 * used bit ordering reversion on the both the firmware bytes
415 * before input input as well as on the final output.
416 * Obviously using crc ccitt directly is much more efficient.
417 */
418 crc = crc_ccitt(~0, data, len - 2);
419
420 /*
421 * There is a small difference between the crc-itu-t + bitrev and
422 * the crc-ccitt crc calculation. In the latter method the 2 bytes
423 * will be swapped, use swab16 to convert the crc to the correct
424 * value.
425 */
426 crc = swab16(crc);
427
428 return fw_crc == crc;
429}
430
431int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
432 const u8 *data, const size_t len)
433{
434 size_t offset = 0;
435 size_t fw_len;
436 bool multiple;
437
438 /*
439 * PCI(e) & SOC devices require firmware with a length
440 * of 8kb. USB devices require firmware files with a length
441 * of 4kb. Certain USB chipsets however require different firmware,
442 * which Ralink only provides attached to the original firmware
443 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 444 * which is a multiple of 4kb. The firmware for rt3290 chip also
445 * have a length which is a multiple of 4kb.
f31c9a8c 446 */
a89534ed 447 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 448 fw_len = 4096;
a89534ed 449 else
f31c9a8c 450 fw_len = 8192;
f31c9a8c 451
a89534ed 452 multiple = true;
f31c9a8c
ID		 453 /*
454 * Validate the firmware length
455 */
456 if (len != fw_len && (!multiple || (len % fw_len) != 0))
457 return FW_BAD_LENGTH;
458
459 /*
460 * Check if the chipset requires one of the upper parts
461 * of the firmware.
462 */
463 if (rt2x00_is_usb(rt2x00dev) &&
464 !rt2x00_rt(rt2x00dev, RT2860) &&
465 !rt2x00_rt(rt2x00dev, RT2872) &&
466 !rt2x00_rt(rt2x00dev, RT3070) &&
467 ((len / fw_len) == 1))
468 return FW_BAD_VERSION;
469
470 /*
471 * 8kb firmware files must be checked as if it were
472 * 2 separate firmware files.
473 */
474 while (offset < len) {
475 if (!rt2800_check_firmware_crc(data + offset, fw_len))
476 return FW_BAD_CRC;
477
478 offset += fw_len;
479 }
480
481 return FW_OK;
482}
483EXPORT_SYMBOL_GPL(rt2800_check_firmware);
484
485int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
486 const u8 *data, const size_t len)
487{
488 unsigned int i;
489 u32 reg;
16ebd608
WH		 490 int retval;
491
492 if (rt2x00_rt(rt2x00dev, RT3290)) {
493 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
494 if (retval)
495 return -EBUSY;
496 }
f31c9a8c
ID		 497
498 /*
b9eca242
ID		 499 * If driver doesn't wake up firmware here,
500 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 501 */
b9eca242 502 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 503
f31c9a8c
ID		 504 /*
505 * Wait for stable hardware.
506 */
5ffddc49 507 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 508 return -EBUSY;
f31c9a8c 509
adde5882 510 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 511 if (rt2x00_rt(rt2x00dev, RT3290) ||
512 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 513 rt2x00_rt(rt2x00dev, RT5390) ||
514 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 515 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
516 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
517 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
518 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
519 }
f31c9a8c 520 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 521 }
f31c9a8c 522
b7e1d225
JK		 523 rt2800_disable_wpdma(rt2x00dev);
524
f31c9a8c
ID		 525 /*
526 * Write firmware to the device.
527 */
528 rt2800_drv_write_firmware(rt2x00dev, data, len);
529
530 /*
531 * Wait for device to stabilize.
532 */
533 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
534 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
535 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
536 break;
537 msleep(1);
538 }
539
540 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 541 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 542 return -EBUSY;
543 }
544
4ed1dd2a
SG		 545 /*
546 * Disable DMA, will be reenabled later when enabling
547 * the radio.
548 */
f7b395e9 549 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 550
f31c9a8c
ID		 551 /*
552 * Initialize firmware.
553 */
554 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
555 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 556 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 557 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 558 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
559 }
f31c9a8c
ID		 560 msleep(1);
561
562 return 0;
563}
564EXPORT_SYMBOL_GPL(rt2800_load_firmware);
565
0c5879bc
ID		 566void rt2800_write_tx_data(struct queue_entry *entry,
567 struct txentry_desc *txdesc)
59679b91 568{
0c5879bc 569 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 570 u32 word;
557985ae 571 int i;
59679b91
GW		 572
573 /*
574 * Initialize TX Info descriptor
575 */
576 rt2x00_desc_read(txwi, 0, &word);
577 rt2x00_set_field32(&word, TXWI_W0_FRAG,
578 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 579 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
580 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 581 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
582 rt2x00_set_field32(&word, TXWI_W0_TS,
583 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
584 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
585 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 586 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
587 txdesc->u.ht.mpdu_density);
588 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
589 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 590 rt2x00_set_field32(&word, TXWI_W0_BW,
591 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
592 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
593 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 594 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 595 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
596 rt2x00_desc_write(txwi, 0, word);
597
598 rt2x00_desc_read(txwi, 1, &word);
599 rt2x00_set_field32(&word, TXWI_W1_ACK,
600 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
601 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
602 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 603 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 604 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
605 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 606 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 607 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
608 txdesc->length);
2b23cdaa 609 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 610 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 611 rt2x00_desc_write(txwi, 1, word);
612
613 /*
557985ae
SG		 614 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
615 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 616 * When TXD_W3_WIV is set to 1 it will use the IV data
617 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
618 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 619 *
620 * Nulify all remaining words as well, we don't know how to program them.
59679b91 621 */
557985ae
SG		 622 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
623 _rt2x00_desc_write(txwi, i, 0);
59679b91 624}
0c5879bc 625EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 626
ff6133be 627static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 628{
7fc41755
LT		 629 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
630 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
631 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 632 u16 eeprom;
633 u8 offset0;
634 u8 offset1;
635 u8 offset2;
636
e5ef5bad 637 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 638 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 639 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
640 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 641 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 642 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
643 } else {
3e38d3da 644 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 645 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
646 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 647 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 648 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
649 }
650
651 /*
652 * Convert the value from the descriptor into the RSSI value
653 * If the value in the descriptor is 0, it is considered invalid
654 * and the default (extremely low) rssi value is assumed
655 */
656 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
657 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
658 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
659
660 /*
661 * mac80211 only accepts a single RSSI value. Calculating the
662 * average doesn't deliver a fair answer either since -60:-60 would
663 * be considered equally good as -50:-70 while the second is the one
664 * which gives less energy...
665 */
666 rssi0 = max(rssi0, rssi1);
7fc41755 667 return (int)max(rssi0, rssi2);
74861922
ID		 668}
669
670void rt2800_process_rxwi(struct queue_entry *entry,
671 struct rxdone_entry_desc *rxdesc)
672{
673 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 674 u32 word;
675
676 rt2x00_desc_read(rxwi, 0, &word);
677
678 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
679 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
680
681 rt2x00_desc_read(rxwi, 1, &word);
682
683 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
684 rxdesc->flags |= RX_FLAG_SHORT_GI;
685
686 if (rt2x00_get_field32(word, RXWI_W1_BW))
687 rxdesc->flags |= RX_FLAG_40MHZ;
688
689 /*
690 * Detect RX rate, always use MCS as signal type.
691 */
692 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
693 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
694 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
695
696 /*
697 * Mask of 0x8 bit to remove the short preamble flag.
698 */
699 if (rxdesc->rate_mode == RATE_MODE_CCK)
700 rxdesc->signal &= ~0x8;
701
702 rt2x00_desc_read(rxwi, 2, &word);
703
74861922
ID		 704 /*
705 * Convert descriptor AGC value to RSSI value.
706 */
707 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 708 /*
709 * Remove RXWI descriptor from start of the buffer.
710 */
711 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 712}
713EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
714
31937c42 715void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 716{
717 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 718 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 719 struct txdone_entry_desc txdesc;
720 u32 word;
721 u16 mcs, real_mcs;
b34793ee 722 int aggr, ampdu;
14433331
HS		 723
724 /*
725 * Obtain the status about this packet.
726 */
727 txdesc.flags = 0;
14433331 728 rt2x00_desc_read(txwi, 0, &word);
b34793ee 729
14433331 730 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 731 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
732
14433331 733 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 734 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
735
736 /*
737 * If a frame was meant to be sent as a single non-aggregated MPDU
738 * but ended up in an aggregate the used tx rate doesn't correlate
739 * with the one specified in the TXWI as the whole aggregate is sent
740 * with the same rate.
741 *
742 * For example: two frames are sent to rt2x00, the first one sets
743 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
744 * and requests MCS15. If the hw aggregates both frames into one
745 * AMDPU the tx status for both frames will contain MCS7 although
746 * the frame was sent successfully.
747 *
748 * Hence, replace the requested rate with the real tx rate to not
749 * confuse the rate control algortihm by providing clearly wrong
750 * data.
751 */
5356d963 752 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 753 skbdesc->tx_rate_idx = real_mcs;
754 mcs = real_mcs;
755 }
14433331 756
f16d2db7
HS		 757 if (aggr == 1 || ampdu == 1)
758 __set_bit(TXDONE_AMPDU, &txdesc.flags);
759
14433331
HS		 760 /*
761 * Ralink has a retry mechanism using a global fallback
762 * table. We setup this fallback table to try the immediate
763 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
764 * always contains the MCS used for the last transmission, be
765 * it successful or not.
766 */
767 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
768 /*
769 * Transmission succeeded. The number of retries is
770 * mcs - real_mcs
771 */
772 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
773 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
774 } else {
775 /*
776 * Transmission failed. The number of retries is
777 * always 7 in this case (for a total number of 8
778 * frames sent).
779 */
780 __set_bit(TXDONE_FAILURE, &txdesc.flags);
781 txdesc.retry = rt2x00dev->long_retry;
782 }
783
784 /*
785 * the frame was retried at least once
786 * -> hw used fallback rates
787 */
788 if (txdesc.retry)
789 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
790
791 rt2x00lib_txdone(entry, &txdesc);
792}
793EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
794
f0194b2d
GW		 795void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
796{
797 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
798 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
799 unsigned int beacon_base;
739fd940 800 unsigned int padding_len;
d76dfc61 801 u32 orig_reg, reg;
f0bda571 802 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 803
804 /*
805 * Disable beaconing while we are reloading the beacon data,
806 * otherwise we might be sending out invalid data.
807 */
808 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 809 orig_reg = reg;
f0194b2d
GW		 810 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
811 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
812
813 /*
814 * Add space for the TXWI in front of the skb.
815 */
f0bda571 816 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 817
818 /*
819 * Register descriptor details in skb frame descriptor.
820 */
821 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
822 skbdesc->desc = entry->skb->data;
f0bda571 823 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 824
825 /*
826 * Add the TXWI for the beacon to the skb.
827 */
0c5879bc 828 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 829
830 /*
831 * Dump beacon to userspace through debugfs.
832 */
833 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
834
835 /*
739fd940 836 * Write entire beacon with TXWI and padding to register.
f0194b2d 837 */
739fd940 838 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 839 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 840 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 841 /* skb freed by skb_pad() on failure */
842 entry->skb = NULL;
843 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
844 return;
845 }
846
f0194b2d 847 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 848 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
849 entry->skb->len + padding_len);
f0194b2d
GW		 850
851 /*
852 * Enable beaconing again.
853 */
f0194b2d
GW		 854 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
855 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
856
857 /*
858 * Clean up beacon skb.
859 */
860 dev_kfree_skb_any(entry->skb);
861 entry->skb = NULL;
862}
50e888ea 863EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 864
69cf36a4
HS		 865static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
866 unsigned int beacon_base)
fdb87251
HS		 867{
868 int i;
0879f875 869 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
fdb87251
HS		 870
871 /*
872 * For the Beacon base registers we only need to clear
873 * the whole TXWI which (when set to 0) will invalidate
874 * the entire beacon.
875 */
f0bda571 876 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 877 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
878}
879
69cf36a4
HS		 880void rt2800_clear_beacon(struct queue_entry *entry)
881{
882 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
883 u32 reg;
884
885 /*
886 * Disable beaconing while we are reloading the beacon data,
887 * otherwise we might be sending out invalid data.
888 */
889 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
890 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
891 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
892
893 /*
894 * Clear beacon.
895 */
896 rt2800_clear_beacon_register(rt2x00dev,
897 HW_BEACON_OFFSET(entry->entry_idx));
898
899 /*
900 * Enabled beaconing again.
901 */
902 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
903 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
904}
905EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
906
f4450616
BZ		 907#ifdef CONFIG_RT2X00_LIB_DEBUGFS
908const struct rt2x00debug rt2800_rt2x00debug = {
909 .owner = THIS_MODULE,
910 .csr = {
911 .read = rt2800_register_read,
912 .write = rt2800_register_write,
913 .flags = RT2X00DEBUGFS_OFFSET,
914 .word_base = CSR_REG_BASE,
915 .word_size = sizeof(u32),
916 .word_count = CSR_REG_SIZE / sizeof(u32),
917 },
918 .eeprom = {
3e38d3da
GJ		 919 /* NOTE: The local EEPROM access functions can't
920 * be used here, use the generic versions instead.
921 */
f4450616
BZ		 922 .read = rt2x00_eeprom_read,
923 .write = rt2x00_eeprom_write,
924 .word_base = EEPROM_BASE,
925 .word_size = sizeof(u16),
926 .word_count = EEPROM_SIZE / sizeof(u16),
927 },
928 .bbp = {
929 .read = rt2800_bbp_read,
930 .write = rt2800_bbp_write,
931 .word_base = BBP_BASE,
932 .word_size = sizeof(u8),
933 .word_count = BBP_SIZE / sizeof(u8),
934 },
935 .rf = {
936 .read = rt2x00_rf_read,
937 .write = rt2800_rf_write,
938 .word_base = RF_BASE,
939 .word_size = sizeof(u32),
940 .word_count = RF_SIZE / sizeof(u32),
941 },
f2bd7f16
AA		 942 .rfcsr = {
943 .read = rt2800_rfcsr_read,
944 .write = rt2800_rfcsr_write,
945 .word_base = RFCSR_BASE,
946 .word_size = sizeof(u8),
947 .word_count = RFCSR_SIZE / sizeof(u8),
948 },
f4450616
BZ		 949};
950EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
951#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
952
953int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
954{
955 u32 reg;
956
a89534ed
WH		 957 if (rt2x00_rt(rt2x00dev, RT3290)) {
958 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
959 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
960 } else {
99bdf51a
GW		 961 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
962 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 963 }
f4450616
BZ		 964}
965EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
966
967#ifdef CONFIG_RT2X00_LIB_LEDS
968static void rt2800_brightness_set(struct led_classdev *led_cdev,
969 enum led_brightness brightness)
970{
971 struct rt2x00_led *led =
972 container_of(led_cdev, struct rt2x00_led, led_dev);
973 unsigned int enabled = brightness != LED_OFF;
974 unsigned int bg_mode =
975 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
976 unsigned int polarity =
977 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
978 EEPROM_FREQ_LED_POLARITY);
979 unsigned int ledmode =
980 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
981 EEPROM_FREQ_LED_MODE);
44704e5d 982 u32 reg;
f4450616 983
44704e5d
LE		 984 /* Check for SoC (SOC devices don't support MCU requests) */
985 if (rt2x00_is_soc(led->rt2x00dev)) {
986 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
987
988 /* Set LED Polarity */
989 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
990
991 /* Set LED Mode */
992 if (led->type == LED_TYPE_RADIO) {
993 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
994 enabled ? 3 : 0);
995 } else if (led->type == LED_TYPE_ASSOC) {
996 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
997 enabled ? 3 : 0);
998 } else if (led->type == LED_TYPE_QUALITY) {
999 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1000 enabled ? 3 : 0);
1001 }
1002
1003 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1004
1005 } else {
1006 if (led->type == LED_TYPE_RADIO) {
1007 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1008 enabled ? 0x20 : 0);
1009 } else if (led->type == LED_TYPE_ASSOC) {
1010 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1011 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1012 } else if (led->type == LED_TYPE_QUALITY) {
1013 /*
1014 * The brightness is divided into 6 levels (0 - 5),
1015 * The specs tell us the following levels:
1016 * 0, 1 ,3, 7, 15, 31
1017 * to determine the level in a simple way we can simply
1018 * work with bitshifting:
1019 * (1 << level) - 1
1020 */
1021 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1022 (1 << brightness / (LED_FULL / 6)) - 1,
1023 polarity);
1024 }
f4450616
BZ		 1025 }
1026}
1027
b3579d6a 1028static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1029 struct rt2x00_led *led, enum led_type type)
1030{
1031 led->rt2x00dev = rt2x00dev;
1032 led->type = type;
1033 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1034 led->flags = LED_INITIALIZED;
1035}
f4450616
BZ		 1036#endif /* CONFIG_RT2X00_LIB_LEDS */
1037
1038/*
1039 * Configuration handlers.
1040 */
a2b1328a
HS		 1041static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1042 const u8 *address,
1043 int wcid)
f4450616
BZ		 1044{
1045 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1046 u32 offset;
1047
1048 offset = MAC_WCID_ENTRY(wcid);
1049
1050 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1051 if (address)
1052 memcpy(wcid_entry.mac, address, ETH_ALEN);
1053
1054 rt2800_register_multiwrite(rt2x00dev, offset,
1055 &wcid_entry, sizeof(wcid_entry));
1056}
1057
1058static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1059{
1060 u32 offset;
1061 offset = MAC_WCID_ATTR_ENTRY(wcid);
1062 rt2800_register_write(rt2x00dev, offset, 0);
1063}
1064
1065static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1066 int wcid, u32 bssidx)
1067{
1068 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1069 u32 reg;
1070
1071 /*
1072 * The BSS Idx numbers is split in a main value of 3 bits,
1073 * and a extended field for adding one additional bit to the value.
1074 */
1075 rt2800_register_read(rt2x00dev, offset, &reg);
1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1078 (bssidx & 0x8) >> 3);
1079 rt2800_register_write(rt2x00dev, offset, reg);
1080}
1081
1082static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1083 struct rt2x00lib_crypto *crypto,
1084 struct ieee80211_key_conf *key)
1085{
f4450616
BZ		 1086 struct mac_iveiv_entry iveiv_entry;
1087 u32 offset;
1088 u32 reg;
1089
1090 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1091
e4a0ab34
ID		 1092 if (crypto->cmd == SET_KEY) {
1093 rt2800_register_read(rt2x00dev, offset, &reg);
1094 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1095 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1096 /*
1097 * Both the cipher as the BSS Idx numbers are split in a main
1098 * value of 3 bits, and a extended field for adding one additional
1099 * bit to the value.
1100 */
1101 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1102 (crypto->cipher & 0x7));
1103 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1104 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1105 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1106 rt2800_register_write(rt2x00dev, offset, reg);
1107 } else {
a2b1328a
HS		 1108 /* Delete the cipher without touching the bssidx */
1109 rt2800_register_read(rt2x00dev, offset, &reg);
1110 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1111 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1112 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1113 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1114 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1115 }
f4450616
BZ		 1116
1117 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1118
1119 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1120 if ((crypto->cipher == CIPHER_TKIP) ||
1121 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1122 (crypto->cipher == CIPHER_AES))
1123 iveiv_entry.iv[3] |= 0x20;
1124 iveiv_entry.iv[3] |= key->keyidx << 6;
1125 rt2800_register_multiwrite(rt2x00dev, offset,
1126 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1127}
1128
1129int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1130 struct rt2x00lib_crypto *crypto,
1131 struct ieee80211_key_conf *key)
1132{
1133 struct hw_key_entry key_entry;
1134 struct rt2x00_field32 field;
1135 u32 offset;
1136 u32 reg;
1137
1138 if (crypto->cmd == SET_KEY) {
1139 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1140
1141 memcpy(key_entry.key, crypto->key,
1142 sizeof(key_entry.key));
1143 memcpy(key_entry.tx_mic, crypto->tx_mic,
1144 sizeof(key_entry.tx_mic));
1145 memcpy(key_entry.rx_mic, crypto->rx_mic,
1146 sizeof(key_entry.rx_mic));
1147
1148 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1149 rt2800_register_multiwrite(rt2x00dev, offset,
1150 &key_entry, sizeof(key_entry));
1151 }
1152
1153 /*
1154 * The cipher types are stored over multiple registers
1155 * starting with SHARED_KEY_MODE_BASE each word will have
1156 * 32 bits and contains the cipher types for 2 bssidx each.
1157 * Using the correct defines correctly will cause overhead,
1158 * so just calculate the correct offset.
1159 */
1160 field.bit_offset = 4 * (key->hw_key_idx % 8);
1161 field.bit_mask = 0x7 << field.bit_offset;
1162
1163 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1164
1165 rt2800_register_read(rt2x00dev, offset, &reg);
1166 rt2x00_set_field32(&reg, field,
1167 (crypto->cmd == SET_KEY) * crypto->cipher);
1168 rt2800_register_write(rt2x00dev, offset, reg);
1169
1170 /*
1171 * Update WCID information
1172 */
a2b1328a
HS		 1173 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1174 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1175 crypto->bssidx);
1176 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1177
1178 return 0;
1179}
1180EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1181
a2b1328a 1182static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1183{
a2b1328a 1184 struct mac_wcid_entry wcid_entry;
1ed3811c 1185 int idx;
a2b1328a 1186 u32 offset;
1ed3811c
HS		 1187
1188 /*
a2b1328a
HS		 1189 * Search for the first free WCID entry and return the corresponding
1190 * index.
1ed3811c
HS		 1191 *
1192 * Make sure the WCID starts _after_ the last possible shared key
1193 * entry (>32).
1194 *
1195 * Since parts of the pairwise key table might be shared with
1196 * the beacon frame buffers 6 & 7 we should only write into the
1197 * first 222 entries.
1198 */
1199 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1200 offset = MAC_WCID_ENTRY(idx);
1201 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1202 sizeof(wcid_entry));
1203 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1204 return idx;
1205 }
a2b1328a
HS		 1206
1207 /*
1208 * Use -1 to indicate that we don't have any more space in the WCID
1209 * table.
1210 */
1ed3811c
HS		 1211 return -1;
1212}
1213
f4450616
BZ		 1214int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1215 struct rt2x00lib_crypto *crypto,
1216 struct ieee80211_key_conf *key)
1217{
1218 struct hw_key_entry key_entry;
1219 u32 offset;
1220
1221 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1222 /*
1223 * Allow key configuration only for STAs that are
1224 * known by the hw.
1225 */
1226 if (crypto->wcid < 0)
f4450616 1227 return -ENOSPC;
a2b1328a 1228 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1229
1230 memcpy(key_entry.key, crypto->key,
1231 sizeof(key_entry.key));
1232 memcpy(key_entry.tx_mic, crypto->tx_mic,
1233 sizeof(key_entry.tx_mic));
1234 memcpy(key_entry.rx_mic, crypto->rx_mic,
1235 sizeof(key_entry.rx_mic));
1236
1237 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1238 rt2800_register_multiwrite(rt2x00dev, offset,
1239 &key_entry, sizeof(key_entry));
1240 }
1241
1242 /*
1243 * Update WCID information
1244 */
a2b1328a 1245 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1246
1247 return 0;
1248}
1249EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1250
a2b1328a
HS		 1251int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1252 struct ieee80211_sta *sta)
1253{
1254 int wcid;
1255 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1256
1257 /*
1258 * Find next free WCID.
1259 */
1260 wcid = rt2800_find_wcid(rt2x00dev);
1261
1262 /*
1263 * Store selected wcid even if it is invalid so that we can
1264 * later decide if the STA is uploaded into the hw.
1265 */
1266 sta_priv->wcid = wcid;
1267
1268 /*
1269 * No space left in the device, however, we can still communicate
1270 * with the STA -> No error.
1271 */
1272 if (wcid < 0)
1273 return 0;
1274
1275 /*
1276 * Clean up WCID attributes and write STA address to the device.
1277 */
1278 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1279 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1280 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1281 rt2x00lib_get_bssidx(rt2x00dev, vif));
1282 return 0;
1283}
1284EXPORT_SYMBOL_GPL(rt2800_sta_add);
1285
1286int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1287{
1288 /*
1289 * Remove WCID entry, no need to clean the attributes as they will
1290 * get renewed when the WCID is reused.
1291 */
1292 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1293
1294 return 0;
1295}
1296EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1297
f4450616
BZ		 1298void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1299 const unsigned int filter_flags)
1300{
1301 u32 reg;
1302
1303 /*
1304 * Start configuration steps.
1305 * Note that the version error will always be dropped
1306 * and broadcast frames will always be accepted since
1307 * there is no filter for it at this time.
1308 */
1309 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1310 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1311 !(filter_flags & FIF_FCSFAIL));
1312 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1313 !(filter_flags & FIF_PLCPFAIL));
1314 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1315 !(filter_flags & FIF_PROMISC_IN_BSS));
1316 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1317 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1318 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1319 !(filter_flags & FIF_ALLMULTI));
1320 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1321 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1322 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1323 !(filter_flags & FIF_CONTROL));
1324 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1325 !(filter_flags & FIF_CONTROL));
1326 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1327 !(filter_flags & FIF_CONTROL));
1328 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1329 !(filter_flags & FIF_CONTROL));
1330 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1331 !(filter_flags & FIF_CONTROL));
1332 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1333 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1334 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1335 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1336 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1337 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1338 !(filter_flags & FIF_CONTROL));
1339 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1340}
1341EXPORT_SYMBOL_GPL(rt2800_config_filter);
1342
1343void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1344 struct rt2x00intf_conf *conf, const unsigned int flags)
1345{
f4450616 1346 u32 reg;
fa8b4b22 1347 bool update_bssid = false;
f4450616
BZ		 1348
1349 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1350 /*
1351 * Enable synchronisation.
1352 */
1353 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1354 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1355 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1356
1357 if (conf->sync == TSF_SYNC_AP_NONE) {
1358 /*
1359 * Tune beacon queue transmit parameters for AP mode
1360 */
1361 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1362 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1363 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1364 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1365 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1366 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1367 } else {
1368 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1369 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1370 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1371 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1372 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1373 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1374 }
f4450616
BZ		 1375 }
1376
1377 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1378 if (flags & CONFIG_UPDATE_TYPE &&
1379 conf->sync == TSF_SYNC_AP_NONE) {
1380 /*
1381 * The BSSID register has to be set to our own mac
1382 * address in AP mode.
1383 */
1384 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1385 update_bssid = true;
1386 }
1387
c600c826
ID		 1388 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1389 reg = le32_to_cpu(conf->mac[1]);
1390 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1391 conf->mac[1] = cpu_to_le32(reg);
1392 }
f4450616
BZ		 1393
1394 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1395 conf->mac, sizeof(conf->mac));
1396 }
1397
fa8b4b22 1398 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1399 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1400 reg = le32_to_cpu(conf->bssid[1]);
1401 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1402 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1403 conf->bssid[1] = cpu_to_le32(reg);
1404 }
f4450616
BZ		 1405
1406 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1407 conf->bssid, sizeof(conf->bssid));
1408 }
1409}
1410EXPORT_SYMBOL_GPL(rt2800_config_intf);
1411
87c1915d
HS		 1412static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1413 struct rt2x00lib_erp *erp)
1414{
1415 bool any_sta_nongf = !!(erp->ht_opmode &
1416 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1417 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1418 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1419 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1420 u32 reg;
1421
1422 /* default protection rate for HT20: OFDM 24M */
1423 mm20_rate = gf20_rate = 0x4004;
1424
1425 /* default protection rate for HT40: duplicate OFDM 24M */
1426 mm40_rate = gf40_rate = 0x4084;
1427
1428 switch (protection) {
1429 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1430 /*
1431 * All STAs in this BSS are HT20/40 but there might be
1432 * STAs not supporting greenfield mode.
1433 * => Disable protection for HT transmissions.
1434 */
1435 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1436
1437 break;
1438 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1439 /*
1440 * All STAs in this BSS are HT20 or HT20/40 but there
1441 * might be STAs not supporting greenfield mode.
1442 * => Protect all HT40 transmissions.
1443 */
1444 mm20_mode = gf20_mode = 0;
1445 mm40_mode = gf40_mode = 2;
1446
1447 break;
1448 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1449 /*
1450 * Nonmember protection:
1451 * According to 802.11n we _should_ protect all
1452 * HT transmissions (but we don't have to).
1453 *
1454 * But if cts_protection is enabled we _shall_ protect
1455 * all HT transmissions using a CCK rate.
1456 *
1457 * And if any station is non GF we _shall_ protect
1458 * GF transmissions.
1459 *
1460 * We decide to protect everything
1461 * -> fall through to mixed mode.
1462 */
1463 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1464 /*
1465 * Legacy STAs are present
1466 * => Protect all HT transmissions.
1467 */
1468 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1469
1470 /*
1471 * If erp protection is needed we have to protect HT
1472 * transmissions with CCK 11M long preamble.
1473 */
1474 if (erp->cts_protection) {
1475 /* don't duplicate RTS/CTS in CCK mode */
1476 mm20_rate = mm40_rate = 0x0003;
1477 gf20_rate = gf40_rate = 0x0003;
1478 }
1479 break;
6403eab1 1480 }
87c1915d
HS		 1481
1482 /* check for STAs not supporting greenfield mode */
1483 if (any_sta_nongf)
1484 gf20_mode = gf40_mode = 2;
1485
1486 /* Update HT protection config */
1487 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1488 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1489 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1490 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1491
1492 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1493 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1494 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1495 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1496
1497 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1498 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1499 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1500 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1501
1502 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1503 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1504 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1505 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1506}
1507
02044643
HS		 1508void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1509 u32 changed)
f4450616
BZ		 1510{
1511 u32 reg;
1512
02044643
HS		 1513 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1514 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1516 !!erp->short_preamble);
1517 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1518 !!erp->short_preamble);
1519 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1520 }
f4450616 1521
02044643
HS		 1522 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1523 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1524 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1525 erp->cts_protection ? 2 : 0);
1526 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1527 }
f4450616 1528
02044643
HS		 1529 if (changed & BSS_CHANGED_BASIC_RATES) {
1530 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1531 erp->basic_rates);
1532 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1533 }
f4450616 1534
02044643
HS		 1535 if (changed & BSS_CHANGED_ERP_SLOT) {
1536 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1537 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1538 erp->slot_time);
1539 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1540
02044643
HS		 1541 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1542 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1543 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1544 }
f4450616 1545
02044643
HS		 1546 if (changed & BSS_CHANGED_BEACON_INT) {
1547 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1548 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1549 erp->beacon_int * 16);
1550 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1551 }
87c1915d
HS		 1552
1553 if (changed & BSS_CHANGED_HT)
1554 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1555}
1556EXPORT_SYMBOL_GPL(rt2800_config_erp);
1557
872834df
GW		 1558static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1559{
1560 u32 reg;
1561 u16 eeprom;
1562 u8 led_ctrl, led_g_mode, led_r_mode;
1563
1564 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1565 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1566 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1567 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1568 } else {
1569 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1570 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1571 }
1572 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1573
1574 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1575 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1576 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1577 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1578 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1579 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1580 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1581 if (led_ctrl == 0 || led_ctrl > 0x40) {
1582 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1583 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1584 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1585 } else {
1586 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1587 (led_g_mode << 2) | led_r_mode, 1);
1588 }
1589 }
1590}
1591
d96aa640
RJH		 1592static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1593 enum antenna ant)
1594{
1595 u32 reg;
1596 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1597 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1598
1599 if (rt2x00_is_pci(rt2x00dev)) {
1600 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1601 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1602 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1603 } else if (rt2x00_is_usb(rt2x00dev))
1604 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1605 eesk_pin, 0);
1606
99bdf51a
GW		 1607 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1608 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1609 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1610 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1611}
1612
f4450616
BZ		 1613void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1614{
1615 u8 r1;
1616 u8 r3;
d96aa640 1617 u16 eeprom;
f4450616
BZ		 1618
1619 rt2800_bbp_read(rt2x00dev, 1, &r1);
1620 rt2800_bbp_read(rt2x00dev, 3, &r3);
1621
872834df
GW		 1622 if (rt2x00_rt(rt2x00dev, RT3572) &&
1623 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1624 rt2800_config_3572bt_ant(rt2x00dev);
1625
f4450616
BZ		 1626 /*
1627 * Configure the TX antenna.
1628 */
d96aa640 1629 switch (ant->tx_chain_num) {
f4450616
BZ		 1630 case 1:
1631 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1632 break;
1633 case 2:
872834df
GW		 1634 if (rt2x00_rt(rt2x00dev, RT3572) &&
1635 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1636 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1637 else
1638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1639 break;
1640 case 3:
e22557f2 1641 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1642 break;
1643 }
1644
1645 /*
1646 * Configure the RX antenna.
1647 */
d96aa640 1648 switch (ant->rx_chain_num) {
f4450616 1649 case 1:
d96aa640
RJH		 1650 if (rt2x00_rt(rt2x00dev, RT3070) ||
1651 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1652 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1653 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1654 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1655 EEPROM_NIC_CONF1, &eeprom);
1656 if (rt2x00_get_field16(eeprom,
1657 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1658 rt2800_set_ant_diversity(rt2x00dev,
1659 rt2x00dev->default_ant.rx);
1660 }
f4450616
BZ		 1661 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1662 break;
1663 case 2:
872834df
GW		 1664 if (rt2x00_rt(rt2x00dev, RT3572) &&
1665 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1666 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1667 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1668 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1669 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1670 } else {
1671 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1672 }
f4450616
BZ		 1673 break;
1674 case 3:
1675 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1676 break;
1677 }
1678
1679 rt2800_bbp_write(rt2x00dev, 3, r3);
1680 rt2800_bbp_write(rt2x00dev, 1, r1);
1681}
1682EXPORT_SYMBOL_GPL(rt2800_config_ant);
1683
1684static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1685 struct rt2x00lib_conf *libconf)
1686{
1687 u16 eeprom;
1688 short lna_gain;
1689
1690 if (libconf->rf.channel <= 14) {
3e38d3da 1691 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1692 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1693 } else if (libconf->rf.channel <= 64) {
3e38d3da 1694 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1695 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1696 } else if (libconf->rf.channel <= 128) {
3e38d3da 1697 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
f4450616
BZ		 1698 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1699 } else {
3e38d3da 1700 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
f4450616
BZ		 1701 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1702 }
1703
1704 rt2x00dev->lna_gain = lna_gain;
1705}
1706
06855ef4
GW		 1707static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1708 struct ieee80211_conf *conf,
1709 struct rf_channel *rf,
1710 struct channel_info *info)
f4450616
BZ		 1711{
1712 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1713
d96aa640 1714 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1715 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1716
d96aa640 1717 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1718 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1719 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1720 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1721 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1722
1723 if (rf->channel > 14) {
1724 /*
1725 * When TX power is below 0, we should increase it by 7 to
25985edc 1726 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1727 * However this means that values between 0 and 7 have
1728 * double meaning, and we should set a 7DBm boost flag.
1729 */
1730 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1731 (info->default_power1 >= 0));
f4450616 1732
8d1331b3
ID		 1733 if (info->default_power1 < 0)
1734 info->default_power1 += 7;
f4450616 1735
8d1331b3 1736 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1737
1738 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1739 (info->default_power2 >= 0));
f4450616 1740
8d1331b3
ID		 1741 if (info->default_power2 < 0)
1742 info->default_power2 += 7;
f4450616 1743
8d1331b3 1744 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1745 } else {
8d1331b3
ID		 1746 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1747 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1748 }
1749
1750 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1751
1752 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1753 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1754 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1755 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1756
1757 udelay(200);
1758
1759 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1760 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1761 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1762 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1763
1764 udelay(200);
1765
1766 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1767 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1768 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1769 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1770}
1771
06855ef4
GW		 1772static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1773 struct ieee80211_conf *conf,
1774 struct rf_channel *rf,
1775 struct channel_info *info)
f4450616 1776{
3a1c0128 1777 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1778 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1779
1780 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1781
1782 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1783 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1784 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1785
1786 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1787 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1788 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1789
1790 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1791 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1792 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1793
5a673964 1794 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1795 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1796 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1797
1798 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1799 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 1800 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1801 rt2x00dev->default_ant.rx_chain_num <= 1);
1802 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1803 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 1804 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 1805 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1806 rt2x00dev->default_ant.tx_chain_num <= 1);
1807 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1808 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 1809 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1810
3e0c7643
SG		 1811 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1812 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1813 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1814 msleep(1);
1815 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1816 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1817
f4450616
BZ		 1818 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1819 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1820 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1821
f1f12f98
SG		 1822 if (rt2x00_rt(rt2x00dev, RT3390)) {
1823 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1824 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1825 } else {
3a1c0128
GW		 1826 if (conf_is_ht40(conf)) {
1827 calib_tx = drv_data->calibration_bw40;
1828 calib_rx = drv_data->calibration_bw40;
1829 } else {
1830 calib_tx = drv_data->calibration_bw20;
1831 calib_rx = drv_data->calibration_bw20;
1832 }
f1f12f98
SG		 1833 }
1834
1835 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1836 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1837 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1838
1839 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1840 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1841 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1842
71976907 1843 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1844 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1845 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1846
1847 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1848 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1849 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1850 msleep(1);
1851 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1852 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1853}
1854
872834df
GW		 1855static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1856 struct ieee80211_conf *conf,
1857 struct rf_channel *rf,
1858 struct channel_info *info)
1859{
3a1c0128 1860 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1861 u8 rfcsr;
1862 u32 reg;
1863
1864 if (rf->channel <= 14) {
5d137dff
GW		 1865 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1866 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1867 } else {
1868 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1869 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1870 }
1871
1872 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1873 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1874
1875 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1876 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1877 if (rf->channel <= 14)
1878 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1879 else
1880 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1881 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1882
1883 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1884 if (rf->channel <= 14)
1885 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1886 else
1887 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1888 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1889
1890 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1891 if (rf->channel <= 14) {
1892 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1893 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1894 info->default_power1);
872834df
GW		 1895 } else {
1896 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1897 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1898 (info->default_power1 & 0x3) |
1899 ((info->default_power1 & 0xC) << 1));
1900 }
1901 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1902
1903 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1904 if (rf->channel <= 14) {
1905 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1906 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1907 info->default_power2);
872834df
GW		 1908 } else {
1909 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1910 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1911 (info->default_power2 & 0x3) |
1912 ((info->default_power2 & 0xC) << 1));
1913 }
1914 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1915
1916 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1917 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1918 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1919 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1920 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1921 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1922 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1923 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1924 if (rf->channel <= 14) {
1925 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1926 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1927 }
1928 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1929 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1930 } else {
1931 switch (rt2x00dev->default_ant.tx_chain_num) {
1932 case 1:
1933 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1934 case 2:
1935 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1936 break;
1937 }
1938
1939 switch (rt2x00dev->default_ant.rx_chain_num) {
1940 case 1:
1941 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1942 case 2:
1943 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1944 break;
1945 }
1946 }
1947 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1948
1949 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1950 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1951 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1952
3a1c0128
GW		 1953 if (conf_is_ht40(conf)) {
1954 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1955 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1956 } else {
1957 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1958 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1959 }
872834df
GW		 1960
1961 if (rf->channel <= 14) {
1962 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1963 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1964 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1965 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1966 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1967 rfcsr = 0x4c;
1968 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1969 drv_data->txmixer_gain_24g);
1970 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1971 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1972 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1973 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1974 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1975 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1976 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1977 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1978 } else {
58b8ae14
GW		 1979 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1980 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1981 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1982 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1983 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1984 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1985 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1986 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1987 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1988 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1989 rfcsr = 0x7a;
1990 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1991 drv_data->txmixer_gain_5g);
1992 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1993 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1994 if (rf->channel <= 64) {
1995 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1996 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1997 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1998 } else if (rf->channel <= 128) {
1999 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2000 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2001 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2002 } else {
2003 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2004 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2005 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2006 }
2007 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2008 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2009 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2010 }
2011
99bdf51a
GW		 2012 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2013 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2014 if (rf->channel <= 14)
99bdf51a 2015 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2016 else
99bdf51a
GW		 2017 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2018 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2019
2020 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2021 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2022 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2023}
60687ba7 2024
7573cb5b 2025#define POWER_BOUND 0x27
8f821098 2026#define POWER_BOUND_5G 0x2b
7573cb5b 2027#define FREQ_OFFSET_BOUND 0x5f
60687ba7 2028
0c9e5fb9
SG		 2029static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2030{
2031 u8 rfcsr;
2032
2033 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2034 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2035 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2036 else
2037 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2038 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2039}
2040
a89534ed
WH		 2041static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2042 struct ieee80211_conf *conf,
2043 struct rf_channel *rf,
2044 struct channel_info *info)
2045{
2046 u8 rfcsr;
2047
2048 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2049 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2050 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2051 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2052 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2053
2054 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2055 if (info->default_power1 > POWER_BOUND)
2056 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2057 else
2058 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2059 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2060
0c9e5fb9 2061 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2062
2063 if (rf->channel <= 14) {
2064 if (rf->channel == 6)
2065 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2066 else
2067 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2068
2069 if (rf->channel >= 1 && rf->channel <= 6)
2070 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2071 else if (rf->channel >= 7 && rf->channel <= 11)
2072 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2073 else if (rf->channel >= 12 && rf->channel <= 14)
2074 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2075 }
2076}
2077
03839951
DG		 2078static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2079 struct ieee80211_conf *conf,
2080 struct rf_channel *rf,
2081 struct channel_info *info)
2082{
2083 u8 rfcsr;
2084
2085 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2086 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2087
2088 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2089 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2090 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2091
2092 if (info->default_power1 > POWER_BOUND)
2093 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2094 else
2095 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2096
2097 if (info->default_power2 > POWER_BOUND)
2098 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2099 else
2100 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2101
0c9e5fb9 2102 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2103
2104 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2105 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2106 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2107
2108 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2109 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2110 else
2111 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2112
2113 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2114 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2115 else
2116 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2117
2118 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2119 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2120
2121 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2122
2123 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2124}
2125
60687ba7 2126static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2127 struct ieee80211_conf *conf,
2128 struct rf_channel *rf,
2129 struct channel_info *info)
2130{
2131 u8 rfcsr;
adde5882
GJ		 2132
2133 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2134 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2135 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2136 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2137 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2138
2139 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2140 if (info->default_power1 > POWER_BOUND)
2141 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2142 else
2143 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2144 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2145
cff3d1f0
ZL		 2146 if (rt2x00_rt(rt2x00dev, RT5392)) {
2147 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2148 if (info->default_power1 > POWER_BOUND)
2149 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2150 else
2151 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2152 info->default_power2);
2153 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2154 }
2155
adde5882 2156 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2157 if (rt2x00_rt(rt2x00dev, RT5392)) {
2158 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2159 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2160 }
adde5882
GJ		 2161 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2162 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2163 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2164 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2165 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2166
0c9e5fb9 2167 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2168
adde5882
GJ		 2169 if (rf->channel <= 14) {
2170 int idx = rf->channel-1;
2171
fdbc7b0a 2172 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2173 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2174 /* r55/r59 value array of channel 1~14 */
2175 static const char r55_bt_rev[] = {0x83, 0x83,
2176 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2177 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2178 static const char r59_bt_rev[] = {0x0e, 0x0e,
2179 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2180 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2181
2182 rt2800_rfcsr_write(rt2x00dev, 55,
2183 r55_bt_rev[idx]);
2184 rt2800_rfcsr_write(rt2x00dev, 59,
2185 r59_bt_rev[idx]);
2186 } else {
2187 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2188 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2189 0x88, 0x88, 0x86, 0x85, 0x84};
2190
2191 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2192 }
2193 } else {
2194 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2195 static const char r55_nonbt_rev[] = {0x23, 0x23,
2196 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2197 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2198 static const char r59_nonbt_rev[] = {0x07, 0x07,
2199 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2200 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2201
2202 rt2800_rfcsr_write(rt2x00dev, 55,
2203 r55_nonbt_rev[idx]);
2204 rt2800_rfcsr_write(rt2x00dev, 59,
2205 r59_nonbt_rev[idx]);
2ed71884 2206 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2207 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2208 static const char r59_non_bt[] = {0x8f, 0x8f,
2209 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2210 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2211
2212 rt2800_rfcsr_write(rt2x00dev, 59,
2213 r59_non_bt[idx]);
2214 }
2215 }
2216 }
60687ba7
RST		 2217}
2218
8f821098
SG		 2219static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2220 struct ieee80211_conf *conf,
2221 struct rf_channel *rf,
2222 struct channel_info *info)
2223{
2224 u8 rfcsr, ep_reg;
d5ae7a6b 2225 u32 reg;
8f821098
SG		 2226 int power_bound;
2227
2228 /* TODO */
2229 const bool is_11b = false;
2230 const bool is_type_ep = false;
2231
d5ae7a6b
SG		 2232 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2233 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2234 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2235 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2236
2237 /* Order of values on rf_channel entry: N, K, mod, R */
2238 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2239
2240 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2241 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2242 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2243 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2244 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2245
2246 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2247 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2248 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2249 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2250
2251 if (rf->channel <= 14) {
2252 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2253 /* FIXME: RF11 owerwrite ? */
2254 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2255 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2256 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2257 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2258 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2259 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2260 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2261 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2262 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2263 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2264 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2265 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2266 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2267 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2268 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2269 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2270 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2271 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2272 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2273 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2274 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2275 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2276 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2277 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2278 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2279 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2280 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2281 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2282
2283 /* TODO RF27 <- tssi */
2284
2285 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2286 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2287 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2288
2289 if (is_11b) {
2290 /* CCK */
2291 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2292 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2293 if (is_type_ep)
2294 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2295 else
2296 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2297 } else {
2298 /* OFDM */
2299 if (is_type_ep)
2300 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2301 else
2302 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2303 }
2304
2305 power_bound = POWER_BOUND;
2306 ep_reg = 0x2;
2307 } else {
2308 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2309 /* FIMXE: RF11 overwrite */
2310 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2311 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2312 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2313 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2314 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2315 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2316 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2317 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2318 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2319 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2320 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2321 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2322 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2323 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2324
2325 /* TODO RF27 <- tssi */
2326
2327 if (rf->channel >= 36 && rf->channel <= 64) {
2328
2329 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2330 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2331 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2332 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2333 if (rf->channel <= 50)
2334 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2335 else if (rf->channel >= 52)
2336 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2337 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2338 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2339 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2340 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2341 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2342 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2343 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2344 if (rf->channel <= 50) {
2345 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2346 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2347 } else if (rf->channel >= 52) {
2348 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2349 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2350 }
2351
2352 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2353 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2354 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2355
2356 } else if (rf->channel >= 100 && rf->channel <= 165) {
2357
2358 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2359 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2360 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2361 if (rf->channel <= 153) {
2362 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2363 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2364 } else if (rf->channel >= 155) {
2365 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2366 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2367 }
2368 if (rf->channel <= 138) {
2369 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2370 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2371 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2372 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2373 } else if (rf->channel >= 140) {
2374 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2375 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2376 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2377 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2378 }
2379 if (rf->channel <= 124)
2380 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2381 else if (rf->channel >= 126)
2382 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2383 if (rf->channel <= 138)
2384 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2385 else if (rf->channel >= 140)
2386 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2387 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2388 if (rf->channel <= 138)
2389 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2390 else if (rf->channel >= 140)
2391 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2392 if (rf->channel <= 128)
2393 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2394 else if (rf->channel >= 130)
2395 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2396 if (rf->channel <= 116)
2397 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2398 else if (rf->channel >= 118)
2399 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2400 if (rf->channel <= 138)
2401 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2402 else if (rf->channel >= 140)
2403 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2404 if (rf->channel <= 116)
2405 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2406 else if (rf->channel >= 118)
2407 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2408 }
2409
2410 power_bound = POWER_BOUND_5G;
2411 ep_reg = 0x3;
2412 }
2413
2414 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2415 if (info->default_power1 > power_bound)
2416 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2417 else
2418 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2419 if (is_type_ep)
2420 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2421 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2422
2423 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2424 if (info->default_power2 > power_bound)
8f821098
SG		 2425 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2426 else
2427 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2428 if (is_type_ep)
2429 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2430 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2431
2432 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2433 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2434 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2435
2436 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2437 rt2x00dev->default_ant.tx_chain_num >= 1);
2438 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2439 rt2x00dev->default_ant.tx_chain_num == 2);
2440 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2441
2442 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2443 rt2x00dev->default_ant.rx_chain_num >= 1);
2444 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2445 rt2x00dev->default_ant.rx_chain_num == 2);
2446 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2447
2448 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2449 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2450
2451 if (conf_is_ht40(conf))
2452 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2453 else
2454 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2455
2456 if (!is_11b) {
2457 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2458 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2459 }
2460
2461 /* TODO proper frequency adjustment */
0c9e5fb9 2462 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2463
2464 /* TODO merge with others */
2465 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2466 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2467 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2468
2469 /* BBP settings */
2470 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2471 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2472 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2473
2474 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2475 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2476 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2477 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2478
2479 /* GLRT band configuration */
2480 rt2800_bbp_write(rt2x00dev, 195, 128);
2481 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2482 rt2800_bbp_write(rt2x00dev, 195, 129);
2483 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2484 rt2800_bbp_write(rt2x00dev, 195, 130);
2485 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2486 rt2800_bbp_write(rt2x00dev, 195, 131);
2487 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2488 rt2800_bbp_write(rt2x00dev, 195, 133);
2489 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2490 rt2800_bbp_write(rt2x00dev, 195, 124);
2491 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2492}
2493
5bc2dd06
SG		 2494static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2495 const unsigned int word,
2496 const u8 value)
2497{
2498 u8 chain, reg;
2499
2500 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2501 rt2800_bbp_read(rt2x00dev, 27, &reg);
2502 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2503 rt2800_bbp_write(rt2x00dev, 27, reg);
2504
2505 rt2800_bbp_write(rt2x00dev, word, value);
2506 }
2507}
2508
8756130b
SG		 2509static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2510{
2511 u8 cal;
2512
415e3f2f 2513 /* TX0 IQ Gain */
8756130b 2514 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 2515 if (channel <= 14)
2516 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2517 else if (channel >= 36 && channel <= 64)
2518 cal = rt2x00_eeprom_byte(rt2x00dev,
2519 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2520 else if (channel >= 100 && channel <= 138)
2521 cal = rt2x00_eeprom_byte(rt2x00dev,
2522 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2523 else if (channel >= 140 && channel <= 165)
2524 cal = rt2x00_eeprom_byte(rt2x00dev,
2525 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2526 else
2527 cal = 0;
8756130b
SG		 2528 rt2800_bbp_write(rt2x00dev, 159, cal);
2529
415e3f2f 2530 /* TX0 IQ Phase */
8756130b 2531 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 2532 if (channel <= 14)
2533 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2534 else if (channel >= 36 && channel <= 64)
2535 cal = rt2x00_eeprom_byte(rt2x00dev,
2536 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2537 else if (channel >= 100 && channel <= 138)
2538 cal = rt2x00_eeprom_byte(rt2x00dev,
2539 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2540 else if (channel >= 140 && channel <= 165)
2541 cal = rt2x00_eeprom_byte(rt2x00dev,
2542 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2543 else
2544 cal = 0;
8756130b
SG		 2545 rt2800_bbp_write(rt2x00dev, 159, cal);
2546
415e3f2f 2547 /* TX1 IQ Gain */
8756130b 2548 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 2549 if (channel <= 14)
2550 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2551 else if (channel >= 36 && channel <= 64)
2552 cal = rt2x00_eeprom_byte(rt2x00dev,
2553 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2554 else if (channel >= 100 && channel <= 138)
2555 cal = rt2x00_eeprom_byte(rt2x00dev,
2556 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2557 else if (channel >= 140 && channel <= 165)
2558 cal = rt2x00_eeprom_byte(rt2x00dev,
2559 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2560 else
2561 cal = 0;
8756130b
SG		 2562 rt2800_bbp_write(rt2x00dev, 159, cal);
2563
415e3f2f 2564 /* TX1 IQ Phase */
8756130b 2565 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 2566 if (channel <= 14)
2567 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2568 else if (channel >= 36 && channel <= 64)
2569 cal = rt2x00_eeprom_byte(rt2x00dev,
2570 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2571 else if (channel >= 100 && channel <= 138)
2572 cal = rt2x00_eeprom_byte(rt2x00dev,
2573 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2574 else if (channel >= 140 && channel <= 165)
2575 cal = rt2x00_eeprom_byte(rt2x00dev,
2576 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2577 else
2578 cal = 0;
8756130b
SG		 2579 rt2800_bbp_write(rt2x00dev, 159, cal);
2580
415e3f2f
SG		 2581 /* FIXME: possible RX0, RX1 callibration ? */
2582
8756130b
SG		 2583 /* RF IQ compensation control */
2584 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2585 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2586 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2587
2588 /* RF IQ imbalance compensation control */
2589 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 2590 cal = rt2x00_eeprom_byte(rt2x00dev,
2591 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 2592 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2593}
2594
f4450616
BZ		 2595static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2596 struct ieee80211_conf *conf,
2597 struct rf_channel *rf,
2598 struct channel_info *info)
2599{
2600 u32 reg;
2601 unsigned int tx_pin;
a89534ed 2602 u8 bbp, rfcsr;
f4450616 2603
46323e11 2604 if (rf->channel <= 14) {
8d1331b3
ID		 2605 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2606 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2607 } else {
8d1331b3
ID		 2608 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2609 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2610 }
2611
5aa57015
GW		 2612 switch (rt2x00dev->chip.rf) {
2613 case RF2020:
2614 case RF3020:
2615 case RF3021:
2616 case RF3022:
2617 case RF3320:
06855ef4 2618 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2619 break;
2620 case RF3052:
872834df 2621 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2622 break;
a89534ed
WH		 2623 case RF3290:
2624 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2625 break;
03839951
DG		 2626 case RF3322:
2627 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2628 break;
ccf91bd6 2629 case RF5360:
5aa57015 2630 case RF5370:
2ed71884 2631 case RF5372:
5aa57015 2632 case RF5390:
cff3d1f0 2633 case RF5392:
adde5882 2634 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 2635 break;
8f821098
SG		 2636 case RF5592:
2637 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2638 break;
5aa57015 2639 default:
06855ef4 2640 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2641 }
f4450616 2642
a89534ed 2643 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2644 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2645 rt2x00_rf(rt2x00dev, RF5360) ||
2646 rt2x00_rf(rt2x00dev, RF5370) ||
2647 rt2x00_rf(rt2x00dev, RF5372) ||
2648 rt2x00_rf(rt2x00dev, RF5390) ||
2649 rt2x00_rf(rt2x00dev, RF5392)) {
2650 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2651 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2652 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2653 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2654
2655 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2656 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 2657 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2658 }
2659
f4450616
BZ		 2660 /*
2661 * Change BBP settings
2662 */
03839951
DG		 2663 if (rt2x00_rt(rt2x00dev, RT3352)) {
2664 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 2665 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 2666 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 2667 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951
DG		 2668 } else {
2669 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2670 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2671 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2672 rt2800_bbp_write(rt2x00dev, 86, 0);
2673 }
f4450616
BZ		 2674
2675 if (rf->channel <= 14) {
2ed71884 2676 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 2677 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2678 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2679 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2680 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2681 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2682 } else {
2683 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2684 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2685 }
f4450616
BZ		 2686 }
2687 } else {
872834df
GW		 2688 if (rt2x00_rt(rt2x00dev, RT3572))
2689 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2690 else
2691 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2692
7dab73b3 2693 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2694 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2695 else
2696 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2697 }
2698
2699 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2700 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2701 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2702 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2703 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2704
872834df
GW		 2705 if (rt2x00_rt(rt2x00dev, RT3572))
2706 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2707
f4450616
BZ		 2708 tx_pin = 0;
2709
bb16d488
GJ		 2710 switch (rt2x00dev->default_ant.tx_chain_num) {
2711 case 3:
2712 /* Turn on tertiary PAs */
2713 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
2714 rf->channel > 14);
2715 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
2716 rf->channel <= 14);
2717 /* fall-through */
2718 case 2:
2719 /* Turn on secondary PAs */
65f31b5e
GW		 2720 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2721 rf->channel > 14);
2722 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2723 rf->channel <= 14);
bb16d488
GJ		 2724 /* fall-through */
2725 case 1:
2726 /* Turn on primary PAs */
2727 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
2728 rf->channel > 14);
2729 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2730 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2731 else
2732 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2733 rf->channel <= 14);
2734 break;
f4450616
BZ		 2735 }
2736
bb16d488
GJ		 2737 switch (rt2x00dev->default_ant.rx_chain_num) {
2738 case 3:
2739 /* Turn on tertiary LNAs */
2740 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
2741 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
2742 /* fall-through */
2743 case 2:
2744 /* Turn on secondary LNAs */
f4450616
BZ		 2745 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2746 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 2747 /* fall-through */
2748 case 1:
2749 /* Turn on primary LNAs */
2750 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2751 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2752 break;
f4450616
BZ		 2753 }
2754
f4450616
BZ		 2755 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2756 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 2757
2758 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2759
872834df
GW		 2760 if (rt2x00_rt(rt2x00dev, RT3572))
2761 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2762
6803141b
SG		 2763 if (rt2x00_rt(rt2x00dev, RT5592)) {
2764 rt2800_bbp_write(rt2x00dev, 195, 141);
2765 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2766
8ba0ebf3
SG		 2767 /* AGC init */
2768 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2769 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2770
8756130b 2771 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 2772 }
2773
f4450616
BZ		 2774 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2775 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2776 rt2800_bbp_write(rt2x00dev, 4, bbp);
2777
2778 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2779 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2780 rt2800_bbp_write(rt2x00dev, 3, bbp);
2781
8d0c9b65 2782 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2783 if (conf_is_ht40(conf)) {
2784 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2785 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2786 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2787 } else {
2788 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2789 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2790 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2791 }
2792 }
2793
2794 msleep(1);
977206d7
HS		 2795
2796 /*
2797 * Clear channel statistic counters
2798 */
2799 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2800 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2801 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2802
2803 /*
2804 * Clear update flag
2805 */
2806 if (rt2x00_rt(rt2x00dev, RT3352)) {
2807 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2808 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2809 rt2800_bbp_write(rt2x00dev, 49, bbp);
2810 }
f4450616
BZ		 2811}
2812
9e33a355
HS		 2813static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2814{
2815 u8 tssi_bounds[9];
2816 u8 current_tssi;
2817 u16 eeprom;
2818 u8 step;
2819 int i;
2820
2821 /*
2822 * Read TSSI boundaries for temperature compensation from
2823 * the EEPROM.
2824 *
2825 * Array idx 0 1 2 3 4 5 6 7 8
2826 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2827 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2828 */
2829 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 2830 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 2831 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2832 EEPROM_TSSI_BOUND_BG1_MINUS4);
2833 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2834 EEPROM_TSSI_BOUND_BG1_MINUS3);
2835
3e38d3da 2836 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 2837 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2838 EEPROM_TSSI_BOUND_BG2_MINUS2);
2839 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2840 EEPROM_TSSI_BOUND_BG2_MINUS1);
2841
3e38d3da 2842 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 2843 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2844 EEPROM_TSSI_BOUND_BG3_REF);
2845 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2846 EEPROM_TSSI_BOUND_BG3_PLUS1);
2847
3e38d3da 2848 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 2849 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2850 EEPROM_TSSI_BOUND_BG4_PLUS2);
2851 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2852 EEPROM_TSSI_BOUND_BG4_PLUS3);
2853
3e38d3da 2854 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 2855 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2856 EEPROM_TSSI_BOUND_BG5_PLUS4);
2857
2858 step = rt2x00_get_field16(eeprom,
2859 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2860 } else {
3e38d3da 2861 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 2862 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2863 EEPROM_TSSI_BOUND_A1_MINUS4);
2864 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2865 EEPROM_TSSI_BOUND_A1_MINUS3);
2866
3e38d3da 2867 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 2868 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2869 EEPROM_TSSI_BOUND_A2_MINUS2);
2870 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2871 EEPROM_TSSI_BOUND_A2_MINUS1);
2872
3e38d3da 2873 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 2874 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2875 EEPROM_TSSI_BOUND_A3_REF);
2876 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2877 EEPROM_TSSI_BOUND_A3_PLUS1);
2878
3e38d3da 2879 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 2880 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2881 EEPROM_TSSI_BOUND_A4_PLUS2);
2882 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2883 EEPROM_TSSI_BOUND_A4_PLUS3);
2884
3e38d3da 2885 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 2886 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2887 EEPROM_TSSI_BOUND_A5_PLUS4);
2888
2889 step = rt2x00_get_field16(eeprom,
2890 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2891 }
2892
2893 /*
2894 * Check if temperature compensation is supported.
2895 */
bf7e1abe 2896 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 2897 return 0;
2898
2899 /*
2900 * Read current TSSI (BBP 49).
2901 */
2902 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2903
2904 /*
2905 * Compare TSSI value (BBP49) with the compensation boundaries
2906 * from the EEPROM and increase or decrease tx power.
2907 */
2908 for (i = 0; i <= 3; i++) {
2909 if (current_tssi > tssi_bounds[i])
2910 break;
2911 }
2912
2913 if (i == 4) {
2914 for (i = 8; i >= 5; i--) {
2915 if (current_tssi < tssi_bounds[i])
2916 break;
2917 }
2918 }
2919
2920 return (i - 4) * step;
2921}
2922
e90c54b2
RJH		 2923static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2924 enum ieee80211_band band)
2925{
2926 u16 eeprom;
2927 u8 comp_en;
2928 u8 comp_type;
75faae8b 2929 int comp_value = 0;
e90c54b2 2930
3e38d3da 2931 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 2932
75faae8b
HS		 2933 /*
2934 * HT40 compensation not required.
2935 */
2936 if (eeprom == 0xffff ||
2937 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2938 return 0;
2939
2940 if (band == IEEE80211_BAND_2GHZ) {
2941 comp_en = rt2x00_get_field16(eeprom,
2942 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2943 if (comp_en) {
2944 comp_type = rt2x00_get_field16(eeprom,
2945 EEPROM_TXPOWER_DELTA_TYPE_2G);
2946 comp_value = rt2x00_get_field16(eeprom,
2947 EEPROM_TXPOWER_DELTA_VALUE_2G);
2948 if (!comp_type)
2949 comp_value = -comp_value;
2950 }
2951 } else {
2952 comp_en = rt2x00_get_field16(eeprom,
2953 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2954 if (comp_en) {
2955 comp_type = rt2x00_get_field16(eeprom,
2956 EEPROM_TXPOWER_DELTA_TYPE_5G);
2957 comp_value = rt2x00_get_field16(eeprom,
2958 EEPROM_TXPOWER_DELTA_VALUE_5G);
2959 if (!comp_type)
2960 comp_value = -comp_value;
2961 }
2962 }
2963
2964 return comp_value;
2965}
2966
1e4cf249
SG		 2967static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2968 int power_level, int max_power)
2969{
2970 int delta;
2971
2972 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2973 return 0;
2974
2975 /*
2976 * XXX: We don't know the maximum transmit power of our hardware since
2977 * the EEPROM doesn't expose it. We only know that we are calibrated
2978 * to 100% tx power.
2979 *
2980 * Hence, we assume the regulatory limit that cfg80211 calulated for
2981 * the current channel is our maximum and if we are requested to lower
2982 * the value we just reduce our tx power accordingly.
2983 */
2984 delta = power_level - max_power;
2985 return min(delta, 0);
2986}
2987
fa71a160
HS		 2988static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2989 enum ieee80211_band band, int power_level,
2990 u8 txpower, int delta)
e90c54b2 2991{
e90c54b2
RJH		 2992 u16 eeprom;
2993 u8 criterion;
2994 u8 eirp_txpower;
2995 u8 eirp_txpower_criterion;
2996 u8 reg_limit;
e90c54b2 2997
7dab73b3 2998 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2999 /*
3000 * Check if eirp txpower exceed txpower_limit.
3001 * We use OFDM 6M as criterion and its eirp txpower
3002 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3003 * .11b data rate need add additional 4dbm
3004 * when calculating eirp txpower.
3005 */
022138ca
GJ		 3006 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3007 1, &eeprom);
d9bceaeb
SG		 3008 criterion = rt2x00_get_field16(eeprom,
3009 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3010
3e38d3da 3011 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3012 &eeprom);
e90c54b2
RJH		 3013
3014 if (band == IEEE80211_BAND_2GHZ)
3015 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3016 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3017 else
3018 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3019 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3020
3021 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3022 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3023
3024 reg_limit = (eirp_txpower > power_level) ?
3025 (eirp_txpower - power_level) : 0;
3026 } else
3027 reg_limit = 0;
3028
19f3fa24
SG		 3029 txpower = max(0, txpower + delta - reg_limit);
3030 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3031}
3032
7a66205a
SG		 3033/*
3034 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3035 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3036 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3037 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3038 * Reference per rate transmit power values are located in the EEPROM at
3039 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3040 * current conditions (i.e. band, bandwidth, temperature, user settings).
3041 */
f4450616 3042static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
146c3b0c 3043 struct ieee80211_channel *chan,
9e33a355 3044 int power_level)
f4450616 3045{
cee2c731 3046 u8 txpower, r1;
5e846004 3047 u16 eeprom;
cee2c731
SG		 3048 u32 reg, offset;
3049 int i, is_rate_b, delta, power_ctrl;
146c3b0c 3050 enum ieee80211_band band = chan->band;
2af242e1
HS		 3051
3052 /*
7a66205a
SG		 3053 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3054 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 3055 */
3056 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 3057
9e33a355 3058 /*
7a66205a
SG		 3059 * Calculate temperature compensation. Depends on measurement of current
3060 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3061 * to temperature or maybe other factors) is smaller or bigger than
3062 * expected. We adjust it, based on TSSI reference and boundaries values
3063 * provided in EEPROM.
9e33a355
HS		 3064 */
3065 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 3066
1e4cf249 3067 /*
7a66205a
SG		 3068 * Decrease power according to user settings, on devices with unknown
3069 * maximum tx power. For other devices we take user power_level into
3070 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 3071 */
3072 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3073 chan->max_power);
3074
5e846004 3075 /*
cee2c731
SG		 3076 * BBP_R1 controls TX power for all rates, it allow to set the following
3077 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3078 *
3079 * TODO: we do not use +6 dBm option to do not increase power beyond
3080 * regulatory limit, however this could be utilized for devices with
3081 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 3082 *
3083 * TODO: add different temperature compensation code for RT3290 & RT5390
3084 * to allow to use BBP_R1 for those chips.
3085 */
3086 if (!rt2x00_rt(rt2x00dev, RT3290) &&
3087 !rt2x00_rt(rt2x00dev, RT5390)) {
3088 rt2800_bbp_read(rt2x00dev, 1, &r1);
3089 if (delta <= -12) {
3090 power_ctrl = 2;
3091 delta += 12;
3092 } else if (delta <= -6) {
3093 power_ctrl = 1;
3094 delta += 6;
3095 } else {
3096 power_ctrl = 0;
3097 }
3098 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3099 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 3100 }
8c8d2017 3101
5e846004
HS		 3102 offset = TX_PWR_CFG_0;
3103
3104 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3105 /* just to be safe */
3106 if (offset > TX_PWR_CFG_4)
3107 break;
3108
3109 rt2800_register_read(rt2x00dev, offset, &reg);
3110
3111 /* read the next four txpower values */
022138ca
GJ		 3112 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3113 i, &eeprom);
5e846004 3114
e90c54b2
RJH		 3115 is_rate_b = i ? 0 : 1;
3116 /*
3117 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 3118 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 3119 * TX_PWR_CFG_4: unknown
3120 */
5e846004
HS		 3121 txpower = rt2x00_get_field16(eeprom,
3122 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3123 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3124 power_level, txpower, delta);
e90c54b2 3125 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 3126
e90c54b2
RJH		 3127 /*
3128 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 3129 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 3130 * TX_PWR_CFG_4: unknown
3131 */
5e846004
HS		 3132 txpower = rt2x00_get_field16(eeprom,
3133 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3134 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3135 power_level, txpower, delta);
e90c54b2 3136 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 3137
e90c54b2
RJH		 3138 /*
3139 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 3140 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 3141 * TX_PWR_CFG_4: unknown
3142 */
5e846004
HS		 3143 txpower = rt2x00_get_field16(eeprom,
3144 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3145 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3146 power_level, txpower, delta);
e90c54b2 3147 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 3148
e90c54b2
RJH		 3149 /*
3150 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 3151 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 3152 * TX_PWR_CFG_4: unknown
3153 */
5e846004
HS		 3154 txpower = rt2x00_get_field16(eeprom,
3155 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3156 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3157 power_level, txpower, delta);
e90c54b2 3158 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 3159
3160 /* read the next four txpower values */
022138ca
GJ		 3161 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3162 i + 1, &eeprom);
5e846004 3163
e90c54b2
RJH		 3164 is_rate_b = 0;
3165 /*
3166 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 3167 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3168 * TX_PWR_CFG_4: unknown
3169 */
5e846004
HS		 3170 txpower = rt2x00_get_field16(eeprom,
3171 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3172 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3173 power_level, txpower, delta);
e90c54b2 3174 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 3175
e90c54b2
RJH		 3176 /*
3177 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 3178 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3179 * TX_PWR_CFG_4: unknown
3180 */
5e846004
HS		 3181 txpower = rt2x00_get_field16(eeprom,
3182 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3183 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3184 power_level, txpower, delta);
e90c54b2 3185 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 3186
e90c54b2
RJH		 3187 /*
3188 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 3189 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3190 * TX_PWR_CFG_4: unknown
3191 */
5e846004
HS		 3192 txpower = rt2x00_get_field16(eeprom,
3193 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3194 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3195 power_level, txpower, delta);
e90c54b2 3196 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 3197
e90c54b2
RJH		 3198 /*
3199 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 3200 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3201 * TX_PWR_CFG_4: unknown
3202 */
5e846004
HS		 3203 txpower = rt2x00_get_field16(eeprom,
3204 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3205 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3206 power_level, txpower, delta);
e90c54b2 3207 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 3208
3209 rt2800_register_write(rt2x00dev, offset, reg);
3210
3211 /* next TX_PWR_CFG register */
3212 offset += 4;
3213 }
f4450616
BZ		 3214}
3215
9e33a355
HS		 3216void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3217{
675a0b04 3218 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 3219 rt2x00dev->tx_power);
3220}
3221EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3222
2e9c43dd
JL		 3223void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3224{
3225 u32 tx_pin;
3226 u8 rfcsr;
3227
3228 /*
3229 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3230 * designed to be controlled in oscillation frequency by a voltage
3231 * input. Maybe the temperature will affect the frequency of
3232 * oscillation to be shifted. The VCO calibration will be called
3233 * periodically to adjust the frequency to be precision.
3234 */
3235
3236 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3237 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3238 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3239
3240 switch (rt2x00dev->chip.rf) {
3241 case RF2020:
3242 case RF3020:
3243 case RF3021:
3244 case RF3022:
3245 case RF3320:
3246 case RF3052:
3247 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3248 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3249 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3250 break;
a89534ed 3251 case RF3290:
ccf91bd6 3252 case RF5360:
2e9c43dd
JL		 3253 case RF5370:
3254 case RF5372:
3255 case RF5390:
cff3d1f0 3256 case RF5392:
2e9c43dd 3257 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3258 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 3259 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3260 break;
3261 default:
3262 return;
3263 }
3264
3265 mdelay(1);
3266
3267 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3268 if (rt2x00dev->rf_channel <= 14) {
3269 switch (rt2x00dev->default_ant.tx_chain_num) {
3270 case 3:
3271 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3272 /* fall through */
3273 case 2:
3274 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3275 /* fall through */
3276 case 1:
3277 default:
3278 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3279 break;
3280 }
3281 } else {
3282 switch (rt2x00dev->default_ant.tx_chain_num) {
3283 case 3:
3284 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3285 /* fall through */
3286 case 2:
3287 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3288 /* fall through */
3289 case 1:
3290 default:
3291 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3292 break;
3293 }
3294 }
3295 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3296
3297}
3298EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3299
f4450616
BZ		 3300static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3301 struct rt2x00lib_conf *libconf)
3302{
3303 u32 reg;
3304
3305 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3306 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3307 libconf->conf->short_frame_max_tx_count);
3308 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3309 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 3310 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3311}
3312
3313static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3314 struct rt2x00lib_conf *libconf)
3315{
3316 enum dev_state state =
3317 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3318 STATE_SLEEP : STATE_AWAKE;
3319 u32 reg;
3320
3321 if (state == STATE_SLEEP) {
3322 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3323
3324 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3325 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3326 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3327 libconf->conf->listen_interval - 1);
3328 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3329 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3330
3331 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3332 } else {
f4450616
BZ		 3333 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3334 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3335 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3336 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3337 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 3338
3339 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 3340 }
3341}
3342
3343void rt2800_config(struct rt2x00_dev *rt2x00dev,
3344 struct rt2x00lib_conf *libconf,
3345 const unsigned int flags)
3346{
3347 /* Always recalculate LNA gain before changing configuration */
3348 rt2800_config_lna_gain(rt2x00dev, libconf);
3349
e90c54b2 3350 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 3351 rt2800_config_channel(rt2x00dev, libconf->conf,
3352 &libconf->rf, &libconf->channel);
675a0b04 3353 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3354 libconf->conf->power_level);
e90c54b2 3355 }
f4450616 3356 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 3357 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3358 libconf->conf->power_level);
f4450616
BZ		 3359 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3360 rt2800_config_retry_limit(rt2x00dev, libconf);
3361 if (flags & IEEE80211_CONF_CHANGE_PS)
3362 rt2800_config_ps(rt2x00dev, libconf);
3363}
3364EXPORT_SYMBOL_GPL(rt2800_config);
3365
3366/*
3367 * Link tuning
3368 */
3369void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3370{
3371 u32 reg;
3372
3373 /*
3374 * Update FCS error count from register.
3375 */
3376 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3377 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3378}
3379EXPORT_SYMBOL_GPL(rt2800_link_stats);
3380
3381static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3382{
8c6728b0
GW		 3383 u8 vgc;
3384
f4450616 3385 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 3386 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3387 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3388 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3389 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 3390 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 3391 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884 3392 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 3393 rt2x00_rt(rt2x00dev, RT5392) ||
3394 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 3395 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3396 else
3397 vgc = 0x2e + rt2x00dev->lna_gain;
3398 } else { /* 5GHZ band */
d961e447
GW		 3399 if (rt2x00_rt(rt2x00dev, RT3572))
3400 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 3401 else if (rt2x00_rt(rt2x00dev, RT5592))
3402 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 3403 else {
3404 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3405 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3406 else
3407 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3408 }
f4450616
BZ		 3409 }
3410
8c6728b0 3411 return vgc;
f4450616
BZ		 3412}
3413
3414static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3415 struct link_qual *qual, u8 vgc_level)
3416{
3417 if (qual->vgc_level != vgc_level) {
3d81535e
SG		 3418 if (rt2x00_rt(rt2x00dev, RT5592)) {
3419 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3420 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3421 } else
3422 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
f4450616
BZ		 3423 qual->vgc_level = vgc_level;
3424 qual->vgc_level_reg = vgc_level;
3425 }
3426}
3427
3428void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3429{
3430 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3431}
3432EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3433
3434void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3435 const u32 count)
3436{
3d81535e
SG		 3437 u8 vgc;
3438
8d0c9b65 3439 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 3440 return;
f4450616 3441 /*
3d81535e
SG		 3442 * When RSSI is better then -80 increase VGC level with 0x10, except
3443 * for rt5592 chip.
f4450616 3444 */
3d81535e
SG		 3445
3446 vgc = rt2800_get_default_vgc(rt2x00dev);
3447
3448 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3449 vgc += 0x20;
3450 else if (qual->rssi > -80)
3451 vgc += 0x10;
3452
3453 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 3454}
3455EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 3456
3457/*
3458 * Initialization functions.
3459 */
b9a07ae9 3460static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3461{
3462 u32 reg;
d5385bfc 3463 u16 eeprom;
fcf51541 3464 unsigned int i;
e3a896b9 3465 int ret;
fcf51541 3466
f7b395e9 3467 rt2800_disable_wpdma(rt2x00dev);
a9dce149 3468
e3a896b9
GW		 3469 ret = rt2800_drv_init_registers(rt2x00dev);
3470 if (ret)
3471 return ret;
fcf51541
BZ		 3472
3473 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3474 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3475 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3476 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3477 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3478 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3479
3480 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3481 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3482 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3483 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3484 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3485 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3486
3487 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3488 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3489
3490 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3491
3492 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 3493 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 3494 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3495 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3496 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3497 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3498 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3499 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3500
a9dce149
GW		 3501 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3502
3503 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3504 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3505 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3506 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3507
a89534ed
WH		 3508 if (rt2x00_rt(rt2x00dev, RT3290)) {
3509 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3510 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3511 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3512 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3513 }
3514
3515 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3516 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3517 rt2x00_set_field32(&reg, LDO0_EN, 1);
3518 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3519 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3520 }
3521
3522 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3523 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3524 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3525 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3526 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3527
3528 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3529 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3530 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3531
3532 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3533 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3534 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3535 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3536 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3537 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3538
3539 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3540 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3541 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3542 }
3543
64522957 3544 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3545 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3546 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 3547 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 3548
3549 if (rt2x00_rt(rt2x00dev, RT3290))
3550 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3551 0x00000404);
3552 else
3553 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3554 0x00000400);
3555
fcf51541 3556 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 3557 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3558 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3559 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 3560 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
3561 &eeprom);
38c8a566 3562 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3563 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3564 0x0000002c);
3565 else
3566 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3567 0x0000000f);
3568 } else {
3569 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3570 }
d5385bfc 3571 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 3572 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 3573
3574 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3575 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3576 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3577 } else {
3578 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3579 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3580 }
c295a81d
HS		 3581 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3582 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3583 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 3584 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 3585 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3586 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3587 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3588 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 3589 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3590 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3591 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884 3592 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 3593 rt2x00_rt(rt2x00dev, RT5392) ||
3594 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 3595 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3596 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3597 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 3598 } else {
3599 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3600 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3601 }
3602
3603 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3604 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3605 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3606 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3607 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3608 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3609 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3610 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3611 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3612 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3613
3614 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3615 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 3616 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 3617 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3618 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3619
3620 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3621 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 3622 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 3623 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 3624 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 3625 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3626 else
3627 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3628 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3629 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3630 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3631
a9dce149
GW		 3632 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3633 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3634 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3635 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3636 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3637 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3638 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3639 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3640 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3641
fcf51541
BZ		 3642 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3643
a9dce149
GW		 3644 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3645 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3646 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3647 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3648 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3649 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3650 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3651 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3652
fcf51541
BZ		 3653 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3654 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 3655 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 3656 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3657 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 3658 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 3659 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3660 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3661 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3662
3663 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 3664 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3665 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3666 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3667 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3668 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3669 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3670 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3671 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3672 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3673 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3674 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3675
3676 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 3677 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3678 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3679 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3680 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3682 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3683 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3684 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3685 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3686 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3687 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3688
3689 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3690 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3691 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3692 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3693 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3694 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3695 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3696 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3697 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3698 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3699 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3700 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3701
3702 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3703 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 3704 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3705 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3706 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3707 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3708 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3709 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3710 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3711 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3712 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3713 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3714
3715 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3716 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3717 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3718 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3719 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3720 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3721 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3722 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3723 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3724 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3725 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3726 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3727
3728 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3729 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3730 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3731 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3732 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3733 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3734 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3735 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3736 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3737 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3738 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3739 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3740
cea90e55 3741 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 3742 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3743
3744 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3745 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3746 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3747 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3748 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3749 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3750 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3751 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3752 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3753 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3754 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3755 }
3756
961621ab
HS		 3757 /*
3758 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3759 * although it is reserved.
3760 */
3761 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3762 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3763 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3764 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3765 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3766 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3767 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3768 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3769 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3770 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3771 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3772 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3773
7641328d
SG		 3774 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3775 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 3776
3777 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3778 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3779 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3780 IEEE80211_MAX_RTS_THRESHOLD);
3781 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3782 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3783
3784 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3785
a21c2ab4
HS		 3786 /*
3787 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3788 * time should be set to 16. However, the original Ralink driver uses
3789 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3790 * connection problems with 11g + CTS protection. Hence, use the same
3791 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3792 */
a9dce149 3793 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3794 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3795 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3796 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3797 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3798 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3799 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3800
fcf51541
BZ		 3801 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3802
3803 /*
3804 * ASIC will keep garbage value after boot, clear encryption keys.
3805 */
3806 for (i = 0; i < 4; i++)
3807 rt2800_register_write(rt2x00dev,
3808 SHARED_KEY_MODE_ENTRY(i), 0);
3809
3810 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3811 rt2800_config_wcid(rt2x00dev, NULL, i);
3812 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3813 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3814 }
3815
3816 /*
3817 * Clear all beacons
fcf51541 3818 */
69cf36a4
HS		 3819 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3820 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3821 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3822 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3823 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3824 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3825 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3826 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3827
cea90e55 3828 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3829 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3830 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3831 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3832 } else if (rt2x00_is_pcie(rt2x00dev)) {
3833 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3834 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3835 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3836 }
3837
3838 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3839 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3840 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3841 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3842 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3843 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3844 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3845 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3846 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3847 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3848
3849 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3850 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3851 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3852 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3853 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3854 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3855 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3856 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3857 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3858 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3859
3860 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3861 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3862 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3863 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3864 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3865 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3866 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3867 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3868 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3869 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3870
3871 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3872 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3873 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3874 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3875 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3876 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3877
47ee3eb1
HS		 3878 /*
3879 * Do not force the BA window size, we use the TXWI to set it
3880 */
3881 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3882 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3883 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3884 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3885
fcf51541
BZ		 3886 /*
3887 * We must clear the error counters.
3888 * These registers are cleared on read,
3889 * so we may pass a useless variable to store the value.
3890 */
3891 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3892 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3893 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3894 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3895 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3896 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3897
9f926fb5
HS		 3898 /*
3899 * Setup leadtime for pre tbtt interrupt to 6ms
3900 */
3901 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3902 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3903 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3904
977206d7
HS		 3905 /*
3906 * Set up channel statistics timer
3907 */
3908 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3909 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3910 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3911 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3912 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3913 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3914 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3915
fcf51541
BZ		 3916 return 0;
3917}
fcf51541
BZ		 3918
3919static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3920{
3921 unsigned int i;
3922 u32 reg;
3923
3924 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3925 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3926 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3927 return 0;
3928
3929 udelay(REGISTER_BUSY_DELAY);
3930 }
3931
ec9c4989 3932 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 3933 return -EACCES;
3934}
3935
3936static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3937{
3938 unsigned int i;
3939 u8 value;
3940
3941 /*
3942 * BBP was enabled after firmware was loaded,
3943 * but we need to reactivate it now.
3944 */
3945 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3946 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3947 msleep(1);
3948
3949 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3950 rt2800_bbp_read(rt2x00dev, 0, &value);
3951 if ((value != 0xff) && (value != 0x00))
3952 return 0;
3953 udelay(REGISTER_BUSY_DELAY);
3954 }
3955
ec9c4989 3956 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 3957 return -EACCES;
3958}
3959
a7bbbe5c
SG		 3960static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3961{
3962 u8 value;
3963
3964 rt2800_bbp_read(rt2x00dev, 4, &value);
3965 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3966 rt2800_bbp_write(rt2x00dev, 4, value);
3967}
3968
c2675487
SG		 3969static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3970{
3971 rt2800_bbp_write(rt2x00dev, 142, 1);
3972 rt2800_bbp_write(rt2x00dev, 143, 57);
3973}
3974
a7bbbe5c
SG		 3975static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3976{
3977 const u8 glrt_table[] = {
3978 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3979 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3980 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3981 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3982 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3983 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3985 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3986 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3987 };
3988 int i;
3989
3990 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3991 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3992 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3993 }
3994};
3995
624708b8 3996static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 3997{
3998 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3999 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4000 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4001 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4002 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4003 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4004 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4005 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4006 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4007 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4008 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4009 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4010 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4011 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4012 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4013 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4014}
4015
5df1ff3a
SG		 4016static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
4017{
4018 u16 eeprom;
4019 u8 value;
4020
4021 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 4022 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 4023 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4024 value |= 0x20;
4025 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4026 value &= ~0x02;
4027 rt2800_bbp_write(rt2x00dev, 138, value);
4028}
4029
dae62957
SG		 4030static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
4031{
b2f8e0bd 4032 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4033
4034 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4035 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4036
4037 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4038 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4039
4040 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4041
4042 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4043 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 4044
4045 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4046
4047 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4048
4049 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4050
4051 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4052
4053 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4054
4055 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4056
4057 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4058
4059 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 4060
4061 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 4062}
4063
39ab3e8b
SG		 4064static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
4065{
e379de12
SG		 4066 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4067 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4068
4069 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4070 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4071 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4072 } else {
4073 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4074 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4075 }
8d97be38
SG		 4076
4077 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4078
4079 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4080
4081 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4082
4083 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4084
4085 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4086 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4087 else
4088 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4089
4090 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4091
4092 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4093
4094 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4095
4096 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4097
4098 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4099
4100 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 4101}
4102
4103static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
4104{
e379de12
SG		 4105 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4106 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4107
4108 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4109 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4110
4111 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4112
4113 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4114 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4115 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4116
4117 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4118
4119 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4120
4121 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4122
4123 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4124
4125 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4126
4127 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4128
4129 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4130 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4131 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
4132 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4133 else
4134 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4135
4136 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4137
4138 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4139
4140 if (rt2x00_rt(rt2x00dev, RT3071) ||
4141 rt2x00_rt(rt2x00dev, RT3090))
4142 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4143}
4144
4145static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4146{
6addb24e
SG		 4147 u8 value;
4148
c3223573 4149 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4150
4151 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4152
4153 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4154 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4155
4156 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4157
4158 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4159 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4160 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4161 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4162
4163 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 4164
4165 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4166
4167 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4168 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4169 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4170 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4171
4172 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4173
4174 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 4175
4176 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 4177
4178 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 4179
4180 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4181
4182 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4183
4184 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4185
4186 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4187
4188 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 4189
4190 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 4191
4192 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 4193
4194 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4195 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4196 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4197 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4198 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4199 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4200 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4201 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4202 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4203 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4204
4205 rt2800_bbp_read(rt2x00dev, 47, &value);
4206 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4207 rt2800_bbp_write(rt2x00dev, 47, value);
4208
4209 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4210 rt2800_bbp_read(rt2x00dev, 3, &value);
4211 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4212 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4213 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 4214}
4215
4216static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4217{
29f3a58b
SG		 4218 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4219 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 4220
4221 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 4222
4223 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 4224
4225 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4226 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4227
4228 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4229
4230 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4231 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4232 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4233 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4234
4235 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4236
4237 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4238
4239 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4240 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4241 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4242
4243 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4244
4245 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4246
4247 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4248
4249 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 4250
4251 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 4252
4253 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4254
4255 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4256
4257 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4258
4259 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4260
4261 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 4262
4263 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 4264
4265 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 4266
4267 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 4268
4269 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4270 /* Set ITxBF timeout to 0x9c40=1000msec */
4271 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4272 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4273 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4274 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4275 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4276 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4277 /* Reprogram the inband interface to put right values in RXWI */
4278 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4279 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4280 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4281 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4282 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4283 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4284 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4285 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4286
4287 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 4288}
4289
4290static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4291{
e379de12
SG		 4292 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4293 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4294
4295 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4296 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4297
4298 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4299
4300 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4301 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4302 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4303
4304 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4305
4306 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4307
4308 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4309
4310 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4311
4312 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4313
4314 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4315
4316 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
4317 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4318 else
4319 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4320
4321 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4322
4323 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4324
4325 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4326}
4327
4328static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4329{
b2f8e0bd 4330 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4331
4332 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4333 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4334
4335 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4336 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4337
4338 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4339
4340 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4341 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4342 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4343
4344 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4345
4346 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4347
4348 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4349
4350 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4351
4352 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4353
4354 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4355
4356 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4357
4358 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4359
4360 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4361
4362 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4363}
4364
4365static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4366{
32ef8f49
SG		 4367 int ant, div_mode;
4368 u16 eeprom;
4369 u8 value;
4370
c3223573 4371 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4372
4373 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4374
4375 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4376 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4377
4378 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4379
4380 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4381 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4382 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4383 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4384
4385 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4386
4387 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4388
4389 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4390 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4391 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4392
4393 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4394
4395 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 4396
4397 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 4398
4399 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 4400
4401 if (rt2x00_rt(rt2x00dev, RT5392))
4402 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 4403
4404 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4405
4406 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 4407
4408 if (rt2x00_rt(rt2x00dev, RT5392)) {
4409 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4410 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4411 }
672d1188
SG		 4412
4413 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4414
4415 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4416
4417 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 4418
4419 if (rt2x00_rt(rt2x00dev, RT5390))
4420 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4421 else if (rt2x00_rt(rt2x00dev, RT5392))
4422 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4423 else
4424 WARN_ON(1);
f2b6777c
SG		 4425
4426 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 4427
4428 if (rt2x00_rt(rt2x00dev, RT5392)) {
4429 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4430 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4431 }
5df1ff3a
SG		 4432
4433 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 4434
3e38d3da 4435 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 4436 div_mode = rt2x00_get_field16(eeprom,
4437 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4438 ant = (div_mode == 3) ? 1 : 0;
4439
4440 /* check if this is a Bluetooth combo card */
4441 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4442 u32 reg;
4443
4444 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4445 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4446 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4447 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4448 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4449 if (ant == 0)
4450 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4451 else if (ant == 1)
4452 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4453 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4454 }
4455
4456 /* This chip has hardware antenna diversity*/
4457 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4458 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4459 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4460 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4461 }
4462
4463 rt2800_bbp_read(rt2x00dev, 152, &value);
4464 if (ant == 0)
4465 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4466 else
4467 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4468 rt2800_bbp_write(rt2x00dev, 152, value);
4469
4470 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 4471}
4472
a7bbbe5c
SG		 4473static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
4474{
4475 int ant, div_mode;
4476 u16 eeprom;
4477 u8 value;
4478
624708b8 4479 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 4480
a7bbbe5c
SG		 4481 rt2800_bbp_read(rt2x00dev, 105, &value);
4482 rt2x00_set_field8(&value, BBP105_MLD,
4483 rt2x00dev->default_ant.rx_chain_num == 2);
4484 rt2800_bbp_write(rt2x00dev, 105, value);
4485
4486 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4487
4488 rt2800_bbp_write(rt2x00dev, 20, 0x06);
4489 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4490 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4491 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
4492 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
4493 rt2800_bbp_write(rt2x00dev, 70, 0x05);
4494 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4495 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
4496 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
4497 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4498 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4499 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
4500 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4501 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4502 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4503 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4504 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4505 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4506 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
4507 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4508 /* FIXME BBP105 owerwrite */
4509 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
4510 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4511 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4512 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
4513 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
4514 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
4515
4516 /* Initialize GLRT (Generalized Likehood Radio Test) */
4517 rt2800_init_bbp_5592_glrt(rt2x00dev);
4518
4519 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4520
3e38d3da 4521 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 4522 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
4523 ant = (div_mode == 3) ? 1 : 0;
4524 rt2800_bbp_read(rt2x00dev, 152, &value);
4525 if (ant == 0) {
4526 /* Main antenna */
4527 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4528 } else {
4529 /* Auxiliary antenna */
4530 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4531 }
4532 rt2800_bbp_write(rt2x00dev, 152, value);
4533
4534 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4535 rt2800_bbp_read(rt2x00dev, 254, &value);
4536 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4537 rt2800_bbp_write(rt2x00dev, 254, value);
4538 }
4539
c2675487
SG		 4540 rt2800_init_freq_calibration(rt2x00dev);
4541
a7bbbe5c 4542 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 4543 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4544 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 4545}
4546
a1ef5039 4547static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4548{
4549 unsigned int i;
4550 u16 eeprom;
4551 u8 reg_id;
4552 u8 value;
4553
dae62957
SG		 4554 if (rt2800_is_305x_soc(rt2x00dev))
4555 rt2800_init_bbp_305x_soc(rt2x00dev);
4556
39ab3e8b
SG		 4557 switch (rt2x00dev->chip.rt) {
4558 case RT2860:
4559 case RT2872:
4560 case RT2883:
4561 rt2800_init_bbp_28xx(rt2x00dev);
4562 break;
4563 case RT3070:
4564 case RT3071:
4565 case RT3090:
4566 rt2800_init_bbp_30xx(rt2x00dev);
4567 break;
4568 case RT3290:
4569 rt2800_init_bbp_3290(rt2x00dev);
4570 break;
4571 case RT3352:
4572 rt2800_init_bbp_3352(rt2x00dev);
4573 break;
4574 case RT3390:
4575 rt2800_init_bbp_3390(rt2x00dev);
4576 break;
4577 case RT3572:
4578 rt2800_init_bbp_3572(rt2x00dev);
4579 break;
4580 case RT5390:
4581 case RT5392:
4582 rt2800_init_bbp_53xx(rt2x00dev);
4583 break;
4584 case RT5592:
a7bbbe5c 4585 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 4586 return;
a7bbbe5c
SG		 4587 }
4588
fcf51541 4589 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 4590 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
4591 &eeprom);
fcf51541
BZ		 4592
4593 if (eeprom != 0xffff && eeprom != 0x0000) {
4594 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4595 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4596 rt2800_bbp_write(rt2x00dev, reg_id, value);
4597 }
4598 }
fcf51541 4599}
fcf51541 4600
d9517f2f
SG		 4601static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
4602{
4603 u32 reg;
4604
4605 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4606 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4607 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4608}
4609
c5b3c350
SG		 4610static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
4611 u8 filter_target)
fcf51541
BZ		 4612{
4613 unsigned int i;
4614 u8 bbp;
4615 u8 rfcsr;
4616 u8 passband;
4617 u8 stopband;
4618 u8 overtuned = 0;
c5b3c350 4619 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 4620
4621 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4622
4623 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4624 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4625 rt2800_bbp_write(rt2x00dev, 4, bbp);
4626
80d184e6
RJH		 4627 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4628 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4629 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4630
fcf51541
BZ		 4631 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4632 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4633 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4634
4635 /*
4636 * Set power & frequency of passband test tone
4637 */
4638 rt2800_bbp_write(rt2x00dev, 24, 0);
4639
4640 for (i = 0; i < 100; i++) {
4641 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4642 msleep(1);
4643
4644 rt2800_bbp_read(rt2x00dev, 55, &passband);
4645 if (passband)
4646 break;
4647 }
4648
4649 /*
4650 * Set power & frequency of stopband test tone
4651 */
4652 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4653
4654 for (i = 0; i < 100; i++) {
4655 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4656 msleep(1);
4657
4658 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4659
4660 if ((passband - stopband) <= filter_target) {
4661 rfcsr24++;
4662 overtuned += ((passband - stopband) == filter_target);
4663 } else
4664 break;
4665
4666 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4667 }
4668
4669 rfcsr24 -= !!overtuned;
4670
4671 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4672 return rfcsr24;
4673}
4674
ce94ede9
SG		 4675static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
4676 const unsigned int rf_reg)
4677{
4678 u8 rfcsr;
4679
4680 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
4681 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
4682 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4683 msleep(1);
4684 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
4685 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4686}
4687
c5b3c350
SG		 4688static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
4689{
4690 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4691 u8 filter_tgt_bw20;
4692 u8 filter_tgt_bw40;
4693 u8 rfcsr, bbp;
4694
4695 /*
4696 * TODO: sync filter_tgt values with vendor driver
4697 */
4698 if (rt2x00_rt(rt2x00dev, RT3070)) {
4699 filter_tgt_bw20 = 0x16;
4700 filter_tgt_bw40 = 0x19;
4701 } else {
4702 filter_tgt_bw20 = 0x13;
4703 filter_tgt_bw40 = 0x15;
4704 }
4705
4706 drv_data->calibration_bw20 =
4707 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
4708 drv_data->calibration_bw40 =
4709 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
4710
4711 /*
4712 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4713 */
4714 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4715 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4716
4717 /*
4718 * Set back to initial state
4719 */
4720 rt2800_bbp_write(rt2x00dev, 24, 0);
4721
4722 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4723 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4724 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4725
4726 /*
4727 * Set BBP back to BW20
4728 */
4729 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4730 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4731 rt2800_bbp_write(rt2x00dev, 4, bbp);
4732}
4733
da8064c2
SG		 4734static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
4735{
4736 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4737 u8 min_gain, rfcsr, bbp;
4738 u16 eeprom;
4739
4740 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4741
4742 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4743 if (rt2x00_rt(rt2x00dev, RT3070) ||
4744 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4745 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4746 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4747 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
4748 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4749 }
4750
4751 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
4752 if (drv_data->txmixer_gain_24g >= min_gain) {
4753 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4754 drv_data->txmixer_gain_24g);
4755 }
4756
4757 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4758
4759 if (rt2x00_rt(rt2x00dev, RT3090)) {
4760 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4761 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 4762 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 4763 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4764 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4765 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4766 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4767 rt2800_bbp_write(rt2x00dev, 138, bbp);
4768 }
4769
4770 if (rt2x00_rt(rt2x00dev, RT3070)) {
4771 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4772 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4773 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4774 else
4775 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4776 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4777 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4778 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4779 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4780 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4781 rt2x00_rt(rt2x00dev, RT3090) ||
4782 rt2x00_rt(rt2x00dev, RT3390)) {
4783 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4784 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4785 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4786 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4787 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4788 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4789 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4790
4791 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4792 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4793 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4794
4795 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4796 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4797 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4798
4799 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4800 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4801 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4802 }
4803}
4804
f7df8fe5
SG		 4805static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
4806{
4807 u8 reg;
4808 u16 eeprom;
4809
4810 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4811 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 4812 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 4813 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4814 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4815 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4816 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4817 rt2800_bbp_write(rt2x00dev, 138, reg);
4818
4819 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4820 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4821 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4822
4823 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4824 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4825 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4826
4827 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4828
4829 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4830 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4831 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4832}
4833
d5374ef1
SG		 4834static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4835{
ce94ede9
SG		 4836 rt2800_rf_init_calibration(rt2x00dev, 30);
4837
d5374ef1
SG		 4838 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4839 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4840 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4841 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4842 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4843 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4844 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4845 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4846 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4847 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4848 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4849 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4850 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4851 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4852 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4853 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4854 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4855 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4856 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4857 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4858 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4859 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4860 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4861 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4862 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4863 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4864 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4865 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4866 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4867 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4868 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4869 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4870}
4871
4872static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4873{
c9a221b2
SG		 4874 u8 rfcsr;
4875 u16 eeprom;
4876 u32 reg;
4877
ce94ede9
SG		 4878 /* XXX vendor driver do this only for 3070 */
4879 rt2800_rf_init_calibration(rt2x00dev, 30);
4880
d5374ef1
SG		 4881 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4882 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4883 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4884 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4885 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4886 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4887 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4888 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4889 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4890 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4891 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4892 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4893 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4894 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4895 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4896 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4897 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4898 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4899 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 4900
4901 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4902 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4903 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4904 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4905 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4906 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4907 rt2x00_rt(rt2x00dev, RT3090)) {
4908 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4909
4910 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4911 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4912 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4913
4914 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4915 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4916 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4917 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 4918 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4919 &eeprom);
c9a221b2
SG		 4920 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4921 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4922 else
4923 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4924 }
4925 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4926
4927 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4928 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4929 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4930 }
c5b3c350
SG		 4931
4932 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 4933
4934 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4935 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4936 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
4937 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 4938
4939 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 4940 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 4941}
4942
4943static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4944{
f9cdcbb1
SG		 4945 u8 rfcsr;
4946
ce94ede9
SG		 4947 rt2800_rf_init_calibration(rt2x00dev, 2);
4948
d5374ef1
SG		 4949 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4950 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4951 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4952 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4953 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4954 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4955 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4956 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4957 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4958 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4959 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4960 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4961 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4962 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4963 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4964 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4965 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4966 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4967 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4968 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4969 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4970 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4971 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4972 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4973 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4974 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4975 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4976 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4977 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4978 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4979 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4980 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4981 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4982 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4983 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4984 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4985 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4986 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4987 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4988 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4989 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4990 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4991 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4992 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4993 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4994 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 4995
4996 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4997 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4998 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 4999
5000 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5001 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5002}
5003
5004static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
5005{
ce94ede9
SG		 5006 rt2800_rf_init_calibration(rt2x00dev, 30);
5007
d5374ef1
SG		 5008 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
5009 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
5010 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
5011 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
5012 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5013 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5014 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
5015 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5016 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5017 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5018 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
5019 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
5020 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
5021 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
5022 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
5023 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5024 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
5025 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
5026 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5027 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5028 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5029 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5030 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5031 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5032 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5033 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5034 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5035 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
5036 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
5037 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5038 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5039 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5040 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5041 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
5042 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
5043 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
5044 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
5045 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
5046 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
5047 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
5048 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
5049 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
5050 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
5051 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
5052 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
5053 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
5054 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
5055 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
5056 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
5057 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
5058 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
5059 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
5060 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
5061 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
5062 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
5063 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
5064 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
5065 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
5066 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
5067 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
5068 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
5069 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5070 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 5071
5072 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5073 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5074 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5075}
5076
5077static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
5078{
2971e66f
SG		 5079 u32 reg;
5080
ce94ede9
SG		 5081 rt2800_rf_init_calibration(rt2x00dev, 30);
5082
d5374ef1
SG		 5083 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
5084 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
5085 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5086 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
5087 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5088 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
5089 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
5090 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
5091 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
5092 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
5093 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
5094 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5095 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
5096 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
5097 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5098 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5099 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
5100 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
5101 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
5102 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
5103 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
5104 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
5105 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5106 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
5107 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5108 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
5109 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5110 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5111 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
5112 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
5113 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
5114 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 5115
5116 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5117 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5118 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 5119
5120 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 5121
5122 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
5123 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5124
5125 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5126 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5127}
5128
5129static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5130{
87d91db9
SG		 5131 u8 rfcsr;
5132 u32 reg;
5133
ce94ede9
SG		 5134 rt2800_rf_init_calibration(rt2x00dev, 30);
5135
d5374ef1
SG		 5136 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5137 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5138 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5139 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5140 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5141 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5142 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5143 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5144 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5145 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5146 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5147 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5148 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5149 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5150 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5151 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5152 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5153 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5154 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5155 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5156 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5157 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5158 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5159 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5160 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5161 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5162 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5163 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5164 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5165 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5166 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 5167
5168 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5169 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5170 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5171
5172 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5173 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5174 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5175 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5176 msleep(1);
5177 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5178 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5179 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5180 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 5181
5182 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5183 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5184 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5185}
5186
5187static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5188{
ce94ede9
SG		 5189 rt2800_rf_init_calibration(rt2x00dev, 2);
5190
d5374ef1
SG		 5191 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5192 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5193 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5194 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5195 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5196 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5197 else
5198 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5199 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5200 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5201 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5202 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5203 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5204 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5205 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5206 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5207 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5208 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5209
5210 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5211 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5212 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5213 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5214 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5215 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5216 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5217 else
5218 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
5219 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5220 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5221 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5222 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5223
5224 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5225 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5226 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5227 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5228 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5229 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5230 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5231 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5232 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5233 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5234
5235 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5236 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5237 else
5238 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
5239 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5240 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
5241 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
5242 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5243 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5244 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5245 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5246 else
5247 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
5248 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5249 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5250 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5251
5252 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5253 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5254 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5255 else
5256 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
5257 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5258 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
5259 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
5260 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5261 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5262 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
5263
5264 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5265 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5266 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
5267 else
5268 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
5269 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5270 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 5271
5272 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5273
5274 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5275}
5276
5277static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
5278{
ce94ede9
SG		 5279 rt2800_rf_init_calibration(rt2x00dev, 2);
5280
d5374ef1
SG		 5281 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
5282 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5283 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5284 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5285 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5286 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5287 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5288 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5289 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5290 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5291 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5292 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5293 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5294 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5295 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
5296 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5297 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
5298 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5299 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
5300 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
5301 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5302 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5303 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5304 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5305 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5306 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5307 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5308 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
5309 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5310 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5311 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5312 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5313 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5314 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
5315 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5316 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
5317 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5318 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5319 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
5320 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5321 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5322 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5323 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
5324 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5325 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5326 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
5327 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
5328 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
5329 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
5330 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
5331 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5332 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
5333 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
5334 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
5335 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
5336 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5337 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
5338 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
5339 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 5340
5341 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5342
5343 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5344}
5345
0c9e5fb9
SG		 5346static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
5347{
ce94ede9
SG		 5348 rt2800_rf_init_calibration(rt2x00dev, 30);
5349
0c9e5fb9
SG		 5350 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
5351 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5352 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5353 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5354 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
5355 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5356 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5357 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5358 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5359 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5360 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
5361 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
5362 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
5363 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5364 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5365 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5366 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5367 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5368 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5369 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
5370 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
5371 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5372
5373 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5374 msleep(1);
5375
5376 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 5377
c630ccf1
SG		 5378 /* Enable DC filter */
5379 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5380 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5381
f7df8fe5 5382 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 5383
5384 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
5385 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5386
5387 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 5388}
5389
074f2529 5390static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 5391{
d5374ef1
SG		 5392 if (rt2800_is_305x_soc(rt2x00dev)) {
5393 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 5394 return;
d5374ef1
SG		 5395 }
5396
5397 switch (rt2x00dev->chip.rt) {
5398 case RT3070:
5399 case RT3071:
5400 case RT3090:
5401 rt2800_init_rfcsr_30xx(rt2x00dev);
5402 break;
5403 case RT3290:
5404 rt2800_init_rfcsr_3290(rt2x00dev);
5405 break;
5406 case RT3352:
5407 rt2800_init_rfcsr_3352(rt2x00dev);
5408 break;
5409 case RT3390:
5410 rt2800_init_rfcsr_3390(rt2x00dev);
5411 break;
5412 case RT3572:
5413 rt2800_init_rfcsr_3572(rt2x00dev);
5414 break;
5415 case RT5390:
5416 rt2800_init_rfcsr_5390(rt2x00dev);
5417 break;
5418 case RT5392:
5419 rt2800_init_rfcsr_5392(rt2x00dev);
5420 break;
0c9e5fb9
SG		 5421 case RT5592:
5422 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 5423 break;
8cdd15e0 5424 }
fcf51541 5425}
b9a07ae9
ID		 5426
5427int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5428{
5429 u32 reg;
5430 u16 word;
5431
5432 /*
5433 * Initialize all registers.
5434 */
5435 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 5436 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 5437 return -EIO;
5438
5439 /*
5440 * Send signal to firmware during boot time.
5441 */
c630ccf1
SG		 5442 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5443 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5444 if (rt2x00_is_usb(rt2x00dev)) {
5445 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5446 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5447 }
5448 msleep(1);
5449
a1ef5039
SG		 5450 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
5451 rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 5452 return -EIO;
b9a07ae9 5453
a1ef5039 5454 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 5455 rt2800_init_rfcsr(rt2x00dev);
5456
b9a07ae9
ID		 5457 if (rt2x00_is_usb(rt2x00dev) &&
5458 (rt2x00_rt(rt2x00dev, RT3070) ||
5459 rt2x00_rt(rt2x00dev, RT3071) ||
5460 rt2x00_rt(rt2x00dev, RT3572))) {
5461 udelay(200);
5462 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5463 udelay(10);
5464 }
5465
5466 /*
5467 * Enable RX.
5468 */
5469 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5470 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5471 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5472 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5473
5474 udelay(50);
5475
5476 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5477 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5478 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5480 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5481 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5482
5483 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5484 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5485 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5486 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5487
5488 /*
5489 * Initialize LED control
5490 */
3e38d3da 5491 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 5492 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 5493 word & 0xff, (word >> 8) & 0xff);
5494
3e38d3da 5495 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 5496 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 5497 word & 0xff, (word >> 8) & 0xff);
5498
3e38d3da 5499 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 5500 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 5501 word & 0xff, (word >> 8) & 0xff);
5502
5503 return 0;
5504}
5505EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5506
5507void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5508{
5509 u32 reg;
5510
f7b395e9 5511 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 5512
5513 /* Wait for DMA, ignore error */
5514 rt2800_wait_wpdma_ready(rt2x00dev);
5515
5516 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5519 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 5520}
5521EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 5522
30e84034
BZ		 5523int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5524{
5525 u32 reg;
a89534ed 5526 u16 efuse_ctrl_reg;
30e84034 5527
a89534ed
WH		 5528 if (rt2x00_rt(rt2x00dev, RT3290))
5529 efuse_ctrl_reg = EFUSE_CTRL_3290;
5530 else
5531 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 5532
a89534ed 5533 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5534 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5535}
5536EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5537
5538static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5539{
5540 u32 reg;
a89534ed
WH		 5541 u16 efuse_ctrl_reg;
5542 u16 efuse_data0_reg;
5543 u16 efuse_data1_reg;
5544 u16 efuse_data2_reg;
5545 u16 efuse_data3_reg;
5546
5547 if (rt2x00_rt(rt2x00dev, RT3290)) {
5548 efuse_ctrl_reg = EFUSE_CTRL_3290;
5549 efuse_data0_reg = EFUSE_DATA0_3290;
5550 efuse_data1_reg = EFUSE_DATA1_3290;
5551 efuse_data2_reg = EFUSE_DATA2_3290;
5552 efuse_data3_reg = EFUSE_DATA3_3290;
5553 } else {
5554 efuse_ctrl_reg = EFUSE_CTRL;
5555 efuse_data0_reg = EFUSE_DATA0;
5556 efuse_data1_reg = EFUSE_DATA1;
5557 efuse_data2_reg = EFUSE_DATA2;
5558 efuse_data3_reg = EFUSE_DATA3;
5559 }
31a4cf1f
GW		 5560 mutex_lock(&rt2x00dev->csr_mutex);
5561
a89534ed 5562 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5563 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5564 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5565 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 5566 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 5567
5568 /* Wait until the EEPROM has been loaded */
a89534ed 5569 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 5570 /* Apparently the data is read from end to start */
a89534ed 5571 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 5572 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 5573 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 5574 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 5575 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 5576 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 5577 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 5578 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 5579 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 5580
5581 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 5582}
5583
a02308e9 5584int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 5585{
5586 unsigned int i;
5587
5588 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5589 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 5590
5591 return 0;
30e84034
BZ		 5592}
5593EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5594
ad417a53 5595static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5596{
77c06c2c 5597 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 5598 u16 word;
5599 u8 *mac;
5600 u8 default_lna_gain;
a02308e9 5601 int retval;
38bd7b8a 5602
ad417a53
GW		 5603 /*
5604 * Read the EEPROM.
5605 */
a02308e9
GJ		 5606 retval = rt2800_read_eeprom(rt2x00dev);
5607 if (retval)
5608 return retval;
ad417a53 5609
38bd7b8a
BZ		 5610 /*
5611 * Start validation of the data that has been read.
5612 */
3e38d3da 5613 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 5614 if (!is_valid_ether_addr(mac)) {
f4f7f414 5615 eth_random_addr(mac);
ec9c4989 5616 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 5617 }
5618
3e38d3da 5619 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 5620 if (word == 0xffff) {
38c8a566
RJH		 5621 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5622 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5623 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 5624 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 5625 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 5626 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 5627 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 5628 /*
5629 * There is a max of 2 RX streams for RT28x0 series
5630 */
38c8a566
RJH		 5631 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5632 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 5633 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 5634 }
5635
3e38d3da 5636 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 5637 if (word == 0xffff) {
38c8a566
RJH		 5638 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5639 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5640 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5641 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5642 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5643 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5644 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5645 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5646 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5647 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5648 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5649 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5650 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5651 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5652 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 5653 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 5654 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 5655 }
5656
3e38d3da 5657 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 5658 if ((word & 0x00ff) == 0x00ff) {
5659 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 5660 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 5661 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 5662 }
5663 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 5664 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5665 LED_MODE_TXRX_ACTIVITY);
5666 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 5667 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5668 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5669 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5670 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 5671 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 5672 }
5673
5674 /*
5675 * During the LNA validation we are going to use
5676 * lna0 as correct value. Note that EEPROM_LNA
5677 * is never validated.
5678 */
3e38d3da 5679 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 5680 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5681
3e38d3da 5682 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 5683 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5684 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5685 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5686 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 5687 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 5688
3e38d3da 5689 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
77c06c2c
GW		 5690 if ((word & 0x00ff) != 0x00ff) {
5691 drv_data->txmixer_gain_24g =
5692 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5693 } else {
5694 drv_data->txmixer_gain_24g = 0;
5695 }
5696
3e38d3da 5697 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 5698 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5699 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5700 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5701 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5702 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5703 default_lna_gain);
3e38d3da 5704 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 5705
3e38d3da 5706 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
77c06c2c
GW		 5707 if ((word & 0x00ff) != 0x00ff) {
5708 drv_data->txmixer_gain_5g =
5709 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5710 } else {
5711 drv_data->txmixer_gain_5g = 0;
5712 }
5713
3e38d3da 5714 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 5715 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5716 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5717 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5718 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 5719 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 5720
3e38d3da 5721 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 5722 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5723 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5724 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5725 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5726 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5727 default_lna_gain);
3e38d3da 5728 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a
BZ		 5729
5730 return 0;
5731}
38bd7b8a 5732
ad417a53 5733static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5734{
38bd7b8a
BZ		 5735 u16 value;
5736 u16 eeprom;
86868b26 5737 u16 rf;
38bd7b8a 5738
86868b26
GJ		 5739 /*
5740 * Read EEPROM word for configuration.
5741 */
3e38d3da 5742 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 5743
5744 /*
5745 * Identify RF chipset by EEPROM value
5746 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5747 * RT53xx: defined in "EEPROM_CHIP_ID" field
5748 */
5749 if (rt2x00_rt(rt2x00dev, RT3290) ||
5750 rt2x00_rt(rt2x00dev, RT5390) ||
5751 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 5752 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 5753 else
5754 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5755
5756 switch (rf) {
d331eb51
LF		 5757 case RF2820:
5758 case RF2850:
5759 case RF2720:
5760 case RF2750:
5761 case RF3020:
5762 case RF2020:
5763 case RF3021:
5764 case RF3022:
5765 case RF3052:
a89534ed 5766 case RF3290:
d331eb51 5767 case RF3320:
03839951 5768 case RF3322:
ccf91bd6 5769 case RF5360:
d331eb51 5770 case RF5370:
2ed71884 5771 case RF5372:
d331eb51 5772 case RF5390:
cff3d1f0 5773 case RF5392:
b8863f8b 5774 case RF5592:
d331eb51
LF		 5775 break;
5776 default:
ec9c4989
JP		 5777 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
5778 rf);
38bd7b8a
BZ		 5779 return -ENODEV;
5780 }
5781
86868b26
GJ		 5782 rt2x00_set_rf(rt2x00dev, rf);
5783
38bd7b8a
BZ		 5784 /*
5785 * Identify default antenna configuration.
5786 */
d96aa640 5787 rt2x00dev->default_ant.tx_chain_num =
38c8a566 5788 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 5789 rt2x00dev->default_ant.rx_chain_num =
38c8a566 5790 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 5791
3e38d3da 5792 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 5793
5794 if (rt2x00_rt(rt2x00dev, RT3070) ||
5795 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 5796 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 5797 rt2x00_rt(rt2x00dev, RT3390)) {
5798 value = rt2x00_get_field16(eeprom,
5799 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5800 switch (value) {
5801 case 0:
5802 case 1:
5803 case 2:
5804 rt2x00dev->default_ant.tx = ANTENNA_A;
5805 rt2x00dev->default_ant.rx = ANTENNA_A;
5806 break;
5807 case 3:
5808 rt2x00dev->default_ant.tx = ANTENNA_A;
5809 rt2x00dev->default_ant.rx = ANTENNA_B;
5810 break;
5811 }
5812 } else {
5813 rt2x00dev->default_ant.tx = ANTENNA_A;
5814 rt2x00dev->default_ant.rx = ANTENNA_A;
5815 }
5816
0586a11b
AA		 5817 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5818 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5819 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5820 }
5821
38bd7b8a 5822 /*
9328fdac 5823 * Determine external LNA informations.
38bd7b8a 5824 */
38c8a566 5825 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 5826 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 5827 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 5828 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 5829
5830 /*
5831 * Detect if this device has an hardware controlled radio.
5832 */
38c8a566 5833 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 5834 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 5835
fdbc7b0a
GW		 5836 /*
5837 * Detect if this device has Bluetooth co-existence.
5838 */
5839 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5840 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5841
9328fdac
GW		 5842 /*
5843 * Read frequency offset and RF programming sequence.
5844 */
3e38d3da 5845 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 5846 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5847
38bd7b8a
BZ		 5848 /*
5849 * Store led settings, for correct led behaviour.
5850 */
5851#ifdef CONFIG_RT2X00_LIB_LEDS
5852 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5853 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5854 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5855
9328fdac 5856 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 5857#endif /* CONFIG_RT2X00_LIB_LEDS */
5858
e90c54b2
RJH		 5859 /*
5860 * Check if support EIRP tx power limit feature.
5861 */
3e38d3da 5862 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 5863
5864 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5865 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 5866 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 5867
38bd7b8a
BZ		 5868 return 0;
5869}
38bd7b8a 5870
4da2933f 5871/*
55f9321a 5872 * RF value list for rt28xx
4da2933f
BZ		 5873 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5874 */
5875static const struct rf_channel rf_vals[] = {
5876 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5877 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5878 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5879 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5880 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5881 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5882 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5883 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5884 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5885 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5886 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5887 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5888 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5889 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5890
5891 /* 802.11 UNI / HyperLan 2 */
5892 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5893 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5894 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5895 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5896 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5897 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5898 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5899 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5900 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5901 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5902 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5903 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5904
5905 /* 802.11 HyperLan 2 */
5906 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5907 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5908 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5909 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5910 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5911 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5912 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5913 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5914 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5915 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5916 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5917 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5918 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5919 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5920 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5921 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5922
5923 /* 802.11 UNII */
5924 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5925 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5926 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5927 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5928 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5929 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5930 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5931 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5932 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5933 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5934 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5935
5936 /* 802.11 Japan */
5937 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5938 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5939 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5940 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5941 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5942 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5943 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5944};
5945
5946/*
55f9321a
ID		 5947 * RF value list for rt3xxx
5948 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 5949 */
55f9321a 5950static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 5951 {1, 241, 2, 2 },
5952 {2, 241, 2, 7 },
5953 {3, 242, 2, 2 },
5954 {4, 242, 2, 7 },
5955 {5, 243, 2, 2 },
5956 {6, 243, 2, 7 },
5957 {7, 244, 2, 2 },
5958 {8, 244, 2, 7 },
5959 {9, 245, 2, 2 },
5960 {10, 245, 2, 7 },
5961 {11, 246, 2, 2 },
5962 {12, 246, 2, 7 },
5963 {13, 247, 2, 2 },
5964 {14, 248, 2, 4 },
55f9321a
ID		 5965
5966 /* 802.11 UNI / HyperLan 2 */
5967 {36, 0x56, 0, 4},
5968 {38, 0x56, 0, 6},
5969 {40, 0x56, 0, 8},
5970 {44, 0x57, 0, 0},
5971 {46, 0x57, 0, 2},
5972 {48, 0x57, 0, 4},
5973 {52, 0x57, 0, 8},
5974 {54, 0x57, 0, 10},
5975 {56, 0x58, 0, 0},
5976 {60, 0x58, 0, 4},
5977 {62, 0x58, 0, 6},
5978 {64, 0x58, 0, 8},
5979
5980 /* 802.11 HyperLan 2 */
5981 {100, 0x5b, 0, 8},
5982 {102, 0x5b, 0, 10},
5983 {104, 0x5c, 0, 0},
5984 {108, 0x5c, 0, 4},
5985 {110, 0x5c, 0, 6},
5986 {112, 0x5c, 0, 8},
5987 {116, 0x5d, 0, 0},
5988 {118, 0x5d, 0, 2},
5989 {120, 0x5d, 0, 4},
5990 {124, 0x5d, 0, 8},
5991 {126, 0x5d, 0, 10},
5992 {128, 0x5e, 0, 0},
5993 {132, 0x5e, 0, 4},
5994 {134, 0x5e, 0, 6},
5995 {136, 0x5e, 0, 8},
5996 {140, 0x5f, 0, 0},
5997
5998 /* 802.11 UNII */
5999 {149, 0x5f, 0, 9},
6000 {151, 0x5f, 0, 11},
6001 {153, 0x60, 0, 1},
6002 {157, 0x60, 0, 5},
6003 {159, 0x60, 0, 7},
6004 {161, 0x60, 0, 9},
6005 {165, 0x61, 0, 1},
6006 {167, 0x61, 0, 3},
6007 {169, 0x61, 0, 5},
6008 {171, 0x61, 0, 7},
6009 {173, 0x61, 0, 9},
4da2933f
BZ		 6010};
6011
7848b231
SG		 6012static const struct rf_channel rf_vals_5592_xtal20[] = {
6013 /* Channel, N, K, mod, R */
6014 {1, 482, 4, 10, 3},
6015 {2, 483, 4, 10, 3},
6016 {3, 484, 4, 10, 3},
6017 {4, 485, 4, 10, 3},
6018 {5, 486, 4, 10, 3},
6019 {6, 487, 4, 10, 3},
6020 {7, 488, 4, 10, 3},
6021 {8, 489, 4, 10, 3},
6022 {9, 490, 4, 10, 3},
6023 {10, 491, 4, 10, 3},
6024 {11, 492, 4, 10, 3},
6025 {12, 493, 4, 10, 3},
6026 {13, 494, 4, 10, 3},
6027 {14, 496, 8, 10, 3},
6028 {36, 172, 8, 12, 1},
6029 {38, 173, 0, 12, 1},
6030 {40, 173, 4, 12, 1},
6031 {42, 173, 8, 12, 1},
6032 {44, 174, 0, 12, 1},
6033 {46, 174, 4, 12, 1},
6034 {48, 174, 8, 12, 1},
6035 {50, 175, 0, 12, 1},
6036 {52, 175, 4, 12, 1},
6037 {54, 175, 8, 12, 1},
6038 {56, 176, 0, 12, 1},
6039 {58, 176, 4, 12, 1},
6040 {60, 176, 8, 12, 1},
6041 {62, 177, 0, 12, 1},
6042 {64, 177, 4, 12, 1},
6043 {100, 183, 4, 12, 1},
6044 {102, 183, 8, 12, 1},
6045 {104, 184, 0, 12, 1},
6046 {106, 184, 4, 12, 1},
6047 {108, 184, 8, 12, 1},
6048 {110, 185, 0, 12, 1},
6049 {112, 185, 4, 12, 1},
6050 {114, 185, 8, 12, 1},
6051 {116, 186, 0, 12, 1},
6052 {118, 186, 4, 12, 1},
6053 {120, 186, 8, 12, 1},
6054 {122, 187, 0, 12, 1},
6055 {124, 187, 4, 12, 1},
6056 {126, 187, 8, 12, 1},
6057 {128, 188, 0, 12, 1},
6058 {130, 188, 4, 12, 1},
6059 {132, 188, 8, 12, 1},
6060 {134, 189, 0, 12, 1},
6061 {136, 189, 4, 12, 1},
6062 {138, 189, 8, 12, 1},
6063 {140, 190, 0, 12, 1},
6064 {149, 191, 6, 12, 1},
6065 {151, 191, 10, 12, 1},
6066 {153, 192, 2, 12, 1},
6067 {155, 192, 6, 12, 1},
6068 {157, 192, 10, 12, 1},
6069 {159, 193, 2, 12, 1},
6070 {161, 193, 6, 12, 1},
6071 {165, 194, 2, 12, 1},
6072 {184, 164, 0, 12, 1},
6073 {188, 164, 4, 12, 1},
6074 {192, 165, 8, 12, 1},
6075 {196, 166, 0, 12, 1},
6076};
6077
6078static const struct rf_channel rf_vals_5592_xtal40[] = {
6079 /* Channel, N, K, mod, R */
6080 {1, 241, 2, 10, 3},
6081 {2, 241, 7, 10, 3},
6082 {3, 242, 2, 10, 3},
6083 {4, 242, 7, 10, 3},
6084 {5, 243, 2, 10, 3},
6085 {6, 243, 7, 10, 3},
6086 {7, 244, 2, 10, 3},
6087 {8, 244, 7, 10, 3},
6088 {9, 245, 2, 10, 3},
6089 {10, 245, 7, 10, 3},
6090 {11, 246, 2, 10, 3},
6091 {12, 246, 7, 10, 3},
6092 {13, 247, 2, 10, 3},
6093 {14, 248, 4, 10, 3},
6094 {36, 86, 4, 12, 1},
6095 {38, 86, 6, 12, 1},
6096 {40, 86, 8, 12, 1},
6097 {42, 86, 10, 12, 1},
6098 {44, 87, 0, 12, 1},
6099 {46, 87, 2, 12, 1},
6100 {48, 87, 4, 12, 1},
6101 {50, 87, 6, 12, 1},
6102 {52, 87, 8, 12, 1},
6103 {54, 87, 10, 12, 1},
6104 {56, 88, 0, 12, 1},
6105 {58, 88, 2, 12, 1},
6106 {60, 88, 4, 12, 1},
6107 {62, 88, 6, 12, 1},
6108 {64, 88, 8, 12, 1},
6109 {100, 91, 8, 12, 1},
6110 {102, 91, 10, 12, 1},
6111 {104, 92, 0, 12, 1},
6112 {106, 92, 2, 12, 1},
6113 {108, 92, 4, 12, 1},
6114 {110, 92, 6, 12, 1},
6115 {112, 92, 8, 12, 1},
6116 {114, 92, 10, 12, 1},
6117 {116, 93, 0, 12, 1},
6118 {118, 93, 2, 12, 1},
6119 {120, 93, 4, 12, 1},
6120 {122, 93, 6, 12, 1},
6121 {124, 93, 8, 12, 1},
6122 {126, 93, 10, 12, 1},
6123 {128, 94, 0, 12, 1},
6124 {130, 94, 2, 12, 1},
6125 {132, 94, 4, 12, 1},
6126 {134, 94, 6, 12, 1},
6127 {136, 94, 8, 12, 1},
6128 {138, 94, 10, 12, 1},
6129 {140, 95, 0, 12, 1},
6130 {149, 95, 9, 12, 1},
6131 {151, 95, 11, 12, 1},
6132 {153, 96, 1, 12, 1},
6133 {155, 96, 3, 12, 1},
6134 {157, 96, 5, 12, 1},
6135 {159, 96, 7, 12, 1},
6136 {161, 96, 9, 12, 1},
6137 {165, 97, 1, 12, 1},
6138 {184, 82, 0, 12, 1},
6139 {188, 82, 4, 12, 1},
6140 {192, 82, 8, 12, 1},
6141 {196, 83, 0, 12, 1},
6142};
6143
ad417a53 6144static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 6145{
4da2933f
BZ		 6146 struct hw_mode_spec *spec = &rt2x00dev->spec;
6147 struct channel_info *info;
8d1331b3
ID		 6148 char *default_power1;
6149 char *default_power2;
4da2933f
BZ		 6150 unsigned int i;
6151 u16 eeprom;
7848b231 6152 u32 reg;
4da2933f 6153
93b6bd26
GW		 6154 /*
6155 * Disable powersaving as default on PCI devices.
6156 */
cea90e55 6157 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 6158 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6159
4da2933f
BZ		 6160 /*
6161 * Initialize all hw fields.
6162 */
6163 rt2x00dev->hw->flags =
4da2933f
BZ		 6164 IEEE80211_HW_SIGNAL_DBM |
6165 IEEE80211_HW_SUPPORTS_PS |
1df90809 6166 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 6167 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 6168 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 6169
5a5b6ed6
HS		 6170 /*
6171 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6172 * unless we are capable of sending the buffered frames out after the
6173 * DTIM transmission using rt2x00lib_beacondone. This will send out
6174 * multicast and broadcast traffic immediately instead of buffering it
6175 * infinitly and thus dropping it after some time.
6176 */
6177 if (!rt2x00_is_usb(rt2x00dev))
6178 rt2x00dev->hw->flags |=
6179 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 6180
4da2933f
BZ		 6181 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6182 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 6183 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 6184 EEPROM_MAC_ADDR_0));
6185
3f2bee24
HS		 6186 /*
6187 * As rt2800 has a global fallback table we cannot specify
6188 * more then one tx rate per frame but since the hw will
6189 * try several rates (based on the fallback table) we should
ba3b9e5e 6190 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 6191 * we are going to try. Otherwise mac80211 will truncate our
6192 * reported tx rates and the rc algortihm will end up with
6193 * incorrect data.
6194 */
ba3b9e5e
HS		 6195 rt2x00dev->hw->max_rates = 1;
6196 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 6197 rt2x00dev->hw->max_rate_tries = 1;
6198
3e38d3da 6199 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 6200
6201 /*
6202 * Initialize hw_mode information.
6203 */
6204 spec->supported_bands = SUPPORT_BAND_2GHZ;
6205 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6206
5122d898 6207 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 6208 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 6209 spec->num_channels = 14;
6210 spec->channels = rf_vals;
55f9321a
ID		 6211 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
6212 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 6213 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6214 spec->num_channels = ARRAY_SIZE(rf_vals);
6215 spec->channels = rf_vals;
5122d898
GW		 6216 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
6217 rt2x00_rf(rt2x00dev, RF2020) ||
6218 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 6219 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 6220 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 6221 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 6222 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 6223 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 6224 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 6225 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 6226 rt2x00_rf(rt2x00dev, RF5390) ||
6227 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 6228 spec->num_channels = 14;
6229 spec->channels = rf_vals_3x;
6230 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
6231 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6232 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
6233 spec->channels = rf_vals_3x;
7848b231
SG		 6234 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
6235 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6236
6237 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
6238 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
6239 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
6240 spec->channels = rf_vals_5592_xtal40;
6241 } else {
6242 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
6243 spec->channels = rf_vals_5592_xtal20;
6244 }
4da2933f
BZ		 6245 }
6246
53216d6a
SG		 6247 if (WARN_ON_ONCE(!spec->channels))
6248 return -ENODEV;
6249
4da2933f
BZ		 6250 /*
6251 * Initialize HT information.
6252 */
5122d898 6253 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 6254 spec->ht.ht_supported = true;
6255 else
6256 spec->ht.ht_supported = false;
6257
4da2933f 6258 spec->ht.cap =
06443e46 6259 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 6260 IEEE80211_HT_CAP_GRN_FLD |
6261 IEEE80211_HT_CAP_SGI_20 |
aa674631 6262 IEEE80211_HT_CAP_SGI_40;
22cabaa6 6263
38c8a566 6264 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 6265 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
6266
aa674631 6267 spec->ht.cap |=
38c8a566 6268 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 6269 IEEE80211_HT_CAP_RX_STBC_SHIFT;
6270
4da2933f
BZ		 6271 spec->ht.ampdu_factor = 3;
6272 spec->ht.ampdu_density = 4;
6273 spec->ht.mcs.tx_params =
6274 IEEE80211_HT_MCS_TX_DEFINED |
6275 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 6276 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 6277 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
6278
38c8a566 6279 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 6280 case 3:
6281 spec->ht.mcs.rx_mask[2] = 0xff;
6282 case 2:
6283 spec->ht.mcs.rx_mask[1] = 0xff;
6284 case 1:
6285 spec->ht.mcs.rx_mask[0] = 0xff;
6286 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
6287 break;
6288 }
6289
6290 /*
6291 * Create channel information array
6292 */
baeb2ffa 6293 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 6294 if (!info)
6295 return -ENOMEM;
6296
6297 spec->channels_info = info;
6298
3e38d3da
GJ		 6299 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6300 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 6301
6302 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 6303 info[i].default_power1 = default_power1[i];
6304 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 6305 }
6306
6307 if (spec->num_channels > 14) {
3e38d3da
GJ		 6308 default_power1 = rt2800_eeprom_addr(rt2x00dev,
6309 EEPROM_TXPOWER_A1);
6310 default_power2 = rt2800_eeprom_addr(rt2x00dev,
6311 EEPROM_TXPOWER_A2);
4da2933f
BZ		 6312
6313 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 6314 info[i].default_power1 = default_power1[i - 14];
6315 info[i].default_power2 = default_power2[i - 14];
4da2933f
BZ		 6316 }
6317 }
6318
2e9c43dd
JL		 6319 switch (rt2x00dev->chip.rf) {
6320 case RF2020:
6321 case RF3020:
6322 case RF3021:
6323 case RF3022:
6324 case RF3320:
6325 case RF3052:
a89534ed 6326 case RF3290:
ccf91bd6 6327 case RF5360:
2e9c43dd
JL		 6328 case RF5370:
6329 case RF5372:
6330 case RF5390:
cff3d1f0 6331 case RF5392:
2e9c43dd
JL		 6332 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6333 break;
6334 }
6335
4da2933f
BZ		 6336 return 0;
6337}
ad417a53 6338
cbafb601
GJ		 6339static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
6340{
6341 u32 reg;
6342 u32 rt;
6343 u32 rev;
6344
6345 if (rt2x00_rt(rt2x00dev, RT3290))
6346 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
6347 else
6348 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
6349
6350 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
6351 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
6352
6353 switch (rt) {
6354 case RT2860:
6355 case RT2872:
6356 case RT2883:
6357 case RT3070:
6358 case RT3071:
6359 case RT3090:
6360 case RT3290:
6361 case RT3352:
6362 case RT3390:
6363 case RT3572:
6364 case RT5390:
6365 case RT5392:
6366 case RT5592:
6367 break;
6368 default:
ec9c4989
JP		 6369 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6370 rt, rev);
cbafb601
GJ		 6371 return -ENODEV;
6372 }
6373
6374 rt2x00_set_rt(rt2x00dev, rt, rev);
6375
6376 return 0;
6377}
6378
ad417a53
GW		 6379int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6380{
6381 int retval;
6382 u32 reg;
6383
cbafb601
GJ		 6384 retval = rt2800_probe_rt(rt2x00dev);
6385 if (retval)
6386 return retval;
6387
ad417a53
GW		 6388 /*
6389 * Allocate eeprom data.
6390 */
6391 retval = rt2800_validate_eeprom(rt2x00dev);
6392 if (retval)
6393 return retval;
6394
6395 retval = rt2800_init_eeprom(rt2x00dev);
6396 if (retval)
6397 return retval;
6398
6399 /*
6400 * Enable rfkill polling by setting GPIO direction of the
6401 * rfkill switch GPIO pin correctly.
6402 */
6403 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6404 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6405 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6406
6407 /*
6408 * Initialize hw specifications.
6409 */
6410 retval = rt2800_probe_hw_mode(rt2x00dev);
6411 if (retval)
6412 return retval;
6413
6414 /*
6415 * Set device capabilities.
6416 */
6417 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6418 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6419 if (!rt2x00_is_usb(rt2x00dev))
6420 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6421
6422 /*
6423 * Set device requirements.
6424 */
6425 if (!rt2x00_is_soc(rt2x00dev))
6426 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6427 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6428 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6429 if (!rt2800_hwcrypt_disabled(rt2x00dev))
6430 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6431 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6432 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6433 if (rt2x00_is_usb(rt2x00dev))
6434 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6435 else {
6436 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6437 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6438 }
6439
6440 /*
6441 * Set the rssi offset.
6442 */
6443 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6444
6445 return 0;
6446}
6447EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 6448
2ce33995
BZ		 6449/*
6450 * IEEE80211 stack callback functions.
6451 */
e783619e
HS		 6452void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6453 u16 *iv16)
2ce33995
BZ		 6454{
6455 struct rt2x00_dev *rt2x00dev = hw->priv;
6456 struct mac_iveiv_entry iveiv_entry;
6457 u32 offset;
6458
6459 offset = MAC_IVEIV_ENTRY(hw_key_idx);
6460 rt2800_register_multiread(rt2x00dev, offset,
6461 &iveiv_entry, sizeof(iveiv_entry));
6462
855da5e0
JL		 6463 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6464 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 6465}
e783619e 6466EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 6467
e783619e 6468int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 6469{
6470 struct rt2x00_dev *rt2x00dev = hw->priv;
6471 u32 reg;
6472 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6473
6474 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6475 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6476 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6477
6478 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6479 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6480 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6481
6482 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6483 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6484 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6485
6486 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6487 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6488 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6489
6490 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6491 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6492 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6493
6494 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6495 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6496 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6497
6498 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6499 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6500 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6501
6502 return 0;
6503}
e783619e 6504EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 6505
8a3a3c85
EP		 6506int rt2800_conf_tx(struct ieee80211_hw *hw,
6507 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 6508 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 6509{
6510 struct rt2x00_dev *rt2x00dev = hw->priv;
6511 struct data_queue *queue;
6512 struct rt2x00_field32 field;
6513 int retval;
6514 u32 reg;
6515 u32 offset;
6516
6517 /*
6518 * First pass the configuration through rt2x00lib, that will
6519 * update the queue settings and validate the input. After that
6520 * we are free to update the registers based on the value
6521 * in the queue parameter.
6522 */
8a3a3c85 6523 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 6524 if (retval)
6525 return retval;
6526
6527 /*
6528 * We only need to perform additional register initialization
6529 * for WMM queues/
6530 */
6531 if (queue_idx >= 4)
6532 return 0;
6533
11f818e0 6534 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 6535
6536 /* Update WMM TXOP register */
6537 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6538 field.bit_offset = (queue_idx & 1) * 16;
6539 field.bit_mask = 0xffff << field.bit_offset;
6540
6541 rt2800_register_read(rt2x00dev, offset, &reg);
6542 rt2x00_set_field32(&reg, field, queue->txop);
6543 rt2800_register_write(rt2x00dev, offset, reg);
6544
6545 /* Update WMM registers */
6546 field.bit_offset = queue_idx * 4;
6547 field.bit_mask = 0xf << field.bit_offset;
6548
6549 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6550 rt2x00_set_field32(&reg, field, queue->aifs);
6551 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6552
6553 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6554 rt2x00_set_field32(&reg, field, queue->cw_min);
6555 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6556
6557 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6558 rt2x00_set_field32(&reg, field, queue->cw_max);
6559 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6560
6561 /* Update EDCA registers */
6562 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6563
6564 rt2800_register_read(rt2x00dev, offset, &reg);
6565 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6566 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6567 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6568 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6569 rt2800_register_write(rt2x00dev, offset, reg);
6570
6571 return 0;
6572}
e783619e 6573EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 6574
37a41b4a 6575u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 6576{
6577 struct rt2x00_dev *rt2x00dev = hw->priv;
6578 u64 tsf;
6579 u32 reg;
6580
6581 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6582 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6583 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6584 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6585
6586 return tsf;
6587}
e783619e 6588EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 6589
e783619e
HS		 6590int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6591 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 6592 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6593 u8 buf_size)
1df90809 6594{
af35323d 6595 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 6596 int ret = 0;
6597
af35323d
HS		 6598 /*
6599 * Don't allow aggregation for stations the hardware isn't aware
6600 * of because tx status reports for frames to an unknown station
6601 * always contain wcid=255 and thus we can't distinguish between
6602 * multiple stations which leads to unwanted situations when the
6603 * hw reorders frames due to aggregation.
6604 */
6605 if (sta_priv->wcid < 0)
6606 return 1;
6607
1df90809
HS		 6608 switch (action) {
6609 case IEEE80211_AMPDU_RX_START:
6610 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 6611 /*
6612 * The hw itself takes care of setting up BlockAck mechanisms.
6613 * So, we only have to allow mac80211 to nagotiate a BlockAck
6614 * agreement. Once that is done, the hw will BlockAck incoming
6615 * AMPDUs without further setup.
6616 */
1df90809
HS		 6617 break;
6618 case IEEE80211_AMPDU_TX_START:
6619 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6620 break;
18b559d5
JB		 6621 case IEEE80211_AMPDU_TX_STOP_CONT:
6622 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6623 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 6624 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6625 break;
6626 case IEEE80211_AMPDU_TX_OPERATIONAL:
6627 break;
6628 default:
ec9c4989
JP		 6629 rt2x00_warn((struct rt2x00_dev *)hw->priv,
6630 "Unknown AMPDU action\n");
1df90809
HS		 6631 }
6632
6633 return ret;
6634}
e783619e 6635EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 6636
977206d7
HS		 6637int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6638 struct survey_info *survey)
6639{
6640 struct rt2x00_dev *rt2x00dev = hw->priv;
6641 struct ieee80211_conf *conf = &hw->conf;
6642 u32 idle, busy, busy_ext;
6643
6644 if (idx != 0)
6645 return -ENOENT;
6646
675a0b04 6647 survey->channel = conf->chandef.chan;
977206d7
HS		 6648
6649 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6650 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6651 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6652
6653 if (idle || busy) {
6654 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6655 SURVEY_INFO_CHANNEL_TIME_BUSY |
6656 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6657
6658 survey->channel_time = (idle + busy) / 1000;
6659 survey->channel_time_busy = busy / 1000;
6660 survey->channel_time_ext_busy = busy_ext / 1000;
6661 }
6662
9931df26
HS		 6663 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6664 survey->filled |= SURVEY_INFO_IN_USE;
6665
977206d7
HS		 6666 return 0;
6667
6668}
6669EXPORT_SYMBOL_GPL(rt2800_get_survey);
6670
a5ea2f02
ID		 6671MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6672MODULE_VERSION(DRV_VERSION);
6673MODULE_DESCRIPTION("Ralink RT2800 library");
6674MODULE_LICENSE("GPL");
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