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ath9k_hw: Enable WLAN RX diversity for AR9565
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
16ebd608
WH		 224static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225{
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283}
284
89297425
BZ		 285void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288{
289 u32 reg;
290
ee303e54 291 /*
cea90e55 292 * SOC devices don't support MCU requests.
ee303e54 293 */
cea90e55 294 if (rt2x00_is_soc(rt2x00dev))
ee303e54 295 return;
89297425
BZ		 296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316}
317EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 318
5ffddc49
ID		 319int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320{
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333}
334EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
67a4c1e2
GW		 336int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337{
338 unsigned int i;
339 u32 reg;
340
08e53100
HS		 341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
67a4c1e2
GW		 345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
08e53100 351 msleep(10);
67a4c1e2
GW		 352 }
353
52b8243b 354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
67a4c1e2
GW		 355 return -EACCES;
356}
357EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
f7b395e9
JK		 359void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360{
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370}
371EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
f31c9a8c
ID		 373static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374{
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403}
404
405int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407{
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
f31c9a8c 420 */
a89534ed 421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 422 fw_len = 4096;
a89534ed 423 else
f31c9a8c 424 fw_len = 8192;
f31c9a8c 425
a89534ed 426 multiple = true;
f31c9a8c
ID		 427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456}
457EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461{
462 unsigned int i;
463 u32 reg;
16ebd608
WH		 464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
f31c9a8c
ID		 471
472 /*
b9eca242
ID		 473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 475 */
b9eca242 476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 477
f31c9a8c
ID		 478 /*
479 * Wait for stable hardware.
480 */
5ffddc49 481 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 482 return -EBUSY;
f31c9a8c 483
adde5882 484 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
f31c9a8c 494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 495 }
f31c9a8c 496
b7e1d225
JK		 497 rt2800_disable_wpdma(rt2x00dev);
498
f31c9a8c
ID		 499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
4ed1dd2a
SG		 519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
f7b395e9 523 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 524
f31c9a8c
ID		 525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 530 if (rt2x00_is_usb(rt2x00dev))
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 532 msleep(1);
533
534 return 0;
535}
536EXPORT_SYMBOL_GPL(rt2800_load_firmware);
537
0c5879bc
ID		 538void rt2800_write_tx_data(struct queue_entry *entry,
539 struct txentry_desc *txdesc)
59679b91 540{
0c5879bc 541 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 542 u32 word;
543
544 /*
545 * Initialize TX Info descriptor
546 */
547 rt2x00_desc_read(txwi, 0, &word);
548 rt2x00_set_field32(&word, TXWI_W0_FRAG,
549 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 550 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
551 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 552 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
553 rt2x00_set_field32(&word, TXWI_W0_TS,
554 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
555 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
556 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 557 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
558 txdesc->u.ht.mpdu_density);
559 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
560 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 561 rt2x00_set_field32(&word, TXWI_W0_BW,
562 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
563 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
564 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 565 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 566 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
567 rt2x00_desc_write(txwi, 0, word);
568
569 rt2x00_desc_read(txwi, 1, &word);
570 rt2x00_set_field32(&word, TXWI_W1_ACK,
571 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
572 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
573 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 574 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 575 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
576 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 577 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 578 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
579 txdesc->length);
2b23cdaa 580 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 581 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 582 rt2x00_desc_write(txwi, 1, word);
583
584 /*
585 * Always write 0 to IV/EIV fields, hardware will insert the IV
586 * from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame.
590 */
591 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
592 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
593}
0c5879bc 594EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 595
ff6133be 596static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 597{
7fc41755
LT		 598 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
599 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
600 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 601 u16 eeprom;
602 u8 offset0;
603 u8 offset1;
604 u8 offset2;
605
e5ef5bad 606 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 607 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
608 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
609 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
610 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
611 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
612 } else {
613 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
614 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
615 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
616 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
617 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
618 }
619
620 /*
621 * Convert the value from the descriptor into the RSSI value
622 * If the value in the descriptor is 0, it is considered invalid
623 * and the default (extremely low) rssi value is assumed
624 */
625 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
626 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
627 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
628
629 /*
630 * mac80211 only accepts a single RSSI value. Calculating the
631 * average doesn't deliver a fair answer either since -60:-60 would
632 * be considered equally good as -50:-70 while the second is the one
633 * which gives less energy...
634 */
635 rssi0 = max(rssi0, rssi1);
7fc41755 636 return (int)max(rssi0, rssi2);
74861922
ID		 637}
638
639void rt2800_process_rxwi(struct queue_entry *entry,
640 struct rxdone_entry_desc *rxdesc)
641{
642 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 643 u32 word;
644
645 rt2x00_desc_read(rxwi, 0, &word);
646
647 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
648 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
649
650 rt2x00_desc_read(rxwi, 1, &word);
651
652 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
653 rxdesc->flags |= RX_FLAG_SHORT_GI;
654
655 if (rt2x00_get_field32(word, RXWI_W1_BW))
656 rxdesc->flags |= RX_FLAG_40MHZ;
657
658 /*
659 * Detect RX rate, always use MCS as signal type.
660 */
661 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
662 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
663 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
664
665 /*
666 * Mask of 0x8 bit to remove the short preamble flag.
667 */
668 if (rxdesc->rate_mode == RATE_MODE_CCK)
669 rxdesc->signal &= ~0x8;
670
671 rt2x00_desc_read(rxwi, 2, &word);
672
74861922
ID		 673 /*
674 * Convert descriptor AGC value to RSSI value.
675 */
676 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 677
678 /*
679 * Remove RXWI descriptor from start of buffer.
680 */
74861922 681 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 682}
683EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
684
31937c42 685void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 686{
687 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 688 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 689 struct txdone_entry_desc txdesc;
690 u32 word;
691 u16 mcs, real_mcs;
b34793ee 692 int aggr, ampdu;
14433331
HS		 693
694 /*
695 * Obtain the status about this packet.
696 */
697 txdesc.flags = 0;
14433331 698 rt2x00_desc_read(txwi, 0, &word);
b34793ee 699
14433331 700 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 701 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
702
14433331 703 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 704 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
705
706 /*
707 * If a frame was meant to be sent as a single non-aggregated MPDU
708 * but ended up in an aggregate the used tx rate doesn't correlate
709 * with the one specified in the TXWI as the whole aggregate is sent
710 * with the same rate.
711 *
712 * For example: two frames are sent to rt2x00, the first one sets
713 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
714 * and requests MCS15. If the hw aggregates both frames into one
715 * AMDPU the tx status for both frames will contain MCS7 although
716 * the frame was sent successfully.
717 *
718 * Hence, replace the requested rate with the real tx rate to not
719 * confuse the rate control algortihm by providing clearly wrong
720 * data.
721 */
5356d963 722 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 723 skbdesc->tx_rate_idx = real_mcs;
724 mcs = real_mcs;
725 }
14433331 726
f16d2db7
HS		 727 if (aggr == 1 || ampdu == 1)
728 __set_bit(TXDONE_AMPDU, &txdesc.flags);
729
14433331
HS		 730 /*
731 * Ralink has a retry mechanism using a global fallback
732 * table. We setup this fallback table to try the immediate
733 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
734 * always contains the MCS used for the last transmission, be
735 * it successful or not.
736 */
737 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
738 /*
739 * Transmission succeeded. The number of retries is
740 * mcs - real_mcs
741 */
742 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
743 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
744 } else {
745 /*
746 * Transmission failed. The number of retries is
747 * always 7 in this case (for a total number of 8
748 * frames sent).
749 */
750 __set_bit(TXDONE_FAILURE, &txdesc.flags);
751 txdesc.retry = rt2x00dev->long_retry;
752 }
753
754 /*
755 * the frame was retried at least once
756 * -> hw used fallback rates
757 */
758 if (txdesc.retry)
759 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
760
761 rt2x00lib_txdone(entry, &txdesc);
762}
763EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
764
f0194b2d
GW		 765void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
766{
767 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
769 unsigned int beacon_base;
739fd940 770 unsigned int padding_len;
d76dfc61 771 u32 orig_reg, reg;
f0194b2d
GW		 772
773 /*
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
776 */
777 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 778 orig_reg = reg;
f0194b2d
GW		 779 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
780 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
781
782 /*
783 * Add space for the TXWI in front of the skb.
784 */
b52398b6 785 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 786
787 /*
788 * Register descriptor details in skb frame descriptor.
789 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE;
793
794 /*
795 * Add the TXWI for the beacon to the skb.
796 */
0c5879bc 797 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 798
799 /*
800 * Dump beacon to userspace through debugfs.
801 */
802 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
803
804 /*
739fd940 805 * Write entire beacon with TXWI and padding to register.
f0194b2d 806 */
739fd940 807 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 808 if (padding_len && skb_pad(entry->skb, padding_len)) {
809 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */
811 entry->skb = NULL;
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
813 return;
814 }
815
f0194b2d 816 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 817 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
818 entry->skb->len + padding_len);
f0194b2d
GW		 819
820 /*
821 * Enable beaconing again.
822 */
f0194b2d
GW		 823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
826 /*
827 * Clean up beacon skb.
828 */
829 dev_kfree_skb_any(entry->skb);
830 entry->skb = NULL;
831}
50e888ea 832EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 833
69cf36a4
HS		 834static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base)
fdb87251
HS		 836{
837 int i;
838
839 /*
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon.
843 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846}
847
69cf36a4
HS		 848void rt2800_clear_beacon(struct queue_entry *entry)
849{
850 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
851 u32 reg;
852
853 /*
854 * Disable beaconing while we are reloading the beacon data,
855 * otherwise we might be sending out invalid data.
856 */
857 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
858 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
859 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
860
861 /*
862 * Clear beacon.
863 */
864 rt2800_clear_beacon_register(rt2x00dev,
865 HW_BEACON_OFFSET(entry->entry_idx));
866
867 /*
868 * Enabled beaconing again.
869 */
870 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
871 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
872}
873EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
874
f4450616
BZ		 875#ifdef CONFIG_RT2X00_LIB_DEBUGFS
876const struct rt2x00debug rt2800_rt2x00debug = {
877 .owner = THIS_MODULE,
878 .csr = {
879 .read = rt2800_register_read,
880 .write = rt2800_register_write,
881 .flags = RT2X00DEBUGFS_OFFSET,
882 .word_base = CSR_REG_BASE,
883 .word_size = sizeof(u32),
884 .word_count = CSR_REG_SIZE / sizeof(u32),
885 },
886 .eeprom = {
887 .read = rt2x00_eeprom_read,
888 .write = rt2x00_eeprom_write,
889 .word_base = EEPROM_BASE,
890 .word_size = sizeof(u16),
891 .word_count = EEPROM_SIZE / sizeof(u16),
892 },
893 .bbp = {
894 .read = rt2800_bbp_read,
895 .write = rt2800_bbp_write,
896 .word_base = BBP_BASE,
897 .word_size = sizeof(u8),
898 .word_count = BBP_SIZE / sizeof(u8),
899 },
900 .rf = {
901 .read = rt2x00_rf_read,
902 .write = rt2800_rf_write,
903 .word_base = RF_BASE,
904 .word_size = sizeof(u32),
905 .word_count = RF_SIZE / sizeof(u32),
906 },
f2bd7f16
AA		 907 .rfcsr = {
908 .read = rt2800_rfcsr_read,
909 .write = rt2800_rfcsr_write,
910 .word_base = RFCSR_BASE,
911 .word_size = sizeof(u8),
912 .word_count = RFCSR_SIZE / sizeof(u8),
913 },
f4450616
BZ		 914};
915EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
916#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
917
918int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
919{
920 u32 reg;
921
a89534ed
WH		 922 if (rt2x00_rt(rt2x00dev, RT3290)) {
923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
925 } else {
99bdf51a
GW		 926 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
927 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 928 }
f4450616
BZ		 929}
930EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
931
932#ifdef CONFIG_RT2X00_LIB_LEDS
933static void rt2800_brightness_set(struct led_classdev *led_cdev,
934 enum led_brightness brightness)
935{
936 struct rt2x00_led *led =
937 container_of(led_cdev, struct rt2x00_led, led_dev);
938 unsigned int enabled = brightness != LED_OFF;
939 unsigned int bg_mode =
940 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
941 unsigned int polarity =
942 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
943 EEPROM_FREQ_LED_POLARITY);
944 unsigned int ledmode =
945 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
946 EEPROM_FREQ_LED_MODE);
44704e5d 947 u32 reg;
f4450616 948
44704e5d
LE		 949 /* Check for SoC (SOC devices don't support MCU requests) */
950 if (rt2x00_is_soc(led->rt2x00dev)) {
951 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
952
953 /* Set LED Polarity */
954 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
955
956 /* Set LED Mode */
957 if (led->type == LED_TYPE_RADIO) {
958 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
959 enabled ? 3 : 0);
960 } else if (led->type == LED_TYPE_ASSOC) {
961 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
962 enabled ? 3 : 0);
963 } else if (led->type == LED_TYPE_QUALITY) {
964 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
965 enabled ? 3 : 0);
966 }
967
968 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
969
970 } else {
971 if (led->type == LED_TYPE_RADIO) {
972 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
973 enabled ? 0x20 : 0);
974 } else if (led->type == LED_TYPE_ASSOC) {
975 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
976 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
977 } else if (led->type == LED_TYPE_QUALITY) {
978 /*
979 * The brightness is divided into 6 levels (0 - 5),
980 * The specs tell us the following levels:
981 * 0, 1 ,3, 7, 15, 31
982 * to determine the level in a simple way we can simply
983 * work with bitshifting:
984 * (1 << level) - 1
985 */
986 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
987 (1 << brightness / (LED_FULL / 6)) - 1,
988 polarity);
989 }
f4450616
BZ		 990 }
991}
992
b3579d6a 993static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 994 struct rt2x00_led *led, enum led_type type)
995{
996 led->rt2x00dev = rt2x00dev;
997 led->type = type;
998 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 999 led->flags = LED_INITIALIZED;
1000}
f4450616
BZ		 1001#endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003/*
1004 * Configuration handlers.
1005 */
a2b1328a
HS		 1006static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007 const u8 *address,
1008 int wcid)
f4450616
BZ		 1009{
1010 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1011 u32 offset;
1012
1013 offset = MAC_WCID_ENTRY(wcid);
1014
1015 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016 if (address)
1017 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019 rt2800_register_multiwrite(rt2x00dev, offset,
1020 &wcid_entry, sizeof(wcid_entry));
1021}
1022
1023static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024{
1025 u32 offset;
1026 offset = MAC_WCID_ATTR_ENTRY(wcid);
1027 rt2800_register_write(rt2x00dev, offset, 0);
1028}
1029
1030static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031 int wcid, u32 bssidx)
1032{
1033 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034 u32 reg;
1035
1036 /*
1037 * The BSS Idx numbers is split in a main value of 3 bits,
1038 * and a extended field for adding one additional bit to the value.
1039 */
1040 rt2800_register_read(rt2x00dev, offset, &reg);
1041 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043 (bssidx & 0x8) >> 3);
1044 rt2800_register_write(rt2x00dev, offset, reg);
1045}
1046
1047static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048 struct rt2x00lib_crypto *crypto,
1049 struct ieee80211_key_conf *key)
1050{
f4450616
BZ		 1051 struct mac_iveiv_entry iveiv_entry;
1052 u32 offset;
1053 u32 reg;
1054
1055 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
e4a0ab34
ID		 1057 if (crypto->cmd == SET_KEY) {
1058 rt2800_register_read(rt2x00dev, offset, &reg);
1059 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061 /*
1062 * Both the cipher as the BSS Idx numbers are split in a main
1063 * value of 3 bits, and a extended field for adding one additional
1064 * bit to the value.
1065 */
1066 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067 (crypto->cipher & 0x7));
1068 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1070 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071 rt2800_register_write(rt2x00dev, offset, reg);
1072 } else {
a2b1328a
HS		 1073 /* Delete the cipher without touching the bssidx */
1074 rt2800_register_read(rt2x00dev, offset, &reg);
1075 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1080 }
f4450616
BZ		 1081
1082 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085 if ((crypto->cipher == CIPHER_TKIP) ||
1086 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087 (crypto->cipher == CIPHER_AES))
1088 iveiv_entry.iv[3] |= 0x20;
1089 iveiv_entry.iv[3] |= key->keyidx << 6;
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1092}
1093
1094int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095 struct rt2x00lib_crypto *crypto,
1096 struct ieee80211_key_conf *key)
1097{
1098 struct hw_key_entry key_entry;
1099 struct rt2x00_field32 field;
1100 u32 offset;
1101 u32 reg;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106 memcpy(key_entry.key, crypto->key,
1107 sizeof(key_entry.key));
1108 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109 sizeof(key_entry.tx_mic));
1110 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111 sizeof(key_entry.rx_mic));
1112
1113 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114 rt2800_register_multiwrite(rt2x00dev, offset,
1115 &key_entry, sizeof(key_entry));
1116 }
1117
1118 /*
1119 * The cipher types are stored over multiple registers
1120 * starting with SHARED_KEY_MODE_BASE each word will have
1121 * 32 bits and contains the cipher types for 2 bssidx each.
1122 * Using the correct defines correctly will cause overhead,
1123 * so just calculate the correct offset.
1124 */
1125 field.bit_offset = 4 * (key->hw_key_idx % 8);
1126 field.bit_mask = 0x7 << field.bit_offset;
1127
1128 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130 rt2800_register_read(rt2x00dev, offset, &reg);
1131 rt2x00_set_field32(&reg, field,
1132 (crypto->cmd == SET_KEY) * crypto->cipher);
1133 rt2800_register_write(rt2x00dev, offset, reg);
1134
1135 /*
1136 * Update WCID information
1137 */
a2b1328a
HS		 1138 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140 crypto->bssidx);
1141 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1142
1143 return 0;
1144}
1145EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
a2b1328a 1147static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1148{
a2b1328a 1149 struct mac_wcid_entry wcid_entry;
1ed3811c 1150 int idx;
a2b1328a 1151 u32 offset;
1ed3811c
HS		 1152
1153 /*
a2b1328a
HS		 1154 * Search for the first free WCID entry and return the corresponding
1155 * index.
1ed3811c
HS		 1156 *
1157 * Make sure the WCID starts _after_ the last possible shared key
1158 * entry (>32).
1159 *
1160 * Since parts of the pairwise key table might be shared with
1161 * the beacon frame buffers 6 & 7 we should only write into the
1162 * first 222 entries.
1163 */
1164 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1165 offset = MAC_WCID_ENTRY(idx);
1166 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167 sizeof(wcid_entry));
1168 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1169 return idx;
1170 }
a2b1328a
HS		 1171
1172 /*
1173 * Use -1 to indicate that we don't have any more space in the WCID
1174 * table.
1175 */
1ed3811c
HS		 1176 return -1;
1177}
1178
f4450616
BZ		 1179int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180 struct rt2x00lib_crypto *crypto,
1181 struct ieee80211_key_conf *key)
1182{
1183 struct hw_key_entry key_entry;
1184 u32 offset;
1185
1186 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1187 /*
1188 * Allow key configuration only for STAs that are
1189 * known by the hw.
1190 */
1191 if (crypto->wcid < 0)
f4450616 1192 return -ENOSPC;
a2b1328a 1193 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1194
1195 memcpy(key_entry.key, crypto->key,
1196 sizeof(key_entry.key));
1197 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198 sizeof(key_entry.tx_mic));
1199 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200 sizeof(key_entry.rx_mic));
1201
1202 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203 rt2800_register_multiwrite(rt2x00dev, offset,
1204 &key_entry, sizeof(key_entry));
1205 }
1206
1207 /*
1208 * Update WCID information
1209 */
a2b1328a 1210 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1211
1212 return 0;
1213}
1214EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
a2b1328a
HS		 1216int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217 struct ieee80211_sta *sta)
1218{
1219 int wcid;
1220 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222 /*
1223 * Find next free WCID.
1224 */
1225 wcid = rt2800_find_wcid(rt2x00dev);
1226
1227 /*
1228 * Store selected wcid even if it is invalid so that we can
1229 * later decide if the STA is uploaded into the hw.
1230 */
1231 sta_priv->wcid = wcid;
1232
1233 /*
1234 * No space left in the device, however, we can still communicate
1235 * with the STA -> No error.
1236 */
1237 if (wcid < 0)
1238 return 0;
1239
1240 /*
1241 * Clean up WCID attributes and write STA address to the device.
1242 */
1243 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246 rt2x00lib_get_bssidx(rt2x00dev, vif));
1247 return 0;
1248}
1249EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252{
1253 /*
1254 * Remove WCID entry, no need to clean the attributes as they will
1255 * get renewed when the WCID is reused.
1256 */
1257 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259 return 0;
1260}
1261EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
f4450616
BZ		 1263void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264 const unsigned int filter_flags)
1265{
1266 u32 reg;
1267
1268 /*
1269 * Start configuration steps.
1270 * Note that the version error will always be dropped
1271 * and broadcast frames will always be accepted since
1272 * there is no filter for it at this time.
1273 */
1274 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276 !(filter_flags & FIF_FCSFAIL));
1277 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278 !(filter_flags & FIF_PLCPFAIL));
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280 !(filter_flags & FIF_PROMISC_IN_BSS));
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284 !(filter_flags & FIF_ALLMULTI));
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288 !(filter_flags & FIF_CONTROL));
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290 !(filter_flags & FIF_CONTROL));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292 !(filter_flags & FIF_CONTROL));
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298 !(filter_flags & FIF_PSPOLL));
48839938
HS		 1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1300 !(filter_flags & FIF_CONTROL));
1301 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1302 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1303 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1304 !(filter_flags & FIF_CONTROL));
1305 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1306}
1307EXPORT_SYMBOL_GPL(rt2800_config_filter);
1308
1309void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1310 struct rt2x00intf_conf *conf, const unsigned int flags)
1311{
f4450616 1312 u32 reg;
fa8b4b22 1313 bool update_bssid = false;
f4450616
BZ		 1314
1315 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1316 /*
1317 * Enable synchronisation.
1318 */
1319 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1320 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1321 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1322
1323 if (conf->sync == TSF_SYNC_AP_NONE) {
1324 /*
1325 * Tune beacon queue transmit parameters for AP mode
1326 */
1327 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1328 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1329 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1330 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1331 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1332 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1333 } else {
1334 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1335 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1337 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1338 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1339 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1340 }
f4450616
BZ		 1341 }
1342
1343 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1344 if (flags & CONFIG_UPDATE_TYPE &&
1345 conf->sync == TSF_SYNC_AP_NONE) {
1346 /*
1347 * The BSSID register has to be set to our own mac
1348 * address in AP mode.
1349 */
1350 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1351 update_bssid = true;
1352 }
1353
c600c826
ID		 1354 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1355 reg = le32_to_cpu(conf->mac[1]);
1356 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1357 conf->mac[1] = cpu_to_le32(reg);
1358 }
f4450616
BZ		 1359
1360 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1361 conf->mac, sizeof(conf->mac));
1362 }
1363
fa8b4b22 1364 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1365 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1366 reg = le32_to_cpu(conf->bssid[1]);
1367 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1368 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1369 conf->bssid[1] = cpu_to_le32(reg);
1370 }
f4450616
BZ		 1371
1372 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1373 conf->bssid, sizeof(conf->bssid));
1374 }
1375}
1376EXPORT_SYMBOL_GPL(rt2800_config_intf);
1377
87c1915d
HS		 1378static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1379 struct rt2x00lib_erp *erp)
1380{
1381 bool any_sta_nongf = !!(erp->ht_opmode &
1382 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1383 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1384 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1385 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1386 u32 reg;
1387
1388 /* default protection rate for HT20: OFDM 24M */
1389 mm20_rate = gf20_rate = 0x4004;
1390
1391 /* default protection rate for HT40: duplicate OFDM 24M */
1392 mm40_rate = gf40_rate = 0x4084;
1393
1394 switch (protection) {
1395 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1396 /*
1397 * All STAs in this BSS are HT20/40 but there might be
1398 * STAs not supporting greenfield mode.
1399 * => Disable protection for HT transmissions.
1400 */
1401 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1402
1403 break;
1404 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1405 /*
1406 * All STAs in this BSS are HT20 or HT20/40 but there
1407 * might be STAs not supporting greenfield mode.
1408 * => Protect all HT40 transmissions.
1409 */
1410 mm20_mode = gf20_mode = 0;
1411 mm40_mode = gf40_mode = 2;
1412
1413 break;
1414 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1415 /*
1416 * Nonmember protection:
1417 * According to 802.11n we _should_ protect all
1418 * HT transmissions (but we don't have to).
1419 *
1420 * But if cts_protection is enabled we _shall_ protect
1421 * all HT transmissions using a CCK rate.
1422 *
1423 * And if any station is non GF we _shall_ protect
1424 * GF transmissions.
1425 *
1426 * We decide to protect everything
1427 * -> fall through to mixed mode.
1428 */
1429 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1430 /*
1431 * Legacy STAs are present
1432 * => Protect all HT transmissions.
1433 */
1434 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1435
1436 /*
1437 * If erp protection is needed we have to protect HT
1438 * transmissions with CCK 11M long preamble.
1439 */
1440 if (erp->cts_protection) {
1441 /* don't duplicate RTS/CTS in CCK mode */
1442 mm20_rate = mm40_rate = 0x0003;
1443 gf20_rate = gf40_rate = 0x0003;
1444 }
1445 break;
6403eab1 1446 }
87c1915d
HS		 1447
1448 /* check for STAs not supporting greenfield mode */
1449 if (any_sta_nongf)
1450 gf20_mode = gf40_mode = 2;
1451
1452 /* Update HT protection config */
1453 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1454 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1455 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1456 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1457
1458 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1459 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1460 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1461 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1462
1463 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1464 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1465 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1466 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1467
1468 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1469 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1470 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1471 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1472}
1473
02044643
HS		 1474void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1475 u32 changed)
f4450616
BZ		 1476{
1477 u32 reg;
1478
02044643
HS		 1479 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1480 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1481 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1482 !!erp->short_preamble);
1483 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1484 !!erp->short_preamble);
1485 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1486 }
f4450616 1487
02044643
HS		 1488 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1489 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1490 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1491 erp->cts_protection ? 2 : 0);
1492 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1493 }
f4450616 1494
02044643
HS		 1495 if (changed & BSS_CHANGED_BASIC_RATES) {
1496 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1497 erp->basic_rates);
1498 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1499 }
f4450616 1500
02044643
HS		 1501 if (changed & BSS_CHANGED_ERP_SLOT) {
1502 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1503 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1504 erp->slot_time);
1505 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1506
02044643
HS		 1507 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1508 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1509 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1510 }
f4450616 1511
02044643
HS		 1512 if (changed & BSS_CHANGED_BEACON_INT) {
1513 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1514 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1515 erp->beacon_int * 16);
1516 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1517 }
87c1915d
HS		 1518
1519 if (changed & BSS_CHANGED_HT)
1520 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1521}
1522EXPORT_SYMBOL_GPL(rt2800_config_erp);
1523
872834df
GW		 1524static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1525{
1526 u32 reg;
1527 u16 eeprom;
1528 u8 led_ctrl, led_g_mode, led_r_mode;
1529
1530 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1531 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1532 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1533 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1534 } else {
1535 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1536 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1537 }
1538 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1539
1540 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1541 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1542 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1543 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1544 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1545 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1546 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1547 if (led_ctrl == 0 || led_ctrl > 0x40) {
1548 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1549 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1550 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1551 } else {
1552 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1553 (led_g_mode << 2) | led_r_mode, 1);
1554 }
1555 }
1556}
1557
d96aa640
RJH		 1558static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1559 enum antenna ant)
1560{
1561 u32 reg;
1562 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1563 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1564
1565 if (rt2x00_is_pci(rt2x00dev)) {
1566 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1567 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1568 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1569 } else if (rt2x00_is_usb(rt2x00dev))
1570 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1571 eesk_pin, 0);
1572
99bdf51a
GW		 1573 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1574 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1575 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1576 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1577}
1578
f4450616
BZ		 1579void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1580{
1581 u8 r1;
1582 u8 r3;
d96aa640 1583 u16 eeprom;
f4450616
BZ		 1584
1585 rt2800_bbp_read(rt2x00dev, 1, &r1);
1586 rt2800_bbp_read(rt2x00dev, 3, &r3);
1587
872834df
GW		 1588 if (rt2x00_rt(rt2x00dev, RT3572) &&
1589 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1590 rt2800_config_3572bt_ant(rt2x00dev);
1591
f4450616
BZ		 1592 /*
1593 * Configure the TX antenna.
1594 */
d96aa640 1595 switch (ant->tx_chain_num) {
f4450616
BZ		 1596 case 1:
1597 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1598 break;
1599 case 2:
872834df
GW		 1600 if (rt2x00_rt(rt2x00dev, RT3572) &&
1601 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1602 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1603 else
1604 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1605 break;
1606 case 3:
e22557f2 1607 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1608 break;
1609 }
1610
1611 /*
1612 * Configure the RX antenna.
1613 */
d96aa640 1614 switch (ant->rx_chain_num) {
f4450616 1615 case 1:
d96aa640
RJH		 1616 if (rt2x00_rt(rt2x00dev, RT3070) ||
1617 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1618 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 1619 rt2x00_rt(rt2x00dev, RT3390)) {
1620 rt2x00_eeprom_read(rt2x00dev,
1621 EEPROM_NIC_CONF1, &eeprom);
1622 if (rt2x00_get_field16(eeprom,
1623 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1624 rt2800_set_ant_diversity(rt2x00dev,
1625 rt2x00dev->default_ant.rx);
1626 }
f4450616
BZ		 1627 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1628 break;
1629 case 2:
872834df
GW		 1630 if (rt2x00_rt(rt2x00dev, RT3572) &&
1631 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1632 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1633 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1634 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1635 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1636 } else {
1637 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1638 }
f4450616
BZ		 1639 break;
1640 case 3:
1641 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1642 break;
1643 }
1644
1645 rt2800_bbp_write(rt2x00dev, 3, r3);
1646 rt2800_bbp_write(rt2x00dev, 1, r1);
1647}
1648EXPORT_SYMBOL_GPL(rt2800_config_ant);
1649
1650static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1651 struct rt2x00lib_conf *libconf)
1652{
1653 u16 eeprom;
1654 short lna_gain;
1655
1656 if (libconf->rf.channel <= 14) {
1657 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1658 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1659 } else if (libconf->rf.channel <= 64) {
1660 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1661 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1662 } else if (libconf->rf.channel <= 128) {
1663 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1664 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1665 } else {
1666 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1667 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1668 }
1669
1670 rt2x00dev->lna_gain = lna_gain;
1671}
1672
06855ef4
GW		 1673static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1674 struct ieee80211_conf *conf,
1675 struct rf_channel *rf,
1676 struct channel_info *info)
f4450616
BZ		 1677{
1678 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1679
d96aa640 1680 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1681 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1682
d96aa640 1683 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1684 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1685 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1686 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1687 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1688
1689 if (rf->channel > 14) {
1690 /*
1691 * When TX power is below 0, we should increase it by 7 to
25985edc 1692 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1693 * However this means that values between 0 and 7 have
1694 * double meaning, and we should set a 7DBm boost flag.
1695 */
1696 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1697 (info->default_power1 >= 0));
f4450616 1698
8d1331b3
ID		 1699 if (info->default_power1 < 0)
1700 info->default_power1 += 7;
f4450616 1701
8d1331b3 1702 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1703
1704 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1705 (info->default_power2 >= 0));
f4450616 1706
8d1331b3
ID		 1707 if (info->default_power2 < 0)
1708 info->default_power2 += 7;
f4450616 1709
8d1331b3 1710 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1711 } else {
8d1331b3
ID		 1712 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1713 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1714 }
1715
1716 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1717
1718 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1719 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1720 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1721 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1722
1723 udelay(200);
1724
1725 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1726 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1727 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1728 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1729
1730 udelay(200);
1731
1732 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1733 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1734 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1735 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1736}
1737
06855ef4
GW		 1738static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1739 struct ieee80211_conf *conf,
1740 struct rf_channel *rf,
1741 struct channel_info *info)
f4450616 1742{
3a1c0128 1743 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1744 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1745
1746 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1747
1748 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1749 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1750 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1751
1752 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1753 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1754 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1755
1756 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1757 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1758 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1759
5a673964 1760 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1761 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1762 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1763
1764 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1765 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1766 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1767 if (rt2x00_rt(rt2x00dev, RT3390)) {
1768 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1769 rt2x00dev->default_ant.rx_chain_num == 1);
1770 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1771 rt2x00dev->default_ant.tx_chain_num == 1);
1772 } else {
1773 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1774 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1775 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1776 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1777
1778 switch (rt2x00dev->default_ant.tx_chain_num) {
1779 case 1:
1780 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1781 /* fall through */
1782 case 2:
1783 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1784 break;
1785 }
1786
1787 switch (rt2x00dev->default_ant.rx_chain_num) {
1788 case 1:
1789 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1790 /* fall through */
1791 case 2:
1792 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1793 break;
1794 }
1795 }
1796 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1797
3e0c7643
SG		 1798 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1799 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1800 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1801 msleep(1);
1802 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1803 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1804
f4450616
BZ		 1805 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1806 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1807 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1808
f1f12f98
SG		 1809 if (rt2x00_rt(rt2x00dev, RT3390)) {
1810 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1811 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1812 } else {
3a1c0128
GW		 1813 if (conf_is_ht40(conf)) {
1814 calib_tx = drv_data->calibration_bw40;
1815 calib_rx = drv_data->calibration_bw40;
1816 } else {
1817 calib_tx = drv_data->calibration_bw20;
1818 calib_rx = drv_data->calibration_bw20;
1819 }
f1f12f98
SG		 1820 }
1821
1822 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1823 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1824 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1825
1826 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1827 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1828 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1829
71976907 1830 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1831 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1832 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1833
1834 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1835 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1836 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1837 msleep(1);
1838 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1839 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1840}
1841
872834df
GW		 1842static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1843 struct ieee80211_conf *conf,
1844 struct rf_channel *rf,
1845 struct channel_info *info)
1846{
3a1c0128 1847 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1848 u8 rfcsr;
1849 u32 reg;
1850
1851 if (rf->channel <= 14) {
5d137dff
GW		 1852 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1853 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1854 } else {
1855 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1856 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1857 }
1858
1859 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1860 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1861
1862 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1863 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1864 if (rf->channel <= 14)
1865 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1866 else
1867 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1868 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1869
1870 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1871 if (rf->channel <= 14)
1872 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1873 else
1874 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1875 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1876
1877 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1878 if (rf->channel <= 14) {
1879 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1880 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1881 info->default_power1);
872834df
GW		 1882 } else {
1883 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1884 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1885 (info->default_power1 & 0x3) |
1886 ((info->default_power1 & 0xC) << 1));
1887 }
1888 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1889
1890 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1891 if (rf->channel <= 14) {
1892 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1893 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1894 info->default_power2);
872834df
GW		 1895 } else {
1896 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1897 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1898 (info->default_power2 & 0x3) |
1899 ((info->default_power2 & 0xC) << 1));
1900 }
1901 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1902
1903 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1904 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1905 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1906 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1907 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1908 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1909 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1910 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1911 if (rf->channel <= 14) {
1912 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1913 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1914 }
1915 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1916 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1917 } else {
1918 switch (rt2x00dev->default_ant.tx_chain_num) {
1919 case 1:
1920 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1921 case 2:
1922 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1923 break;
1924 }
1925
1926 switch (rt2x00dev->default_ant.rx_chain_num) {
1927 case 1:
1928 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1929 case 2:
1930 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1931 break;
1932 }
1933 }
1934 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1935
1936 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1937 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1938 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1939
3a1c0128
GW		 1940 if (conf_is_ht40(conf)) {
1941 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1942 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1943 } else {
1944 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1945 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1946 }
872834df
GW		 1947
1948 if (rf->channel <= 14) {
1949 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1950 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1951 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1952 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1953 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1954 rfcsr = 0x4c;
1955 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1956 drv_data->txmixer_gain_24g);
1957 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1958 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1959 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1960 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1961 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1962 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1963 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1964 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1965 } else {
58b8ae14
GW		 1966 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1967 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1968 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1969 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1970 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1971 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1972 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1973 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1974 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1975 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1976 rfcsr = 0x7a;
1977 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1978 drv_data->txmixer_gain_5g);
1979 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1980 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1981 if (rf->channel <= 64) {
1982 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1983 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1984 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1985 } else if (rf->channel <= 128) {
1986 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1987 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1988 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1989 } else {
1990 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1991 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1992 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1993 }
1994 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1995 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1996 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1997 }
1998
99bdf51a
GW		 1999 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2000 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2001 if (rf->channel <= 14)
99bdf51a 2002 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2003 else
99bdf51a
GW		 2004 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2005 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2006
2007 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2008 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2009 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2010}
60687ba7 2011
7573cb5b
SG		 2012#define POWER_BOUND 0x27
2013#define FREQ_OFFSET_BOUND 0x5f
60687ba7 2014
a89534ed
WH		 2015static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2016 struct ieee80211_conf *conf,
2017 struct rf_channel *rf,
2018 struct channel_info *info)
2019{
2020 u8 rfcsr;
2021
2022 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2023 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2024 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2025 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2026 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2027
2028 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2029 if (info->default_power1 > POWER_BOUND)
2030 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2031 else
2032 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2033 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2034
2035 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
7573cb5b
SG		 2036 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2037 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
a89534ed
WH		 2038 else
2039 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2040 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2041
2042 if (rf->channel <= 14) {
2043 if (rf->channel == 6)
2044 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2045 else
2046 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2047
2048 if (rf->channel >= 1 && rf->channel <= 6)
2049 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2050 else if (rf->channel >= 7 && rf->channel <= 11)
2051 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2052 else if (rf->channel >= 12 && rf->channel <= 14)
2053 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2054 }
2055}
2056
03839951
DG		 2057static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2058 struct ieee80211_conf *conf,
2059 struct rf_channel *rf,
2060 struct channel_info *info)
2061{
2062 u8 rfcsr;
2063
2064 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2065 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2066
2067 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2068 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2069 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2070
2071 if (info->default_power1 > POWER_BOUND)
2072 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2073 else
2074 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2075
2076 if (info->default_power2 > POWER_BOUND)
2077 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2078 else
2079 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2080
2081 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2082 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2083 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2084 else
2085 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2086
2087 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2088
2089 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2090 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2091 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2092
2093 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2094 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2095 else
2096 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2097
2098 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2099 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2100 else
2101 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2102
2103 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2104 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2105
2106 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2107
2108 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2109}
2110
60687ba7 2111static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2112 struct ieee80211_conf *conf,
2113 struct rf_channel *rf,
2114 struct channel_info *info)
2115{
2116 u8 rfcsr;
adde5882
GJ		 2117
2118 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2119 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2120 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2121 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2122 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2123
2124 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2125 if (info->default_power1 > POWER_BOUND)
2126 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2127 else
2128 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2129 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2130
cff3d1f0
ZL		 2131 if (rt2x00_rt(rt2x00dev, RT5392)) {
2132 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2133 if (info->default_power1 > POWER_BOUND)
2134 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2135 else
2136 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2137 info->default_power2);
2138 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2139 }
2140
adde5882 2141 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2142 if (rt2x00_rt(rt2x00dev, RT5392)) {
2143 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2144 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2145 }
adde5882
GJ		 2146 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2147 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2148 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2149 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2150 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2151
2152 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
7573cb5b
SG		 2153 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2154 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
adde5882
GJ		 2155 else
2156 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2157 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2158
adde5882
GJ		 2159 if (rf->channel <= 14) {
2160 int idx = rf->channel-1;
2161
fdbc7b0a 2162 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2163 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2164 /* r55/r59 value array of channel 1~14 */
2165 static const char r55_bt_rev[] = {0x83, 0x83,
2166 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2167 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2168 static const char r59_bt_rev[] = {0x0e, 0x0e,
2169 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2170 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2171
2172 rt2800_rfcsr_write(rt2x00dev, 55,
2173 r55_bt_rev[idx]);
2174 rt2800_rfcsr_write(rt2x00dev, 59,
2175 r59_bt_rev[idx]);
2176 } else {
2177 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2178 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2179 0x88, 0x88, 0x86, 0x85, 0x84};
2180
2181 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2182 }
2183 } else {
2184 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2185 static const char r55_nonbt_rev[] = {0x23, 0x23,
2186 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2187 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2188 static const char r59_nonbt_rev[] = {0x07, 0x07,
2189 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2190 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2191
2192 rt2800_rfcsr_write(rt2x00dev, 55,
2193 r55_nonbt_rev[idx]);
2194 rt2800_rfcsr_write(rt2x00dev, 59,
2195 r59_nonbt_rev[idx]);
2ed71884
JL		 2196 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2197 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2198 static const char r59_non_bt[] = {0x8f, 0x8f,
2199 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2200 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2201
2202 rt2800_rfcsr_write(rt2x00dev, 59,
2203 r59_non_bt[idx]);
2204 }
2205 }
2206 }
60687ba7
RST		 2207}
2208
f4450616
BZ		 2209static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2210 struct ieee80211_conf *conf,
2211 struct rf_channel *rf,
2212 struct channel_info *info)
2213{
2214 u32 reg;
2215 unsigned int tx_pin;
a89534ed 2216 u8 bbp, rfcsr;
f4450616 2217
46323e11 2218 if (rf->channel <= 14) {
8d1331b3
ID		 2219 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2220 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2221 } else {
8d1331b3
ID		 2222 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2223 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2224 }
2225
5aa57015
GW		 2226 switch (rt2x00dev->chip.rf) {
2227 case RF2020:
2228 case RF3020:
2229 case RF3021:
2230 case RF3022:
2231 case RF3320:
06855ef4 2232 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2233 break;
2234 case RF3052:
872834df 2235 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2236 break;
a89534ed
WH		 2237 case RF3290:
2238 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2239 break;
03839951
DG		 2240 case RF3322:
2241 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2242 break;
ccf91bd6 2243 case RF5360:
5aa57015 2244 case RF5370:
2ed71884 2245 case RF5372:
5aa57015 2246 case RF5390:
cff3d1f0 2247 case RF5392:
adde5882 2248 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2249 break;
2250 default:
06855ef4 2251 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2252 }
f4450616 2253
a89534ed 2254 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2255 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2256 rt2x00_rf(rt2x00dev, RF5360) ||
2257 rt2x00_rf(rt2x00dev, RF5370) ||
2258 rt2x00_rf(rt2x00dev, RF5372) ||
2259 rt2x00_rf(rt2x00dev, RF5390) ||
2260 rt2x00_rf(rt2x00dev, RF5392)) {
2261 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2262 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2263 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2264 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2265
2266 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2267 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2268 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2269 }
2270
f4450616
BZ		 2271 /*
2272 * Change BBP settings
2273 */
03839951
DG		 2274 if (rt2x00_rt(rt2x00dev, RT3352)) {
2275 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2276 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2277 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2278 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2279 } else {
2280 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2281 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2282 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2283 rt2800_bbp_write(rt2x00dev, 86, 0);
2284 }
f4450616
BZ		 2285
2286 if (rf->channel <= 14) {
2ed71884
JL		 2287 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2288 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2289 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2290 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2291 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2292 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2293 } else {
2294 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2295 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2296 }
f4450616
BZ		 2297 }
2298 } else {
872834df
GW		 2299 if (rt2x00_rt(rt2x00dev, RT3572))
2300 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2301 else
2302 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2303
7dab73b3 2304 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2305 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2306 else
2307 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2308 }
2309
2310 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2311 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2312 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2313 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2314 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2315
872834df
GW		 2316 if (rt2x00_rt(rt2x00dev, RT3572))
2317 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2318
f4450616
BZ		 2319 tx_pin = 0;
2320
2321 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2322 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2323 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2324 rf->channel > 14);
2325 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2326 rf->channel <= 14);
f4450616
BZ		 2327 }
2328
2329 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2330 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2331 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2333 }
2334
2335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2336 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2337 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2338 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2339 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2341 else
2342 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2343 rf->channel <= 14);
f4450616
BZ		 2344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2345
2346 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2347
872834df
GW		 2348 if (rt2x00_rt(rt2x00dev, RT3572))
2349 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2350
f4450616
BZ		 2351 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2352 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2353 rt2800_bbp_write(rt2x00dev, 4, bbp);
2354
2355 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2356 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2357 rt2800_bbp_write(rt2x00dev, 3, bbp);
2358
8d0c9b65 2359 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2360 if (conf_is_ht40(conf)) {
2361 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2362 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2363 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2364 } else {
2365 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2366 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2367 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2368 }
2369 }
2370
2371 msleep(1);
977206d7
HS		 2372
2373 /*
2374 * Clear channel statistic counters
2375 */
2376 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2377 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2378 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2379
2380 /*
2381 * Clear update flag
2382 */
2383 if (rt2x00_rt(rt2x00dev, RT3352)) {
2384 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2385 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2386 rt2800_bbp_write(rt2x00dev, 49, bbp);
2387 }
f4450616
BZ		 2388}
2389
9e33a355
HS		 2390static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2391{
2392 u8 tssi_bounds[9];
2393 u8 current_tssi;
2394 u16 eeprom;
2395 u8 step;
2396 int i;
2397
2398 /*
2399 * Read TSSI boundaries for temperature compensation from
2400 * the EEPROM.
2401 *
2402 * Array idx 0 1 2 3 4 5 6 7 8
2403 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2404 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2405 */
2406 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2407 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2408 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2409 EEPROM_TSSI_BOUND_BG1_MINUS4);
2410 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2411 EEPROM_TSSI_BOUND_BG1_MINUS3);
2412
2413 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2414 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2415 EEPROM_TSSI_BOUND_BG2_MINUS2);
2416 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2417 EEPROM_TSSI_BOUND_BG2_MINUS1);
2418
2419 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2420 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2421 EEPROM_TSSI_BOUND_BG3_REF);
2422 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2423 EEPROM_TSSI_BOUND_BG3_PLUS1);
2424
2425 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2426 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2427 EEPROM_TSSI_BOUND_BG4_PLUS2);
2428 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2429 EEPROM_TSSI_BOUND_BG4_PLUS3);
2430
2431 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2432 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2433 EEPROM_TSSI_BOUND_BG5_PLUS4);
2434
2435 step = rt2x00_get_field16(eeprom,
2436 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2437 } else {
2438 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2439 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2440 EEPROM_TSSI_BOUND_A1_MINUS4);
2441 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2442 EEPROM_TSSI_BOUND_A1_MINUS3);
2443
2444 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2445 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2446 EEPROM_TSSI_BOUND_A2_MINUS2);
2447 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2448 EEPROM_TSSI_BOUND_A2_MINUS1);
2449
2450 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2451 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2452 EEPROM_TSSI_BOUND_A3_REF);
2453 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2454 EEPROM_TSSI_BOUND_A3_PLUS1);
2455
2456 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2457 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2458 EEPROM_TSSI_BOUND_A4_PLUS2);
2459 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2460 EEPROM_TSSI_BOUND_A4_PLUS3);
2461
2462 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2463 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2464 EEPROM_TSSI_BOUND_A5_PLUS4);
2465
2466 step = rt2x00_get_field16(eeprom,
2467 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2468 }
2469
2470 /*
2471 * Check if temperature compensation is supported.
2472 */
2473 if (tssi_bounds[4] == 0xff)
2474 return 0;
2475
2476 /*
2477 * Read current TSSI (BBP 49).
2478 */
2479 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2480
2481 /*
2482 * Compare TSSI value (BBP49) with the compensation boundaries
2483 * from the EEPROM and increase or decrease tx power.
2484 */
2485 for (i = 0; i <= 3; i++) {
2486 if (current_tssi > tssi_bounds[i])
2487 break;
2488 }
2489
2490 if (i == 4) {
2491 for (i = 8; i >= 5; i--) {
2492 if (current_tssi < tssi_bounds[i])
2493 break;
2494 }
2495 }
2496
2497 return (i - 4) * step;
2498}
2499
e90c54b2
RJH		 2500static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2501 enum ieee80211_band band)
2502{
2503 u16 eeprom;
2504 u8 comp_en;
2505 u8 comp_type;
75faae8b 2506 int comp_value = 0;
e90c54b2
RJH		 2507
2508 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2509
75faae8b
HS		 2510 /*
2511 * HT40 compensation not required.
2512 */
2513 if (eeprom == 0xffff ||
2514 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2515 return 0;
2516
2517 if (band == IEEE80211_BAND_2GHZ) {
2518 comp_en = rt2x00_get_field16(eeprom,
2519 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2520 if (comp_en) {
2521 comp_type = rt2x00_get_field16(eeprom,
2522 EEPROM_TXPOWER_DELTA_TYPE_2G);
2523 comp_value = rt2x00_get_field16(eeprom,
2524 EEPROM_TXPOWER_DELTA_VALUE_2G);
2525 if (!comp_type)
2526 comp_value = -comp_value;
2527 }
2528 } else {
2529 comp_en = rt2x00_get_field16(eeprom,
2530 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2531 if (comp_en) {
2532 comp_type = rt2x00_get_field16(eeprom,
2533 EEPROM_TXPOWER_DELTA_TYPE_5G);
2534 comp_value = rt2x00_get_field16(eeprom,
2535 EEPROM_TXPOWER_DELTA_VALUE_5G);
2536 if (!comp_type)
2537 comp_value = -comp_value;
2538 }
2539 }
2540
2541 return comp_value;
2542}
2543
fa71a160
HS		 2544static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2545 enum ieee80211_band band, int power_level,
2546 u8 txpower, int delta)
e90c54b2
RJH		 2547{
2548 u32 reg;
2549 u16 eeprom;
2550 u8 criterion;
2551 u8 eirp_txpower;
2552 u8 eirp_txpower_criterion;
2553 u8 reg_limit;
e90c54b2
RJH		 2554
2555 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2556 return txpower;
2557
7dab73b3 2558 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2559 /*
2560 * Check if eirp txpower exceed txpower_limit.
2561 * We use OFDM 6M as criterion and its eirp txpower
2562 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2563 * .11b data rate need add additional 4dbm
2564 * when calculating eirp txpower.
2565 */
2566 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2567 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2568
2569 rt2x00_eeprom_read(rt2x00dev,
2570 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2571
2572 if (band == IEEE80211_BAND_2GHZ)
2573 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2574 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2575 else
2576 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2577 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2578
2579 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2580 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2581
2582 reg_limit = (eirp_txpower > power_level) ?
2583 (eirp_txpower - power_level) : 0;
2584 } else
2585 reg_limit = 0;
2586
2af242e1 2587 return txpower + delta - reg_limit;
e90c54b2
RJH		 2588}
2589
f4450616 2590static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2591 enum ieee80211_band band,
2592 int power_level)
f4450616 2593{
5e846004 2594 u8 txpower;
5e846004 2595 u16 eeprom;
e90c54b2 2596 int i, is_rate_b;
f4450616 2597 u32 reg;
f4450616 2598 u8 r1;
5e846004 2599 u32 offset;
2af242e1
HS		 2600 int delta;
2601
2602 /*
2603 * Calculate HT40 compensation delta
2604 */
2605 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2606
9e33a355
HS		 2607 /*
2608 * calculate temperature compensation delta
2609 */
2610 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2611
5e846004 2612 /*
e90c54b2 2613 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2614 */
f4450616 2615 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2616 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2617 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2618 offset = TX_PWR_CFG_0;
2619
2620 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2621 /* just to be safe */
2622 if (offset > TX_PWR_CFG_4)
2623 break;
2624
2625 rt2800_register_read(rt2x00dev, offset, &reg);
2626
2627 /* read the next four txpower values */
2628 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2629 &eeprom);
2630
e90c54b2
RJH		 2631 is_rate_b = i ? 0 : 1;
2632 /*
2633 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2634 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2635 * TX_PWR_CFG_4: unknown
2636 */
5e846004
HS		 2637 txpower = rt2x00_get_field16(eeprom,
2638 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2639 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2640 power_level, txpower, delta);
e90c54b2 2641 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2642
e90c54b2
RJH		 2643 /*
2644 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2645 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2646 * TX_PWR_CFG_4: unknown
2647 */
5e846004
HS		 2648 txpower = rt2x00_get_field16(eeprom,
2649 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2650 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2651 power_level, txpower, delta);
e90c54b2 2652 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2653
e90c54b2
RJH		 2654 /*
2655 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2656 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2657 * TX_PWR_CFG_4: unknown
2658 */
5e846004
HS		 2659 txpower = rt2x00_get_field16(eeprom,
2660 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2661 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2662 power_level, txpower, delta);
e90c54b2 2663 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2664
e90c54b2
RJH		 2665 /*
2666 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2667 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2668 * TX_PWR_CFG_4: unknown
2669 */
5e846004
HS		 2670 txpower = rt2x00_get_field16(eeprom,
2671 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2672 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2673 power_level, txpower, delta);
e90c54b2 2674 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2675
2676 /* read the next four txpower values */
2677 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2678 &eeprom);
2679
e90c54b2
RJH		 2680 is_rate_b = 0;
2681 /*
2682 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2683 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2684 * TX_PWR_CFG_4: unknown
2685 */
5e846004
HS		 2686 txpower = rt2x00_get_field16(eeprom,
2687 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2688 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2689 power_level, txpower, delta);
e90c54b2 2690 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2691
e90c54b2
RJH		 2692 /*
2693 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2694 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2695 * TX_PWR_CFG_4: unknown
2696 */
5e846004
HS		 2697 txpower = rt2x00_get_field16(eeprom,
2698 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2699 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2700 power_level, txpower, delta);
e90c54b2 2701 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2702
e90c54b2
RJH		 2703 /*
2704 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2705 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2706 * TX_PWR_CFG_4: unknown
2707 */
5e846004
HS		 2708 txpower = rt2x00_get_field16(eeprom,
2709 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2710 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2711 power_level, txpower, delta);
e90c54b2 2712 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2713
e90c54b2
RJH		 2714 /*
2715 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2716 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2717 * TX_PWR_CFG_4: unknown
2718 */
5e846004
HS		 2719 txpower = rt2x00_get_field16(eeprom,
2720 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2721 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2722 power_level, txpower, delta);
e90c54b2 2723 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2724
2725 rt2800_register_write(rt2x00dev, offset, reg);
2726
2727 /* next TX_PWR_CFG register */
2728 offset += 4;
2729 }
f4450616
BZ		 2730}
2731
9e33a355
HS		 2732void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2733{
2734 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2735 rt2x00dev->tx_power);
2736}
2737EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2738
2e9c43dd
JL		 2739void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2740{
2741 u32 tx_pin;
2742 u8 rfcsr;
2743
2744 /*
2745 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2746 * designed to be controlled in oscillation frequency by a voltage
2747 * input. Maybe the temperature will affect the frequency of
2748 * oscillation to be shifted. The VCO calibration will be called
2749 * periodically to adjust the frequency to be precision.
2750 */
2751
2752 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2753 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2754 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2755
2756 switch (rt2x00dev->chip.rf) {
2757 case RF2020:
2758 case RF3020:
2759 case RF3021:
2760 case RF3022:
2761 case RF3320:
2762 case RF3052:
2763 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2764 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2765 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2766 break;
a89534ed 2767 case RF3290:
ccf91bd6 2768 case RF5360:
2e9c43dd
JL		 2769 case RF5370:
2770 case RF5372:
2771 case RF5390:
cff3d1f0 2772 case RF5392:
2e9c43dd
JL		 2773 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2774 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2775 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2776 break;
2777 default:
2778 return;
2779 }
2780
2781 mdelay(1);
2782
2783 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2784 if (rt2x00dev->rf_channel <= 14) {
2785 switch (rt2x00dev->default_ant.tx_chain_num) {
2786 case 3:
2787 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2788 /* fall through */
2789 case 2:
2790 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2791 /* fall through */
2792 case 1:
2793 default:
2794 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2795 break;
2796 }
2797 } else {
2798 switch (rt2x00dev->default_ant.tx_chain_num) {
2799 case 3:
2800 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2801 /* fall through */
2802 case 2:
2803 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2804 /* fall through */
2805 case 1:
2806 default:
2807 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2808 break;
2809 }
2810 }
2811 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2812
2813}
2814EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2815
f4450616
BZ		 2816static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2817 struct rt2x00lib_conf *libconf)
2818{
2819 u32 reg;
2820
2821 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2822 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2823 libconf->conf->short_frame_max_tx_count);
2824 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2825 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2826 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2827}
2828
2829static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2830 struct rt2x00lib_conf *libconf)
2831{
2832 enum dev_state state =
2833 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2834 STATE_SLEEP : STATE_AWAKE;
2835 u32 reg;
2836
2837 if (state == STATE_SLEEP) {
2838 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2839
2840 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2841 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2842 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2843 libconf->conf->listen_interval - 1);
2844 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2845 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2846
2847 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2848 } else {
f4450616
BZ		 2849 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2850 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2851 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2852 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2853 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2854
2855 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2856 }
2857}
2858
2859void rt2800_config(struct rt2x00_dev *rt2x00dev,
2860 struct rt2x00lib_conf *libconf,
2861 const unsigned int flags)
2862{
2863 /* Always recalculate LNA gain before changing configuration */
2864 rt2800_config_lna_gain(rt2x00dev, libconf);
2865
e90c54b2 2866 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2867 rt2800_config_channel(rt2x00dev, libconf->conf,
2868 &libconf->rf, &libconf->channel);
9e33a355
HS		 2869 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2870 libconf->conf->power_level);
e90c54b2 2871 }
f4450616 2872 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2873 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2874 libconf->conf->power_level);
f4450616
BZ		 2875 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2876 rt2800_config_retry_limit(rt2x00dev, libconf);
2877 if (flags & IEEE80211_CONF_CHANGE_PS)
2878 rt2800_config_ps(rt2x00dev, libconf);
2879}
2880EXPORT_SYMBOL_GPL(rt2800_config);
2881
2882/*
2883 * Link tuning
2884 */
2885void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2886{
2887 u32 reg;
2888
2889 /*
2890 * Update FCS error count from register.
2891 */
2892 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2893 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2894}
2895EXPORT_SYMBOL_GPL(rt2800_link_stats);
2896
2897static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2898{
2899 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2900 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2901 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2902 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 2903 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 2904 rt2x00_rt(rt2x00dev, RT3390) ||
2ed71884
JL		 2905 rt2x00_rt(rt2x00dev, RT5390) ||
2906 rt2x00_rt(rt2x00dev, RT5392))
f4450616
BZ		 2907 return 0x1c + (2 * rt2x00dev->lna_gain);
2908 else
2909 return 0x2e + rt2x00dev->lna_gain;
2910 }
2911
2912 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2913 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2914 else
2915 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2916}
2917
2918static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2919 struct link_qual *qual, u8 vgc_level)
2920{
2921 if (qual->vgc_level != vgc_level) {
2922 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2923 qual->vgc_level = vgc_level;
2924 qual->vgc_level_reg = vgc_level;
2925 }
2926}
2927
2928void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2929{
2930 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2931}
2932EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2933
2934void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2935 const u32 count)
2936{
8d0c9b65 2937 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2938 return;
2939
2940 /*
2941 * When RSSI is better then -80 increase VGC level with 0x10
2942 */
2943 rt2800_set_vgc(rt2x00dev, qual,
2944 rt2800_get_default_vgc(rt2x00dev) +
2945 ((qual->rssi > -80) * 0x10));
2946}
2947EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2948
2949/*
2950 * Initialization functions.
2951 */
b9a07ae9 2952static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2953{
2954 u32 reg;
d5385bfc 2955 u16 eeprom;
fcf51541 2956 unsigned int i;
e3a896b9 2957 int ret;
fcf51541 2958
f7b395e9 2959 rt2800_disable_wpdma(rt2x00dev);
a9dce149 2960
e3a896b9
GW		 2961 ret = rt2800_drv_init_registers(rt2x00dev);
2962 if (ret)
2963 return ret;
fcf51541
BZ		 2964
2965 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2966 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2967 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2968 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2969 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2970 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2971
2972 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2973 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2974 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2975 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2976 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2977 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2978
2979 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2980 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2981
2982 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2983
2984 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2985 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2986 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2987 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2988 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2989 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2990 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2991 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2992
a9dce149
GW		 2993 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2994
2995 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2996 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2997 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2998 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2999
a89534ed
WH		 3000 if (rt2x00_rt(rt2x00dev, RT3290)) {
3001 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3002 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3003 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3004 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3005 }
3006
3007 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3008 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3009 rt2x00_set_field32(&reg, LDO0_EN, 1);
3010 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3011 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3012 }
3013
3014 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3015 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3016 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3017 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3018 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3019
3020 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3021 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3022 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3023
3024 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3025 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3026 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3027 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3028 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3029 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3030
3031 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3032 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3033 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3034 }
3035
64522957 3036 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3037 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3038 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 3039 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 3040
3041 if (rt2x00_rt(rt2x00dev, RT3290))
3042 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3043 0x00000404);
3044 else
3045 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3046 0x00000400);
3047
fcf51541 3048 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 3049 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3050 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3051 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 3052 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3053 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3054 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3055 0x0000002c);
3056 else
3057 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3058 0x0000000f);
3059 } else {
3060 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3061 }
d5385bfc 3062 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 3063 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 3064
3065 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3066 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3067 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3068 } else {
3069 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3070 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3071 }
c295a81d
HS		 3072 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3073 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3074 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 3075 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 3076 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3077 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3078 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3079 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 3080 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3081 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3082 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884
JL		 3083 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3084 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3085 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3086 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3087 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 3088 } else {
3089 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3090 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3091 }
3092
3093 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3094 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3095 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3096 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3097 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3098 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3099 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3100 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3101 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3102 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3103
3104 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3105 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 3106 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 3107 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3108 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3109
3110 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3111 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 3112 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 3113 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 3114 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 3115 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3116 else
3117 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3118 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3119 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3120 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3121
a9dce149
GW		 3122 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3123 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3124 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3125 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3126 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3127 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3128 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3129 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3130 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3131
fcf51541
BZ		 3132 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3133
a9dce149
GW		 3134 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3135 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3136 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3137 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3138 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3139 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3140 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3141 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3142
fcf51541
BZ		 3143 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3144 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 3145 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 3146 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3147 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 3148 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 3149 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3150 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3151 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3152
3153 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 3154 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3155 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3156 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3157 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3158 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3159 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3160 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3161 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3162 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3163 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3164 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3165
3166 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 3167 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3168 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3169 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3170 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3171 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3172 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3173 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3174 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3175 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3176 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3177 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3178
3179 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3180 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3181 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3182 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3183 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3184 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3185 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3186 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3187 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3188 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3189 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3190 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3191
3192 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3193 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 3194 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3195 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3196 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3197 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3198 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3199 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3200 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3201 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3202 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3203 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3204
3205 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3206 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3207 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3208 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3209 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3210 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3211 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3212 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3213 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3214 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3215 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3216 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3217
3218 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3219 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3220 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3221 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3222 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3223 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3224 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3225 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3226 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3227 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3228 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3229 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3230
cea90e55 3231 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 3232 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3233
3234 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3235 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3236 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3237 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3238 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3239 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3240 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3241 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3242 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3243 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3244 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3245 }
3246
961621ab
HS		 3247 /*
3248 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3249 * although it is reserved.
3250 */
3251 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3252 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3253 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3254 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3255 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3256 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3257 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3258 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3259 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3260 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3261 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3262 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3263
fcf51541
BZ		 3264 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3265
3266 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3267 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3268 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3269 IEEE80211_MAX_RTS_THRESHOLD);
3270 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3271 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3272
3273 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3274
a21c2ab4
HS		 3275 /*
3276 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3277 * time should be set to 16. However, the original Ralink driver uses
3278 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3279 * connection problems with 11g + CTS protection. Hence, use the same
3280 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3281 */
a9dce149 3282 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3283 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3284 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3285 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3286 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3287 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3288 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3289
fcf51541
BZ		 3290 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3291
3292 /*
3293 * ASIC will keep garbage value after boot, clear encryption keys.
3294 */
3295 for (i = 0; i < 4; i++)
3296 rt2800_register_write(rt2x00dev,
3297 SHARED_KEY_MODE_ENTRY(i), 0);
3298
3299 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3300 rt2800_config_wcid(rt2x00dev, NULL, i);
3301 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3302 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3303 }
3304
3305 /*
3306 * Clear all beacons
fcf51541 3307 */
69cf36a4
HS		 3308 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3309 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3310 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3311 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3312 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3313 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3314 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3315 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3316
cea90e55 3317 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3318 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3319 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3320 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3321 } else if (rt2x00_is_pcie(rt2x00dev)) {
3322 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3323 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3324 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3325 }
3326
3327 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3328 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3329 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3330 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3331 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3332 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3333 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3334 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3335 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3336 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3337
3338 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3339 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3340 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3341 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3342 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3343 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3344 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3345 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3346 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3347 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3348
3349 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3350 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3351 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3352 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3353 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3354 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3355 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3356 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3357 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3358 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3359
3360 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3361 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3362 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3363 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3364 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3365 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3366
47ee3eb1
HS		 3367 /*
3368 * Do not force the BA window size, we use the TXWI to set it
3369 */
3370 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3371 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3372 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3373 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3374
fcf51541
BZ		 3375 /*
3376 * We must clear the error counters.
3377 * These registers are cleared on read,
3378 * so we may pass a useless variable to store the value.
3379 */
3380 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3381 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3382 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3383 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3384 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3385 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3386
9f926fb5
HS		 3387 /*
3388 * Setup leadtime for pre tbtt interrupt to 6ms
3389 */
3390 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3391 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3392 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3393
977206d7
HS		 3394 /*
3395 * Set up channel statistics timer
3396 */
3397 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3398 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3399 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3400 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3401 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3402 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3403 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3404
fcf51541
BZ		 3405 return 0;
3406}
fcf51541
BZ		 3407
3408static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3409{
3410 unsigned int i;
3411 u32 reg;
3412
3413 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3414 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3415 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3416 return 0;
3417
3418 udelay(REGISTER_BUSY_DELAY);
3419 }
3420
3421 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3422 return -EACCES;
3423}
3424
3425static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3426{
3427 unsigned int i;
3428 u8 value;
3429
3430 /*
3431 * BBP was enabled after firmware was loaded,
3432 * but we need to reactivate it now.
3433 */
3434 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3435 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3436 msleep(1);
3437
3438 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3439 rt2800_bbp_read(rt2x00dev, 0, &value);
3440 if ((value != 0xff) && (value != 0x00))
3441 return 0;
3442 udelay(REGISTER_BUSY_DELAY);
3443 }
3444
3445 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3446 return -EACCES;
3447}
3448
b9a07ae9 3449static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3450{
3451 unsigned int i;
3452 u16 eeprom;
3453 u8 reg_id;
3454 u8 value;
3455
3456 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3457 rt2800_wait_bbp_ready(rt2x00dev)))
3458 return -EACCES;
3459
03839951
DG		 3460 if (rt2x00_rt(rt2x00dev, RT3352)) {
3461 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3462 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3463 }
3464
a89534ed
WH		 3465 if (rt2x00_rt(rt2x00dev, RT3290) ||
3466 rt2x00_rt(rt2x00dev, RT5390) ||
3467 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3468 rt2800_bbp_read(rt2x00dev, 4, &value);
3469 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3470 rt2800_bbp_write(rt2x00dev, 4, value);
3471 }
60687ba7 3472
adde5882 3473 if (rt2800_is_305x_soc(rt2x00dev) ||
a89534ed 3474 rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3475 rt2x00_rt(rt2x00dev, RT3352) ||
872834df 3476 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3477 rt2x00_rt(rt2x00dev, RT5390) ||
3478 rt2x00_rt(rt2x00dev, RT5392))
baff8006
HS		 3479 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3480
03839951
DG		 3481 if (rt2x00_rt(rt2x00dev, RT3352))
3482 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3483
fcf51541
BZ		 3484 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3485 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3486
a89534ed 3487 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3488 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3489 rt2x00_rt(rt2x00dev, RT5390) ||
3490 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3491 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3492
a9dce149
GW		 3493 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3494 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3495 rt2800_bbp_write(rt2x00dev, 73, 0x12);
a89534ed 3496 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3497 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3498 rt2x00_rt(rt2x00dev, RT5390) ||
3499 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3500 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3501 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3502 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3503 rt2800_bbp_write(rt2x00dev, 76, 0x28);
a89534ed
WH		 3504
3505 if (rt2x00_rt(rt2x00dev, RT3290))
3506 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3507 else
3508 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3509 } else {
3510 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3511 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3512 }
3513
fcf51541 3514 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3515
d5385bfc 3516 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3517 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3518 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3519 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3520 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3521 rt2x00_rt(rt2x00dev, RT5390) ||
3522 rt2x00_rt(rt2x00dev, RT5392)) {
8cdd15e0
GW		 3523 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3524 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3525 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3526 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3527 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3528 rt2800_bbp_write(rt2x00dev, 80, 0x08);
03839951
DG		 3529 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3530 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3531 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3532 rt2800_bbp_write(rt2x00dev, 81, 0x37);
8cdd15e0
GW		 3533 } else {
3534 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3535 }
3536
a89534ed
WH		 3537 if (rt2x00_rt(rt2x00dev, RT3290)) {
3538 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3539 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3540 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3541 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3542 }
3543
fcf51541 3544 rt2800_bbp_write(rt2x00dev, 82, 0x62);
a89534ed
WH		 3545 if (rt2x00_rt(rt2x00dev, RT3290) ||
3546 rt2x00_rt(rt2x00dev, RT5390) ||
3547 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3548 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3549 else
3550 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3551
5ed8f458 3552 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3553 rt2800_bbp_write(rt2x00dev, 84, 0x19);
a89534ed
WH		 3554 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3555 rt2x00_rt(rt2x00dev, RT5390) ||
3556 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3557 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3558 else
3559 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3560
a89534ed 3561 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3562 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3563 rt2x00_rt(rt2x00dev, RT5390) ||
3564 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3565 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3566 else
3567 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3568
03839951
DG		 3569 if (rt2x00_rt(rt2x00dev, RT3352) ||
3570 rt2x00_rt(rt2x00dev, RT5392))
2ed71884
JL		 3571 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3572
fcf51541 3573 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3574
a89534ed 3575 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3576 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3577 rt2x00_rt(rt2x00dev, RT5390) ||
3578 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3579 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3580 else
3581 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3582
2ed71884
JL		 3583 if (rt2x00_rt(rt2x00dev, RT5392)) {
3584 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3585 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3586 }
3587
d5385bfc 3588 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3589 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3590 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3591 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
a89534ed 3592 rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3593 rt2x00_rt(rt2x00dev, RT3352) ||
872834df 3594 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3595 rt2x00_rt(rt2x00dev, RT5390) ||
2ed71884 3596 rt2x00_rt(rt2x00dev, RT5392) ||
baff8006 3597 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3598 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3599 else
3600 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3601
a89534ed 3602 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3603 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3604 rt2x00_rt(rt2x00dev, RT5390) ||
3605 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3606 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3607
baff8006
HS		 3608 if (rt2800_is_305x_soc(rt2x00dev))
3609 rt2800_bbp_write(rt2x00dev, 105, 0x01);
a89534ed
WH		 3610 else if (rt2x00_rt(rt2x00dev, RT3290))
3611 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
03839951
DG		 3612 else if (rt2x00_rt(rt2x00dev, RT3352))
3613 rt2800_bbp_write(rt2x00dev, 105, 0x34);
2ed71884
JL		 3614 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3615 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3616 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3617 else
3618 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3619
a89534ed
WH		 3620 if (rt2x00_rt(rt2x00dev, RT3290) ||
3621 rt2x00_rt(rt2x00dev, RT5390))
adde5882 3622 rt2800_bbp_write(rt2x00dev, 106, 0x03);
03839951
DG		 3623 else if (rt2x00_rt(rt2x00dev, RT3352))
3624 rt2800_bbp_write(rt2x00dev, 106, 0x05);
2ed71884
JL		 3625 else if (rt2x00_rt(rt2x00dev, RT5392))
3626 rt2800_bbp_write(rt2x00dev, 106, 0x12);
adde5882
GJ		 3627 else
3628 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3629
03839951
DG		 3630 if (rt2x00_rt(rt2x00dev, RT3352))
3631 rt2800_bbp_write(rt2x00dev, 120, 0x50);
3632
a89534ed
WH		 3633 if (rt2x00_rt(rt2x00dev, RT3290) ||
3634 rt2x00_rt(rt2x00dev, RT5390) ||
3635 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3636 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3637
2ed71884
JL		 3638 if (rt2x00_rt(rt2x00dev, RT5392)) {
3639 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3640 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3641 }
3642
03839951
DG		 3643 if (rt2x00_rt(rt2x00dev, RT3352))
3644 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
3645
64522957 3646 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3647 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3648 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3649 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3650 rt2x00_rt(rt2x00dev, RT5390) ||
3651 rt2x00_rt(rt2x00dev, RT5392)) {
d5385bfc 3652 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3653
38c8a566
RJH		 3654 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3655 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3656 value |= 0x20;
38c8a566 3657 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3658 value &= ~0x02;
fcf51541 3659
d5385bfc 3660 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3661 }
3662
a89534ed
WH		 3663 if (rt2x00_rt(rt2x00dev, RT3290)) {
3664 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3665 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3666 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3667 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3668 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3669 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3670 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3671 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3672 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3673 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3674
3675 rt2800_bbp_read(rt2x00dev, 47, &value);
3676 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3677 rt2800_bbp_write(rt2x00dev, 47, value);
3678
3679 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3680 rt2800_bbp_read(rt2x00dev, 3, &value);
3681 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3682 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3683 rt2800_bbp_write(rt2x00dev, 3, value);
3684 }
3685
03839951
DG		 3686 if (rt2x00_rt(rt2x00dev, RT3352)) {
3687 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
3688 /* Set ITxBF timeout to 0x9c40=1000msec */
3689 rt2800_bbp_write(rt2x00dev, 179, 0x02);
3690 rt2800_bbp_write(rt2x00dev, 180, 0x00);
3691 rt2800_bbp_write(rt2x00dev, 182, 0x40);
3692 rt2800_bbp_write(rt2x00dev, 180, 0x01);
3693 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
3694 rt2800_bbp_write(rt2x00dev, 179, 0x00);
3695 /* Reprogram the inband interface to put right values in RXWI */
3696 rt2800_bbp_write(rt2x00dev, 142, 0x04);
3697 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
3698 rt2800_bbp_write(rt2x00dev, 142, 0x06);
3699 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
3700 rt2800_bbp_write(rt2x00dev, 142, 0x07);
3701 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
3702 rt2800_bbp_write(rt2x00dev, 142, 0x08);
3703 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
3704
3705 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
3706 }
3707
2ed71884
JL		 3708 if (rt2x00_rt(rt2x00dev, RT5390) ||
3709 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3710 int ant, div_mode;
3711
3712 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3713 div_mode = rt2x00_get_field16(eeprom,
3714 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3715 ant = (div_mode == 3) ? 1 : 0;
3716
3717 /* check if this is a Bluetooth combo card */
fdbc7b0a 3718 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3719 u32 reg;
3720
99bdf51a
GW		 3721 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3722 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
3723 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
3724 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
3725 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
adde5882 3726 if (ant == 0)
99bdf51a 3727 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
adde5882 3728 else if (ant == 1)
99bdf51a
GW		 3729 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
3730 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
adde5882
GJ		 3731 }
3732
0586a11b
AA		 3733 /* This chip has hardware antenna diversity*/
3734 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3735 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3736 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3737 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3738 }
3739
adde5882
GJ		 3740 rt2800_bbp_read(rt2x00dev, 152, &value);
3741 if (ant == 0)
3742 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3743 else
3744 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3745 rt2800_bbp_write(rt2x00dev, 152, value);
3746
3747 /* Init frequency calibration */
3748 rt2800_bbp_write(rt2x00dev, 142, 1);
3749 rt2800_bbp_write(rt2x00dev, 143, 57);
3750 }
fcf51541
BZ		 3751
3752 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3753 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3754
3755 if (eeprom != 0xffff && eeprom != 0x0000) {
3756 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3757 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3758 rt2800_bbp_write(rt2x00dev, reg_id, value);
3759 }
3760 }
3761
3762 return 0;
3763}
fcf51541
BZ		 3764
3765static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3766 bool bw40, u8 rfcsr24, u8 filter_target)
3767{
3768 unsigned int i;
3769 u8 bbp;
3770 u8 rfcsr;
3771 u8 passband;
3772 u8 stopband;
3773 u8 overtuned = 0;
3774
3775 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3776
3777 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3778 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3779 rt2800_bbp_write(rt2x00dev, 4, bbp);
3780
80d184e6
RJH		 3781 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3782 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3783 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3784
fcf51541
BZ		 3785 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3786 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3787 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3788
3789 /*
3790 * Set power & frequency of passband test tone
3791 */
3792 rt2800_bbp_write(rt2x00dev, 24, 0);
3793
3794 for (i = 0; i < 100; i++) {
3795 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3796 msleep(1);
3797
3798 rt2800_bbp_read(rt2x00dev, 55, &passband);
3799 if (passband)
3800 break;
3801 }
3802
3803 /*
3804 * Set power & frequency of stopband test tone
3805 */
3806 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3807
3808 for (i = 0; i < 100; i++) {
3809 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3810 msleep(1);
3811
3812 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3813
3814 if ((passband - stopband) <= filter_target) {
3815 rfcsr24++;
3816 overtuned += ((passband - stopband) == filter_target);
3817 } else
3818 break;
3819
3820 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3821 }
3822
3823 rfcsr24 -= !!overtuned;
3824
3825 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3826 return rfcsr24;
3827}
3828
b9a07ae9 3829static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 3830{
3a1c0128 3831 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541
BZ		 3832 u8 rfcsr;
3833 u8 bbp;
8cdd15e0
GW		 3834 u32 reg;
3835 u16 eeprom;
fcf51541 3836
d5385bfc 3837 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3838 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3839 !rt2x00_rt(rt2x00dev, RT3090) &&
a89534ed 3840 !rt2x00_rt(rt2x00dev, RT3290) &&
03839951 3841 !rt2x00_rt(rt2x00dev, RT3352) &&
23812383 3842 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3843 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3844 !rt2x00_rt(rt2x00dev, RT5390) &&
2ed71884 3845 !rt2x00_rt(rt2x00dev, RT5392) &&
baff8006 3846 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3847 return 0;
3848
fcf51541
BZ		 3849 /*
3850 * Init RF calibration.
3851 */
a89534ed
WH		 3852 if (rt2x00_rt(rt2x00dev, RT3290) ||
3853 rt2x00_rt(rt2x00dev, RT5390) ||
3854 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3855 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3856 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3857 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3858 msleep(1);
3859 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3860 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3861 } else {
3862 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3863 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3864 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3865 msleep(1);
3866 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3867 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3868 }
fcf51541 3869
d5385bfc 3870 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3871 rt2x00_rt(rt2x00dev, RT3071) ||
3872 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3873 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3874 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3875 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3876 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3877 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3878 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3879 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3880 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3881 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3882 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3883 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3884 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3885 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3886 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3887 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3888 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3889 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3890 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3891 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
a89534ed
WH		 3892 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3893 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3894 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3895 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3896 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3897 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3898 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3899 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3900 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3901 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3902 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3903 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3904 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3905 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3906 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3907 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3908 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3909 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3910 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3911 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3912 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3913 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3914 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3915 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3916 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3917 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3918 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3919 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3920 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3921 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3922 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3923 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3924 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3925 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3926 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3927 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3928 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3929 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3930 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3931 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3932 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3933 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3934 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3935 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3936 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3937 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3938 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
cc78e904
GW		 3939 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3940 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3941 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3942 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3943 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3944 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3945 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3946 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3947 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3948 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3949 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3950 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3951 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3952 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3953 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3954 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3955 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3956 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3957 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3958 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3959 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3960 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3961 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3962 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3963 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3964 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3965 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3966 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3967 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3968 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3969 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3970 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3971 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3972 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3973 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3974 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3975 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3976 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3977 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3978 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3979 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3980 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3981 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3982 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3983 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3984 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3985 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3986 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3987 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3988 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3989 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3990 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3991 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3992 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3993 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3994 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3995 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3996 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3997 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3998 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3999 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4000 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4001 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4002 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4003 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 4004 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 4005 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4006 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4007 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4008 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4009 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4010 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4011 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4012 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4013 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4014 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4015 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4016 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4017 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4018 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4019 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4020 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4021 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4022 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4023 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4024 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4025 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4026 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4027 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4028 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4029 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4030 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4031 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4032 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4033 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4034 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 4035 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4036 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4037 return 0;
03839951
DG		 4038 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4039 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4040 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4041 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4042 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4043 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4044 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4045 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4046 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4047 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4048 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4049 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4050 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4051 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4052 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4053 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4054 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4055 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4056 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4057 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4058 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4059 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4060 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4061 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4062 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4063 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4064 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4065 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4066 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4067 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4068 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4069 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4070 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4071 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4072 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4073 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4074 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4075 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4076 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4077 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4078 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4079 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4080 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4081 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4082 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4083 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4084 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4085 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4086 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4087 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4088 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4089 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4090 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4091 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4092 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4093 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4094 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4095 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4096 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4097 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4098 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4099 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4100 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4101 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
adde5882
GJ		 4102 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
4103 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4104 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4105 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4106 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4107 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4108 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4109 else
4110 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4111 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4112 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4113 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4114 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4115 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4116 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4117 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4118 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4119 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4120 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4121
4122 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4123 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4124 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4125 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4126 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4127 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4128 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4129 else
4130 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4131 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4132 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4133 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4134 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4135
4136 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4137 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4138 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4139 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4140 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4141 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4142 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4143 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4144 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4145 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4146
4147 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4148 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4149 else
4150 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4151 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4152 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4153 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4154 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4155 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4156 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4157 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4158 else
4159 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4160 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4161 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4162 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4163
4164 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4165 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4166 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4167 else
4168 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4169 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4170 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4171 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4172 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4173 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4174 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4175
4176 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4177 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4178 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4179 else
4180 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4181 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4182 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2ed71884
JL		 4183 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
4184 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4185 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4186 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4187 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4188 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4189 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4190 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4191 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4192 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4193 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4194 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4195 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4196 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4197 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4198 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4199 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4200 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4201 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4202 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4203 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4204 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4205 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4206 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4207 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4208 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4209 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4210 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4211 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4212 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4213 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4214 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4215 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4216 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4217 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4218 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4219 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4220 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4221 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4222 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4223 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4224 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4225 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4226 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4227 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4228 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4229 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4230 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4231 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4232 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4233 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4234 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4235 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4236 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4237 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4238 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4239 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4240 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4241 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4242 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8cdd15e0
GW		 4243 }
4244
4245 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4246 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4247 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4248 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4249 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 4250 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4251 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 4252 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4253
d5385bfc
GW		 4254 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4255 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4256 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4257
d5385bfc
GW		 4258 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4259 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 4260 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4261 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 4262 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4263 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4264 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4265 else
4266 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4267 }
4268 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 4269
4270 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4271 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4272 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 4273 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4274 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4275 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4276 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 4277 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4278 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4279 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4280 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4281
4282 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4283 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4284 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4285 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4286 msleep(1);
4287 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
d0f21fe6 4288 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
872834df
GW		 4289 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4290 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 4291 }
4292
4293 /*
4294 * Set RX Filter calibration for 20MHz and 40MHz
4295 */
8cdd15e0 4296 if (rt2x00_rt(rt2x00dev, RT3070)) {
3a1c0128 4297 drv_data->calibration_bw20 =
8cdd15e0 4298 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3a1c0128 4299 drv_data->calibration_bw40 =
8cdd15e0 4300 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 4301 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4302 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 4303 rt2x00_rt(rt2x00dev, RT3352) ||
872834df
GW		 4304 rt2x00_rt(rt2x00dev, RT3390) ||
4305 rt2x00_rt(rt2x00dev, RT3572)) {
3a1c0128 4306 drv_data->calibration_bw20 =
d5385bfc 4307 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3a1c0128 4308 drv_data->calibration_bw40 =
d5385bfc 4309 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 4310 }
fcf51541 4311
5d137dff
GW		 4312 /*
4313 * Save BBP 25 & 26 values for later use in channel switching
4314 */
4315 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4316 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4317
2ed71884
JL		 4318 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4319 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4320 /*
4321 * Set back to initial state
4322 */
4323 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 4324
adde5882
GJ		 4325 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4326 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4327 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 4328
adde5882
GJ		 4329 /*
4330 * Set BBP back to BW20
4331 */
4332 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4333 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4334 rt2800_bbp_write(rt2x00dev, 4, bbp);
4335 }
fcf51541 4336
d5385bfc 4337 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 4338 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4339 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4340 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 4341 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4342
4343 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4344 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4345 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4346
2ed71884
JL		 4347 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4348 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4349 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4350 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4351 if (rt2x00_rt(rt2x00dev, RT3070) ||
4352 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4353 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4354 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 4355 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4356 &rt2x00dev->cap_flags))
adde5882
GJ		 4357 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4358 }
77c06c2c
GW		 4359 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4360 drv_data->txmixer_gain_24g);
adde5882
GJ		 4361 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4362 }
8cdd15e0 4363
64522957
GW		 4364 if (rt2x00_rt(rt2x00dev, RT3090)) {
4365 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4366
80d184e6 4367 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 4368 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4369 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 4370 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 4371 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 4372 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4373
4374 rt2800_bbp_write(rt2x00dev, 138, bbp);
4375 }
4376
4377 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 4378 rt2x00_rt(rt2x00dev, RT3090) ||
4379 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 4380 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4381 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4382 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4383 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4384 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4385 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4386 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4387
4388 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4389 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4390 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4391
4392 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4393 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4394 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4395
4396 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4397 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4398 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4399 }
4400
80d184e6 4401 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 4402 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 4403 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 4404 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4405 else
4406 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4407 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4408 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4409 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4410 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4411 }
4412
a89534ed
WH		 4413 if (rt2x00_rt(rt2x00dev, RT3290)) {
4414 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4415 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4416 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4417 }
4418
2ed71884
JL		 4419 if (rt2x00_rt(rt2x00dev, RT5390) ||
4420 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4421 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4422 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4423 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 4424
adde5882
GJ		 4425 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4426 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4427 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 4428
adde5882
GJ		 4429 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4430 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4431 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4432 }
60687ba7 4433
fcf51541
BZ		 4434 return 0;
4435}
b9a07ae9
ID		 4436
4437int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4438{
4439 u32 reg;
4440 u16 word;
4441
4442 /*
4443 * Initialize all registers.
4444 */
4445 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4446 rt2800_init_registers(rt2x00dev) ||
4447 rt2800_init_bbp(rt2x00dev) ||
4448 rt2800_init_rfcsr(rt2x00dev)))
4449 return -EIO;
4450
4451 /*
4452 * Send signal to firmware during boot time.
4453 */
4454 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4455
4456 if (rt2x00_is_usb(rt2x00dev) &&
4457 (rt2x00_rt(rt2x00dev, RT3070) ||
4458 rt2x00_rt(rt2x00dev, RT3071) ||
4459 rt2x00_rt(rt2x00dev, RT3572))) {
4460 udelay(200);
4461 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4462 udelay(10);
4463 }
4464
4465 /*
4466 * Enable RX.
4467 */
4468 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4469 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4470 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4471 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4472
4473 udelay(50);
4474
4475 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4476 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4477 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4478 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4479 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4480 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4481
4482 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4483 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4484 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4485 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4486
4487 /*
4488 * Initialize LED control
4489 */
38c8a566
RJH		 4490 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4491 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 4492 word & 0xff, (word >> 8) & 0xff);
4493
38c8a566
RJH		 4494 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4495 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 4496 word & 0xff, (word >> 8) & 0xff);
4497
38c8a566
RJH		 4498 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4499 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 4500 word & 0xff, (word >> 8) & 0xff);
4501
4502 return 0;
4503}
4504EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4505
4506void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4507{
4508 u32 reg;
4509
f7b395e9 4510 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 4511
4512 /* Wait for DMA, ignore error */
4513 rt2800_wait_wpdma_ready(rt2x00dev);
4514
4515 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4516 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4518 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 4519}
4520EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 4521
30e84034
BZ		 4522int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4523{
4524 u32 reg;
a89534ed 4525 u16 efuse_ctrl_reg;
30e84034 4526
a89534ed
WH		 4527 if (rt2x00_rt(rt2x00dev, RT3290))
4528 efuse_ctrl_reg = EFUSE_CTRL_3290;
4529 else
4530 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 4531
a89534ed 4532 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 4533 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4534}
4535EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4536
4537static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4538{
4539 u32 reg;
a89534ed
WH		 4540 u16 efuse_ctrl_reg;
4541 u16 efuse_data0_reg;
4542 u16 efuse_data1_reg;
4543 u16 efuse_data2_reg;
4544 u16 efuse_data3_reg;
4545
4546 if (rt2x00_rt(rt2x00dev, RT3290)) {
4547 efuse_ctrl_reg = EFUSE_CTRL_3290;
4548 efuse_data0_reg = EFUSE_DATA0_3290;
4549 efuse_data1_reg = EFUSE_DATA1_3290;
4550 efuse_data2_reg = EFUSE_DATA2_3290;
4551 efuse_data3_reg = EFUSE_DATA3_3290;
4552 } else {
4553 efuse_ctrl_reg = EFUSE_CTRL;
4554 efuse_data0_reg = EFUSE_DATA0;
4555 efuse_data1_reg = EFUSE_DATA1;
4556 efuse_data2_reg = EFUSE_DATA2;
4557 efuse_data3_reg = EFUSE_DATA3;
4558 }
31a4cf1f
GW		 4559 mutex_lock(&rt2x00dev->csr_mutex);
4560
a89534ed 4561 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 4562 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4563 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4564 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 4565 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 4566
4567 /* Wait until the EEPROM has been loaded */
a89534ed 4568 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 4569 /* Apparently the data is read from end to start */
a89534ed 4570 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 4571 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 4572 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 4573 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 4574 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 4575 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 4576 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 4577 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 4578 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 4579
4580 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 4581}
4582
4583void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4584{
4585 unsigned int i;
4586
4587 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4588 rt2800_efuse_read(rt2x00dev, i);
4589}
4590EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4591
ad417a53 4592static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 4593{
77c06c2c 4594 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 4595 u16 word;
4596 u8 *mac;
4597 u8 default_lna_gain;
4598
ad417a53
GW		 4599 /*
4600 * Read the EEPROM.
4601 */
4602 rt2800_read_eeprom(rt2x00dev);
4603
38bd7b8a
BZ		 4604 /*
4605 * Start validation of the data that has been read.
4606 */
4607 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4608 if (!is_valid_ether_addr(mac)) {
f4f7f414 4609 eth_random_addr(mac);
38bd7b8a
BZ		 4610 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4611 }
4612
38c8a566 4613 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 4614 if (word == 0xffff) {
38c8a566
RJH		 4615 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4616 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4617 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4618 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 4619 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 4620 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 4621 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 4622 /*
4623 * There is a max of 2 RX streams for RT28x0 series
4624 */
38c8a566
RJH		 4625 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4626 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4627 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 4628 }
4629
38c8a566 4630 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 4631 if (word == 0xffff) {
38c8a566
RJH		 4632 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4633 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4634 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4635 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4636 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4637 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4638 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4639 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4640 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4641 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4642 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4643 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4644 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4645 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4646 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4647 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 4648 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4649 }
4650
4651 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4652 if ((word & 0x00ff) == 0x00ff) {
4653 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 4654 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4655 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4656 }
4657 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 4658 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4659 LED_MODE_TXRX_ACTIVITY);
4660 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4661 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 4662 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4663 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4664 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 4665 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 4666 }
4667
4668 /*
4669 * During the LNA validation we are going to use
4670 * lna0 as correct value. Note that EEPROM_LNA
4671 * is never validated.
4672 */
4673 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4674 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4675
4676 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4677 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4678 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4679 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4680 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4681 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4682
77c06c2c
GW		 4683 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4684 if ((word & 0x00ff) != 0x00ff) {
4685 drv_data->txmixer_gain_24g =
4686 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4687 } else {
4688 drv_data->txmixer_gain_24g = 0;
4689 }
4690
38bd7b8a
BZ		 4691 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4692 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4693 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4694 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4695 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4696 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4697 default_lna_gain);
4698 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4699
77c06c2c
GW		 4700 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4701 if ((word & 0x00ff) != 0x00ff) {
4702 drv_data->txmixer_gain_5g =
4703 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4704 } else {
4705 drv_data->txmixer_gain_5g = 0;
4706 }
4707
38bd7b8a
BZ		 4708 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4709 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4710 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4711 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4712 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4713 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4714
4715 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4716 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4717 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4718 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4719 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4720 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4721 default_lna_gain);
4722 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4723
4724 return 0;
4725}
38bd7b8a 4726
ad417a53 4727static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a
BZ		 4728{
4729 u32 reg;
4730 u16 value;
4731 u16 eeprom;
4732
4733 /*
4734 * Read EEPROM word for configuration.
4735 */
38c8a566 4736 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 4737
4738 /*
adde5882
GJ		 4739 * Identify RF chipset by EEPROM value
4740 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4741 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 4742 */
a89534ed
WH		 4743 if (rt2x00_rt(rt2x00dev, RT3290))
4744 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4745 else
4746 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4747
4748 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4749 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4750 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
adde5882
GJ		 4751 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4752 else
4753 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 4754
49e721ec
GW		 4755 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4756 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4757
5aa57015
GW		 4758 switch (rt2x00dev->chip.rt) {
4759 case RT2860:
4760 case RT2872:
4761 case RT2883:
4762 case RT3070:
4763 case RT3071:
4764 case RT3090:
a89534ed 4765 case RT3290:
03839951 4766 case RT3352:
5aa57015
GW		 4767 case RT3390:
4768 case RT3572:
4769 case RT5390:
2ed71884 4770 case RT5392:
5aa57015
GW		 4771 break;
4772 default:
b6df7f1d 4773 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
49e721ec 4774 return -ENODEV;
f273fe55 4775 }
714fa663 4776
d331eb51
LF		 4777 switch (rt2x00dev->chip.rf) {
4778 case RF2820:
4779 case RF2850:
4780 case RF2720:
4781 case RF2750:
4782 case RF3020:
4783 case RF2020:
4784 case RF3021:
4785 case RF3022:
4786 case RF3052:
a89534ed 4787 case RF3290:
d331eb51 4788 case RF3320:
03839951 4789 case RF3322:
ccf91bd6 4790 case RF5360:
d331eb51 4791 case RF5370:
2ed71884 4792 case RF5372:
d331eb51 4793 case RF5390:
cff3d1f0 4794 case RF5392:
d331eb51
LF		 4795 break;
4796 default:
b6df7f1d 4797 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
d331eb51 4798 rt2x00dev->chip.rf);
38bd7b8a
BZ		 4799 return -ENODEV;
4800 }
4801
4802 /*
4803 * Identify default antenna configuration.
4804 */
d96aa640 4805 rt2x00dev->default_ant.tx_chain_num =
38c8a566 4806 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 4807 rt2x00dev->default_ant.rx_chain_num =
38c8a566 4808 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 4809
d96aa640
RJH		 4810 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4811
4812 if (rt2x00_rt(rt2x00dev, RT3070) ||
4813 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 4814 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 4815 rt2x00_rt(rt2x00dev, RT3390)) {
4816 value = rt2x00_get_field16(eeprom,
4817 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4818 switch (value) {
4819 case 0:
4820 case 1:
4821 case 2:
4822 rt2x00dev->default_ant.tx = ANTENNA_A;
4823 rt2x00dev->default_ant.rx = ANTENNA_A;
4824 break;
4825 case 3:
4826 rt2x00dev->default_ant.tx = ANTENNA_A;
4827 rt2x00dev->default_ant.rx = ANTENNA_B;
4828 break;
4829 }
4830 } else {
4831 rt2x00dev->default_ant.tx = ANTENNA_A;
4832 rt2x00dev->default_ant.rx = ANTENNA_A;
4833 }
4834
0586a11b
AA		 4835 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4836 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4837 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4838 }
4839
38bd7b8a 4840 /*
9328fdac 4841 * Determine external LNA informations.
38bd7b8a 4842 */
38c8a566 4843 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4844 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4845 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4846 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4847
4848 /*
4849 * Detect if this device has an hardware controlled radio.
4850 */
38c8a566 4851 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4852 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4853
fdbc7b0a
GW		 4854 /*
4855 * Detect if this device has Bluetooth co-existence.
4856 */
4857 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4858 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4859
9328fdac
GW		 4860 /*
4861 * Read frequency offset and RF programming sequence.
4862 */
4863 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4864 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4865
38bd7b8a
BZ		 4866 /*
4867 * Store led settings, for correct led behaviour.
4868 */
4869#ifdef CONFIG_RT2X00_LIB_LEDS
4870 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4871 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4872 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4873
9328fdac 4874 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4875#endif /* CONFIG_RT2X00_LIB_LEDS */
4876
e90c54b2
RJH		 4877 /*
4878 * Check if support EIRP tx power limit feature.
4879 */
4880 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4881
4882 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4883 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4884 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4885
38bd7b8a
BZ		 4886 return 0;
4887}
38bd7b8a 4888
4da2933f 4889/*
55f9321a 4890 * RF value list for rt28xx
4da2933f
BZ		 4891 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4892 */
4893static const struct rf_channel rf_vals[] = {
4894 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4895 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4896 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4897 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4898 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4899 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4900 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4901 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4902 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4903 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4904 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4905 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4906 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4907 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4908
4909 /* 802.11 UNI / HyperLan 2 */
4910 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4911 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4912 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4913 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4914 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4915 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4916 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4917 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4918 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4919 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4920 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4921 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4922
4923 /* 802.11 HyperLan 2 */
4924 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4925 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4926 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4927 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4928 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4929 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4930 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4931 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4932 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4933 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4934 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4935 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4936 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4937 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4938 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4939 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4940
4941 /* 802.11 UNII */
4942 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4943 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4944 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4945 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4946 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4947 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4948 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4949 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4950 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4951 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4952 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4953
4954 /* 802.11 Japan */
4955 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4956 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4957 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4958 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4959 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4960 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4961 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4962};
4963
4964/*
55f9321a
ID		 4965 * RF value list for rt3xxx
4966 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4967 */
55f9321a 4968static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4969 {1, 241, 2, 2 },
4970 {2, 241, 2, 7 },
4971 {3, 242, 2, 2 },
4972 {4, 242, 2, 7 },
4973 {5, 243, 2, 2 },
4974 {6, 243, 2, 7 },
4975 {7, 244, 2, 2 },
4976 {8, 244, 2, 7 },
4977 {9, 245, 2, 2 },
4978 {10, 245, 2, 7 },
4979 {11, 246, 2, 2 },
4980 {12, 246, 2, 7 },
4981 {13, 247, 2, 2 },
4982 {14, 248, 2, 4 },
55f9321a
ID		 4983
4984 /* 802.11 UNI / HyperLan 2 */
4985 {36, 0x56, 0, 4},
4986 {38, 0x56, 0, 6},
4987 {40, 0x56, 0, 8},
4988 {44, 0x57, 0, 0},
4989 {46, 0x57, 0, 2},
4990 {48, 0x57, 0, 4},
4991 {52, 0x57, 0, 8},
4992 {54, 0x57, 0, 10},
4993 {56, 0x58, 0, 0},
4994 {60, 0x58, 0, 4},
4995 {62, 0x58, 0, 6},
4996 {64, 0x58, 0, 8},
4997
4998 /* 802.11 HyperLan 2 */
4999 {100, 0x5b, 0, 8},
5000 {102, 0x5b, 0, 10},
5001 {104, 0x5c, 0, 0},
5002 {108, 0x5c, 0, 4},
5003 {110, 0x5c, 0, 6},
5004 {112, 0x5c, 0, 8},
5005 {116, 0x5d, 0, 0},
5006 {118, 0x5d, 0, 2},
5007 {120, 0x5d, 0, 4},
5008 {124, 0x5d, 0, 8},
5009 {126, 0x5d, 0, 10},
5010 {128, 0x5e, 0, 0},
5011 {132, 0x5e, 0, 4},
5012 {134, 0x5e, 0, 6},
5013 {136, 0x5e, 0, 8},
5014 {140, 0x5f, 0, 0},
5015
5016 /* 802.11 UNII */
5017 {149, 0x5f, 0, 9},
5018 {151, 0x5f, 0, 11},
5019 {153, 0x60, 0, 1},
5020 {157, 0x60, 0, 5},
5021 {159, 0x60, 0, 7},
5022 {161, 0x60, 0, 9},
5023 {165, 0x61, 0, 1},
5024 {167, 0x61, 0, 3},
5025 {169, 0x61, 0, 5},
5026 {171, 0x61, 0, 7},
5027 {173, 0x61, 0, 9},
4da2933f
BZ		 5028};
5029
ad417a53 5030static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 5031{
4da2933f
BZ		 5032 struct hw_mode_spec *spec = &rt2x00dev->spec;
5033 struct channel_info *info;
8d1331b3
ID		 5034 char *default_power1;
5035 char *default_power2;
4da2933f
BZ		 5036 unsigned int i;
5037 u16 eeprom;
5038
93b6bd26
GW		 5039 /*
5040 * Disable powersaving as default on PCI devices.
5041 */
cea90e55 5042 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 5043 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5044
4da2933f
BZ		 5045 /*
5046 * Initialize all hw fields.
5047 */
5048 rt2x00dev->hw->flags =
4da2933f
BZ		 5049 IEEE80211_HW_SIGNAL_DBM |
5050 IEEE80211_HW_SUPPORTS_PS |
1df90809 5051 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8
HS		 5052 IEEE80211_HW_AMPDU_AGGREGATION |
5053 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5054
5a5b6ed6
HS		 5055 /*
5056 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5057 * unless we are capable of sending the buffered frames out after the
5058 * DTIM transmission using rt2x00lib_beacondone. This will send out
5059 * multicast and broadcast traffic immediately instead of buffering it
5060 * infinitly and thus dropping it after some time.
5061 */
5062 if (!rt2x00_is_usb(rt2x00dev))
5063 rt2x00dev->hw->flags |=
5064 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 5065
4da2933f
BZ		 5066 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5067 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5068 rt2x00_eeprom_addr(rt2x00dev,
5069 EEPROM_MAC_ADDR_0));
5070
3f2bee24
HS		 5071 /*
5072 * As rt2800 has a global fallback table we cannot specify
5073 * more then one tx rate per frame but since the hw will
5074 * try several rates (based on the fallback table) we should
ba3b9e5e 5075 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 5076 * we are going to try. Otherwise mac80211 will truncate our
5077 * reported tx rates and the rc algortihm will end up with
5078 * incorrect data.
5079 */
ba3b9e5e
HS		 5080 rt2x00dev->hw->max_rates = 1;
5081 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 5082 rt2x00dev->hw->max_rate_tries = 1;
5083
38c8a566 5084 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 5085
5086 /*
5087 * Initialize hw_mode information.
5088 */
5089 spec->supported_bands = SUPPORT_BAND_2GHZ;
5090 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5091
5122d898 5092 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 5093 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 5094 spec->num_channels = 14;
5095 spec->channels = rf_vals;
55f9321a
ID		 5096 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5097 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 5098 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5099 spec->num_channels = ARRAY_SIZE(rf_vals);
5100 spec->channels = rf_vals;
5122d898
GW		 5101 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5102 rt2x00_rf(rt2x00dev, RF2020) ||
5103 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 5104 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 5105 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 5106 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 5107 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 5108 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 5109 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 5110 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 5111 rt2x00_rf(rt2x00dev, RF5390) ||
5112 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 5113 spec->num_channels = 14;
5114 spec->channels = rf_vals_3x;
5115 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5116 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5117 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5118 spec->channels = rf_vals_3x;
4da2933f
BZ		 5119 }
5120
5121 /*
5122 * Initialize HT information.
5123 */
5122d898 5124 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 5125 spec->ht.ht_supported = true;
5126 else
5127 spec->ht.ht_supported = false;
5128
4da2933f 5129 spec->ht.cap =
06443e46 5130 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 5131 IEEE80211_HT_CAP_GRN_FLD |
5132 IEEE80211_HT_CAP_SGI_20 |
aa674631 5133 IEEE80211_HT_CAP_SGI_40;
22cabaa6 5134
38c8a566 5135 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 5136 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5137
aa674631 5138 spec->ht.cap |=
38c8a566 5139 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 5140 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5141
4da2933f
BZ		 5142 spec->ht.ampdu_factor = 3;
5143 spec->ht.ampdu_density = 4;
5144 spec->ht.mcs.tx_params =
5145 IEEE80211_HT_MCS_TX_DEFINED |
5146 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 5147 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 5148 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5149
38c8a566 5150 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 5151 case 3:
5152 spec->ht.mcs.rx_mask[2] = 0xff;
5153 case 2:
5154 spec->ht.mcs.rx_mask[1] = 0xff;
5155 case 1:
5156 spec->ht.mcs.rx_mask[0] = 0xff;
5157 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5158 break;
5159 }
5160
5161 /*
5162 * Create channel information array
5163 */
baeb2ffa 5164 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 5165 if (!info)
5166 return -ENOMEM;
5167
5168 spec->channels_info = info;
5169
8d1331b3
ID		 5170 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5171 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 5172
5173 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 5174 info[i].default_power1 = default_power1[i];
5175 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 5176 }
5177
5178 if (spec->num_channels > 14) {
8d1331b3
ID		 5179 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5180 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 5181
5182 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 5183 info[i].default_power1 = default_power1[i];
5184 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 5185 }
5186 }
5187
2e9c43dd
JL		 5188 switch (rt2x00dev->chip.rf) {
5189 case RF2020:
5190 case RF3020:
5191 case RF3021:
5192 case RF3022:
5193 case RF3320:
5194 case RF3052:
a89534ed 5195 case RF3290:
ccf91bd6 5196 case RF5360:
2e9c43dd
JL		 5197 case RF5370:
5198 case RF5372:
5199 case RF5390:
cff3d1f0 5200 case RF5392:
2e9c43dd
JL		 5201 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5202 break;
5203 }
5204
4da2933f
BZ		 5205 return 0;
5206}
ad417a53
GW		 5207
5208int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5209{
5210 int retval;
5211 u32 reg;
5212
5213 /*
5214 * Allocate eeprom data.
5215 */
5216 retval = rt2800_validate_eeprom(rt2x00dev);
5217 if (retval)
5218 return retval;
5219
5220 retval = rt2800_init_eeprom(rt2x00dev);
5221 if (retval)
5222 return retval;
5223
5224 /*
5225 * Enable rfkill polling by setting GPIO direction of the
5226 * rfkill switch GPIO pin correctly.
5227 */
5228 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5229 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5230 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5231
5232 /*
5233 * Initialize hw specifications.
5234 */
5235 retval = rt2800_probe_hw_mode(rt2x00dev);
5236 if (retval)
5237 return retval;
5238
5239 /*
5240 * Set device capabilities.
5241 */
5242 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5243 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5244 if (!rt2x00_is_usb(rt2x00dev))
5245 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5246
5247 /*
5248 * Set device requirements.
5249 */
5250 if (!rt2x00_is_soc(rt2x00dev))
5251 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5252 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5253 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5254 if (!rt2800_hwcrypt_disabled(rt2x00dev))
5255 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5256 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5257 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5258 if (rt2x00_is_usb(rt2x00dev))
5259 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5260 else {
5261 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5262 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5263 }
5264
5265 /*
5266 * Set the rssi offset.
5267 */
5268 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5269
5270 return 0;
5271}
5272EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 5273
2ce33995
BZ		 5274/*
5275 * IEEE80211 stack callback functions.
5276 */
e783619e
HS		 5277void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5278 u16 *iv16)
2ce33995
BZ		 5279{
5280 struct rt2x00_dev *rt2x00dev = hw->priv;
5281 struct mac_iveiv_entry iveiv_entry;
5282 u32 offset;
5283
5284 offset = MAC_IVEIV_ENTRY(hw_key_idx);
5285 rt2800_register_multiread(rt2x00dev, offset,
5286 &iveiv_entry, sizeof(iveiv_entry));
5287
855da5e0
JL		 5288 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5289 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 5290}
e783619e 5291EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 5292
e783619e 5293int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 5294{
5295 struct rt2x00_dev *rt2x00dev = hw->priv;
5296 u32 reg;
5297 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5298
5299 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5300 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5301 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5302
5303 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5304 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5305 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5306
5307 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5308 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5309 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5310
5311 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5312 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5313 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5314
5315 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5316 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5317 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5318
5319 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5320 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5321 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5322
5323 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5324 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5325 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5326
5327 return 0;
5328}
e783619e 5329EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 5330
8a3a3c85
EP		 5331int rt2800_conf_tx(struct ieee80211_hw *hw,
5332 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 5333 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 5334{
5335 struct rt2x00_dev *rt2x00dev = hw->priv;
5336 struct data_queue *queue;
5337 struct rt2x00_field32 field;
5338 int retval;
5339 u32 reg;
5340 u32 offset;
5341
5342 /*
5343 * First pass the configuration through rt2x00lib, that will
5344 * update the queue settings and validate the input. After that
5345 * we are free to update the registers based on the value
5346 * in the queue parameter.
5347 */
8a3a3c85 5348 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 5349 if (retval)
5350 return retval;
5351
5352 /*
5353 * We only need to perform additional register initialization
5354 * for WMM queues/
5355 */
5356 if (queue_idx >= 4)
5357 return 0;
5358
11f818e0 5359 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 5360
5361 /* Update WMM TXOP register */
5362 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5363 field.bit_offset = (queue_idx & 1) * 16;
5364 field.bit_mask = 0xffff << field.bit_offset;
5365
5366 rt2800_register_read(rt2x00dev, offset, &reg);
5367 rt2x00_set_field32(&reg, field, queue->txop);
5368 rt2800_register_write(rt2x00dev, offset, reg);
5369
5370 /* Update WMM registers */
5371 field.bit_offset = queue_idx * 4;
5372 field.bit_mask = 0xf << field.bit_offset;
5373
5374 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5375 rt2x00_set_field32(&reg, field, queue->aifs);
5376 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5377
5378 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5379 rt2x00_set_field32(&reg, field, queue->cw_min);
5380 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5381
5382 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5383 rt2x00_set_field32(&reg, field, queue->cw_max);
5384 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5385
5386 /* Update EDCA registers */
5387 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5388
5389 rt2800_register_read(rt2x00dev, offset, &reg);
5390 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5391 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5392 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5393 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5394 rt2800_register_write(rt2x00dev, offset, reg);
5395
5396 return 0;
5397}
e783619e 5398EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 5399
37a41b4a 5400u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 5401{
5402 struct rt2x00_dev *rt2x00dev = hw->priv;
5403 u64 tsf;
5404 u32 reg;
5405
5406 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
5407 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5408 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
5409 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5410
5411 return tsf;
5412}
e783619e 5413EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 5414
e783619e
HS		 5415int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5416 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5417 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5418 u8 buf_size)
1df90809 5419{
af35323d 5420 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 5421 int ret = 0;
5422
af35323d
HS		 5423 /*
5424 * Don't allow aggregation for stations the hardware isn't aware
5425 * of because tx status reports for frames to an unknown station
5426 * always contain wcid=255 and thus we can't distinguish between
5427 * multiple stations which leads to unwanted situations when the
5428 * hw reorders frames due to aggregation.
5429 */
5430 if (sta_priv->wcid < 0)
5431 return 1;
5432
1df90809
HS		 5433 switch (action) {
5434 case IEEE80211_AMPDU_RX_START:
5435 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 5436 /*
5437 * The hw itself takes care of setting up BlockAck mechanisms.
5438 * So, we only have to allow mac80211 to nagotiate a BlockAck
5439 * agreement. Once that is done, the hw will BlockAck incoming
5440 * AMPDUs without further setup.
5441 */
1df90809
HS		 5442 break;
5443 case IEEE80211_AMPDU_TX_START:
5444 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5445 break;
5446 case IEEE80211_AMPDU_TX_STOP:
5447 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5448 break;
5449 case IEEE80211_AMPDU_TX_OPERATIONAL:
5450 break;
5451 default:
4e9e58c6 5452 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 5453 }
5454
5455 return ret;
5456}
e783619e 5457EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 5458
977206d7
HS		 5459int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5460 struct survey_info *survey)
5461{
5462 struct rt2x00_dev *rt2x00dev = hw->priv;
5463 struct ieee80211_conf *conf = &hw->conf;
5464 u32 idle, busy, busy_ext;
5465
5466 if (idx != 0)
5467 return -ENOENT;
5468
5469 survey->channel = conf->channel;
5470
5471 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5472 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5473 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5474
5475 if (idle || busy) {
5476 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5477 SURVEY_INFO_CHANNEL_TIME_BUSY |
5478 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5479
5480 survey->channel_time = (idle + busy) / 1000;
5481 survey->channel_time_busy = busy / 1000;
5482 survey->channel_time_ext_busy = busy_ext / 1000;
5483 }
5484
9931df26
HS		 5485 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5486 survey->filled |= SURVEY_INFO_IN_USE;
5487
977206d7
HS		 5488 return 0;
5489
5490}
5491EXPORT_SYMBOL_GPL(rt2800_get_survey);
5492
a5ea2f02
ID		 5493MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5494MODULE_VERSION(DRV_VERSION);
5495MODULE_DESCRIPTION("Ralink RT2800 library");
5496MODULE_LICENSE("GPL");
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