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rt2800usb: initialize H2M_INT_SRC register
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c 402
adde5882 403 if (rt2x00_is_pci(rt2x00dev)) {
872834df
GW		 404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
adde5882
GJ		 406 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
407 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
408 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
409 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
410 }
f31c9a8c 411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 412 }
f31c9a8c
ID		 413
414 /*
415 * Disable DMA, will be reenabled later when enabling
416 * the radio.
417 */
418 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
419 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
420 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
421 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
422 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
423 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
424 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
425
426 /*
427 * Write firmware to the device.
428 */
429 rt2800_drv_write_firmware(rt2x00dev, data, len);
430
431 /*
432 * Wait for device to stabilize.
433 */
434 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
435 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
436 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
437 break;
438 msleep(1);
439 }
440
441 if (i == REGISTER_BUSY_COUNT) {
442 ERROR(rt2x00dev, "PBF system register not ready.\n");
443 return -EBUSY;
444 }
445
446 /*
447 * Initialize firmware.
448 */
449 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
450 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 451 if (rt2x00_is_usb(rt2x00dev))
452 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 453 msleep(1);
454
455 return 0;
456}
457EXPORT_SYMBOL_GPL(rt2800_load_firmware);
458
0c5879bc
ID		 459void rt2800_write_tx_data(struct queue_entry *entry,
460 struct txentry_desc *txdesc)
59679b91 461{
0c5879bc 462 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 463 u32 word;
464
465 /*
466 * Initialize TX Info descriptor
467 */
468 rt2x00_desc_read(txwi, 0, &word);
469 rt2x00_set_field32(&word, TXWI_W0_FRAG,
470 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 471 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
472 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 473 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
474 rt2x00_set_field32(&word, TXWI_W0_TS,
475 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
476 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
477 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 478 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
479 txdesc->u.ht.mpdu_density);
480 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
481 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 482 rt2x00_set_field32(&word, TXWI_W0_BW,
483 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
485 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 486 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 487 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
488 rt2x00_desc_write(txwi, 0, word);
489
490 rt2x00_desc_read(txwi, 1, &word);
491 rt2x00_set_field32(&word, TXWI_W1_ACK,
492 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
493 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
494 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 495 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 496 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
497 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 498 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 499 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
500 txdesc->length);
2b23cdaa 501 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 502 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 503 rt2x00_desc_write(txwi, 1, word);
504
505 /*
506 * Always write 0 to IV/EIV fields, hardware will insert the IV
507 * from the IVEIV register when TXD_W3_WIV is set to 0.
508 * When TXD_W3_WIV is set to 1 it will use the IV data
509 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
510 * crypto entry in the registers should be used to encrypt the frame.
511 */
512 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
513 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
514}
0c5879bc 515EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 516
ff6133be 517static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 518{
74861922
ID		 519 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
520 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
521 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
522 u16 eeprom;
523 u8 offset0;
524 u8 offset1;
525 u8 offset2;
526
e5ef5bad 527 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 528 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
529 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
530 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
531 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
532 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
533 } else {
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
535 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
536 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
537 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
538 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
539 }
540
541 /*
542 * Convert the value from the descriptor into the RSSI value
543 * If the value in the descriptor is 0, it is considered invalid
544 * and the default (extremely low) rssi value is assumed
545 */
546 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
547 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
548 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
549
550 /*
551 * mac80211 only accepts a single RSSI value. Calculating the
552 * average doesn't deliver a fair answer either since -60:-60 would
553 * be considered equally good as -50:-70 while the second is the one
554 * which gives less energy...
555 */
556 rssi0 = max(rssi0, rssi1);
557 return max(rssi0, rssi2);
558}
559
560void rt2800_process_rxwi(struct queue_entry *entry,
561 struct rxdone_entry_desc *rxdesc)
562{
563 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 564 u32 word;
565
566 rt2x00_desc_read(rxwi, 0, &word);
567
568 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
569 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
570
571 rt2x00_desc_read(rxwi, 1, &word);
572
573 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
574 rxdesc->flags |= RX_FLAG_SHORT_GI;
575
576 if (rt2x00_get_field32(word, RXWI_W1_BW))
577 rxdesc->flags |= RX_FLAG_40MHZ;
578
579 /*
580 * Detect RX rate, always use MCS as signal type.
581 */
582 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
583 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
584 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
585
586 /*
587 * Mask of 0x8 bit to remove the short preamble flag.
588 */
589 if (rxdesc->rate_mode == RATE_MODE_CCK)
590 rxdesc->signal &= ~0x8;
591
592 rt2x00_desc_read(rxwi, 2, &word);
593
74861922
ID		 594 /*
595 * Convert descriptor AGC value to RSSI value.
596 */
597 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 598
599 /*
600 * Remove RXWI descriptor from start of buffer.
601 */
74861922 602 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 603}
604EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
605
31937c42 606void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 607{
608 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 609 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 610 struct txdone_entry_desc txdesc;
611 u32 word;
612 u16 mcs, real_mcs;
b34793ee 613 int aggr, ampdu;
14433331
HS		 614
615 /*
616 * Obtain the status about this packet.
617 */
618 txdesc.flags = 0;
14433331 619 rt2x00_desc_read(txwi, 0, &word);
b34793ee 620
14433331 621 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 622 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
623
14433331 624 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 625 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
626
627 /*
628 * If a frame was meant to be sent as a single non-aggregated MPDU
629 * but ended up in an aggregate the used tx rate doesn't correlate
630 * with the one specified in the TXWI as the whole aggregate is sent
631 * with the same rate.
632 *
633 * For example: two frames are sent to rt2x00, the first one sets
634 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
635 * and requests MCS15. If the hw aggregates both frames into one
636 * AMDPU the tx status for both frames will contain MCS7 although
637 * the frame was sent successfully.
638 *
639 * Hence, replace the requested rate with the real tx rate to not
640 * confuse the rate control algortihm by providing clearly wrong
641 * data.
642 */
5356d963 643 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 644 skbdesc->tx_rate_idx = real_mcs;
645 mcs = real_mcs;
646 }
14433331 647
f16d2db7
HS		 648 if (aggr == 1 || ampdu == 1)
649 __set_bit(TXDONE_AMPDU, &txdesc.flags);
650
14433331
HS		 651 /*
652 * Ralink has a retry mechanism using a global fallback
653 * table. We setup this fallback table to try the immediate
654 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
655 * always contains the MCS used for the last transmission, be
656 * it successful or not.
657 */
658 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
659 /*
660 * Transmission succeeded. The number of retries is
661 * mcs - real_mcs
662 */
663 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
664 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
665 } else {
666 /*
667 * Transmission failed. The number of retries is
668 * always 7 in this case (for a total number of 8
669 * frames sent).
670 */
671 __set_bit(TXDONE_FAILURE, &txdesc.flags);
672 txdesc.retry = rt2x00dev->long_retry;
673 }
674
675 /*
676 * the frame was retried at least once
677 * -> hw used fallback rates
678 */
679 if (txdesc.retry)
680 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
681
682 rt2x00lib_txdone(entry, &txdesc);
683}
684EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
685
f0194b2d
GW		 686void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
687{
688 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
689 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
690 unsigned int beacon_base;
739fd940 691 unsigned int padding_len;
d76dfc61 692 u32 orig_reg, reg;
f0194b2d
GW		 693
694 /*
695 * Disable beaconing while we are reloading the beacon data,
696 * otherwise we might be sending out invalid data.
697 */
698 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 699 orig_reg = reg;
f0194b2d
GW		 700 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
701 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
702
703 /*
704 * Add space for the TXWI in front of the skb.
705 */
b52398b6 706 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 707
708 /*
709 * Register descriptor details in skb frame descriptor.
710 */
711 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
712 skbdesc->desc = entry->skb->data;
713 skbdesc->desc_len = TXWI_DESC_SIZE;
714
715 /*
716 * Add the TXWI for the beacon to the skb.
717 */
0c5879bc 718 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 719
720 /*
721 * Dump beacon to userspace through debugfs.
722 */
723 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
724
725 /*
739fd940 726 * Write entire beacon with TXWI and padding to register.
f0194b2d 727 */
739fd940 728 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 729 if (padding_len && skb_pad(entry->skb, padding_len)) {
730 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
731 /* skb freed by skb_pad() on failure */
732 entry->skb = NULL;
733 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
734 return;
735 }
736
f0194b2d 737 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 738 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
739 entry->skb->len + padding_len);
f0194b2d
GW		 740
741 /*
742 * Enable beaconing again.
743 */
f0194b2d
GW		 744 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
745 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
746
747 /*
748 * Clean up beacon skb.
749 */
750 dev_kfree_skb_any(entry->skb);
751 entry->skb = NULL;
752}
50e888ea 753EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 754
69cf36a4
HS		 755static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
756 unsigned int beacon_base)
fdb87251
HS		 757{
758 int i;
759
760 /*
761 * For the Beacon base registers we only need to clear
762 * the whole TXWI which (when set to 0) will invalidate
763 * the entire beacon.
764 */
765 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
766 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
767}
768
69cf36a4
HS		 769void rt2800_clear_beacon(struct queue_entry *entry)
770{
771 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
772 u32 reg;
773
774 /*
775 * Disable beaconing while we are reloading the beacon data,
776 * otherwise we might be sending out invalid data.
777 */
778 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
779 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
780 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
781
782 /*
783 * Clear beacon.
784 */
785 rt2800_clear_beacon_register(rt2x00dev,
786 HW_BEACON_OFFSET(entry->entry_idx));
787
788 /*
789 * Enabled beaconing again.
790 */
791 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
792 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
793}
794EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
795
f4450616
BZ		 796#ifdef CONFIG_RT2X00_LIB_DEBUGFS
797const struct rt2x00debug rt2800_rt2x00debug = {
798 .owner = THIS_MODULE,
799 .csr = {
800 .read = rt2800_register_read,
801 .write = rt2800_register_write,
802 .flags = RT2X00DEBUGFS_OFFSET,
803 .word_base = CSR_REG_BASE,
804 .word_size = sizeof(u32),
805 .word_count = CSR_REG_SIZE / sizeof(u32),
806 },
807 .eeprom = {
808 .read = rt2x00_eeprom_read,
809 .write = rt2x00_eeprom_write,
810 .word_base = EEPROM_BASE,
811 .word_size = sizeof(u16),
812 .word_count = EEPROM_SIZE / sizeof(u16),
813 },
814 .bbp = {
815 .read = rt2800_bbp_read,
816 .write = rt2800_bbp_write,
817 .word_base = BBP_BASE,
818 .word_size = sizeof(u8),
819 .word_count = BBP_SIZE / sizeof(u8),
820 },
821 .rf = {
822 .read = rt2x00_rf_read,
823 .write = rt2800_rf_write,
824 .word_base = RF_BASE,
825 .word_size = sizeof(u32),
826 .word_count = RF_SIZE / sizeof(u32),
827 },
828};
829EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
830#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
831
832int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
833{
834 u32 reg;
835
836 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
837 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
838}
839EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
840
841#ifdef CONFIG_RT2X00_LIB_LEDS
842static void rt2800_brightness_set(struct led_classdev *led_cdev,
843 enum led_brightness brightness)
844{
845 struct rt2x00_led *led =
846 container_of(led_cdev, struct rt2x00_led, led_dev);
847 unsigned int enabled = brightness != LED_OFF;
848 unsigned int bg_mode =
849 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
850 unsigned int polarity =
851 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
852 EEPROM_FREQ_LED_POLARITY);
853 unsigned int ledmode =
854 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
855 EEPROM_FREQ_LED_MODE);
44704e5d 856 u32 reg;
f4450616 857
44704e5d
LE		 858 /* Check for SoC (SOC devices don't support MCU requests) */
859 if (rt2x00_is_soc(led->rt2x00dev)) {
860 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
861
862 /* Set LED Polarity */
863 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
864
865 /* Set LED Mode */
866 if (led->type == LED_TYPE_RADIO) {
867 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
868 enabled ? 3 : 0);
869 } else if (led->type == LED_TYPE_ASSOC) {
870 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
871 enabled ? 3 : 0);
872 } else if (led->type == LED_TYPE_QUALITY) {
873 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
874 enabled ? 3 : 0);
875 }
876
877 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
878
879 } else {
880 if (led->type == LED_TYPE_RADIO) {
881 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
882 enabled ? 0x20 : 0);
883 } else if (led->type == LED_TYPE_ASSOC) {
884 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
885 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
886 } else if (led->type == LED_TYPE_QUALITY) {
887 /*
888 * The brightness is divided into 6 levels (0 - 5),
889 * The specs tell us the following levels:
890 * 0, 1 ,3, 7, 15, 31
891 * to determine the level in a simple way we can simply
892 * work with bitshifting:
893 * (1 << level) - 1
894 */
895 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
896 (1 << brightness / (LED_FULL / 6)) - 1,
897 polarity);
898 }
f4450616
BZ		 899 }
900}
901
b3579d6a 902static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 903 struct rt2x00_led *led, enum led_type type)
904{
905 led->rt2x00dev = rt2x00dev;
906 led->type = type;
907 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 908 led->flags = LED_INITIALIZED;
909}
f4450616
BZ		 910#endif /* CONFIG_RT2X00_LIB_LEDS */
911
912/*
913 * Configuration handlers.
914 */
a2b1328a
HS		 915static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
916 const u8 *address,
917 int wcid)
f4450616
BZ		 918{
919 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 920 u32 offset;
921
922 offset = MAC_WCID_ENTRY(wcid);
923
924 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
925 if (address)
926 memcpy(wcid_entry.mac, address, ETH_ALEN);
927
928 rt2800_register_multiwrite(rt2x00dev, offset,
929 &wcid_entry, sizeof(wcid_entry));
930}
931
932static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
933{
934 u32 offset;
935 offset = MAC_WCID_ATTR_ENTRY(wcid);
936 rt2800_register_write(rt2x00dev, offset, 0);
937}
938
939static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
940 int wcid, u32 bssidx)
941{
942 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
943 u32 reg;
944
945 /*
946 * The BSS Idx numbers is split in a main value of 3 bits,
947 * and a extended field for adding one additional bit to the value.
948 */
949 rt2800_register_read(rt2x00dev, offset, &reg);
950 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
951 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
952 (bssidx & 0x8) >> 3);
953 rt2800_register_write(rt2x00dev, offset, reg);
954}
955
956static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
957 struct rt2x00lib_crypto *crypto,
958 struct ieee80211_key_conf *key)
959{
f4450616
BZ		 960 struct mac_iveiv_entry iveiv_entry;
961 u32 offset;
962 u32 reg;
963
964 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
965
e4a0ab34
ID		 966 if (crypto->cmd == SET_KEY) {
967 rt2800_register_read(rt2x00dev, offset, &reg);
968 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
969 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
970 /*
971 * Both the cipher as the BSS Idx numbers are split in a main
972 * value of 3 bits, and a extended field for adding one additional
973 * bit to the value.
974 */
975 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
976 (crypto->cipher & 0x7));
977 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
978 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 979 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
980 rt2800_register_write(rt2x00dev, offset, reg);
981 } else {
a2b1328a
HS		 982 /* Delete the cipher without touching the bssidx */
983 rt2800_register_read(rt2x00dev, offset, &reg);
984 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
985 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
986 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
987 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
988 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 989 }
f4450616
BZ		 990
991 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
992
993 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
994 if ((crypto->cipher == CIPHER_TKIP) ||
995 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
996 (crypto->cipher == CIPHER_AES))
997 iveiv_entry.iv[3] |= 0x20;
998 iveiv_entry.iv[3] |= key->keyidx << 6;
999 rt2800_register_multiwrite(rt2x00dev, offset,
1000 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1001}
1002
1003int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1004 struct rt2x00lib_crypto *crypto,
1005 struct ieee80211_key_conf *key)
1006{
1007 struct hw_key_entry key_entry;
1008 struct rt2x00_field32 field;
1009 u32 offset;
1010 u32 reg;
1011
1012 if (crypto->cmd == SET_KEY) {
1013 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1014
1015 memcpy(key_entry.key, crypto->key,
1016 sizeof(key_entry.key));
1017 memcpy(key_entry.tx_mic, crypto->tx_mic,
1018 sizeof(key_entry.tx_mic));
1019 memcpy(key_entry.rx_mic, crypto->rx_mic,
1020 sizeof(key_entry.rx_mic));
1021
1022 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1023 rt2800_register_multiwrite(rt2x00dev, offset,
1024 &key_entry, sizeof(key_entry));
1025 }
1026
1027 /*
1028 * The cipher types are stored over multiple registers
1029 * starting with SHARED_KEY_MODE_BASE each word will have
1030 * 32 bits and contains the cipher types for 2 bssidx each.
1031 * Using the correct defines correctly will cause overhead,
1032 * so just calculate the correct offset.
1033 */
1034 field.bit_offset = 4 * (key->hw_key_idx % 8);
1035 field.bit_mask = 0x7 << field.bit_offset;
1036
1037 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1038
1039 rt2800_register_read(rt2x00dev, offset, &reg);
1040 rt2x00_set_field32(&reg, field,
1041 (crypto->cmd == SET_KEY) * crypto->cipher);
1042 rt2800_register_write(rt2x00dev, offset, reg);
1043
1044 /*
1045 * Update WCID information
1046 */
a2b1328a
HS		 1047 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1048 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1049 crypto->bssidx);
1050 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1051
1052 return 0;
1053}
1054EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1055
a2b1328a 1056static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1057{
a2b1328a 1058 struct mac_wcid_entry wcid_entry;
1ed3811c 1059 int idx;
a2b1328a 1060 u32 offset;
1ed3811c
HS		 1061
1062 /*
a2b1328a
HS		 1063 * Search for the first free WCID entry and return the corresponding
1064 * index.
1ed3811c
HS		 1065 *
1066 * Make sure the WCID starts _after_ the last possible shared key
1067 * entry (>32).
1068 *
1069 * Since parts of the pairwise key table might be shared with
1070 * the beacon frame buffers 6 & 7 we should only write into the
1071 * first 222 entries.
1072 */
1073 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1074 offset = MAC_WCID_ENTRY(idx);
1075 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1076 sizeof(wcid_entry));
1077 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1078 return idx;
1079 }
a2b1328a
HS		 1080
1081 /*
1082 * Use -1 to indicate that we don't have any more space in the WCID
1083 * table.
1084 */
1ed3811c
HS		 1085 return -1;
1086}
1087
f4450616
BZ		 1088int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1089 struct rt2x00lib_crypto *crypto,
1090 struct ieee80211_key_conf *key)
1091{
1092 struct hw_key_entry key_entry;
1093 u32 offset;
1094
1095 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1096 /*
1097 * Allow key configuration only for STAs that are
1098 * known by the hw.
1099 */
1100 if (crypto->wcid < 0)
f4450616 1101 return -ENOSPC;
a2b1328a 1102 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1103
1104 memcpy(key_entry.key, crypto->key,
1105 sizeof(key_entry.key));
1106 memcpy(key_entry.tx_mic, crypto->tx_mic,
1107 sizeof(key_entry.tx_mic));
1108 memcpy(key_entry.rx_mic, crypto->rx_mic,
1109 sizeof(key_entry.rx_mic));
1110
1111 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1112 rt2800_register_multiwrite(rt2x00dev, offset,
1113 &key_entry, sizeof(key_entry));
1114 }
1115
1116 /*
1117 * Update WCID information
1118 */
a2b1328a 1119 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1120
1121 return 0;
1122}
1123EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1124
a2b1328a
HS		 1125int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1126 struct ieee80211_sta *sta)
1127{
1128 int wcid;
1129 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1130
1131 /*
1132 * Find next free WCID.
1133 */
1134 wcid = rt2800_find_wcid(rt2x00dev);
1135
1136 /*
1137 * Store selected wcid even if it is invalid so that we can
1138 * later decide if the STA is uploaded into the hw.
1139 */
1140 sta_priv->wcid = wcid;
1141
1142 /*
1143 * No space left in the device, however, we can still communicate
1144 * with the STA -> No error.
1145 */
1146 if (wcid < 0)
1147 return 0;
1148
1149 /*
1150 * Clean up WCID attributes and write STA address to the device.
1151 */
1152 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1153 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1154 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1155 rt2x00lib_get_bssidx(rt2x00dev, vif));
1156 return 0;
1157}
1158EXPORT_SYMBOL_GPL(rt2800_sta_add);
1159
1160int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1161{
1162 /*
1163 * Remove WCID entry, no need to clean the attributes as they will
1164 * get renewed when the WCID is reused.
1165 */
1166 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1167
1168 return 0;
1169}
1170EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1171
f4450616
BZ		 1172void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1173 const unsigned int filter_flags)
1174{
1175 u32 reg;
1176
1177 /*
1178 * Start configuration steps.
1179 * Note that the version error will always be dropped
1180 * and broadcast frames will always be accepted since
1181 * there is no filter for it at this time.
1182 */
1183 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1184 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1185 !(filter_flags & FIF_FCSFAIL));
1186 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1187 !(filter_flags & FIF_PLCPFAIL));
1188 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1189 !(filter_flags & FIF_PROMISC_IN_BSS));
1190 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1191 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1192 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1193 !(filter_flags & FIF_ALLMULTI));
1194 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1195 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1196 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1197 !(filter_flags & FIF_CONTROL));
1198 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1199 !(filter_flags & FIF_CONTROL));
1200 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1201 !(filter_flags & FIF_CONTROL));
1202 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1203 !(filter_flags & FIF_CONTROL));
1204 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1205 !(filter_flags & FIF_CONTROL));
1206 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1207 !(filter_flags & FIF_PSPOLL));
48839938
HS		 1208 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1209 !(filter_flags & FIF_CONTROL));
1210 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1211 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1212 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1213 !(filter_flags & FIF_CONTROL));
1214 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1215}
1216EXPORT_SYMBOL_GPL(rt2800_config_filter);
1217
1218void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1219 struct rt2x00intf_conf *conf, const unsigned int flags)
1220{
f4450616 1221 u32 reg;
fa8b4b22 1222 bool update_bssid = false;
f4450616
BZ		 1223
1224 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1225 /*
1226 * Enable synchronisation.
1227 */
1228 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1229 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1230 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1231
1232 if (conf->sync == TSF_SYNC_AP_NONE) {
1233 /*
1234 * Tune beacon queue transmit parameters for AP mode
1235 */
1236 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1237 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1238 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1239 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1240 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1241 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1242 } else {
1243 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1244 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1245 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1246 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1247 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1248 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1249 }
f4450616
BZ		 1250 }
1251
1252 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1253 if (flags & CONFIG_UPDATE_TYPE &&
1254 conf->sync == TSF_SYNC_AP_NONE) {
1255 /*
1256 * The BSSID register has to be set to our own mac
1257 * address in AP mode.
1258 */
1259 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1260 update_bssid = true;
1261 }
1262
c600c826
ID		 1263 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1264 reg = le32_to_cpu(conf->mac[1]);
1265 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1266 conf->mac[1] = cpu_to_le32(reg);
1267 }
f4450616
BZ		 1268
1269 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1270 conf->mac, sizeof(conf->mac));
1271 }
1272
fa8b4b22 1273 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1274 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1275 reg = le32_to_cpu(conf->bssid[1]);
1276 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1277 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1278 conf->bssid[1] = cpu_to_le32(reg);
1279 }
f4450616
BZ		 1280
1281 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1282 conf->bssid, sizeof(conf->bssid));
1283 }
1284}
1285EXPORT_SYMBOL_GPL(rt2800_config_intf);
1286
87c1915d
HS		 1287static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1288 struct rt2x00lib_erp *erp)
1289{
1290 bool any_sta_nongf = !!(erp->ht_opmode &
1291 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1292 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1293 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1294 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1295 u32 reg;
1296
1297 /* default protection rate for HT20: OFDM 24M */
1298 mm20_rate = gf20_rate = 0x4004;
1299
1300 /* default protection rate for HT40: duplicate OFDM 24M */
1301 mm40_rate = gf40_rate = 0x4084;
1302
1303 switch (protection) {
1304 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1305 /*
1306 * All STAs in this BSS are HT20/40 but there might be
1307 * STAs not supporting greenfield mode.
1308 * => Disable protection for HT transmissions.
1309 */
1310 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1311
1312 break;
1313 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1314 /*
1315 * All STAs in this BSS are HT20 or HT20/40 but there
1316 * might be STAs not supporting greenfield mode.
1317 * => Protect all HT40 transmissions.
1318 */
1319 mm20_mode = gf20_mode = 0;
1320 mm40_mode = gf40_mode = 2;
1321
1322 break;
1323 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1324 /*
1325 * Nonmember protection:
1326 * According to 802.11n we _should_ protect all
1327 * HT transmissions (but we don't have to).
1328 *
1329 * But if cts_protection is enabled we _shall_ protect
1330 * all HT transmissions using a CCK rate.
1331 *
1332 * And if any station is non GF we _shall_ protect
1333 * GF transmissions.
1334 *
1335 * We decide to protect everything
1336 * -> fall through to mixed mode.
1337 */
1338 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1339 /*
1340 * Legacy STAs are present
1341 * => Protect all HT transmissions.
1342 */
1343 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1344
1345 /*
1346 * If erp protection is needed we have to protect HT
1347 * transmissions with CCK 11M long preamble.
1348 */
1349 if (erp->cts_protection) {
1350 /* don't duplicate RTS/CTS in CCK mode */
1351 mm20_rate = mm40_rate = 0x0003;
1352 gf20_rate = gf40_rate = 0x0003;
1353 }
1354 break;
6403eab1 1355 }
87c1915d
HS		 1356
1357 /* check for STAs not supporting greenfield mode */
1358 if (any_sta_nongf)
1359 gf20_mode = gf40_mode = 2;
1360
1361 /* Update HT protection config */
1362 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1363 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1364 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1365 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1366
1367 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1368 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1369 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1370 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1371
1372 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1373 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1374 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1375 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1376
1377 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1378 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1379 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1380 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1381}
1382
02044643
HS		 1383void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1384 u32 changed)
f4450616
BZ		 1385{
1386 u32 reg;
1387
02044643
HS		 1388 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1389 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1390 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1391 !!erp->short_preamble);
1392 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1393 !!erp->short_preamble);
1394 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1395 }
f4450616 1396
02044643
HS		 1397 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1398 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1399 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1400 erp->cts_protection ? 2 : 0);
1401 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1402 }
f4450616 1403
02044643
HS		 1404 if (changed & BSS_CHANGED_BASIC_RATES) {
1405 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1406 erp->basic_rates);
1407 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1408 }
f4450616 1409
02044643
HS		 1410 if (changed & BSS_CHANGED_ERP_SLOT) {
1411 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1412 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1413 erp->slot_time);
1414 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1415
02044643
HS		 1416 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1417 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1418 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1419 }
f4450616 1420
02044643
HS		 1421 if (changed & BSS_CHANGED_BEACON_INT) {
1422 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1423 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1424 erp->beacon_int * 16);
1425 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1426 }
87c1915d
HS		 1427
1428 if (changed & BSS_CHANGED_HT)
1429 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1430}
1431EXPORT_SYMBOL_GPL(rt2800_config_erp);
1432
872834df
GW		 1433static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1434{
1435 u32 reg;
1436 u16 eeprom;
1437 u8 led_ctrl, led_g_mode, led_r_mode;
1438
1439 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1440 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1441 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1442 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1443 } else {
1444 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1445 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1446 }
1447 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1448
1449 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1450 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1451 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1452 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1453 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1454 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1455 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1456 if (led_ctrl == 0 || led_ctrl > 0x40) {
1457 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1458 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1459 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1460 } else {
1461 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1462 (led_g_mode << 2) | led_r_mode, 1);
1463 }
1464 }
1465}
1466
d96aa640
RJH		 1467static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1468 enum antenna ant)
1469{
1470 u32 reg;
1471 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1472 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1473
1474 if (rt2x00_is_pci(rt2x00dev)) {
1475 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1476 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1477 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1478 } else if (rt2x00_is_usb(rt2x00dev))
1479 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1480 eesk_pin, 0);
1481
1482 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1483 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1484 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1485 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1486}
1487
f4450616
BZ		 1488void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1489{
1490 u8 r1;
1491 u8 r3;
d96aa640 1492 u16 eeprom;
f4450616
BZ		 1493
1494 rt2800_bbp_read(rt2x00dev, 1, &r1);
1495 rt2800_bbp_read(rt2x00dev, 3, &r3);
1496
872834df
GW		 1497 if (rt2x00_rt(rt2x00dev, RT3572) &&
1498 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1499 rt2800_config_3572bt_ant(rt2x00dev);
1500
f4450616
BZ		 1501 /*
1502 * Configure the TX antenna.
1503 */
d96aa640 1504 switch (ant->tx_chain_num) {
f4450616
BZ		 1505 case 1:
1506 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1507 break;
1508 case 2:
872834df
GW		 1509 if (rt2x00_rt(rt2x00dev, RT3572) &&
1510 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1511 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1512 else
1513 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1514 break;
1515 case 3:
e22557f2 1516 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1517 break;
1518 }
1519
1520 /*
1521 * Configure the RX antenna.
1522 */
d96aa640 1523 switch (ant->rx_chain_num) {
f4450616 1524 case 1:
d96aa640
RJH		 1525 if (rt2x00_rt(rt2x00dev, RT3070) ||
1526 rt2x00_rt(rt2x00dev, RT3090) ||
1527 rt2x00_rt(rt2x00dev, RT3390)) {
1528 rt2x00_eeprom_read(rt2x00dev,
1529 EEPROM_NIC_CONF1, &eeprom);
1530 if (rt2x00_get_field16(eeprom,
1531 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1532 rt2800_set_ant_diversity(rt2x00dev,
1533 rt2x00dev->default_ant.rx);
1534 }
f4450616
BZ		 1535 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1536 break;
1537 case 2:
872834df
GW		 1538 if (rt2x00_rt(rt2x00dev, RT3572) &&
1539 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1540 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1541 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1542 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1543 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1544 } else {
1545 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1546 }
f4450616
BZ		 1547 break;
1548 case 3:
1549 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1550 break;
1551 }
1552
1553 rt2800_bbp_write(rt2x00dev, 3, r3);
1554 rt2800_bbp_write(rt2x00dev, 1, r1);
1555}
1556EXPORT_SYMBOL_GPL(rt2800_config_ant);
1557
1558static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1559 struct rt2x00lib_conf *libconf)
1560{
1561 u16 eeprom;
1562 short lna_gain;
1563
1564 if (libconf->rf.channel <= 14) {
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1566 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1567 } else if (libconf->rf.channel <= 64) {
1568 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1569 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1570 } else if (libconf->rf.channel <= 128) {
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1572 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1573 } else {
1574 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1575 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1576 }
1577
1578 rt2x00dev->lna_gain = lna_gain;
1579}
1580
06855ef4
GW		 1581static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1582 struct ieee80211_conf *conf,
1583 struct rf_channel *rf,
1584 struct channel_info *info)
f4450616
BZ		 1585{
1586 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1587
d96aa640 1588 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1589 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1590
d96aa640 1591 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1592 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1593 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1594 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1595 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1596
1597 if (rf->channel > 14) {
1598 /*
1599 * When TX power is below 0, we should increase it by 7 to
25985edc 1600 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1601 * However this means that values between 0 and 7 have
1602 * double meaning, and we should set a 7DBm boost flag.
1603 */
1604 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1605 (info->default_power1 >= 0));
f4450616 1606
8d1331b3
ID		 1607 if (info->default_power1 < 0)
1608 info->default_power1 += 7;
f4450616 1609
8d1331b3 1610 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1611
1612 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1613 (info->default_power2 >= 0));
f4450616 1614
8d1331b3
ID		 1615 if (info->default_power2 < 0)
1616 info->default_power2 += 7;
f4450616 1617
8d1331b3 1618 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1619 } else {
8d1331b3
ID		 1620 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1621 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1622 }
1623
1624 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1625
1626 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1627 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1628 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1629 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1630
1631 udelay(200);
1632
1633 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1634 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1635 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1636 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1637
1638 udelay(200);
1639
1640 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1641 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1642 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1643 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1644}
1645
06855ef4
GW		 1646static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1647 struct ieee80211_conf *conf,
1648 struct rf_channel *rf,
1649 struct channel_info *info)
f4450616
BZ		 1650{
1651 u8 rfcsr;
1652
1653 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1654 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1655
1656 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1657 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1658 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1659
1660 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1661 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1662 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1663
5a673964 1664 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1665 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1666 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1667
f4450616
BZ		 1668 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1669 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1670 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1671
1672 rt2800_rfcsr_write(rt2x00dev, 24,
1673 rt2x00dev->calibration[conf_is_ht40(conf)]);
1674
71976907 1675 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1676 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1677 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1678}
1679
872834df
GW		 1680static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1681 struct ieee80211_conf *conf,
1682 struct rf_channel *rf,
1683 struct channel_info *info)
1684{
1685 u8 rfcsr;
1686 u32 reg;
1687
1688 if (rf->channel <= 14) {
1689 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1690 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1691 } else {
1692 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1693 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1694 }
1695
1696 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1697 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1698
1699 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1700 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1701 if (rf->channel <= 14)
1702 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1703 else
1704 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1705 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1706
1707 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1708 if (rf->channel <= 14)
1709 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1710 else
1711 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1712 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1713
1714 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1715 if (rf->channel <= 14) {
1716 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1717 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1718 (info->default_power1 & 0x3) |
1719 ((info->default_power1 & 0xC) << 1));
1720 } else {
1721 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1722 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1723 (info->default_power1 & 0x3) |
1724 ((info->default_power1 & 0xC) << 1));
1725 }
1726 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1727
1728 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1729 if (rf->channel <= 14) {
1730 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1731 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1732 (info->default_power2 & 0x3) |
1733 ((info->default_power2 & 0xC) << 1));
1734 } else {
1735 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1736 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1737 (info->default_power2 & 0x3) |
1738 ((info->default_power2 & 0xC) << 1));
1739 }
1740 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1741
1742 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1743 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1744 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1745 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1746 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1747 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1748 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1749 if (rf->channel <= 14) {
1750 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1751 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1752 }
1753 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1754 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1755 } else {
1756 switch (rt2x00dev->default_ant.tx_chain_num) {
1757 case 1:
1758 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1759 case 2:
1760 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1761 break;
1762 }
1763
1764 switch (rt2x00dev->default_ant.rx_chain_num) {
1765 case 1:
1766 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1767 case 2:
1768 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1769 break;
1770 }
1771 }
1772 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1773
1774 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1775 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1776 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1777
1778 rt2800_rfcsr_write(rt2x00dev, 24,
1779 rt2x00dev->calibration[conf_is_ht40(conf)]);
1780 rt2800_rfcsr_write(rt2x00dev, 31,
1781 rt2x00dev->calibration[conf_is_ht40(conf)]);
1782
1783 if (rf->channel <= 14) {
1784 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1785 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1786 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1787 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1788 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1789 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1790 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1791 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1792 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1793 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1794 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1795 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1796 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1797 } else {
1798 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1799 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1800 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1801 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1802 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1803 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1804 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1805 if (rf->channel <= 64) {
1806 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1807 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1808 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1809 } else if (rf->channel <= 128) {
1810 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1811 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1812 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1813 } else {
1814 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1815 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1816 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1817 }
1818 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1819 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1820 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1821 }
1822
1823 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1824 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1825 if (rf->channel <= 14)
1826 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1827 else
1828 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1829 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1830
1831 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1832 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1833 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1834}
60687ba7
RST		 1835
1836#define RT5390_POWER_BOUND 0x27
1837#define RT5390_FREQ_OFFSET_BOUND 0x5f
1838
1839static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1840 struct ieee80211_conf *conf,
1841 struct rf_channel *rf,
1842 struct channel_info *info)
1843{
1844 u8 rfcsr;
adde5882
GJ		 1845
1846 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1847 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1848 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1849 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1850 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1851
1852 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1853 if (info->default_power1 > RT5390_POWER_BOUND)
1854 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1855 else
1856 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1857 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1858
1859 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1860 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1861 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1862 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1863 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1864 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1865
1866 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1867 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1868 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1869 RT5390_FREQ_OFFSET_BOUND);
1870 else
1871 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1872 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1873
adde5882
GJ		 1874 if (rf->channel <= 14) {
1875 int idx = rf->channel-1;
1876
fdbc7b0a 1877 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 1878 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1879 /* r55/r59 value array of channel 1~14 */
1880 static const char r55_bt_rev[] = {0x83, 0x83,
1881 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1882 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1883 static const char r59_bt_rev[] = {0x0e, 0x0e,
1884 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1885 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1886
1887 rt2800_rfcsr_write(rt2x00dev, 55,
1888 r55_bt_rev[idx]);
1889 rt2800_rfcsr_write(rt2x00dev, 59,
1890 r59_bt_rev[idx]);
1891 } else {
1892 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1893 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1894 0x88, 0x88, 0x86, 0x85, 0x84};
1895
1896 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1897 }
1898 } else {
1899 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1900 static const char r55_nonbt_rev[] = {0x23, 0x23,
1901 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1902 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1903 static const char r59_nonbt_rev[] = {0x07, 0x07,
1904 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1905 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1906
1907 rt2800_rfcsr_write(rt2x00dev, 55,
1908 r55_nonbt_rev[idx]);
1909 rt2800_rfcsr_write(rt2x00dev, 59,
1910 r59_nonbt_rev[idx]);
1911 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1912 static const char r59_non_bt[] = {0x8f, 0x8f,
1913 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1914 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1915
1916 rt2800_rfcsr_write(rt2x00dev, 59,
1917 r59_non_bt[idx]);
1918 }
1919 }
1920 }
1921
1922 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1923 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1924 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1925 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1926
1927 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1928 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1929 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 1930}
1931
f4450616
BZ		 1932static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1933 struct ieee80211_conf *conf,
1934 struct rf_channel *rf,
1935 struct channel_info *info)
1936{
1937 u32 reg;
1938 unsigned int tx_pin;
1939 u8 bbp;
1940
46323e11 1941 if (rf->channel <= 14) {
8d1331b3
ID		 1942 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1943 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1944 } else {
8d1331b3
ID		 1945 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1946 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1947 }
1948
5aa57015
GW		 1949 switch (rt2x00dev->chip.rf) {
1950 case RF2020:
1951 case RF3020:
1952 case RF3021:
1953 case RF3022:
1954 case RF3320:
06855ef4 1955 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 1956 break;
1957 case RF3052:
872834df 1958 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015
GW		 1959 break;
1960 case RF5370:
1961 case RF5390:
adde5882 1962 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 1963 break;
1964 default:
06855ef4 1965 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 1966 }
f4450616
BZ		 1967
1968 /*
1969 * Change BBP settings
1970 */
1971 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1972 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1973 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1974 rt2800_bbp_write(rt2x00dev, 86, 0);
1975
1976 if (rf->channel <= 14) {
adde5882 1977 if (!rt2x00_rt(rt2x00dev, RT5390)) {
7dab73b3
ID		 1978 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1979 &rt2x00dev->cap_flags)) {
adde5882
GJ		 1980 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1981 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1982 } else {
1983 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1984 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1985 }
f4450616
BZ		 1986 }
1987 } else {
872834df
GW		 1988 if (rt2x00_rt(rt2x00dev, RT3572))
1989 rt2800_bbp_write(rt2x00dev, 82, 0x94);
1990 else
1991 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 1992
7dab73b3 1993 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 1994 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1995 else
1996 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1997 }
1998
1999 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2000 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2001 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2002 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2003 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2004
872834df
GW		 2005 if (rt2x00_rt(rt2x00dev, RT3572))
2006 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2007
f4450616
BZ		 2008 tx_pin = 0;
2009
2010 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2011 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2012 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2013 rf->channel > 14);
2014 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2015 rf->channel <= 14);
f4450616
BZ		 2016 }
2017
2018 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2019 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2020 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2021 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2022 }
2023
2024 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2025 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2026 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2027 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2028 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2029 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2030 else
2031 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2032 rf->channel <= 14);
f4450616
BZ		 2033 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2034
2035 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2036
872834df
GW		 2037 if (rt2x00_rt(rt2x00dev, RT3572))
2038 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2039
f4450616
BZ		 2040 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2041 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2042 rt2800_bbp_write(rt2x00dev, 4, bbp);
2043
2044 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2045 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2046 rt2800_bbp_write(rt2x00dev, 3, bbp);
2047
8d0c9b65 2048 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2049 if (conf_is_ht40(conf)) {
2050 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2051 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2052 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2053 } else {
2054 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2055 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2056 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2057 }
2058 }
2059
2060 msleep(1);
977206d7
HS		 2061
2062 /*
2063 * Clear channel statistic counters
2064 */
2065 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2066 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2067 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 2068}
2069
9e33a355
HS		 2070static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2071{
2072 u8 tssi_bounds[9];
2073 u8 current_tssi;
2074 u16 eeprom;
2075 u8 step;
2076 int i;
2077
2078 /*
2079 * Read TSSI boundaries for temperature compensation from
2080 * the EEPROM.
2081 *
2082 * Array idx 0 1 2 3 4 5 6 7 8
2083 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2084 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2085 */
2086 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2087 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2088 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2089 EEPROM_TSSI_BOUND_BG1_MINUS4);
2090 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2091 EEPROM_TSSI_BOUND_BG1_MINUS3);
2092
2093 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2094 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2095 EEPROM_TSSI_BOUND_BG2_MINUS2);
2096 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2097 EEPROM_TSSI_BOUND_BG2_MINUS1);
2098
2099 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2100 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2101 EEPROM_TSSI_BOUND_BG3_REF);
2102 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2103 EEPROM_TSSI_BOUND_BG3_PLUS1);
2104
2105 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2106 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2107 EEPROM_TSSI_BOUND_BG4_PLUS2);
2108 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2109 EEPROM_TSSI_BOUND_BG4_PLUS3);
2110
2111 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2112 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2113 EEPROM_TSSI_BOUND_BG5_PLUS4);
2114
2115 step = rt2x00_get_field16(eeprom,
2116 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2117 } else {
2118 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2119 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2120 EEPROM_TSSI_BOUND_A1_MINUS4);
2121 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2122 EEPROM_TSSI_BOUND_A1_MINUS3);
2123
2124 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2125 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2126 EEPROM_TSSI_BOUND_A2_MINUS2);
2127 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2128 EEPROM_TSSI_BOUND_A2_MINUS1);
2129
2130 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2131 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2132 EEPROM_TSSI_BOUND_A3_REF);
2133 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2134 EEPROM_TSSI_BOUND_A3_PLUS1);
2135
2136 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2137 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2138 EEPROM_TSSI_BOUND_A4_PLUS2);
2139 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2140 EEPROM_TSSI_BOUND_A4_PLUS3);
2141
2142 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2143 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2144 EEPROM_TSSI_BOUND_A5_PLUS4);
2145
2146 step = rt2x00_get_field16(eeprom,
2147 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2148 }
2149
2150 /*
2151 * Check if temperature compensation is supported.
2152 */
2153 if (tssi_bounds[4] == 0xff)
2154 return 0;
2155
2156 /*
2157 * Read current TSSI (BBP 49).
2158 */
2159 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2160
2161 /*
2162 * Compare TSSI value (BBP49) with the compensation boundaries
2163 * from the EEPROM and increase or decrease tx power.
2164 */
2165 for (i = 0; i <= 3; i++) {
2166 if (current_tssi > tssi_bounds[i])
2167 break;
2168 }
2169
2170 if (i == 4) {
2171 for (i = 8; i >= 5; i--) {
2172 if (current_tssi < tssi_bounds[i])
2173 break;
2174 }
2175 }
2176
2177 return (i - 4) * step;
2178}
2179
e90c54b2
RJH		 2180static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2181 enum ieee80211_band band)
2182{
2183 u16 eeprom;
2184 u8 comp_en;
2185 u8 comp_type;
75faae8b 2186 int comp_value = 0;
e90c54b2
RJH		 2187
2188 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2189
75faae8b
HS		 2190 /*
2191 * HT40 compensation not required.
2192 */
2193 if (eeprom == 0xffff ||
2194 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2195 return 0;
2196
2197 if (band == IEEE80211_BAND_2GHZ) {
2198 comp_en = rt2x00_get_field16(eeprom,
2199 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2200 if (comp_en) {
2201 comp_type = rt2x00_get_field16(eeprom,
2202 EEPROM_TXPOWER_DELTA_TYPE_2G);
2203 comp_value = rt2x00_get_field16(eeprom,
2204 EEPROM_TXPOWER_DELTA_VALUE_2G);
2205 if (!comp_type)
2206 comp_value = -comp_value;
2207 }
2208 } else {
2209 comp_en = rt2x00_get_field16(eeprom,
2210 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2211 if (comp_en) {
2212 comp_type = rt2x00_get_field16(eeprom,
2213 EEPROM_TXPOWER_DELTA_TYPE_5G);
2214 comp_value = rt2x00_get_field16(eeprom,
2215 EEPROM_TXPOWER_DELTA_VALUE_5G);
2216 if (!comp_type)
2217 comp_value = -comp_value;
2218 }
2219 }
2220
2221 return comp_value;
2222}
2223
fa71a160
HS		 2224static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2225 enum ieee80211_band band, int power_level,
2226 u8 txpower, int delta)
e90c54b2
RJH		 2227{
2228 u32 reg;
2229 u16 eeprom;
2230 u8 criterion;
2231 u8 eirp_txpower;
2232 u8 eirp_txpower_criterion;
2233 u8 reg_limit;
e90c54b2
RJH		 2234
2235 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2236 return txpower;
2237
7dab73b3 2238 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2239 /*
2240 * Check if eirp txpower exceed txpower_limit.
2241 * We use OFDM 6M as criterion and its eirp txpower
2242 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2243 * .11b data rate need add additional 4dbm
2244 * when calculating eirp txpower.
2245 */
2246 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2247 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2248
2249 rt2x00_eeprom_read(rt2x00dev,
2250 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2251
2252 if (band == IEEE80211_BAND_2GHZ)
2253 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2254 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2255 else
2256 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2257 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2258
2259 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2260 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2261
2262 reg_limit = (eirp_txpower > power_level) ?
2263 (eirp_txpower - power_level) : 0;
2264 } else
2265 reg_limit = 0;
2266
2af242e1 2267 return txpower + delta - reg_limit;
e90c54b2
RJH		 2268}
2269
f4450616 2270static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2271 enum ieee80211_band band,
2272 int power_level)
f4450616 2273{
5e846004 2274 u8 txpower;
5e846004 2275 u16 eeprom;
e90c54b2 2276 int i, is_rate_b;
f4450616 2277 u32 reg;
f4450616 2278 u8 r1;
5e846004 2279 u32 offset;
2af242e1
HS		 2280 int delta;
2281
2282 /*
2283 * Calculate HT40 compensation delta
2284 */
2285 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2286
9e33a355
HS		 2287 /*
2288 * calculate temperature compensation delta
2289 */
2290 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2291
5e846004 2292 /*
e90c54b2 2293 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2294 */
f4450616 2295 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2296 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2297 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2298 offset = TX_PWR_CFG_0;
2299
2300 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2301 /* just to be safe */
2302 if (offset > TX_PWR_CFG_4)
2303 break;
2304
2305 rt2800_register_read(rt2x00dev, offset, &reg);
2306
2307 /* read the next four txpower values */
2308 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2309 &eeprom);
2310
e90c54b2
RJH		 2311 is_rate_b = i ? 0 : 1;
2312 /*
2313 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2314 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2315 * TX_PWR_CFG_4: unknown
2316 */
5e846004
HS		 2317 txpower = rt2x00_get_field16(eeprom,
2318 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2319 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2320 power_level, txpower, delta);
e90c54b2 2321 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2322
e90c54b2
RJH		 2323 /*
2324 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2325 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2326 * TX_PWR_CFG_4: unknown
2327 */
5e846004
HS		 2328 txpower = rt2x00_get_field16(eeprom,
2329 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2330 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2331 power_level, txpower, delta);
e90c54b2 2332 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2333
e90c54b2
RJH		 2334 /*
2335 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2336 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2337 * TX_PWR_CFG_4: unknown
2338 */
5e846004
HS		 2339 txpower = rt2x00_get_field16(eeprom,
2340 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2341 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2342 power_level, txpower, delta);
e90c54b2 2343 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2344
e90c54b2
RJH		 2345 /*
2346 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2347 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2348 * TX_PWR_CFG_4: unknown
2349 */
5e846004
HS		 2350 txpower = rt2x00_get_field16(eeprom,
2351 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2352 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2353 power_level, txpower, delta);
e90c54b2 2354 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2355
2356 /* read the next four txpower values */
2357 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2358 &eeprom);
2359
e90c54b2
RJH		 2360 is_rate_b = 0;
2361 /*
2362 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2363 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2364 * TX_PWR_CFG_4: unknown
2365 */
5e846004
HS		 2366 txpower = rt2x00_get_field16(eeprom,
2367 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2368 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2369 power_level, txpower, delta);
e90c54b2 2370 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2371
e90c54b2
RJH		 2372 /*
2373 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2374 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2375 * TX_PWR_CFG_4: unknown
2376 */
5e846004
HS		 2377 txpower = rt2x00_get_field16(eeprom,
2378 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2379 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2380 power_level, txpower, delta);
e90c54b2 2381 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2382
e90c54b2
RJH		 2383 /*
2384 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2385 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2386 * TX_PWR_CFG_4: unknown
2387 */
5e846004
HS		 2388 txpower = rt2x00_get_field16(eeprom,
2389 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2390 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2391 power_level, txpower, delta);
e90c54b2 2392 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2393
e90c54b2
RJH		 2394 /*
2395 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2396 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2397 * TX_PWR_CFG_4: unknown
2398 */
5e846004
HS		 2399 txpower = rt2x00_get_field16(eeprom,
2400 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2401 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2402 power_level, txpower, delta);
e90c54b2 2403 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2404
2405 rt2800_register_write(rt2x00dev, offset, reg);
2406
2407 /* next TX_PWR_CFG register */
2408 offset += 4;
2409 }
f4450616
BZ		 2410}
2411
9e33a355
HS		 2412void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2413{
2414 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2415 rt2x00dev->tx_power);
2416}
2417EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2418
f4450616
BZ		 2419static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2420 struct rt2x00lib_conf *libconf)
2421{
2422 u32 reg;
2423
2424 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2425 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2426 libconf->conf->short_frame_max_tx_count);
2427 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2428 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2429 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2430}
2431
2432static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2433 struct rt2x00lib_conf *libconf)
2434{
2435 enum dev_state state =
2436 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2437 STATE_SLEEP : STATE_AWAKE;
2438 u32 reg;
2439
2440 if (state == STATE_SLEEP) {
2441 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2442
2443 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2444 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2445 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2446 libconf->conf->listen_interval - 1);
2447 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2448 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2449
2450 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2451 } else {
f4450616
BZ		 2452 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2453 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2454 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2455 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2456 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2457
2458 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2459 }
2460}
2461
2462void rt2800_config(struct rt2x00_dev *rt2x00dev,
2463 struct rt2x00lib_conf *libconf,
2464 const unsigned int flags)
2465{
2466 /* Always recalculate LNA gain before changing configuration */
2467 rt2800_config_lna_gain(rt2x00dev, libconf);
2468
e90c54b2 2469 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2470 rt2800_config_channel(rt2x00dev, libconf->conf,
2471 &libconf->rf, &libconf->channel);
9e33a355
HS		 2472 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2473 libconf->conf->power_level);
e90c54b2 2474 }
f4450616 2475 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2476 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2477 libconf->conf->power_level);
f4450616
BZ		 2478 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2479 rt2800_config_retry_limit(rt2x00dev, libconf);
2480 if (flags & IEEE80211_CONF_CHANGE_PS)
2481 rt2800_config_ps(rt2x00dev, libconf);
2482}
2483EXPORT_SYMBOL_GPL(rt2800_config);
2484
2485/*
2486 * Link tuning
2487 */
2488void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2489{
2490 u32 reg;
2491
2492 /*
2493 * Update FCS error count from register.
2494 */
2495 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2496 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2497}
2498EXPORT_SYMBOL_GPL(rt2800_link_stats);
2499
2500static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2501{
2502 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2503 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2504 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2505 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2506 rt2x00_rt(rt2x00dev, RT3390) ||
2507 rt2x00_rt(rt2x00dev, RT5390))
f4450616
BZ		 2508 return 0x1c + (2 * rt2x00dev->lna_gain);
2509 else
2510 return 0x2e + rt2x00dev->lna_gain;
2511 }
2512
2513 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2514 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2515 else
2516 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2517}
2518
2519static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2520 struct link_qual *qual, u8 vgc_level)
2521{
2522 if (qual->vgc_level != vgc_level) {
2523 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2524 qual->vgc_level = vgc_level;
2525 qual->vgc_level_reg = vgc_level;
2526 }
2527}
2528
2529void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2530{
2531 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2532}
2533EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2534
2535void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2536 const u32 count)
2537{
8d0c9b65 2538 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2539 return;
2540
2541 /*
2542 * When RSSI is better then -80 increase VGC level with 0x10
2543 */
2544 rt2800_set_vgc(rt2x00dev, qual,
2545 rt2800_get_default_vgc(rt2x00dev) +
2546 ((qual->rssi > -80) * 0x10));
2547}
2548EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2549
2550/*
2551 * Initialization functions.
2552 */
b9a07ae9 2553static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2554{
2555 u32 reg;
d5385bfc 2556 u16 eeprom;
fcf51541 2557 unsigned int i;
e3a896b9 2558 int ret;
fcf51541 2559
a9dce149
GW		 2560 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2561 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2562 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2563 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2564 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2565 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2566 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2567
e3a896b9
GW		 2568 ret = rt2800_drv_init_registers(rt2x00dev);
2569 if (ret)
2570 return ret;
fcf51541
BZ		 2571
2572 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2573 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2574 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2575 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2576 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2577 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2578
2579 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2580 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2581 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2582 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2583 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2584 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2585
2586 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2587 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2588
2589 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2590
2591 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2592 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2593 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2594 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2595 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2596 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2597 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2598 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2599
a9dce149
GW		 2600 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2601
2602 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2603 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2604 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2605 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2606
64522957 2607 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2608 rt2x00_rt(rt2x00dev, RT3090) ||
2609 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2610 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2611 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2612 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2613 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2614 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2615 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2616 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2617 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2618 0x0000002c);
2619 else
2620 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2621 0x0000000f);
2622 } else {
2623 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2624 }
d5385bfc 2625 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2626 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2627
2628 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2629 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2630 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2631 } else {
2632 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2633 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2634 }
c295a81d
HS		 2635 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2636 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2637 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 2638 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
872834df
GW		 2639 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2640 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2641 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
adde5882
GJ		 2642 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2643 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2644 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2645 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2646 } else {
2647 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2648 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2649 }
2650
2651 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2652 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2653 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2654 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2655 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2656 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2657 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2658 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2659 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2660 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2661
2662 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2663 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2664 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2665 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2666 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2667
2668 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2669 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2670 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2671 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2672 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2673 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2674 else
2675 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2676 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2677 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2678 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2679
a9dce149
GW		 2680 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2681 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2682 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2683 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2684 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2685 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2686 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2687 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2688 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2689
fcf51541
BZ		 2690 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2691
a9dce149
GW		 2692 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2693 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2694 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2695 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2696 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2697 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2698 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2699 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2700
fcf51541
BZ		 2701 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2702 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2703 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2704 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2705 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2706 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2707 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2708 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2709 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2710
2711 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2712 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2713 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2714 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2715 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2716 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2717 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2718 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2719 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2720 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2721 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2722 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2723
2724 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2725 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2726 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2727 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2728 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2729 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2730 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2731 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2732 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2734 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2735 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2736
2737 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2738 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2739 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2740 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2741 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2742 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2743 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2744 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2745 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2746 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2747 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2748 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2749
2750 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2751 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2752 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2753 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2754 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2755 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2756 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2757 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2758 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2759 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2760 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2761 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2762
2763 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2764 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2765 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2766 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2767 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2768 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2769 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2770 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2771 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2772 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2773 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2774 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2775
2776 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2777 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2778 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2779 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2780 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2781 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2782 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2783 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2784 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2785 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2786 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2787 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2788
cea90e55 2789 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2790 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2791
2792 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2793 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2794 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2795 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2796 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2797 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2798 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2799 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2800 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2801 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2802 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2803 }
2804
961621ab
HS		 2805 /*
2806 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2807 * although it is reserved.
2808 */
2809 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2810 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2811 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2812 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2813 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2814 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2815 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2816 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2817 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2818 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2819 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2820 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2821
fcf51541
BZ		 2822 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2823
2824 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2825 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2826 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2827 IEEE80211_MAX_RTS_THRESHOLD);
2828 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2829 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2830
2831 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2832
a21c2ab4
HS		 2833 /*
2834 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2835 * time should be set to 16. However, the original Ralink driver uses
2836 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2837 * connection problems with 11g + CTS protection. Hence, use the same
2838 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2839 */
a9dce149 2840 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2841 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2842 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2843 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2844 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2845 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2846 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2847
fcf51541
BZ		 2848 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2849
2850 /*
2851 * ASIC will keep garbage value after boot, clear encryption keys.
2852 */
2853 for (i = 0; i < 4; i++)
2854 rt2800_register_write(rt2x00dev,
2855 SHARED_KEY_MODE_ENTRY(i), 0);
2856
2857 for (i = 0; i < 256; i++) {
d7d259d3
HS		 2858 rt2800_config_wcid(rt2x00dev, NULL, i);
2859 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 2860 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2861 }
2862
2863 /*
2864 * Clear all beacons
fcf51541 2865 */
69cf36a4
HS		 2866 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2867 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2868 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2869 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2870 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2871 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2872 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2873 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2874
cea90e55 2875 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2876 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2877 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2878 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2879 } else if (rt2x00_is_pcie(rt2x00dev)) {
2880 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2881 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2882 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2883 }
2884
2885 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2886 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2887 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2888 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2889 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2890 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2891 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2892 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2893 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2894 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2895
2896 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2897 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2898 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2899 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2900 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2901 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2902 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2903 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2904 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2905 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2906
2907 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2908 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2909 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2910 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2911 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2912 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2913 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2914 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2915 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2916 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2917
2918 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2919 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2920 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2921 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2922 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2923 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2924
47ee3eb1
HS		 2925 /*
2926 * Do not force the BA window size, we use the TXWI to set it
2927 */
2928 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2929 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2930 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2931 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2932
fcf51541
BZ		 2933 /*
2934 * We must clear the error counters.
2935 * These registers are cleared on read,
2936 * so we may pass a useless variable to store the value.
2937 */
2938 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2939 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2940 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2941 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2942 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2943 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2944
9f926fb5
HS		 2945 /*
2946 * Setup leadtime for pre tbtt interrupt to 6ms
2947 */
2948 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2949 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2950 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2951
977206d7
HS		 2952 /*
2953 * Set up channel statistics timer
2954 */
2955 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2956 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2957 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2958 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2959 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2960 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2961 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2962
fcf51541
BZ		 2963 return 0;
2964}
fcf51541
BZ		 2965
2966static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2967{
2968 unsigned int i;
2969 u32 reg;
2970
2971 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2972 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2973 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2974 return 0;
2975
2976 udelay(REGISTER_BUSY_DELAY);
2977 }
2978
2979 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2980 return -EACCES;
2981}
2982
2983static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2984{
2985 unsigned int i;
2986 u8 value;
2987
2988 /*
2989 * BBP was enabled after firmware was loaded,
2990 * but we need to reactivate it now.
2991 */
2992 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2993 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2994 msleep(1);
2995
2996 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2997 rt2800_bbp_read(rt2x00dev, 0, &value);
2998 if ((value != 0xff) && (value != 0x00))
2999 return 0;
3000 udelay(REGISTER_BUSY_DELAY);
3001 }
3002
3003 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3004 return -EACCES;
3005}
3006
b9a07ae9 3007static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3008{
3009 unsigned int i;
3010 u16 eeprom;
3011 u8 reg_id;
3012 u8 value;
3013
3014 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3015 rt2800_wait_bbp_ready(rt2x00dev)))
3016 return -EACCES;
3017
adde5882
GJ		 3018 if (rt2x00_rt(rt2x00dev, RT5390)) {
3019 rt2800_bbp_read(rt2x00dev, 4, &value);
3020 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3021 rt2800_bbp_write(rt2x00dev, 4, value);
3022 }
60687ba7 3023
adde5882 3024 if (rt2800_is_305x_soc(rt2x00dev) ||
872834df 3025 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3026 rt2x00_rt(rt2x00dev, RT5390))
baff8006
HS		 3027 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3028
fcf51541
BZ		 3029 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3030 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3031
adde5882
GJ		 3032 if (rt2x00_rt(rt2x00dev, RT5390))
3033 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3034
a9dce149
GW		 3035 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3036 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3037 rt2800_bbp_write(rt2x00dev, 73, 0x12);
adde5882
GJ		 3038 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3039 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3040 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3041 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3042 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3043 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3044 } else {
3045 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3046 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3047 }
3048
fcf51541 3049 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3050
d5385bfc 3051 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3052 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3053 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3054 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3055 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3056 rt2x00_rt(rt2x00dev, RT5390)) {
8cdd15e0
GW		 3057 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3058 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3059 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3060 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3061 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3062 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 3063 } else {
3064 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3065 }
3066
fcf51541 3067 rt2800_bbp_write(rt2x00dev, 82, 0x62);
adde5882
GJ		 3068 if (rt2x00_rt(rt2x00dev, RT5390))
3069 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3070 else
3071 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3072
5ed8f458 3073 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3074 rt2800_bbp_write(rt2x00dev, 84, 0x19);
adde5882
GJ		 3075 else if (rt2x00_rt(rt2x00dev, RT5390))
3076 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3077 else
3078 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3079
adde5882
GJ		 3080 if (rt2x00_rt(rt2x00dev, RT5390))
3081 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3082 else
3083 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3084
fcf51541 3085 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3086
adde5882
GJ		 3087 if (rt2x00_rt(rt2x00dev, RT5390))
3088 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3089 else
3090 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3091
d5385bfc 3092 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3093 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3094 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3095 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
872834df 3096 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3097 rt2x00_rt(rt2x00dev, RT5390) ||
baff8006 3098 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3099 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3100 else
3101 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3102
adde5882
GJ		 3103 if (rt2x00_rt(rt2x00dev, RT5390))
3104 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3105
baff8006
HS		 3106 if (rt2800_is_305x_soc(rt2x00dev))
3107 rt2800_bbp_write(rt2x00dev, 105, 0x01);
adde5882
GJ		 3108 else if (rt2x00_rt(rt2x00dev, RT5390))
3109 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3110 else
3111 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3112
adde5882
GJ		 3113 if (rt2x00_rt(rt2x00dev, RT5390))
3114 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3115 else
3116 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3117
adde5882
GJ		 3118 if (rt2x00_rt(rt2x00dev, RT5390))
3119 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3120
64522957 3121 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3122 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3123 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3124 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3125 rt2x00_rt(rt2x00dev, RT5390)) {
d5385bfc 3126 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3127
38c8a566
RJH		 3128 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3129 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3130 value |= 0x20;
38c8a566 3131 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3132 value &= ~0x02;
fcf51541 3133
d5385bfc 3134 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3135 }
3136
adde5882
GJ		 3137 if (rt2x00_rt(rt2x00dev, RT5390)) {
3138 int ant, div_mode;
3139
3140 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3141 div_mode = rt2x00_get_field16(eeprom,
3142 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3143 ant = (div_mode == 3) ? 1 : 0;
3144
3145 /* check if this is a Bluetooth combo card */
fdbc7b0a 3146 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3147 u32 reg;
3148
3149 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3150 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3151 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3152 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3153 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3154 if (ant == 0)
3155 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3156 else if (ant == 1)
3157 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3158 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3159 }
3160
3161 rt2800_bbp_read(rt2x00dev, 152, &value);
3162 if (ant == 0)
3163 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3164 else
3165 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3166 rt2800_bbp_write(rt2x00dev, 152, value);
3167
3168 /* Init frequency calibration */
3169 rt2800_bbp_write(rt2x00dev, 142, 1);
3170 rt2800_bbp_write(rt2x00dev, 143, 57);
3171 }
fcf51541
BZ		 3172
3173 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3174 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3175
3176 if (eeprom != 0xffff && eeprom != 0x0000) {
3177 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3178 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3179 rt2800_bbp_write(rt2x00dev, reg_id, value);
3180 }
3181 }
3182
3183 return 0;
3184}
fcf51541
BZ		 3185
3186static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3187 bool bw40, u8 rfcsr24, u8 filter_target)
3188{
3189 unsigned int i;
3190 u8 bbp;
3191 u8 rfcsr;
3192 u8 passband;
3193 u8 stopband;
3194 u8 overtuned = 0;
3195
3196 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3197
3198 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3199 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3200 rt2800_bbp_write(rt2x00dev, 4, bbp);
3201
80d184e6
RJH		 3202 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3203 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3204 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3205
fcf51541
BZ		 3206 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3207 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3208 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3209
3210 /*
3211 * Set power & frequency of passband test tone
3212 */
3213 rt2800_bbp_write(rt2x00dev, 24, 0);
3214
3215 for (i = 0; i < 100; i++) {
3216 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3217 msleep(1);
3218
3219 rt2800_bbp_read(rt2x00dev, 55, &passband);
3220 if (passband)
3221 break;
3222 }
3223
3224 /*
3225 * Set power & frequency of stopband test tone
3226 */
3227 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3228
3229 for (i = 0; i < 100; i++) {
3230 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3231 msleep(1);
3232
3233 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3234
3235 if ((passband - stopband) <= filter_target) {
3236 rfcsr24++;
3237 overtuned += ((passband - stopband) == filter_target);
3238 } else
3239 break;
3240
3241 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3242 }
3243
3244 rfcsr24 -= !!overtuned;
3245
3246 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3247 return rfcsr24;
3248}
3249
b9a07ae9 3250static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3251{
3252 u8 rfcsr;
3253 u8 bbp;
8cdd15e0
GW		 3254 u32 reg;
3255 u16 eeprom;
fcf51541 3256
d5385bfc 3257 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3258 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3259 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3260 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3261 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3262 !rt2x00_rt(rt2x00dev, RT5390) &&
baff8006 3263 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3264 return 0;
3265
fcf51541
BZ		 3266 /*
3267 * Init RF calibration.
3268 */
adde5882
GJ		 3269 if (rt2x00_rt(rt2x00dev, RT5390)) {
3270 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3271 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3272 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3273 msleep(1);
3274 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3275 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3276 } else {
3277 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3278 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3279 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3280 msleep(1);
3281 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3282 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3283 }
fcf51541 3284
d5385bfc 3285 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3286 rt2x00_rt(rt2x00dev, RT3071) ||
3287 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3288 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3289 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3290 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3291 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3292 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3293 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3294 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3295 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3296 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3297 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3298 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3299 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3300 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3301 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3302 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3303 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3304 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3305 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3306 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3307 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3308 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3309 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3310 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3311 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3312 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3313 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3314 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3315 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3316 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3317 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3318 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3319 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3320 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3321 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3322 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3323 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3324 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3325 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3326 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3327 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3328 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3329 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3330 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3331 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3332 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3333 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3334 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3335 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3336 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3337 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3338 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3339 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3340 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3341 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3342 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3343 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3344 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3345 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3346 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3347 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3348 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3349 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3350 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3351 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3352 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3353 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3354 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3355 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3356 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3357 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3358 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3359 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3360 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3361 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3362 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3363 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3364 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3365 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3366 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3367 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3368 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3369 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3370 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3371 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 3372 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3373 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3374 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3375 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3376 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3377 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3378 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3379 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3380 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3381 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3382 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3383 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3384 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3385 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3386 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3387 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3388 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3389 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3390 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3391 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3392 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3393 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3394 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3395 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3396 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3397 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3398 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3399 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3400 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3401 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3402 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3403 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3404 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3405 return 0;
adde5882
GJ		 3406 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3407 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3408 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3409 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3410 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3411 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3412 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3413 else
3414 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3415 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3416 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3417 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3418 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3419 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3420 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3421 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3422 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3423 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3424 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3425
3426 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3427 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3428 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3429 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3430 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3431 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3432 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3433 else
3434 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3435 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3436 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3437 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3438 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3439
3440 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3441 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3442 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3443 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3444 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3445 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3446 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3447 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3448 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3449 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3450
3451 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3452 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3453 else
3454 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3455 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3456 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3457 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3458 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3459 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3460 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3461 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3462 else
3463 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3464 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3465 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3466 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3467
3468 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3469 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3470 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3471 else
3472 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3473 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3474 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3475 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3476 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3477 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3478 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3479
3480 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3481 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3482 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3483 else
3484 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3485 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3486 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8cdd15e0
GW		 3487 }
3488
3489 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3490 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3491 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3492 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3493 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3494 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3495 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3496 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3497
d5385bfc
GW		 3498 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3499 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3500 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3501
d5385bfc
GW		 3502 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3503 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3504 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3505 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3506 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3507 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3508 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3509 else
3510 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3511 }
3512 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3513
3514 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3515 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3516 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3517 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3518 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3519 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3520 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 3521 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3522 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3523 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3524 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3525
3526 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3527 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3528 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3529 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3530 msleep(1);
3531 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3532 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3533 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 3534 }
3535
3536 /*
3537 * Set RX Filter calibration for 20MHz and 40MHz
3538 */
8cdd15e0
GW		 3539 if (rt2x00_rt(rt2x00dev, RT3070)) {
3540 rt2x00dev->calibration[0] =
3541 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3542 rt2x00dev->calibration[1] =
3543 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3544 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3545 rt2x00_rt(rt2x00dev, RT3090) ||
872834df
GW		 3546 rt2x00_rt(rt2x00dev, RT3390) ||
3547 rt2x00_rt(rt2x00dev, RT3572)) {
d5385bfc
GW		 3548 rt2x00dev->calibration[0] =
3549 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3550 rt2x00dev->calibration[1] =
3551 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3552 }
fcf51541 3553
adde5882
GJ		 3554 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3555 /*
3556 * Set back to initial state
3557 */
3558 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3559
adde5882
GJ		 3560 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3561 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3562 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3563
adde5882
GJ		 3564 /*
3565 * Set BBP back to BW20
3566 */
3567 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3568 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3569 rt2800_bbp_write(rt2x00dev, 4, bbp);
3570 }
fcf51541 3571
d5385bfc 3572 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3573 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3574 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3575 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3576 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3577
3578 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3579 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3580 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3581
adde5882
GJ		 3582 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3583 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3584 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3585 if (rt2x00_rt(rt2x00dev, RT3070) ||
3586 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3587 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3588 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3589 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3590 &rt2x00dev->cap_flags))
adde5882
GJ		 3591 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3592 }
3593 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3594 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3595 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3596 rt2x00_get_field16(eeprom,
3597 EEPROM_TXMIXER_GAIN_BG_VAL));
3598 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3599 }
8cdd15e0 3600
64522957
GW		 3601 if (rt2x00_rt(rt2x00dev, RT3090)) {
3602 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3603
80d184e6 3604 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3605 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3606 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3607 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3608 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3609 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3610
3611 rt2800_bbp_write(rt2x00dev, 138, bbp);
3612 }
3613
3614 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3615 rt2x00_rt(rt2x00dev, RT3090) ||
3616 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3617 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3618 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3619 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3620 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3621 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3622 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3623 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3624
3625 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3626 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3627 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3628
3629 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3630 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3631 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3632
3633 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3634 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3635 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3636 }
3637
80d184e6 3638 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3639 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3640 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3641 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3642 else
3643 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3644 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3645 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3646 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3647 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3648 }
3649
adde5882
GJ		 3650 if (rt2x00_rt(rt2x00dev, RT5390)) {
3651 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3652 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3653 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3654
adde5882
GJ		 3655 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3656 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3657 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3658
adde5882
GJ		 3659 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3660 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3661 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3662 }
60687ba7 3663
fcf51541
BZ		 3664 return 0;
3665}
b9a07ae9
ID		 3666
3667int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3668{
3669 u32 reg;
3670 u16 word;
3671
3672 /*
3673 * Initialize all registers.
3674 */
3675 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3676 rt2800_init_registers(rt2x00dev) ||
3677 rt2800_init_bbp(rt2x00dev) ||
3678 rt2800_init_rfcsr(rt2x00dev)))
3679 return -EIO;
3680
3681 /*
3682 * Send signal to firmware during boot time.
3683 */
3684 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3685
3686 if (rt2x00_is_usb(rt2x00dev) &&
3687 (rt2x00_rt(rt2x00dev, RT3070) ||
3688 rt2x00_rt(rt2x00dev, RT3071) ||
3689 rt2x00_rt(rt2x00dev, RT3572))) {
3690 udelay(200);
3691 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3692 udelay(10);
3693 }
3694
3695 /*
3696 * Enable RX.
3697 */
3698 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3699 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3700 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3701 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3702
3703 udelay(50);
3704
3705 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3706 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3707 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3708 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3709 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3710 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3711
3712 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3713 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3714 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3715 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3716
3717 /*
3718 * Initialize LED control
3719 */
38c8a566
RJH		 3720 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3721 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3722 word & 0xff, (word >> 8) & 0xff);
3723
38c8a566
RJH		 3724 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3725 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3726 word & 0xff, (word >> 8) & 0xff);
3727
38c8a566
RJH		 3728 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3729 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3730 word & 0xff, (word >> 8) & 0xff);
3731
3732 return 0;
3733}
3734EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3735
3736void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3737{
3738 u32 reg;
3739
3740 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3741 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 3742 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 3743 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3744
3745 /* Wait for DMA, ignore error */
3746 rt2800_wait_wpdma_ready(rt2x00dev);
3747
3748 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3749 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3750 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3751 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 3752}
3753EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 3754
30e84034
BZ		 3755int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3756{
3757 u32 reg;
3758
3759 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3760
3761 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3762}
3763EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3764
3765static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3766{
3767 u32 reg;
3768
31a4cf1f
GW		 3769 mutex_lock(&rt2x00dev->csr_mutex);
3770
3771 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3772 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3773 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3774 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3775 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3776
3777 /* Wait until the EEPROM has been loaded */
3778 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3779
3780 /* Apparently the data is read from end to start */
daabead1
LF		 3781 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3782 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 3783 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
daabead1
LF		 3784 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3785 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3786 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3787 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3788 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3789 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 3790
3791 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3792}
3793
3794void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3795{
3796 unsigned int i;
3797
3798 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3799 rt2800_efuse_read(rt2x00dev, i);
3800}
3801EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3802
38bd7b8a
BZ		 3803int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3804{
3805 u16 word;
3806 u8 *mac;
3807 u8 default_lna_gain;
3808
3809 /*
3810 * Start validation of the data that has been read.
3811 */
3812 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3813 if (!is_valid_ether_addr(mac)) {
3814 random_ether_addr(mac);
3815 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3816 }
3817
38c8a566 3818 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3819 if (word == 0xffff) {
38c8a566
RJH		 3820 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3821 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3822 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3823 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3824 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3825 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3826 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3827 /*
3828 * There is a max of 2 RX streams for RT28x0 series
3829 */
38c8a566
RJH		 3830 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3831 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3832 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3833 }
3834
38c8a566 3835 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3836 if (word == 0xffff) {
38c8a566
RJH		 3837 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3838 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3839 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3840 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3841 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3842 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3843 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3844 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3845 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3846 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3847 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3848 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3849 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3850 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3851 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3852 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3853 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3854 }
3855
3856 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3857 if ((word & 0x00ff) == 0x00ff) {
3858 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3859 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3860 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3861 }
3862 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3863 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3864 LED_MODE_TXRX_ACTIVITY);
3865 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3866 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3867 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3868 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3869 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3870 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3871 }
3872
3873 /*
3874 * During the LNA validation we are going to use
3875 * lna0 as correct value. Note that EEPROM_LNA
3876 * is never validated.
3877 */
3878 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3879 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3880
3881 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3882 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3883 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3884 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3885 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3886 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3887
3888 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3889 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3890 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3891 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3892 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3893 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3894 default_lna_gain);
3895 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3896
3897 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3898 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3899 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3900 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3901 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3902 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3903
3904 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3905 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3906 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3907 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3908 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3909 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3910 default_lna_gain);
3911 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3912
3913 return 0;
3914}
3915EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3916
3917int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3918{
3919 u32 reg;
3920 u16 value;
3921 u16 eeprom;
3922
3923 /*
3924 * Read EEPROM word for configuration.
3925 */
38c8a566 3926 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3927
3928 /*
adde5882
GJ		 3929 * Identify RF chipset by EEPROM value
3930 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3931 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 3932 */
38bd7b8a 3933 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
adde5882
GJ		 3934 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3935 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3936 else
3937 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 3938
49e721ec
GW		 3939 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3940 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3941
5aa57015
GW		 3942 switch (rt2x00dev->chip.rt) {
3943 case RT2860:
3944 case RT2872:
3945 case RT2883:
3946 case RT3070:
3947 case RT3071:
3948 case RT3090:
3949 case RT3390:
3950 case RT3572:
3951 case RT5390:
3952 break;
3953 default:
49e721ec
GW		 3954 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3955 return -ENODEV;
f273fe55 3956 }
714fa663 3957
d331eb51
LF		 3958 switch (rt2x00dev->chip.rf) {
3959 case RF2820:
3960 case RF2850:
3961 case RF2720:
3962 case RF2750:
3963 case RF3020:
3964 case RF2020:
3965 case RF3021:
3966 case RF3022:
3967 case RF3052:
3968 case RF3320:
3969 case RF5370:
3970 case RF5390:
3971 break;
3972 default:
3973 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
3974 rt2x00dev->chip.rf);
38bd7b8a
BZ		 3975 return -ENODEV;
3976 }
3977
3978 /*
3979 * Identify default antenna configuration.
3980 */
d96aa640 3981 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3982 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3983 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3984 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3985
d96aa640
RJH		 3986 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3987
3988 if (rt2x00_rt(rt2x00dev, RT3070) ||
3989 rt2x00_rt(rt2x00dev, RT3090) ||
3990 rt2x00_rt(rt2x00dev, RT3390)) {
3991 value = rt2x00_get_field16(eeprom,
3992 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3993 switch (value) {
3994 case 0:
3995 case 1:
3996 case 2:
3997 rt2x00dev->default_ant.tx = ANTENNA_A;
3998 rt2x00dev->default_ant.rx = ANTENNA_A;
3999 break;
4000 case 3:
4001 rt2x00dev->default_ant.tx = ANTENNA_A;
4002 rt2x00dev->default_ant.rx = ANTENNA_B;
4003 break;
4004 }
4005 } else {
4006 rt2x00dev->default_ant.tx = ANTENNA_A;
4007 rt2x00dev->default_ant.rx = ANTENNA_A;
4008 }
4009
38bd7b8a 4010 /*
9328fdac 4011 * Determine external LNA informations.
38bd7b8a 4012 */
38c8a566 4013 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4014 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4015 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4016 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4017
4018 /*
4019 * Detect if this device has an hardware controlled radio.
4020 */
38c8a566 4021 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4022 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4023
fdbc7b0a
GW		 4024 /*
4025 * Detect if this device has Bluetooth co-existence.
4026 */
4027 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4028 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4029
9328fdac
GW		 4030 /*
4031 * Read frequency offset and RF programming sequence.
4032 */
4033 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4034 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4035
38bd7b8a
BZ		 4036 /*
4037 * Store led settings, for correct led behaviour.
4038 */
4039#ifdef CONFIG_RT2X00_LIB_LEDS
4040 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4041 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4042 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4043
9328fdac 4044 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4045#endif /* CONFIG_RT2X00_LIB_LEDS */
4046
e90c54b2
RJH		 4047 /*
4048 * Check if support EIRP tx power limit feature.
4049 */
4050 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4051
4052 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4053 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4054 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4055
38bd7b8a
BZ		 4056 return 0;
4057}
4058EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4059
4da2933f 4060/*
55f9321a 4061 * RF value list for rt28xx
4da2933f
BZ		 4062 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4063 */
4064static const struct rf_channel rf_vals[] = {
4065 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4066 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4067 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4068 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4069 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4070 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4071 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4072 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4073 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4074 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4075 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4076 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4077 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4078 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4079
4080 /* 802.11 UNI / HyperLan 2 */
4081 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4082 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4083 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4084 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4085 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4086 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4087 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4088 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4089 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4090 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4091 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4092 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4093
4094 /* 802.11 HyperLan 2 */
4095 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4096 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4097 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4098 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4099 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4100 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4101 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4102 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4103 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4104 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4105 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4106 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4107 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4108 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4109 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4110 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4111
4112 /* 802.11 UNII */
4113 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4114 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4115 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4116 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4117 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4118 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4119 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4120 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4121 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4122 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4123 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4124
4125 /* 802.11 Japan */
4126 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4127 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4128 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4129 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4130 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4131 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4132 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4133};
4134
4135/*
55f9321a
ID		 4136 * RF value list for rt3xxx
4137 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4138 */
55f9321a 4139static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4140 {1, 241, 2, 2 },
4141 {2, 241, 2, 7 },
4142 {3, 242, 2, 2 },
4143 {4, 242, 2, 7 },
4144 {5, 243, 2, 2 },
4145 {6, 243, 2, 7 },
4146 {7, 244, 2, 2 },
4147 {8, 244, 2, 7 },
4148 {9, 245, 2, 2 },
4149 {10, 245, 2, 7 },
4150 {11, 246, 2, 2 },
4151 {12, 246, 2, 7 },
4152 {13, 247, 2, 2 },
4153 {14, 248, 2, 4 },
55f9321a
ID		 4154
4155 /* 802.11 UNI / HyperLan 2 */
4156 {36, 0x56, 0, 4},
4157 {38, 0x56, 0, 6},
4158 {40, 0x56, 0, 8},
4159 {44, 0x57, 0, 0},
4160 {46, 0x57, 0, 2},
4161 {48, 0x57, 0, 4},
4162 {52, 0x57, 0, 8},
4163 {54, 0x57, 0, 10},
4164 {56, 0x58, 0, 0},
4165 {60, 0x58, 0, 4},
4166 {62, 0x58, 0, 6},
4167 {64, 0x58, 0, 8},
4168
4169 /* 802.11 HyperLan 2 */
4170 {100, 0x5b, 0, 8},
4171 {102, 0x5b, 0, 10},
4172 {104, 0x5c, 0, 0},
4173 {108, 0x5c, 0, 4},
4174 {110, 0x5c, 0, 6},
4175 {112, 0x5c, 0, 8},
4176 {116, 0x5d, 0, 0},
4177 {118, 0x5d, 0, 2},
4178 {120, 0x5d, 0, 4},
4179 {124, 0x5d, 0, 8},
4180 {126, 0x5d, 0, 10},
4181 {128, 0x5e, 0, 0},
4182 {132, 0x5e, 0, 4},
4183 {134, 0x5e, 0, 6},
4184 {136, 0x5e, 0, 8},
4185 {140, 0x5f, 0, 0},
4186
4187 /* 802.11 UNII */
4188 {149, 0x5f, 0, 9},
4189 {151, 0x5f, 0, 11},
4190 {153, 0x60, 0, 1},
4191 {157, 0x60, 0, 5},
4192 {159, 0x60, 0, 7},
4193 {161, 0x60, 0, 9},
4194 {165, 0x61, 0, 1},
4195 {167, 0x61, 0, 3},
4196 {169, 0x61, 0, 5},
4197 {171, 0x61, 0, 7},
4198 {173, 0x61, 0, 9},
4da2933f
BZ		 4199};
4200
4201int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4202{
4da2933f
BZ		 4203 struct hw_mode_spec *spec = &rt2x00dev->spec;
4204 struct channel_info *info;
8d1331b3
ID		 4205 char *default_power1;
4206 char *default_power2;
4da2933f
BZ		 4207 unsigned int i;
4208 u16 eeprom;
4209
93b6bd26
GW		 4210 /*
4211 * Disable powersaving as default on PCI devices.
4212 */
cea90e55 4213 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 4214 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4215
4da2933f
BZ		 4216 /*
4217 * Initialize all hw fields.
4218 */
4219 rt2x00dev->hw->flags =
4da2933f
BZ		 4220 IEEE80211_HW_SIGNAL_DBM |
4221 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 4222 IEEE80211_HW_PS_NULLFUNC_STACK |
4223 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 4224 /*
4225 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4226 * unless we are capable of sending the buffered frames out after the
4227 * DTIM transmission using rt2x00lib_beacondone. This will send out
4228 * multicast and broadcast traffic immediately instead of buffering it
4229 * infinitly and thus dropping it after some time.
4230 */
4231 if (!rt2x00_is_usb(rt2x00dev))
4232 rt2x00dev->hw->flags |=
4233 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 4234
4da2933f
BZ		 4235 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4236 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4237 rt2x00_eeprom_addr(rt2x00dev,
4238 EEPROM_MAC_ADDR_0));
4239
3f2bee24
HS		 4240 /*
4241 * As rt2800 has a global fallback table we cannot specify
4242 * more then one tx rate per frame but since the hw will
4243 * try several rates (based on the fallback table) we should
ba3b9e5e 4244 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 4245 * we are going to try. Otherwise mac80211 will truncate our
4246 * reported tx rates and the rc algortihm will end up with
4247 * incorrect data.
4248 */
ba3b9e5e
HS		 4249 rt2x00dev->hw->max_rates = 1;
4250 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 4251 rt2x00dev->hw->max_rate_tries = 1;
4252
38c8a566 4253 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 4254
4255 /*
4256 * Initialize hw_mode information.
4257 */
4258 spec->supported_bands = SUPPORT_BAND_2GHZ;
4259 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4260
5122d898 4261 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 4262 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 4263 spec->num_channels = 14;
4264 spec->channels = rf_vals;
55f9321a
ID		 4265 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4266 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 4267 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4268 spec->num_channels = ARRAY_SIZE(rf_vals);
4269 spec->channels = rf_vals;
5122d898
GW		 4270 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4271 rt2x00_rf(rt2x00dev, RF2020) ||
4272 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4273 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882 4274 rt2x00_rf(rt2x00dev, RF3320) ||
aca355b9 4275 rt2x00_rf(rt2x00dev, RF5370) ||
adde5882 4276 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 4277 spec->num_channels = 14;
4278 spec->channels = rf_vals_3x;
4279 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4280 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4281 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4282 spec->channels = rf_vals_3x;
4da2933f
BZ		 4283 }
4284
4285 /*
4286 * Initialize HT information.
4287 */
5122d898 4288 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4289 spec->ht.ht_supported = true;
4290 else
4291 spec->ht.ht_supported = false;
4292
4da2933f 4293 spec->ht.cap =
06443e46 4294 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4295 IEEE80211_HT_CAP_GRN_FLD |
4296 IEEE80211_HT_CAP_SGI_20 |
aa674631 4297 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4298
38c8a566 4299 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4300 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4301
aa674631 4302 spec->ht.cap |=
38c8a566 4303 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4304 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4305
4da2933f
BZ		 4306 spec->ht.ampdu_factor = 3;
4307 spec->ht.ampdu_density = 4;
4308 spec->ht.mcs.tx_params =
4309 IEEE80211_HT_MCS_TX_DEFINED |
4310 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4311 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4312 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4313
38c8a566 4314 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4315 case 3:
4316 spec->ht.mcs.rx_mask[2] = 0xff;
4317 case 2:
4318 spec->ht.mcs.rx_mask[1] = 0xff;
4319 case 1:
4320 spec->ht.mcs.rx_mask[0] = 0xff;
4321 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4322 break;
4323 }
4324
4325 /*
4326 * Create channel information array
4327 */
baeb2ffa 4328 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4329 if (!info)
4330 return -ENOMEM;
4331
4332 spec->channels_info = info;
4333
8d1331b3
ID		 4334 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4335 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4336
4337 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4338 info[i].default_power1 = default_power1[i];
4339 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4340 }
4341
4342 if (spec->num_channels > 14) {
8d1331b3
ID		 4343 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4344 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4345
4346 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4347 info[i].default_power1 = default_power1[i];
4348 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4349 }
4350 }
4351
4352 return 0;
4353}
4354EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4355
2ce33995
BZ		 4356/*
4357 * IEEE80211 stack callback functions.
4358 */
e783619e
HS		 4359void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4360 u16 *iv16)
2ce33995
BZ		 4361{
4362 struct rt2x00_dev *rt2x00dev = hw->priv;
4363 struct mac_iveiv_entry iveiv_entry;
4364 u32 offset;
4365
4366 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4367 rt2800_register_multiread(rt2x00dev, offset,
4368 &iveiv_entry, sizeof(iveiv_entry));
4369
855da5e0
JL		 4370 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4371 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4372}
e783619e 4373EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4374
e783619e 4375int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4376{
4377 struct rt2x00_dev *rt2x00dev = hw->priv;
4378 u32 reg;
4379 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4380
4381 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4382 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4383 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4384
4385 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4386 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4387 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4388
4389 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4390 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4391 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4392
4393 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4394 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4395 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4396
4397 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4398 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4399 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4400
4401 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4402 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4403 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4404
4405 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4406 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4407 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4408
4409 return 0;
4410}
e783619e 4411EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4412
8a3a3c85
EP		 4413int rt2800_conf_tx(struct ieee80211_hw *hw,
4414 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 4415 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4416{
4417 struct rt2x00_dev *rt2x00dev = hw->priv;
4418 struct data_queue *queue;
4419 struct rt2x00_field32 field;
4420 int retval;
4421 u32 reg;
4422 u32 offset;
4423
4424 /*
4425 * First pass the configuration through rt2x00lib, that will
4426 * update the queue settings and validate the input. After that
4427 * we are free to update the registers based on the value
4428 * in the queue parameter.
4429 */
8a3a3c85 4430 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 4431 if (retval)
4432 return retval;
4433
4434 /*
4435 * We only need to perform additional register initialization
4436 * for WMM queues/
4437 */
4438 if (queue_idx >= 4)
4439 return 0;
4440
11f818e0 4441 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4442
4443 /* Update WMM TXOP register */
4444 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4445 field.bit_offset = (queue_idx & 1) * 16;
4446 field.bit_mask = 0xffff << field.bit_offset;
4447
4448 rt2800_register_read(rt2x00dev, offset, &reg);
4449 rt2x00_set_field32(&reg, field, queue->txop);
4450 rt2800_register_write(rt2x00dev, offset, reg);
4451
4452 /* Update WMM registers */
4453 field.bit_offset = queue_idx * 4;
4454 field.bit_mask = 0xf << field.bit_offset;
4455
4456 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4457 rt2x00_set_field32(&reg, field, queue->aifs);
4458 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4459
4460 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4461 rt2x00_set_field32(&reg, field, queue->cw_min);
4462 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4463
4464 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4465 rt2x00_set_field32(&reg, field, queue->cw_max);
4466 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4467
4468 /* Update EDCA registers */
4469 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4470
4471 rt2800_register_read(rt2x00dev, offset, &reg);
4472 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4473 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4474 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4475 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4476 rt2800_register_write(rt2x00dev, offset, reg);
4477
4478 return 0;
4479}
e783619e 4480EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4481
37a41b4a 4482u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 4483{
4484 struct rt2x00_dev *rt2x00dev = hw->priv;
4485 u64 tsf;
4486 u32 reg;
4487
4488 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4489 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4490 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4491 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4492
4493 return tsf;
4494}
e783619e 4495EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4496
e783619e
HS		 4497int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4498 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4499 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4500 u8 buf_size)
1df90809 4501{
af35323d 4502 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 4503 int ret = 0;
4504
af35323d
HS		 4505 /*
4506 * Don't allow aggregation for stations the hardware isn't aware
4507 * of because tx status reports for frames to an unknown station
4508 * always contain wcid=255 and thus we can't distinguish between
4509 * multiple stations which leads to unwanted situations when the
4510 * hw reorders frames due to aggregation.
4511 */
4512 if (sta_priv->wcid < 0)
4513 return 1;
4514
1df90809
HS		 4515 switch (action) {
4516 case IEEE80211_AMPDU_RX_START:
4517 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4518 /*
4519 * The hw itself takes care of setting up BlockAck mechanisms.
4520 * So, we only have to allow mac80211 to nagotiate a BlockAck
4521 * agreement. Once that is done, the hw will BlockAck incoming
4522 * AMPDUs without further setup.
4523 */
1df90809
HS		 4524 break;
4525 case IEEE80211_AMPDU_TX_START:
4526 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4527 break;
4528 case IEEE80211_AMPDU_TX_STOP:
4529 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4530 break;
4531 case IEEE80211_AMPDU_TX_OPERATIONAL:
4532 break;
4533 default:
4e9e58c6 4534 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4535 }
4536
4537 return ret;
4538}
e783619e 4539EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4540
977206d7
HS		 4541int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4542 struct survey_info *survey)
4543{
4544 struct rt2x00_dev *rt2x00dev = hw->priv;
4545 struct ieee80211_conf *conf = &hw->conf;
4546 u32 idle, busy, busy_ext;
4547
4548 if (idx != 0)
4549 return -ENOENT;
4550
4551 survey->channel = conf->channel;
4552
4553 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4554 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4555 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4556
4557 if (idle || busy) {
4558 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4559 SURVEY_INFO_CHANNEL_TIME_BUSY |
4560 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4561
4562 survey->channel_time = (idle + busy) / 1000;
4563 survey->channel_time_busy = busy / 1000;
4564 survey->channel_time_ext_busy = busy_ext / 1000;
4565 }
4566
9931df26
HS		 4567 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4568 survey->filled |= SURVEY_INFO_IN_USE;
4569
977206d7
HS		 4570 return 0;
4571
4572}
4573EXPORT_SYMBOL_GPL(rt2800_get_survey);
4574
a5ea2f02
ID		 4575MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4576MODULE_VERSION(DRV_VERSION);
4577MODULE_DESCRIPTION("Ralink RT2800 library");
4578MODULE_LICENSE("GPL");
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