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89297425 | 1 | /* |
96481b20 | 2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
a5ea2f02 | 3 | Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> |
9c9a0d14 | 4 | Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> |
cce5fc45 | 5 | Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
89297425 | 6 | |
9c9a0d14 | 7 | Based on the original rt2800pci.c and rt2800usb.c. |
9c9a0d14 GW |
8 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
9 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
10 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
11 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
12 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
13 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
89297425 BZ |
14 | <http://rt2x00.serialmonkey.com> |
15 | ||
16 | This program is free software; you can redistribute it and/or modify | |
17 | it under the terms of the GNU General Public License as published by | |
18 | the Free Software Foundation; either version 2 of the License, or | |
19 | (at your option) any later version. | |
20 | ||
21 | This program is distributed in the hope that it will be useful, | |
22 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | GNU General Public License for more details. | |
25 | ||
26 | You should have received a copy of the GNU General Public License | |
27 | along with this program; if not, write to the | |
28 | Free Software Foundation, Inc., | |
29 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
32 | /* | |
33 | Module: rt2800lib | |
34 | Abstract: rt2800 generic device routines. | |
35 | */ | |
36 | ||
f31c9a8c | 37 | #include <linux/crc-ccitt.h> |
89297425 BZ |
38 | #include <linux/kernel.h> |
39 | #include <linux/module.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
89297425 BZ |
41 | |
42 | #include "rt2x00.h" | |
43 | #include "rt2800lib.h" | |
44 | #include "rt2800.h" | |
45 | ||
89297425 BZ |
46 | /* |
47 | * Register access. | |
48 | * All access to the CSR registers will go through the methods | |
49 | * rt2800_register_read and rt2800_register_write. | |
50 | * BBP and RF register require indirect register access, | |
51 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
52 | * These indirect registers work with busy bits, | |
53 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
54 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
55 | * between each attampt. When the busy bit is still set at that time, | |
56 | * the access attempt is considered to have failed, | |
57 | * and we will print an error. | |
58 | * The _lock versions must be used if you already hold the csr_mutex | |
59 | */ | |
60 | #define WAIT_FOR_BBP(__dev, __reg) \ | |
61 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) | |
62 | #define WAIT_FOR_RFCSR(__dev, __reg) \ | |
63 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) | |
64 | #define WAIT_FOR_RF(__dev, __reg) \ | |
65 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) | |
66 | #define WAIT_FOR_MCU(__dev, __reg) \ | |
67 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ | |
68 | H2M_MAILBOX_CSR_OWNER, (__reg)) | |
69 | ||
baff8006 HS |
70 | static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) |
71 | { | |
72 | /* check for rt2872 on SoC */ | |
73 | if (!rt2x00_is_soc(rt2x00dev) || | |
74 | !rt2x00_rt(rt2x00dev, RT2872)) | |
75 | return false; | |
76 | ||
77 | /* we know for sure that these rf chipsets are used on rt305x boards */ | |
78 | if (rt2x00_rf(rt2x00dev, RF3020) || | |
79 | rt2x00_rf(rt2x00dev, RF3021) || | |
80 | rt2x00_rf(rt2x00dev, RF3022)) | |
81 | return true; | |
82 | ||
ec9c4989 | 83 | rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); |
baff8006 HS |
84 | return false; |
85 | } | |
86 | ||
fcf51541 BZ |
87 | static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
88 | const unsigned int word, const u8 value) | |
89297425 BZ |
89 | { |
90 | u32 reg; | |
91 | ||
92 | mutex_lock(&rt2x00dev->csr_mutex); | |
93 | ||
94 | /* | |
95 | * Wait until the BBP becomes available, afterwards we | |
96 | * can safely write the new data into the register. | |
97 | */ | |
98 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
99 | reg = 0; | |
100 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); | |
101 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
102 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
103 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); | |
efc7d36f | 104 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
105 | |
106 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
107 | } | |
108 | ||
109 | mutex_unlock(&rt2x00dev->csr_mutex); | |
110 | } | |
89297425 | 111 | |
fcf51541 BZ |
112 | static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
113 | const unsigned int word, u8 *value) | |
89297425 BZ |
114 | { |
115 | u32 reg; | |
116 | ||
117 | mutex_lock(&rt2x00dev->csr_mutex); | |
118 | ||
119 | /* | |
120 | * Wait until the BBP becomes available, afterwards we | |
121 | * can safely write the read request into the register. | |
122 | * After the data has been written, we wait until hardware | |
123 | * returns the correct value, if at any time the register | |
124 | * doesn't become available in time, reg will be 0xffffffff | |
125 | * which means we return 0xff to the caller. | |
126 | */ | |
127 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
128 | reg = 0; | |
129 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
130 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
131 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); | |
efc7d36f | 132 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
133 | |
134 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
135 | ||
136 | WAIT_FOR_BBP(rt2x00dev, ®); | |
137 | } | |
138 | ||
139 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); | |
140 | ||
141 | mutex_unlock(&rt2x00dev->csr_mutex); | |
142 | } | |
89297425 | 143 | |
fcf51541 BZ |
144 | static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
145 | const unsigned int word, const u8 value) | |
89297425 BZ |
146 | { |
147 | u32 reg; | |
148 | ||
149 | mutex_lock(&rt2x00dev->csr_mutex); | |
150 | ||
151 | /* | |
152 | * Wait until the RFCSR becomes available, afterwards we | |
153 | * can safely write the new data into the register. | |
154 | */ | |
155 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
156 | reg = 0; | |
157 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); | |
158 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
159 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); | |
160 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
161 | ||
162 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
163 | } | |
164 | ||
165 | mutex_unlock(&rt2x00dev->csr_mutex); | |
166 | } | |
89297425 | 167 | |
fcf51541 BZ |
168 | static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
169 | const unsigned int word, u8 *value) | |
89297425 BZ |
170 | { |
171 | u32 reg; | |
172 | ||
173 | mutex_lock(&rt2x00dev->csr_mutex); | |
174 | ||
175 | /* | |
176 | * Wait until the RFCSR becomes available, afterwards we | |
177 | * can safely write the read request into the register. | |
178 | * After the data has been written, we wait until hardware | |
179 | * returns the correct value, if at any time the register | |
180 | * doesn't become available in time, reg will be 0xffffffff | |
181 | * which means we return 0xff to the caller. | |
182 | */ | |
183 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
184 | reg = 0; | |
185 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
186 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); | |
187 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
188 | ||
189 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
190 | ||
191 | WAIT_FOR_RFCSR(rt2x00dev, ®); | |
192 | } | |
193 | ||
194 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); | |
195 | ||
196 | mutex_unlock(&rt2x00dev->csr_mutex); | |
197 | } | |
89297425 | 198 | |
fcf51541 BZ |
199 | static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
200 | const unsigned int word, const u32 value) | |
89297425 BZ |
201 | { |
202 | u32 reg; | |
203 | ||
204 | mutex_lock(&rt2x00dev->csr_mutex); | |
205 | ||
206 | /* | |
207 | * Wait until the RF becomes available, afterwards we | |
208 | * can safely write the new data into the register. | |
209 | */ | |
210 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
211 | reg = 0; | |
212 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); | |
213 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); | |
214 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); | |
215 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); | |
216 | ||
217 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); | |
218 | rt2x00_rf_write(rt2x00dev, word, value); | |
219 | } | |
220 | ||
221 | mutex_unlock(&rt2x00dev->csr_mutex); | |
222 | } | |
89297425 | 223 | |
379448fe GJ |
224 | static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { |
225 | [EEPROM_CHIP_ID] = 0x0000, | |
226 | [EEPROM_VERSION] = 0x0001, | |
227 | [EEPROM_MAC_ADDR_0] = 0x0002, | |
228 | [EEPROM_MAC_ADDR_1] = 0x0003, | |
229 | [EEPROM_MAC_ADDR_2] = 0x0004, | |
230 | [EEPROM_NIC_CONF0] = 0x001a, | |
231 | [EEPROM_NIC_CONF1] = 0x001b, | |
232 | [EEPROM_FREQ] = 0x001d, | |
233 | [EEPROM_LED_AG_CONF] = 0x001e, | |
234 | [EEPROM_LED_ACT_CONF] = 0x001f, | |
235 | [EEPROM_LED_POLARITY] = 0x0020, | |
236 | [EEPROM_NIC_CONF2] = 0x0021, | |
237 | [EEPROM_LNA] = 0x0022, | |
238 | [EEPROM_RSSI_BG] = 0x0023, | |
239 | [EEPROM_RSSI_BG2] = 0x0024, | |
240 | [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ | |
241 | [EEPROM_RSSI_A] = 0x0025, | |
242 | [EEPROM_RSSI_A2] = 0x0026, | |
243 | [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ | |
244 | [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, | |
245 | [EEPROM_TXPOWER_DELTA] = 0x0028, | |
246 | [EEPROM_TXPOWER_BG1] = 0x0029, | |
247 | [EEPROM_TXPOWER_BG2] = 0x0030, | |
248 | [EEPROM_TSSI_BOUND_BG1] = 0x0037, | |
249 | [EEPROM_TSSI_BOUND_BG2] = 0x0038, | |
250 | [EEPROM_TSSI_BOUND_BG3] = 0x0039, | |
251 | [EEPROM_TSSI_BOUND_BG4] = 0x003a, | |
252 | [EEPROM_TSSI_BOUND_BG5] = 0x003b, | |
253 | [EEPROM_TXPOWER_A1] = 0x003c, | |
254 | [EEPROM_TXPOWER_A2] = 0x0053, | |
255 | [EEPROM_TSSI_BOUND_A1] = 0x006a, | |
256 | [EEPROM_TSSI_BOUND_A2] = 0x006b, | |
257 | [EEPROM_TSSI_BOUND_A3] = 0x006c, | |
258 | [EEPROM_TSSI_BOUND_A4] = 0x006d, | |
259 | [EEPROM_TSSI_BOUND_A5] = 0x006e, | |
260 | [EEPROM_TXPOWER_BYRATE] = 0x006f, | |
261 | [EEPROM_BBP_START] = 0x0078, | |
262 | }; | |
263 | ||
fa31d157 GJ |
264 | static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { |
265 | [EEPROM_CHIP_ID] = 0x0000, | |
266 | [EEPROM_VERSION] = 0x0001, | |
267 | [EEPROM_MAC_ADDR_0] = 0x0002, | |
268 | [EEPROM_MAC_ADDR_1] = 0x0003, | |
269 | [EEPROM_MAC_ADDR_2] = 0x0004, | |
270 | [EEPROM_NIC_CONF0] = 0x001a, | |
271 | [EEPROM_NIC_CONF1] = 0x001b, | |
272 | [EEPROM_NIC_CONF2] = 0x001c, | |
273 | [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, | |
274 | [EEPROM_FREQ] = 0x0022, | |
275 | [EEPROM_LED_AG_CONF] = 0x0023, | |
276 | [EEPROM_LED_ACT_CONF] = 0x0024, | |
277 | [EEPROM_LED_POLARITY] = 0x0025, | |
278 | [EEPROM_LNA] = 0x0026, | |
279 | [EEPROM_EXT_LNA2] = 0x0027, | |
280 | [EEPROM_RSSI_BG] = 0x0028, | |
281 | [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */ | |
282 | [EEPROM_RSSI_BG2] = 0x0029, | |
283 | [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */ | |
284 | [EEPROM_RSSI_A] = 0x002a, | |
285 | [EEPROM_RSSI_A2] = 0x002b, | |
286 | [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */ | |
287 | [EEPROM_TXPOWER_BG1] = 0x0030, | |
288 | [EEPROM_TXPOWER_BG2] = 0x0037, | |
289 | [EEPROM_EXT_TXPOWER_BG3] = 0x003e, | |
290 | [EEPROM_TSSI_BOUND_BG1] = 0x0045, | |
291 | [EEPROM_TSSI_BOUND_BG2] = 0x0046, | |
292 | [EEPROM_TSSI_BOUND_BG3] = 0x0047, | |
293 | [EEPROM_TSSI_BOUND_BG4] = 0x0048, | |
294 | [EEPROM_TSSI_BOUND_BG5] = 0x0049, | |
295 | [EEPROM_TXPOWER_A1] = 0x004b, | |
296 | [EEPROM_TXPOWER_A2] = 0x0065, | |
297 | [EEPROM_EXT_TXPOWER_A3] = 0x007f, | |
298 | [EEPROM_TSSI_BOUND_A1] = 0x009a, | |
299 | [EEPROM_TSSI_BOUND_A2] = 0x009b, | |
300 | [EEPROM_TSSI_BOUND_A3] = 0x009c, | |
301 | [EEPROM_TSSI_BOUND_A4] = 0x009d, | |
302 | [EEPROM_TSSI_BOUND_A5] = 0x009e, | |
303 | [EEPROM_TXPOWER_BYRATE] = 0x00a0, | |
304 | }; | |
305 | ||
379448fe GJ |
306 | static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, |
307 | const enum rt2800_eeprom_word word) | |
308 | { | |
309 | const unsigned int *map; | |
310 | unsigned int index; | |
311 | ||
312 | if (WARN_ONCE(word >= EEPROM_WORD_COUNT, | |
313 | "%s: invalid EEPROM word %d\n", | |
314 | wiphy_name(rt2x00dev->hw->wiphy), word)) | |
315 | return 0; | |
316 | ||
fa31d157 GJ |
317 | if (rt2x00_rt(rt2x00dev, RT3593)) |
318 | map = rt2800_eeprom_map_ext; | |
319 | else | |
320 | map = rt2800_eeprom_map; | |
321 | ||
379448fe GJ |
322 | index = map[word]; |
323 | ||
324 | /* Index 0 is valid only for EEPROM_CHIP_ID. | |
325 | * Otherwise it means that the offset of the | |
326 | * given word is not initialized in the map, | |
327 | * or that the field is not usable on the | |
328 | * actual chipset. | |
329 | */ | |
330 | WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, | |
331 | "%s: invalid access of EEPROM word %d\n", | |
332 | wiphy_name(rt2x00dev->hw->wiphy), word); | |
333 | ||
334 | return index; | |
335 | } | |
336 | ||
3e38d3da GJ |
337 | static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, |
338 | const enum rt2800_eeprom_word word) | |
339 | { | |
379448fe GJ |
340 | unsigned int index; |
341 | ||
342 | index = rt2800_eeprom_word_index(rt2x00dev, word); | |
343 | return rt2x00_eeprom_addr(rt2x00dev, index); | |
3e38d3da GJ |
344 | } |
345 | ||
346 | static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, | |
347 | const enum rt2800_eeprom_word word, u16 *data) | |
348 | { | |
379448fe GJ |
349 | unsigned int index; |
350 | ||
351 | index = rt2800_eeprom_word_index(rt2x00dev, word); | |
352 | rt2x00_eeprom_read(rt2x00dev, index, data); | |
3e38d3da GJ |
353 | } |
354 | ||
355 | static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, | |
356 | const enum rt2800_eeprom_word word, u16 data) | |
357 | { | |
379448fe GJ |
358 | unsigned int index; |
359 | ||
360 | index = rt2800_eeprom_word_index(rt2x00dev, word); | |
361 | rt2x00_eeprom_write(rt2x00dev, index, data); | |
3e38d3da GJ |
362 | } |
363 | ||
022138ca GJ |
364 | static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, |
365 | const enum rt2800_eeprom_word array, | |
366 | unsigned int offset, | |
367 | u16 *data) | |
368 | { | |
379448fe GJ |
369 | unsigned int index; |
370 | ||
371 | index = rt2800_eeprom_word_index(rt2x00dev, array); | |
372 | rt2x00_eeprom_read(rt2x00dev, index + offset, data); | |
022138ca GJ |
373 | } |
374 | ||
16ebd608 WH |
375 | static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) |
376 | { | |
377 | u32 reg; | |
378 | int i, count; | |
379 | ||
380 | rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); | |
381 | if (rt2x00_get_field32(reg, WLAN_EN)) | |
382 | return 0; | |
383 | ||
384 | rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); | |
385 | rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); | |
386 | rt2x00_set_field32(®, WLAN_CLK_EN, 0); | |
387 | rt2x00_set_field32(®, WLAN_EN, 1); | |
388 | rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); | |
389 | ||
390 | udelay(REGISTER_BUSY_DELAY); | |
391 | ||
392 | count = 0; | |
393 | do { | |
394 | /* | |
395 | * Check PLL_LD & XTAL_RDY. | |
396 | */ | |
397 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
398 | rt2800_register_read(rt2x00dev, CMB_CTRL, ®); | |
399 | if (rt2x00_get_field32(reg, PLL_LD) && | |
400 | rt2x00_get_field32(reg, XTAL_RDY)) | |
401 | break; | |
402 | udelay(REGISTER_BUSY_DELAY); | |
403 | } | |
404 | ||
405 | if (i >= REGISTER_BUSY_COUNT) { | |
406 | ||
407 | if (count >= 10) | |
408 | return -EIO; | |
409 | ||
410 | rt2800_register_write(rt2x00dev, 0x58, 0x018); | |
411 | udelay(REGISTER_BUSY_DELAY); | |
412 | rt2800_register_write(rt2x00dev, 0x58, 0x418); | |
413 | udelay(REGISTER_BUSY_DELAY); | |
414 | rt2800_register_write(rt2x00dev, 0x58, 0x618); | |
415 | udelay(REGISTER_BUSY_DELAY); | |
416 | count++; | |
417 | } else { | |
418 | count = 0; | |
419 | } | |
420 | ||
421 | rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); | |
422 | rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); | |
423 | rt2x00_set_field32(®, WLAN_CLK_EN, 1); | |
424 | rt2x00_set_field32(®, WLAN_RESET, 1); | |
425 | rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); | |
426 | udelay(10); | |
427 | rt2x00_set_field32(®, WLAN_RESET, 0); | |
428 | rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); | |
429 | udelay(10); | |
430 | rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); | |
431 | } while (count != 0); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
89297425 BZ |
436 | void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, |
437 | const u8 command, const u8 token, | |
438 | const u8 arg0, const u8 arg1) | |
439 | { | |
440 | u32 reg; | |
441 | ||
ee303e54 | 442 | /* |
cea90e55 | 443 | * SOC devices don't support MCU requests. |
ee303e54 | 444 | */ |
cea90e55 | 445 | if (rt2x00_is_soc(rt2x00dev)) |
ee303e54 | 446 | return; |
89297425 BZ |
447 | |
448 | mutex_lock(&rt2x00dev->csr_mutex); | |
449 | ||
450 | /* | |
451 | * Wait until the MCU becomes available, afterwards we | |
452 | * can safely write the new data into the register. | |
453 | */ | |
454 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { | |
455 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
456 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
457 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
458 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
459 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); | |
460 | ||
461 | reg = 0; | |
462 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); | |
463 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); | |
464 | } | |
465 | ||
466 | mutex_unlock(&rt2x00dev->csr_mutex); | |
467 | } | |
468 | EXPORT_SYMBOL_GPL(rt2800_mcu_request); | |
f4450616 | 469 | |
5ffddc49 ID |
470 | int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) |
471 | { | |
472 | unsigned int i = 0; | |
473 | u32 reg; | |
474 | ||
475 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
476 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
477 | if (reg && reg != ~0) | |
478 | return 0; | |
479 | msleep(1); | |
480 | } | |
481 | ||
ec9c4989 | 482 | rt2x00_err(rt2x00dev, "Unstable hardware\n"); |
5ffddc49 ID |
483 | return -EBUSY; |
484 | } | |
485 | EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); | |
486 | ||
67a4c1e2 GW |
487 | int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) |
488 | { | |
489 | unsigned int i; | |
490 | u32 reg; | |
491 | ||
08e53100 HS |
492 | /* |
493 | * Some devices are really slow to respond here. Wait a whole second | |
494 | * before timing out. | |
495 | */ | |
67a4c1e2 GW |
496 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
497 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
498 | if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && | |
499 | !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) | |
500 | return 0; | |
501 | ||
08e53100 | 502 | msleep(10); |
67a4c1e2 GW |
503 | } |
504 | ||
ec9c4989 | 505 | rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); |
67a4c1e2 GW |
506 | return -EACCES; |
507 | } | |
508 | EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); | |
509 | ||
f7b395e9 JK |
510 | void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) |
511 | { | |
512 | u32 reg; | |
513 | ||
514 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
515 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
516 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
517 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
518 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
519 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
520 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
521 | } | |
522 | EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); | |
523 | ||
f31c9a8c ID |
524 | static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) |
525 | { | |
526 | u16 fw_crc; | |
527 | u16 crc; | |
528 | ||
529 | /* | |
530 | * The last 2 bytes in the firmware array are the crc checksum itself, | |
531 | * this means that we should never pass those 2 bytes to the crc | |
532 | * algorithm. | |
533 | */ | |
534 | fw_crc = (data[len - 2] << 8 | data[len - 1]); | |
535 | ||
536 | /* | |
537 | * Use the crc ccitt algorithm. | |
538 | * This will return the same value as the legacy driver which | |
539 | * used bit ordering reversion on the both the firmware bytes | |
540 | * before input input as well as on the final output. | |
541 | * Obviously using crc ccitt directly is much more efficient. | |
542 | */ | |
543 | crc = crc_ccitt(~0, data, len - 2); | |
544 | ||
545 | /* | |
546 | * There is a small difference between the crc-itu-t + bitrev and | |
547 | * the crc-ccitt crc calculation. In the latter method the 2 bytes | |
548 | * will be swapped, use swab16 to convert the crc to the correct | |
549 | * value. | |
550 | */ | |
551 | crc = swab16(crc); | |
552 | ||
553 | return fw_crc == crc; | |
554 | } | |
555 | ||
556 | int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, | |
557 | const u8 *data, const size_t len) | |
558 | { | |
559 | size_t offset = 0; | |
560 | size_t fw_len; | |
561 | bool multiple; | |
562 | ||
563 | /* | |
564 | * PCI(e) & SOC devices require firmware with a length | |
565 | * of 8kb. USB devices require firmware files with a length | |
566 | * of 4kb. Certain USB chipsets however require different firmware, | |
567 | * which Ralink only provides attached to the original firmware | |
568 | * file. Thus for USB devices, firmware files have a length | |
a89534ed WH |
569 | * which is a multiple of 4kb. The firmware for rt3290 chip also |
570 | * have a length which is a multiple of 4kb. | |
f31c9a8c | 571 | */ |
a89534ed | 572 | if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) |
f31c9a8c | 573 | fw_len = 4096; |
a89534ed | 574 | else |
f31c9a8c | 575 | fw_len = 8192; |
f31c9a8c | 576 | |
a89534ed | 577 | multiple = true; |
f31c9a8c ID |
578 | /* |
579 | * Validate the firmware length | |
580 | */ | |
581 | if (len != fw_len && (!multiple || (len % fw_len) != 0)) | |
582 | return FW_BAD_LENGTH; | |
583 | ||
584 | /* | |
585 | * Check if the chipset requires one of the upper parts | |
586 | * of the firmware. | |
587 | */ | |
588 | if (rt2x00_is_usb(rt2x00dev) && | |
589 | !rt2x00_rt(rt2x00dev, RT2860) && | |
590 | !rt2x00_rt(rt2x00dev, RT2872) && | |
591 | !rt2x00_rt(rt2x00dev, RT3070) && | |
592 | ((len / fw_len) == 1)) | |
593 | return FW_BAD_VERSION; | |
594 | ||
595 | /* | |
596 | * 8kb firmware files must be checked as if it were | |
597 | * 2 separate firmware files. | |
598 | */ | |
599 | while (offset < len) { | |
600 | if (!rt2800_check_firmware_crc(data + offset, fw_len)) | |
601 | return FW_BAD_CRC; | |
602 | ||
603 | offset += fw_len; | |
604 | } | |
605 | ||
606 | return FW_OK; | |
607 | } | |
608 | EXPORT_SYMBOL_GPL(rt2800_check_firmware); | |
609 | ||
610 | int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, | |
611 | const u8 *data, const size_t len) | |
612 | { | |
613 | unsigned int i; | |
614 | u32 reg; | |
16ebd608 WH |
615 | int retval; |
616 | ||
617 | if (rt2x00_rt(rt2x00dev, RT3290)) { | |
618 | retval = rt2800_enable_wlan_rt3290(rt2x00dev); | |
619 | if (retval) | |
620 | return -EBUSY; | |
621 | } | |
f31c9a8c ID |
622 | |
623 | /* | |
b9eca242 ID |
624 | * If driver doesn't wake up firmware here, |
625 | * rt2800_load_firmware will hang forever when interface is up again. | |
f31c9a8c | 626 | */ |
b9eca242 | 627 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); |
f31c9a8c | 628 | |
f31c9a8c ID |
629 | /* |
630 | * Wait for stable hardware. | |
631 | */ | |
5ffddc49 | 632 | if (rt2800_wait_csr_ready(rt2x00dev)) |
f31c9a8c | 633 | return -EBUSY; |
f31c9a8c | 634 | |
adde5882 | 635 | if (rt2x00_is_pci(rt2x00dev)) { |
a89534ed WH |
636 | if (rt2x00_rt(rt2x00dev, RT3290) || |
637 | rt2x00_rt(rt2x00dev, RT3572) || | |
2ed71884 JL |
638 | rt2x00_rt(rt2x00dev, RT5390) || |
639 | rt2x00_rt(rt2x00dev, RT5392)) { | |
adde5882 GJ |
640 | rt2800_register_read(rt2x00dev, AUX_CTRL, ®); |
641 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); | |
642 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); | |
643 | rt2800_register_write(rt2x00dev, AUX_CTRL, reg); | |
644 | } | |
f31c9a8c | 645 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); |
adde5882 | 646 | } |
f31c9a8c | 647 | |
b7e1d225 JK |
648 | rt2800_disable_wpdma(rt2x00dev); |
649 | ||
f31c9a8c ID |
650 | /* |
651 | * Write firmware to the device. | |
652 | */ | |
653 | rt2800_drv_write_firmware(rt2x00dev, data, len); | |
654 | ||
655 | /* | |
656 | * Wait for device to stabilize. | |
657 | */ | |
658 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
659 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); | |
660 | if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) | |
661 | break; | |
662 | msleep(1); | |
663 | } | |
664 | ||
665 | if (i == REGISTER_BUSY_COUNT) { | |
ec9c4989 | 666 | rt2x00_err(rt2x00dev, "PBF system register not ready\n"); |
f31c9a8c ID |
667 | return -EBUSY; |
668 | } | |
669 | ||
4ed1dd2a SG |
670 | /* |
671 | * Disable DMA, will be reenabled later when enabling | |
672 | * the radio. | |
673 | */ | |
f7b395e9 | 674 | rt2800_disable_wpdma(rt2x00dev); |
4ed1dd2a | 675 | |
f31c9a8c ID |
676 | /* |
677 | * Initialize firmware. | |
678 | */ | |
679 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
680 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
8756130b | 681 | if (rt2x00_is_usb(rt2x00dev)) { |
0c17cf96 | 682 | rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); |
8756130b SG |
683 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); |
684 | } | |
f31c9a8c ID |
685 | msleep(1); |
686 | ||
687 | return 0; | |
688 | } | |
689 | EXPORT_SYMBOL_GPL(rt2800_load_firmware); | |
690 | ||
0c5879bc ID |
691 | void rt2800_write_tx_data(struct queue_entry *entry, |
692 | struct txentry_desc *txdesc) | |
59679b91 | 693 | { |
0c5879bc | 694 | __le32 *txwi = rt2800_drv_get_txwi(entry); |
59679b91 | 695 | u32 word; |
557985ae | 696 | int i; |
59679b91 GW |
697 | |
698 | /* | |
699 | * Initialize TX Info descriptor | |
700 | */ | |
701 | rt2x00_desc_read(txwi, 0, &word); | |
702 | rt2x00_set_field32(&word, TXWI_W0_FRAG, | |
703 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
84804cdc ID |
704 | rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, |
705 | test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); | |
59679b91 GW |
706 | rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); |
707 | rt2x00_set_field32(&word, TXWI_W0_TS, | |
708 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
709 | rt2x00_set_field32(&word, TXWI_W0_AMPDU, | |
710 | test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); | |
26a1d07f HS |
711 | rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, |
712 | txdesc->u.ht.mpdu_density); | |
713 | rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); | |
714 | rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); | |
59679b91 GW |
715 | rt2x00_set_field32(&word, TXWI_W0_BW, |
716 | test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); | |
717 | rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, | |
718 | test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); | |
26a1d07f | 719 | rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); |
59679b91 GW |
720 | rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); |
721 | rt2x00_desc_write(txwi, 0, word); | |
722 | ||
723 | rt2x00_desc_read(txwi, 1, &word); | |
724 | rt2x00_set_field32(&word, TXWI_W1_ACK, | |
725 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
726 | rt2x00_set_field32(&word, TXWI_W1_NSEQ, | |
727 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
26a1d07f | 728 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); |
59679b91 GW |
729 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, |
730 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? | |
a2b1328a | 731 | txdesc->key_idx : txdesc->u.ht.wcid); |
59679b91 GW |
732 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, |
733 | txdesc->length); | |
2b23cdaa | 734 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); |
bc8a979e | 735 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); |
59679b91 GW |
736 | rt2x00_desc_write(txwi, 1, word); |
737 | ||
738 | /* | |
557985ae SG |
739 | * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert |
740 | * the IV from the IVEIV register when TXD_W3_WIV is set to 0. | |
59679b91 GW |
741 | * When TXD_W3_WIV is set to 1 it will use the IV data |
742 | * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which | |
743 | * crypto entry in the registers should be used to encrypt the frame. | |
557985ae SG |
744 | * |
745 | * Nulify all remaining words as well, we don't know how to program them. | |
59679b91 | 746 | */ |
557985ae SG |
747 | for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) |
748 | _rt2x00_desc_write(txwi, i, 0); | |
59679b91 | 749 | } |
0c5879bc | 750 | EXPORT_SYMBOL_GPL(rt2800_write_tx_data); |
59679b91 | 751 | |
ff6133be | 752 | static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) |
2de64dd2 | 753 | { |
7fc41755 LT |
754 | s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); |
755 | s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); | |
756 | s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); | |
74861922 ID |
757 | u16 eeprom; |
758 | u8 offset0; | |
759 | u8 offset1; | |
760 | u8 offset2; | |
761 | ||
e5ef5bad | 762 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { |
3e38d3da | 763 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); |
74861922 ID |
764 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); |
765 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); | |
3e38d3da | 766 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); |
74861922 ID |
767 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); |
768 | } else { | |
3e38d3da | 769 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); |
74861922 ID |
770 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); |
771 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); | |
3e38d3da | 772 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); |
74861922 ID |
773 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); |
774 | } | |
775 | ||
776 | /* | |
777 | * Convert the value from the descriptor into the RSSI value | |
778 | * If the value in the descriptor is 0, it is considered invalid | |
779 | * and the default (extremely low) rssi value is assumed | |
780 | */ | |
781 | rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; | |
782 | rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; | |
783 | rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; | |
784 | ||
785 | /* | |
786 | * mac80211 only accepts a single RSSI value. Calculating the | |
787 | * average doesn't deliver a fair answer either since -60:-60 would | |
788 | * be considered equally good as -50:-70 while the second is the one | |
789 | * which gives less energy... | |
790 | */ | |
791 | rssi0 = max(rssi0, rssi1); | |
7fc41755 | 792 | return (int)max(rssi0, rssi2); |
74861922 ID |
793 | } |
794 | ||
795 | void rt2800_process_rxwi(struct queue_entry *entry, | |
796 | struct rxdone_entry_desc *rxdesc) | |
797 | { | |
798 | __le32 *rxwi = (__le32 *) entry->skb->data; | |
2de64dd2 GW |
799 | u32 word; |
800 | ||
801 | rt2x00_desc_read(rxwi, 0, &word); | |
802 | ||
803 | rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); | |
804 | rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); | |
805 | ||
806 | rt2x00_desc_read(rxwi, 1, &word); | |
807 | ||
808 | if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) | |
809 | rxdesc->flags |= RX_FLAG_SHORT_GI; | |
810 | ||
811 | if (rt2x00_get_field32(word, RXWI_W1_BW)) | |
812 | rxdesc->flags |= RX_FLAG_40MHZ; | |
813 | ||
814 | /* | |
815 | * Detect RX rate, always use MCS as signal type. | |
816 | */ | |
817 | rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; | |
818 | rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); | |
819 | rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); | |
820 | ||
821 | /* | |
822 | * Mask of 0x8 bit to remove the short preamble flag. | |
823 | */ | |
824 | if (rxdesc->rate_mode == RATE_MODE_CCK) | |
825 | rxdesc->signal &= ~0x8; | |
826 | ||
827 | rt2x00_desc_read(rxwi, 2, &word); | |
828 | ||
74861922 ID |
829 | /* |
830 | * Convert descriptor AGC value to RSSI value. | |
831 | */ | |
832 | rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); | |
f0bda571 SG |
833 | /* |
834 | * Remove RXWI descriptor from start of the buffer. | |
835 | */ | |
836 | skb_pull(entry->skb, entry->queue->winfo_size); | |
2de64dd2 GW |
837 | } |
838 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); | |
839 | ||
31937c42 | 840 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) |
14433331 HS |
841 | { |
842 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
b34793ee | 843 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
14433331 HS |
844 | struct txdone_entry_desc txdesc; |
845 | u32 word; | |
846 | u16 mcs, real_mcs; | |
b34793ee | 847 | int aggr, ampdu; |
14433331 HS |
848 | |
849 | /* | |
850 | * Obtain the status about this packet. | |
851 | */ | |
852 | txdesc.flags = 0; | |
14433331 | 853 | rt2x00_desc_read(txwi, 0, &word); |
b34793ee | 854 | |
14433331 | 855 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); |
b34793ee HS |
856 | ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); |
857 | ||
14433331 | 858 | real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); |
b34793ee HS |
859 | aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); |
860 | ||
861 | /* | |
862 | * If a frame was meant to be sent as a single non-aggregated MPDU | |
863 | * but ended up in an aggregate the used tx rate doesn't correlate | |
864 | * with the one specified in the TXWI as the whole aggregate is sent | |
865 | * with the same rate. | |
866 | * | |
867 | * For example: two frames are sent to rt2x00, the first one sets | |
868 | * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 | |
869 | * and requests MCS15. If the hw aggregates both frames into one | |
870 | * AMDPU the tx status for both frames will contain MCS7 although | |
871 | * the frame was sent successfully. | |
872 | * | |
873 | * Hence, replace the requested rate with the real tx rate to not | |
874 | * confuse the rate control algortihm by providing clearly wrong | |
875 | * data. | |
876 | */ | |
5356d963 | 877 | if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { |
b34793ee HS |
878 | skbdesc->tx_rate_idx = real_mcs; |
879 | mcs = real_mcs; | |
880 | } | |
14433331 | 881 | |
f16d2db7 HS |
882 | if (aggr == 1 || ampdu == 1) |
883 | __set_bit(TXDONE_AMPDU, &txdesc.flags); | |
884 | ||
14433331 HS |
885 | /* |
886 | * Ralink has a retry mechanism using a global fallback | |
887 | * table. We setup this fallback table to try the immediate | |
888 | * lower rate for all rates. In the TX_STA_FIFO, the MCS field | |
889 | * always contains the MCS used for the last transmission, be | |
890 | * it successful or not. | |
891 | */ | |
892 | if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { | |
893 | /* | |
894 | * Transmission succeeded. The number of retries is | |
895 | * mcs - real_mcs | |
896 | */ | |
897 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
898 | txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); | |
899 | } else { | |
900 | /* | |
901 | * Transmission failed. The number of retries is | |
902 | * always 7 in this case (for a total number of 8 | |
903 | * frames sent). | |
904 | */ | |
905 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
906 | txdesc.retry = rt2x00dev->long_retry; | |
907 | } | |
908 | ||
909 | /* | |
910 | * the frame was retried at least once | |
911 | * -> hw used fallback rates | |
912 | */ | |
913 | if (txdesc.retry) | |
914 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); | |
915 | ||
916 | rt2x00lib_txdone(entry, &txdesc); | |
917 | } | |
918 | EXPORT_SYMBOL_GPL(rt2800_txdone_entry); | |
919 | ||
f0194b2d GW |
920 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) |
921 | { | |
922 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
923 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
924 | unsigned int beacon_base; | |
739fd940 | 925 | unsigned int padding_len; |
d76dfc61 | 926 | u32 orig_reg, reg; |
f0bda571 | 927 | const int txwi_desc_size = entry->queue->winfo_size; |
f0194b2d GW |
928 | |
929 | /* | |
930 | * Disable beaconing while we are reloading the beacon data, | |
931 | * otherwise we might be sending out invalid data. | |
932 | */ | |
933 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
d76dfc61 | 934 | orig_reg = reg; |
f0194b2d GW |
935 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
936 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
937 | ||
938 | /* | |
939 | * Add space for the TXWI in front of the skb. | |
940 | */ | |
f0bda571 | 941 | memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); |
f0194b2d GW |
942 | |
943 | /* | |
944 | * Register descriptor details in skb frame descriptor. | |
945 | */ | |
946 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; | |
947 | skbdesc->desc = entry->skb->data; | |
f0bda571 | 948 | skbdesc->desc_len = txwi_desc_size; |
f0194b2d GW |
949 | |
950 | /* | |
951 | * Add the TXWI for the beacon to the skb. | |
952 | */ | |
0c5879bc | 953 | rt2800_write_tx_data(entry, txdesc); |
f0194b2d GW |
954 | |
955 | /* | |
956 | * Dump beacon to userspace through debugfs. | |
957 | */ | |
958 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
959 | ||
960 | /* | |
739fd940 | 961 | * Write entire beacon with TXWI and padding to register. |
f0194b2d | 962 | */ |
739fd940 | 963 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 | 964 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
ec9c4989 | 965 | rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); |
d76dfc61 SF |
966 | /* skb freed by skb_pad() on failure */ |
967 | entry->skb = NULL; | |
968 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); | |
969 | return; | |
970 | } | |
971 | ||
f0194b2d | 972 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
973 | rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
974 | entry->skb->len + padding_len); | |
f0194b2d GW |
975 | |
976 | /* | |
977 | * Enable beaconing again. | |
978 | */ | |
f0194b2d GW |
979 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); |
980 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
981 | ||
982 | /* | |
983 | * Clean up beacon skb. | |
984 | */ | |
985 | dev_kfree_skb_any(entry->skb); | |
986 | entry->skb = NULL; | |
987 | } | |
50e888ea | 988 | EXPORT_SYMBOL_GPL(rt2800_write_beacon); |
f0194b2d | 989 | |
69cf36a4 HS |
990 | static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, |
991 | unsigned int beacon_base) | |
fdb87251 HS |
992 | { |
993 | int i; | |
0879f875 | 994 | const int txwi_desc_size = rt2x00dev->bcn->winfo_size; |
fdb87251 HS |
995 | |
996 | /* | |
997 | * For the Beacon base registers we only need to clear | |
998 | * the whole TXWI which (when set to 0) will invalidate | |
999 | * the entire beacon. | |
1000 | */ | |
f0bda571 | 1001 | for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) |
fdb87251 HS |
1002 | rt2800_register_write(rt2x00dev, beacon_base + i, 0); |
1003 | } | |
1004 | ||
69cf36a4 HS |
1005 | void rt2800_clear_beacon(struct queue_entry *entry) |
1006 | { | |
1007 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1008 | u32 reg; | |
1009 | ||
1010 | /* | |
1011 | * Disable beaconing while we are reloading the beacon data, | |
1012 | * otherwise we might be sending out invalid data. | |
1013 | */ | |
1014 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
1015 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
1016 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1017 | ||
1018 | /* | |
1019 | * Clear beacon. | |
1020 | */ | |
1021 | rt2800_clear_beacon_register(rt2x00dev, | |
1022 | HW_BEACON_OFFSET(entry->entry_idx)); | |
1023 | ||
1024 | /* | |
1025 | * Enabled beaconing again. | |
1026 | */ | |
1027 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); | |
1028 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1029 | } | |
1030 | EXPORT_SYMBOL_GPL(rt2800_clear_beacon); | |
1031 | ||
f4450616 BZ |
1032 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
1033 | const struct rt2x00debug rt2800_rt2x00debug = { | |
1034 | .owner = THIS_MODULE, | |
1035 | .csr = { | |
1036 | .read = rt2800_register_read, | |
1037 | .write = rt2800_register_write, | |
1038 | .flags = RT2X00DEBUGFS_OFFSET, | |
1039 | .word_base = CSR_REG_BASE, | |
1040 | .word_size = sizeof(u32), | |
1041 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
1042 | }, | |
1043 | .eeprom = { | |
3e38d3da GJ |
1044 | /* NOTE: The local EEPROM access functions can't |
1045 | * be used here, use the generic versions instead. | |
1046 | */ | |
f4450616 BZ |
1047 | .read = rt2x00_eeprom_read, |
1048 | .write = rt2x00_eeprom_write, | |
1049 | .word_base = EEPROM_BASE, | |
1050 | .word_size = sizeof(u16), | |
1051 | .word_count = EEPROM_SIZE / sizeof(u16), | |
1052 | }, | |
1053 | .bbp = { | |
1054 | .read = rt2800_bbp_read, | |
1055 | .write = rt2800_bbp_write, | |
1056 | .word_base = BBP_BASE, | |
1057 | .word_size = sizeof(u8), | |
1058 | .word_count = BBP_SIZE / sizeof(u8), | |
1059 | }, | |
1060 | .rf = { | |
1061 | .read = rt2x00_rf_read, | |
1062 | .write = rt2800_rf_write, | |
1063 | .word_base = RF_BASE, | |
1064 | .word_size = sizeof(u32), | |
1065 | .word_count = RF_SIZE / sizeof(u32), | |
1066 | }, | |
f2bd7f16 AA |
1067 | .rfcsr = { |
1068 | .read = rt2800_rfcsr_read, | |
1069 | .write = rt2800_rfcsr_write, | |
1070 | .word_base = RFCSR_BASE, | |
1071 | .word_size = sizeof(u8), | |
1072 | .word_count = RFCSR_SIZE / sizeof(u8), | |
1073 | }, | |
f4450616 BZ |
1074 | }; |
1075 | EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); | |
1076 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
1077 | ||
1078 | int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) | |
1079 | { | |
1080 | u32 reg; | |
1081 | ||
a89534ed WH |
1082 | if (rt2x00_rt(rt2x00dev, RT3290)) { |
1083 | rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); | |
1084 | return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); | |
1085 | } else { | |
99bdf51a GW |
1086 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); |
1087 | return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); | |
a89534ed | 1088 | } |
f4450616 BZ |
1089 | } |
1090 | EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); | |
1091 | ||
1092 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
1093 | static void rt2800_brightness_set(struct led_classdev *led_cdev, | |
1094 | enum led_brightness brightness) | |
1095 | { | |
1096 | struct rt2x00_led *led = | |
1097 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
1098 | unsigned int enabled = brightness != LED_OFF; | |
1099 | unsigned int bg_mode = | |
1100 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
1101 | unsigned int polarity = | |
1102 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
1103 | EEPROM_FREQ_LED_POLARITY); | |
1104 | unsigned int ledmode = | |
1105 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
1106 | EEPROM_FREQ_LED_MODE); | |
44704e5d | 1107 | u32 reg; |
f4450616 | 1108 | |
44704e5d LE |
1109 | /* Check for SoC (SOC devices don't support MCU requests) */ |
1110 | if (rt2x00_is_soc(led->rt2x00dev)) { | |
1111 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | |
1112 | ||
1113 | /* Set LED Polarity */ | |
1114 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); | |
1115 | ||
1116 | /* Set LED Mode */ | |
1117 | if (led->type == LED_TYPE_RADIO) { | |
1118 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, | |
1119 | enabled ? 3 : 0); | |
1120 | } else if (led->type == LED_TYPE_ASSOC) { | |
1121 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, | |
1122 | enabled ? 3 : 0); | |
1123 | } else if (led->type == LED_TYPE_QUALITY) { | |
1124 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, | |
1125 | enabled ? 3 : 0); | |
1126 | } | |
1127 | ||
1128 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); | |
1129 | ||
1130 | } else { | |
1131 | if (led->type == LED_TYPE_RADIO) { | |
1132 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
1133 | enabled ? 0x20 : 0); | |
1134 | } else if (led->type == LED_TYPE_ASSOC) { | |
1135 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
1136 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); | |
1137 | } else if (led->type == LED_TYPE_QUALITY) { | |
1138 | /* | |
1139 | * The brightness is divided into 6 levels (0 - 5), | |
1140 | * The specs tell us the following levels: | |
1141 | * 0, 1 ,3, 7, 15, 31 | |
1142 | * to determine the level in a simple way we can simply | |
1143 | * work with bitshifting: | |
1144 | * (1 << level) - 1 | |
1145 | */ | |
1146 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
1147 | (1 << brightness / (LED_FULL / 6)) - 1, | |
1148 | polarity); | |
1149 | } | |
f4450616 BZ |
1150 | } |
1151 | } | |
1152 | ||
b3579d6a | 1153 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, |
f4450616 BZ |
1154 | struct rt2x00_led *led, enum led_type type) |
1155 | { | |
1156 | led->rt2x00dev = rt2x00dev; | |
1157 | led->type = type; | |
1158 | led->led_dev.brightness_set = rt2800_brightness_set; | |
f4450616 BZ |
1159 | led->flags = LED_INITIALIZED; |
1160 | } | |
f4450616 BZ |
1161 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
1162 | ||
1163 | /* | |
1164 | * Configuration handlers. | |
1165 | */ | |
a2b1328a HS |
1166 | static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, |
1167 | const u8 *address, | |
1168 | int wcid) | |
f4450616 BZ |
1169 | { |
1170 | struct mac_wcid_entry wcid_entry; | |
a2b1328a HS |
1171 | u32 offset; |
1172 | ||
1173 | offset = MAC_WCID_ENTRY(wcid); | |
1174 | ||
1175 | memset(&wcid_entry, 0xff, sizeof(wcid_entry)); | |
1176 | if (address) | |
1177 | memcpy(wcid_entry.mac, address, ETH_ALEN); | |
1178 | ||
1179 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1180 | &wcid_entry, sizeof(wcid_entry)); | |
1181 | } | |
1182 | ||
1183 | static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) | |
1184 | { | |
1185 | u32 offset; | |
1186 | offset = MAC_WCID_ATTR_ENTRY(wcid); | |
1187 | rt2800_register_write(rt2x00dev, offset, 0); | |
1188 | } | |
1189 | ||
1190 | static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, | |
1191 | int wcid, u32 bssidx) | |
1192 | { | |
1193 | u32 offset = MAC_WCID_ATTR_ENTRY(wcid); | |
1194 | u32 reg; | |
1195 | ||
1196 | /* | |
1197 | * The BSS Idx numbers is split in a main value of 3 bits, | |
1198 | * and a extended field for adding one additional bit to the value. | |
1199 | */ | |
1200 | rt2800_register_read(rt2x00dev, offset, ®); | |
1201 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); | |
1202 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, | |
1203 | (bssidx & 0x8) >> 3); | |
1204 | rt2800_register_write(rt2x00dev, offset, reg); | |
1205 | } | |
1206 | ||
1207 | static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, | |
1208 | struct rt2x00lib_crypto *crypto, | |
1209 | struct ieee80211_key_conf *key) | |
1210 | { | |
f4450616 BZ |
1211 | struct mac_iveiv_entry iveiv_entry; |
1212 | u32 offset; | |
1213 | u32 reg; | |
1214 | ||
1215 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); | |
1216 | ||
e4a0ab34 ID |
1217 | if (crypto->cmd == SET_KEY) { |
1218 | rt2800_register_read(rt2x00dev, offset, ®); | |
1219 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, | |
1220 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); | |
1221 | /* | |
1222 | * Both the cipher as the BSS Idx numbers are split in a main | |
1223 | * value of 3 bits, and a extended field for adding one additional | |
1224 | * bit to the value. | |
1225 | */ | |
1226 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, | |
1227 | (crypto->cipher & 0x7)); | |
1228 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, | |
1229 | (crypto->cipher & 0x8) >> 3); | |
e4a0ab34 ID |
1230 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); |
1231 | rt2800_register_write(rt2x00dev, offset, reg); | |
1232 | } else { | |
a2b1328a HS |
1233 | /* Delete the cipher without touching the bssidx */ |
1234 | rt2800_register_read(rt2x00dev, offset, ®); | |
1235 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); | |
1236 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); | |
1237 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); | |
1238 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); | |
1239 | rt2800_register_write(rt2x00dev, offset, reg); | |
e4a0ab34 | 1240 | } |
f4450616 BZ |
1241 | |
1242 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); | |
1243 | ||
1244 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); | |
1245 | if ((crypto->cipher == CIPHER_TKIP) || | |
1246 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || | |
1247 | (crypto->cipher == CIPHER_AES)) | |
1248 | iveiv_entry.iv[3] |= 0x20; | |
1249 | iveiv_entry.iv[3] |= key->keyidx << 6; | |
1250 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1251 | &iveiv_entry, sizeof(iveiv_entry)); | |
f4450616 BZ |
1252 | } |
1253 | ||
1254 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |
1255 | struct rt2x00lib_crypto *crypto, | |
1256 | struct ieee80211_key_conf *key) | |
1257 | { | |
1258 | struct hw_key_entry key_entry; | |
1259 | struct rt2x00_field32 field; | |
1260 | u32 offset; | |
1261 | u32 reg; | |
1262 | ||
1263 | if (crypto->cmd == SET_KEY) { | |
1264 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; | |
1265 | ||
1266 | memcpy(key_entry.key, crypto->key, | |
1267 | sizeof(key_entry.key)); | |
1268 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1269 | sizeof(key_entry.tx_mic)); | |
1270 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1271 | sizeof(key_entry.rx_mic)); | |
1272 | ||
1273 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); | |
1274 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1275 | &key_entry, sizeof(key_entry)); | |
1276 | } | |
1277 | ||
1278 | /* | |
1279 | * The cipher types are stored over multiple registers | |
1280 | * starting with SHARED_KEY_MODE_BASE each word will have | |
1281 | * 32 bits and contains the cipher types for 2 bssidx each. | |
1282 | * Using the correct defines correctly will cause overhead, | |
1283 | * so just calculate the correct offset. | |
1284 | */ | |
1285 | field.bit_offset = 4 * (key->hw_key_idx % 8); | |
1286 | field.bit_mask = 0x7 << field.bit_offset; | |
1287 | ||
1288 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); | |
1289 | ||
1290 | rt2800_register_read(rt2x00dev, offset, ®); | |
1291 | rt2x00_set_field32(®, field, | |
1292 | (crypto->cmd == SET_KEY) * crypto->cipher); | |
1293 | rt2800_register_write(rt2x00dev, offset, reg); | |
1294 | ||
1295 | /* | |
1296 | * Update WCID information | |
1297 | */ | |
a2b1328a HS |
1298 | rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); |
1299 | rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, | |
1300 | crypto->bssidx); | |
1301 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); | |
f4450616 BZ |
1302 | |
1303 | return 0; | |
1304 | } | |
1305 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); | |
1306 | ||
a2b1328a | 1307 | static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev) |
1ed3811c | 1308 | { |
a2b1328a | 1309 | struct mac_wcid_entry wcid_entry; |
1ed3811c | 1310 | int idx; |
a2b1328a | 1311 | u32 offset; |
1ed3811c HS |
1312 | |
1313 | /* | |
a2b1328a HS |
1314 | * Search for the first free WCID entry and return the corresponding |
1315 | * index. | |
1ed3811c HS |
1316 | * |
1317 | * Make sure the WCID starts _after_ the last possible shared key | |
1318 | * entry (>32). | |
1319 | * | |
1320 | * Since parts of the pairwise key table might be shared with | |
1321 | * the beacon frame buffers 6 & 7 we should only write into the | |
1322 | * first 222 entries. | |
1323 | */ | |
1324 | for (idx = 33; idx <= 222; idx++) { | |
a2b1328a HS |
1325 | offset = MAC_WCID_ENTRY(idx); |
1326 | rt2800_register_multiread(rt2x00dev, offset, &wcid_entry, | |
1327 | sizeof(wcid_entry)); | |
1328 | if (is_broadcast_ether_addr(wcid_entry.mac)) | |
1ed3811c HS |
1329 | return idx; |
1330 | } | |
a2b1328a HS |
1331 | |
1332 | /* | |
1333 | * Use -1 to indicate that we don't have any more space in the WCID | |
1334 | * table. | |
1335 | */ | |
1ed3811c HS |
1336 | return -1; |
1337 | } | |
1338 | ||
f4450616 BZ |
1339 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
1340 | struct rt2x00lib_crypto *crypto, | |
1341 | struct ieee80211_key_conf *key) | |
1342 | { | |
1343 | struct hw_key_entry key_entry; | |
1344 | u32 offset; | |
1345 | ||
1346 | if (crypto->cmd == SET_KEY) { | |
a2b1328a HS |
1347 | /* |
1348 | * Allow key configuration only for STAs that are | |
1349 | * known by the hw. | |
1350 | */ | |
1351 | if (crypto->wcid < 0) | |
f4450616 | 1352 | return -ENOSPC; |
a2b1328a | 1353 | key->hw_key_idx = crypto->wcid; |
f4450616 BZ |
1354 | |
1355 | memcpy(key_entry.key, crypto->key, | |
1356 | sizeof(key_entry.key)); | |
1357 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1358 | sizeof(key_entry.tx_mic)); | |
1359 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1360 | sizeof(key_entry.rx_mic)); | |
1361 | ||
1362 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
1363 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1364 | &key_entry, sizeof(key_entry)); | |
1365 | } | |
1366 | ||
1367 | /* | |
1368 | * Update WCID information | |
1369 | */ | |
a2b1328a | 1370 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); |
f4450616 BZ |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); | |
1375 | ||
a2b1328a HS |
1376 | int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, |
1377 | struct ieee80211_sta *sta) | |
1378 | { | |
1379 | int wcid; | |
1380 | struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); | |
1381 | ||
1382 | /* | |
1383 | * Find next free WCID. | |
1384 | */ | |
1385 | wcid = rt2800_find_wcid(rt2x00dev); | |
1386 | ||
1387 | /* | |
1388 | * Store selected wcid even if it is invalid so that we can | |
1389 | * later decide if the STA is uploaded into the hw. | |
1390 | */ | |
1391 | sta_priv->wcid = wcid; | |
1392 | ||
1393 | /* | |
1394 | * No space left in the device, however, we can still communicate | |
1395 | * with the STA -> No error. | |
1396 | */ | |
1397 | if (wcid < 0) | |
1398 | return 0; | |
1399 | ||
1400 | /* | |
1401 | * Clean up WCID attributes and write STA address to the device. | |
1402 | */ | |
1403 | rt2800_delete_wcid_attr(rt2x00dev, wcid); | |
1404 | rt2800_config_wcid(rt2x00dev, sta->addr, wcid); | |
1405 | rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, | |
1406 | rt2x00lib_get_bssidx(rt2x00dev, vif)); | |
1407 | return 0; | |
1408 | } | |
1409 | EXPORT_SYMBOL_GPL(rt2800_sta_add); | |
1410 | ||
1411 | int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) | |
1412 | { | |
1413 | /* | |
1414 | * Remove WCID entry, no need to clean the attributes as they will | |
1415 | * get renewed when the WCID is reused. | |
1416 | */ | |
1417 | rt2800_config_wcid(rt2x00dev, NULL, wcid); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | EXPORT_SYMBOL_GPL(rt2800_sta_remove); | |
1422 | ||
f4450616 BZ |
1423 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, |
1424 | const unsigned int filter_flags) | |
1425 | { | |
1426 | u32 reg; | |
1427 | ||
1428 | /* | |
1429 | * Start configuration steps. | |
1430 | * Note that the version error will always be dropped | |
1431 | * and broadcast frames will always be accepted since | |
1432 | * there is no filter for it at this time. | |
1433 | */ | |
1434 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); | |
1435 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, | |
1436 | !(filter_flags & FIF_FCSFAIL)); | |
1437 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, | |
1438 | !(filter_flags & FIF_PLCPFAIL)); | |
1439 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, | |
1440 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
1441 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); | |
1442 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); | |
1443 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, | |
1444 | !(filter_flags & FIF_ALLMULTI)); | |
1445 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); | |
1446 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); | |
1447 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, | |
1448 | !(filter_flags & FIF_CONTROL)); | |
1449 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, | |
1450 | !(filter_flags & FIF_CONTROL)); | |
1451 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, | |
1452 | !(filter_flags & FIF_CONTROL)); | |
1453 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, | |
1454 | !(filter_flags & FIF_CONTROL)); | |
1455 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, | |
1456 | !(filter_flags & FIF_CONTROL)); | |
1457 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, | |
1458 | !(filter_flags & FIF_PSPOLL)); | |
84e9e8eb | 1459 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); |
48839938 HS |
1460 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, |
1461 | !(filter_flags & FIF_CONTROL)); | |
f4450616 BZ |
1462 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, |
1463 | !(filter_flags & FIF_CONTROL)); | |
1464 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); | |
1465 | } | |
1466 | EXPORT_SYMBOL_GPL(rt2800_config_filter); | |
1467 | ||
1468 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, | |
1469 | struct rt2x00intf_conf *conf, const unsigned int flags) | |
1470 | { | |
f4450616 | 1471 | u32 reg; |
fa8b4b22 | 1472 | bool update_bssid = false; |
f4450616 BZ |
1473 | |
1474 | if (flags & CONFIG_UPDATE_TYPE) { | |
f4450616 BZ |
1475 | /* |
1476 | * Enable synchronisation. | |
1477 | */ | |
1478 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
f4450616 | 1479 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); |
f4450616 | 1480 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
15a533c4 HS |
1481 | |
1482 | if (conf->sync == TSF_SYNC_AP_NONE) { | |
1483 | /* | |
1484 | * Tune beacon queue transmit parameters for AP mode | |
1485 | */ | |
1486 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1487 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); | |
1488 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); | |
1489 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1490 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); | |
1491 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1492 | } else { | |
1493 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1494 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); | |
1495 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); | |
1496 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1497 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); | |
1498 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1499 | } | |
f4450616 BZ |
1500 | } |
1501 | ||
1502 | if (flags & CONFIG_UPDATE_MAC) { | |
fa8b4b22 HS |
1503 | if (flags & CONFIG_UPDATE_TYPE && |
1504 | conf->sync == TSF_SYNC_AP_NONE) { | |
1505 | /* | |
1506 | * The BSSID register has to be set to our own mac | |
1507 | * address in AP mode. | |
1508 | */ | |
1509 | memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); | |
1510 | update_bssid = true; | |
1511 | } | |
1512 | ||
c600c826 ID |
1513 | if (!is_zero_ether_addr((const u8 *)conf->mac)) { |
1514 | reg = le32_to_cpu(conf->mac[1]); | |
1515 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); | |
1516 | conf->mac[1] = cpu_to_le32(reg); | |
1517 | } | |
f4450616 BZ |
1518 | |
1519 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, | |
1520 | conf->mac, sizeof(conf->mac)); | |
1521 | } | |
1522 | ||
fa8b4b22 | 1523 | if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { |
c600c826 ID |
1524 | if (!is_zero_ether_addr((const u8 *)conf->bssid)) { |
1525 | reg = le32_to_cpu(conf->bssid[1]); | |
1526 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); | |
1527 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7); | |
1528 | conf->bssid[1] = cpu_to_le32(reg); | |
1529 | } | |
f4450616 BZ |
1530 | |
1531 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, | |
1532 | conf->bssid, sizeof(conf->bssid)); | |
1533 | } | |
1534 | } | |
1535 | EXPORT_SYMBOL_GPL(rt2800_config_intf); | |
1536 | ||
87c1915d HS |
1537 | static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, |
1538 | struct rt2x00lib_erp *erp) | |
1539 | { | |
1540 | bool any_sta_nongf = !!(erp->ht_opmode & | |
1541 | IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); | |
1542 | u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; | |
1543 | u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; | |
1544 | u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; | |
1545 | u32 reg; | |
1546 | ||
1547 | /* default protection rate for HT20: OFDM 24M */ | |
1548 | mm20_rate = gf20_rate = 0x4004; | |
1549 | ||
1550 | /* default protection rate for HT40: duplicate OFDM 24M */ | |
1551 | mm40_rate = gf40_rate = 0x4084; | |
1552 | ||
1553 | switch (protection) { | |
1554 | case IEEE80211_HT_OP_MODE_PROTECTION_NONE: | |
1555 | /* | |
1556 | * All STAs in this BSS are HT20/40 but there might be | |
1557 | * STAs not supporting greenfield mode. | |
1558 | * => Disable protection for HT transmissions. | |
1559 | */ | |
1560 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; | |
1561 | ||
1562 | break; | |
1563 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
1564 | /* | |
1565 | * All STAs in this BSS are HT20 or HT20/40 but there | |
1566 | * might be STAs not supporting greenfield mode. | |
1567 | * => Protect all HT40 transmissions. | |
1568 | */ | |
1569 | mm20_mode = gf20_mode = 0; | |
1570 | mm40_mode = gf40_mode = 2; | |
1571 | ||
1572 | break; | |
1573 | case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: | |
1574 | /* | |
1575 | * Nonmember protection: | |
1576 | * According to 802.11n we _should_ protect all | |
1577 | * HT transmissions (but we don't have to). | |
1578 | * | |
1579 | * But if cts_protection is enabled we _shall_ protect | |
1580 | * all HT transmissions using a CCK rate. | |
1581 | * | |
1582 | * And if any station is non GF we _shall_ protect | |
1583 | * GF transmissions. | |
1584 | * | |
1585 | * We decide to protect everything | |
1586 | * -> fall through to mixed mode. | |
1587 | */ | |
1588 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
1589 | /* | |
1590 | * Legacy STAs are present | |
1591 | * => Protect all HT transmissions. | |
1592 | */ | |
1593 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2; | |
1594 | ||
1595 | /* | |
1596 | * If erp protection is needed we have to protect HT | |
1597 | * transmissions with CCK 11M long preamble. | |
1598 | */ | |
1599 | if (erp->cts_protection) { | |
1600 | /* don't duplicate RTS/CTS in CCK mode */ | |
1601 | mm20_rate = mm40_rate = 0x0003; | |
1602 | gf20_rate = gf40_rate = 0x0003; | |
1603 | } | |
1604 | break; | |
6403eab1 | 1605 | } |
87c1915d HS |
1606 | |
1607 | /* check for STAs not supporting greenfield mode */ | |
1608 | if (any_sta_nongf) | |
1609 | gf20_mode = gf40_mode = 2; | |
1610 | ||
1611 | /* Update HT protection config */ | |
1612 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
1613 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); | |
1614 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); | |
1615 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
1616 | ||
1617 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
1618 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); | |
1619 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); | |
1620 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
1621 | ||
1622 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
1623 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); | |
1624 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); | |
1625 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
1626 | ||
1627 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
1628 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); | |
1629 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); | |
1630 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
1631 | } | |
1632 | ||
02044643 HS |
1633 | void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, |
1634 | u32 changed) | |
f4450616 BZ |
1635 | { |
1636 | u32 reg; | |
1637 | ||
02044643 HS |
1638 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1639 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); | |
1640 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, | |
1641 | !!erp->short_preamble); | |
1642 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, | |
1643 | !!erp->short_preamble); | |
1644 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
1645 | } | |
f4450616 | 1646 | |
02044643 HS |
1647 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1648 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
1649 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, | |
1650 | erp->cts_protection ? 2 : 0); | |
1651 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
1652 | } | |
f4450616 | 1653 | |
02044643 HS |
1654 | if (changed & BSS_CHANGED_BASIC_RATES) { |
1655 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, | |
1656 | erp->basic_rates); | |
1657 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
1658 | } | |
f4450616 | 1659 | |
02044643 HS |
1660 | if (changed & BSS_CHANGED_ERP_SLOT) { |
1661 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
1662 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, | |
1663 | erp->slot_time); | |
1664 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
f4450616 | 1665 | |
02044643 HS |
1666 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
1667 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); | |
1668 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
1669 | } | |
f4450616 | 1670 | |
02044643 HS |
1671 | if (changed & BSS_CHANGED_BEACON_INT) { |
1672 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
1673 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, | |
1674 | erp->beacon_int * 16); | |
1675 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1676 | } | |
87c1915d HS |
1677 | |
1678 | if (changed & BSS_CHANGED_HT) | |
1679 | rt2800_config_ht_opmode(rt2x00dev, erp); | |
f4450616 BZ |
1680 | } |
1681 | EXPORT_SYMBOL_GPL(rt2800_config_erp); | |
1682 | ||
872834df GW |
1683 | static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) |
1684 | { | |
1685 | u32 reg; | |
1686 | u16 eeprom; | |
1687 | u8 led_ctrl, led_g_mode, led_r_mode; | |
1688 | ||
1689 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
1690 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { | |
1691 | rt2x00_set_field32(®, GPIO_SWITCH_0, 1); | |
1692 | rt2x00_set_field32(®, GPIO_SWITCH_1, 1); | |
1693 | } else { | |
1694 | rt2x00_set_field32(®, GPIO_SWITCH_0, 0); | |
1695 | rt2x00_set_field32(®, GPIO_SWITCH_1, 0); | |
1696 | } | |
1697 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
1698 | ||
1699 | rt2800_register_read(rt2x00dev, LED_CFG, ®); | |
1700 | led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; | |
1701 | led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; | |
1702 | if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || | |
1703 | led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { | |
3e38d3da | 1704 | rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
872834df GW |
1705 | led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); |
1706 | if (led_ctrl == 0 || led_ctrl > 0x40) { | |
1707 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); | |
1708 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); | |
1709 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | |
1710 | } else { | |
1711 | rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, | |
1712 | (led_g_mode << 2) | led_r_mode, 1); | |
1713 | } | |
1714 | } | |
1715 | } | |
1716 | ||
d96aa640 RJH |
1717 | static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, |
1718 | enum antenna ant) | |
1719 | { | |
1720 | u32 reg; | |
1721 | u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; | |
1722 | u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; | |
1723 | ||
1724 | if (rt2x00_is_pci(rt2x00dev)) { | |
1725 | rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); | |
1726 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); | |
1727 | rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); | |
1728 | } else if (rt2x00_is_usb(rt2x00dev)) | |
1729 | rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, | |
1730 | eesk_pin, 0); | |
1731 | ||
99bdf51a GW |
1732 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); |
1733 | rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); | |
1734 | rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); | |
1735 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | |
d96aa640 RJH |
1736 | } |
1737 | ||
f4450616 BZ |
1738 | void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) |
1739 | { | |
1740 | u8 r1; | |
1741 | u8 r3; | |
d96aa640 | 1742 | u16 eeprom; |
f4450616 BZ |
1743 | |
1744 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
1745 | rt2800_bbp_read(rt2x00dev, 3, &r3); | |
1746 | ||
872834df GW |
1747 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1748 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | |
1749 | rt2800_config_3572bt_ant(rt2x00dev); | |
1750 | ||
f4450616 BZ |
1751 | /* |
1752 | * Configure the TX antenna. | |
1753 | */ | |
d96aa640 | 1754 | switch (ant->tx_chain_num) { |
f4450616 BZ |
1755 | case 1: |
1756 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | |
f4450616 BZ |
1757 | break; |
1758 | case 2: | |
872834df GW |
1759 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1760 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | |
1761 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); | |
1762 | else | |
1763 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | |
f4450616 BZ |
1764 | break; |
1765 | case 3: | |
4788ac1e | 1766 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); |
f4450616 BZ |
1767 | break; |
1768 | } | |
1769 | ||
1770 | /* | |
1771 | * Configure the RX antenna. | |
1772 | */ | |
d96aa640 | 1773 | switch (ant->rx_chain_num) { |
f4450616 | 1774 | case 1: |
d96aa640 RJH |
1775 | if (rt2x00_rt(rt2x00dev, RT3070) || |
1776 | rt2x00_rt(rt2x00dev, RT3090) || | |
03839951 | 1777 | rt2x00_rt(rt2x00dev, RT3352) || |
d96aa640 | 1778 | rt2x00_rt(rt2x00dev, RT3390)) { |
3e38d3da | 1779 | rt2800_eeprom_read(rt2x00dev, |
d96aa640 RJH |
1780 | EEPROM_NIC_CONF1, &eeprom); |
1781 | if (rt2x00_get_field16(eeprom, | |
1782 | EEPROM_NIC_CONF1_ANT_DIVERSITY)) | |
1783 | rt2800_set_ant_diversity(rt2x00dev, | |
1784 | rt2x00dev->default_ant.rx); | |
1785 | } | |
f4450616 BZ |
1786 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
1787 | break; | |
1788 | case 2: | |
872834df GW |
1789 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1790 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | |
1791 | rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); | |
1792 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, | |
1793 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
1794 | rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); | |
1795 | } else { | |
1796 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | |
1797 | } | |
f4450616 BZ |
1798 | break; |
1799 | case 3: | |
1800 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); | |
1801 | break; | |
1802 | } | |
1803 | ||
1804 | rt2800_bbp_write(rt2x00dev, 3, r3); | |
1805 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
5cddb3c2 GJ |
1806 | |
1807 | if (rt2x00_rt(rt2x00dev, RT3593)) { | |
1808 | if (ant->rx_chain_num == 1) | |
1809 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
1810 | else | |
1811 | rt2800_bbp_write(rt2x00dev, 86, 0x46); | |
1812 | } | |
f4450616 BZ |
1813 | } |
1814 | EXPORT_SYMBOL_GPL(rt2800_config_ant); | |
1815 | ||
1816 | static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, | |
1817 | struct rt2x00lib_conf *libconf) | |
1818 | { | |
1819 | u16 eeprom; | |
1820 | short lna_gain; | |
1821 | ||
1822 | if (libconf->rf.channel <= 14) { | |
3e38d3da | 1823 | rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
f4450616 BZ |
1824 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); |
1825 | } else if (libconf->rf.channel <= 64) { | |
3e38d3da | 1826 | rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
f4450616 BZ |
1827 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); |
1828 | } else if (libconf->rf.channel <= 128) { | |
f36bb0ca GJ |
1829 | if (rt2x00_rt(rt2x00dev, RT3593)) { |
1830 | rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); | |
1831 | lna_gain = rt2x00_get_field16(eeprom, | |
1832 | EEPROM_EXT_LNA2_A1); | |
1833 | } else { | |
1834 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
1835 | lna_gain = rt2x00_get_field16(eeprom, | |
1836 | EEPROM_RSSI_BG2_LNA_A1); | |
1837 | } | |
f4450616 | 1838 | } else { |
f36bb0ca GJ |
1839 | if (rt2x00_rt(rt2x00dev, RT3593)) { |
1840 | rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); | |
1841 | lna_gain = rt2x00_get_field16(eeprom, | |
1842 | EEPROM_EXT_LNA2_A2); | |
1843 | } else { | |
1844 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
1845 | lna_gain = rt2x00_get_field16(eeprom, | |
1846 | EEPROM_RSSI_A2_LNA_A2); | |
1847 | } | |
f4450616 BZ |
1848 | } |
1849 | ||
1850 | rt2x00dev->lna_gain = lna_gain; | |
1851 | } | |
1852 | ||
06855ef4 GW |
1853 | static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, |
1854 | struct ieee80211_conf *conf, | |
1855 | struct rf_channel *rf, | |
1856 | struct channel_info *info) | |
f4450616 BZ |
1857 | { |
1858 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1859 | ||
d96aa640 | 1860 | if (rt2x00dev->default_ant.tx_chain_num == 1) |
f4450616 BZ |
1861 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); |
1862 | ||
d96aa640 | 1863 | if (rt2x00dev->default_ant.rx_chain_num == 1) { |
f4450616 BZ |
1864 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); |
1865 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); | |
d96aa640 | 1866 | } else if (rt2x00dev->default_ant.rx_chain_num == 2) |
f4450616 BZ |
1867 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
1868 | ||
1869 | if (rf->channel > 14) { | |
1870 | /* | |
1871 | * When TX power is below 0, we should increase it by 7 to | |
25985edc | 1872 | * make it a positive value (Minimum value is -7). |
f4450616 BZ |
1873 | * However this means that values between 0 and 7 have |
1874 | * double meaning, and we should set a 7DBm boost flag. | |
1875 | */ | |
1876 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1877 | (info->default_power1 >= 0)); |
f4450616 | 1878 | |
8d1331b3 ID |
1879 | if (info->default_power1 < 0) |
1880 | info->default_power1 += 7; | |
f4450616 | 1881 | |
8d1331b3 | 1882 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); |
f4450616 BZ |
1883 | |
1884 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1885 | (info->default_power2 >= 0)); |
f4450616 | 1886 | |
8d1331b3 ID |
1887 | if (info->default_power2 < 0) |
1888 | info->default_power2 += 7; | |
f4450616 | 1889 | |
8d1331b3 | 1890 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); |
f4450616 | 1891 | } else { |
8d1331b3 ID |
1892 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); |
1893 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); | |
f4450616 BZ |
1894 | } |
1895 | ||
1896 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); | |
1897 | ||
1898 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1899 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1900 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1901 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1902 | ||
1903 | udelay(200); | |
1904 | ||
1905 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1906 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1907 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
1908 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1909 | ||
1910 | udelay(200); | |
1911 | ||
1912 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1913 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1914 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1915 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1916 | } | |
1917 | ||
06855ef4 GW |
1918 | static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, |
1919 | struct ieee80211_conf *conf, | |
1920 | struct rf_channel *rf, | |
1921 | struct channel_info *info) | |
f4450616 | 1922 | { |
3a1c0128 | 1923 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; |
f1f12f98 | 1924 | u8 rfcsr, calib_tx, calib_rx; |
f4450616 BZ |
1925 | |
1926 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
7f4666ab SG |
1927 | |
1928 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
1929 | rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); | |
1930 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); | |
f4450616 BZ |
1931 | |
1932 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
fab799c3 | 1933 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); |
f4450616 BZ |
1934 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); |
1935 | ||
1936 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
8d1331b3 | 1937 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); |
f4450616 BZ |
1938 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); |
1939 | ||
5a673964 | 1940 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); |
8d1331b3 | 1941 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); |
5a673964 | 1942 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); |
e3bab197 SG |
1943 | |
1944 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
1945 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
7ad63035 GW |
1946 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, |
1947 | rt2x00dev->default_ant.rx_chain_num <= 1); | |
1948 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, | |
1949 | rt2x00dev->default_ant.rx_chain_num <= 2); | |
e3bab197 | 1950 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); |
7ad63035 GW |
1951 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, |
1952 | rt2x00dev->default_ant.tx_chain_num <= 1); | |
1953 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, | |
1954 | rt2x00dev->default_ant.tx_chain_num <= 2); | |
e3bab197 | 1955 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); |
5a673964 | 1956 | |
3e0c7643 SG |
1957 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); |
1958 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
1959 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1960 | msleep(1); | |
1961 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | |
1962 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1963 | ||
f4450616 BZ |
1964 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
1965 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1966 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
1967 | ||
f1f12f98 SG |
1968 | if (rt2x00_rt(rt2x00dev, RT3390)) { |
1969 | calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; | |
1970 | calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; | |
1971 | } else { | |
3a1c0128 GW |
1972 | if (conf_is_ht40(conf)) { |
1973 | calib_tx = drv_data->calibration_bw40; | |
1974 | calib_rx = drv_data->calibration_bw40; | |
1975 | } else { | |
1976 | calib_tx = drv_data->calibration_bw20; | |
1977 | calib_rx = drv_data->calibration_bw20; | |
1978 | } | |
f1f12f98 SG |
1979 | } |
1980 | ||
1981 | rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); | |
1982 | rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); | |
1983 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); | |
1984 | ||
1985 | rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); | |
1986 | rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); | |
1987 | rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); | |
f4450616 | 1988 | |
71976907 | 1989 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); |
f4450616 | 1990 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); |
71976907 | 1991 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
3e0c7643 SG |
1992 | |
1993 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
1994 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
1995 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1996 | msleep(1); | |
1997 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | |
1998 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
f4450616 BZ |
1999 | } |
2000 | ||
872834df GW |
2001 | static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, |
2002 | struct ieee80211_conf *conf, | |
2003 | struct rf_channel *rf, | |
2004 | struct channel_info *info) | |
2005 | { | |
3a1c0128 | 2006 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; |
872834df GW |
2007 | u8 rfcsr; |
2008 | u32 reg; | |
2009 | ||
2010 | if (rf->channel <= 14) { | |
5d137dff GW |
2011 | rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); |
2012 | rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); | |
872834df GW |
2013 | } else { |
2014 | rt2800_bbp_write(rt2x00dev, 25, 0x09); | |
2015 | rt2800_bbp_write(rt2x00dev, 26, 0xff); | |
2016 | } | |
2017 | ||
2018 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
2019 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); | |
2020 | ||
2021 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
2022 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); | |
2023 | if (rf->channel <= 14) | |
2024 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); | |
2025 | else | |
2026 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); | |
2027 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
2028 | ||
2029 | rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); | |
2030 | if (rf->channel <= 14) | |
2031 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); | |
2032 | else | |
2033 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); | |
2034 | rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); | |
2035 | ||
2036 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
2037 | if (rf->channel <= 14) { | |
2038 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); | |
2039 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | |
569ffa56 | 2040 | info->default_power1); |
872834df GW |
2041 | } else { |
2042 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); | |
2043 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | |
2044 | (info->default_power1 & 0x3) | | |
2045 | ((info->default_power1 & 0xC) << 1)); | |
2046 | } | |
2047 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); | |
2048 | ||
2049 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); | |
2050 | if (rf->channel <= 14) { | |
2051 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); | |
2052 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | |
569ffa56 | 2053 | info->default_power2); |
872834df GW |
2054 | } else { |
2055 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); | |
2056 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | |
2057 | (info->default_power2 & 0x3) | | |
2058 | ((info->default_power2 & 0xC) << 1)); | |
2059 | } | |
2060 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); | |
2061 | ||
2062 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
872834df GW |
2063 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); |
2064 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
2065 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); | |
2066 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | |
0cd461ef GW |
2067 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); |
2068 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); | |
872834df GW |
2069 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
2070 | if (rf->channel <= 14) { | |
2071 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
2072 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
2073 | } | |
2074 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | |
2075 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | |
2076 | } else { | |
2077 | switch (rt2x00dev->default_ant.tx_chain_num) { | |
2078 | case 1: | |
2079 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
2080 | case 2: | |
2081 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | |
2082 | break; | |
2083 | } | |
2084 | ||
2085 | switch (rt2x00dev->default_ant.rx_chain_num) { | |
2086 | case 1: | |
2087 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
2088 | case 2: | |
2089 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | |
2090 | break; | |
2091 | } | |
2092 | } | |
2093 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
2094 | ||
2095 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | |
2096 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
2097 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
2098 | ||
3a1c0128 GW |
2099 | if (conf_is_ht40(conf)) { |
2100 | rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); | |
2101 | rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); | |
2102 | } else { | |
2103 | rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); | |
2104 | rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); | |
2105 | } | |
872834df GW |
2106 | |
2107 | if (rf->channel <= 14) { | |
2108 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | |
2109 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | |
2110 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
2111 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | |
2112 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | |
77c06c2c GW |
2113 | rfcsr = 0x4c; |
2114 | rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, | |
2115 | drv_data->txmixer_gain_24g); | |
2116 | rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); | |
872834df GW |
2117 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); |
2118 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | |
2119 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | |
2120 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | |
2121 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
2122 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
2123 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | |
2124 | } else { | |
58b8ae14 GW |
2125 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); |
2126 | rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); | |
2127 | rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); | |
2128 | rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); | |
2129 | rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); | |
2130 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | |
872834df GW |
2131 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); |
2132 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
2133 | rt2800_rfcsr_write(rt2x00dev, 11, 0x00); | |
2134 | rt2800_rfcsr_write(rt2x00dev, 15, 0x43); | |
77c06c2c GW |
2135 | rfcsr = 0x7a; |
2136 | rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, | |
2137 | drv_data->txmixer_gain_5g); | |
2138 | rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); | |
872834df GW |
2139 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); |
2140 | if (rf->channel <= 64) { | |
2141 | rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); | |
2142 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); | |
2143 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | |
2144 | } else if (rf->channel <= 128) { | |
2145 | rt2800_rfcsr_write(rt2x00dev, 19, 0x74); | |
2146 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); | |
2147 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
2148 | } else { | |
2149 | rt2800_rfcsr_write(rt2x00dev, 19, 0x72); | |
2150 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); | |
2151 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
2152 | } | |
2153 | rt2800_rfcsr_write(rt2x00dev, 26, 0x87); | |
2154 | rt2800_rfcsr_write(rt2x00dev, 27, 0x01); | |
2155 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); | |
2156 | } | |
2157 | ||
99bdf51a GW |
2158 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); |
2159 | rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); | |
872834df | 2160 | if (rf->channel <= 14) |
99bdf51a | 2161 | rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); |
872834df | 2162 | else |
99bdf51a GW |
2163 | rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); |
2164 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | |
872834df GW |
2165 | |
2166 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); | |
2167 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); | |
2168 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | |
2169 | } | |
60687ba7 | 2170 | |
f42b0465 GJ |
2171 | static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, |
2172 | struct ieee80211_conf *conf, | |
2173 | struct rf_channel *rf, | |
2174 | struct channel_info *info) | |
2175 | { | |
2176 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | |
2177 | u8 txrx_agc_fc; | |
2178 | u8 txrx_h20m; | |
2179 | u8 rfcsr; | |
2180 | u8 bbp; | |
2181 | const bool txbf_enabled = false; /* TODO */ | |
2182 | ||
2183 | /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ | |
2184 | rt2800_bbp_read(rt2x00dev, 109, &bbp); | |
2185 | rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); | |
2186 | rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); | |
2187 | rt2800_bbp_write(rt2x00dev, 109, bbp); | |
2188 | ||
2189 | rt2800_bbp_read(rt2x00dev, 110, &bbp); | |
2190 | rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); | |
2191 | rt2800_bbp_write(rt2x00dev, 110, bbp); | |
2192 | ||
2193 | if (rf->channel <= 14) { | |
2194 | /* Restore BBP 25 & 26 for 2.4 GHz */ | |
2195 | rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); | |
2196 | rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); | |
2197 | } else { | |
2198 | /* Hard code BBP 25 & 26 for 5GHz */ | |
2199 | ||
2200 | /* Enable IQ Phase correction */ | |
2201 | rt2800_bbp_write(rt2x00dev, 25, 0x09); | |
2202 | /* Setup IQ Phase correction value */ | |
2203 | rt2800_bbp_write(rt2x00dev, 26, 0xff); | |
2204 | } | |
2205 | ||
2206 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
2207 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); | |
2208 | ||
2209 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
2210 | rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); | |
2211 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
2212 | ||
2213 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
2214 | rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); | |
2215 | if (rf->channel <= 14) | |
2216 | rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); | |
2217 | else | |
2218 | rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); | |
2219 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
2220 | ||
2221 | rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr); | |
2222 | if (rf->channel <= 14) { | |
2223 | rfcsr = 0; | |
2224 | rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, | |
2225 | info->default_power1 & 0x1f); | |
2226 | } else { | |
2227 | if (rt2x00_is_usb(rt2x00dev)) | |
2228 | rfcsr = 0x40; | |
2229 | ||
2230 | rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, | |
2231 | ((info->default_power1 & 0x18) << 1) | | |
2232 | (info->default_power1 & 7)); | |
2233 | } | |
2234 | rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); | |
2235 | ||
2236 | rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr); | |
2237 | if (rf->channel <= 14) { | |
2238 | rfcsr = 0; | |
2239 | rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, | |
2240 | info->default_power2 & 0x1f); | |
2241 | } else { | |
2242 | if (rt2x00_is_usb(rt2x00dev)) | |
2243 | rfcsr = 0x40; | |
2244 | ||
2245 | rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, | |
2246 | ((info->default_power2 & 0x18) << 1) | | |
2247 | (info->default_power2 & 7)); | |
2248 | } | |
2249 | rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); | |
2250 | ||
2251 | rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr); | |
2252 | if (rf->channel <= 14) { | |
2253 | rfcsr = 0; | |
2254 | rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, | |
2255 | info->default_power3 & 0x1f); | |
2256 | } else { | |
2257 | if (rt2x00_is_usb(rt2x00dev)) | |
2258 | rfcsr = 0x40; | |
2259 | ||
2260 | rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, | |
2261 | ((info->default_power3 & 0x18) << 1) | | |
2262 | (info->default_power3 & 7)); | |
2263 | } | |
2264 | rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); | |
2265 | ||
2266 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
2267 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
2268 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
2269 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); | |
2270 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | |
2271 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); | |
2272 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); | |
2273 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
2274 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
2275 | ||
2276 | switch (rt2x00dev->default_ant.tx_chain_num) { | |
2277 | case 3: | |
2278 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | |
2279 | /* fallthrough */ | |
2280 | case 2: | |
2281 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
2282 | /* fallthrough */ | |
2283 | case 1: | |
2284 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
2285 | break; | |
2286 | } | |
2287 | ||
2288 | switch (rt2x00dev->default_ant.rx_chain_num) { | |
2289 | case 3: | |
2290 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | |
2291 | /* fallthrough */ | |
2292 | case 2: | |
2293 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
2294 | /* fallthrough */ | |
2295 | case 1: | |
2296 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
2297 | break; | |
2298 | } | |
2299 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
2300 | ||
2301 | /* TODO: frequency calibration? */ | |
2302 | ||
2303 | if (conf_is_ht40(conf)) { | |
2304 | txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, | |
2305 | RFCSR24_TX_AGC_FC); | |
2306 | txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, | |
2307 | RFCSR24_TX_H20M); | |
2308 | } else { | |
2309 | txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, | |
2310 | RFCSR24_TX_AGC_FC); | |
2311 | txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, | |
2312 | RFCSR24_TX_H20M); | |
2313 | } | |
2314 | ||
2315 | /* NOTE: the reference driver does not writes the new value | |
2316 | * back to RFCSR 32 | |
2317 | */ | |
2318 | rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr); | |
2319 | rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); | |
2320 | ||
2321 | if (rf->channel <= 14) | |
2322 | rfcsr = 0xa0; | |
2323 | else | |
2324 | rfcsr = 0x80; | |
2325 | rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); | |
2326 | ||
2327 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
2328 | rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); | |
2329 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); | |
2330 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
2331 | ||
2332 | /* Band selection */ | |
2333 | rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr); | |
2334 | if (rf->channel <= 14) | |
2335 | rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); | |
2336 | else | |
2337 | rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); | |
2338 | rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); | |
2339 | ||
2340 | rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr); | |
2341 | if (rf->channel <= 14) | |
2342 | rfcsr = 0x3c; | |
2343 | else | |
2344 | rfcsr = 0x20; | |
2345 | rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); | |
2346 | ||
2347 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
2348 | if (rf->channel <= 14) | |
2349 | rfcsr = 0x1a; | |
2350 | else | |
2351 | rfcsr = 0x12; | |
2352 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); | |
2353 | ||
2354 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
2355 | if (rf->channel >= 1 && rf->channel <= 14) | |
2356 | rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); | |
2357 | else if (rf->channel >= 36 && rf->channel <= 64) | |
2358 | rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); | |
2359 | else if (rf->channel >= 100 && rf->channel <= 128) | |
2360 | rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); | |
2361 | else | |
2362 | rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); | |
2363 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
2364 | ||
2365 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
2366 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); | |
2367 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
2368 | ||
2369 | rt2800_rfcsr_write(rt2x00dev, 46, 0x60); | |
2370 | ||
2371 | if (rf->channel <= 14) { | |
2372 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); | |
2373 | rt2800_rfcsr_write(rt2x00dev, 13, 0x12); | |
2374 | } else { | |
2375 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); | |
2376 | rt2800_rfcsr_write(rt2x00dev, 13, 0x23); | |
2377 | } | |
2378 | ||
2379 | rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); | |
2380 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); | |
2381 | rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); | |
2382 | ||
2383 | rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); | |
2384 | if (rf->channel <= 14) { | |
2385 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); | |
2386 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); | |
2387 | } else { | |
2388 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); | |
2389 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); | |
2390 | } | |
2391 | rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); | |
2392 | ||
2393 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
2394 | if (rf->channel <= 14) | |
2395 | rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); | |
2396 | else | |
2397 | rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); | |
2398 | ||
2399 | if (txbf_enabled) | |
2400 | rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); | |
2401 | ||
2402 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
2403 | ||
2404 | rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); | |
2405 | rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); | |
2406 | rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); | |
2407 | ||
2408 | rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr); | |
2409 | if (rf->channel <= 14) | |
2410 | rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); | |
2411 | else | |
2412 | rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); | |
2413 | rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); | |
2414 | ||
2415 | if (rf->channel <= 14) { | |
2416 | rt2800_rfcsr_write(rt2x00dev, 44, 0x93); | |
2417 | rt2800_rfcsr_write(rt2x00dev, 52, 0x45); | |
2418 | } else { | |
2419 | rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); | |
2420 | rt2800_rfcsr_write(rt2x00dev, 52, 0x05); | |
2421 | } | |
2422 | ||
2423 | /* Initiate VCO calibration */ | |
2424 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
2425 | if (rf->channel <= 14) { | |
2426 | rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); | |
2427 | } else { | |
2428 | rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); | |
2429 | rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); | |
2430 | rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); | |
2431 | rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); | |
2432 | rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); | |
2433 | rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); | |
2434 | } | |
2435 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); | |
2436 | ||
2437 | if (rf->channel >= 1 && rf->channel <= 14) { | |
2438 | rfcsr = 0x23; | |
2439 | if (txbf_enabled) | |
2440 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); | |
2441 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
2442 | ||
2443 | rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); | |
2444 | } else if (rf->channel >= 36 && rf->channel <= 64) { | |
2445 | rfcsr = 0x36; | |
2446 | if (txbf_enabled) | |
2447 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); | |
2448 | rt2800_rfcsr_write(rt2x00dev, 39, 0x36); | |
2449 | ||
2450 | rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); | |
2451 | } else if (rf->channel >= 100 && rf->channel <= 128) { | |
2452 | rfcsr = 0x32; | |
2453 | if (txbf_enabled) | |
2454 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); | |
2455 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
2456 | ||
2457 | rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); | |
2458 | } else { | |
2459 | rfcsr = 0x30; | |
2460 | if (txbf_enabled) | |
2461 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); | |
2462 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
2463 | ||
2464 | rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); | |
2465 | } | |
2466 | } | |
2467 | ||
7573cb5b | 2468 | #define POWER_BOUND 0x27 |
8f821098 | 2469 | #define POWER_BOUND_5G 0x2b |
7573cb5b | 2470 | #define FREQ_OFFSET_BOUND 0x5f |
60687ba7 | 2471 | |
0c9e5fb9 SG |
2472 | static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev) |
2473 | { | |
2474 | u8 rfcsr; | |
2475 | ||
2476 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
2477 | if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND) | |
2478 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND); | |
2479 | else | |
2480 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset); | |
2481 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
2482 | } | |
2483 | ||
a89534ed WH |
2484 | static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, |
2485 | struct ieee80211_conf *conf, | |
2486 | struct rf_channel *rf, | |
2487 | struct channel_info *info) | |
2488 | { | |
2489 | u8 rfcsr; | |
2490 | ||
2491 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
2492 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); | |
2493 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
2494 | rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); | |
2495 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
2496 | ||
2497 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
7573cb5b SG |
2498 | if (info->default_power1 > POWER_BOUND) |
2499 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); | |
a89534ed WH |
2500 | else |
2501 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); | |
2502 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
2503 | ||
0c9e5fb9 | 2504 | rt2800_adjust_freq_offset(rt2x00dev); |
a89534ed WH |
2505 | |
2506 | if (rf->channel <= 14) { | |
2507 | if (rf->channel == 6) | |
2508 | rt2800_bbp_write(rt2x00dev, 68, 0x0c); | |
2509 | else | |
2510 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
2511 | ||
2512 | if (rf->channel >= 1 && rf->channel <= 6) | |
2513 | rt2800_bbp_write(rt2x00dev, 59, 0x0f); | |
2514 | else if (rf->channel >= 7 && rf->channel <= 11) | |
2515 | rt2800_bbp_write(rt2x00dev, 59, 0x0e); | |
2516 | else if (rf->channel >= 12 && rf->channel <= 14) | |
2517 | rt2800_bbp_write(rt2x00dev, 59, 0x0d); | |
2518 | } | |
2519 | } | |
2520 | ||
03839951 DG |
2521 | static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, |
2522 | struct ieee80211_conf *conf, | |
2523 | struct rf_channel *rf, | |
2524 | struct channel_info *info) | |
2525 | { | |
2526 | u8 rfcsr; | |
2527 | ||
2528 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
2529 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); | |
2530 | ||
2531 | rt2800_rfcsr_write(rt2x00dev, 11, 0x42); | |
2532 | rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); | |
2533 | rt2800_rfcsr_write(rt2x00dev, 13, 0x00); | |
2534 | ||
2535 | if (info->default_power1 > POWER_BOUND) | |
2536 | rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); | |
2537 | else | |
2538 | rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); | |
2539 | ||
2540 | if (info->default_power2 > POWER_BOUND) | |
2541 | rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); | |
2542 | else | |
2543 | rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); | |
2544 | ||
0c9e5fb9 | 2545 | rt2800_adjust_freq_offset(rt2x00dev); |
03839951 DG |
2546 | |
2547 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
2548 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
2549 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
2550 | ||
2551 | if ( rt2x00dev->default_ant.tx_chain_num == 2 ) | |
2552 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
2553 | else | |
2554 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | |
2555 | ||
2556 | if ( rt2x00dev->default_ant.rx_chain_num == 2 ) | |
2557 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
2558 | else | |
2559 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); | |
2560 | ||
2561 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); | |
2562 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); | |
2563 | ||
2564 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
2565 | ||
2566 | rt2800_rfcsr_write(rt2x00dev, 31, 80); | |
2567 | } | |
2568 | ||
60687ba7 | 2569 | static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, |
adde5882 GJ |
2570 | struct ieee80211_conf *conf, |
2571 | struct rf_channel *rf, | |
2572 | struct channel_info *info) | |
2573 | { | |
2574 | u8 rfcsr; | |
adde5882 GJ |
2575 | |
2576 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
2577 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); | |
2578 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
2579 | rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); | |
2580 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
2581 | ||
2582 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
7573cb5b SG |
2583 | if (info->default_power1 > POWER_BOUND) |
2584 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); | |
adde5882 GJ |
2585 | else |
2586 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); | |
2587 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
2588 | ||
cff3d1f0 ZL |
2589 | if (rt2x00_rt(rt2x00dev, RT5392)) { |
2590 | rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); | |
7573cb5b SG |
2591 | if (info->default_power1 > POWER_BOUND) |
2592 | rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); | |
cff3d1f0 ZL |
2593 | else |
2594 | rt2x00_set_field8(&rfcsr, RFCSR50_TX, | |
2595 | info->default_power2); | |
2596 | rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); | |
2597 | } | |
2598 | ||
adde5882 | 2599 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); |
cff3d1f0 ZL |
2600 | if (rt2x00_rt(rt2x00dev, RT5392)) { |
2601 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
2602 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
2603 | } | |
adde5882 GJ |
2604 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); |
2605 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
2606 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
2607 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
2608 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
2609 | ||
0c9e5fb9 | 2610 | rt2800_adjust_freq_offset(rt2x00dev); |
adde5882 | 2611 | |
adde5882 GJ |
2612 | if (rf->channel <= 14) { |
2613 | int idx = rf->channel-1; | |
2614 | ||
fdbc7b0a | 2615 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
adde5882 GJ |
2616 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { |
2617 | /* r55/r59 value array of channel 1~14 */ | |
2618 | static const char r55_bt_rev[] = {0x83, 0x83, | |
2619 | 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, | |
2620 | 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; | |
2621 | static const char r59_bt_rev[] = {0x0e, 0x0e, | |
2622 | 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, | |
2623 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; | |
2624 | ||
2625 | rt2800_rfcsr_write(rt2x00dev, 55, | |
2626 | r55_bt_rev[idx]); | |
2627 | rt2800_rfcsr_write(rt2x00dev, 59, | |
2628 | r59_bt_rev[idx]); | |
2629 | } else { | |
2630 | static const char r59_bt[] = {0x8b, 0x8b, 0x8b, | |
2631 | 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, | |
2632 | 0x88, 0x88, 0x86, 0x85, 0x84}; | |
2633 | ||
2634 | rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); | |
2635 | } | |
2636 | } else { | |
2637 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { | |
2638 | static const char r55_nonbt_rev[] = {0x23, 0x23, | |
2639 | 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, | |
2640 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; | |
2641 | static const char r59_nonbt_rev[] = {0x07, 0x07, | |
2642 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
2643 | 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; | |
2644 | ||
2645 | rt2800_rfcsr_write(rt2x00dev, 55, | |
2646 | r55_nonbt_rev[idx]); | |
2647 | rt2800_rfcsr_write(rt2x00dev, 59, | |
2648 | r59_nonbt_rev[idx]); | |
2ed71884 | 2649 | } else if (rt2x00_rt(rt2x00dev, RT5390) || |
e6d227b9 | 2650 | rt2x00_rt(rt2x00dev, RT5392)) { |
adde5882 GJ |
2651 | static const char r59_non_bt[] = {0x8f, 0x8f, |
2652 | 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, | |
2653 | 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; | |
2654 | ||
2655 | rt2800_rfcsr_write(rt2x00dev, 59, | |
2656 | r59_non_bt[idx]); | |
2657 | } | |
2658 | } | |
2659 | } | |
60687ba7 RST |
2660 | } |
2661 | ||
8f821098 SG |
2662 | static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, |
2663 | struct ieee80211_conf *conf, | |
2664 | struct rf_channel *rf, | |
2665 | struct channel_info *info) | |
2666 | { | |
2667 | u8 rfcsr, ep_reg; | |
d5ae7a6b | 2668 | u32 reg; |
8f821098 SG |
2669 | int power_bound; |
2670 | ||
2671 | /* TODO */ | |
2672 | const bool is_11b = false; | |
2673 | const bool is_type_ep = false; | |
2674 | ||
d5ae7a6b SG |
2675 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); |
2676 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, | |
2677 | (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); | |
2678 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
8f821098 SG |
2679 | |
2680 | /* Order of values on rf_channel entry: N, K, mod, R */ | |
2681 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); | |
2682 | ||
2683 | rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr); | |
2684 | rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); | |
2685 | rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); | |
2686 | rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); | |
2687 | rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); | |
2688 | ||
2689 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
2690 | rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); | |
2691 | rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); | |
2692 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
2693 | ||
2694 | if (rf->channel <= 14) { | |
2695 | rt2800_rfcsr_write(rt2x00dev, 10, 0x90); | |
2696 | /* FIXME: RF11 owerwrite ? */ | |
2697 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); | |
2698 | rt2800_rfcsr_write(rt2x00dev, 12, 0x52); | |
2699 | rt2800_rfcsr_write(rt2x00dev, 13, 0x42); | |
2700 | rt2800_rfcsr_write(rt2x00dev, 22, 0x40); | |
2701 | rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); | |
2702 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
2703 | rt2800_rfcsr_write(rt2x00dev, 27, 0x42); | |
2704 | rt2800_rfcsr_write(rt2x00dev, 36, 0x80); | |
2705 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | |
2706 | rt2800_rfcsr_write(rt2x00dev, 38, 0x89); | |
2707 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); | |
2708 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); | |
2709 | rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); | |
2710 | rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); | |
2711 | rt2800_rfcsr_write(rt2x00dev, 43, 0x72); | |
2712 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); | |
2713 | rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); | |
2714 | rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); | |
2715 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
2716 | rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); | |
2717 | rt2800_rfcsr_write(rt2x00dev, 52, 0x48); | |
2718 | rt2800_rfcsr_write(rt2x00dev, 54, 0x38); | |
2719 | rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); | |
2720 | rt2800_rfcsr_write(rt2x00dev, 57, 0x00); | |
2721 | rt2800_rfcsr_write(rt2x00dev, 58, 0x39); | |
2722 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
2723 | rt2800_rfcsr_write(rt2x00dev, 61, 0x91); | |
2724 | rt2800_rfcsr_write(rt2x00dev, 62, 0x39); | |
2725 | ||
2726 | /* TODO RF27 <- tssi */ | |
2727 | ||
2728 | rfcsr = rf->channel <= 10 ? 0x07 : 0x06; | |
2729 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
2730 | rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); | |
2731 | ||
2732 | if (is_11b) { | |
2733 | /* CCK */ | |
2734 | rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); | |
2735 | rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); | |
2736 | if (is_type_ep) | |
2737 | rt2800_rfcsr_write(rt2x00dev, 55, 0x06); | |
2738 | else | |
2739 | rt2800_rfcsr_write(rt2x00dev, 55, 0x47); | |
2740 | } else { | |
2741 | /* OFDM */ | |
2742 | if (is_type_ep) | |
2743 | rt2800_rfcsr_write(rt2x00dev, 55, 0x03); | |
2744 | else | |
2745 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | |
2746 | } | |
2747 | ||
2748 | power_bound = POWER_BOUND; | |
2749 | ep_reg = 0x2; | |
2750 | } else { | |
2751 | rt2800_rfcsr_write(rt2x00dev, 10, 0x97); | |
2752 | /* FIMXE: RF11 overwrite */ | |
2753 | rt2800_rfcsr_write(rt2x00dev, 11, 0x40); | |
2754 | rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); | |
2755 | rt2800_rfcsr_write(rt2x00dev, 27, 0x42); | |
2756 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
2757 | rt2800_rfcsr_write(rt2x00dev, 37, 0x04); | |
2758 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | |
2759 | rt2800_rfcsr_write(rt2x00dev, 40, 0x42); | |
2760 | rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); | |
2761 | rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); | |
2762 | rt2800_rfcsr_write(rt2x00dev, 45, 0x41); | |
2763 | rt2800_rfcsr_write(rt2x00dev, 48, 0x00); | |
2764 | rt2800_rfcsr_write(rt2x00dev, 57, 0x77); | |
2765 | rt2800_rfcsr_write(rt2x00dev, 60, 0x05); | |
2766 | rt2800_rfcsr_write(rt2x00dev, 61, 0x01); | |
2767 | ||
2768 | /* TODO RF27 <- tssi */ | |
2769 | ||
2770 | if (rf->channel >= 36 && rf->channel <= 64) { | |
2771 | ||
2772 | rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); | |
2773 | rt2800_rfcsr_write(rt2x00dev, 13, 0x22); | |
2774 | rt2800_rfcsr_write(rt2x00dev, 22, 0x60); | |
2775 | rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); | |
2776 | if (rf->channel <= 50) | |
2777 | rt2800_rfcsr_write(rt2x00dev, 24, 0x09); | |
2778 | else if (rf->channel >= 52) | |
2779 | rt2800_rfcsr_write(rt2x00dev, 24, 0x07); | |
2780 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); | |
2781 | rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); | |
2782 | rt2800_rfcsr_write(rt2x00dev, 44, 0X40); | |
2783 | rt2800_rfcsr_write(rt2x00dev, 46, 0X00); | |
2784 | rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); | |
2785 | rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); | |
2786 | rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); | |
2787 | if (rf->channel <= 50) { | |
2788 | rt2800_rfcsr_write(rt2x00dev, 55, 0x06), | |
2789 | rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); | |
2790 | } else if (rf->channel >= 52) { | |
2791 | rt2800_rfcsr_write(rt2x00dev, 55, 0x04); | |
2792 | rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); | |
2793 | } | |
2794 | ||
2795 | rt2800_rfcsr_write(rt2x00dev, 58, 0x15); | |
2796 | rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); | |
2797 | rt2800_rfcsr_write(rt2x00dev, 62, 0x15); | |
2798 | ||
2799 | } else if (rf->channel >= 100 && rf->channel <= 165) { | |
2800 | ||
2801 | rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); | |
2802 | rt2800_rfcsr_write(rt2x00dev, 13, 0x42); | |
2803 | rt2800_rfcsr_write(rt2x00dev, 22, 0x40); | |
2804 | if (rf->channel <= 153) { | |
2805 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); | |
2806 | rt2800_rfcsr_write(rt2x00dev, 24, 0x06); | |
2807 | } else if (rf->channel >= 155) { | |
2808 | rt2800_rfcsr_write(rt2x00dev, 23, 0x38); | |
2809 | rt2800_rfcsr_write(rt2x00dev, 24, 0x05); | |
2810 | } | |
2811 | if (rf->channel <= 138) { | |
2812 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); | |
2813 | rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); | |
2814 | rt2800_rfcsr_write(rt2x00dev, 44, 0x20); | |
2815 | rt2800_rfcsr_write(rt2x00dev, 46, 0x18); | |
2816 | } else if (rf->channel >= 140) { | |
2817 | rt2800_rfcsr_write(rt2x00dev, 39, 0x18); | |
2818 | rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); | |
2819 | rt2800_rfcsr_write(rt2x00dev, 44, 0x10); | |
2820 | rt2800_rfcsr_write(rt2x00dev, 46, 0X08); | |
2821 | } | |
2822 | if (rf->channel <= 124) | |
2823 | rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); | |
2824 | else if (rf->channel >= 126) | |
2825 | rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); | |
2826 | if (rf->channel <= 138) | |
2827 | rt2800_rfcsr_write(rt2x00dev, 52, 0x06); | |
2828 | else if (rf->channel >= 140) | |
2829 | rt2800_rfcsr_write(rt2x00dev, 52, 0x06); | |
2830 | rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); | |
2831 | if (rf->channel <= 138) | |
2832 | rt2800_rfcsr_write(rt2x00dev, 55, 0x01); | |
2833 | else if (rf->channel >= 140) | |
2834 | rt2800_rfcsr_write(rt2x00dev, 55, 0x00); | |
2835 | if (rf->channel <= 128) | |
2836 | rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); | |
2837 | else if (rf->channel >= 130) | |
2838 | rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); | |
2839 | if (rf->channel <= 116) | |
2840 | rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); | |
2841 | else if (rf->channel >= 118) | |
2842 | rt2800_rfcsr_write(rt2x00dev, 58, 0x15); | |
2843 | if (rf->channel <= 138) | |
2844 | rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); | |
2845 | else if (rf->channel >= 140) | |
2846 | rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); | |
2847 | if (rf->channel <= 116) | |
2848 | rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); | |
2849 | else if (rf->channel >= 118) | |
2850 | rt2800_rfcsr_write(rt2x00dev, 62, 0x15); | |
2851 | } | |
2852 | ||
2853 | power_bound = POWER_BOUND_5G; | |
2854 | ep_reg = 0x3; | |
2855 | } | |
2856 | ||
2857 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
2858 | if (info->default_power1 > power_bound) | |
2859 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); | |
2860 | else | |
2861 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); | |
2862 | if (is_type_ep) | |
2863 | rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); | |
2864 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
2865 | ||
2866 | rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); | |
0847beb2 | 2867 | if (info->default_power2 > power_bound) |
8f821098 SG |
2868 | rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); |
2869 | else | |
2870 | rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); | |
2871 | if (is_type_ep) | |
2872 | rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); | |
2873 | rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); | |
2874 | ||
2875 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
2876 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
2877 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
2878 | ||
2879 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, | |
2880 | rt2x00dev->default_ant.tx_chain_num >= 1); | |
2881 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, | |
2882 | rt2x00dev->default_ant.tx_chain_num == 2); | |
2883 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); | |
2884 | ||
2885 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, | |
2886 | rt2x00dev->default_ant.rx_chain_num >= 1); | |
2887 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, | |
2888 | rt2x00dev->default_ant.rx_chain_num == 2); | |
2889 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); | |
2890 | ||
2891 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
2892 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); | |
2893 | ||
2894 | if (conf_is_ht40(conf)) | |
2895 | rt2800_rfcsr_write(rt2x00dev, 30, 0x16); | |
2896 | else | |
2897 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | |
2898 | ||
2899 | if (!is_11b) { | |
2900 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
2901 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
2902 | } | |
2903 | ||
2904 | /* TODO proper frequency adjustment */ | |
0c9e5fb9 | 2905 | rt2800_adjust_freq_offset(rt2x00dev); |
8f821098 SG |
2906 | |
2907 | /* TODO merge with others */ | |
2908 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
2909 | rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); | |
2910 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); | |
6803141b SG |
2911 | |
2912 | /* BBP settings */ | |
2913 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
2914 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
2915 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
2916 | ||
2917 | rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); | |
2918 | rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); | |
2919 | rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); | |
2920 | rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); | |
2921 | ||
2922 | /* GLRT band configuration */ | |
2923 | rt2800_bbp_write(rt2x00dev, 195, 128); | |
2924 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); | |
2925 | rt2800_bbp_write(rt2x00dev, 195, 129); | |
2926 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); | |
2927 | rt2800_bbp_write(rt2x00dev, 195, 130); | |
2928 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); | |
2929 | rt2800_bbp_write(rt2x00dev, 195, 131); | |
2930 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); | |
2931 | rt2800_bbp_write(rt2x00dev, 195, 133); | |
2932 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); | |
2933 | rt2800_bbp_write(rt2x00dev, 195, 124); | |
2934 | rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); | |
8f821098 SG |
2935 | } |
2936 | ||
5bc2dd06 SG |
2937 | static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, |
2938 | const unsigned int word, | |
2939 | const u8 value) | |
2940 | { | |
2941 | u8 chain, reg; | |
2942 | ||
2943 | for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { | |
2944 | rt2800_bbp_read(rt2x00dev, 27, ®); | |
2945 | rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); | |
2946 | rt2800_bbp_write(rt2x00dev, 27, reg); | |
2947 | ||
2948 | rt2800_bbp_write(rt2x00dev, word, value); | |
2949 | } | |
2950 | } | |
2951 | ||
8756130b SG |
2952 | static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) |
2953 | { | |
2954 | u8 cal; | |
2955 | ||
415e3f2f | 2956 | /* TX0 IQ Gain */ |
8756130b | 2957 | rt2800_bbp_write(rt2x00dev, 158, 0x2c); |
415e3f2f SG |
2958 | if (channel <= 14) |
2959 | cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); | |
2960 | else if (channel >= 36 && channel <= 64) | |
2961 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2962 | EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); | |
2963 | else if (channel >= 100 && channel <= 138) | |
2964 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2965 | EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); | |
2966 | else if (channel >= 140 && channel <= 165) | |
2967 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2968 | EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); | |
2969 | else | |
2970 | cal = 0; | |
8756130b SG |
2971 | rt2800_bbp_write(rt2x00dev, 159, cal); |
2972 | ||
415e3f2f | 2973 | /* TX0 IQ Phase */ |
8756130b | 2974 | rt2800_bbp_write(rt2x00dev, 158, 0x2d); |
415e3f2f SG |
2975 | if (channel <= 14) |
2976 | cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); | |
2977 | else if (channel >= 36 && channel <= 64) | |
2978 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2979 | EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); | |
2980 | else if (channel >= 100 && channel <= 138) | |
2981 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2982 | EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); | |
2983 | else if (channel >= 140 && channel <= 165) | |
2984 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2985 | EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); | |
2986 | else | |
2987 | cal = 0; | |
8756130b SG |
2988 | rt2800_bbp_write(rt2x00dev, 159, cal); |
2989 | ||
415e3f2f | 2990 | /* TX1 IQ Gain */ |
8756130b | 2991 | rt2800_bbp_write(rt2x00dev, 158, 0x4a); |
415e3f2f SG |
2992 | if (channel <= 14) |
2993 | cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); | |
2994 | else if (channel >= 36 && channel <= 64) | |
2995 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2996 | EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); | |
2997 | else if (channel >= 100 && channel <= 138) | |
2998 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
2999 | EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); | |
3000 | else if (channel >= 140 && channel <= 165) | |
3001 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
3002 | EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); | |
3003 | else | |
3004 | cal = 0; | |
8756130b SG |
3005 | rt2800_bbp_write(rt2x00dev, 159, cal); |
3006 | ||
415e3f2f | 3007 | /* TX1 IQ Phase */ |
8756130b | 3008 | rt2800_bbp_write(rt2x00dev, 158, 0x4b); |
415e3f2f SG |
3009 | if (channel <= 14) |
3010 | cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); | |
3011 | else if (channel >= 36 && channel <= 64) | |
3012 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
3013 | EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); | |
3014 | else if (channel >= 100 && channel <= 138) | |
3015 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
3016 | EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); | |
3017 | else if (channel >= 140 && channel <= 165) | |
3018 | cal = rt2x00_eeprom_byte(rt2x00dev, | |
3019 | EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); | |
3020 | else | |
3021 | cal = 0; | |
8756130b SG |
3022 | rt2800_bbp_write(rt2x00dev, 159, cal); |
3023 | ||
415e3f2f SG |
3024 | /* FIXME: possible RX0, RX1 callibration ? */ |
3025 | ||
8756130b SG |
3026 | /* RF IQ compensation control */ |
3027 | rt2800_bbp_write(rt2x00dev, 158, 0x04); | |
3028 | cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); | |
3029 | rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); | |
3030 | ||
3031 | /* RF IQ imbalance compensation control */ | |
3032 | rt2800_bbp_write(rt2x00dev, 158, 0x03); | |
415e3f2f SG |
3033 | cal = rt2x00_eeprom_byte(rt2x00dev, |
3034 | EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); | |
8756130b SG |
3035 | rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); |
3036 | } | |
3037 | ||
97aa03f1 GJ |
3038 | static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, |
3039 | unsigned int channel, | |
3040 | char txpower) | |
3041 | { | |
fc739cfe GJ |
3042 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3043 | txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); | |
3044 | ||
97aa03f1 GJ |
3045 | if (channel <= 14) |
3046 | return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); | |
fc739cfe GJ |
3047 | |
3048 | if (rt2x00_rt(rt2x00dev, RT3593)) | |
3049 | return clamp_t(char, txpower, MIN_A_TXPOWER_3593, | |
3050 | MAX_A_TXPOWER_3593); | |
97aa03f1 GJ |
3051 | else |
3052 | return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); | |
3053 | } | |
3054 | ||
f4450616 BZ |
3055 | static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, |
3056 | struct ieee80211_conf *conf, | |
3057 | struct rf_channel *rf, | |
3058 | struct channel_info *info) | |
3059 | { | |
3060 | u32 reg; | |
3061 | unsigned int tx_pin; | |
a89534ed | 3062 | u8 bbp, rfcsr; |
f4450616 | 3063 | |
97aa03f1 GJ |
3064 | info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, |
3065 | info->default_power1); | |
3066 | info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, | |
3067 | info->default_power2); | |
c0a14369 GJ |
3068 | if (rt2x00dev->default_ant.tx_chain_num > 2) |
3069 | info->default_power3 = | |
3070 | rt2800_txpower_to_dev(rt2x00dev, rf->channel, | |
3071 | info->default_power3); | |
46323e11 | 3072 | |
5aa57015 GW |
3073 | switch (rt2x00dev->chip.rf) { |
3074 | case RF2020: | |
3075 | case RF3020: | |
3076 | case RF3021: | |
3077 | case RF3022: | |
3078 | case RF3320: | |
06855ef4 | 3079 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); |
5aa57015 GW |
3080 | break; |
3081 | case RF3052: | |
872834df | 3082 | rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); |
5aa57015 | 3083 | break; |
f42b0465 GJ |
3084 | case RF3053: |
3085 | rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); | |
3086 | break; | |
a89534ed WH |
3087 | case RF3290: |
3088 | rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); | |
3089 | break; | |
03839951 DG |
3090 | case RF3322: |
3091 | rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); | |
3092 | break; | |
ccf91bd6 | 3093 | case RF5360: |
5aa57015 | 3094 | case RF5370: |
2ed71884 | 3095 | case RF5372: |
5aa57015 | 3096 | case RF5390: |
cff3d1f0 | 3097 | case RF5392: |
adde5882 | 3098 | rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); |
5aa57015 | 3099 | break; |
8f821098 SG |
3100 | case RF5592: |
3101 | rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); | |
3102 | break; | |
5aa57015 | 3103 | default: |
06855ef4 | 3104 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); |
5aa57015 | 3105 | } |
f4450616 | 3106 | |
a89534ed | 3107 | if (rt2x00_rf(rt2x00dev, RF3290) || |
03839951 | 3108 | rt2x00_rf(rt2x00dev, RF3322) || |
a89534ed WH |
3109 | rt2x00_rf(rt2x00dev, RF5360) || |
3110 | rt2x00_rf(rt2x00dev, RF5370) || | |
3111 | rt2x00_rf(rt2x00dev, RF5372) || | |
3112 | rt2x00_rf(rt2x00dev, RF5390) || | |
3113 | rt2x00_rf(rt2x00dev, RF5392)) { | |
3114 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
3115 | rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); | |
3116 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); | |
3117 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3118 | ||
3119 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
d6d82020 | 3120 | rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); |
a89534ed WH |
3121 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); |
3122 | } | |
3123 | ||
f4450616 BZ |
3124 | /* |
3125 | * Change BBP settings | |
3126 | */ | |
03839951 DG |
3127 | if (rt2x00_rt(rt2x00dev, RT3352)) { |
3128 | rt2800_bbp_write(rt2x00dev, 27, 0x0); | |
cf193f6d | 3129 | rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); |
03839951 | 3130 | rt2800_bbp_write(rt2x00dev, 27, 0x20); |
cf193f6d | 3131 | rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); |
f42b0465 GJ |
3132 | } else if (rt2x00_rt(rt2x00dev, RT3593)) { |
3133 | if (rf->channel > 14) { | |
3134 | /* Disable CCK Packet detection on 5GHz */ | |
3135 | rt2800_bbp_write(rt2x00dev, 70, 0x00); | |
3136 | } else { | |
3137 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
3138 | } | |
3139 | ||
3140 | if (conf_is_ht40(conf)) | |
3141 | rt2800_bbp_write(rt2x00dev, 105, 0x04); | |
3142 | else | |
3143 | rt2800_bbp_write(rt2x00dev, 105, 0x34); | |
3144 | ||
3145 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
3146 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
3147 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
3148 | rt2800_bbp_write(rt2x00dev, 77, 0x98); | |
03839951 DG |
3149 | } else { |
3150 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
3151 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
3152 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
3153 | rt2800_bbp_write(rt2x00dev, 86, 0); | |
3154 | } | |
f4450616 BZ |
3155 | |
3156 | if (rf->channel <= 14) { | |
2ed71884 | 3157 | if (!rt2x00_rt(rt2x00dev, RT5390) && |
e6d227b9 | 3158 | !rt2x00_rt(rt2x00dev, RT5392)) { |
7dab73b3 ID |
3159 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, |
3160 | &rt2x00dev->cap_flags)) { | |
adde5882 GJ |
3161 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
3162 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
3163 | } else { | |
f42b0465 GJ |
3164 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3165 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
3166 | else | |
3167 | rt2800_bbp_write(rt2x00dev, 82, 0x84); | |
adde5882 GJ |
3168 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
3169 | } | |
f42b0465 GJ |
3170 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3171 | rt2800_bbp_write(rt2x00dev, 83, 0x8a); | |
f4450616 | 3172 | } |
f42b0465 | 3173 | |
f4450616 | 3174 | } else { |
872834df GW |
3175 | if (rt2x00_rt(rt2x00dev, RT3572)) |
3176 | rt2800_bbp_write(rt2x00dev, 82, 0x94); | |
f42b0465 GJ |
3177 | else if (rt2x00_rt(rt2x00dev, RT3593)) |
3178 | rt2800_bbp_write(rt2x00dev, 82, 0x82); | |
872834df GW |
3179 | else |
3180 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | |
f4450616 | 3181 | |
f42b0465 GJ |
3182 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3183 | rt2800_bbp_write(rt2x00dev, 83, 0x9a); | |
3184 | ||
7dab73b3 | 3185 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) |
f4450616 BZ |
3186 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
3187 | else | |
3188 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
3189 | } | |
3190 | ||
3191 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); | |
a21ee724 | 3192 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
3193 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); |
3194 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); | |
3195 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); | |
3196 | ||
872834df GW |
3197 | if (rt2x00_rt(rt2x00dev, RT3572)) |
3198 | rt2800_rfcsr_write(rt2x00dev, 8, 0); | |
3199 | ||
f4450616 BZ |
3200 | tx_pin = 0; |
3201 | ||
bb16d488 GJ |
3202 | switch (rt2x00dev->default_ant.tx_chain_num) { |
3203 | case 3: | |
3204 | /* Turn on tertiary PAs */ | |
3205 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, | |
3206 | rf->channel > 14); | |
3207 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, | |
3208 | rf->channel <= 14); | |
3209 | /* fall-through */ | |
3210 | case 2: | |
3211 | /* Turn on secondary PAs */ | |
65f31b5e GW |
3212 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, |
3213 | rf->channel > 14); | |
3214 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, | |
3215 | rf->channel <= 14); | |
bb16d488 GJ |
3216 | /* fall-through */ |
3217 | case 1: | |
3218 | /* Turn on primary PAs */ | |
3219 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, | |
3220 | rf->channel > 14); | |
3221 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | |
3222 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); | |
3223 | else | |
3224 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, | |
3225 | rf->channel <= 14); | |
3226 | break; | |
f4450616 BZ |
3227 | } |
3228 | ||
bb16d488 GJ |
3229 | switch (rt2x00dev->default_ant.rx_chain_num) { |
3230 | case 3: | |
3231 | /* Turn on tertiary LNAs */ | |
3232 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); | |
3233 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); | |
3234 | /* fall-through */ | |
3235 | case 2: | |
3236 | /* Turn on secondary LNAs */ | |
f4450616 BZ |
3237 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); |
3238 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); | |
bb16d488 GJ |
3239 | /* fall-through */ |
3240 | case 1: | |
3241 | /* Turn on primary LNAs */ | |
3242 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); | |
3243 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); | |
3244 | break; | |
f4450616 BZ |
3245 | } |
3246 | ||
f4450616 BZ |
3247 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); |
3248 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); | |
f4450616 BZ |
3249 | |
3250 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
3251 | ||
872834df GW |
3252 | if (rt2x00_rt(rt2x00dev, RT3572)) |
3253 | rt2800_rfcsr_write(rt2x00dev, 8, 0x80); | |
3254 | ||
f42b0465 GJ |
3255 | if (rt2x00_rt(rt2x00dev, RT3593)) { |
3256 | if (rt2x00_is_usb(rt2x00dev)) { | |
3257 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); | |
3258 | ||
3259 | /* Band selection. GPIO #8 controls all paths */ | |
3260 | rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); | |
3261 | if (rf->channel <= 14) | |
3262 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); | |
3263 | else | |
3264 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); | |
3265 | ||
3266 | rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); | |
3267 | rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); | |
3268 | ||
3269 | /* LNA PE control. | |
3270 | * GPIO #4 controls PE0 and PE1, | |
3271 | * GPIO #7 controls PE2 | |
3272 | */ | |
3273 | rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); | |
3274 | rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); | |
3275 | ||
3276 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | |
3277 | } | |
3278 | ||
3279 | /* AGC init */ | |
3280 | if (rf->channel <= 14) | |
3281 | reg = 0x1c + 2 * rt2x00dev->lna_gain; | |
3282 | else | |
3283 | reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); | |
3284 | ||
3285 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); | |
3286 | ||
3287 | usleep_range(1000, 1500); | |
3288 | } | |
3289 | ||
6803141b SG |
3290 | if (rt2x00_rt(rt2x00dev, RT5592)) { |
3291 | rt2800_bbp_write(rt2x00dev, 195, 141); | |
3292 | rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); | |
3293 | ||
8ba0ebf3 SG |
3294 | /* AGC init */ |
3295 | reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; | |
3296 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); | |
3297 | ||
8756130b | 3298 | rt2800_iq_calibrate(rt2x00dev, rf->channel); |
6803141b SG |
3299 | } |
3300 | ||
f4450616 BZ |
3301 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
3302 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); | |
3303 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
3304 | ||
3305 | rt2800_bbp_read(rt2x00dev, 3, &bbp); | |
a21ee724 | 3306 | rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
3307 | rt2800_bbp_write(rt2x00dev, 3, bbp); |
3308 | ||
8d0c9b65 | 3309 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
f4450616 BZ |
3310 | if (conf_is_ht40(conf)) { |
3311 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); | |
3312 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
3313 | rt2800_bbp_write(rt2x00dev, 73, 0x16); | |
3314 | } else { | |
3315 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
3316 | rt2800_bbp_write(rt2x00dev, 70, 0x08); | |
3317 | rt2800_bbp_write(rt2x00dev, 73, 0x11); | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | msleep(1); | |
977206d7 HS |
3322 | |
3323 | /* | |
3324 | * Clear channel statistic counters | |
3325 | */ | |
3326 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); | |
3327 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); | |
3328 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); | |
03839951 DG |
3329 | |
3330 | /* | |
3331 | * Clear update flag | |
3332 | */ | |
3333 | if (rt2x00_rt(rt2x00dev, RT3352)) { | |
3334 | rt2800_bbp_read(rt2x00dev, 49, &bbp); | |
3335 | rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); | |
3336 | rt2800_bbp_write(rt2x00dev, 49, bbp); | |
3337 | } | |
f4450616 BZ |
3338 | } |
3339 | ||
9e33a355 HS |
3340 | static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) |
3341 | { | |
3342 | u8 tssi_bounds[9]; | |
3343 | u8 current_tssi; | |
3344 | u16 eeprom; | |
3345 | u8 step; | |
3346 | int i; | |
3347 | ||
3348 | /* | |
3349 | * Read TSSI boundaries for temperature compensation from | |
3350 | * the EEPROM. | |
3351 | * | |
3352 | * Array idx 0 1 2 3 4 5 6 7 8 | |
3353 | * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 | |
3354 | * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 | |
3355 | */ | |
3356 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
3e38d3da | 3357 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); |
9e33a355 HS |
3358 | tssi_bounds[0] = rt2x00_get_field16(eeprom, |
3359 | EEPROM_TSSI_BOUND_BG1_MINUS4); | |
3360 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
3361 | EEPROM_TSSI_BOUND_BG1_MINUS3); | |
3362 | ||
3e38d3da | 3363 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); |
9e33a355 HS |
3364 | tssi_bounds[2] = rt2x00_get_field16(eeprom, |
3365 | EEPROM_TSSI_BOUND_BG2_MINUS2); | |
3366 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
3367 | EEPROM_TSSI_BOUND_BG2_MINUS1); | |
3368 | ||
3e38d3da | 3369 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); |
9e33a355 HS |
3370 | tssi_bounds[4] = rt2x00_get_field16(eeprom, |
3371 | EEPROM_TSSI_BOUND_BG3_REF); | |
3372 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
3373 | EEPROM_TSSI_BOUND_BG3_PLUS1); | |
3374 | ||
3e38d3da | 3375 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); |
9e33a355 HS |
3376 | tssi_bounds[6] = rt2x00_get_field16(eeprom, |
3377 | EEPROM_TSSI_BOUND_BG4_PLUS2); | |
3378 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
3379 | EEPROM_TSSI_BOUND_BG4_PLUS3); | |
3380 | ||
3e38d3da | 3381 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); |
9e33a355 HS |
3382 | tssi_bounds[8] = rt2x00_get_field16(eeprom, |
3383 | EEPROM_TSSI_BOUND_BG5_PLUS4); | |
3384 | ||
3385 | step = rt2x00_get_field16(eeprom, | |
3386 | EEPROM_TSSI_BOUND_BG5_AGC_STEP); | |
3387 | } else { | |
3e38d3da | 3388 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); |
9e33a355 HS |
3389 | tssi_bounds[0] = rt2x00_get_field16(eeprom, |
3390 | EEPROM_TSSI_BOUND_A1_MINUS4); | |
3391 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
3392 | EEPROM_TSSI_BOUND_A1_MINUS3); | |
3393 | ||
3e38d3da | 3394 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); |
9e33a355 HS |
3395 | tssi_bounds[2] = rt2x00_get_field16(eeprom, |
3396 | EEPROM_TSSI_BOUND_A2_MINUS2); | |
3397 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
3398 | EEPROM_TSSI_BOUND_A2_MINUS1); | |
3399 | ||
3e38d3da | 3400 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); |
9e33a355 HS |
3401 | tssi_bounds[4] = rt2x00_get_field16(eeprom, |
3402 | EEPROM_TSSI_BOUND_A3_REF); | |
3403 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
3404 | EEPROM_TSSI_BOUND_A3_PLUS1); | |
3405 | ||
3e38d3da | 3406 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); |
9e33a355 HS |
3407 | tssi_bounds[6] = rt2x00_get_field16(eeprom, |
3408 | EEPROM_TSSI_BOUND_A4_PLUS2); | |
3409 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
3410 | EEPROM_TSSI_BOUND_A4_PLUS3); | |
3411 | ||
3e38d3da | 3412 | rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); |
9e33a355 HS |
3413 | tssi_bounds[8] = rt2x00_get_field16(eeprom, |
3414 | EEPROM_TSSI_BOUND_A5_PLUS4); | |
3415 | ||
3416 | step = rt2x00_get_field16(eeprom, | |
3417 | EEPROM_TSSI_BOUND_A5_AGC_STEP); | |
3418 | } | |
3419 | ||
3420 | /* | |
3421 | * Check if temperature compensation is supported. | |
3422 | */ | |
bf7e1abe | 3423 | if (tssi_bounds[4] == 0xff || step == 0xff) |
9e33a355 HS |
3424 | return 0; |
3425 | ||
3426 | /* | |
3427 | * Read current TSSI (BBP 49). | |
3428 | */ | |
3429 | rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); | |
3430 | ||
3431 | /* | |
3432 | * Compare TSSI value (BBP49) with the compensation boundaries | |
3433 | * from the EEPROM and increase or decrease tx power. | |
3434 | */ | |
3435 | for (i = 0; i <= 3; i++) { | |
3436 | if (current_tssi > tssi_bounds[i]) | |
3437 | break; | |
3438 | } | |
3439 | ||
3440 | if (i == 4) { | |
3441 | for (i = 8; i >= 5; i--) { | |
3442 | if (current_tssi < tssi_bounds[i]) | |
3443 | break; | |
3444 | } | |
3445 | } | |
3446 | ||
3447 | return (i - 4) * step; | |
3448 | } | |
3449 | ||
e90c54b2 RJH |
3450 | static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, |
3451 | enum ieee80211_band band) | |
3452 | { | |
3453 | u16 eeprom; | |
3454 | u8 comp_en; | |
3455 | u8 comp_type; | |
75faae8b | 3456 | int comp_value = 0; |
e90c54b2 | 3457 | |
3e38d3da | 3458 | rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); |
e90c54b2 | 3459 | |
75faae8b HS |
3460 | /* |
3461 | * HT40 compensation not required. | |
3462 | */ | |
3463 | if (eeprom == 0xffff || | |
3464 | !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
e90c54b2 RJH |
3465 | return 0; |
3466 | ||
3467 | if (band == IEEE80211_BAND_2GHZ) { | |
3468 | comp_en = rt2x00_get_field16(eeprom, | |
3469 | EEPROM_TXPOWER_DELTA_ENABLE_2G); | |
3470 | if (comp_en) { | |
3471 | comp_type = rt2x00_get_field16(eeprom, | |
3472 | EEPROM_TXPOWER_DELTA_TYPE_2G); | |
3473 | comp_value = rt2x00_get_field16(eeprom, | |
3474 | EEPROM_TXPOWER_DELTA_VALUE_2G); | |
3475 | if (!comp_type) | |
3476 | comp_value = -comp_value; | |
3477 | } | |
3478 | } else { | |
3479 | comp_en = rt2x00_get_field16(eeprom, | |
3480 | EEPROM_TXPOWER_DELTA_ENABLE_5G); | |
3481 | if (comp_en) { | |
3482 | comp_type = rt2x00_get_field16(eeprom, | |
3483 | EEPROM_TXPOWER_DELTA_TYPE_5G); | |
3484 | comp_value = rt2x00_get_field16(eeprom, | |
3485 | EEPROM_TXPOWER_DELTA_VALUE_5G); | |
3486 | if (!comp_type) | |
3487 | comp_value = -comp_value; | |
3488 | } | |
3489 | } | |
3490 | ||
3491 | return comp_value; | |
3492 | } | |
3493 | ||
1e4cf249 SG |
3494 | static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, |
3495 | int power_level, int max_power) | |
3496 | { | |
3497 | int delta; | |
3498 | ||
3499 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) | |
3500 | return 0; | |
3501 | ||
3502 | /* | |
3503 | * XXX: We don't know the maximum transmit power of our hardware since | |
3504 | * the EEPROM doesn't expose it. We only know that we are calibrated | |
3505 | * to 100% tx power. | |
3506 | * | |
3507 | * Hence, we assume the regulatory limit that cfg80211 calulated for | |
3508 | * the current channel is our maximum and if we are requested to lower | |
3509 | * the value we just reduce our tx power accordingly. | |
3510 | */ | |
3511 | delta = power_level - max_power; | |
3512 | return min(delta, 0); | |
3513 | } | |
3514 | ||
fa71a160 HS |
3515 | static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, |
3516 | enum ieee80211_band band, int power_level, | |
3517 | u8 txpower, int delta) | |
e90c54b2 | 3518 | { |
e90c54b2 RJH |
3519 | u16 eeprom; |
3520 | u8 criterion; | |
3521 | u8 eirp_txpower; | |
3522 | u8 eirp_txpower_criterion; | |
3523 | u8 reg_limit; | |
e90c54b2 | 3524 | |
34542ff5 GJ |
3525 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3526 | return min_t(u8, txpower, 0xc); | |
3527 | ||
7dab73b3 | 3528 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) { |
e90c54b2 RJH |
3529 | /* |
3530 | * Check if eirp txpower exceed txpower_limit. | |
3531 | * We use OFDM 6M as criterion and its eirp txpower | |
3532 | * is stored at EEPROM_EIRP_MAX_TX_POWER. | |
3533 | * .11b data rate need add additional 4dbm | |
3534 | * when calculating eirp txpower. | |
3535 | */ | |
022138ca GJ |
3536 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, |
3537 | 1, &eeprom); | |
d9bceaeb SG |
3538 | criterion = rt2x00_get_field16(eeprom, |
3539 | EEPROM_TXPOWER_BYRATE_RATE0); | |
e90c54b2 | 3540 | |
3e38d3da | 3541 | rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, |
d9bceaeb | 3542 | &eeprom); |
e90c54b2 RJH |
3543 | |
3544 | if (band == IEEE80211_BAND_2GHZ) | |
3545 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
3546 | EEPROM_EIRP_MAX_TX_POWER_2GHZ); | |
3547 | else | |
3548 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
3549 | EEPROM_EIRP_MAX_TX_POWER_5GHZ); | |
3550 | ||
3551 | eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + | |
2af242e1 | 3552 | (is_rate_b ? 4 : 0) + delta; |
e90c54b2 RJH |
3553 | |
3554 | reg_limit = (eirp_txpower > power_level) ? | |
3555 | (eirp_txpower - power_level) : 0; | |
3556 | } else | |
3557 | reg_limit = 0; | |
3558 | ||
19f3fa24 SG |
3559 | txpower = max(0, txpower + delta - reg_limit); |
3560 | return min_t(u8, txpower, 0xc); | |
e90c54b2 RJH |
3561 | } |
3562 | ||
34542ff5 GJ |
3563 | |
3564 | enum { | |
3565 | TX_PWR_CFG_0_IDX, | |
3566 | TX_PWR_CFG_1_IDX, | |
3567 | TX_PWR_CFG_2_IDX, | |
3568 | TX_PWR_CFG_3_IDX, | |
3569 | TX_PWR_CFG_4_IDX, | |
3570 | TX_PWR_CFG_5_IDX, | |
3571 | TX_PWR_CFG_6_IDX, | |
3572 | TX_PWR_CFG_7_IDX, | |
3573 | TX_PWR_CFG_8_IDX, | |
3574 | TX_PWR_CFG_9_IDX, | |
3575 | TX_PWR_CFG_0_EXT_IDX, | |
3576 | TX_PWR_CFG_1_EXT_IDX, | |
3577 | TX_PWR_CFG_2_EXT_IDX, | |
3578 | TX_PWR_CFG_3_EXT_IDX, | |
3579 | TX_PWR_CFG_4_EXT_IDX, | |
3580 | TX_PWR_CFG_IDX_COUNT, | |
3581 | }; | |
3582 | ||
3583 | static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, | |
3584 | struct ieee80211_channel *chan, | |
3585 | int power_level) | |
3586 | { | |
3587 | u8 txpower; | |
3588 | u16 eeprom; | |
3589 | u32 regs[TX_PWR_CFG_IDX_COUNT]; | |
3590 | unsigned int offset; | |
3591 | enum ieee80211_band band = chan->band; | |
3592 | int delta; | |
3593 | int i; | |
3594 | ||
3595 | memset(regs, '\0', sizeof(regs)); | |
3596 | ||
3597 | /* TODO: adapt TX power reduction from the rt28xx code */ | |
3598 | ||
3599 | /* calculate temperature compensation delta */ | |
3600 | delta = rt2800_get_gain_calibration_delta(rt2x00dev); | |
3601 | ||
3602 | if (band == IEEE80211_BAND_5GHZ) | |
3603 | offset = 16; | |
3604 | else | |
3605 | offset = 0; | |
3606 | ||
3607 | if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
3608 | offset += 8; | |
3609 | ||
3610 | /* read the next four txpower values */ | |
3611 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3612 | offset, &eeprom); | |
3613 | ||
3614 | /* CCK 1MBS,2MBS */ | |
3615 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3616 | txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, | |
3617 | txpower, delta); | |
3618 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3619 | TX_PWR_CFG_0_CCK1_CH0, txpower); | |
3620 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3621 | TX_PWR_CFG_0_CCK1_CH1, txpower); | |
3622 | rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], | |
3623 | TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); | |
3624 | ||
3625 | /* CCK 5.5MBS,11MBS */ | |
3626 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3627 | txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, | |
3628 | txpower, delta); | |
3629 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3630 | TX_PWR_CFG_0_CCK5_CH0, txpower); | |
3631 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3632 | TX_PWR_CFG_0_CCK5_CH1, txpower); | |
3633 | rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], | |
3634 | TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); | |
3635 | ||
3636 | /* OFDM 6MBS,9MBS */ | |
3637 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3638 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3639 | txpower, delta); | |
3640 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3641 | TX_PWR_CFG_0_OFDM6_CH0, txpower); | |
3642 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3643 | TX_PWR_CFG_0_OFDM6_CH1, txpower); | |
3644 | rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], | |
3645 | TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); | |
3646 | ||
3647 | /* OFDM 12MBS,18MBS */ | |
3648 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); | |
3649 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3650 | txpower, delta); | |
3651 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3652 | TX_PWR_CFG_0_OFDM12_CH0, txpower); | |
3653 | rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], | |
3654 | TX_PWR_CFG_0_OFDM12_CH1, txpower); | |
3655 | rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], | |
3656 | TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); | |
3657 | ||
3658 | /* read the next four txpower values */ | |
3659 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3660 | offset + 1, &eeprom); | |
3661 | ||
3662 | /* OFDM 24MBS,36MBS */ | |
3663 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3664 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3665 | txpower, delta); | |
3666 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3667 | TX_PWR_CFG_1_OFDM24_CH0, txpower); | |
3668 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3669 | TX_PWR_CFG_1_OFDM24_CH1, txpower); | |
3670 | rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], | |
3671 | TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); | |
3672 | ||
3673 | /* OFDM 48MBS */ | |
3674 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3675 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3676 | txpower, delta); | |
3677 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3678 | TX_PWR_CFG_1_OFDM48_CH0, txpower); | |
3679 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3680 | TX_PWR_CFG_1_OFDM48_CH1, txpower); | |
3681 | rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], | |
3682 | TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); | |
3683 | ||
3684 | /* OFDM 54MBS */ | |
3685 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3686 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3687 | txpower, delta); | |
3688 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3689 | TX_PWR_CFG_7_OFDM54_CH0, txpower); | |
3690 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3691 | TX_PWR_CFG_7_OFDM54_CH1, txpower); | |
3692 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3693 | TX_PWR_CFG_7_OFDM54_CH2, txpower); | |
3694 | ||
3695 | /* read the next four txpower values */ | |
3696 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3697 | offset + 2, &eeprom); | |
3698 | ||
3699 | /* MCS 0,1 */ | |
3700 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3701 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3702 | txpower, delta); | |
3703 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3704 | TX_PWR_CFG_1_MCS0_CH0, txpower); | |
3705 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3706 | TX_PWR_CFG_1_MCS0_CH1, txpower); | |
3707 | rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], | |
3708 | TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); | |
3709 | ||
3710 | /* MCS 2,3 */ | |
3711 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3712 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3713 | txpower, delta); | |
3714 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3715 | TX_PWR_CFG_1_MCS2_CH0, txpower); | |
3716 | rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], | |
3717 | TX_PWR_CFG_1_MCS2_CH1, txpower); | |
3718 | rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], | |
3719 | TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); | |
3720 | ||
3721 | /* MCS 4,5 */ | |
3722 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3723 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3724 | txpower, delta); | |
3725 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3726 | TX_PWR_CFG_2_MCS4_CH0, txpower); | |
3727 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3728 | TX_PWR_CFG_2_MCS4_CH1, txpower); | |
3729 | rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], | |
3730 | TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); | |
3731 | ||
3732 | /* MCS 6 */ | |
3733 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); | |
3734 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3735 | txpower, delta); | |
3736 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3737 | TX_PWR_CFG_2_MCS6_CH0, txpower); | |
3738 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3739 | TX_PWR_CFG_2_MCS6_CH1, txpower); | |
3740 | rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], | |
3741 | TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); | |
3742 | ||
3743 | /* read the next four txpower values */ | |
3744 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3745 | offset + 3, &eeprom); | |
3746 | ||
3747 | /* MCS 7 */ | |
3748 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3749 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3750 | txpower, delta); | |
3751 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3752 | TX_PWR_CFG_7_MCS7_CH0, txpower); | |
3753 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3754 | TX_PWR_CFG_7_MCS7_CH1, txpower); | |
3755 | rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], | |
3756 | TX_PWR_CFG_7_MCS7_CH2, txpower); | |
3757 | ||
3758 | /* MCS 8,9 */ | |
3759 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3760 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3761 | txpower, delta); | |
3762 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3763 | TX_PWR_CFG_2_MCS8_CH0, txpower); | |
3764 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3765 | TX_PWR_CFG_2_MCS8_CH1, txpower); | |
3766 | rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], | |
3767 | TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); | |
3768 | ||
3769 | /* MCS 10,11 */ | |
3770 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3771 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3772 | txpower, delta); | |
3773 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3774 | TX_PWR_CFG_2_MCS10_CH0, txpower); | |
3775 | rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], | |
3776 | TX_PWR_CFG_2_MCS10_CH1, txpower); | |
3777 | rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], | |
3778 | TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); | |
3779 | ||
3780 | /* MCS 12,13 */ | |
3781 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); | |
3782 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3783 | txpower, delta); | |
3784 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3785 | TX_PWR_CFG_3_MCS12_CH0, txpower); | |
3786 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3787 | TX_PWR_CFG_3_MCS12_CH1, txpower); | |
3788 | rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], | |
3789 | TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); | |
3790 | ||
3791 | /* read the next four txpower values */ | |
3792 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3793 | offset + 4, &eeprom); | |
3794 | ||
3795 | /* MCS 14 */ | |
3796 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3797 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3798 | txpower, delta); | |
3799 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3800 | TX_PWR_CFG_3_MCS14_CH0, txpower); | |
3801 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3802 | TX_PWR_CFG_3_MCS14_CH1, txpower); | |
3803 | rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], | |
3804 | TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); | |
3805 | ||
3806 | /* MCS 15 */ | |
3807 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3808 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3809 | txpower, delta); | |
3810 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3811 | TX_PWR_CFG_8_MCS15_CH0, txpower); | |
3812 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3813 | TX_PWR_CFG_8_MCS15_CH1, txpower); | |
3814 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3815 | TX_PWR_CFG_8_MCS15_CH2, txpower); | |
3816 | ||
3817 | /* MCS 16,17 */ | |
3818 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3819 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3820 | txpower, delta); | |
3821 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3822 | TX_PWR_CFG_5_MCS16_CH0, txpower); | |
3823 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3824 | TX_PWR_CFG_5_MCS16_CH1, txpower); | |
3825 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3826 | TX_PWR_CFG_5_MCS16_CH2, txpower); | |
3827 | ||
3828 | /* MCS 18,19 */ | |
3829 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); | |
3830 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3831 | txpower, delta); | |
3832 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3833 | TX_PWR_CFG_5_MCS18_CH0, txpower); | |
3834 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3835 | TX_PWR_CFG_5_MCS18_CH1, txpower); | |
3836 | rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], | |
3837 | TX_PWR_CFG_5_MCS18_CH2, txpower); | |
3838 | ||
3839 | /* read the next four txpower values */ | |
3840 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3841 | offset + 5, &eeprom); | |
3842 | ||
3843 | /* MCS 20,21 */ | |
3844 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3845 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3846 | txpower, delta); | |
3847 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3848 | TX_PWR_CFG_6_MCS20_CH0, txpower); | |
3849 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3850 | TX_PWR_CFG_6_MCS20_CH1, txpower); | |
3851 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3852 | TX_PWR_CFG_6_MCS20_CH2, txpower); | |
3853 | ||
3854 | /* MCS 22 */ | |
3855 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3856 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3857 | txpower, delta); | |
3858 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3859 | TX_PWR_CFG_6_MCS22_CH0, txpower); | |
3860 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3861 | TX_PWR_CFG_6_MCS22_CH1, txpower); | |
3862 | rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], | |
3863 | TX_PWR_CFG_6_MCS22_CH2, txpower); | |
3864 | ||
3865 | /* MCS 23 */ | |
3866 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3867 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3868 | txpower, delta); | |
3869 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3870 | TX_PWR_CFG_8_MCS23_CH0, txpower); | |
3871 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3872 | TX_PWR_CFG_8_MCS23_CH1, txpower); | |
3873 | rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], | |
3874 | TX_PWR_CFG_8_MCS23_CH2, txpower); | |
3875 | ||
3876 | /* read the next four txpower values */ | |
3877 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3878 | offset + 6, &eeprom); | |
3879 | ||
3880 | /* STBC, MCS 0,1 */ | |
3881 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3882 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3883 | txpower, delta); | |
3884 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3885 | TX_PWR_CFG_3_STBC0_CH0, txpower); | |
3886 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3887 | TX_PWR_CFG_3_STBC0_CH1, txpower); | |
3888 | rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], | |
3889 | TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); | |
3890 | ||
3891 | /* STBC, MCS 2,3 */ | |
3892 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); | |
3893 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3894 | txpower, delta); | |
3895 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3896 | TX_PWR_CFG_3_STBC2_CH0, txpower); | |
3897 | rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], | |
3898 | TX_PWR_CFG_3_STBC2_CH1, txpower); | |
3899 | rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], | |
3900 | TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); | |
3901 | ||
3902 | /* STBC, MCS 4,5 */ | |
3903 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); | |
3904 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3905 | txpower, delta); | |
3906 | rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); | |
3907 | rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); | |
3908 | rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, | |
3909 | txpower); | |
3910 | ||
3911 | /* STBC, MCS 6 */ | |
3912 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); | |
3913 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3914 | txpower, delta); | |
3915 | rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); | |
3916 | rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); | |
3917 | rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, | |
3918 | txpower); | |
3919 | ||
3920 | /* read the next four txpower values */ | |
3921 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, | |
3922 | offset + 7, &eeprom); | |
3923 | ||
3924 | /* STBC, MCS 7 */ | |
3925 | txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); | |
3926 | txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, | |
3927 | txpower, delta); | |
3928 | rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], | |
3929 | TX_PWR_CFG_9_STBC7_CH0, txpower); | |
3930 | rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], | |
3931 | TX_PWR_CFG_9_STBC7_CH1, txpower); | |
3932 | rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], | |
3933 | TX_PWR_CFG_9_STBC7_CH2, txpower); | |
3934 | ||
3935 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); | |
3936 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); | |
3937 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); | |
3938 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); | |
3939 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); | |
3940 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); | |
3941 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); | |
3942 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); | |
3943 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); | |
3944 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); | |
3945 | ||
3946 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, | |
3947 | regs[TX_PWR_CFG_0_EXT_IDX]); | |
3948 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, | |
3949 | regs[TX_PWR_CFG_1_EXT_IDX]); | |
3950 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, | |
3951 | regs[TX_PWR_CFG_2_EXT_IDX]); | |
3952 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, | |
3953 | regs[TX_PWR_CFG_3_EXT_IDX]); | |
3954 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, | |
3955 | regs[TX_PWR_CFG_4_EXT_IDX]); | |
3956 | ||
3957 | for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) | |
3958 | rt2x00_dbg(rt2x00dev, | |
3959 | "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", | |
3960 | (band == IEEE80211_BAND_5GHZ) ? '5' : '2', | |
3961 | (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? | |
3962 | '4' : '2', | |
3963 | (i > TX_PWR_CFG_9_IDX) ? | |
3964 | (i - TX_PWR_CFG_9_IDX - 1) : i, | |
3965 | (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", | |
3966 | (unsigned long) regs[i]); | |
3967 | } | |
3968 | ||
7a66205a SG |
3969 | /* |
3970 | * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and | |
3971 | * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, | |
3972 | * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power | |
3973 | * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. | |
3974 | * Reference per rate transmit power values are located in the EEPROM at | |
3975 | * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to | |
3976 | * current conditions (i.e. band, bandwidth, temperature, user settings). | |
3977 | */ | |
34542ff5 GJ |
3978 | static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, |
3979 | struct ieee80211_channel *chan, | |
3980 | int power_level) | |
f4450616 | 3981 | { |
cee2c731 | 3982 | u8 txpower, r1; |
5e846004 | 3983 | u16 eeprom; |
cee2c731 SG |
3984 | u32 reg, offset; |
3985 | int i, is_rate_b, delta, power_ctrl; | |
146c3b0c | 3986 | enum ieee80211_band band = chan->band; |
2af242e1 HS |
3987 | |
3988 | /* | |
7a66205a SG |
3989 | * Calculate HT40 compensation. For 40MHz we need to add or subtract |
3990 | * value read from EEPROM (different for 2GHz and for 5GHz). | |
2af242e1 HS |
3991 | */ |
3992 | delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); | |
f4450616 | 3993 | |
9e33a355 | 3994 | /* |
7a66205a SG |
3995 | * Calculate temperature compensation. Depends on measurement of current |
3996 | * TSSI (Transmitter Signal Strength Indication) we know TX power (due | |
3997 | * to temperature or maybe other factors) is smaller or bigger than | |
3998 | * expected. We adjust it, based on TSSI reference and boundaries values | |
3999 | * provided in EEPROM. | |
9e33a355 HS |
4000 | */ |
4001 | delta += rt2800_get_gain_calibration_delta(rt2x00dev); | |
f4450616 | 4002 | |
1e4cf249 | 4003 | /* |
7a66205a SG |
4004 | * Decrease power according to user settings, on devices with unknown |
4005 | * maximum tx power. For other devices we take user power_level into | |
4006 | * consideration on rt2800_compensate_txpower(). | |
1e4cf249 SG |
4007 | */ |
4008 | delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, | |
4009 | chan->max_power); | |
4010 | ||
5e846004 | 4011 | /* |
cee2c731 SG |
4012 | * BBP_R1 controls TX power for all rates, it allow to set the following |
4013 | * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. | |
4014 | * | |
4015 | * TODO: we do not use +6 dBm option to do not increase power beyond | |
4016 | * regulatory limit, however this could be utilized for devices with | |
4017 | * CAPABILITY_POWER_LIMIT. | |
8c8d2017 SG |
4018 | * |
4019 | * TODO: add different temperature compensation code for RT3290 & RT5390 | |
4020 | * to allow to use BBP_R1 for those chips. | |
4021 | */ | |
4022 | if (!rt2x00_rt(rt2x00dev, RT3290) && | |
4023 | !rt2x00_rt(rt2x00dev, RT5390)) { | |
4024 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
4025 | if (delta <= -12) { | |
4026 | power_ctrl = 2; | |
4027 | delta += 12; | |
4028 | } else if (delta <= -6) { | |
4029 | power_ctrl = 1; | |
4030 | delta += 6; | |
4031 | } else { | |
4032 | power_ctrl = 0; | |
4033 | } | |
4034 | rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); | |
4035 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
cee2c731 | 4036 | } |
8c8d2017 | 4037 | |
5e846004 HS |
4038 | offset = TX_PWR_CFG_0; |
4039 | ||
4040 | for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { | |
4041 | /* just to be safe */ | |
4042 | if (offset > TX_PWR_CFG_4) | |
4043 | break; | |
4044 | ||
4045 | rt2800_register_read(rt2x00dev, offset, ®); | |
4046 | ||
4047 | /* read the next four txpower values */ | |
022138ca GJ |
4048 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, |
4049 | i, &eeprom); | |
5e846004 | 4050 | |
e90c54b2 RJH |
4051 | is_rate_b = i ? 0 : 1; |
4052 | /* | |
4053 | * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, | |
5e846004 | 4054 | * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, |
e90c54b2 RJH |
4055 | * TX_PWR_CFG_4: unknown |
4056 | */ | |
5e846004 HS |
4057 | txpower = rt2x00_get_field16(eeprom, |
4058 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 4059 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4060 | power_level, txpower, delta); |
e90c54b2 | 4061 | rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); |
5e846004 | 4062 | |
e90c54b2 RJH |
4063 | /* |
4064 | * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, | |
5e846004 | 4065 | * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, |
e90c54b2 RJH |
4066 | * TX_PWR_CFG_4: unknown |
4067 | */ | |
5e846004 HS |
4068 | txpower = rt2x00_get_field16(eeprom, |
4069 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 4070 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4071 | power_level, txpower, delta); |
e90c54b2 | 4072 | rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); |
5e846004 | 4073 | |
e90c54b2 RJH |
4074 | /* |
4075 | * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, | |
5e846004 | 4076 | * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, |
e90c54b2 RJH |
4077 | * TX_PWR_CFG_4: unknown |
4078 | */ | |
5e846004 HS |
4079 | txpower = rt2x00_get_field16(eeprom, |
4080 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 4081 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4082 | power_level, txpower, delta); |
e90c54b2 | 4083 | rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); |
5e846004 | 4084 | |
e90c54b2 RJH |
4085 | /* |
4086 | * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, | |
5e846004 | 4087 | * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, |
e90c54b2 RJH |
4088 | * TX_PWR_CFG_4: unknown |
4089 | */ | |
5e846004 HS |
4090 | txpower = rt2x00_get_field16(eeprom, |
4091 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 4092 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4093 | power_level, txpower, delta); |
e90c54b2 | 4094 | rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); |
5e846004 HS |
4095 | |
4096 | /* read the next four txpower values */ | |
022138ca GJ |
4097 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, |
4098 | i + 1, &eeprom); | |
5e846004 | 4099 | |
e90c54b2 RJH |
4100 | is_rate_b = 0; |
4101 | /* | |
4102 | * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, | |
5e846004 | 4103 | * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
4104 | * TX_PWR_CFG_4: unknown |
4105 | */ | |
5e846004 HS |
4106 | txpower = rt2x00_get_field16(eeprom, |
4107 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 4108 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4109 | power_level, txpower, delta); |
e90c54b2 | 4110 | rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); |
5e846004 | 4111 | |
e90c54b2 RJH |
4112 | /* |
4113 | * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, | |
5e846004 | 4114 | * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
4115 | * TX_PWR_CFG_4: unknown |
4116 | */ | |
5e846004 HS |
4117 | txpower = rt2x00_get_field16(eeprom, |
4118 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 4119 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4120 | power_level, txpower, delta); |
e90c54b2 | 4121 | rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); |
5e846004 | 4122 | |
e90c54b2 RJH |
4123 | /* |
4124 | * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, | |
5e846004 | 4125 | * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
4126 | * TX_PWR_CFG_4: unknown |
4127 | */ | |
5e846004 HS |
4128 | txpower = rt2x00_get_field16(eeprom, |
4129 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 4130 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4131 | power_level, txpower, delta); |
e90c54b2 | 4132 | rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); |
5e846004 | 4133 | |
e90c54b2 RJH |
4134 | /* |
4135 | * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, | |
5e846004 | 4136 | * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
4137 | * TX_PWR_CFG_4: unknown |
4138 | */ | |
5e846004 HS |
4139 | txpower = rt2x00_get_field16(eeprom, |
4140 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 4141 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 4142 | power_level, txpower, delta); |
e90c54b2 | 4143 | rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); |
5e846004 HS |
4144 | |
4145 | rt2800_register_write(rt2x00dev, offset, reg); | |
4146 | ||
4147 | /* next TX_PWR_CFG register */ | |
4148 | offset += 4; | |
4149 | } | |
f4450616 BZ |
4150 | } |
4151 | ||
34542ff5 GJ |
4152 | static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, |
4153 | struct ieee80211_channel *chan, | |
4154 | int power_level) | |
4155 | { | |
4156 | if (rt2x00_rt(rt2x00dev, RT3593)) | |
4157 | rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); | |
4158 | else | |
4159 | rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); | |
4160 | } | |
4161 | ||
9e33a355 HS |
4162 | void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) |
4163 | { | |
675a0b04 | 4164 | rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, |
9e33a355 HS |
4165 | rt2x00dev->tx_power); |
4166 | } | |
4167 | EXPORT_SYMBOL_GPL(rt2800_gain_calibration); | |
4168 | ||
2e9c43dd JL |
4169 | void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) |
4170 | { | |
4171 | u32 tx_pin; | |
4172 | u8 rfcsr; | |
4173 | ||
4174 | /* | |
4175 | * A voltage-controlled oscillator(VCO) is an electronic oscillator | |
4176 | * designed to be controlled in oscillation frequency by a voltage | |
4177 | * input. Maybe the temperature will affect the frequency of | |
4178 | * oscillation to be shifted. The VCO calibration will be called | |
4179 | * periodically to adjust the frequency to be precision. | |
4180 | */ | |
4181 | ||
4182 | rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); | |
4183 | tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; | |
4184 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
4185 | ||
4186 | switch (rt2x00dev->chip.rf) { | |
4187 | case RF2020: | |
4188 | case RF3020: | |
4189 | case RF3021: | |
4190 | case RF3022: | |
4191 | case RF3320: | |
4192 | case RF3052: | |
4193 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); | |
4194 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); | |
4195 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | |
4196 | break; | |
1095df07 | 4197 | case RF3053: |
a89534ed | 4198 | case RF3290: |
ccf91bd6 | 4199 | case RF5360: |
2e9c43dd JL |
4200 | case RF5370: |
4201 | case RF5372: | |
4202 | case RF5390: | |
cff3d1f0 | 4203 | case RF5392: |
2e9c43dd | 4204 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); |
d6d82020 | 4205 | rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); |
2e9c43dd JL |
4206 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); |
4207 | break; | |
4208 | default: | |
4209 | return; | |
4210 | } | |
4211 | ||
4212 | mdelay(1); | |
4213 | ||
4214 | rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); | |
4215 | if (rt2x00dev->rf_channel <= 14) { | |
4216 | switch (rt2x00dev->default_ant.tx_chain_num) { | |
4217 | case 3: | |
4218 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); | |
4219 | /* fall through */ | |
4220 | case 2: | |
4221 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); | |
4222 | /* fall through */ | |
4223 | case 1: | |
4224 | default: | |
4225 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); | |
4226 | break; | |
4227 | } | |
4228 | } else { | |
4229 | switch (rt2x00dev->default_ant.tx_chain_num) { | |
4230 | case 3: | |
4231 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); | |
4232 | /* fall through */ | |
4233 | case 2: | |
4234 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); | |
4235 | /* fall through */ | |
4236 | case 1: | |
4237 | default: | |
4238 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); | |
4239 | break; | |
4240 | } | |
4241 | } | |
4242 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
4243 | ||
4244 | } | |
4245 | EXPORT_SYMBOL_GPL(rt2800_vco_calibration); | |
4246 | ||
f4450616 BZ |
4247 | static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
4248 | struct rt2x00lib_conf *libconf) | |
4249 | { | |
4250 | u32 reg; | |
4251 | ||
4252 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); | |
4253 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, | |
4254 | libconf->conf->short_frame_max_tx_count); | |
4255 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, | |
4256 | libconf->conf->long_frame_max_tx_count); | |
f4450616 BZ |
4257 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); |
4258 | } | |
4259 | ||
4260 | static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, | |
4261 | struct rt2x00lib_conf *libconf) | |
4262 | { | |
4263 | enum dev_state state = | |
4264 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
4265 | STATE_SLEEP : STATE_AWAKE; | |
4266 | u32 reg; | |
4267 | ||
4268 | if (state == STATE_SLEEP) { | |
4269 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); | |
4270 | ||
4271 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); | |
4272 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); | |
4273 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, | |
4274 | libconf->conf->listen_interval - 1); | |
4275 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); | |
4276 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
4277 | ||
4278 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
4279 | } else { | |
f4450616 BZ |
4280 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
4281 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); | |
4282 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); | |
4283 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); | |
4284 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
5731858d GW |
4285 | |
4286 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
f4450616 BZ |
4287 | } |
4288 | } | |
4289 | ||
4290 | void rt2800_config(struct rt2x00_dev *rt2x00dev, | |
4291 | struct rt2x00lib_conf *libconf, | |
4292 | const unsigned int flags) | |
4293 | { | |
4294 | /* Always recalculate LNA gain before changing configuration */ | |
4295 | rt2800_config_lna_gain(rt2x00dev, libconf); | |
4296 | ||
e90c54b2 | 4297 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { |
f4450616 BZ |
4298 | rt2800_config_channel(rt2x00dev, libconf->conf, |
4299 | &libconf->rf, &libconf->channel); | |
675a0b04 | 4300 | rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, |
9e33a355 | 4301 | libconf->conf->power_level); |
e90c54b2 | 4302 | } |
f4450616 | 4303 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
675a0b04 | 4304 | rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, |
9e33a355 | 4305 | libconf->conf->power_level); |
f4450616 BZ |
4306 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
4307 | rt2800_config_retry_limit(rt2x00dev, libconf); | |
4308 | if (flags & IEEE80211_CONF_CHANGE_PS) | |
4309 | rt2800_config_ps(rt2x00dev, libconf); | |
4310 | } | |
4311 | EXPORT_SYMBOL_GPL(rt2800_config); | |
4312 | ||
4313 | /* | |
4314 | * Link tuning | |
4315 | */ | |
4316 | void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
4317 | { | |
4318 | u32 reg; | |
4319 | ||
4320 | /* | |
4321 | * Update FCS error count from register. | |
4322 | */ | |
4323 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
4324 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); | |
4325 | } | |
4326 | EXPORT_SYMBOL_GPL(rt2800_link_stats); | |
4327 | ||
4328 | static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |
4329 | { | |
8c6728b0 GW |
4330 | u8 vgc; |
4331 | ||
f4450616 | 4332 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { |
d5385bfc | 4333 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 | 4334 | rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 4335 | rt2x00_rt(rt2x00dev, RT3090) || |
a89534ed | 4336 | rt2x00_rt(rt2x00dev, RT3290) || |
adde5882 | 4337 | rt2x00_rt(rt2x00dev, RT3390) || |
d961e447 | 4338 | rt2x00_rt(rt2x00dev, RT3572) || |
2ed71884 | 4339 | rt2x00_rt(rt2x00dev, RT5390) || |
3d81535e SG |
4340 | rt2x00_rt(rt2x00dev, RT5392) || |
4341 | rt2x00_rt(rt2x00dev, RT5592)) | |
8c6728b0 GW |
4342 | vgc = 0x1c + (2 * rt2x00dev->lna_gain); |
4343 | else | |
4344 | vgc = 0x2e + rt2x00dev->lna_gain; | |
4345 | } else { /* 5GHZ band */ | |
d961e447 GW |
4346 | if (rt2x00_rt(rt2x00dev, RT3572)) |
4347 | vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3; | |
3d81535e SG |
4348 | else if (rt2x00_rt(rt2x00dev, RT5592)) |
4349 | vgc = 0x24 + (2 * rt2x00dev->lna_gain); | |
d961e447 GW |
4350 | else { |
4351 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
4352 | vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; | |
4353 | else | |
4354 | vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; | |
4355 | } | |
f4450616 BZ |
4356 | } |
4357 | ||
8c6728b0 | 4358 | return vgc; |
f4450616 BZ |
4359 | } |
4360 | ||
4361 | static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, | |
4362 | struct link_qual *qual, u8 vgc_level) | |
4363 | { | |
4364 | if (qual->vgc_level != vgc_level) { | |
3d81535e SG |
4365 | if (rt2x00_rt(rt2x00dev, RT5592)) { |
4366 | rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); | |
4367 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); | |
4368 | } else | |
4369 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); | |
f4450616 BZ |
4370 | qual->vgc_level = vgc_level; |
4371 | qual->vgc_level_reg = vgc_level; | |
4372 | } | |
4373 | } | |
4374 | ||
4375 | void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
4376 | { | |
4377 | rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); | |
4378 | } | |
4379 | EXPORT_SYMBOL_GPL(rt2800_reset_tuner); | |
4380 | ||
4381 | void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, | |
4382 | const u32 count) | |
4383 | { | |
3d81535e SG |
4384 | u8 vgc; |
4385 | ||
8d0c9b65 | 4386 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) |
f4450616 | 4387 | return; |
f4450616 | 4388 | /* |
3d81535e SG |
4389 | * When RSSI is better then -80 increase VGC level with 0x10, except |
4390 | * for rt5592 chip. | |
f4450616 | 4391 | */ |
3d81535e SG |
4392 | |
4393 | vgc = rt2800_get_default_vgc(rt2x00dev); | |
4394 | ||
4395 | if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65) | |
4396 | vgc += 0x20; | |
4397 | else if (qual->rssi > -80) | |
4398 | vgc += 0x10; | |
4399 | ||
4400 | rt2800_set_vgc(rt2x00dev, qual, vgc); | |
f4450616 BZ |
4401 | } |
4402 | EXPORT_SYMBOL_GPL(rt2800_link_tuner); | |
fcf51541 BZ |
4403 | |
4404 | /* | |
4405 | * Initialization functions. | |
4406 | */ | |
b9a07ae9 | 4407 | static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
4408 | { |
4409 | u32 reg; | |
d5385bfc | 4410 | u16 eeprom; |
fcf51541 | 4411 | unsigned int i; |
e3a896b9 | 4412 | int ret; |
fcf51541 | 4413 | |
f7b395e9 | 4414 | rt2800_disable_wpdma(rt2x00dev); |
a9dce149 | 4415 | |
e3a896b9 GW |
4416 | ret = rt2800_drv_init_registers(rt2x00dev); |
4417 | if (ret) | |
4418 | return ret; | |
fcf51541 BZ |
4419 | |
4420 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); | |
4421 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ | |
4422 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ | |
4423 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ | |
4424 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ | |
4425 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); | |
4426 | ||
4427 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); | |
4428 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ | |
4429 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ | |
4430 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ | |
4431 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ | |
4432 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); | |
4433 | ||
4434 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); | |
4435 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
4436 | ||
4437 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); | |
4438 | ||
4439 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
8544df32 | 4440 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); |
fcf51541 BZ |
4441 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); |
4442 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); | |
4443 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); | |
4444 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
4445 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); | |
4446 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
4447 | ||
a9dce149 GW |
4448 | rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); |
4449 | ||
4450 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
4451 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); | |
4452 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); | |
4453 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
4454 | ||
a89534ed WH |
4455 | if (rt2x00_rt(rt2x00dev, RT3290)) { |
4456 | rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); | |
4457 | if (rt2x00_get_field32(reg, WLAN_EN) == 1) { | |
4458 | rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); | |
4459 | rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); | |
4460 | } | |
4461 | ||
4462 | rt2800_register_read(rt2x00dev, CMB_CTRL, ®); | |
4463 | if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { | |
4464 | rt2x00_set_field32(®, LDO0_EN, 1); | |
4465 | rt2x00_set_field32(®, LDO_BGSEL, 3); | |
4466 | rt2800_register_write(rt2x00dev, CMB_CTRL, reg); | |
4467 | } | |
4468 | ||
4469 | rt2800_register_read(rt2x00dev, OSC_CTRL, ®); | |
4470 | rt2x00_set_field32(®, OSC_ROSC_EN, 1); | |
4471 | rt2x00_set_field32(®, OSC_CAL_REQ, 1); | |
4472 | rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); | |
4473 | rt2800_register_write(rt2x00dev, OSC_CTRL, reg); | |
4474 | ||
4475 | rt2800_register_read(rt2x00dev, COEX_CFG0, ®); | |
4476 | rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); | |
4477 | rt2800_register_write(rt2x00dev, COEX_CFG0, reg); | |
4478 | ||
4479 | rt2800_register_read(rt2x00dev, COEX_CFG2, ®); | |
4480 | rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); | |
4481 | rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); | |
4482 | rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); | |
4483 | rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); | |
4484 | rt2800_register_write(rt2x00dev, COEX_CFG2, reg); | |
4485 | ||
4486 | rt2800_register_read(rt2x00dev, PLL_CTRL, ®); | |
4487 | rt2x00_set_field32(®, PLL_CONTROL, 1); | |
4488 | rt2800_register_write(rt2x00dev, PLL_CTRL, reg); | |
4489 | } | |
4490 | ||
64522957 | 4491 | if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 4492 | rt2x00_rt(rt2x00dev, RT3090) || |
a89534ed | 4493 | rt2x00_rt(rt2x00dev, RT3290) || |
cc78e904 | 4494 | rt2x00_rt(rt2x00dev, RT3390)) { |
a89534ed WH |
4495 | |
4496 | if (rt2x00_rt(rt2x00dev, RT3290)) | |
4497 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, | |
4498 | 0x00000404); | |
4499 | else | |
4500 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, | |
4501 | 0x00000400); | |
4502 | ||
fcf51541 | 4503 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); |
64522957 | 4504 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 GW |
4505 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
4506 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
3e38d3da GJ |
4507 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, |
4508 | &eeprom); | |
38c8a566 | 4509 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) |
d5385bfc GW |
4510 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, |
4511 | 0x0000002c); | |
4512 | else | |
4513 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
4514 | 0x0000000f); | |
4515 | } else { | |
4516 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
4517 | } | |
d5385bfc | 4518 | } else if (rt2x00_rt(rt2x00dev, RT3070)) { |
fcf51541 | 4519 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
8cdd15e0 GW |
4520 | |
4521 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
4522 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
4523 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); | |
4524 | } else { | |
4525 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
4526 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
4527 | } | |
c295a81d HS |
4528 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
4529 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
4530 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
961636ba | 4531 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); |
03839951 DG |
4532 | } else if (rt2x00_rt(rt2x00dev, RT3352)) { |
4533 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); | |
4534 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
4535 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
872834df GW |
4536 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { |
4537 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
4538 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
1706d15d GJ |
4539 | } else if (rt2x00_rt(rt2x00dev, RT3593)) { |
4540 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); | |
4541 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
4542 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { | |
4543 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, | |
4544 | &eeprom); | |
4545 | if (rt2x00_get_field16(eeprom, | |
4546 | EEPROM_NIC_CONF1_DAC_TEST)) | |
4547 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
4548 | 0x0000001f); | |
4549 | else | |
4550 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
4551 | 0x0000000f); | |
4552 | } else { | |
4553 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
4554 | 0x00000000); | |
4555 | } | |
2ed71884 | 4556 | } else if (rt2x00_rt(rt2x00dev, RT5390) || |
7641328d SG |
4557 | rt2x00_rt(rt2x00dev, RT5392) || |
4558 | rt2x00_rt(rt2x00dev, RT5592)) { | |
adde5882 GJ |
4559 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); |
4560 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
4561 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
fcf51541 BZ |
4562 | } else { |
4563 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); | |
4564 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
4565 | } | |
4566 | ||
4567 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); | |
4568 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); | |
4569 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); | |
4570 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); | |
4571 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); | |
4572 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); | |
4573 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); | |
4574 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); | |
4575 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); | |
4576 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); | |
4577 | ||
4578 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); | |
4579 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); | |
a9dce149 | 4580 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); |
fcf51541 BZ |
4581 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); |
4582 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); | |
4583 | ||
4584 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); | |
4585 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); | |
8d0c9b65 | 4586 | if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || |
49e721ec | 4587 | rt2x00_rt(rt2x00dev, RT2883) || |
8d0c9b65 | 4588 | rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) |
fcf51541 BZ |
4589 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); |
4590 | else | |
4591 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); | |
4592 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); | |
4593 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); | |
4594 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); | |
4595 | ||
a9dce149 GW |
4596 | rt2800_register_read(rt2x00dev, LED_CFG, ®); |
4597 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); | |
4598 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); | |
4599 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); | |
4600 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); | |
4601 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); | |
4602 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); | |
4603 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); | |
4604 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | |
4605 | ||
fcf51541 BZ |
4606 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); |
4607 | ||
a9dce149 GW |
4608 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); |
4609 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); | |
4610 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); | |
4611 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); | |
4612 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); | |
4613 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); | |
4614 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); | |
4615 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); | |
4616 | ||
fcf51541 BZ |
4617 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
4618 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); | |
a9dce149 | 4619 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); |
fcf51541 BZ |
4620 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); |
4621 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); | |
a9dce149 | 4622 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); |
fcf51541 BZ |
4623 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); |
4624 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); | |
4625 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
4626 | ||
4627 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
a9dce149 | 4628 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 4629 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 4630 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4631 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4632 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4633 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 4634 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 4635 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
4636 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
4637 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
4638 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
4639 | ||
4640 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
a9dce149 | 4641 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 4642 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 4643 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4644 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4645 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4646 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 4647 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 4648 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
4649 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
4650 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
4651 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
4652 | ||
4653 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
4654 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); | |
4655 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 4656 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4657 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4658 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4659 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
4660 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
4661 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
4662 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 4663 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
4664 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
4665 | ||
4666 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
4667 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); | |
d13a97f0 | 4668 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 4669 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4670 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4671 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4672 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
4673 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
4674 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
4675 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 4676 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
4677 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
4678 | ||
4679 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
4680 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); | |
4681 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 4682 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4683 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4684 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4685 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
4686 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
4687 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
4688 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 4689 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
4690 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
4691 | ||
4692 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
4693 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); | |
4694 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 4695 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
4696 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
4697 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
4698 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
4699 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
4700 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
4701 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 4702 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
4703 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
4704 | ||
cea90e55 | 4705 | if (rt2x00_is_usb(rt2x00dev)) { |
fcf51541 BZ |
4706 | rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); |
4707 | ||
4708 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
4709 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
4710 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
4711 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
4712 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
4713 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); | |
4714 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); | |
4715 | rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); | |
4716 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); | |
4717 | rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); | |
4718 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
4719 | } | |
4720 | ||
961621ab HS |
4721 | /* |
4722 | * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 | |
4723 | * although it is reserved. | |
4724 | */ | |
4725 | rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); | |
4726 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); | |
4727 | rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); | |
4728 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); | |
4729 | rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); | |
4730 | rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); | |
4731 | rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); | |
4732 | rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); | |
4733 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); | |
4734 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); | |
4735 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); | |
4736 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); | |
4737 | ||
7641328d SG |
4738 | reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; |
4739 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); | |
fcf51541 BZ |
4740 | |
4741 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
4742 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); | |
4743 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, | |
4744 | IEEE80211_MAX_RTS_THRESHOLD); | |
4745 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); | |
4746 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
4747 | ||
4748 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); | |
a9dce149 | 4749 | |
a21c2ab4 HS |
4750 | /* |
4751 | * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS | |
4752 | * time should be set to 16. However, the original Ralink driver uses | |
4753 | * 16 for both and indeed using a value of 10 for CCK SIFS results in | |
4754 | * connection problems with 11g + CTS protection. Hence, use the same | |
4755 | * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. | |
4756 | */ | |
a9dce149 | 4757 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
a21c2ab4 HS |
4758 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); |
4759 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); | |
a9dce149 GW |
4760 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); |
4761 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); | |
4762 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); | |
4763 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
4764 | ||
fcf51541 BZ |
4765 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
4766 | ||
4767 | /* | |
4768 | * ASIC will keep garbage value after boot, clear encryption keys. | |
4769 | */ | |
4770 | for (i = 0; i < 4; i++) | |
4771 | rt2800_register_write(rt2x00dev, | |
4772 | SHARED_KEY_MODE_ENTRY(i), 0); | |
4773 | ||
4774 | for (i = 0; i < 256; i++) { | |
d7d259d3 HS |
4775 | rt2800_config_wcid(rt2x00dev, NULL, i); |
4776 | rt2800_delete_wcid_attr(rt2x00dev, i); | |
fcf51541 BZ |
4777 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
4778 | } | |
4779 | ||
4780 | /* | |
4781 | * Clear all beacons | |
fcf51541 | 4782 | */ |
69cf36a4 HS |
4783 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0); |
4784 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1); | |
4785 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2); | |
4786 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3); | |
4787 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4); | |
4788 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5); | |
4789 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6); | |
4790 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7); | |
fcf51541 | 4791 | |
cea90e55 | 4792 | if (rt2x00_is_usb(rt2x00dev)) { |
785c3c06 GW |
4793 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); |
4794 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); | |
4795 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
c6fcc0e5 RJH |
4796 | } else if (rt2x00_is_pcie(rt2x00dev)) { |
4797 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); | |
4798 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); | |
4799 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
fcf51541 BZ |
4800 | } |
4801 | ||
4802 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); | |
4803 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); | |
4804 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); | |
4805 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); | |
4806 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); | |
4807 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); | |
4808 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); | |
4809 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); | |
4810 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); | |
4811 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); | |
4812 | ||
4813 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); | |
4814 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); | |
4815 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); | |
4816 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); | |
4817 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); | |
4818 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); | |
4819 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); | |
4820 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); | |
4821 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); | |
4822 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); | |
4823 | ||
4824 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); | |
4825 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); | |
4826 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); | |
4827 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); | |
4828 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); | |
4829 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); | |
4830 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); | |
4831 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); | |
4832 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); | |
4833 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); | |
4834 | ||
4835 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); | |
4836 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); | |
4837 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); | |
4838 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); | |
4839 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); | |
4840 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); | |
4841 | ||
47ee3eb1 HS |
4842 | /* |
4843 | * Do not force the BA window size, we use the TXWI to set it | |
4844 | */ | |
4845 | rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); | |
4846 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); | |
4847 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); | |
4848 | rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); | |
4849 | ||
fcf51541 BZ |
4850 | /* |
4851 | * We must clear the error counters. | |
4852 | * These registers are cleared on read, | |
4853 | * so we may pass a useless variable to store the value. | |
4854 | */ | |
4855 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
4856 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); | |
4857 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); | |
4858 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); | |
4859 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); | |
4860 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); | |
4861 | ||
9f926fb5 HS |
4862 | /* |
4863 | * Setup leadtime for pre tbtt interrupt to 6ms | |
4864 | */ | |
4865 | rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); | |
4866 | rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); | |
4867 | rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); | |
4868 | ||
977206d7 HS |
4869 | /* |
4870 | * Set up channel statistics timer | |
4871 | */ | |
4872 | rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); | |
4873 | rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); | |
4874 | rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); | |
4875 | rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); | |
4876 | rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); | |
4877 | rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); | |
4878 | rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); | |
4879 | ||
fcf51541 BZ |
4880 | return 0; |
4881 | } | |
fcf51541 BZ |
4882 | |
4883 | static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) | |
4884 | { | |
4885 | unsigned int i; | |
4886 | u32 reg; | |
4887 | ||
4888 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
4889 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); | |
4890 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) | |
4891 | return 0; | |
4892 | ||
4893 | udelay(REGISTER_BUSY_DELAY); | |
4894 | } | |
4895 | ||
ec9c4989 | 4896 | rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); |
fcf51541 BZ |
4897 | return -EACCES; |
4898 | } | |
4899 | ||
4900 | static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) | |
4901 | { | |
4902 | unsigned int i; | |
4903 | u8 value; | |
4904 | ||
4905 | /* | |
4906 | * BBP was enabled after firmware was loaded, | |
4907 | * but we need to reactivate it now. | |
4908 | */ | |
4909 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
4910 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
4911 | msleep(1); | |
4912 | ||
4913 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
4914 | rt2800_bbp_read(rt2x00dev, 0, &value); | |
4915 | if ((value != 0xff) && (value != 0x00)) | |
4916 | return 0; | |
4917 | udelay(REGISTER_BUSY_DELAY); | |
4918 | } | |
4919 | ||
ec9c4989 | 4920 | rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); |
fcf51541 BZ |
4921 | return -EACCES; |
4922 | } | |
4923 | ||
a7bbbe5c SG |
4924 | static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) |
4925 | { | |
4926 | u8 value; | |
4927 | ||
4928 | rt2800_bbp_read(rt2x00dev, 4, &value); | |
4929 | rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); | |
4930 | rt2800_bbp_write(rt2x00dev, 4, value); | |
4931 | } | |
4932 | ||
c2675487 SG |
4933 | static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) |
4934 | { | |
4935 | rt2800_bbp_write(rt2x00dev, 142, 1); | |
4936 | rt2800_bbp_write(rt2x00dev, 143, 57); | |
4937 | } | |
4938 | ||
a7bbbe5c SG |
4939 | static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) |
4940 | { | |
4941 | const u8 glrt_table[] = { | |
4942 | 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ | |
4943 | 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ | |
4944 | 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ | |
4945 | 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ | |
4946 | 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ | |
4947 | 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ | |
4948 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ | |
4949 | 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ | |
4950 | 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ | |
4951 | }; | |
4952 | int i; | |
4953 | ||
4954 | for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { | |
4955 | rt2800_bbp_write(rt2x00dev, 195, 128 + i); | |
4956 | rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); | |
4957 | } | |
4958 | }; | |
4959 | ||
624708b8 | 4960 | static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) |
a4969d0d SG |
4961 | { |
4962 | rt2800_bbp_write(rt2x00dev, 65, 0x2C); | |
4963 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
4964 | rt2800_bbp_write(rt2x00dev, 68, 0x0B); | |
4965 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
4966 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
4967 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
4968 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
4969 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
4970 | rt2800_bbp_write(rt2x00dev, 83, 0x6A); | |
4971 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
4972 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
4973 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
4974 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
4975 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
4976 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
4977 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
4978 | } | |
4979 | ||
5df1ff3a SG |
4980 | static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) |
4981 | { | |
4982 | u16 eeprom; | |
4983 | u8 value; | |
4984 | ||
4985 | rt2800_bbp_read(rt2x00dev, 138, &value); | |
3e38d3da | 4986 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
5df1ff3a SG |
4987 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) |
4988 | value |= 0x20; | |
4989 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) | |
4990 | value &= ~0x02; | |
4991 | rt2800_bbp_write(rt2x00dev, 138, value); | |
4992 | } | |
4993 | ||
dae62957 SG |
4994 | static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) |
4995 | { | |
b2f8e0bd | 4996 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
e379de12 SG |
4997 | |
4998 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
4999 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
72ffe142 SG |
5000 | |
5001 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5002 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
8d97be38 SG |
5003 | |
5004 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5005 | |
5006 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); | |
5007 | rt2800_bbp_write(rt2x00dev, 80, 0x08); | |
fa1e3424 SG |
5008 | |
5009 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5010 | |
5011 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5012 | |
5013 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5014 | |
5015 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
7af98742 SG |
5016 | |
5017 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5018 | |
5019 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
672d1188 SG |
5020 | |
5021 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
49d61118 SG |
5022 | |
5023 | rt2800_bbp_write(rt2x00dev, 105, 0x01); | |
f867085e SG |
5024 | |
5025 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
dae62957 SG |
5026 | } |
5027 | ||
39ab3e8b SG |
5028 | static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) |
5029 | { | |
e379de12 SG |
5030 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
5031 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
72ffe142 SG |
5032 | |
5033 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { | |
5034 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
5035 | rt2800_bbp_write(rt2x00dev, 73, 0x12); | |
5036 | } else { | |
5037 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5038 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
5039 | } | |
8d97be38 SG |
5040 | |
5041 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5042 | |
5043 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
fa1e3424 SG |
5044 | |
5045 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5046 | |
5047 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5048 | |
5049 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) | |
5050 | rt2800_bbp_write(rt2x00dev, 84, 0x19); | |
5051 | else | |
5052 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5053 | |
5054 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
7af98742 SG |
5055 | |
5056 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5057 | |
5058 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
672d1188 SG |
5059 | |
5060 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
49d61118 SG |
5061 | |
5062 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
f867085e SG |
5063 | |
5064 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
39ab3e8b SG |
5065 | } |
5066 | ||
5067 | static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) | |
5068 | { | |
e379de12 SG |
5069 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
5070 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
72ffe142 SG |
5071 | |
5072 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5073 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
8d97be38 SG |
5074 | |
5075 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5076 | |
5077 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | |
5078 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
5079 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
fa1e3424 SG |
5080 | |
5081 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5082 | |
5083 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5084 | |
5085 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5086 | |
5087 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
7af98742 SG |
5088 | |
5089 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5090 | |
5091 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
672d1188 SG |
5092 | |
5093 | if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || | |
5094 | rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || | |
5095 | rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) | |
5096 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
5097 | else | |
5098 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
49d61118 SG |
5099 | |
5100 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
f867085e SG |
5101 | |
5102 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
5df1ff3a SG |
5103 | |
5104 | if (rt2x00_rt(rt2x00dev, RT3071) || | |
5105 | rt2x00_rt(rt2x00dev, RT3090)) | |
5106 | rt2800_disable_unused_dac_adc(rt2x00dev); | |
39ab3e8b SG |
5107 | } |
5108 | ||
5109 | static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) | |
5110 | { | |
6addb24e SG |
5111 | u8 value; |
5112 | ||
c3223573 | 5113 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); |
b2f8e0bd SG |
5114 | |
5115 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
e379de12 SG |
5116 | |
5117 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
5118 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
59dcabb5 SG |
5119 | |
5120 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
72ffe142 SG |
5121 | |
5122 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5123 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
5124 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
5125 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
5126 | ||
5127 | rt2800_bbp_write(rt2x00dev, 77, 0x58); | |
8d97be38 SG |
5128 | |
5129 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5130 | |
5131 | rt2800_bbp_write(rt2x00dev, 74, 0x0b); | |
5132 | rt2800_bbp_write(rt2x00dev, 79, 0x18); | |
5133 | rt2800_bbp_write(rt2x00dev, 80, 0x09); | |
5134 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
fa1e3424 SG |
5135 | |
5136 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5137 | |
5138 | rt2800_bbp_write(rt2x00dev, 83, 0x7a); | |
3c20a122 SG |
5139 | |
5140 | rt2800_bbp_write(rt2x00dev, 84, 0x9a); | |
aef9f38b SG |
5141 | |
5142 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
7af98742 SG |
5143 | |
5144 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5145 | |
5146 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
672d1188 SG |
5147 | |
5148 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
1ad4408a SG |
5149 | |
5150 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
49d61118 SG |
5151 | |
5152 | rt2800_bbp_write(rt2x00dev, 105, 0x1c); | |
f867085e SG |
5153 | |
5154 | rt2800_bbp_write(rt2x00dev, 106, 0x03); | |
f2b6777c SG |
5155 | |
5156 | rt2800_bbp_write(rt2x00dev, 128, 0x12); | |
6addb24e SG |
5157 | |
5158 | rt2800_bbp_write(rt2x00dev, 67, 0x24); | |
5159 | rt2800_bbp_write(rt2x00dev, 143, 0x04); | |
5160 | rt2800_bbp_write(rt2x00dev, 142, 0x99); | |
5161 | rt2800_bbp_write(rt2x00dev, 150, 0x30); | |
5162 | rt2800_bbp_write(rt2x00dev, 151, 0x2e); | |
5163 | rt2800_bbp_write(rt2x00dev, 152, 0x20); | |
5164 | rt2800_bbp_write(rt2x00dev, 153, 0x34); | |
5165 | rt2800_bbp_write(rt2x00dev, 154, 0x40); | |
5166 | rt2800_bbp_write(rt2x00dev, 155, 0x3b); | |
5167 | rt2800_bbp_write(rt2x00dev, 253, 0x04); | |
5168 | ||
5169 | rt2800_bbp_read(rt2x00dev, 47, &value); | |
5170 | rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); | |
5171 | rt2800_bbp_write(rt2x00dev, 47, value); | |
5172 | ||
5173 | /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ | |
5174 | rt2800_bbp_read(rt2x00dev, 3, &value); | |
5175 | rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); | |
5176 | rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); | |
5177 | rt2800_bbp_write(rt2x00dev, 3, value); | |
39ab3e8b SG |
5178 | } |
5179 | ||
5180 | static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) | |
5181 | { | |
29f3a58b SG |
5182 | rt2800_bbp_write(rt2x00dev, 3, 0x00); |
5183 | rt2800_bbp_write(rt2x00dev, 4, 0x50); | |
b2f8e0bd SG |
5184 | |
5185 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
3420f797 SG |
5186 | |
5187 | rt2800_bbp_write(rt2x00dev, 47, 0x48); | |
e379de12 SG |
5188 | |
5189 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
5190 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
59dcabb5 SG |
5191 | |
5192 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
72ffe142 SG |
5193 | |
5194 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5195 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
5196 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
5197 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
5198 | ||
5199 | rt2800_bbp_write(rt2x00dev, 77, 0x59); | |
8d97be38 SG |
5200 | |
5201 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5202 | |
5203 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); | |
5204 | rt2800_bbp_write(rt2x00dev, 80, 0x08); | |
5205 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
fa1e3424 SG |
5206 | |
5207 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5208 | |
5209 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5210 | |
5211 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5212 | |
5213 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
9400fa87 SG |
5214 | |
5215 | rt2800_bbp_write(rt2x00dev, 88, 0x90); | |
7af98742 SG |
5216 | |
5217 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5218 | |
5219 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
672d1188 SG |
5220 | |
5221 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
1ad4408a SG |
5222 | |
5223 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
49d61118 SG |
5224 | |
5225 | rt2800_bbp_write(rt2x00dev, 105, 0x34); | |
f867085e SG |
5226 | |
5227 | rt2800_bbp_write(rt2x00dev, 106, 0x05); | |
46b90d32 SG |
5228 | |
5229 | rt2800_bbp_write(rt2x00dev, 120, 0x50); | |
b7feb9ba SG |
5230 | |
5231 | rt2800_bbp_write(rt2x00dev, 137, 0x0f); | |
c2da5273 SG |
5232 | |
5233 | rt2800_bbp_write(rt2x00dev, 163, 0xbd); | |
5234 | /* Set ITxBF timeout to 0x9c40=1000msec */ | |
5235 | rt2800_bbp_write(rt2x00dev, 179, 0x02); | |
5236 | rt2800_bbp_write(rt2x00dev, 180, 0x00); | |
5237 | rt2800_bbp_write(rt2x00dev, 182, 0x40); | |
5238 | rt2800_bbp_write(rt2x00dev, 180, 0x01); | |
5239 | rt2800_bbp_write(rt2x00dev, 182, 0x9c); | |
5240 | rt2800_bbp_write(rt2x00dev, 179, 0x00); | |
5241 | /* Reprogram the inband interface to put right values in RXWI */ | |
5242 | rt2800_bbp_write(rt2x00dev, 142, 0x04); | |
5243 | rt2800_bbp_write(rt2x00dev, 143, 0x3b); | |
5244 | rt2800_bbp_write(rt2x00dev, 142, 0x06); | |
5245 | rt2800_bbp_write(rt2x00dev, 143, 0xa0); | |
5246 | rt2800_bbp_write(rt2x00dev, 142, 0x07); | |
5247 | rt2800_bbp_write(rt2x00dev, 143, 0xa1); | |
5248 | rt2800_bbp_write(rt2x00dev, 142, 0x08); | |
5249 | rt2800_bbp_write(rt2x00dev, 143, 0xa2); | |
5250 | ||
5251 | rt2800_bbp_write(rt2x00dev, 148, 0xc8); | |
39ab3e8b SG |
5252 | } |
5253 | ||
5254 | static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) | |
5255 | { | |
e379de12 SG |
5256 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
5257 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
72ffe142 SG |
5258 | |
5259 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5260 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
8d97be38 SG |
5261 | |
5262 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5263 | |
5264 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | |
5265 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
5266 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
fa1e3424 SG |
5267 | |
5268 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5269 | |
5270 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5271 | |
5272 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5273 | |
5274 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
7af98742 SG |
5275 | |
5276 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5277 | |
5278 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
672d1188 SG |
5279 | |
5280 | if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) | |
5281 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
5282 | else | |
5283 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
49d61118 SG |
5284 | |
5285 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
f867085e SG |
5286 | |
5287 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
5df1ff3a SG |
5288 | |
5289 | rt2800_disable_unused_dac_adc(rt2x00dev); | |
39ab3e8b SG |
5290 | } |
5291 | ||
5292 | static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) | |
5293 | { | |
b2f8e0bd | 5294 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
e379de12 SG |
5295 | |
5296 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
5297 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
72ffe142 SG |
5298 | |
5299 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5300 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
8d97be38 SG |
5301 | |
5302 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5303 | |
5304 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | |
5305 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
5306 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
fa1e3424 SG |
5307 | |
5308 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5309 | |
5310 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
3c20a122 SG |
5311 | |
5312 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
aef9f38b SG |
5313 | |
5314 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
7af98742 SG |
5315 | |
5316 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5317 | |
5318 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
672d1188 SG |
5319 | |
5320 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
49d61118 SG |
5321 | |
5322 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
f867085e SG |
5323 | |
5324 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
5df1ff3a SG |
5325 | |
5326 | rt2800_disable_unused_dac_adc(rt2x00dev); | |
39ab3e8b SG |
5327 | } |
5328 | ||
b189a181 GJ |
5329 | static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) |
5330 | { | |
5331 | rt2800_init_bbp_early(rt2x00dev); | |
5332 | ||
5333 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | |
5334 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
5335 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
5336 | rt2800_bbp_write(rt2x00dev, 137, 0x0f); | |
5337 | ||
5338 | rt2800_bbp_write(rt2x00dev, 84, 0x19); | |
5339 | ||
5340 | /* Enable DC filter */ | |
5341 | if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) | |
5342 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
5343 | } | |
5344 | ||
39ab3e8b SG |
5345 | static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) |
5346 | { | |
32ef8f49 SG |
5347 | int ant, div_mode; |
5348 | u16 eeprom; | |
5349 | u8 value; | |
5350 | ||
c3223573 | 5351 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); |
b2f8e0bd SG |
5352 | |
5353 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
e379de12 SG |
5354 | |
5355 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
5356 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
59dcabb5 SG |
5357 | |
5358 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
72ffe142 SG |
5359 | |
5360 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
5361 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
5362 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
5363 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
5364 | ||
5365 | rt2800_bbp_write(rt2x00dev, 77, 0x59); | |
8d97be38 SG |
5366 | |
5367 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
43f535e2 SG |
5368 | |
5369 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | |
5370 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
5371 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
fa1e3424 SG |
5372 | |
5373 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
885f2414 SG |
5374 | |
5375 | rt2800_bbp_write(rt2x00dev, 83, 0x7a); | |
3c20a122 SG |
5376 | |
5377 | rt2800_bbp_write(rt2x00dev, 84, 0x9a); | |
aef9f38b SG |
5378 | |
5379 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
9400fa87 SG |
5380 | |
5381 | if (rt2x00_rt(rt2x00dev, RT5392)) | |
5382 | rt2800_bbp_write(rt2x00dev, 88, 0x90); | |
7af98742 SG |
5383 | |
5384 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
b4e121d1 SG |
5385 | |
5386 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
90fed535 SG |
5387 | |
5388 | if (rt2x00_rt(rt2x00dev, RT5392)) { | |
5389 | rt2800_bbp_write(rt2x00dev, 95, 0x9a); | |
5390 | rt2800_bbp_write(rt2x00dev, 98, 0x12); | |
5391 | } | |
672d1188 SG |
5392 | |
5393 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
1ad4408a SG |
5394 | |
5395 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
49d61118 SG |
5396 | |
5397 | rt2800_bbp_write(rt2x00dev, 105, 0x3c); | |
f867085e SG |
5398 | |
5399 | if (rt2x00_rt(rt2x00dev, RT5390)) | |
5400 | rt2800_bbp_write(rt2x00dev, 106, 0x03); | |
5401 | else if (rt2x00_rt(rt2x00dev, RT5392)) | |
5402 | rt2800_bbp_write(rt2x00dev, 106, 0x12); | |
5403 | else | |
5404 | WARN_ON(1); | |
f2b6777c SG |
5405 | |
5406 | rt2800_bbp_write(rt2x00dev, 128, 0x12); | |
72917140 SG |
5407 | |
5408 | if (rt2x00_rt(rt2x00dev, RT5392)) { | |
5409 | rt2800_bbp_write(rt2x00dev, 134, 0xd0); | |
5410 | rt2800_bbp_write(rt2x00dev, 135, 0xf6); | |
5411 | } | |
5df1ff3a SG |
5412 | |
5413 | rt2800_disable_unused_dac_adc(rt2x00dev); | |
32ef8f49 | 5414 | |
3e38d3da | 5415 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
32ef8f49 SG |
5416 | div_mode = rt2x00_get_field16(eeprom, |
5417 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
5418 | ant = (div_mode == 3) ? 1 : 0; | |
5419 | ||
5420 | /* check if this is a Bluetooth combo card */ | |
5421 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | |
5422 | u32 reg; | |
5423 | ||
5424 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); | |
5425 | rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); | |
5426 | rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); | |
5427 | rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); | |
5428 | rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); | |
5429 | if (ant == 0) | |
5430 | rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); | |
5431 | else if (ant == 1) | |
5432 | rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); | |
5433 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | |
5434 | } | |
5435 | ||
5436 | /* This chip has hardware antenna diversity*/ | |
5437 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { | |
5438 | rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ | |
5439 | rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ | |
5440 | rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ | |
5441 | } | |
5442 | ||
5443 | rt2800_bbp_read(rt2x00dev, 152, &value); | |
5444 | if (ant == 0) | |
5445 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); | |
5446 | else | |
5447 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); | |
5448 | rt2800_bbp_write(rt2x00dev, 152, value); | |
5449 | ||
5450 | rt2800_init_freq_calibration(rt2x00dev); | |
39ab3e8b SG |
5451 | } |
5452 | ||
a7bbbe5c SG |
5453 | static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) |
5454 | { | |
5455 | int ant, div_mode; | |
5456 | u16 eeprom; | |
5457 | u8 value; | |
5458 | ||
624708b8 | 5459 | rt2800_init_bbp_early(rt2x00dev); |
a4969d0d | 5460 | |
a7bbbe5c SG |
5461 | rt2800_bbp_read(rt2x00dev, 105, &value); |
5462 | rt2x00_set_field8(&value, BBP105_MLD, | |
5463 | rt2x00dev->default_ant.rx_chain_num == 2); | |
5464 | rt2800_bbp_write(rt2x00dev, 105, value); | |
5465 | ||
5466 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); | |
5467 | ||
5468 | rt2800_bbp_write(rt2x00dev, 20, 0x06); | |
5469 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
5470 | rt2800_bbp_write(rt2x00dev, 65, 0x2C); | |
5471 | rt2800_bbp_write(rt2x00dev, 68, 0xDD); | |
5472 | rt2800_bbp_write(rt2x00dev, 69, 0x1A); | |
5473 | rt2800_bbp_write(rt2x00dev, 70, 0x05); | |
5474 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
5475 | rt2800_bbp_write(rt2x00dev, 74, 0x0F); | |
5476 | rt2800_bbp_write(rt2x00dev, 75, 0x4F); | |
5477 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
5478 | rt2800_bbp_write(rt2x00dev, 77, 0x59); | |
5479 | rt2800_bbp_write(rt2x00dev, 84, 0x9A); | |
5480 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
5481 | rt2800_bbp_write(rt2x00dev, 88, 0x90); | |
5482 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
5483 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
5484 | rt2800_bbp_write(rt2x00dev, 95, 0x9a); | |
5485 | rt2800_bbp_write(rt2x00dev, 98, 0x12); | |
5486 | rt2800_bbp_write(rt2x00dev, 103, 0xC0); | |
5487 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
5488 | /* FIXME BBP105 owerwrite */ | |
5489 | rt2800_bbp_write(rt2x00dev, 105, 0x3C); | |
5490 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
5491 | rt2800_bbp_write(rt2x00dev, 128, 0x12); | |
5492 | rt2800_bbp_write(rt2x00dev, 134, 0xD0); | |
5493 | rt2800_bbp_write(rt2x00dev, 135, 0xF6); | |
5494 | rt2800_bbp_write(rt2x00dev, 137, 0x0F); | |
5495 | ||
5496 | /* Initialize GLRT (Generalized Likehood Radio Test) */ | |
5497 | rt2800_init_bbp_5592_glrt(rt2x00dev); | |
5498 | ||
5499 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); | |
5500 | ||
3e38d3da | 5501 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
a7bbbe5c SG |
5502 | div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); |
5503 | ant = (div_mode == 3) ? 1 : 0; | |
5504 | rt2800_bbp_read(rt2x00dev, 152, &value); | |
5505 | if (ant == 0) { | |
5506 | /* Main antenna */ | |
5507 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); | |
5508 | } else { | |
5509 | /* Auxiliary antenna */ | |
5510 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); | |
5511 | } | |
5512 | rt2800_bbp_write(rt2x00dev, 152, value); | |
5513 | ||
5514 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { | |
5515 | rt2800_bbp_read(rt2x00dev, 254, &value); | |
5516 | rt2x00_set_field8(&value, BBP254_BIT7, 1); | |
5517 | rt2800_bbp_write(rt2x00dev, 254, value); | |
5518 | } | |
5519 | ||
c2675487 SG |
5520 | rt2800_init_freq_calibration(rt2x00dev); |
5521 | ||
a7bbbe5c | 5522 | rt2800_bbp_write(rt2x00dev, 84, 0x19); |
6e04f253 SG |
5523 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) |
5524 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
a7bbbe5c SG |
5525 | } |
5526 | ||
a1ef5039 | 5527 | static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
5528 | { |
5529 | unsigned int i; | |
5530 | u16 eeprom; | |
5531 | u8 reg_id; | |
5532 | u8 value; | |
5533 | ||
dae62957 SG |
5534 | if (rt2800_is_305x_soc(rt2x00dev)) |
5535 | rt2800_init_bbp_305x_soc(rt2x00dev); | |
5536 | ||
39ab3e8b SG |
5537 | switch (rt2x00dev->chip.rt) { |
5538 | case RT2860: | |
5539 | case RT2872: | |
5540 | case RT2883: | |
5541 | rt2800_init_bbp_28xx(rt2x00dev); | |
5542 | break; | |
5543 | case RT3070: | |
5544 | case RT3071: | |
5545 | case RT3090: | |
5546 | rt2800_init_bbp_30xx(rt2x00dev); | |
5547 | break; | |
5548 | case RT3290: | |
5549 | rt2800_init_bbp_3290(rt2x00dev); | |
5550 | break; | |
5551 | case RT3352: | |
5552 | rt2800_init_bbp_3352(rt2x00dev); | |
5553 | break; | |
5554 | case RT3390: | |
5555 | rt2800_init_bbp_3390(rt2x00dev); | |
5556 | break; | |
5557 | case RT3572: | |
5558 | rt2800_init_bbp_3572(rt2x00dev); | |
5559 | break; | |
b189a181 GJ |
5560 | case RT3593: |
5561 | rt2800_init_bbp_3593(rt2x00dev); | |
5562 | return; | |
39ab3e8b SG |
5563 | case RT5390: |
5564 | case RT5392: | |
5565 | rt2800_init_bbp_53xx(rt2x00dev); | |
5566 | break; | |
5567 | case RT5592: | |
a7bbbe5c | 5568 | rt2800_init_bbp_5592(rt2x00dev); |
a1ef5039 | 5569 | return; |
a7bbbe5c SG |
5570 | } |
5571 | ||
fcf51541 | 5572 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
022138ca GJ |
5573 | rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i, |
5574 | &eeprom); | |
fcf51541 BZ |
5575 | |
5576 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
5577 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
5578 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
5579 | rt2800_bbp_write(rt2x00dev, reg_id, value); | |
5580 | } | |
5581 | } | |
fcf51541 | 5582 | } |
fcf51541 | 5583 | |
d9517f2f SG |
5584 | static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) |
5585 | { | |
5586 | u32 reg; | |
5587 | ||
5588 | rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); | |
5589 | rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); | |
5590 | rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); | |
5591 | } | |
5592 | ||
c5b3c350 SG |
5593 | static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, |
5594 | u8 filter_target) | |
fcf51541 BZ |
5595 | { |
5596 | unsigned int i; | |
5597 | u8 bbp; | |
5598 | u8 rfcsr; | |
5599 | u8 passband; | |
5600 | u8 stopband; | |
5601 | u8 overtuned = 0; | |
c5b3c350 | 5602 | u8 rfcsr24 = (bw40) ? 0x27 : 0x07; |
fcf51541 BZ |
5603 | |
5604 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
5605 | ||
5606 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
5607 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); | |
5608 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
5609 | ||
80d184e6 RJH |
5610 | rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); |
5611 | rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); | |
5612 | rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); | |
5613 | ||
fcf51541 BZ |
5614 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
5615 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); | |
5616 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
5617 | ||
5618 | /* | |
5619 | * Set power & frequency of passband test tone | |
5620 | */ | |
5621 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
5622 | ||
5623 | for (i = 0; i < 100; i++) { | |
5624 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
5625 | msleep(1); | |
5626 | ||
5627 | rt2800_bbp_read(rt2x00dev, 55, &passband); | |
5628 | if (passband) | |
5629 | break; | |
5630 | } | |
5631 | ||
5632 | /* | |
5633 | * Set power & frequency of stopband test tone | |
5634 | */ | |
5635 | rt2800_bbp_write(rt2x00dev, 24, 0x06); | |
5636 | ||
5637 | for (i = 0; i < 100; i++) { | |
5638 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
5639 | msleep(1); | |
5640 | ||
5641 | rt2800_bbp_read(rt2x00dev, 55, &stopband); | |
5642 | ||
5643 | if ((passband - stopband) <= filter_target) { | |
5644 | rfcsr24++; | |
5645 | overtuned += ((passband - stopband) == filter_target); | |
5646 | } else | |
5647 | break; | |
5648 | ||
5649 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
5650 | } | |
5651 | ||
5652 | rfcsr24 -= !!overtuned; | |
5653 | ||
5654 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
5655 | return rfcsr24; | |
5656 | } | |
5657 | ||
ce94ede9 SG |
5658 | static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, |
5659 | const unsigned int rf_reg) | |
5660 | { | |
5661 | u8 rfcsr; | |
5662 | ||
5663 | rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr); | |
5664 | rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); | |
5665 | rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); | |
5666 | msleep(1); | |
5667 | rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); | |
5668 | rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); | |
5669 | } | |
5670 | ||
c5b3c350 SG |
5671 | static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) |
5672 | { | |
5673 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | |
5674 | u8 filter_tgt_bw20; | |
5675 | u8 filter_tgt_bw40; | |
5676 | u8 rfcsr, bbp; | |
5677 | ||
5678 | /* | |
5679 | * TODO: sync filter_tgt values with vendor driver | |
5680 | */ | |
5681 | if (rt2x00_rt(rt2x00dev, RT3070)) { | |
5682 | filter_tgt_bw20 = 0x16; | |
5683 | filter_tgt_bw40 = 0x19; | |
5684 | } else { | |
5685 | filter_tgt_bw20 = 0x13; | |
5686 | filter_tgt_bw40 = 0x15; | |
5687 | } | |
5688 | ||
5689 | drv_data->calibration_bw20 = | |
5690 | rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); | |
5691 | drv_data->calibration_bw40 = | |
5692 | rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); | |
5693 | ||
5694 | /* | |
5695 | * Save BBP 25 & 26 values for later use in channel switching (for 3052) | |
5696 | */ | |
5697 | rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); | |
5698 | rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); | |
5699 | ||
5700 | /* | |
5701 | * Set back to initial state | |
5702 | */ | |
5703 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
5704 | ||
5705 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); | |
5706 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); | |
5707 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
5708 | ||
5709 | /* | |
5710 | * Set BBP back to BW20 | |
5711 | */ | |
5712 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
5713 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); | |
5714 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
5715 | } | |
5716 | ||
da8064c2 SG |
5717 | static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) |
5718 | { | |
5719 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | |
5720 | u8 min_gain, rfcsr, bbp; | |
5721 | u16 eeprom; | |
5722 | ||
5723 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
5724 | ||
5725 | rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); | |
5726 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
5727 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | |
5728 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || | |
5729 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
5730 | if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) | |
5731 | rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); | |
5732 | } | |
5733 | ||
5734 | min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; | |
5735 | if (drv_data->txmixer_gain_24g >= min_gain) { | |
5736 | rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, | |
5737 | drv_data->txmixer_gain_24g); | |
5738 | } | |
5739 | ||
5740 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
5741 | ||
5742 | if (rt2x00_rt(rt2x00dev, RT3090)) { | |
5743 | /* Turn off unused DAC1 and ADC1 to reduce power consumption */ | |
5744 | rt2800_bbp_read(rt2x00dev, 138, &bbp); | |
3e38d3da | 5745 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
da8064c2 SG |
5746 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) |
5747 | rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); | |
5748 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) | |
5749 | rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); | |
5750 | rt2800_bbp_write(rt2x00dev, 138, bbp); | |
5751 | } | |
5752 | ||
5753 | if (rt2x00_rt(rt2x00dev, RT3070)) { | |
5754 | rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); | |
5755 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) | |
5756 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); | |
5757 | else | |
5758 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); | |
5759 | rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); | |
5760 | rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); | |
5761 | rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); | |
5762 | rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); | |
5763 | } else if (rt2x00_rt(rt2x00dev, RT3071) || | |
5764 | rt2x00_rt(rt2x00dev, RT3090) || | |
5765 | rt2x00_rt(rt2x00dev, RT3390)) { | |
5766 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
5767 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
5768 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
5769 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
5770 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
5771 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
5772 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
5773 | ||
5774 | rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); | |
5775 | rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); | |
5776 | rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); | |
5777 | ||
5778 | rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); | |
5779 | rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); | |
5780 | rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); | |
5781 | ||
5782 | rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); | |
5783 | rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); | |
5784 | rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); | |
5785 | } | |
5786 | } | |
5787 | ||
ab7078ac GJ |
5788 | static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) |
5789 | { | |
5790 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | |
5791 | u8 rfcsr; | |
5792 | u8 tx_gain; | |
5793 | ||
5794 | rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); | |
5795 | rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); | |
5796 | rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); | |
5797 | ||
5798 | rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); | |
5799 | tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, | |
5800 | RFCSR17_TXMIXER_GAIN); | |
5801 | rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); | |
5802 | rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); | |
5803 | ||
5804 | rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); | |
5805 | rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); | |
5806 | rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); | |
5807 | ||
5808 | rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); | |
5809 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); | |
5810 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
5811 | ||
5812 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
5813 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
5814 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
5815 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
5816 | ||
5817 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
5818 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); | |
5819 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
5820 | ||
5821 | /* TODO: enable stream mode */ | |
5822 | } | |
5823 | ||
f7df8fe5 SG |
5824 | static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) |
5825 | { | |
5826 | u8 reg; | |
5827 | u16 eeprom; | |
5828 | ||
5829 | /* Turn off unused DAC1 and ADC1 to reduce power consumption */ | |
5830 | rt2800_bbp_read(rt2x00dev, 138, ®); | |
3e38d3da | 5831 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
f7df8fe5 SG |
5832 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) |
5833 | rt2x00_set_field8(®, BBP138_RX_ADC1, 0); | |
5834 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) | |
5835 | rt2x00_set_field8(®, BBP138_TX_DAC1, 1); | |
5836 | rt2800_bbp_write(rt2x00dev, 138, reg); | |
5837 | ||
5838 | rt2800_rfcsr_read(rt2x00dev, 38, ®); | |
5839 | rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); | |
5840 | rt2800_rfcsr_write(rt2x00dev, 38, reg); | |
5841 | ||
5842 | rt2800_rfcsr_read(rt2x00dev, 39, ®); | |
5843 | rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); | |
5844 | rt2800_rfcsr_write(rt2x00dev, 39, reg); | |
5845 | ||
5846 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); | |
5847 | ||
5848 | rt2800_rfcsr_read(rt2x00dev, 30, ®); | |
5849 | rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); | |
5850 | rt2800_rfcsr_write(rt2x00dev, 30, reg); | |
5851 | } | |
5852 | ||
d5374ef1 SG |
5853 | static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) |
5854 | { | |
ce94ede9 SG |
5855 | rt2800_rf_init_calibration(rt2x00dev, 30); |
5856 | ||
d5374ef1 SG |
5857 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
5858 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | |
5859 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | |
5860 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | |
5861 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
5862 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
5863 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
5864 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | |
5865 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | |
5866 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
5867 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | |
5868 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
5869 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | |
5870 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | |
5871 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
5872 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
5873 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
5874 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
5875 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
5876 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
5877 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
5878 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
5879 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
5880 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | |
5881 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | |
5882 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
5883 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | |
5884 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | |
5885 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | |
5886 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | |
5887 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | |
5888 | rt2800_rfcsr_write(rt2x00dev, 31, 0x00); | |
5889 | } | |
5890 | ||
5891 | static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) | |
5892 | { | |
c9a221b2 SG |
5893 | u8 rfcsr; |
5894 | u16 eeprom; | |
5895 | u32 reg; | |
5896 | ||
ce94ede9 SG |
5897 | /* XXX vendor driver do this only for 3070 */ |
5898 | rt2800_rf_init_calibration(rt2x00dev, 30); | |
5899 | ||
d5374ef1 SG |
5900 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
5901 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
5902 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
5903 | rt2800_rfcsr_write(rt2x00dev, 7, 0x60); | |
5904 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
5905 | rt2800_rfcsr_write(rt2x00dev, 10, 0x41); | |
5906 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
5907 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | |
5908 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
5909 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
5910 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
5911 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
5912 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
5913 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
5914 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
5915 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
5916 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
5917 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
5918 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); | |
c9a221b2 SG |
5919 | |
5920 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
5921 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
5922 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
5923 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
5924 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
5925 | } else if (rt2x00_rt(rt2x00dev, RT3071) || | |
5926 | rt2x00_rt(rt2x00dev, RT3090)) { | |
5927 | rt2800_rfcsr_write(rt2x00dev, 31, 0x14); | |
5928 | ||
5929 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
5930 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | |
5931 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
5932 | ||
5933 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
5934 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
5935 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | |
5936 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { | |
3e38d3da GJ |
5937 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, |
5938 | &eeprom); | |
c9a221b2 SG |
5939 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) |
5940 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
5941 | else | |
5942 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); | |
5943 | } | |
5944 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
5945 | ||
5946 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
5947 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
5948 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
5949 | } | |
c5b3c350 SG |
5950 | |
5951 | rt2800_rx_filter_calibration(rt2x00dev); | |
5de5a1f4 SG |
5952 | |
5953 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || | |
5954 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | |
5955 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) | |
5956 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | |
d9517f2f SG |
5957 | |
5958 | rt2800_led_open_drain_enable(rt2x00dev); | |
da8064c2 | 5959 | rt2800_normal_mode_setup_3xxx(rt2x00dev); |
d5374ef1 SG |
5960 | } |
5961 | ||
5962 | static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) | |
5963 | { | |
f9cdcbb1 SG |
5964 | u8 rfcsr; |
5965 | ||
ce94ede9 SG |
5966 | rt2800_rf_init_calibration(rt2x00dev, 2); |
5967 | ||
d5374ef1 SG |
5968 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); |
5969 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
5970 | rt2800_rfcsr_write(rt2x00dev, 3, 0x08); | |
5971 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | |
5972 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | |
5973 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); | |
5974 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | |
5975 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | |
5976 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | |
5977 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | |
5978 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | |
5979 | rt2800_rfcsr_write(rt2x00dev, 18, 0x02); | |
5980 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
5981 | rt2800_rfcsr_write(rt2x00dev, 25, 0x83); | |
5982 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | |
5983 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | |
5984 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
5985 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | |
5986 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
5987 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
5988 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | |
5989 | rt2800_rfcsr_write(rt2x00dev, 34, 0x05); | |
5990 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
5991 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
5992 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | |
5993 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | |
5994 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | |
5995 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | |
5996 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | |
5997 | rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); | |
5998 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | |
5999 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | |
6000 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | |
6001 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | |
6002 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
6003 | rt2800_rfcsr_write(rt2x00dev, 49, 0x98); | |
6004 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | |
6005 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | |
6006 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | |
6007 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | |
6008 | rt2800_rfcsr_write(rt2x00dev, 56, 0x02); | |
6009 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | |
6010 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | |
6011 | rt2800_rfcsr_write(rt2x00dev, 59, 0x09); | |
6012 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
6013 | rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); | |
f9cdcbb1 SG |
6014 | |
6015 | rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr); | |
6016 | rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); | |
6017 | rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); | |
d9517f2f SG |
6018 | |
6019 | rt2800_led_open_drain_enable(rt2x00dev); | |
da8064c2 | 6020 | rt2800_normal_mode_setup_3xxx(rt2x00dev); |
d5374ef1 SG |
6021 | } |
6022 | ||
6023 | static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) | |
6024 | { | |
ce94ede9 SG |
6025 | rt2800_rf_init_calibration(rt2x00dev, 30); |
6026 | ||
d5374ef1 SG |
6027 | rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); |
6028 | rt2800_rfcsr_write(rt2x00dev, 1, 0x23); | |
6029 | rt2800_rfcsr_write(rt2x00dev, 2, 0x50); | |
6030 | rt2800_rfcsr_write(rt2x00dev, 3, 0x18); | |
6031 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | |
6032 | rt2800_rfcsr_write(rt2x00dev, 5, 0x00); | |
6033 | rt2800_rfcsr_write(rt2x00dev, 6, 0x33); | |
6034 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
6035 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); | |
6036 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | |
6037 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); | |
6038 | rt2800_rfcsr_write(rt2x00dev, 11, 0x42); | |
6039 | rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); | |
6040 | rt2800_rfcsr_write(rt2x00dev, 13, 0x00); | |
6041 | rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); | |
6042 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
6043 | rt2800_rfcsr_write(rt2x00dev, 16, 0x01); | |
6044 | rt2800_rfcsr_write(rt2x00dev, 18, 0x45); | |
6045 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
6046 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | |
6047 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | |
6048 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
6049 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | |
6050 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | |
6051 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
6052 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | |
6053 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | |
6054 | rt2800_rfcsr_write(rt2x00dev, 28, 0x03); | |
6055 | rt2800_rfcsr_write(rt2x00dev, 29, 0x00); | |
6056 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | |
6057 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
6058 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
6059 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | |
6060 | rt2800_rfcsr_write(rt2x00dev, 34, 0x01); | |
6061 | rt2800_rfcsr_write(rt2x00dev, 35, 0x03); | |
6062 | rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); | |
6063 | rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); | |
6064 | rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); | |
6065 | rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); | |
6066 | rt2800_rfcsr_write(rt2x00dev, 40, 0x33); | |
6067 | rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); | |
6068 | rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); | |
6069 | rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); | |
6070 | rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); | |
6071 | rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); | |
6072 | rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); | |
6073 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); | |
6074 | rt2800_rfcsr_write(rt2x00dev, 48, 0x14); | |
6075 | rt2800_rfcsr_write(rt2x00dev, 49, 0x00); | |
6076 | rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); | |
6077 | rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); | |
6078 | rt2800_rfcsr_write(rt2x00dev, 52, 0x00); | |
6079 | rt2800_rfcsr_write(rt2x00dev, 53, 0x52); | |
6080 | rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); | |
6081 | rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); | |
6082 | rt2800_rfcsr_write(rt2x00dev, 56, 0x00); | |
6083 | rt2800_rfcsr_write(rt2x00dev, 57, 0x52); | |
6084 | rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); | |
6085 | rt2800_rfcsr_write(rt2x00dev, 59, 0x00); | |
6086 | rt2800_rfcsr_write(rt2x00dev, 60, 0x00); | |
6087 | rt2800_rfcsr_write(rt2x00dev, 61, 0x00); | |
6088 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | |
6089 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | |
c5b3c350 SG |
6090 | |
6091 | rt2800_rx_filter_calibration(rt2x00dev); | |
d9517f2f | 6092 | rt2800_led_open_drain_enable(rt2x00dev); |
da8064c2 | 6093 | rt2800_normal_mode_setup_3xxx(rt2x00dev); |
d5374ef1 SG |
6094 | } |
6095 | ||
6096 | static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) | |
6097 | { | |
2971e66f SG |
6098 | u32 reg; |
6099 | ||
ce94ede9 SG |
6100 | rt2800_rf_init_calibration(rt2x00dev, 30); |
6101 | ||
d5374ef1 SG |
6102 | rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); |
6103 | rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); | |
6104 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | |
6105 | rt2800_rfcsr_write(rt2x00dev, 3, 0x62); | |
6106 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
6107 | rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); | |
6108 | rt2800_rfcsr_write(rt2x00dev, 6, 0x42); | |
6109 | rt2800_rfcsr_write(rt2x00dev, 7, 0x34); | |
6110 | rt2800_rfcsr_write(rt2x00dev, 8, 0x00); | |
6111 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | |
6112 | rt2800_rfcsr_write(rt2x00dev, 10, 0x61); | |
6113 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
6114 | rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); | |
6115 | rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); | |
6116 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
6117 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | |
6118 | rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); | |
6119 | rt2800_rfcsr_write(rt2x00dev, 17, 0x94); | |
6120 | rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); | |
6121 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); | |
6122 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); | |
6123 | rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); | |
6124 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
6125 | rt2800_rfcsr_write(rt2x00dev, 23, 0x14); | |
6126 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | |
6127 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | |
6128 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
6129 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
6130 | rt2800_rfcsr_write(rt2x00dev, 28, 0x41); | |
6131 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | |
6132 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | |
6133 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | |
2971e66f SG |
6134 | |
6135 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
6136 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
6137 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
c5b3c350 SG |
6138 | |
6139 | rt2800_rx_filter_calibration(rt2x00dev); | |
5de5a1f4 SG |
6140 | |
6141 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) | |
6142 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | |
d9517f2f SG |
6143 | |
6144 | rt2800_led_open_drain_enable(rt2x00dev); | |
da8064c2 | 6145 | rt2800_normal_mode_setup_3xxx(rt2x00dev); |
d5374ef1 SG |
6146 | } |
6147 | ||
6148 | static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) | |
6149 | { | |
87d91db9 SG |
6150 | u8 rfcsr; |
6151 | u32 reg; | |
6152 | ||
ce94ede9 SG |
6153 | rt2800_rf_init_calibration(rt2x00dev, 30); |
6154 | ||
d5374ef1 SG |
6155 | rt2800_rfcsr_write(rt2x00dev, 0, 0x70); |
6156 | rt2800_rfcsr_write(rt2x00dev, 1, 0x81); | |
6157 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | |
6158 | rt2800_rfcsr_write(rt2x00dev, 3, 0x02); | |
6159 | rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); | |
6160 | rt2800_rfcsr_write(rt2x00dev, 5, 0x05); | |
6161 | rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); | |
6162 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | |
6163 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | |
6164 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
6165 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | |
6166 | rt2800_rfcsr_write(rt2x00dev, 12, 0x70); | |
6167 | rt2800_rfcsr_write(rt2x00dev, 13, 0x65); | |
6168 | rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); | |
6169 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | |
6170 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | |
6171 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | |
6172 | rt2800_rfcsr_write(rt2x00dev, 18, 0xac); | |
6173 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | |
6174 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | |
6175 | rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); | |
6176 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
6177 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); | |
6178 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
6179 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | |
6180 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
6181 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
6182 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
6183 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | |
6184 | rt2800_rfcsr_write(rt2x00dev, 30, 0x09); | |
6185 | rt2800_rfcsr_write(rt2x00dev, 31, 0x10); | |
87d91db9 SG |
6186 | |
6187 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
6188 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | |
6189 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
6190 | ||
6191 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
6192 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
6193 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
6194 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
6195 | msleep(1); | |
6196 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
6197 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); | |
6198 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
6199 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
c5b3c350 SG |
6200 | |
6201 | rt2800_rx_filter_calibration(rt2x00dev); | |
d9517f2f | 6202 | rt2800_led_open_drain_enable(rt2x00dev); |
da8064c2 | 6203 | rt2800_normal_mode_setup_3xxx(rt2x00dev); |
d5374ef1 SG |
6204 | } |
6205 | ||
d63f7e8c GJ |
6206 | static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) |
6207 | { | |
6208 | u8 bbp; | |
6209 | bool txbf_enabled = false; /* FIXME */ | |
6210 | ||
6211 | rt2800_bbp_read(rt2x00dev, 105, &bbp); | |
6212 | if (rt2x00dev->default_ant.rx_chain_num == 1) | |
6213 | rt2x00_set_field8(&bbp, BBP105_MLD, 0); | |
6214 | else | |
6215 | rt2x00_set_field8(&bbp, BBP105_MLD, 1); | |
6216 | rt2800_bbp_write(rt2x00dev, 105, bbp); | |
6217 | ||
6218 | rt2800_bbp4_mac_if_ctrl(rt2x00dev); | |
6219 | ||
6220 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
6221 | rt2800_bbp_write(rt2x00dev, 82, 0x82); | |
6222 | rt2800_bbp_write(rt2x00dev, 106, 0x05); | |
6223 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
6224 | rt2800_bbp_write(rt2x00dev, 88, 0x90); | |
6225 | rt2800_bbp_write(rt2x00dev, 148, 0xc8); | |
6226 | rt2800_bbp_write(rt2x00dev, 47, 0x48); | |
6227 | rt2800_bbp_write(rt2x00dev, 120, 0x50); | |
6228 | ||
6229 | if (txbf_enabled) | |
6230 | rt2800_bbp_write(rt2x00dev, 163, 0xbd); | |
6231 | else | |
6232 | rt2800_bbp_write(rt2x00dev, 163, 0x9d); | |
6233 | ||
6234 | /* SNR mapping */ | |
6235 | rt2800_bbp_write(rt2x00dev, 142, 6); | |
6236 | rt2800_bbp_write(rt2x00dev, 143, 160); | |
6237 | rt2800_bbp_write(rt2x00dev, 142, 7); | |
6238 | rt2800_bbp_write(rt2x00dev, 143, 161); | |
6239 | rt2800_bbp_write(rt2x00dev, 142, 8); | |
6240 | rt2800_bbp_write(rt2x00dev, 143, 162); | |
6241 | ||
6242 | /* ADC/DAC control */ | |
6243 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
6244 | ||
6245 | /* RX AGC energy lower bound in log2 */ | |
6246 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
6247 | ||
6248 | /* FIXME: BBP 105 owerwrite? */ | |
6249 | rt2800_bbp_write(rt2x00dev, 105, 0x04); | |
f42b0465 | 6250 | |
d63f7e8c GJ |
6251 | } |
6252 | ||
ab7078ac GJ |
6253 | static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) |
6254 | { | |
6255 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | |
6256 | u32 reg; | |
6257 | u8 rfcsr; | |
6258 | ||
6259 | /* Disable GPIO #4 and #7 function for LAN PE control */ | |
6260 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
6261 | rt2x00_set_field32(®, GPIO_SWITCH_4, 0); | |
6262 | rt2x00_set_field32(®, GPIO_SWITCH_7, 0); | |
6263 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
6264 | ||
6265 | /* Initialize default register values */ | |
6266 | rt2800_rfcsr_write(rt2x00dev, 1, 0x03); | |
6267 | rt2800_rfcsr_write(rt2x00dev, 3, 0x80); | |
6268 | rt2800_rfcsr_write(rt2x00dev, 5, 0x00); | |
6269 | rt2800_rfcsr_write(rt2x00dev, 6, 0x40); | |
6270 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); | |
6271 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | |
6272 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); | |
6273 | rt2800_rfcsr_write(rt2x00dev, 11, 0x40); | |
6274 | rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); | |
6275 | rt2800_rfcsr_write(rt2x00dev, 13, 0x12); | |
6276 | rt2800_rfcsr_write(rt2x00dev, 18, 0x40); | |
6277 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
6278 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | |
6279 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
6280 | rt2800_rfcsr_write(rt2x00dev, 32, 0x78); | |
6281 | rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); | |
6282 | rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); | |
6283 | rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); | |
6284 | rt2800_rfcsr_write(rt2x00dev, 38, 0x86); | |
6285 | rt2800_rfcsr_write(rt2x00dev, 39, 0x23); | |
6286 | rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); | |
6287 | rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); | |
6288 | rt2800_rfcsr_write(rt2x00dev, 46, 0x60); | |
6289 | rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); | |
6290 | rt2800_rfcsr_write(rt2x00dev, 50, 0x86); | |
6291 | rt2800_rfcsr_write(rt2x00dev, 51, 0x75); | |
6292 | rt2800_rfcsr_write(rt2x00dev, 52, 0x45); | |
6293 | rt2800_rfcsr_write(rt2x00dev, 53, 0x18); | |
6294 | rt2800_rfcsr_write(rt2x00dev, 54, 0x18); | |
6295 | rt2800_rfcsr_write(rt2x00dev, 55, 0x18); | |
6296 | rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); | |
6297 | rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); | |
6298 | ||
6299 | /* Initiate calibration */ | |
6300 | /* TODO: use rt2800_rf_init_calibration ? */ | |
6301 | rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); | |
6302 | rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); | |
6303 | rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); | |
6304 | ||
6305 | rt2800_adjust_freq_offset(rt2x00dev); | |
6306 | ||
6307 | rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); | |
6308 | rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); | |
6309 | rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); | |
6310 | ||
6311 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
6312 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
6313 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
6314 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
6315 | usleep_range(1000, 1500); | |
6316 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
6317 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); | |
6318 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
6319 | ||
6320 | /* Set initial values for RX filter calibration */ | |
6321 | drv_data->calibration_bw20 = 0x1f; | |
6322 | drv_data->calibration_bw40 = 0x2f; | |
6323 | ||
6324 | /* Save BBP 25 & 26 values for later use in channel switching */ | |
6325 | rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); | |
6326 | rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); | |
6327 | ||
6328 | rt2800_led_open_drain_enable(rt2x00dev); | |
6329 | rt2800_normal_mode_setup_3593(rt2x00dev); | |
6330 | ||
d63f7e8c | 6331 | rt3593_post_bbp_init(rt2x00dev); |
ab7078ac GJ |
6332 | |
6333 | /* TODO: enable stream mode support */ | |
6334 | } | |
6335 | ||
d5374ef1 SG |
6336 | static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) |
6337 | { | |
ce94ede9 SG |
6338 | rt2800_rf_init_calibration(rt2x00dev, 2); |
6339 | ||
d5374ef1 SG |
6340 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); |
6341 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
6342 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | |
6343 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | |
6344 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6345 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | |
6346 | else | |
6347 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | |
6348 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
6349 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | |
6350 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | |
6351 | rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); | |
6352 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | |
6353 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | |
6354 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
6355 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | |
6356 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | |
6357 | rt2800_rfcsr_write(rt2x00dev, 19, 0x00); | |
6358 | ||
6359 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | |
6360 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | |
6361 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
6362 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | |
6363 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | |
6364 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6365 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
6366 | else | |
6367 | rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); | |
6368 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | |
6369 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | |
6370 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
6371 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
6372 | ||
6373 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | |
6374 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
6375 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
6376 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | |
6377 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | |
6378 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
6379 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
6380 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | |
6381 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | |
6382 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | |
6383 | ||
6384 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6385 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | |
6386 | else | |
6387 | rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); | |
6388 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | |
6389 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); | |
6390 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); | |
6391 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | |
6392 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | |
6393 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6394 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | |
6395 | else | |
6396 | rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); | |
6397 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | |
6398 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
6399 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | |
6400 | ||
6401 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | |
6402 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6403 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | |
6404 | else | |
6405 | rt2800_rfcsr_write(rt2x00dev, 53, 0x84); | |
6406 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | |
6407 | rt2800_rfcsr_write(rt2x00dev, 55, 0x44); | |
6408 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | |
6409 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | |
6410 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | |
6411 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | |
6412 | ||
6413 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
6414 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
6415 | rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); | |
6416 | else | |
6417 | rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); | |
6418 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | |
6419 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | |
f7df8fe5 SG |
6420 | |
6421 | rt2800_normal_mode_setup_5xxx(rt2x00dev); | |
d9517f2f SG |
6422 | |
6423 | rt2800_led_open_drain_enable(rt2x00dev); | |
d5374ef1 SG |
6424 | } |
6425 | ||
6426 | static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) | |
6427 | { | |
ce94ede9 SG |
6428 | rt2800_rf_init_calibration(rt2x00dev, 2); |
6429 | ||
d5374ef1 SG |
6430 | rt2800_rfcsr_write(rt2x00dev, 1, 0x17); |
6431 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
6432 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | |
6433 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | |
6434 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | |
6435 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
6436 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | |
6437 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | |
6438 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | |
6439 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | |
6440 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | |
6441 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
6442 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | |
6443 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | |
6444 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); | |
6445 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | |
6446 | rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); | |
6447 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
6448 | rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); | |
6449 | rt2800_rfcsr_write(rt2x00dev, 24, 0x44); | |
6450 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
6451 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | |
6452 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | |
6453 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
6454 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
6455 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | |
6456 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
6457 | rt2800_rfcsr_write(rt2x00dev, 32, 0x20); | |
6458 | rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); | |
6459 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | |
6460 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
6461 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
6462 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | |
6463 | rt2800_rfcsr_write(rt2x00dev, 38, 0x89); | |
6464 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | |
6465 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); | |
6466 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | |
6467 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | |
6468 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); | |
6469 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | |
6470 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | |
6471 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | |
6472 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); | |
6473 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
6474 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | |
6475 | rt2800_rfcsr_write(rt2x00dev, 50, 0x94); | |
6476 | rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); | |
6477 | rt2800_rfcsr_write(rt2x00dev, 52, 0x48); | |
6478 | rt2800_rfcsr_write(rt2x00dev, 53, 0x44); | |
6479 | rt2800_rfcsr_write(rt2x00dev, 54, 0x38); | |
6480 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | |
6481 | rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); | |
6482 | rt2800_rfcsr_write(rt2x00dev, 57, 0x00); | |
6483 | rt2800_rfcsr_write(rt2x00dev, 58, 0x39); | |
6484 | rt2800_rfcsr_write(rt2x00dev, 59, 0x07); | |
6485 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
6486 | rt2800_rfcsr_write(rt2x00dev, 61, 0x91); | |
6487 | rt2800_rfcsr_write(rt2x00dev, 62, 0x39); | |
6488 | rt2800_rfcsr_write(rt2x00dev, 63, 0x07); | |
f7df8fe5 SG |
6489 | |
6490 | rt2800_normal_mode_setup_5xxx(rt2x00dev); | |
d9517f2f SG |
6491 | |
6492 | rt2800_led_open_drain_enable(rt2x00dev); | |
d5374ef1 SG |
6493 | } |
6494 | ||
0c9e5fb9 SG |
6495 | static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) |
6496 | { | |
ce94ede9 SG |
6497 | rt2800_rf_init_calibration(rt2x00dev, 30); |
6498 | ||
0c9e5fb9 SG |
6499 | rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); |
6500 | rt2800_rfcsr_write(rt2x00dev, 3, 0x08); | |
6501 | rt2800_rfcsr_write(rt2x00dev, 3, 0x08); | |
6502 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | |
6503 | rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); | |
6504 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
6505 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | |
6506 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
6507 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | |
6508 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | |
6509 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); | |
6510 | rt2800_rfcsr_write(rt2x00dev, 20, 0x10); | |
6511 | rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); | |
6512 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | |
6513 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
6514 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
6515 | rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); | |
6516 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | |
6517 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
6518 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); | |
6519 | rt2800_rfcsr_write(rt2x00dev, 53, 0x22); | |
6520 | rt2800_rfcsr_write(rt2x00dev, 63, 0x07); | |
6521 | ||
6522 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
6523 | msleep(1); | |
6524 | ||
6525 | rt2800_adjust_freq_offset(rt2x00dev); | |
c630ccf1 | 6526 | |
c630ccf1 SG |
6527 | /* Enable DC filter */ |
6528 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) | |
6529 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | |
6530 | ||
f7df8fe5 | 6531 | rt2800_normal_mode_setup_5xxx(rt2x00dev); |
5de5a1f4 SG |
6532 | |
6533 | if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) | |
6534 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | |
d9517f2f SG |
6535 | |
6536 | rt2800_led_open_drain_enable(rt2x00dev); | |
0c9e5fb9 SG |
6537 | } |
6538 | ||
074f2529 | 6539 | static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
fcf51541 | 6540 | { |
d5374ef1 SG |
6541 | if (rt2800_is_305x_soc(rt2x00dev)) { |
6542 | rt2800_init_rfcsr_305x_soc(rt2x00dev); | |
074f2529 | 6543 | return; |
d5374ef1 SG |
6544 | } |
6545 | ||
6546 | switch (rt2x00dev->chip.rt) { | |
6547 | case RT3070: | |
6548 | case RT3071: | |
6549 | case RT3090: | |
6550 | rt2800_init_rfcsr_30xx(rt2x00dev); | |
6551 | break; | |
6552 | case RT3290: | |
6553 | rt2800_init_rfcsr_3290(rt2x00dev); | |
6554 | break; | |
6555 | case RT3352: | |
6556 | rt2800_init_rfcsr_3352(rt2x00dev); | |
6557 | break; | |
6558 | case RT3390: | |
6559 | rt2800_init_rfcsr_3390(rt2x00dev); | |
6560 | break; | |
6561 | case RT3572: | |
6562 | rt2800_init_rfcsr_3572(rt2x00dev); | |
6563 | break; | |
ab7078ac GJ |
6564 | case RT3593: |
6565 | rt2800_init_rfcsr_3593(rt2x00dev); | |
6566 | break; | |
d5374ef1 SG |
6567 | case RT5390: |
6568 | rt2800_init_rfcsr_5390(rt2x00dev); | |
6569 | break; | |
6570 | case RT5392: | |
6571 | rt2800_init_rfcsr_5392(rt2x00dev); | |
6572 | break; | |
0c9e5fb9 SG |
6573 | case RT5592: |
6574 | rt2800_init_rfcsr_5592(rt2x00dev); | |
074f2529 | 6575 | break; |
8cdd15e0 | 6576 | } |
fcf51541 | 6577 | } |
b9a07ae9 ID |
6578 | |
6579 | int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) | |
6580 | { | |
6581 | u32 reg; | |
6582 | u16 word; | |
6583 | ||
6584 | /* | |
6585 | * Initialize all registers. | |
6586 | */ | |
6587 | if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || | |
c630ccf1 | 6588 | rt2800_init_registers(rt2x00dev))) |
b9a07ae9 ID |
6589 | return -EIO; |
6590 | ||
6591 | /* | |
6592 | * Send signal to firmware during boot time. | |
6593 | */ | |
c630ccf1 SG |
6594 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
6595 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
6596 | if (rt2x00_is_usb(rt2x00dev)) { | |
6597 | rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); | |
6598 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); | |
6599 | } | |
6600 | msleep(1); | |
6601 | ||
a1ef5039 SG |
6602 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || |
6603 | rt2800_wait_bbp_ready(rt2x00dev))) | |
c630ccf1 | 6604 | return -EIO; |
b9a07ae9 | 6605 | |
a1ef5039 | 6606 | rt2800_init_bbp(rt2x00dev); |
074f2529 SG |
6607 | rt2800_init_rfcsr(rt2x00dev); |
6608 | ||
b9a07ae9 ID |
6609 | if (rt2x00_is_usb(rt2x00dev) && |
6610 | (rt2x00_rt(rt2x00dev, RT3070) || | |
6611 | rt2x00_rt(rt2x00dev, RT3071) || | |
6612 | rt2x00_rt(rt2x00dev, RT3572))) { | |
6613 | udelay(200); | |
6614 | rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); | |
6615 | udelay(10); | |
6616 | } | |
6617 | ||
6618 | /* | |
6619 | * Enable RX. | |
6620 | */ | |
6621 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
6622 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
6623 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
6624 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
6625 | ||
6626 | udelay(50); | |
6627 | ||
6628 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
6629 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); | |
6630 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); | |
6631 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); | |
6632 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
6633 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
6634 | ||
6635 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
6636 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
6637 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); | |
6638 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
6639 | ||
6640 | /* | |
6641 | * Initialize LED control | |
6642 | */ | |
3e38d3da | 6643 | rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); |
38c8a566 | 6644 | rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, |
b9a07ae9 ID |
6645 | word & 0xff, (word >> 8) & 0xff); |
6646 | ||
3e38d3da | 6647 | rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); |
38c8a566 | 6648 | rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, |
b9a07ae9 ID |
6649 | word & 0xff, (word >> 8) & 0xff); |
6650 | ||
3e38d3da | 6651 | rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); |
38c8a566 | 6652 | rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, |
b9a07ae9 ID |
6653 | word & 0xff, (word >> 8) & 0xff); |
6654 | ||
6655 | return 0; | |
6656 | } | |
6657 | EXPORT_SYMBOL_GPL(rt2800_enable_radio); | |
6658 | ||
6659 | void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) | |
6660 | { | |
6661 | u32 reg; | |
6662 | ||
f7b395e9 | 6663 | rt2800_disable_wpdma(rt2x00dev); |
b9a07ae9 ID |
6664 | |
6665 | /* Wait for DMA, ignore error */ | |
6666 | rt2800_wait_wpdma_ready(rt2x00dev); | |
6667 | ||
6668 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
6669 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); | |
6670 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
6671 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
b9a07ae9 ID |
6672 | } |
6673 | EXPORT_SYMBOL_GPL(rt2800_disable_radio); | |
2ce33995 | 6674 | |
30e84034 BZ |
6675 | int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) |
6676 | { | |
6677 | u32 reg; | |
a89534ed | 6678 | u16 efuse_ctrl_reg; |
30e84034 | 6679 | |
a89534ed WH |
6680 | if (rt2x00_rt(rt2x00dev, RT3290)) |
6681 | efuse_ctrl_reg = EFUSE_CTRL_3290; | |
6682 | else | |
6683 | efuse_ctrl_reg = EFUSE_CTRL; | |
30e84034 | 6684 | |
a89534ed | 6685 | rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); |
30e84034 BZ |
6686 | return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); |
6687 | } | |
6688 | EXPORT_SYMBOL_GPL(rt2800_efuse_detect); | |
6689 | ||
6690 | static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) | |
6691 | { | |
6692 | u32 reg; | |
a89534ed WH |
6693 | u16 efuse_ctrl_reg; |
6694 | u16 efuse_data0_reg; | |
6695 | u16 efuse_data1_reg; | |
6696 | u16 efuse_data2_reg; | |
6697 | u16 efuse_data3_reg; | |
6698 | ||
6699 | if (rt2x00_rt(rt2x00dev, RT3290)) { | |
6700 | efuse_ctrl_reg = EFUSE_CTRL_3290; | |
6701 | efuse_data0_reg = EFUSE_DATA0_3290; | |
6702 | efuse_data1_reg = EFUSE_DATA1_3290; | |
6703 | efuse_data2_reg = EFUSE_DATA2_3290; | |
6704 | efuse_data3_reg = EFUSE_DATA3_3290; | |
6705 | } else { | |
6706 | efuse_ctrl_reg = EFUSE_CTRL; | |
6707 | efuse_data0_reg = EFUSE_DATA0; | |
6708 | efuse_data1_reg = EFUSE_DATA1; | |
6709 | efuse_data2_reg = EFUSE_DATA2; | |
6710 | efuse_data3_reg = EFUSE_DATA3; | |
6711 | } | |
31a4cf1f GW |
6712 | mutex_lock(&rt2x00dev->csr_mutex); |
6713 | ||
a89534ed | 6714 | rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); |
30e84034 BZ |
6715 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
6716 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); | |
6717 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); | |
a89534ed | 6718 | rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); |
30e84034 BZ |
6719 | |
6720 | /* Wait until the EEPROM has been loaded */ | |
a89534ed | 6721 | rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); |
30e84034 | 6722 | /* Apparently the data is read from end to start */ |
a89534ed | 6723 | rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); |
daabead1 | 6724 | /* The returned value is in CPU order, but eeprom is le */ |
68fa64ef | 6725 | *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); |
a89534ed | 6726 | rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); |
daabead1 | 6727 | *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); |
a89534ed | 6728 | rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); |
daabead1 | 6729 | *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); |
a89534ed | 6730 | rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); |
daabead1 | 6731 | *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); |
31a4cf1f GW |
6732 | |
6733 | mutex_unlock(&rt2x00dev->csr_mutex); | |
30e84034 BZ |
6734 | } |
6735 | ||
a02308e9 | 6736 | int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
30e84034 BZ |
6737 | { |
6738 | unsigned int i; | |
6739 | ||
6740 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) | |
6741 | rt2800_efuse_read(rt2x00dev, i); | |
a02308e9 GJ |
6742 | |
6743 | return 0; | |
30e84034 BZ |
6744 | } |
6745 | EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); | |
6746 | ||
a3f1625d GJ |
6747 | static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) |
6748 | { | |
6749 | u16 word; | |
6750 | ||
6316c786 GJ |
6751 | if (rt2x00_rt(rt2x00dev, RT3593)) |
6752 | return 0; | |
6753 | ||
a3f1625d GJ |
6754 | rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word); |
6755 | if ((word & 0x00ff) != 0x00ff) | |
6756 | return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); | |
6757 | ||
6758 | return 0; | |
6759 | } | |
6760 | ||
6761 | static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) | |
6762 | { | |
6763 | u16 word; | |
6764 | ||
6316c786 GJ |
6765 | if (rt2x00_rt(rt2x00dev, RT3593)) |
6766 | return 0; | |
6767 | ||
a3f1625d GJ |
6768 | rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word); |
6769 | if ((word & 0x00ff) != 0x00ff) | |
6770 | return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); | |
6771 | ||
6772 | return 0; | |
6773 | } | |
6774 | ||
ad417a53 | 6775 | static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
38bd7b8a | 6776 | { |
77c06c2c | 6777 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; |
38bd7b8a BZ |
6778 | u16 word; |
6779 | u8 *mac; | |
6780 | u8 default_lna_gain; | |
a02308e9 | 6781 | int retval; |
38bd7b8a | 6782 | |
ad417a53 GW |
6783 | /* |
6784 | * Read the EEPROM. | |
6785 | */ | |
a02308e9 GJ |
6786 | retval = rt2800_read_eeprom(rt2x00dev); |
6787 | if (retval) | |
6788 | return retval; | |
ad417a53 | 6789 | |
38bd7b8a BZ |
6790 | /* |
6791 | * Start validation of the data that has been read. | |
6792 | */ | |
3e38d3da | 6793 | mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
38bd7b8a | 6794 | if (!is_valid_ether_addr(mac)) { |
f4f7f414 | 6795 | eth_random_addr(mac); |
ec9c4989 | 6796 | rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); |
38bd7b8a BZ |
6797 | } |
6798 | ||
3e38d3da | 6799 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); |
38bd7b8a | 6800 | if (word == 0xffff) { |
38c8a566 RJH |
6801 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); |
6802 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); | |
6803 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); | |
3e38d3da | 6804 | rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); |
ec9c4989 | 6805 | rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); |
49e721ec | 6806 | } else if (rt2x00_rt(rt2x00dev, RT2860) || |
e148b4c8 | 6807 | rt2x00_rt(rt2x00dev, RT2872)) { |
38bd7b8a BZ |
6808 | /* |
6809 | * There is a max of 2 RX streams for RT28x0 series | |
6810 | */ | |
38c8a566 RJH |
6811 | if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) |
6812 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); | |
3e38d3da | 6813 | rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); |
38bd7b8a BZ |
6814 | } |
6815 | ||
3e38d3da | 6816 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); |
38bd7b8a | 6817 | if (word == 0xffff) { |
38c8a566 RJH |
6818 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); |
6819 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); | |
6820 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); | |
6821 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); | |
6822 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); | |
6823 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); | |
6824 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); | |
6825 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); | |
6826 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); | |
6827 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); | |
6828 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); | |
6829 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); | |
6830 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); | |
6831 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); | |
6832 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); | |
3e38d3da | 6833 | rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); |
ec9c4989 | 6834 | rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); |
38bd7b8a BZ |
6835 | } |
6836 | ||
3e38d3da | 6837 | rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); |
38bd7b8a BZ |
6838 | if ((word & 0x00ff) == 0x00ff) { |
6839 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
3e38d3da | 6840 | rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
ec9c4989 | 6841 | rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); |
ec2d1791 GW |
6842 | } |
6843 | if ((word & 0xff00) == 0xff00) { | |
38bd7b8a BZ |
6844 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, |
6845 | LED_MODE_TXRX_ACTIVITY); | |
6846 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); | |
3e38d3da GJ |
6847 | rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
6848 | rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); | |
6849 | rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); | |
6850 | rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); | |
ec9c4989 | 6851 | rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); |
38bd7b8a BZ |
6852 | } |
6853 | ||
6854 | /* | |
6855 | * During the LNA validation we are going to use | |
6856 | * lna0 as correct value. Note that EEPROM_LNA | |
6857 | * is never validated. | |
6858 | */ | |
3e38d3da | 6859 | rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word); |
38bd7b8a BZ |
6860 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); |
6861 | ||
3e38d3da | 6862 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); |
38bd7b8a BZ |
6863 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) |
6864 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); | |
6865 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) | |
6866 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); | |
3e38d3da | 6867 | rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); |
38bd7b8a | 6868 | |
a3f1625d | 6869 | drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); |
77c06c2c | 6870 | |
3e38d3da | 6871 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); |
38bd7b8a BZ |
6872 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) |
6873 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); | |
f36bb0ca GJ |
6874 | if (!rt2x00_rt(rt2x00dev, RT3593)) { |
6875 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || | |
6876 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) | |
6877 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, | |
6878 | default_lna_gain); | |
6879 | } | |
3e38d3da | 6880 | rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); |
38bd7b8a | 6881 | |
a3f1625d | 6882 | drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); |
77c06c2c | 6883 | |
3e38d3da | 6884 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); |
38bd7b8a BZ |
6885 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) |
6886 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); | |
6887 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) | |
6888 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); | |
3e38d3da | 6889 | rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); |
38bd7b8a | 6890 | |
3e38d3da | 6891 | rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); |
38bd7b8a BZ |
6892 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) |
6893 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); | |
f36bb0ca GJ |
6894 | if (!rt2x00_rt(rt2x00dev, RT3593)) { |
6895 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || | |
6896 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) | |
6897 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, | |
6898 | default_lna_gain); | |
6899 | } | |
3e38d3da | 6900 | rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); |
38bd7b8a | 6901 | |
f36bb0ca GJ |
6902 | if (rt2x00_rt(rt2x00dev, RT3593)) { |
6903 | rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word); | |
6904 | if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || | |
6905 | rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) | |
6906 | rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, | |
6907 | default_lna_gain); | |
6908 | if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || | |
6909 | rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) | |
6910 | rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, | |
6911 | default_lna_gain); | |
6912 | rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); | |
6913 | } | |
6914 | ||
38bd7b8a BZ |
6915 | return 0; |
6916 | } | |
38bd7b8a | 6917 | |
ad417a53 | 6918 | static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) |
38bd7b8a | 6919 | { |
38bd7b8a BZ |
6920 | u16 value; |
6921 | u16 eeprom; | |
86868b26 | 6922 | u16 rf; |
38bd7b8a | 6923 | |
86868b26 GJ |
6924 | /* |
6925 | * Read EEPROM word for configuration. | |
6926 | */ | |
3e38d3da | 6927 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
86868b26 GJ |
6928 | |
6929 | /* | |
6930 | * Identify RF chipset by EEPROM value | |
6931 | * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field | |
6932 | * RT53xx: defined in "EEPROM_CHIP_ID" field | |
6933 | */ | |
6934 | if (rt2x00_rt(rt2x00dev, RT3290) || | |
6935 | rt2x00_rt(rt2x00dev, RT5390) || | |
6936 | rt2x00_rt(rt2x00dev, RT5392)) | |
3e38d3da | 6937 | rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); |
86868b26 GJ |
6938 | else |
6939 | rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); | |
6940 | ||
6941 | switch (rf) { | |
d331eb51 LF |
6942 | case RF2820: |
6943 | case RF2850: | |
6944 | case RF2720: | |
6945 | case RF2750: | |
6946 | case RF3020: | |
6947 | case RF2020: | |
6948 | case RF3021: | |
6949 | case RF3022: | |
6950 | case RF3052: | |
a89534ed | 6951 | case RF3290: |
d331eb51 | 6952 | case RF3320: |
03839951 | 6953 | case RF3322: |
ccf91bd6 | 6954 | case RF5360: |
d331eb51 | 6955 | case RF5370: |
2ed71884 | 6956 | case RF5372: |
d331eb51 | 6957 | case RF5390: |
cff3d1f0 | 6958 | case RF5392: |
b8863f8b | 6959 | case RF5592: |
d331eb51 LF |
6960 | break; |
6961 | default: | |
ec9c4989 JP |
6962 | rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", |
6963 | rf); | |
38bd7b8a BZ |
6964 | return -ENODEV; |
6965 | } | |
6966 | ||
86868b26 GJ |
6967 | rt2x00_set_rf(rt2x00dev, rf); |
6968 | ||
38bd7b8a BZ |
6969 | /* |
6970 | * Identify default antenna configuration. | |
6971 | */ | |
d96aa640 | 6972 | rt2x00dev->default_ant.tx_chain_num = |
38c8a566 | 6973 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); |
d96aa640 | 6974 | rt2x00dev->default_ant.rx_chain_num = |
38c8a566 | 6975 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); |
38bd7b8a | 6976 | |
3e38d3da | 6977 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
d96aa640 RJH |
6978 | |
6979 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
6980 | rt2x00_rt(rt2x00dev, RT3090) || | |
03839951 | 6981 | rt2x00_rt(rt2x00dev, RT3352) || |
d96aa640 RJH |
6982 | rt2x00_rt(rt2x00dev, RT3390)) { |
6983 | value = rt2x00_get_field16(eeprom, | |
6984 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
6985 | switch (value) { | |
6986 | case 0: | |
6987 | case 1: | |
6988 | case 2: | |
6989 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
6990 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
6991 | break; | |
6992 | case 3: | |
6993 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
6994 | rt2x00dev->default_ant.rx = ANTENNA_B; | |
6995 | break; | |
6996 | } | |
6997 | } else { | |
6998 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
6999 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
7000 | } | |
7001 | ||
0586a11b AA |
7002 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { |
7003 | rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ | |
7004 | rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ | |
7005 | } | |
7006 | ||
38bd7b8a | 7007 | /* |
9328fdac | 7008 | * Determine external LNA informations. |
38bd7b8a | 7009 | */ |
38c8a566 | 7010 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) |
7dab73b3 | 7011 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
38c8a566 | 7012 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) |
7dab73b3 | 7013 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); |
38bd7b8a BZ |
7014 | |
7015 | /* | |
7016 | * Detect if this device has an hardware controlled radio. | |
7017 | */ | |
38c8a566 | 7018 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) |
7dab73b3 | 7019 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
38bd7b8a | 7020 | |
fdbc7b0a GW |
7021 | /* |
7022 | * Detect if this device has Bluetooth co-existence. | |
7023 | */ | |
7024 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) | |
7025 | __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); | |
7026 | ||
9328fdac GW |
7027 | /* |
7028 | * Read frequency offset and RF programming sequence. | |
7029 | */ | |
3e38d3da | 7030 | rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
9328fdac GW |
7031 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); |
7032 | ||
38bd7b8a BZ |
7033 | /* |
7034 | * Store led settings, for correct led behaviour. | |
7035 | */ | |
7036 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
7037 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); | |
7038 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
7039 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); | |
7040 | ||
9328fdac | 7041 | rt2x00dev->led_mcu_reg = eeprom; |
38bd7b8a BZ |
7042 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
7043 | ||
e90c54b2 RJH |
7044 | /* |
7045 | * Check if support EIRP tx power limit feature. | |
7046 | */ | |
3e38d3da | 7047 | rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); |
e90c54b2 RJH |
7048 | |
7049 | if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < | |
7050 | EIRP_MAX_TX_POWER_LIMIT) | |
7dab73b3 | 7051 | __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); |
e90c54b2 | 7052 | |
38bd7b8a BZ |
7053 | return 0; |
7054 | } | |
38bd7b8a | 7055 | |
4da2933f | 7056 | /* |
55f9321a | 7057 | * RF value list for rt28xx |
4da2933f BZ |
7058 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) |
7059 | */ | |
7060 | static const struct rf_channel rf_vals[] = { | |
7061 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, | |
7062 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, | |
7063 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, | |
7064 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, | |
7065 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, | |
7066 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, | |
7067 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, | |
7068 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, | |
7069 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, | |
7070 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, | |
7071 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, | |
7072 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, | |
7073 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, | |
7074 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, | |
7075 | ||
7076 | /* 802.11 UNI / HyperLan 2 */ | |
7077 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, | |
7078 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, | |
7079 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, | |
7080 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, | |
7081 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, | |
7082 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, | |
7083 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, | |
7084 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, | |
7085 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, | |
7086 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, | |
7087 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, | |
7088 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, | |
7089 | ||
7090 | /* 802.11 HyperLan 2 */ | |
7091 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, | |
7092 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, | |
7093 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, | |
7094 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, | |
7095 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, | |
7096 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, | |
7097 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, | |
7098 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, | |
7099 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, | |
7100 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, | |
7101 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, | |
7102 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, | |
7103 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, | |
7104 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, | |
7105 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, | |
7106 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, | |
7107 | ||
7108 | /* 802.11 UNII */ | |
7109 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, | |
7110 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, | |
7111 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, | |
7112 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, | |
7113 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, | |
7114 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, | |
7115 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, | |
7116 | { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, | |
7117 | { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, | |
7118 | { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, | |
7119 | { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, | |
7120 | ||
7121 | /* 802.11 Japan */ | |
7122 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, | |
7123 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, | |
7124 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, | |
7125 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, | |
7126 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, | |
7127 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, | |
7128 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, | |
7129 | }; | |
7130 | ||
7131 | /* | |
55f9321a ID |
7132 | * RF value list for rt3xxx |
7133 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052) | |
4da2933f | 7134 | */ |
55f9321a | 7135 | static const struct rf_channel rf_vals_3x[] = { |
4da2933f BZ |
7136 | {1, 241, 2, 2 }, |
7137 | {2, 241, 2, 7 }, | |
7138 | {3, 242, 2, 2 }, | |
7139 | {4, 242, 2, 7 }, | |
7140 | {5, 243, 2, 2 }, | |
7141 | {6, 243, 2, 7 }, | |
7142 | {7, 244, 2, 2 }, | |
7143 | {8, 244, 2, 7 }, | |
7144 | {9, 245, 2, 2 }, | |
7145 | {10, 245, 2, 7 }, | |
7146 | {11, 246, 2, 2 }, | |
7147 | {12, 246, 2, 7 }, | |
7148 | {13, 247, 2, 2 }, | |
7149 | {14, 248, 2, 4 }, | |
55f9321a ID |
7150 | |
7151 | /* 802.11 UNI / HyperLan 2 */ | |
7152 | {36, 0x56, 0, 4}, | |
7153 | {38, 0x56, 0, 6}, | |
7154 | {40, 0x56, 0, 8}, | |
7155 | {44, 0x57, 0, 0}, | |
7156 | {46, 0x57, 0, 2}, | |
7157 | {48, 0x57, 0, 4}, | |
7158 | {52, 0x57, 0, 8}, | |
7159 | {54, 0x57, 0, 10}, | |
7160 | {56, 0x58, 0, 0}, | |
7161 | {60, 0x58, 0, 4}, | |
7162 | {62, 0x58, 0, 6}, | |
7163 | {64, 0x58, 0, 8}, | |
7164 | ||
7165 | /* 802.11 HyperLan 2 */ | |
7166 | {100, 0x5b, 0, 8}, | |
7167 | {102, 0x5b, 0, 10}, | |
7168 | {104, 0x5c, 0, 0}, | |
7169 | {108, 0x5c, 0, 4}, | |
7170 | {110, 0x5c, 0, 6}, | |
7171 | {112, 0x5c, 0, 8}, | |
7172 | {116, 0x5d, 0, 0}, | |
7173 | {118, 0x5d, 0, 2}, | |
7174 | {120, 0x5d, 0, 4}, | |
7175 | {124, 0x5d, 0, 8}, | |
7176 | {126, 0x5d, 0, 10}, | |
7177 | {128, 0x5e, 0, 0}, | |
7178 | {132, 0x5e, 0, 4}, | |
7179 | {134, 0x5e, 0, 6}, | |
7180 | {136, 0x5e, 0, 8}, | |
7181 | {140, 0x5f, 0, 0}, | |
7182 | ||
7183 | /* 802.11 UNII */ | |
7184 | {149, 0x5f, 0, 9}, | |
7185 | {151, 0x5f, 0, 11}, | |
7186 | {153, 0x60, 0, 1}, | |
7187 | {157, 0x60, 0, 5}, | |
7188 | {159, 0x60, 0, 7}, | |
7189 | {161, 0x60, 0, 9}, | |
7190 | {165, 0x61, 0, 1}, | |
7191 | {167, 0x61, 0, 3}, | |
7192 | {169, 0x61, 0, 5}, | |
7193 | {171, 0x61, 0, 7}, | |
7194 | {173, 0x61, 0, 9}, | |
4da2933f BZ |
7195 | }; |
7196 | ||
7848b231 SG |
7197 | static const struct rf_channel rf_vals_5592_xtal20[] = { |
7198 | /* Channel, N, K, mod, R */ | |
7199 | {1, 482, 4, 10, 3}, | |
7200 | {2, 483, 4, 10, 3}, | |
7201 | {3, 484, 4, 10, 3}, | |
7202 | {4, 485, 4, 10, 3}, | |
7203 | {5, 486, 4, 10, 3}, | |
7204 | {6, 487, 4, 10, 3}, | |
7205 | {7, 488, 4, 10, 3}, | |
7206 | {8, 489, 4, 10, 3}, | |
7207 | {9, 490, 4, 10, 3}, | |
7208 | {10, 491, 4, 10, 3}, | |
7209 | {11, 492, 4, 10, 3}, | |
7210 | {12, 493, 4, 10, 3}, | |
7211 | {13, 494, 4, 10, 3}, | |
7212 | {14, 496, 8, 10, 3}, | |
7213 | {36, 172, 8, 12, 1}, | |
7214 | {38, 173, 0, 12, 1}, | |
7215 | {40, 173, 4, 12, 1}, | |
7216 | {42, 173, 8, 12, 1}, | |
7217 | {44, 174, 0, 12, 1}, | |
7218 | {46, 174, 4, 12, 1}, | |
7219 | {48, 174, 8, 12, 1}, | |
7220 | {50, 175, 0, 12, 1}, | |
7221 | {52, 175, 4, 12, 1}, | |
7222 | {54, 175, 8, 12, 1}, | |
7223 | {56, 176, 0, 12, 1}, | |
7224 | {58, 176, 4, 12, 1}, | |
7225 | {60, 176, 8, 12, 1}, | |
7226 | {62, 177, 0, 12, 1}, | |
7227 | {64, 177, 4, 12, 1}, | |
7228 | {100, 183, 4, 12, 1}, | |
7229 | {102, 183, 8, 12, 1}, | |
7230 | {104, 184, 0, 12, 1}, | |
7231 | {106, 184, 4, 12, 1}, | |
7232 | {108, 184, 8, 12, 1}, | |
7233 | {110, 185, 0, 12, 1}, | |
7234 | {112, 185, 4, 12, 1}, | |
7235 | {114, 185, 8, 12, 1}, | |
7236 | {116, 186, 0, 12, 1}, | |
7237 | {118, 186, 4, 12, 1}, | |
7238 | {120, 186, 8, 12, 1}, | |
7239 | {122, 187, 0, 12, 1}, | |
7240 | {124, 187, 4, 12, 1}, | |
7241 | {126, 187, 8, 12, 1}, | |
7242 | {128, 188, 0, 12, 1}, | |
7243 | {130, 188, 4, 12, 1}, | |
7244 | {132, 188, 8, 12, 1}, | |
7245 | {134, 189, 0, 12, 1}, | |
7246 | {136, 189, 4, 12, 1}, | |
7247 | {138, 189, 8, 12, 1}, | |
7248 | {140, 190, 0, 12, 1}, | |
7249 | {149, 191, 6, 12, 1}, | |
7250 | {151, 191, 10, 12, 1}, | |
7251 | {153, 192, 2, 12, 1}, | |
7252 | {155, 192, 6, 12, 1}, | |
7253 | {157, 192, 10, 12, 1}, | |
7254 | {159, 193, 2, 12, 1}, | |
7255 | {161, 193, 6, 12, 1}, | |
7256 | {165, 194, 2, 12, 1}, | |
7257 | {184, 164, 0, 12, 1}, | |
7258 | {188, 164, 4, 12, 1}, | |
7259 | {192, 165, 8, 12, 1}, | |
7260 | {196, 166, 0, 12, 1}, | |
7261 | }; | |
7262 | ||
7263 | static const struct rf_channel rf_vals_5592_xtal40[] = { | |
7264 | /* Channel, N, K, mod, R */ | |
7265 | {1, 241, 2, 10, 3}, | |
7266 | {2, 241, 7, 10, 3}, | |
7267 | {3, 242, 2, 10, 3}, | |
7268 | {4, 242, 7, 10, 3}, | |
7269 | {5, 243, 2, 10, 3}, | |
7270 | {6, 243, 7, 10, 3}, | |
7271 | {7, 244, 2, 10, 3}, | |
7272 | {8, 244, 7, 10, 3}, | |
7273 | {9, 245, 2, 10, 3}, | |
7274 | {10, 245, 7, 10, 3}, | |
7275 | {11, 246, 2, 10, 3}, | |
7276 | {12, 246, 7, 10, 3}, | |
7277 | {13, 247, 2, 10, 3}, | |
7278 | {14, 248, 4, 10, 3}, | |
7279 | {36, 86, 4, 12, 1}, | |
7280 | {38, 86, 6, 12, 1}, | |
7281 | {40, 86, 8, 12, 1}, | |
7282 | {42, 86, 10, 12, 1}, | |
7283 | {44, 87, 0, 12, 1}, | |
7284 | {46, 87, 2, 12, 1}, | |
7285 | {48, 87, 4, 12, 1}, | |
7286 | {50, 87, 6, 12, 1}, | |
7287 | {52, 87, 8, 12, 1}, | |
7288 | {54, 87, 10, 12, 1}, | |
7289 | {56, 88, 0, 12, 1}, | |
7290 | {58, 88, 2, 12, 1}, | |
7291 | {60, 88, 4, 12, 1}, | |
7292 | {62, 88, 6, 12, 1}, | |
7293 | {64, 88, 8, 12, 1}, | |
7294 | {100, 91, 8, 12, 1}, | |
7295 | {102, 91, 10, 12, 1}, | |
7296 | {104, 92, 0, 12, 1}, | |
7297 | {106, 92, 2, 12, 1}, | |
7298 | {108, 92, 4, 12, 1}, | |
7299 | {110, 92, 6, 12, 1}, | |
7300 | {112, 92, 8, 12, 1}, | |
7301 | {114, 92, 10, 12, 1}, | |
7302 | {116, 93, 0, 12, 1}, | |
7303 | {118, 93, 2, 12, 1}, | |
7304 | {120, 93, 4, 12, 1}, | |
7305 | {122, 93, 6, 12, 1}, | |
7306 | {124, 93, 8, 12, 1}, | |
7307 | {126, 93, 10, 12, 1}, | |
7308 | {128, 94, 0, 12, 1}, | |
7309 | {130, 94, 2, 12, 1}, | |
7310 | {132, 94, 4, 12, 1}, | |
7311 | {134, 94, 6, 12, 1}, | |
7312 | {136, 94, 8, 12, 1}, | |
7313 | {138, 94, 10, 12, 1}, | |
7314 | {140, 95, 0, 12, 1}, | |
7315 | {149, 95, 9, 12, 1}, | |
7316 | {151, 95, 11, 12, 1}, | |
7317 | {153, 96, 1, 12, 1}, | |
7318 | {155, 96, 3, 12, 1}, | |
7319 | {157, 96, 5, 12, 1}, | |
7320 | {159, 96, 7, 12, 1}, | |
7321 | {161, 96, 9, 12, 1}, | |
7322 | {165, 97, 1, 12, 1}, | |
7323 | {184, 82, 0, 12, 1}, | |
7324 | {188, 82, 4, 12, 1}, | |
7325 | {192, 82, 8, 12, 1}, | |
7326 | {196, 83, 0, 12, 1}, | |
7327 | }; | |
7328 | ||
c8b9d3dc GJ |
7329 | static const struct rf_channel rf_vals_3053[] = { |
7330 | /* Channel, N, R, K */ | |
7331 | {1, 241, 2, 2}, | |
7332 | {2, 241, 2, 7}, | |
7333 | {3, 242, 2, 2}, | |
7334 | {4, 242, 2, 7}, | |
7335 | {5, 243, 2, 2}, | |
7336 | {6, 243, 2, 7}, | |
7337 | {7, 244, 2, 2}, | |
7338 | {8, 244, 2, 7}, | |
7339 | {9, 245, 2, 2}, | |
7340 | {10, 245, 2, 7}, | |
7341 | {11, 246, 2, 2}, | |
7342 | {12, 246, 2, 7}, | |
7343 | {13, 247, 2, 2}, | |
7344 | {14, 248, 2, 4}, | |
7345 | ||
7346 | {36, 0x56, 0, 4}, | |
7347 | {38, 0x56, 0, 6}, | |
7348 | {40, 0x56, 0, 8}, | |
7349 | {44, 0x57, 0, 0}, | |
7350 | {46, 0x57, 0, 2}, | |
7351 | {48, 0x57, 0, 4}, | |
7352 | {52, 0x57, 0, 8}, | |
7353 | {54, 0x57, 0, 10}, | |
7354 | {56, 0x58, 0, 0}, | |
7355 | {60, 0x58, 0, 4}, | |
7356 | {62, 0x58, 0, 6}, | |
7357 | {64, 0x58, 0, 8}, | |
7358 | ||
7359 | {100, 0x5B, 0, 8}, | |
7360 | {102, 0x5B, 0, 10}, | |
7361 | {104, 0x5C, 0, 0}, | |
7362 | {108, 0x5C, 0, 4}, | |
7363 | {110, 0x5C, 0, 6}, | |
7364 | {112, 0x5C, 0, 8}, | |
7365 | ||
7366 | /* NOTE: Channel 114 has been removed intentionally. | |
7367 | * The EEPROM contains no TX power values for that, | |
7368 | * and it is disabled in the vendor driver as well. | |
7369 | */ | |
7370 | ||
7371 | {116, 0x5D, 0, 0}, | |
7372 | {118, 0x5D, 0, 2}, | |
7373 | {120, 0x5D, 0, 4}, | |
7374 | {124, 0x5D, 0, 8}, | |
7375 | {126, 0x5D, 0, 10}, | |
7376 | {128, 0x5E, 0, 0}, | |
7377 | {132, 0x5E, 0, 4}, | |
7378 | {134, 0x5E, 0, 6}, | |
7379 | {136, 0x5E, 0, 8}, | |
7380 | {140, 0x5F, 0, 0}, | |
7381 | ||
7382 | {149, 0x5F, 0, 9}, | |
7383 | {151, 0x5F, 0, 11}, | |
7384 | {153, 0x60, 0, 1}, | |
7385 | {157, 0x60, 0, 5}, | |
7386 | {159, 0x60, 0, 7}, | |
7387 | {161, 0x60, 0, 9}, | |
7388 | {165, 0x61, 0, 1}, | |
7389 | {167, 0x61, 0, 3}, | |
7390 | {169, 0x61, 0, 5}, | |
7391 | {171, 0x61, 0, 7}, | |
7392 | {173, 0x61, 0, 9}, | |
7393 | }; | |
7394 | ||
ad417a53 | 7395 | static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
4da2933f | 7396 | { |
4da2933f BZ |
7397 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
7398 | struct channel_info *info; | |
8d1331b3 ID |
7399 | char *default_power1; |
7400 | char *default_power2; | |
c0a14369 | 7401 | char *default_power3; |
4da2933f BZ |
7402 | unsigned int i; |
7403 | u16 eeprom; | |
7848b231 | 7404 | u32 reg; |
4da2933f | 7405 | |
93b6bd26 GW |
7406 | /* |
7407 | * Disable powersaving as default on PCI devices. | |
7408 | */ | |
cea90e55 | 7409 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
93b6bd26 GW |
7410 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
7411 | ||
4da2933f BZ |
7412 | /* |
7413 | * Initialize all hw fields. | |
7414 | */ | |
7415 | rt2x00dev->hw->flags = | |
4da2933f BZ |
7416 | IEEE80211_HW_SIGNAL_DBM | |
7417 | IEEE80211_HW_SUPPORTS_PS | | |
1df90809 | 7418 | IEEE80211_HW_PS_NULLFUNC_STACK | |
9d4f09b8 | 7419 | IEEE80211_HW_AMPDU_AGGREGATION | |
84e9e8eb | 7420 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
9d4f09b8 | 7421 | |
5a5b6ed6 HS |
7422 | /* |
7423 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices | |
7424 | * unless we are capable of sending the buffered frames out after the | |
7425 | * DTIM transmission using rt2x00lib_beacondone. This will send out | |
7426 | * multicast and broadcast traffic immediately instead of buffering it | |
7427 | * infinitly and thus dropping it after some time. | |
7428 | */ | |
7429 | if (!rt2x00_is_usb(rt2x00dev)) | |
7430 | rt2x00dev->hw->flags |= | |
7431 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; | |
4da2933f | 7432 | |
4da2933f BZ |
7433 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
7434 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | |
3e38d3da | 7435 | rt2800_eeprom_addr(rt2x00dev, |
4da2933f BZ |
7436 | EEPROM_MAC_ADDR_0)); |
7437 | ||
3f2bee24 HS |
7438 | /* |
7439 | * As rt2800 has a global fallback table we cannot specify | |
7440 | * more then one tx rate per frame but since the hw will | |
7441 | * try several rates (based on the fallback table) we should | |
ba3b9e5e | 7442 | * initialize max_report_rates to the maximum number of rates |
3f2bee24 HS |
7443 | * we are going to try. Otherwise mac80211 will truncate our |
7444 | * reported tx rates and the rc algortihm will end up with | |
7445 | * incorrect data. | |
7446 | */ | |
ba3b9e5e HS |
7447 | rt2x00dev->hw->max_rates = 1; |
7448 | rt2x00dev->hw->max_report_rates = 7; | |
3f2bee24 HS |
7449 | rt2x00dev->hw->max_rate_tries = 1; |
7450 | ||
3e38d3da | 7451 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
4da2933f BZ |
7452 | |
7453 | /* | |
7454 | * Initialize hw_mode information. | |
7455 | */ | |
7456 | spec->supported_bands = SUPPORT_BAND_2GHZ; | |
7457 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
7458 | ||
5122d898 | 7459 | if (rt2x00_rf(rt2x00dev, RF2820) || |
55f9321a | 7460 | rt2x00_rf(rt2x00dev, RF2720)) { |
4da2933f BZ |
7461 | spec->num_channels = 14; |
7462 | spec->channels = rf_vals; | |
55f9321a ID |
7463 | } else if (rt2x00_rf(rt2x00dev, RF2850) || |
7464 | rt2x00_rf(rt2x00dev, RF2750)) { | |
4da2933f BZ |
7465 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
7466 | spec->num_channels = ARRAY_SIZE(rf_vals); | |
7467 | spec->channels = rf_vals; | |
5122d898 GW |
7468 | } else if (rt2x00_rf(rt2x00dev, RF3020) || |
7469 | rt2x00_rf(rt2x00dev, RF2020) || | |
7470 | rt2x00_rf(rt2x00dev, RF3021) || | |
f93bc9b3 | 7471 | rt2x00_rf(rt2x00dev, RF3022) || |
a89534ed | 7472 | rt2x00_rf(rt2x00dev, RF3290) || |
adde5882 | 7473 | rt2x00_rf(rt2x00dev, RF3320) || |
03839951 | 7474 | rt2x00_rf(rt2x00dev, RF3322) || |
ccf91bd6 | 7475 | rt2x00_rf(rt2x00dev, RF5360) || |
aca355b9 | 7476 | rt2x00_rf(rt2x00dev, RF5370) || |
2ed71884 | 7477 | rt2x00_rf(rt2x00dev, RF5372) || |
cff3d1f0 ZL |
7478 | rt2x00_rf(rt2x00dev, RF5390) || |
7479 | rt2x00_rf(rt2x00dev, RF5392)) { | |
55f9321a ID |
7480 | spec->num_channels = 14; |
7481 | spec->channels = rf_vals_3x; | |
7482 | } else if (rt2x00_rf(rt2x00dev, RF3052)) { | |
7483 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | |
7484 | spec->num_channels = ARRAY_SIZE(rf_vals_3x); | |
7485 | spec->channels = rf_vals_3x; | |
c8b9d3dc GJ |
7486 | } else if (rt2x00_rf(rt2x00dev, RF3053)) { |
7487 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | |
7488 | spec->num_channels = ARRAY_SIZE(rf_vals_3053); | |
7489 | spec->channels = rf_vals_3053; | |
7848b231 SG |
7490 | } else if (rt2x00_rf(rt2x00dev, RF5592)) { |
7491 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | |
7492 | ||
7493 | rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); | |
7494 | if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { | |
7495 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); | |
7496 | spec->channels = rf_vals_5592_xtal40; | |
7497 | } else { | |
7498 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); | |
7499 | spec->channels = rf_vals_5592_xtal20; | |
7500 | } | |
4da2933f BZ |
7501 | } |
7502 | ||
53216d6a SG |
7503 | if (WARN_ON_ONCE(!spec->channels)) |
7504 | return -ENODEV; | |
7505 | ||
4da2933f BZ |
7506 | /* |
7507 | * Initialize HT information. | |
7508 | */ | |
5122d898 | 7509 | if (!rt2x00_rf(rt2x00dev, RF2020)) |
38a522e6 GW |
7510 | spec->ht.ht_supported = true; |
7511 | else | |
7512 | spec->ht.ht_supported = false; | |
7513 | ||
4da2933f | 7514 | spec->ht.cap = |
06443e46 | 7515 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
4da2933f BZ |
7516 | IEEE80211_HT_CAP_GRN_FLD | |
7517 | IEEE80211_HT_CAP_SGI_20 | | |
aa674631 | 7518 | IEEE80211_HT_CAP_SGI_40; |
22cabaa6 | 7519 | |
38c8a566 | 7520 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2) |
22cabaa6 HS |
7521 | spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; |
7522 | ||
aa674631 | 7523 | spec->ht.cap |= |
38c8a566 | 7524 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) << |
aa674631 ID |
7525 | IEEE80211_HT_CAP_RX_STBC_SHIFT; |
7526 | ||
4da2933f BZ |
7527 | spec->ht.ampdu_factor = 3; |
7528 | spec->ht.ampdu_density = 4; | |
7529 | spec->ht.mcs.tx_params = | |
7530 | IEEE80211_HT_MCS_TX_DEFINED | | |
7531 | IEEE80211_HT_MCS_TX_RX_DIFF | | |
38c8a566 | 7532 | ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) << |
4da2933f BZ |
7533 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
7534 | ||
38c8a566 | 7535 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) { |
4da2933f BZ |
7536 | case 3: |
7537 | spec->ht.mcs.rx_mask[2] = 0xff; | |
7538 | case 2: | |
7539 | spec->ht.mcs.rx_mask[1] = 0xff; | |
7540 | case 1: | |
7541 | spec->ht.mcs.rx_mask[0] = 0xff; | |
7542 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ | |
7543 | break; | |
7544 | } | |
7545 | ||
7546 | /* | |
7547 | * Create channel information array | |
7548 | */ | |
baeb2ffa | 7549 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
4da2933f BZ |
7550 | if (!info) |
7551 | return -ENOMEM; | |
7552 | ||
7553 | spec->channels_info = info; | |
7554 | ||
3e38d3da GJ |
7555 | default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); |
7556 | default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); | |
4da2933f | 7557 | |
c0a14369 GJ |
7558 | if (rt2x00dev->default_ant.tx_chain_num > 2) |
7559 | default_power3 = rt2800_eeprom_addr(rt2x00dev, | |
7560 | EEPROM_EXT_TXPOWER_BG3); | |
7561 | else | |
7562 | default_power3 = NULL; | |
7563 | ||
4da2933f | 7564 | for (i = 0; i < 14; i++) { |
e90c54b2 RJH |
7565 | info[i].default_power1 = default_power1[i]; |
7566 | info[i].default_power2 = default_power2[i]; | |
c0a14369 GJ |
7567 | if (default_power3) |
7568 | info[i].default_power3 = default_power3[i]; | |
4da2933f BZ |
7569 | } |
7570 | ||
7571 | if (spec->num_channels > 14) { | |
3e38d3da GJ |
7572 | default_power1 = rt2800_eeprom_addr(rt2x00dev, |
7573 | EEPROM_TXPOWER_A1); | |
7574 | default_power2 = rt2800_eeprom_addr(rt2x00dev, | |
7575 | EEPROM_TXPOWER_A2); | |
4da2933f | 7576 | |
c0a14369 GJ |
7577 | if (rt2x00dev->default_ant.tx_chain_num > 2) |
7578 | default_power3 = | |
7579 | rt2800_eeprom_addr(rt2x00dev, | |
7580 | EEPROM_EXT_TXPOWER_A3); | |
7581 | else | |
7582 | default_power3 = NULL; | |
7583 | ||
4da2933f | 7584 | for (i = 14; i < spec->num_channels; i++) { |
0a6f3a8e GJ |
7585 | info[i].default_power1 = default_power1[i - 14]; |
7586 | info[i].default_power2 = default_power2[i - 14]; | |
c0a14369 GJ |
7587 | if (default_power3) |
7588 | info[i].default_power3 = default_power3[i - 14]; | |
4da2933f BZ |
7589 | } |
7590 | } | |
7591 | ||
2e9c43dd JL |
7592 | switch (rt2x00dev->chip.rf) { |
7593 | case RF2020: | |
7594 | case RF3020: | |
7595 | case RF3021: | |
7596 | case RF3022: | |
7597 | case RF3320: | |
7598 | case RF3052: | |
1095df07 | 7599 | case RF3053: |
a89534ed | 7600 | case RF3290: |
ccf91bd6 | 7601 | case RF5360: |
2e9c43dd JL |
7602 | case RF5370: |
7603 | case RF5372: | |
7604 | case RF5390: | |
cff3d1f0 | 7605 | case RF5392: |
2e9c43dd JL |
7606 | __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); |
7607 | break; | |
7608 | } | |
7609 | ||
4da2933f BZ |
7610 | return 0; |
7611 | } | |
ad417a53 | 7612 | |
cbafb601 GJ |
7613 | static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) |
7614 | { | |
7615 | u32 reg; | |
7616 | u32 rt; | |
7617 | u32 rev; | |
7618 | ||
7619 | if (rt2x00_rt(rt2x00dev, RT3290)) | |
7620 | rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); | |
7621 | else | |
7622 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
7623 | ||
7624 | rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); | |
7625 | rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); | |
7626 | ||
7627 | switch (rt) { | |
7628 | case RT2860: | |
7629 | case RT2872: | |
7630 | case RT2883: | |
7631 | case RT3070: | |
7632 | case RT3071: | |
7633 | case RT3090: | |
7634 | case RT3290: | |
7635 | case RT3352: | |
7636 | case RT3390: | |
7637 | case RT3572: | |
7638 | case RT5390: | |
7639 | case RT5392: | |
7640 | case RT5592: | |
7641 | break; | |
7642 | default: | |
ec9c4989 JP |
7643 | rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", |
7644 | rt, rev); | |
cbafb601 GJ |
7645 | return -ENODEV; |
7646 | } | |
7647 | ||
7648 | rt2x00_set_rt(rt2x00dev, rt, rev); | |
7649 | ||
7650 | return 0; | |
7651 | } | |
7652 | ||
ad417a53 GW |
7653 | int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) |
7654 | { | |
7655 | int retval; | |
7656 | u32 reg; | |
7657 | ||
cbafb601 GJ |
7658 | retval = rt2800_probe_rt(rt2x00dev); |
7659 | if (retval) | |
7660 | return retval; | |
7661 | ||
ad417a53 GW |
7662 | /* |
7663 | * Allocate eeprom data. | |
7664 | */ | |
7665 | retval = rt2800_validate_eeprom(rt2x00dev); | |
7666 | if (retval) | |
7667 | return retval; | |
7668 | ||
7669 | retval = rt2800_init_eeprom(rt2x00dev); | |
7670 | if (retval) | |
7671 | return retval; | |
7672 | ||
7673 | /* | |
7674 | * Enable rfkill polling by setting GPIO direction of the | |
7675 | * rfkill switch GPIO pin correctly. | |
7676 | */ | |
7677 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); | |
7678 | rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); | |
7679 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | |
7680 | ||
7681 | /* | |
7682 | * Initialize hw specifications. | |
7683 | */ | |
7684 | retval = rt2800_probe_hw_mode(rt2x00dev); | |
7685 | if (retval) | |
7686 | return retval; | |
7687 | ||
7688 | /* | |
7689 | * Set device capabilities. | |
7690 | */ | |
7691 | __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); | |
7692 | __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); | |
7693 | if (!rt2x00_is_usb(rt2x00dev)) | |
7694 | __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); | |
7695 | ||
7696 | /* | |
7697 | * Set device requirements. | |
7698 | */ | |
7699 | if (!rt2x00_is_soc(rt2x00dev)) | |
7700 | __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); | |
7701 | __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); | |
7702 | __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); | |
7703 | if (!rt2800_hwcrypt_disabled(rt2x00dev)) | |
7704 | __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); | |
7705 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); | |
7706 | __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); | |
7707 | if (rt2x00_is_usb(rt2x00dev)) | |
7708 | __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); | |
7709 | else { | |
7710 | __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); | |
7711 | __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); | |
7712 | } | |
7713 | ||
7714 | /* | |
7715 | * Set the rssi offset. | |
7716 | */ | |
7717 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
7718 | ||
7719 | return 0; | |
7720 | } | |
7721 | EXPORT_SYMBOL_GPL(rt2800_probe_hw); | |
4da2933f | 7722 | |
2ce33995 BZ |
7723 | /* |
7724 | * IEEE80211 stack callback functions. | |
7725 | */ | |
e783619e HS |
7726 | void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32, |
7727 | u16 *iv16) | |
2ce33995 BZ |
7728 | { |
7729 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
7730 | struct mac_iveiv_entry iveiv_entry; | |
7731 | u32 offset; | |
7732 | ||
7733 | offset = MAC_IVEIV_ENTRY(hw_key_idx); | |
7734 | rt2800_register_multiread(rt2x00dev, offset, | |
7735 | &iveiv_entry, sizeof(iveiv_entry)); | |
7736 | ||
855da5e0 JL |
7737 | memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); |
7738 | memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); | |
2ce33995 | 7739 | } |
e783619e | 7740 | EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq); |
2ce33995 | 7741 | |
e783619e | 7742 | int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
2ce33995 BZ |
7743 | { |
7744 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
7745 | u32 reg; | |
7746 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); | |
7747 | ||
7748 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
7749 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); | |
7750 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
7751 | ||
7752 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
7753 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); | |
7754 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); | |
7755 | ||
7756 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
7757 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); | |
7758 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
7759 | ||
7760 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
7761 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); | |
7762 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
7763 | ||
7764 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
7765 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); | |
7766 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
7767 | ||
7768 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
7769 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); | |
7770 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
7771 | ||
7772 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
7773 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); | |
7774 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
7775 | ||
7776 | return 0; | |
7777 | } | |
e783619e | 7778 | EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); |
2ce33995 | 7779 | |
8a3a3c85 EP |
7780 | int rt2800_conf_tx(struct ieee80211_hw *hw, |
7781 | struct ieee80211_vif *vif, u16 queue_idx, | |
e783619e | 7782 | const struct ieee80211_tx_queue_params *params) |
2ce33995 BZ |
7783 | { |
7784 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
7785 | struct data_queue *queue; | |
7786 | struct rt2x00_field32 field; | |
7787 | int retval; | |
7788 | u32 reg; | |
7789 | u32 offset; | |
7790 | ||
7791 | /* | |
7792 | * First pass the configuration through rt2x00lib, that will | |
7793 | * update the queue settings and validate the input. After that | |
7794 | * we are free to update the registers based on the value | |
7795 | * in the queue parameter. | |
7796 | */ | |
8a3a3c85 | 7797 | retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); |
2ce33995 BZ |
7798 | if (retval) |
7799 | return retval; | |
7800 | ||
7801 | /* | |
7802 | * We only need to perform additional register initialization | |
7803 | * for WMM queues/ | |
7804 | */ | |
7805 | if (queue_idx >= 4) | |
7806 | return 0; | |
7807 | ||
11f818e0 | 7808 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2ce33995 BZ |
7809 | |
7810 | /* Update WMM TXOP register */ | |
7811 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); | |
7812 | field.bit_offset = (queue_idx & 1) * 16; | |
7813 | field.bit_mask = 0xffff << field.bit_offset; | |
7814 | ||
7815 | rt2800_register_read(rt2x00dev, offset, ®); | |
7816 | rt2x00_set_field32(®, field, queue->txop); | |
7817 | rt2800_register_write(rt2x00dev, offset, reg); | |
7818 | ||
7819 | /* Update WMM registers */ | |
7820 | field.bit_offset = queue_idx * 4; | |
7821 | field.bit_mask = 0xf << field.bit_offset; | |
7822 | ||
7823 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); | |
7824 | rt2x00_set_field32(®, field, queue->aifs); | |
7825 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); | |
7826 | ||
7827 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); | |
7828 | rt2x00_set_field32(®, field, queue->cw_min); | |
7829 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); | |
7830 | ||
7831 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); | |
7832 | rt2x00_set_field32(®, field, queue->cw_max); | |
7833 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); | |
7834 | ||
7835 | /* Update EDCA registers */ | |
7836 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); | |
7837 | ||
7838 | rt2800_register_read(rt2x00dev, offset, ®); | |
7839 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); | |
7840 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); | |
7841 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); | |
7842 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); | |
7843 | rt2800_register_write(rt2x00dev, offset, reg); | |
7844 | ||
7845 | return 0; | |
7846 | } | |
e783619e | 7847 | EXPORT_SYMBOL_GPL(rt2800_conf_tx); |
2ce33995 | 7848 | |
37a41b4a | 7849 | u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
2ce33995 BZ |
7850 | { |
7851 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
7852 | u64 tsf; | |
7853 | u32 reg; | |
7854 | ||
7855 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); | |
7856 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; | |
7857 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); | |
7858 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); | |
7859 | ||
7860 | return tsf; | |
7861 | } | |
e783619e | 7862 | EXPORT_SYMBOL_GPL(rt2800_get_tsf); |
2ce33995 | 7863 | |
e783619e HS |
7864 | int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
7865 | enum ieee80211_ampdu_mlme_action action, | |
0b01f030 JB |
7866 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
7867 | u8 buf_size) | |
1df90809 | 7868 | { |
af35323d | 7869 | struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; |
1df90809 HS |
7870 | int ret = 0; |
7871 | ||
af35323d HS |
7872 | /* |
7873 | * Don't allow aggregation for stations the hardware isn't aware | |
7874 | * of because tx status reports for frames to an unknown station | |
7875 | * always contain wcid=255 and thus we can't distinguish between | |
7876 | * multiple stations which leads to unwanted situations when the | |
7877 | * hw reorders frames due to aggregation. | |
7878 | */ | |
7879 | if (sta_priv->wcid < 0) | |
7880 | return 1; | |
7881 | ||
1df90809 HS |
7882 | switch (action) { |
7883 | case IEEE80211_AMPDU_RX_START: | |
7884 | case IEEE80211_AMPDU_RX_STOP: | |
58ed826e HS |
7885 | /* |
7886 | * The hw itself takes care of setting up BlockAck mechanisms. | |
7887 | * So, we only have to allow mac80211 to nagotiate a BlockAck | |
7888 | * agreement. Once that is done, the hw will BlockAck incoming | |
7889 | * AMPDUs without further setup. | |
7890 | */ | |
1df90809 HS |
7891 | break; |
7892 | case IEEE80211_AMPDU_TX_START: | |
7893 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
7894 | break; | |
18b559d5 JB |
7895 | case IEEE80211_AMPDU_TX_STOP_CONT: |
7896 | case IEEE80211_AMPDU_TX_STOP_FLUSH: | |
7897 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
1df90809 HS |
7898 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
7899 | break; | |
7900 | case IEEE80211_AMPDU_TX_OPERATIONAL: | |
7901 | break; | |
7902 | default: | |
ec9c4989 JP |
7903 | rt2x00_warn((struct rt2x00_dev *)hw->priv, |
7904 | "Unknown AMPDU action\n"); | |
1df90809 HS |
7905 | } |
7906 | ||
7907 | return ret; | |
7908 | } | |
e783619e | 7909 | EXPORT_SYMBOL_GPL(rt2800_ampdu_action); |
a5ea2f02 | 7910 | |
977206d7 HS |
7911 | int rt2800_get_survey(struct ieee80211_hw *hw, int idx, |
7912 | struct survey_info *survey) | |
7913 | { | |
7914 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
7915 | struct ieee80211_conf *conf = &hw->conf; | |
7916 | u32 idle, busy, busy_ext; | |
7917 | ||
7918 | if (idx != 0) | |
7919 | return -ENOENT; | |
7920 | ||
675a0b04 | 7921 | survey->channel = conf->chandef.chan; |
977206d7 HS |
7922 | |
7923 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); | |
7924 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); | |
7925 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); | |
7926 | ||
7927 | if (idle || busy) { | |
7928 | survey->filled = SURVEY_INFO_CHANNEL_TIME | | |
7929 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
7930 | SURVEY_INFO_CHANNEL_TIME_EXT_BUSY; | |
7931 | ||
7932 | survey->channel_time = (idle + busy) / 1000; | |
7933 | survey->channel_time_busy = busy / 1000; | |
7934 | survey->channel_time_ext_busy = busy_ext / 1000; | |
7935 | } | |
7936 | ||
9931df26 HS |
7937 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) |
7938 | survey->filled |= SURVEY_INFO_IN_USE; | |
7939 | ||
977206d7 HS |
7940 | return 0; |
7941 | ||
7942 | } | |
7943 | EXPORT_SYMBOL_GPL(rt2800_get_survey); | |
7944 | ||
a5ea2f02 ID |
7945 | MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); |
7946 | MODULE_VERSION(DRV_VERSION); | |
7947 | MODULE_DESCRIPTION("Ralink RT2800 library"); | |
7948 | MODULE_LICENSE("GPL"); |