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rt2x00: Use correct TBTT_SYNC config in AP mode
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c 402
adde5882
GJ		 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 }
f31c9a8c 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 411 }
f31c9a8c
ID		 412
413 /*
414 * Disable DMA, will be reenabled later when enabling
415 * the radio.
416 */
417 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425 /*
426 * Write firmware to the device.
427 */
428 rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430 /*
431 * Wait for device to stabilize.
432 */
433 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436 break;
437 msleep(1);
438 }
439
440 if (i == REGISTER_BUSY_COUNT) {
441 ERROR(rt2x00dev, "PBF system register not ready.\n");
442 return -EBUSY;
443 }
444
445 /*
446 * Initialize firmware.
447 */
448 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450 msleep(1);
451
452 return 0;
453}
454EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
0c5879bc
ID		 456void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
59679b91 458{
0c5879bc 459 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 460 u32 word;
461
462 /*
463 * Initialize TX Info descriptor
464 */
465 rt2x00_desc_read(txwi, 0, &word);
466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471 rt2x00_set_field32(&word, TXWI_W0_TS,
472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476 txdesc->u.ht.mpdu_density);
477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 479 rt2x00_set_field32(&word, TXWI_W0_BW,
480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485 rt2x00_desc_write(txwi, 0, word);
486
487 rt2x00_desc_read(txwi, 1, &word);
488 rt2x00_set_field32(&word, TXWI_W1_ACK,
489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495 txdesc->key_idx : 0xff);
496 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497 txdesc->length);
2b23cdaa 498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 500 rt2x00_desc_write(txwi, 1, word);
501
502 /*
503 * Always write 0 to IV/EIV fields, hardware will insert the IV
504 * from the IVEIV register when TXD_W3_WIV is set to 0.
505 * When TXD_W3_WIV is set to 1 it will use the IV data
506 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507 * crypto entry in the registers should be used to encrypt the frame.
508 */
509 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511}
0c5879bc 512EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 513
ff6133be 514static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 515{
74861922
ID		 516 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519 u16 eeprom;
520 u8 offset0;
521 u8 offset1;
522 u8 offset2;
523
e5ef5bad 524 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 525 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530 } else {
531 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536 }
537
538 /*
539 * Convert the value from the descriptor into the RSSI value
540 * If the value in the descriptor is 0, it is considered invalid
541 * and the default (extremely low) rssi value is assumed
542 */
543 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547 /*
548 * mac80211 only accepts a single RSSI value. Calculating the
549 * average doesn't deliver a fair answer either since -60:-60 would
550 * be considered equally good as -50:-70 while the second is the one
551 * which gives less energy...
552 */
553 rssi0 = max(rssi0, rssi1);
554 return max(rssi0, rssi2);
555}
556
557void rt2800_process_rxwi(struct queue_entry *entry,
558 struct rxdone_entry_desc *rxdesc)
559{
560 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 561 u32 word;
562
563 rt2x00_desc_read(rxwi, 0, &word);
564
565 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568 rt2x00_desc_read(rxwi, 1, &word);
569
570 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573 if (rt2x00_get_field32(word, RXWI_W1_BW))
574 rxdesc->flags |= RX_FLAG_40MHZ;
575
576 /*
577 * Detect RX rate, always use MCS as signal type.
578 */
579 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583 /*
584 * Mask of 0x8 bit to remove the short preamble flag.
585 */
586 if (rxdesc->rate_mode == RATE_MODE_CCK)
587 rxdesc->signal &= ~0x8;
588
589 rt2x00_desc_read(rxwi, 2, &word);
590
74861922
ID		 591 /*
592 * Convert descriptor AGC value to RSSI value.
593 */
594 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 595
596 /*
597 * Remove RXWI descriptor from start of buffer.
598 */
74861922 599 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 600}
601EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
3613884d
ID		 603static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604{
605 __le32 *txwi;
606 u32 word;
607 int wcid, ack, pid;
608 int tx_wcid, tx_ack, tx_pid;
609
610 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614 /*
615 * This frames has returned with an IO error,
616 * so the status report is not intended for this
617 * frame.
618 */
619 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621 return false;
622 }
623
624 /*
625 * Validate if this TX status report is intended for
626 * this entry by comparing the WCID/ACK/PID fields.
627 */
628 txwi = rt2800_drv_get_txwi(entry);
629
630 rt2x00_desc_read(txwi, 1, &word);
631 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
633 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636 WARNING(entry->queue->rt2x00dev,
637 "TX status report missed for queue %d entry %d\n",
638 entry->queue->qid, entry->entry_idx);
639 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640 return false;
641 }
642
643 return true;
644}
645
14433331
HS		 646void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647{
648 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 649 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 650 struct txdone_entry_desc txdesc;
651 u32 word;
652 u16 mcs, real_mcs;
b34793ee 653 int aggr, ampdu;
14433331
HS		 654 __le32 *txwi;
655
656 /*
657 * Obtain the status about this packet.
658 */
659 txdesc.flags = 0;
660 txwi = rt2800_drv_get_txwi(entry);
661 rt2x00_desc_read(txwi, 0, &word);
b34793ee 662
14433331 663 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 664 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
665
14433331 666 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 667 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
668
669 /*
670 * If a frame was meant to be sent as a single non-aggregated MPDU
671 * but ended up in an aggregate the used tx rate doesn't correlate
672 * with the one specified in the TXWI as the whole aggregate is sent
673 * with the same rate.
674 *
675 * For example: two frames are sent to rt2x00, the first one sets
676 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
677 * and requests MCS15. If the hw aggregates both frames into one
678 * AMDPU the tx status for both frames will contain MCS7 although
679 * the frame was sent successfully.
680 *
681 * Hence, replace the requested rate with the real tx rate to not
682 * confuse the rate control algortihm by providing clearly wrong
683 * data.
684 */
5356d963 685 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 686 skbdesc->tx_rate_idx = real_mcs;
687 mcs = real_mcs;
688 }
14433331 689
f16d2db7
HS		 690 if (aggr == 1 || ampdu == 1)
691 __set_bit(TXDONE_AMPDU, &txdesc.flags);
692
14433331
HS		 693 /*
694 * Ralink has a retry mechanism using a global fallback
695 * table. We setup this fallback table to try the immediate
696 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
697 * always contains the MCS used for the last transmission, be
698 * it successful or not.
699 */
700 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
701 /*
702 * Transmission succeeded. The number of retries is
703 * mcs - real_mcs
704 */
705 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
706 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
707 } else {
708 /*
709 * Transmission failed. The number of retries is
710 * always 7 in this case (for a total number of 8
711 * frames sent).
712 */
713 __set_bit(TXDONE_FAILURE, &txdesc.flags);
714 txdesc.retry = rt2x00dev->long_retry;
715 }
716
717 /*
718 * the frame was retried at least once
719 * -> hw used fallback rates
720 */
721 if (txdesc.retry)
722 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
723
724 rt2x00lib_txdone(entry, &txdesc);
725}
726EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
727
96481b20
ID		 728void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
729{
730 struct data_queue *queue;
731 struct queue_entry *entry;
96481b20 732 u32 reg;
3613884d 733 u8 pid;
96481b20
ID		 734 int i;
735
736 /*
737 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
738 * at most X times and also stop processing once the TX_STA_FIFO_VALID
739 * flag is not set anymore.
740 *
741 * The legacy drivers use X=TX_RING_SIZE but state in a comment
742 * that the TX_STA_FIFO stack has a size of 16. We stick to our
743 * tx ring size for now.
744 */
efd2f271 745 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 746 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
747 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
748 break;
749
96481b20
ID		 750 /*
751 * Skip this entry when it contains an invalid
752 * queue identication number.
753 */
bc8a979e 754 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 755 if (pid >= QID_RX)
96481b20
ID		 756 continue;
757
11f818e0 758 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
96481b20
ID		 759 if (unlikely(!queue))
760 continue;
761
762 /*
763 * Inside each queue, we process each entry in a chronological
764 * order. We first check that the queue is not empty.
765 */
766 entry = NULL;
767 while (!rt2x00queue_empty(queue)) {
768 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 769 if (rt2800_txdone_entry_check(entry, reg))
96481b20 770 break;
96481b20
ID		 771 }
772
773 if (!entry || rt2x00queue_empty(queue))
774 break;
775
14433331 776 rt2800_txdone_entry(entry, reg);
96481b20
ID		 777 }
778}
779EXPORT_SYMBOL_GPL(rt2800_txdone);
780
f0194b2d
GW		 781void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
782{
783 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
784 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
785 unsigned int beacon_base;
739fd940 786 unsigned int padding_len;
d76dfc61 787 u32 orig_reg, reg;
f0194b2d
GW		 788
789 /*
790 * Disable beaconing while we are reloading the beacon data,
791 * otherwise we might be sending out invalid data.
792 */
793 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 794 orig_reg = reg;
f0194b2d
GW		 795 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
796 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
797
798 /*
799 * Add space for the TXWI in front of the skb.
800 */
801 skb_push(entry->skb, TXWI_DESC_SIZE);
802 memset(entry->skb, 0, TXWI_DESC_SIZE);
803
804 /*
805 * Register descriptor details in skb frame descriptor.
806 */
807 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
808 skbdesc->desc = entry->skb->data;
809 skbdesc->desc_len = TXWI_DESC_SIZE;
810
811 /*
812 * Add the TXWI for the beacon to the skb.
813 */
0c5879bc 814 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 815
816 /*
817 * Dump beacon to userspace through debugfs.
818 */
819 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
820
821 /*
739fd940 822 * Write entire beacon with TXWI and padding to register.
f0194b2d 823 */
739fd940 824 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 825 if (padding_len && skb_pad(entry->skb, padding_len)) {
826 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
827 /* skb freed by skb_pad() on failure */
828 entry->skb = NULL;
829 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
830 return;
831 }
832
f0194b2d 833 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 834 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
835 entry->skb->len + padding_len);
f0194b2d
GW		 836
837 /*
838 * Enable beaconing again.
839 */
f0194b2d
GW		 840 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
841 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
842
843 /*
844 * Clean up beacon skb.
845 */
846 dev_kfree_skb_any(entry->skb);
847 entry->skb = NULL;
848}
50e888ea 849EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 850
69cf36a4
HS		 851static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
852 unsigned int beacon_base)
fdb87251
HS		 853{
854 int i;
855
856 /*
857 * For the Beacon base registers we only need to clear
858 * the whole TXWI which (when set to 0) will invalidate
859 * the entire beacon.
860 */
861 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
862 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
863}
864
69cf36a4
HS		 865void rt2800_clear_beacon(struct queue_entry *entry)
866{
867 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
868 u32 reg;
869
870 /*
871 * Disable beaconing while we are reloading the beacon data,
872 * otherwise we might be sending out invalid data.
873 */
874 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
875 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
876 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
877
878 /*
879 * Clear beacon.
880 */
881 rt2800_clear_beacon_register(rt2x00dev,
882 HW_BEACON_OFFSET(entry->entry_idx));
883
884 /*
885 * Enabled beaconing again.
886 */
887 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
888 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
889}
890EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
891
f4450616
BZ		 892#ifdef CONFIG_RT2X00_LIB_DEBUGFS
893const struct rt2x00debug rt2800_rt2x00debug = {
894 .owner = THIS_MODULE,
895 .csr = {
896 .read = rt2800_register_read,
897 .write = rt2800_register_write,
898 .flags = RT2X00DEBUGFS_OFFSET,
899 .word_base = CSR_REG_BASE,
900 .word_size = sizeof(u32),
901 .word_count = CSR_REG_SIZE / sizeof(u32),
902 },
903 .eeprom = {
904 .read = rt2x00_eeprom_read,
905 .write = rt2x00_eeprom_write,
906 .word_base = EEPROM_BASE,
907 .word_size = sizeof(u16),
908 .word_count = EEPROM_SIZE / sizeof(u16),
909 },
910 .bbp = {
911 .read = rt2800_bbp_read,
912 .write = rt2800_bbp_write,
913 .word_base = BBP_BASE,
914 .word_size = sizeof(u8),
915 .word_count = BBP_SIZE / sizeof(u8),
916 },
917 .rf = {
918 .read = rt2x00_rf_read,
919 .write = rt2800_rf_write,
920 .word_base = RF_BASE,
921 .word_size = sizeof(u32),
922 .word_count = RF_SIZE / sizeof(u32),
923 },
924};
925EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
926#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
927
928int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
929{
930 u32 reg;
931
932 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
933 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
934}
935EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
936
937#ifdef CONFIG_RT2X00_LIB_LEDS
938static void rt2800_brightness_set(struct led_classdev *led_cdev,
939 enum led_brightness brightness)
940{
941 struct rt2x00_led *led =
942 container_of(led_cdev, struct rt2x00_led, led_dev);
943 unsigned int enabled = brightness != LED_OFF;
944 unsigned int bg_mode =
945 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
946 unsigned int polarity =
947 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
948 EEPROM_FREQ_LED_POLARITY);
949 unsigned int ledmode =
950 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
951 EEPROM_FREQ_LED_MODE);
44704e5d 952 u32 reg;
f4450616 953
44704e5d
LE		 954 /* Check for SoC (SOC devices don't support MCU requests) */
955 if (rt2x00_is_soc(led->rt2x00dev)) {
956 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
957
958 /* Set LED Polarity */
959 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
960
961 /* Set LED Mode */
962 if (led->type == LED_TYPE_RADIO) {
963 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
964 enabled ? 3 : 0);
965 } else if (led->type == LED_TYPE_ASSOC) {
966 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
967 enabled ? 3 : 0);
968 } else if (led->type == LED_TYPE_QUALITY) {
969 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
970 enabled ? 3 : 0);
971 }
972
973 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
974
975 } else {
976 if (led->type == LED_TYPE_RADIO) {
977 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
978 enabled ? 0x20 : 0);
979 } else if (led->type == LED_TYPE_ASSOC) {
980 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
981 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
982 } else if (led->type == LED_TYPE_QUALITY) {
983 /*
984 * The brightness is divided into 6 levels (0 - 5),
985 * The specs tell us the following levels:
986 * 0, 1 ,3, 7, 15, 31
987 * to determine the level in a simple way we can simply
988 * work with bitshifting:
989 * (1 << level) - 1
990 */
991 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
992 (1 << brightness / (LED_FULL / 6)) - 1,
993 polarity);
994 }
f4450616
BZ		 995 }
996}
997
998static int rt2800_blink_set(struct led_classdev *led_cdev,
999 unsigned long *delay_on, unsigned long *delay_off)
1000{
1001 struct rt2x00_led *led =
1002 container_of(led_cdev, struct rt2x00_led, led_dev);
1003 u32 reg;
1004
1005 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1006 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
1007 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 1008 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1009
1010 return 0;
1011}
1012
b3579d6a 1013static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1014 struct rt2x00_led *led, enum led_type type)
1015{
1016 led->rt2x00dev = rt2x00dev;
1017 led->type = type;
1018 led->led_dev.brightness_set = rt2800_brightness_set;
1019 led->led_dev.blink_set = rt2800_blink_set;
1020 led->flags = LED_INITIALIZED;
1021}
f4450616
BZ		 1022#endif /* CONFIG_RT2X00_LIB_LEDS */
1023
1024/*
1025 * Configuration handlers.
1026 */
1027static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1028 struct rt2x00lib_crypto *crypto,
1029 struct ieee80211_key_conf *key)
1030{
1031 struct mac_wcid_entry wcid_entry;
1032 struct mac_iveiv_entry iveiv_entry;
1033 u32 offset;
1034 u32 reg;
1035
1036 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1037
e4a0ab34
ID		 1038 if (crypto->cmd == SET_KEY) {
1039 rt2800_register_read(rt2x00dev, offset, &reg);
1040 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1041 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1042 /*
1043 * Both the cipher as the BSS Idx numbers are split in a main
1044 * value of 3 bits, and a extended field for adding one additional
1045 * bit to the value.
1046 */
1047 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1048 (crypto->cipher & 0x7));
1049 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1050 (crypto->cipher & 0x8) >> 3);
1051 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1052 (crypto->bssidx & 0x7));
1053 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1054 (crypto->bssidx & 0x8) >> 3);
1055 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1056 rt2800_register_write(rt2x00dev, offset, reg);
1057 } else {
1058 rt2800_register_write(rt2x00dev, offset, 0);
1059 }
f4450616
BZ		 1060
1061 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1062
1063 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1064 if ((crypto->cipher == CIPHER_TKIP) ||
1065 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1066 (crypto->cipher == CIPHER_AES))
1067 iveiv_entry.iv[3] |= 0x20;
1068 iveiv_entry.iv[3] |= key->keyidx << 6;
1069 rt2800_register_multiwrite(rt2x00dev, offset,
1070 &iveiv_entry, sizeof(iveiv_entry));
1071
1072 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1073
1074 memset(&wcid_entry, 0, sizeof(wcid_entry));
1075 if (crypto->cmd == SET_KEY)
10026f77 1076 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
f4450616
BZ		 1077 rt2800_register_multiwrite(rt2x00dev, offset,
1078 &wcid_entry, sizeof(wcid_entry));
1079}
1080
1081int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1082 struct rt2x00lib_crypto *crypto,
1083 struct ieee80211_key_conf *key)
1084{
1085 struct hw_key_entry key_entry;
1086 struct rt2x00_field32 field;
1087 u32 offset;
1088 u32 reg;
1089
1090 if (crypto->cmd == SET_KEY) {
1091 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1092
1093 memcpy(key_entry.key, crypto->key,
1094 sizeof(key_entry.key));
1095 memcpy(key_entry.tx_mic, crypto->tx_mic,
1096 sizeof(key_entry.tx_mic));
1097 memcpy(key_entry.rx_mic, crypto->rx_mic,
1098 sizeof(key_entry.rx_mic));
1099
1100 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1101 rt2800_register_multiwrite(rt2x00dev, offset,
1102 &key_entry, sizeof(key_entry));
1103 }
1104
1105 /*
1106 * The cipher types are stored over multiple registers
1107 * starting with SHARED_KEY_MODE_BASE each word will have
1108 * 32 bits and contains the cipher types for 2 bssidx each.
1109 * Using the correct defines correctly will cause overhead,
1110 * so just calculate the correct offset.
1111 */
1112 field.bit_offset = 4 * (key->hw_key_idx % 8);
1113 field.bit_mask = 0x7 << field.bit_offset;
1114
1115 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1116
1117 rt2800_register_read(rt2x00dev, offset, &reg);
1118 rt2x00_set_field32(&reg, field,
1119 (crypto->cmd == SET_KEY) * crypto->cipher);
1120 rt2800_register_write(rt2x00dev, offset, reg);
1121
1122 /*
1123 * Update WCID information
1124 */
1125 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1126
1127 return 0;
1128}
1129EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1130
1ed3811c
HS		 1131static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1132{
1133 int idx;
1134 u32 offset, reg;
1135
1136 /*
1137 * Search for the first free pairwise key entry and return the
1138 * corresponding index.
1139 *
1140 * Make sure the WCID starts _after_ the last possible shared key
1141 * entry (>32).
1142 *
1143 * Since parts of the pairwise key table might be shared with
1144 * the beacon frame buffers 6 & 7 we should only write into the
1145 * first 222 entries.
1146 */
1147 for (idx = 33; idx <= 222; idx++) {
1148 offset = MAC_WCID_ATTR_ENTRY(idx);
1149 rt2800_register_read(rt2x00dev, offset, &reg);
1150 if (!reg)
1151 return idx;
1152 }
1153 return -1;
1154}
1155
f4450616
BZ		 1156int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1157 struct rt2x00lib_crypto *crypto,
1158 struct ieee80211_key_conf *key)
1159{
1160 struct hw_key_entry key_entry;
1161 u32 offset;
1ed3811c 1162 int idx;
f4450616
BZ		 1163
1164 if (crypto->cmd == SET_KEY) {
1ed3811c
HS		 1165 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1166 if (idx < 0)
f4450616 1167 return -ENOSPC;
1ed3811c 1168 key->hw_key_idx = idx;
f4450616
BZ		 1169
1170 memcpy(key_entry.key, crypto->key,
1171 sizeof(key_entry.key));
1172 memcpy(key_entry.tx_mic, crypto->tx_mic,
1173 sizeof(key_entry.tx_mic));
1174 memcpy(key_entry.rx_mic, crypto->rx_mic,
1175 sizeof(key_entry.rx_mic));
1176
1177 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1178 rt2800_register_multiwrite(rt2x00dev, offset,
1179 &key_entry, sizeof(key_entry));
1180 }
1181
1182 /*
1183 * Update WCID information
1184 */
1185 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1186
1187 return 0;
1188}
1189EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1190
1191void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1192 const unsigned int filter_flags)
1193{
1194 u32 reg;
1195
1196 /*
1197 * Start configuration steps.
1198 * Note that the version error will always be dropped
1199 * and broadcast frames will always be accepted since
1200 * there is no filter for it at this time.
1201 */
1202 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1203 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1204 !(filter_flags & FIF_FCSFAIL));
1205 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1206 !(filter_flags & FIF_PLCPFAIL));
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1208 !(filter_flags & FIF_PROMISC_IN_BSS));
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1210 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1211 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1212 !(filter_flags & FIF_ALLMULTI));
1213 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1214 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1215 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1216 !(filter_flags & FIF_CONTROL));
1217 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1218 !(filter_flags & FIF_CONTROL));
1219 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1220 !(filter_flags & FIF_CONTROL));
1221 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1222 !(filter_flags & FIF_CONTROL));
1223 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1224 !(filter_flags & FIF_CONTROL));
1225 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1226 !(filter_flags & FIF_PSPOLL));
1227 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1228 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1229 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1230 !(filter_flags & FIF_CONTROL));
1231 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1232}
1233EXPORT_SYMBOL_GPL(rt2800_config_filter);
1234
1235void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1236 struct rt2x00intf_conf *conf, const unsigned int flags)
1237{
f4450616 1238 u32 reg;
fa8b4b22 1239 bool update_bssid = false;
f4450616
BZ		 1240
1241 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1242 /*
1243 * Enable synchronisation.
1244 */
1245 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1246 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1247 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1248
1249 if (conf->sync == TSF_SYNC_AP_NONE) {
1250 /*
1251 * Tune beacon queue transmit parameters for AP mode
1252 */
1253 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1254 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1255 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1256 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1257 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1258 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1259 } else {
1260 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1261 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1262 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1263 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1264 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1265 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1266 }
f4450616
BZ		 1267 }
1268
1269 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1270 if (flags & CONFIG_UPDATE_TYPE &&
1271 conf->sync == TSF_SYNC_AP_NONE) {
1272 /*
1273 * The BSSID register has to be set to our own mac
1274 * address in AP mode.
1275 */
1276 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1277 update_bssid = true;
1278 }
1279
c600c826
ID		 1280 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1281 reg = le32_to_cpu(conf->mac[1]);
1282 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1283 conf->mac[1] = cpu_to_le32(reg);
1284 }
f4450616
BZ		 1285
1286 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1287 conf->mac, sizeof(conf->mac));
1288 }
1289
fa8b4b22 1290 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1291 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1292 reg = le32_to_cpu(conf->bssid[1]);
1293 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1294 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1295 conf->bssid[1] = cpu_to_le32(reg);
1296 }
f4450616
BZ		 1297
1298 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1299 conf->bssid, sizeof(conf->bssid));
1300 }
1301}
1302EXPORT_SYMBOL_GPL(rt2800_config_intf);
1303
87c1915d
HS		 1304static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1305 struct rt2x00lib_erp *erp)
1306{
1307 bool any_sta_nongf = !!(erp->ht_opmode &
1308 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1309 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1310 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1311 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1312 u32 reg;
1313
1314 /* default protection rate for HT20: OFDM 24M */
1315 mm20_rate = gf20_rate = 0x4004;
1316
1317 /* default protection rate for HT40: duplicate OFDM 24M */
1318 mm40_rate = gf40_rate = 0x4084;
1319
1320 switch (protection) {
1321 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1322 /*
1323 * All STAs in this BSS are HT20/40 but there might be
1324 * STAs not supporting greenfield mode.
1325 * => Disable protection for HT transmissions.
1326 */
1327 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1328
1329 break;
1330 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1331 /*
1332 * All STAs in this BSS are HT20 or HT20/40 but there
1333 * might be STAs not supporting greenfield mode.
1334 * => Protect all HT40 transmissions.
1335 */
1336 mm20_mode = gf20_mode = 0;
1337 mm40_mode = gf40_mode = 2;
1338
1339 break;
1340 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1341 /*
1342 * Nonmember protection:
1343 * According to 802.11n we _should_ protect all
1344 * HT transmissions (but we don't have to).
1345 *
1346 * But if cts_protection is enabled we _shall_ protect
1347 * all HT transmissions using a CCK rate.
1348 *
1349 * And if any station is non GF we _shall_ protect
1350 * GF transmissions.
1351 *
1352 * We decide to protect everything
1353 * -> fall through to mixed mode.
1354 */
1355 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1356 /*
1357 * Legacy STAs are present
1358 * => Protect all HT transmissions.
1359 */
1360 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1361
1362 /*
1363 * If erp protection is needed we have to protect HT
1364 * transmissions with CCK 11M long preamble.
1365 */
1366 if (erp->cts_protection) {
1367 /* don't duplicate RTS/CTS in CCK mode */
1368 mm20_rate = mm40_rate = 0x0003;
1369 gf20_rate = gf40_rate = 0x0003;
1370 }
1371 break;
1372 };
1373
1374 /* check for STAs not supporting greenfield mode */
1375 if (any_sta_nongf)
1376 gf20_mode = gf40_mode = 2;
1377
1378 /* Update HT protection config */
1379 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1380 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1381 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1382 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1383
1384 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1385 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1386 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1387 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1388
1389 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1390 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1391 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1392 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1393
1394 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1395 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1396 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1397 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1398}
1399
02044643
HS		 1400void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1401 u32 changed)
f4450616
BZ		 1402{
1403 u32 reg;
1404
02044643
HS		 1405 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1406 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1407 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1408 !!erp->short_preamble);
1409 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1410 !!erp->short_preamble);
1411 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1412 }
f4450616 1413
02044643
HS		 1414 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1415 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1416 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1417 erp->cts_protection ? 2 : 0);
1418 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1419 }
f4450616 1420
02044643
HS		 1421 if (changed & BSS_CHANGED_BASIC_RATES) {
1422 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1423 erp->basic_rates);
1424 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1425 }
f4450616 1426
02044643
HS		 1427 if (changed & BSS_CHANGED_ERP_SLOT) {
1428 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1429 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1430 erp->slot_time);
1431 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1432
02044643
HS		 1433 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1434 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1435 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1436 }
f4450616 1437
02044643
HS		 1438 if (changed & BSS_CHANGED_BEACON_INT) {
1439 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1440 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1441 erp->beacon_int * 16);
1442 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1443 }
87c1915d
HS		 1444
1445 if (changed & BSS_CHANGED_HT)
1446 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1447}
1448EXPORT_SYMBOL_GPL(rt2800_config_erp);
1449
d96aa640
RJH		 1450static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1451 enum antenna ant)
1452{
1453 u32 reg;
1454 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1455 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1456
1457 if (rt2x00_is_pci(rt2x00dev)) {
1458 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1459 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1460 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1461 } else if (rt2x00_is_usb(rt2x00dev))
1462 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1463 eesk_pin, 0);
1464
1465 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1466 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1467 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1468 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1469}
1470
f4450616
BZ		 1471void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1472{
1473 u8 r1;
1474 u8 r3;
d96aa640 1475 u16 eeprom;
f4450616
BZ		 1476
1477 rt2800_bbp_read(rt2x00dev, 1, &r1);
1478 rt2800_bbp_read(rt2x00dev, 3, &r3);
1479
1480 /*
1481 * Configure the TX antenna.
1482 */
d96aa640 1483 switch (ant->tx_chain_num) {
f4450616
BZ		 1484 case 1:
1485 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1486 break;
1487 case 2:
1488 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1489 break;
1490 case 3:
e22557f2 1491 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1492 break;
1493 }
1494
1495 /*
1496 * Configure the RX antenna.
1497 */
d96aa640 1498 switch (ant->rx_chain_num) {
f4450616 1499 case 1:
d96aa640
RJH		 1500 if (rt2x00_rt(rt2x00dev, RT3070) ||
1501 rt2x00_rt(rt2x00dev, RT3090) ||
1502 rt2x00_rt(rt2x00dev, RT3390)) {
1503 rt2x00_eeprom_read(rt2x00dev,
1504 EEPROM_NIC_CONF1, &eeprom);
1505 if (rt2x00_get_field16(eeprom,
1506 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1507 rt2800_set_ant_diversity(rt2x00dev,
1508 rt2x00dev->default_ant.rx);
1509 }
f4450616
BZ		 1510 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1511 break;
1512 case 2:
1513 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1514 break;
1515 case 3:
1516 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1517 break;
1518 }
1519
1520 rt2800_bbp_write(rt2x00dev, 3, r3);
1521 rt2800_bbp_write(rt2x00dev, 1, r1);
1522}
1523EXPORT_SYMBOL_GPL(rt2800_config_ant);
1524
1525static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1526 struct rt2x00lib_conf *libconf)
1527{
1528 u16 eeprom;
1529 short lna_gain;
1530
1531 if (libconf->rf.channel <= 14) {
1532 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1533 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1534 } else if (libconf->rf.channel <= 64) {
1535 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1536 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1537 } else if (libconf->rf.channel <= 128) {
1538 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1539 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1540 } else {
1541 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1542 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1543 }
1544
1545 rt2x00dev->lna_gain = lna_gain;
1546}
1547
06855ef4
GW		 1548static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1549 struct ieee80211_conf *conf,
1550 struct rf_channel *rf,
1551 struct channel_info *info)
f4450616
BZ		 1552{
1553 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1554
d96aa640 1555 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1556 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1557
d96aa640 1558 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1559 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1560 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1561 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1562 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1563
1564 if (rf->channel > 14) {
1565 /*
1566 * When TX power is below 0, we should increase it by 7 to
1567 * make it a positive value (Minumum value is -7).
1568 * However this means that values between 0 and 7 have
1569 * double meaning, and we should set a 7DBm boost flag.
1570 */
1571 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1572 (info->default_power1 >= 0));
f4450616 1573
8d1331b3
ID		 1574 if (info->default_power1 < 0)
1575 info->default_power1 += 7;
f4450616 1576
8d1331b3 1577 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1578
1579 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1580 (info->default_power2 >= 0));
f4450616 1581
8d1331b3
ID		 1582 if (info->default_power2 < 0)
1583 info->default_power2 += 7;
f4450616 1584
8d1331b3 1585 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1586 } else {
8d1331b3
ID		 1587 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1588 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1589 }
1590
1591 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1592
1593 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1594 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1595 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1596 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1597
1598 udelay(200);
1599
1600 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1601 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1602 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1603 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1604
1605 udelay(200);
1606
1607 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1608 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1609 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1610 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1611}
1612
06855ef4
GW		 1613static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1614 struct ieee80211_conf *conf,
1615 struct rf_channel *rf,
1616 struct channel_info *info)
f4450616
BZ		 1617{
1618 u8 rfcsr;
1619
1620 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1621 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1622
1623 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1624 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1625 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1626
1627 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1628 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1629 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1630
5a673964 1631 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1632 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1633 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1634
f4450616
BZ		 1635 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1636 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1637 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1638
1639 rt2800_rfcsr_write(rt2x00dev, 24,
1640 rt2x00dev->calibration[conf_is_ht40(conf)]);
1641
71976907 1642 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1643 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1644 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1645}
1646
60687ba7
RST		 1647
1648#define RT5390_POWER_BOUND 0x27
1649#define RT5390_FREQ_OFFSET_BOUND 0x5f
1650
1651static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1652 struct ieee80211_conf *conf,
1653 struct rf_channel *rf,
1654 struct channel_info *info)
1655{
1656 u8 rfcsr;
1657 u16 eeprom;
1658
1659 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1660 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1661 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1662 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1663 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1664
1665 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1666 if (info->default_power1 > RT5390_POWER_BOUND)
1667 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1668 else
1669 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1670 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1671
1672 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1673 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1674 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1675 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1676 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1677 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1678
1679 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1680 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1681 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1682 RT5390_FREQ_OFFSET_BOUND);
1683 else
1684 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1685 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1686
1687 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1688 if (rf->channel <= 14) {
1689 int idx = rf->channel-1;
1690
1691 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1692 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1693 /* r55/r59 value array of channel 1~14 */
1694 static const char r55_bt_rev[] = {0x83, 0x83,
1695 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1696 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1697 static const char r59_bt_rev[] = {0x0e, 0x0e,
1698 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1699 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1700
1701 rt2800_rfcsr_write(rt2x00dev, 55,
1702 r55_bt_rev[idx]);
1703 rt2800_rfcsr_write(rt2x00dev, 59,
1704 r59_bt_rev[idx]);
1705 } else {
1706 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1707 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1708 0x88, 0x88, 0x86, 0x85, 0x84};
1709
1710 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1711 }
1712 } else {
1713 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1714 static const char r55_nonbt_rev[] = {0x23, 0x23,
1715 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1716 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1717 static const char r59_nonbt_rev[] = {0x07, 0x07,
1718 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1719 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1720
1721 rt2800_rfcsr_write(rt2x00dev, 55,
1722 r55_nonbt_rev[idx]);
1723 rt2800_rfcsr_write(rt2x00dev, 59,
1724 r59_nonbt_rev[idx]);
1725 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1726 static const char r59_non_bt[] = {0x8f, 0x8f,
1727 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1728 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1729
1730 rt2800_rfcsr_write(rt2x00dev, 59,
1731 r59_non_bt[idx]);
1732 }
1733 }
1734 }
1735
1736 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1737 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1738 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1739 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1740
1741 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1742 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1743 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 1744}
1745
f4450616
BZ		 1746static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1747 struct ieee80211_conf *conf,
1748 struct rf_channel *rf,
1749 struct channel_info *info)
1750{
1751 u32 reg;
1752 unsigned int tx_pin;
1753 u8 bbp;
1754
46323e11 1755 if (rf->channel <= 14) {
8d1331b3
ID		 1756 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1757 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1758 } else {
8d1331b3
ID		 1759 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1760 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1761 }
1762
06855ef4
GW		 1763 if (rt2x00_rf(rt2x00dev, RF2020) ||
1764 rt2x00_rf(rt2x00dev, RF3020) ||
1765 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1766 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1767 rt2x00_rf(rt2x00dev, RF3052) ||
1768 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1769 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
adde5882
GJ		 1770 else if (rt2x00_rf(rt2x00dev, RF5390))
1771 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
fa6f632f 1772 else
06855ef4 1773 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1774
1775 /*
1776 * Change BBP settings
1777 */
1778 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1779 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1780 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1781 rt2800_bbp_write(rt2x00dev, 86, 0);
1782
1783 if (rf->channel <= 14) {
adde5882 1784 if (!rt2x00_rt(rt2x00dev, RT5390)) {
7dab73b3
ID		 1785 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1786 &rt2x00dev->cap_flags)) {
adde5882
GJ		 1787 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1788 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1789 } else {
1790 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1791 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1792 }
f4450616
BZ		 1793 }
1794 } else {
1795 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1796
7dab73b3 1797 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 1798 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1799 else
1800 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1801 }
1802
1803 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1804 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1805 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1806 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1807 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1808
1809 tx_pin = 0;
1810
1811 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1812 if (rt2x00dev->default_ant.tx_chain_num == 2) {
f4450616
BZ		 1813 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1814 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1815 }
1816
1817 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1818 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 1819 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1820 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1821 }
1822
1823 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1824 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1825 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1826 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1827 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1828 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1829
1830 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1831
1832 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1833 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1834 rt2800_bbp_write(rt2x00dev, 4, bbp);
1835
1836 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1837 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1838 rt2800_bbp_write(rt2x00dev, 3, bbp);
1839
8d0c9b65 1840 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1841 if (conf_is_ht40(conf)) {
1842 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1843 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1844 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1845 } else {
1846 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1847 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1848 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1849 }
1850 }
1851
1852 msleep(1);
977206d7
HS		 1853
1854 /*
1855 * Clear channel statistic counters
1856 */
1857 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1858 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1859 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1860}
1861
9e33a355
HS		 1862static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1863{
1864 u8 tssi_bounds[9];
1865 u8 current_tssi;
1866 u16 eeprom;
1867 u8 step;
1868 int i;
1869
1870 /*
1871 * Read TSSI boundaries for temperature compensation from
1872 * the EEPROM.
1873 *
1874 * Array idx 0 1 2 3 4 5 6 7 8
1875 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
1876 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1877 */
1878 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1879 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1880 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1881 EEPROM_TSSI_BOUND_BG1_MINUS4);
1882 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1883 EEPROM_TSSI_BOUND_BG1_MINUS3);
1884
1885 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1886 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1887 EEPROM_TSSI_BOUND_BG2_MINUS2);
1888 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1889 EEPROM_TSSI_BOUND_BG2_MINUS1);
1890
1891 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1892 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1893 EEPROM_TSSI_BOUND_BG3_REF);
1894 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1895 EEPROM_TSSI_BOUND_BG3_PLUS1);
1896
1897 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1898 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1899 EEPROM_TSSI_BOUND_BG4_PLUS2);
1900 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1901 EEPROM_TSSI_BOUND_BG4_PLUS3);
1902
1903 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1904 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1905 EEPROM_TSSI_BOUND_BG5_PLUS4);
1906
1907 step = rt2x00_get_field16(eeprom,
1908 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1909 } else {
1910 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1911 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1912 EEPROM_TSSI_BOUND_A1_MINUS4);
1913 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1914 EEPROM_TSSI_BOUND_A1_MINUS3);
1915
1916 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1917 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1918 EEPROM_TSSI_BOUND_A2_MINUS2);
1919 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1920 EEPROM_TSSI_BOUND_A2_MINUS1);
1921
1922 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1923 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1924 EEPROM_TSSI_BOUND_A3_REF);
1925 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1926 EEPROM_TSSI_BOUND_A3_PLUS1);
1927
1928 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1929 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1930 EEPROM_TSSI_BOUND_A4_PLUS2);
1931 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1932 EEPROM_TSSI_BOUND_A4_PLUS3);
1933
1934 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1935 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1936 EEPROM_TSSI_BOUND_A5_PLUS4);
1937
1938 step = rt2x00_get_field16(eeprom,
1939 EEPROM_TSSI_BOUND_A5_AGC_STEP);
1940 }
1941
1942 /*
1943 * Check if temperature compensation is supported.
1944 */
1945 if (tssi_bounds[4] == 0xff)
1946 return 0;
1947
1948 /*
1949 * Read current TSSI (BBP 49).
1950 */
1951 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
1952
1953 /*
1954 * Compare TSSI value (BBP49) with the compensation boundaries
1955 * from the EEPROM and increase or decrease tx power.
1956 */
1957 for (i = 0; i <= 3; i++) {
1958 if (current_tssi > tssi_bounds[i])
1959 break;
1960 }
1961
1962 if (i == 4) {
1963 for (i = 8; i >= 5; i--) {
1964 if (current_tssi < tssi_bounds[i])
1965 break;
1966 }
1967 }
1968
1969 return (i - 4) * step;
1970}
1971
e90c54b2
RJH		 1972static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1973 enum ieee80211_band band)
1974{
1975 u16 eeprom;
1976 u8 comp_en;
1977 u8 comp_type;
75faae8b 1978 int comp_value = 0;
e90c54b2
RJH		 1979
1980 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1981
75faae8b
HS		 1982 /*
1983 * HT40 compensation not required.
1984 */
1985 if (eeprom == 0xffff ||
1986 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 1987 return 0;
1988
1989 if (band == IEEE80211_BAND_2GHZ) {
1990 comp_en = rt2x00_get_field16(eeprom,
1991 EEPROM_TXPOWER_DELTA_ENABLE_2G);
1992 if (comp_en) {
1993 comp_type = rt2x00_get_field16(eeprom,
1994 EEPROM_TXPOWER_DELTA_TYPE_2G);
1995 comp_value = rt2x00_get_field16(eeprom,
1996 EEPROM_TXPOWER_DELTA_VALUE_2G);
1997 if (!comp_type)
1998 comp_value = -comp_value;
1999 }
2000 } else {
2001 comp_en = rt2x00_get_field16(eeprom,
2002 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2003 if (comp_en) {
2004 comp_type = rt2x00_get_field16(eeprom,
2005 EEPROM_TXPOWER_DELTA_TYPE_5G);
2006 comp_value = rt2x00_get_field16(eeprom,
2007 EEPROM_TXPOWER_DELTA_VALUE_5G);
2008 if (!comp_type)
2009 comp_value = -comp_value;
2010 }
2011 }
2012
2013 return comp_value;
2014}
2015
fa71a160
HS		 2016static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2017 enum ieee80211_band band, int power_level,
2018 u8 txpower, int delta)
e90c54b2
RJH		 2019{
2020 u32 reg;
2021 u16 eeprom;
2022 u8 criterion;
2023 u8 eirp_txpower;
2024 u8 eirp_txpower_criterion;
2025 u8 reg_limit;
e90c54b2
RJH		 2026
2027 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2028 return txpower;
2029
7dab73b3 2030 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2031 /*
2032 * Check if eirp txpower exceed txpower_limit.
2033 * We use OFDM 6M as criterion and its eirp txpower
2034 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2035 * .11b data rate need add additional 4dbm
2036 * when calculating eirp txpower.
2037 */
2038 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2039 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2040
2041 rt2x00_eeprom_read(rt2x00dev,
2042 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2043
2044 if (band == IEEE80211_BAND_2GHZ)
2045 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2046 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2047 else
2048 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2049 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2050
2051 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2052 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2053
2054 reg_limit = (eirp_txpower > power_level) ?
2055 (eirp_txpower - power_level) : 0;
2056 } else
2057 reg_limit = 0;
2058
2af242e1 2059 return txpower + delta - reg_limit;
e90c54b2
RJH		 2060}
2061
f4450616 2062static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2063 enum ieee80211_band band,
2064 int power_level)
f4450616 2065{
5e846004 2066 u8 txpower;
5e846004 2067 u16 eeprom;
e90c54b2 2068 int i, is_rate_b;
f4450616 2069 u32 reg;
f4450616 2070 u8 r1;
5e846004 2071 u32 offset;
2af242e1
HS		 2072 int delta;
2073
2074 /*
2075 * Calculate HT40 compensation delta
2076 */
2077 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2078
9e33a355
HS		 2079 /*
2080 * calculate temperature compensation delta
2081 */
2082 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2083
5e846004 2084 /*
e90c54b2 2085 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2086 */
f4450616 2087 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2088 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2089 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2090 offset = TX_PWR_CFG_0;
2091
2092 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2093 /* just to be safe */
2094 if (offset > TX_PWR_CFG_4)
2095 break;
2096
2097 rt2800_register_read(rt2x00dev, offset, &reg);
2098
2099 /* read the next four txpower values */
2100 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2101 &eeprom);
2102
e90c54b2
RJH		 2103 is_rate_b = i ? 0 : 1;
2104 /*
2105 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2106 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2107 * TX_PWR_CFG_4: unknown
2108 */
5e846004
HS		 2109 txpower = rt2x00_get_field16(eeprom,
2110 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2111 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2112 power_level, txpower, delta);
e90c54b2 2113 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2114
e90c54b2
RJH		 2115 /*
2116 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2117 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2118 * TX_PWR_CFG_4: unknown
2119 */
5e846004
HS		 2120 txpower = rt2x00_get_field16(eeprom,
2121 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2122 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2123 power_level, txpower, delta);
e90c54b2 2124 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2125
e90c54b2
RJH		 2126 /*
2127 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2128 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2129 * TX_PWR_CFG_4: unknown
2130 */
5e846004
HS		 2131 txpower = rt2x00_get_field16(eeprom,
2132 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2133 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2134 power_level, txpower, delta);
e90c54b2 2135 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2136
e90c54b2
RJH		 2137 /*
2138 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2139 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2140 * TX_PWR_CFG_4: unknown
2141 */
5e846004
HS		 2142 txpower = rt2x00_get_field16(eeprom,
2143 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2144 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2145 power_level, txpower, delta);
e90c54b2 2146 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2147
2148 /* read the next four txpower values */
2149 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2150 &eeprom);
2151
e90c54b2
RJH		 2152 is_rate_b = 0;
2153 /*
2154 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2155 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2156 * TX_PWR_CFG_4: unknown
2157 */
5e846004
HS		 2158 txpower = rt2x00_get_field16(eeprom,
2159 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2160 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2161 power_level, txpower, delta);
e90c54b2 2162 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2163
e90c54b2
RJH		 2164 /*
2165 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2166 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2167 * TX_PWR_CFG_4: unknown
2168 */
5e846004
HS		 2169 txpower = rt2x00_get_field16(eeprom,
2170 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2171 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2172 power_level, txpower, delta);
e90c54b2 2173 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2174
e90c54b2
RJH		 2175 /*
2176 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2177 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2178 * TX_PWR_CFG_4: unknown
2179 */
5e846004
HS		 2180 txpower = rt2x00_get_field16(eeprom,
2181 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2182 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2183 power_level, txpower, delta);
e90c54b2 2184 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2185
e90c54b2
RJH		 2186 /*
2187 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2188 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2189 * TX_PWR_CFG_4: unknown
2190 */
5e846004
HS		 2191 txpower = rt2x00_get_field16(eeprom,
2192 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2193 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2194 power_level, txpower, delta);
e90c54b2 2195 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2196
2197 rt2800_register_write(rt2x00dev, offset, reg);
2198
2199 /* next TX_PWR_CFG register */
2200 offset += 4;
2201 }
f4450616
BZ		 2202}
2203
9e33a355
HS		 2204void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2205{
2206 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2207 rt2x00dev->tx_power);
2208}
2209EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2210
f4450616
BZ		 2211static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2212 struct rt2x00lib_conf *libconf)
2213{
2214 u32 reg;
2215
2216 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2217 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2218 libconf->conf->short_frame_max_tx_count);
2219 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2220 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2221 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2222}
2223
2224static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2225 struct rt2x00lib_conf *libconf)
2226{
2227 enum dev_state state =
2228 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2229 STATE_SLEEP : STATE_AWAKE;
2230 u32 reg;
2231
2232 if (state == STATE_SLEEP) {
2233 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2234
2235 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2236 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2237 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2238 libconf->conf->listen_interval - 1);
2239 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2240 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2241
2242 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2243 } else {
f4450616
BZ		 2244 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2245 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2246 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2247 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2248 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2249
2250 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2251 }
2252}
2253
2254void rt2800_config(struct rt2x00_dev *rt2x00dev,
2255 struct rt2x00lib_conf *libconf,
2256 const unsigned int flags)
2257{
2258 /* Always recalculate LNA gain before changing configuration */
2259 rt2800_config_lna_gain(rt2x00dev, libconf);
2260
e90c54b2 2261 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2262 rt2800_config_channel(rt2x00dev, libconf->conf,
2263 &libconf->rf, &libconf->channel);
9e33a355
HS		 2264 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2265 libconf->conf->power_level);
e90c54b2 2266 }
f4450616 2267 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2268 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2269 libconf->conf->power_level);
f4450616
BZ		 2270 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2271 rt2800_config_retry_limit(rt2x00dev, libconf);
2272 if (flags & IEEE80211_CONF_CHANGE_PS)
2273 rt2800_config_ps(rt2x00dev, libconf);
2274}
2275EXPORT_SYMBOL_GPL(rt2800_config);
2276
2277/*
2278 * Link tuning
2279 */
2280void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2281{
2282 u32 reg;
2283
2284 /*
2285 * Update FCS error count from register.
2286 */
2287 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2288 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2289}
2290EXPORT_SYMBOL_GPL(rt2800_link_stats);
2291
2292static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2293{
2294 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2295 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2296 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2297 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2298 rt2x00_rt(rt2x00dev, RT3390) ||
2299 rt2x00_rt(rt2x00dev, RT5390))
f4450616
BZ		 2300 return 0x1c + (2 * rt2x00dev->lna_gain);
2301 else
2302 return 0x2e + rt2x00dev->lna_gain;
2303 }
2304
2305 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2306 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2307 else
2308 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2309}
2310
2311static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2312 struct link_qual *qual, u8 vgc_level)
2313{
2314 if (qual->vgc_level != vgc_level) {
2315 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2316 qual->vgc_level = vgc_level;
2317 qual->vgc_level_reg = vgc_level;
2318 }
2319}
2320
2321void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2322{
2323 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2324}
2325EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2326
2327void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2328 const u32 count)
2329{
8d0c9b65 2330 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2331 return;
2332
2333 /*
2334 * When RSSI is better then -80 increase VGC level with 0x10
2335 */
2336 rt2800_set_vgc(rt2x00dev, qual,
2337 rt2800_get_default_vgc(rt2x00dev) +
2338 ((qual->rssi > -80) * 0x10));
2339}
2340EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2341
2342/*
2343 * Initialization functions.
2344 */
b9a07ae9 2345static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2346{
2347 u32 reg;
d5385bfc 2348 u16 eeprom;
fcf51541 2349 unsigned int i;
e3a896b9 2350 int ret;
fcf51541 2351
a9dce149
GW		 2352 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2353 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2354 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2355 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2356 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2357 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2358 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2359
e3a896b9
GW		 2360 ret = rt2800_drv_init_registers(rt2x00dev);
2361 if (ret)
2362 return ret;
fcf51541
BZ		 2363
2364 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2365 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2366 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2367 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2368 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2369 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2370
2371 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2372 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2373 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2374 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2375 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2376 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2377
2378 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2379 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2380
2381 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2382
2383 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2384 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2385 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2386 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2387 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2388 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2389 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2390 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2391
a9dce149
GW		 2392 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2393
2394 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2395 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2396 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2397 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2398
64522957 2399 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2400 rt2x00_rt(rt2x00dev, RT3090) ||
2401 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2402 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2403 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2404 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2405 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2406 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2407 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2408 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2409 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2410 0x0000002c);
2411 else
2412 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2413 0x0000000f);
2414 } else {
2415 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2416 }
d5385bfc 2417 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2418 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2419
2420 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2421 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2422 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2423 } else {
2424 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2425 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2426 }
c295a81d
HS		 2427 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2428 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2429 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2430 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
adde5882
GJ		 2431 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2432 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2433 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2434 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2435 } else {
2436 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2437 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2438 }
2439
2440 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2441 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2442 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2443 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2444 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2445 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2446 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2447 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2448 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2449 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2450
2451 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2452 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2453 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2454 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2455 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2456
2457 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2458 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2459 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2460 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2461 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2462 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2463 else
2464 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2465 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2466 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2467 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2468
a9dce149
GW		 2469 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2470 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2471 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2472 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2473 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2474 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2475 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2476 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2477 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2478
fcf51541
BZ		 2479 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2480
a9dce149
GW		 2481 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2482 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2483 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2484 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2485 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2486 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2487 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2488 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2489
fcf51541
BZ		 2490 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2491 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2492 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2493 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2494 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2495 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2496 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2497 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2498 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2499
2500 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2501 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2502 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2503 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2504 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2505 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2506 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2507 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2508 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2509 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2510 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2511 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2512
2513 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2514 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2515 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2516 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2517 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2518 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2519 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2520 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2521 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2522 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2523 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2524 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2525
2526 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2527 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2528 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2529 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2530 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2531 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2532 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2533 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2534 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2535 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2536 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2537 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2538
2539 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2540 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2541 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2542 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2543 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2544 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2545 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2546 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2547 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2548 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2549 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2550 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2551
2552 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2553 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2554 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2555 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2556 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2557 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2558 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2559 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2560 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2561 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2562 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2563 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2564
2565 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2566 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2567 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2568 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2569 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2570 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2571 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2572 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2573 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2574 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2575 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2576 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2577
cea90e55 2578 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2579 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2580
2581 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2582 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2583 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2584 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2585 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2586 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2587 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2588 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2589 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2590 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2591 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2592 }
2593
961621ab
HS		 2594 /*
2595 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2596 * although it is reserved.
2597 */
2598 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2599 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2600 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2601 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2602 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2603 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2604 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2605 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2606 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2607 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2608 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2609 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2610
fcf51541
BZ		 2611 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2612
2613 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2614 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2615 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2616 IEEE80211_MAX_RTS_THRESHOLD);
2617 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2618 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2619
2620 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2621
a21c2ab4
HS		 2622 /*
2623 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2624 * time should be set to 16. However, the original Ralink driver uses
2625 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2626 * connection problems with 11g + CTS protection. Hence, use the same
2627 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2628 */
a9dce149 2629 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2630 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2631 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2632 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2633 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2634 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2635 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2636
fcf51541
BZ		 2637 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2638
2639 /*
2640 * ASIC will keep garbage value after boot, clear encryption keys.
2641 */
2642 for (i = 0; i < 4; i++)
2643 rt2800_register_write(rt2x00dev,
2644 SHARED_KEY_MODE_ENTRY(i), 0);
2645
2646 for (i = 0; i < 256; i++) {
f4e16e41 2647 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2648 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2649 wcid, sizeof(wcid));
2650
1ed3811c 2651 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
fcf51541
BZ		 2652 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2653 }
2654
2655 /*
2656 * Clear all beacons
fcf51541 2657 */
69cf36a4
HS		 2658 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2659 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2660 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2661 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2662 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2663 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2664 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2665 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2666
cea90e55 2667 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2668 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2669 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2670 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2671 } else if (rt2x00_is_pcie(rt2x00dev)) {
2672 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2673 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2674 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2675 }
2676
2677 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2678 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2679 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2680 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2681 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2682 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2683 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2684 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2685 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2686 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2687
2688 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2689 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2690 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2691 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2692 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2693 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2694 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2695 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2696 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2697 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2698
2699 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2700 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2701 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2702 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2703 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2704 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2705 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2706 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2707 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2708 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2709
2710 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2711 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2712 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2713 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2714 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2715 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2716
47ee3eb1
HS		 2717 /*
2718 * Do not force the BA window size, we use the TXWI to set it
2719 */
2720 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2721 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2722 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2723 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2724
fcf51541
BZ		 2725 /*
2726 * We must clear the error counters.
2727 * These registers are cleared on read,
2728 * so we may pass a useless variable to store the value.
2729 */
2730 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2731 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2732 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2733 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2734 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2735 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2736
9f926fb5
HS		 2737 /*
2738 * Setup leadtime for pre tbtt interrupt to 6ms
2739 */
2740 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2741 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2742 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2743
977206d7
HS		 2744 /*
2745 * Set up channel statistics timer
2746 */
2747 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2748 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2749 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2750 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2751 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2752 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2753 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2754
fcf51541
BZ		 2755 return 0;
2756}
fcf51541
BZ		 2757
2758static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2759{
2760 unsigned int i;
2761 u32 reg;
2762
2763 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2764 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2765 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2766 return 0;
2767
2768 udelay(REGISTER_BUSY_DELAY);
2769 }
2770
2771 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2772 return -EACCES;
2773}
2774
2775static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2776{
2777 unsigned int i;
2778 u8 value;
2779
2780 /*
2781 * BBP was enabled after firmware was loaded,
2782 * but we need to reactivate it now.
2783 */
2784 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2785 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2786 msleep(1);
2787
2788 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2789 rt2800_bbp_read(rt2x00dev, 0, &value);
2790 if ((value != 0xff) && (value != 0x00))
2791 return 0;
2792 udelay(REGISTER_BUSY_DELAY);
2793 }
2794
2795 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2796 return -EACCES;
2797}
2798
b9a07ae9 2799static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2800{
2801 unsigned int i;
2802 u16 eeprom;
2803 u8 reg_id;
2804 u8 value;
2805
2806 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2807 rt2800_wait_bbp_ready(rt2x00dev)))
2808 return -EACCES;
2809
adde5882
GJ		 2810 if (rt2x00_rt(rt2x00dev, RT5390)) {
2811 rt2800_bbp_read(rt2x00dev, 4, &value);
2812 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2813 rt2800_bbp_write(rt2x00dev, 4, value);
2814 }
60687ba7 2815
adde5882
GJ		 2816 if (rt2800_is_305x_soc(rt2x00dev) ||
2817 rt2x00_rt(rt2x00dev, RT5390))
baff8006
HS		 2818 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2819
fcf51541
BZ		 2820 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2821 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 2822
adde5882
GJ		 2823 if (rt2x00_rt(rt2x00dev, RT5390))
2824 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 2825
a9dce149
GW		 2826 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2827 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2828 rt2800_bbp_write(rt2x00dev, 73, 0x12);
adde5882
GJ		 2829 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2830 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2831 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2832 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2833 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2834 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 2835 } else {
2836 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2837 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2838 }
2839
fcf51541 2840 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2841
d5385bfc 2842 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2843 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2844 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2845 rt2x00_rt(rt2x00dev, RT3390) ||
2846 rt2x00_rt(rt2x00dev, RT5390)) {
8cdd15e0
GW		 2847 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2848 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2849 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2850 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2851 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2852 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2853 } else {
2854 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2855 }
2856
fcf51541 2857 rt2800_bbp_write(rt2x00dev, 82, 0x62);
adde5882
GJ		 2858 if (rt2x00_rt(rt2x00dev, RT5390))
2859 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2860 else
2861 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2862
5ed8f458 2863 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 2864 rt2800_bbp_write(rt2x00dev, 84, 0x19);
adde5882
GJ		 2865 else if (rt2x00_rt(rt2x00dev, RT5390))
2866 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 2867 else
2868 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2869
adde5882
GJ		 2870 if (rt2x00_rt(rt2x00dev, RT5390))
2871 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2872 else
2873 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 2874
fcf51541 2875 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 2876
adde5882
GJ		 2877 if (rt2x00_rt(rt2x00dev, RT5390))
2878 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2879 else
2880 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2881
d5385bfc 2882 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2883 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2884 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 2885 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
adde5882 2886 rt2x00_rt(rt2x00dev, RT5390) ||
baff8006 2887 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2888 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2889 else
2890 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2891
adde5882
GJ		 2892 if (rt2x00_rt(rt2x00dev, RT5390))
2893 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 2894
baff8006
HS		 2895 if (rt2800_is_305x_soc(rt2x00dev))
2896 rt2800_bbp_write(rt2x00dev, 105, 0x01);
adde5882
GJ		 2897 else if (rt2x00_rt(rt2x00dev, RT5390))
2898 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 2899 else
2900 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 2901
adde5882
GJ		 2902 if (rt2x00_rt(rt2x00dev, RT5390))
2903 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2904 else
2905 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 2906
adde5882
GJ		 2907 if (rt2x00_rt(rt2x00dev, RT5390))
2908 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 2909
64522957 2910 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2911 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2912 rt2x00_rt(rt2x00dev, RT3390) ||
2913 rt2x00_rt(rt2x00dev, RT5390)) {
d5385bfc 2914 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2915
38c8a566
RJH		 2916 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2917 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2918 value |= 0x20;
38c8a566 2919 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2920 value &= ~0x02;
fcf51541 2921
d5385bfc 2922 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2923 }
2924
adde5882
GJ		 2925 if (rt2x00_rt(rt2x00dev, RT5390)) {
2926 int ant, div_mode;
2927
2928 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2929 div_mode = rt2x00_get_field16(eeprom,
2930 EEPROM_NIC_CONF1_ANT_DIVERSITY);
2931 ant = (div_mode == 3) ? 1 : 0;
2932
2933 /* check if this is a Bluetooth combo card */
2934 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2935 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2936 u32 reg;
2937
2938 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2939 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2940 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2941 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2942 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2943 if (ant == 0)
2944 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2945 else if (ant == 1)
2946 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2947 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2948 }
2949
2950 rt2800_bbp_read(rt2x00dev, 152, &value);
2951 if (ant == 0)
2952 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2953 else
2954 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2955 rt2800_bbp_write(rt2x00dev, 152, value);
2956
2957 /* Init frequency calibration */
2958 rt2800_bbp_write(rt2x00dev, 142, 1);
2959 rt2800_bbp_write(rt2x00dev, 143, 57);
2960 }
fcf51541
BZ		 2961
2962 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2963 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2964
2965 if (eeprom != 0xffff && eeprom != 0x0000) {
2966 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2967 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2968 rt2800_bbp_write(rt2x00dev, reg_id, value);
2969 }
2970 }
2971
2972 return 0;
2973}
fcf51541
BZ		 2974
2975static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2976 bool bw40, u8 rfcsr24, u8 filter_target)
2977{
2978 unsigned int i;
2979 u8 bbp;
2980 u8 rfcsr;
2981 u8 passband;
2982 u8 stopband;
2983 u8 overtuned = 0;
2984
2985 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2986
2987 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2988 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2989 rt2800_bbp_write(rt2x00dev, 4, bbp);
2990
80d184e6
RJH		 2991 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2992 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2993 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2994
fcf51541
BZ		 2995 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2996 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2997 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2998
2999 /*
3000 * Set power & frequency of passband test tone
3001 */
3002 rt2800_bbp_write(rt2x00dev, 24, 0);
3003
3004 for (i = 0; i < 100; i++) {
3005 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3006 msleep(1);
3007
3008 rt2800_bbp_read(rt2x00dev, 55, &passband);
3009 if (passband)
3010 break;
3011 }
3012
3013 /*
3014 * Set power & frequency of stopband test tone
3015 */
3016 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3017
3018 for (i = 0; i < 100; i++) {
3019 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3020 msleep(1);
3021
3022 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3023
3024 if ((passband - stopband) <= filter_target) {
3025 rfcsr24++;
3026 overtuned += ((passband - stopband) == filter_target);
3027 } else
3028 break;
3029
3030 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3031 }
3032
3033 rfcsr24 -= !!overtuned;
3034
3035 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3036 return rfcsr24;
3037}
3038
b9a07ae9 3039static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3040{
3041 u8 rfcsr;
3042 u8 bbp;
8cdd15e0
GW		 3043 u32 reg;
3044 u16 eeprom;
fcf51541 3045
d5385bfc 3046 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3047 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3048 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3049 !rt2x00_rt(rt2x00dev, RT3390) &&
adde5882 3050 !rt2x00_rt(rt2x00dev, RT5390) &&
baff8006 3051 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3052 return 0;
3053
fcf51541
BZ		 3054 /*
3055 * Init RF calibration.
3056 */
adde5882
GJ		 3057 if (rt2x00_rt(rt2x00dev, RT5390)) {
3058 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3059 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3060 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3061 msleep(1);
3062 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3063 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3064 } else {
3065 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3066 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3067 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3068 msleep(1);
3069 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3070 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3071 }
fcf51541 3072
d5385bfc 3073 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3074 rt2x00_rt(rt2x00dev, RT3071) ||
3075 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3076 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3077 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3078 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3079 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3080 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3081 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3082 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3083 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3084 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3085 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3086 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3087 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3088 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3089 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3090 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3091 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3092 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3093 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3094 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3095 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3096 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3097 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3098 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3099 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3100 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3101 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3102 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3103 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3104 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3105 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3106 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3107 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3108 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3109 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3110 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3111 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3112 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3113 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3114 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3115 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3116 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3117 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3118 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3119 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3120 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3121 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3122 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3123 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3124 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3125 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3126 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3127 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 3128 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3129 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3130 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3131 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3132 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3133 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3134 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3135 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3136 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3137 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3138 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3139 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3140 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3141 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3142 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3143 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3144 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3145 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3146 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3147 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3148 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3149 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3150 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3151 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3152 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3153 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3154 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3155 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3156 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3157 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3158 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3159 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3160 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3161 return 0;
adde5882
GJ		 3162 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3163 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3164 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3165 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3166 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3167 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3168 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3169 else
3170 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3171 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3172 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3173 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3174 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3175 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3176 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3177 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3178 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3179 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3180 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3181
3182 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3183 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3184 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3185 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3186 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3187 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3188 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3189 else
3190 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3191 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3192 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3193 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3194 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3195
3196 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3197 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3198 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3199 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3200 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3201 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3202 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3203 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3204 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3205 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3206
3207 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3208 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3209 else
3210 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3211 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3212 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3213 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3214 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3215 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3216 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3217 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3218 else
3219 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3220 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3221 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3222 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3223
3224 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3225 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3226 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3227 else
3228 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3229 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3230 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3231 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3232 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3233 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3234 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3235
3236 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3237 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3238 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3239 else
3240 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3241 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3242 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8cdd15e0
GW		 3243 }
3244
3245 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3246 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3247 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3248 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3249 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3250 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3251 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3252 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3253
d5385bfc
GW		 3254 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3255 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3256 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3257
d5385bfc
GW		 3258 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3259 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3260 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3261 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3262 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3263 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3264 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3265 else
3266 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3267 }
3268 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3269
3270 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3271 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3272 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3273 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3274 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3275 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3276 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 3277 }
3278
3279 /*
3280 * Set RX Filter calibration for 20MHz and 40MHz
3281 */
8cdd15e0
GW		 3282 if (rt2x00_rt(rt2x00dev, RT3070)) {
3283 rt2x00dev->calibration[0] =
3284 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3285 rt2x00dev->calibration[1] =
3286 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3287 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3288 rt2x00_rt(rt2x00dev, RT3090) ||
3289 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3290 rt2x00dev->calibration[0] =
3291 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3292 rt2x00dev->calibration[1] =
3293 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3294 }
fcf51541 3295
adde5882
GJ		 3296 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3297 /*
3298 * Set back to initial state
3299 */
3300 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3301
adde5882
GJ		 3302 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3303 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3304 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3305
adde5882
GJ		 3306 /*
3307 * Set BBP back to BW20
3308 */
3309 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3310 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3311 rt2800_bbp_write(rt2x00dev, 4, bbp);
3312 }
fcf51541 3313
d5385bfc 3314 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3315 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3316 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3317 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3318 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3319
3320 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3321 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3322 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3323
adde5882
GJ		 3324 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3325 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3326 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3327 if (rt2x00_rt(rt2x00dev, RT3070) ||
3328 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3329 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3330 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3331 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3332 &rt2x00dev->cap_flags))
adde5882
GJ		 3333 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3334 }
3335 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3336 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3337 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3338 rt2x00_get_field16(eeprom,
3339 EEPROM_TXMIXER_GAIN_BG_VAL));
3340 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3341 }
8cdd15e0 3342
64522957
GW		 3343 if (rt2x00_rt(rt2x00dev, RT3090)) {
3344 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3345
80d184e6 3346 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3347 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3348 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3349 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3350 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3351 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3352
3353 rt2800_bbp_write(rt2x00dev, 138, bbp);
3354 }
3355
3356 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3357 rt2x00_rt(rt2x00dev, RT3090) ||
3358 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3359 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3360 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3361 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3362 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3363 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3364 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3365 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3366
3367 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3368 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3369 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3370
3371 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3372 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3373 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3374
3375 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3376 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3377 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3378 }
3379
80d184e6 3380 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3381 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3382 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3383 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3384 else
3385 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3386 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3387 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3388 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3389 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3390 }
3391
adde5882
GJ		 3392 if (rt2x00_rt(rt2x00dev, RT5390)) {
3393 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3394 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3395 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3396
adde5882
GJ		 3397 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3398 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3399 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3400
adde5882
GJ		 3401 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3402 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3403 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3404 }
60687ba7 3405
fcf51541
BZ		 3406 return 0;
3407}
b9a07ae9
ID		 3408
3409int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3410{
3411 u32 reg;
3412 u16 word;
3413
3414 /*
3415 * Initialize all registers.
3416 */
3417 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3418 rt2800_init_registers(rt2x00dev) ||
3419 rt2800_init_bbp(rt2x00dev) ||
3420 rt2800_init_rfcsr(rt2x00dev)))
3421 return -EIO;
3422
3423 /*
3424 * Send signal to firmware during boot time.
3425 */
3426 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3427
3428 if (rt2x00_is_usb(rt2x00dev) &&
3429 (rt2x00_rt(rt2x00dev, RT3070) ||
3430 rt2x00_rt(rt2x00dev, RT3071) ||
3431 rt2x00_rt(rt2x00dev, RT3572))) {
3432 udelay(200);
3433 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3434 udelay(10);
3435 }
3436
3437 /*
3438 * Enable RX.
3439 */
3440 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3441 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3442 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3443 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3444
3445 udelay(50);
3446
3447 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3448 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3449 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3450 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3451 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3452 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3453
3454 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3455 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3456 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3457 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3458
3459 /*
3460 * Initialize LED control
3461 */
38c8a566
RJH		 3462 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3463 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3464 word & 0xff, (word >> 8) & 0xff);
3465
38c8a566
RJH		 3466 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3467 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3468 word & 0xff, (word >> 8) & 0xff);
3469
38c8a566
RJH		 3470 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3471 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3472 word & 0xff, (word >> 8) & 0xff);
3473
3474 return 0;
3475}
3476EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3477
3478void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3479{
3480 u32 reg;
3481
3482 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3483 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 3484 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 3485 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3486
3487 /* Wait for DMA, ignore error */
3488 rt2800_wait_wpdma_ready(rt2x00dev);
3489
3490 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3491 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3492 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3493 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 3494}
3495EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 3496
30e84034
BZ		 3497int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3498{
3499 u32 reg;
3500
3501 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3502
3503 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3504}
3505EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3506
3507static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3508{
3509 u32 reg;
3510
31a4cf1f
GW		 3511 mutex_lock(&rt2x00dev->csr_mutex);
3512
3513 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3514 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3515 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3516 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3517 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3518
3519 /* Wait until the EEPROM has been loaded */
3520 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3521
3522 /* Apparently the data is read from end to start */
31a4cf1f
GW		 3523 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3524 (u32 *)&rt2x00dev->eeprom[i]);
3525 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3526 (u32 *)&rt2x00dev->eeprom[i + 2]);
3527 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3528 (u32 *)&rt2x00dev->eeprom[i + 4]);
3529 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3530 (u32 *)&rt2x00dev->eeprom[i + 6]);
3531
3532 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3533}
3534
3535void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3536{
3537 unsigned int i;
3538
3539 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3540 rt2800_efuse_read(rt2x00dev, i);
3541}
3542EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3543
38bd7b8a
BZ		 3544int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3545{
3546 u16 word;
3547 u8 *mac;
3548 u8 default_lna_gain;
3549
3550 /*
3551 * Start validation of the data that has been read.
3552 */
3553 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3554 if (!is_valid_ether_addr(mac)) {
3555 random_ether_addr(mac);
3556 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3557 }
3558
38c8a566 3559 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3560 if (word == 0xffff) {
38c8a566
RJH		 3561 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3562 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3563 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3564 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3565 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3566 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3567 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3568 /*
3569 * There is a max of 2 RX streams for RT28x0 series
3570 */
38c8a566
RJH		 3571 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3572 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3573 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3574 }
3575
38c8a566 3576 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3577 if (word == 0xffff) {
38c8a566
RJH		 3578 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3579 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3580 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3581 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3582 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3583 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3584 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3585 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3586 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3587 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3588 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3589 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3590 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3591 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3592 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3593 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3594 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3595 }
3596
3597 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3598 if ((word & 0x00ff) == 0x00ff) {
3599 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3600 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3601 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3602 }
3603 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3604 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3605 LED_MODE_TXRX_ACTIVITY);
3606 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3607 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3608 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3609 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3610 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3611 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3612 }
3613
3614 /*
3615 * During the LNA validation we are going to use
3616 * lna0 as correct value. Note that EEPROM_LNA
3617 * is never validated.
3618 */
3619 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3620 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3621
3622 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3623 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3624 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3625 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3626 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3627 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3628
3629 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3630 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3631 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3632 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3633 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3634 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3635 default_lna_gain);
3636 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3637
3638 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3639 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3640 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3641 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3642 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3643 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3644
3645 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3646 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3647 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3648 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3649 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3650 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3651 default_lna_gain);
3652 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3653
3654 return 0;
3655}
3656EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3657
3658int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3659{
3660 u32 reg;
3661 u16 value;
3662 u16 eeprom;
3663
3664 /*
3665 * Read EEPROM word for configuration.
3666 */
38c8a566 3667 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3668
3669 /*
adde5882
GJ		 3670 * Identify RF chipset by EEPROM value
3671 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3672 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 3673 */
38bd7b8a 3674 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
adde5882
GJ		 3675 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3676 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3677 else
3678 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 3679
49e721ec
GW		 3680 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3681 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3682
3683 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3684 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3685 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3686 !rt2x00_rt(rt2x00dev, RT3070) &&
3687 !rt2x00_rt(rt2x00dev, RT3071) &&
3688 !rt2x00_rt(rt2x00dev, RT3090) &&
3689 !rt2x00_rt(rt2x00dev, RT3390) &&
adde5882
GJ		 3690 !rt2x00_rt(rt2x00dev, RT3572) &&
3691 !rt2x00_rt(rt2x00dev, RT5390)) {
49e721ec
GW		 3692 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3693 return -ENODEV;
f273fe55 3694 }
714fa663 3695
5122d898
GW		 3696 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3697 !rt2x00_rf(rt2x00dev, RF2850) &&
3698 !rt2x00_rf(rt2x00dev, RF2720) &&
3699 !rt2x00_rf(rt2x00dev, RF2750) &&
3700 !rt2x00_rf(rt2x00dev, RF3020) &&
3701 !rt2x00_rf(rt2x00dev, RF2020) &&
3702 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3703 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3 3704 !rt2x00_rf(rt2x00dev, RF3052) &&
adde5882
GJ		 3705 !rt2x00_rf(rt2x00dev, RF3320) &&
3706 !rt2x00_rf(rt2x00dev, RF5390)) {
38bd7b8a
BZ		 3707 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3708 return -ENODEV;
3709 }
3710
3711 /*
3712 * Identify default antenna configuration.
3713 */
d96aa640 3714 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3715 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3716 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3717 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3718
d96aa640
RJH		 3719 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3720
3721 if (rt2x00_rt(rt2x00dev, RT3070) ||
3722 rt2x00_rt(rt2x00dev, RT3090) ||
3723 rt2x00_rt(rt2x00dev, RT3390)) {
3724 value = rt2x00_get_field16(eeprom,
3725 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3726 switch (value) {
3727 case 0:
3728 case 1:
3729 case 2:
3730 rt2x00dev->default_ant.tx = ANTENNA_A;
3731 rt2x00dev->default_ant.rx = ANTENNA_A;
3732 break;
3733 case 3:
3734 rt2x00dev->default_ant.tx = ANTENNA_A;
3735 rt2x00dev->default_ant.rx = ANTENNA_B;
3736 break;
3737 }
3738 } else {
3739 rt2x00dev->default_ant.tx = ANTENNA_A;
3740 rt2x00dev->default_ant.rx = ANTENNA_A;
3741 }
3742
38bd7b8a
BZ		 3743 /*
3744 * Read frequency offset and RF programming sequence.
3745 */
3746 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3747 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3748
3749 /*
3750 * Read external LNA informations.
3751 */
38c8a566 3752 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3753
38c8a566 3754 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 3755 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 3756 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 3757 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 3758
3759 /*
3760 * Detect if this device has an hardware controlled radio.
3761 */
38c8a566 3762 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 3763 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 3764
3765 /*
3766 * Store led settings, for correct led behaviour.
3767 */
3768#ifdef CONFIG_RT2X00_LIB_LEDS
3769 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3770 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3771 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3772
3773 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3774#endif /* CONFIG_RT2X00_LIB_LEDS */
3775
e90c54b2
RJH		 3776 /*
3777 * Check if support EIRP tx power limit feature.
3778 */
3779 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3780
3781 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3782 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 3783 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 3784
38bd7b8a
BZ		 3785 return 0;
3786}
3787EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3788
4da2933f 3789/*
55f9321a 3790 * RF value list for rt28xx
4da2933f
BZ		 3791 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3792 */
3793static const struct rf_channel rf_vals[] = {
3794 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3795 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3796 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3797 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3798 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3799 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3800 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3801 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3802 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3803 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3804 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3805 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3806 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3807 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3808
3809 /* 802.11 UNI / HyperLan 2 */
3810 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3811 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3812 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3813 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3814 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3815 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3816 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3817 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3818 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3819 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3820 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3821 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3822
3823 /* 802.11 HyperLan 2 */
3824 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3825 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3826 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3827 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3828 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3829 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3830 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3831 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3832 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3833 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3834 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3835 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3836 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3837 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3838 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3839 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3840
3841 /* 802.11 UNII */
3842 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3843 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3844 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3845 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3846 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3847 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3848 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3849 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3850 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3851 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3852 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3853
3854 /* 802.11 Japan */
3855 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3856 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3857 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3858 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3859 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3860 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3861 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3862};
3863
3864/*
55f9321a
ID		 3865 * RF value list for rt3xxx
3866 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3867 */
55f9321a 3868static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3869 {1, 241, 2, 2 },
3870 {2, 241, 2, 7 },
3871 {3, 242, 2, 2 },
3872 {4, 242, 2, 7 },
3873 {5, 243, 2, 2 },
3874 {6, 243, 2, 7 },
3875 {7, 244, 2, 2 },
3876 {8, 244, 2, 7 },
3877 {9, 245, 2, 2 },
3878 {10, 245, 2, 7 },
3879 {11, 246, 2, 2 },
3880 {12, 246, 2, 7 },
3881 {13, 247, 2, 2 },
3882 {14, 248, 2, 4 },
55f9321a
ID		 3883
3884 /* 802.11 UNI / HyperLan 2 */
3885 {36, 0x56, 0, 4},
3886 {38, 0x56, 0, 6},
3887 {40, 0x56, 0, 8},
3888 {44, 0x57, 0, 0},
3889 {46, 0x57, 0, 2},
3890 {48, 0x57, 0, 4},
3891 {52, 0x57, 0, 8},
3892 {54, 0x57, 0, 10},
3893 {56, 0x58, 0, 0},
3894 {60, 0x58, 0, 4},
3895 {62, 0x58, 0, 6},
3896 {64, 0x58, 0, 8},
3897
3898 /* 802.11 HyperLan 2 */
3899 {100, 0x5b, 0, 8},
3900 {102, 0x5b, 0, 10},
3901 {104, 0x5c, 0, 0},
3902 {108, 0x5c, 0, 4},
3903 {110, 0x5c, 0, 6},
3904 {112, 0x5c, 0, 8},
3905 {116, 0x5d, 0, 0},
3906 {118, 0x5d, 0, 2},
3907 {120, 0x5d, 0, 4},
3908 {124, 0x5d, 0, 8},
3909 {126, 0x5d, 0, 10},
3910 {128, 0x5e, 0, 0},
3911 {132, 0x5e, 0, 4},
3912 {134, 0x5e, 0, 6},
3913 {136, 0x5e, 0, 8},
3914 {140, 0x5f, 0, 0},
3915
3916 /* 802.11 UNII */
3917 {149, 0x5f, 0, 9},
3918 {151, 0x5f, 0, 11},
3919 {153, 0x60, 0, 1},
3920 {157, 0x60, 0, 5},
3921 {159, 0x60, 0, 7},
3922 {161, 0x60, 0, 9},
3923 {165, 0x61, 0, 1},
3924 {167, 0x61, 0, 3},
3925 {169, 0x61, 0, 5},
3926 {171, 0x61, 0, 7},
3927 {173, 0x61, 0, 9},
4da2933f
BZ		 3928};
3929
3930int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3931{
4da2933f
BZ		 3932 struct hw_mode_spec *spec = &rt2x00dev->spec;
3933 struct channel_info *info;
8d1331b3
ID		 3934 char *default_power1;
3935 char *default_power2;
4da2933f
BZ		 3936 unsigned int i;
3937 u16 eeprom;
3938
93b6bd26
GW		 3939 /*
3940 * Disable powersaving as default on PCI devices.
3941 */
cea90e55 3942 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3943 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3944
4da2933f
BZ		 3945 /*
3946 * Initialize all hw fields.
3947 */
3948 rt2x00dev->hw->flags =
4da2933f
BZ		 3949 IEEE80211_HW_SIGNAL_DBM |
3950 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3951 IEEE80211_HW_PS_NULLFUNC_STACK |
3952 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3953 /*
3954 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3955 * unless we are capable of sending the buffered frames out after the
3956 * DTIM transmission using rt2x00lib_beacondone. This will send out
3957 * multicast and broadcast traffic immediately instead of buffering it
3958 * infinitly and thus dropping it after some time.
3959 */
3960 if (!rt2x00_is_usb(rt2x00dev))
3961 rt2x00dev->hw->flags |=
3962 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3963
4da2933f
BZ		 3964 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3965 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3966 rt2x00_eeprom_addr(rt2x00dev,
3967 EEPROM_MAC_ADDR_0));
3968
3f2bee24
HS		 3969 /*
3970 * As rt2800 has a global fallback table we cannot specify
3971 * more then one tx rate per frame but since the hw will
3972 * try several rates (based on the fallback table) we should
ba3b9e5e 3973 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3974 * we are going to try. Otherwise mac80211 will truncate our
3975 * reported tx rates and the rc algortihm will end up with
3976 * incorrect data.
3977 */
ba3b9e5e
HS		 3978 rt2x00dev->hw->max_rates = 1;
3979 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3980 rt2x00dev->hw->max_rate_tries = 1;
3981
38c8a566 3982 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3983
3984 /*
3985 * Initialize hw_mode information.
3986 */
3987 spec->supported_bands = SUPPORT_BAND_2GHZ;
3988 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3989
5122d898 3990 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3991 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3992 spec->num_channels = 14;
3993 spec->channels = rf_vals;
55f9321a
ID		 3994 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3995 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3996 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3997 spec->num_channels = ARRAY_SIZE(rf_vals);
3998 spec->channels = rf_vals;
5122d898
GW		 3999 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4000 rt2x00_rf(rt2x00dev, RF2020) ||
4001 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4002 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882
GJ		 4003 rt2x00_rf(rt2x00dev, RF3320) ||
4004 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 4005 spec->num_channels = 14;
4006 spec->channels = rf_vals_3x;
4007 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4008 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4009 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4010 spec->channels = rf_vals_3x;
4da2933f
BZ		 4011 }
4012
4013 /*
4014 * Initialize HT information.
4015 */
5122d898 4016 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4017 spec->ht.ht_supported = true;
4018 else
4019 spec->ht.ht_supported = false;
4020
4da2933f 4021 spec->ht.cap =
06443e46 4022 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4023 IEEE80211_HT_CAP_GRN_FLD |
4024 IEEE80211_HT_CAP_SGI_20 |
aa674631 4025 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4026
38c8a566 4027 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4028 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4029
aa674631 4030 spec->ht.cap |=
38c8a566 4031 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4032 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4033
4da2933f
BZ		 4034 spec->ht.ampdu_factor = 3;
4035 spec->ht.ampdu_density = 4;
4036 spec->ht.mcs.tx_params =
4037 IEEE80211_HT_MCS_TX_DEFINED |
4038 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4039 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4040 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4041
38c8a566 4042 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4043 case 3:
4044 spec->ht.mcs.rx_mask[2] = 0xff;
4045 case 2:
4046 spec->ht.mcs.rx_mask[1] = 0xff;
4047 case 1:
4048 spec->ht.mcs.rx_mask[0] = 0xff;
4049 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4050 break;
4051 }
4052
4053 /*
4054 * Create channel information array
4055 */
baeb2ffa 4056 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4057 if (!info)
4058 return -ENOMEM;
4059
4060 spec->channels_info = info;
4061
8d1331b3
ID		 4062 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4063 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4064
4065 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4066 info[i].default_power1 = default_power1[i];
4067 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4068 }
4069
4070 if (spec->num_channels > 14) {
8d1331b3
ID		 4071 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4072 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4073
4074 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4075 info[i].default_power1 = default_power1[i];
4076 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4077 }
4078 }
4079
4080 return 0;
4081}
4082EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4083
2ce33995
BZ		 4084/*
4085 * IEEE80211 stack callback functions.
4086 */
e783619e
HS		 4087void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4088 u16 *iv16)
2ce33995
BZ		 4089{
4090 struct rt2x00_dev *rt2x00dev = hw->priv;
4091 struct mac_iveiv_entry iveiv_entry;
4092 u32 offset;
4093
4094 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4095 rt2800_register_multiread(rt2x00dev, offset,
4096 &iveiv_entry, sizeof(iveiv_entry));
4097
855da5e0
JL		 4098 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4099 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4100}
e783619e 4101EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4102
e783619e 4103int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4104{
4105 struct rt2x00_dev *rt2x00dev = hw->priv;
4106 u32 reg;
4107 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4108
4109 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4110 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4111 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4112
4113 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4114 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4115 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4116
4117 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4118 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4119 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4120
4121 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4122 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4123 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4124
4125 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4126 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4127 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4128
4129 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4130 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4131 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4132
4133 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4134 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4135 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4136
4137 return 0;
4138}
e783619e 4139EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4140
e783619e
HS		 4141int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4142 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4143{
4144 struct rt2x00_dev *rt2x00dev = hw->priv;
4145 struct data_queue *queue;
4146 struct rt2x00_field32 field;
4147 int retval;
4148 u32 reg;
4149 u32 offset;
4150
4151 /*
4152 * First pass the configuration through rt2x00lib, that will
4153 * update the queue settings and validate the input. After that
4154 * we are free to update the registers based on the value
4155 * in the queue parameter.
4156 */
4157 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4158 if (retval)
4159 return retval;
4160
4161 /*
4162 * We only need to perform additional register initialization
4163 * for WMM queues/
4164 */
4165 if (queue_idx >= 4)
4166 return 0;
4167
11f818e0 4168 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4169
4170 /* Update WMM TXOP register */
4171 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4172 field.bit_offset = (queue_idx & 1) * 16;
4173 field.bit_mask = 0xffff << field.bit_offset;
4174
4175 rt2800_register_read(rt2x00dev, offset, &reg);
4176 rt2x00_set_field32(&reg, field, queue->txop);
4177 rt2800_register_write(rt2x00dev, offset, reg);
4178
4179 /* Update WMM registers */
4180 field.bit_offset = queue_idx * 4;
4181 field.bit_mask = 0xf << field.bit_offset;
4182
4183 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4184 rt2x00_set_field32(&reg, field, queue->aifs);
4185 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4186
4187 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4188 rt2x00_set_field32(&reg, field, queue->cw_min);
4189 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4190
4191 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4192 rt2x00_set_field32(&reg, field, queue->cw_max);
4193 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4194
4195 /* Update EDCA registers */
4196 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4197
4198 rt2800_register_read(rt2x00dev, offset, &reg);
4199 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4200 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4201 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4202 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4203 rt2800_register_write(rt2x00dev, offset, reg);
4204
4205 return 0;
4206}
e783619e 4207EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4208
e783619e 4209u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 4210{
4211 struct rt2x00_dev *rt2x00dev = hw->priv;
4212 u64 tsf;
4213 u32 reg;
4214
4215 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4216 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4217 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4218 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4219
4220 return tsf;
4221}
e783619e 4222EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4223
e783619e
HS		 4224int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4225 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4226 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4227 u8 buf_size)
1df90809 4228{
1df90809
HS		 4229 int ret = 0;
4230
4231 switch (action) {
4232 case IEEE80211_AMPDU_RX_START:
4233 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4234 /*
4235 * The hw itself takes care of setting up BlockAck mechanisms.
4236 * So, we only have to allow mac80211 to nagotiate a BlockAck
4237 * agreement. Once that is done, the hw will BlockAck incoming
4238 * AMPDUs without further setup.
4239 */
1df90809
HS		 4240 break;
4241 case IEEE80211_AMPDU_TX_START:
4242 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4243 break;
4244 case IEEE80211_AMPDU_TX_STOP:
4245 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4246 break;
4247 case IEEE80211_AMPDU_TX_OPERATIONAL:
4248 break;
4249 default:
4e9e58c6 4250 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4251 }
4252
4253 return ret;
4254}
e783619e 4255EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4256
977206d7
HS		 4257int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4258 struct survey_info *survey)
4259{
4260 struct rt2x00_dev *rt2x00dev = hw->priv;
4261 struct ieee80211_conf *conf = &hw->conf;
4262 u32 idle, busy, busy_ext;
4263
4264 if (idx != 0)
4265 return -ENOENT;
4266
4267 survey->channel = conf->channel;
4268
4269 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4270 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4271 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4272
4273 if (idle || busy) {
4274 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4275 SURVEY_INFO_CHANNEL_TIME_BUSY |
4276 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4277
4278 survey->channel_time = (idle + busy) / 1000;
4279 survey->channel_time_busy = busy / 1000;
4280 survey->channel_time_ext_busy = busy_ext / 1000;
4281 }
4282
4283 return 0;
4284
4285}
4286EXPORT_SYMBOL_GPL(rt2800_get_survey);
4287
a5ea2f02
ID		 4288MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4289MODULE_VERSION(DRV_VERSION);
4290MODULE_DESCRIPTION("Ralink RT2800 library");
4291MODULE_LICENSE("GPL");
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