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[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
9c9a0d14 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 4
9c9a0d14
GW		 5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38
39#include "rt2x00.h"
ac394917 40#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 41#include "rt2x00usb.h"
42#endif
89297425
BZ		 43#include "rt2800lib.h"
44#include "rt2800.h"
fcf51541 45#include "rt2800usb.h"
89297425
BZ		 46
47MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
48MODULE_DESCRIPTION("rt2800 library");
49MODULE_LICENSE("GPL");
50
51/*
52 * Register access.
53 * All access to the CSR registers will go through the methods
54 * rt2800_register_read and rt2800_register_write.
55 * BBP and RF register require indirect register access,
56 * and use the CSR registers BBPCSR and RFCSR to achieve this.
57 * These indirect registers work with busy bits,
58 * and we will try maximal REGISTER_BUSY_COUNT times to access
59 * the register while taking a REGISTER_BUSY_DELAY us delay
60 * between each attampt. When the busy bit is still set at that time,
61 * the access attempt is considered to have failed,
62 * and we will print an error.
63 * The _lock versions must be used if you already hold the csr_mutex
64 */
65#define WAIT_FOR_BBP(__dev, __reg) \
66 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
67#define WAIT_FOR_RFCSR(__dev, __reg) \
68 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
69#define WAIT_FOR_RF(__dev, __reg) \
70 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
71#define WAIT_FOR_MCU(__dev, __reg) \
72 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
73 H2M_MAILBOX_CSR_OWNER, (__reg))
74
fcf51541
BZ		 75static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
76 const unsigned int word, const u8 value)
89297425
BZ		 77{
78 u32 reg;
79
80 mutex_lock(&rt2x00dev->csr_mutex);
81
82 /*
83 * Wait until the BBP becomes available, afterwards we
84 * can safely write the new data into the register.
85 */
86 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
87 reg = 0;
88 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
89 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
90 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
92 if (rt2x00_intf_is_pci(rt2x00dev))
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
94
95 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
96 }
97
98 mutex_unlock(&rt2x00dev->csr_mutex);
99}
89297425 100
fcf51541
BZ		 101static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
102 const unsigned int word, u8 *value)
89297425
BZ		 103{
104 u32 reg;
105
106 mutex_lock(&rt2x00dev->csr_mutex);
107
108 /*
109 * Wait until the BBP becomes available, afterwards we
110 * can safely write the read request into the register.
111 * After the data has been written, we wait until hardware
112 * returns the correct value, if at any time the register
113 * doesn't become available in time, reg will be 0xffffffff
114 * which means we return 0xff to the caller.
115 */
116 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
117 reg = 0;
118 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
119 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
121 if (rt2x00_intf_is_pci(rt2x00dev))
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
123
124 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
125
126 WAIT_FOR_BBP(rt2x00dev, &reg);
127 }
128
129 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
130
131 mutex_unlock(&rt2x00dev->csr_mutex);
132}
89297425 133
fcf51541
BZ		 134static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
135 const unsigned int word, const u8 value)
89297425
BZ		 136{
137 u32 reg;
138
139 mutex_lock(&rt2x00dev->csr_mutex);
140
141 /*
142 * Wait until the RFCSR becomes available, afterwards we
143 * can safely write the new data into the register.
144 */
145 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
146 reg = 0;
147 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
148 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
151
152 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
153 }
154
155 mutex_unlock(&rt2x00dev->csr_mutex);
156}
89297425 157
fcf51541
BZ		 158static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
159 const unsigned int word, u8 *value)
89297425
BZ		 160{
161 u32 reg;
162
163 mutex_lock(&rt2x00dev->csr_mutex);
164
165 /*
166 * Wait until the RFCSR becomes available, afterwards we
167 * can safely write the read request into the register.
168 * After the data has been written, we wait until hardware
169 * returns the correct value, if at any time the register
170 * doesn't become available in time, reg will be 0xffffffff
171 * which means we return 0xff to the caller.
172 */
173 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
174 reg = 0;
175 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
176 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
178
179 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
180
181 WAIT_FOR_RFCSR(rt2x00dev, &reg);
182 }
183
184 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
185
186 mutex_unlock(&rt2x00dev->csr_mutex);
187}
89297425 188
fcf51541
BZ		 189static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
190 const unsigned int word, const u32 value)
89297425
BZ		 191{
192 u32 reg;
193
194 mutex_lock(&rt2x00dev->csr_mutex);
195
196 /*
197 * Wait until the RF becomes available, afterwards we
198 * can safely write the new data into the register.
199 */
200 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
201 reg = 0;
202 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
206
207 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
208 rt2x00_rf_write(rt2x00dev, word, value);
209 }
210
211 mutex_unlock(&rt2x00dev->csr_mutex);
212}
89297425
BZ		 213
214void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
215 const u8 command, const u8 token,
216 const u8 arg0, const u8 arg1)
217{
218 u32 reg;
219
ee303e54
GW		 220 /*
221 * RT2880 and RT3052 don't support MCU requests.
222 */
5122d898 223 if (rt2x00_rt(rt2x00dev, RT2880) || rt2x00_rt(rt2x00dev, RT3052))
ee303e54 224 return;
89297425
BZ		 225
226 mutex_lock(&rt2x00dev->csr_mutex);
227
228 /*
229 * Wait until the MCU becomes available, afterwards we
230 * can safely write the new data into the register.
231 */
232 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
233 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
234 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
237 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
238
239 reg = 0;
240 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
241 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
242 }
243
244 mutex_unlock(&rt2x00dev->csr_mutex);
245}
246EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 247
67a4c1e2
GW		 248int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
249{
250 unsigned int i;
251 u32 reg;
252
253 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
254 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
255 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
256 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
257 return 0;
258
259 msleep(1);
260 }
261
262 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
263 return -EACCES;
264}
265EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
266
f4450616
BZ		 267#ifdef CONFIG_RT2X00_LIB_DEBUGFS
268const struct rt2x00debug rt2800_rt2x00debug = {
269 .owner = THIS_MODULE,
270 .csr = {
271 .read = rt2800_register_read,
272 .write = rt2800_register_write,
273 .flags = RT2X00DEBUGFS_OFFSET,
274 .word_base = CSR_REG_BASE,
275 .word_size = sizeof(u32),
276 .word_count = CSR_REG_SIZE / sizeof(u32),
277 },
278 .eeprom = {
279 .read = rt2x00_eeprom_read,
280 .write = rt2x00_eeprom_write,
281 .word_base = EEPROM_BASE,
282 .word_size = sizeof(u16),
283 .word_count = EEPROM_SIZE / sizeof(u16),
284 },
285 .bbp = {
286 .read = rt2800_bbp_read,
287 .write = rt2800_bbp_write,
288 .word_base = BBP_BASE,
289 .word_size = sizeof(u8),
290 .word_count = BBP_SIZE / sizeof(u8),
291 },
292 .rf = {
293 .read = rt2x00_rf_read,
294 .write = rt2800_rf_write,
295 .word_base = RF_BASE,
296 .word_size = sizeof(u32),
297 .word_count = RF_SIZE / sizeof(u32),
298 },
299};
300EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
301#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
302
303int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
304{
305 u32 reg;
306
307 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
308 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
309}
310EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
311
312#ifdef CONFIG_RT2X00_LIB_LEDS
313static void rt2800_brightness_set(struct led_classdev *led_cdev,
314 enum led_brightness brightness)
315{
316 struct rt2x00_led *led =
317 container_of(led_cdev, struct rt2x00_led, led_dev);
318 unsigned int enabled = brightness != LED_OFF;
319 unsigned int bg_mode =
320 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
321 unsigned int polarity =
322 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
323 EEPROM_FREQ_LED_POLARITY);
324 unsigned int ledmode =
325 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
326 EEPROM_FREQ_LED_MODE);
327
328 if (led->type == LED_TYPE_RADIO) {
329 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
330 enabled ? 0x20 : 0);
331 } else if (led->type == LED_TYPE_ASSOC) {
332 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
333 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
334 } else if (led->type == LED_TYPE_QUALITY) {
335 /*
336 * The brightness is divided into 6 levels (0 - 5),
337 * The specs tell us the following levels:
338 * 0, 1 ,3, 7, 15, 31
339 * to determine the level in a simple way we can simply
340 * work with bitshifting:
341 * (1 << level) - 1
342 */
343 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
344 (1 << brightness / (LED_FULL / 6)) - 1,
345 polarity);
346 }
347}
348
349static int rt2800_blink_set(struct led_classdev *led_cdev,
350 unsigned long *delay_on, unsigned long *delay_off)
351{
352 struct rt2x00_led *led =
353 container_of(led_cdev, struct rt2x00_led, led_dev);
354 u32 reg;
355
356 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
357 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
358 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
359 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
360 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
301a8234 361 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
f4450616
BZ		 362 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
363 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
364 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
365
366 return 0;
367}
368
b3579d6a 369static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 370 struct rt2x00_led *led, enum led_type type)
371{
372 led->rt2x00dev = rt2x00dev;
373 led->type = type;
374 led->led_dev.brightness_set = rt2800_brightness_set;
375 led->led_dev.blink_set = rt2800_blink_set;
376 led->flags = LED_INITIALIZED;
377}
f4450616
BZ		 378#endif /* CONFIG_RT2X00_LIB_LEDS */
379
380/*
381 * Configuration handlers.
382 */
383static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
384 struct rt2x00lib_crypto *crypto,
385 struct ieee80211_key_conf *key)
386{
387 struct mac_wcid_entry wcid_entry;
388 struct mac_iveiv_entry iveiv_entry;
389 u32 offset;
390 u32 reg;
391
392 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
393
394 rt2800_register_read(rt2x00dev, offset, &reg);
395 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
396 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
397 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
398 (crypto->cmd == SET_KEY) * crypto->cipher);
399 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
400 (crypto->cmd == SET_KEY) * crypto->bssidx);
401 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
402 rt2800_register_write(rt2x00dev, offset, reg);
403
404 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
405
406 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
407 if ((crypto->cipher == CIPHER_TKIP) ||
408 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
409 (crypto->cipher == CIPHER_AES))
410 iveiv_entry.iv[3] |= 0x20;
411 iveiv_entry.iv[3] |= key->keyidx << 6;
412 rt2800_register_multiwrite(rt2x00dev, offset,
413 &iveiv_entry, sizeof(iveiv_entry));
414
415 offset = MAC_WCID_ENTRY(key->hw_key_idx);
416
417 memset(&wcid_entry, 0, sizeof(wcid_entry));
418 if (crypto->cmd == SET_KEY)
419 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
420 rt2800_register_multiwrite(rt2x00dev, offset,
421 &wcid_entry, sizeof(wcid_entry));
422}
423
424int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
425 struct rt2x00lib_crypto *crypto,
426 struct ieee80211_key_conf *key)
427{
428 struct hw_key_entry key_entry;
429 struct rt2x00_field32 field;
430 u32 offset;
431 u32 reg;
432
433 if (crypto->cmd == SET_KEY) {
434 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
435
436 memcpy(key_entry.key, crypto->key,
437 sizeof(key_entry.key));
438 memcpy(key_entry.tx_mic, crypto->tx_mic,
439 sizeof(key_entry.tx_mic));
440 memcpy(key_entry.rx_mic, crypto->rx_mic,
441 sizeof(key_entry.rx_mic));
442
443 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
444 rt2800_register_multiwrite(rt2x00dev, offset,
445 &key_entry, sizeof(key_entry));
446 }
447
448 /*
449 * The cipher types are stored over multiple registers
450 * starting with SHARED_KEY_MODE_BASE each word will have
451 * 32 bits and contains the cipher types for 2 bssidx each.
452 * Using the correct defines correctly will cause overhead,
453 * so just calculate the correct offset.
454 */
455 field.bit_offset = 4 * (key->hw_key_idx % 8);
456 field.bit_mask = 0x7 << field.bit_offset;
457
458 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
459
460 rt2800_register_read(rt2x00dev, offset, &reg);
461 rt2x00_set_field32(&reg, field,
462 (crypto->cmd == SET_KEY) * crypto->cipher);
463 rt2800_register_write(rt2x00dev, offset, reg);
464
465 /*
466 * Update WCID information
467 */
468 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
469
470 return 0;
471}
472EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
473
474int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
475 struct rt2x00lib_crypto *crypto,
476 struct ieee80211_key_conf *key)
477{
478 struct hw_key_entry key_entry;
479 u32 offset;
480
481 if (crypto->cmd == SET_KEY) {
482 /*
483 * 1 pairwise key is possible per AID, this means that the AID
484 * equals our hw_key_idx. Make sure the WCID starts _after_ the
485 * last possible shared key entry.
486 */
487 if (crypto->aid > (256 - 32))
488 return -ENOSPC;
489
490 key->hw_key_idx = 32 + crypto->aid;
491
492 memcpy(key_entry.key, crypto->key,
493 sizeof(key_entry.key));
494 memcpy(key_entry.tx_mic, crypto->tx_mic,
495 sizeof(key_entry.tx_mic));
496 memcpy(key_entry.rx_mic, crypto->rx_mic,
497 sizeof(key_entry.rx_mic));
498
499 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
500 rt2800_register_multiwrite(rt2x00dev, offset,
501 &key_entry, sizeof(key_entry));
502 }
503
504 /*
505 * Update WCID information
506 */
507 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
508
509 return 0;
510}
511EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
512
513void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
514 const unsigned int filter_flags)
515{
516 u32 reg;
517
518 /*
519 * Start configuration steps.
520 * Note that the version error will always be dropped
521 * and broadcast frames will always be accepted since
522 * there is no filter for it at this time.
523 */
524 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
525 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
526 !(filter_flags & FIF_FCSFAIL));
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
528 !(filter_flags & FIF_PLCPFAIL));
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
530 !(filter_flags & FIF_PROMISC_IN_BSS));
531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
532 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
533 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
534 !(filter_flags & FIF_ALLMULTI));
535 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
538 !(filter_flags & FIF_CONTROL));
539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
540 !(filter_flags & FIF_CONTROL));
541 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
542 !(filter_flags & FIF_CONTROL));
543 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
544 !(filter_flags & FIF_CONTROL));
545 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
546 !(filter_flags & FIF_CONTROL));
547 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
548 !(filter_flags & FIF_PSPOLL));
549 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
550 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
551 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
552 !(filter_flags & FIF_CONTROL));
553 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
554}
555EXPORT_SYMBOL_GPL(rt2800_config_filter);
556
557void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
558 struct rt2x00intf_conf *conf, const unsigned int flags)
559{
560 unsigned int beacon_base;
561 u32 reg;
562
563 if (flags & CONFIG_UPDATE_TYPE) {
564 /*
565 * Clear current synchronisation setup.
566 * For the Beacon base registers we only need to clear
567 * the first byte since that byte contains the VALID and OWNER
568 * bits which (when set to 0) will invalidate the entire beacon.
569 */
570 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
571 rt2800_register_write(rt2x00dev, beacon_base, 0);
572
573 /*
574 * Enable synchronisation.
575 */
576 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
577 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
578 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 579 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
580 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 581 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
582 }
583
584 if (flags & CONFIG_UPDATE_MAC) {
585 reg = le32_to_cpu(conf->mac[1]);
586 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
587 conf->mac[1] = cpu_to_le32(reg);
588
589 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
590 conf->mac, sizeof(conf->mac));
591 }
592
593 if (flags & CONFIG_UPDATE_BSSID) {
594 reg = le32_to_cpu(conf->bssid[1]);
595 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
596 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
597 conf->bssid[1] = cpu_to_le32(reg);
598
599 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
600 conf->bssid, sizeof(conf->bssid));
601 }
602}
603EXPORT_SYMBOL_GPL(rt2800_config_intf);
604
605void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
606{
607 u32 reg;
608
609 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
610 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
611 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
612
613 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
614 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
615 !!erp->short_preamble);
616 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
617 !!erp->short_preamble);
618 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
619
620 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
621 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
622 erp->cts_protection ? 2 : 0);
623 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
624
625 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
626 erp->basic_rates);
627 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
628
629 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
630 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
631 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
632 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
633
634 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
635 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
636 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
637 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
638 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
639 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
640 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
641
642 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
643 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
644 erp->beacon_int * 16);
645 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
646}
647EXPORT_SYMBOL_GPL(rt2800_config_erp);
648
649void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
650{
651 u8 r1;
652 u8 r3;
653
654 rt2800_bbp_read(rt2x00dev, 1, &r1);
655 rt2800_bbp_read(rt2x00dev, 3, &r3);
656
657 /*
658 * Configure the TX antenna.
659 */
660 switch ((int)ant->tx) {
661 case 1:
662 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
663 if (rt2x00_intf_is_pci(rt2x00dev))
664 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
665 break;
666 case 2:
667 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
668 break;
669 case 3:
670 /* Do nothing */
671 break;
672 }
673
674 /*
675 * Configure the RX antenna.
676 */
677 switch ((int)ant->rx) {
678 case 1:
679 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
680 break;
681 case 2:
682 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
683 break;
684 case 3:
685 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
686 break;
687 }
688
689 rt2800_bbp_write(rt2x00dev, 3, r3);
690 rt2800_bbp_write(rt2x00dev, 1, r1);
691}
692EXPORT_SYMBOL_GPL(rt2800_config_ant);
693
694static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
695 struct rt2x00lib_conf *libconf)
696{
697 u16 eeprom;
698 short lna_gain;
699
700 if (libconf->rf.channel <= 14) {
701 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
702 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
703 } else if (libconf->rf.channel <= 64) {
704 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
705 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
706 } else if (libconf->rf.channel <= 128) {
707 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
708 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
709 } else {
710 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
711 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
712 }
713
714 rt2x00dev->lna_gain = lna_gain;
715}
716
717static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
718 struct ieee80211_conf *conf,
719 struct rf_channel *rf,
720 struct channel_info *info)
721{
722 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
723
724 if (rt2x00dev->default_ant.tx == 1)
725 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
726
727 if (rt2x00dev->default_ant.rx == 1) {
728 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
729 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
730 } else if (rt2x00dev->default_ant.rx == 2)
731 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
732
733 if (rf->channel > 14) {
734 /*
735 * When TX power is below 0, we should increase it by 7 to
736 * make it a positive value (Minumum value is -7).
737 * However this means that values between 0 and 7 have
738 * double meaning, and we should set a 7DBm boost flag.
739 */
740 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
741 (info->tx_power1 >= 0));
742
743 if (info->tx_power1 < 0)
744 info->tx_power1 += 7;
745
746 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
747 TXPOWER_A_TO_DEV(info->tx_power1));
748
749 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
750 (info->tx_power2 >= 0));
751
752 if (info->tx_power2 < 0)
753 info->tx_power2 += 7;
754
755 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
756 TXPOWER_A_TO_DEV(info->tx_power2));
757 } else {
758 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
759 TXPOWER_G_TO_DEV(info->tx_power1));
760 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
761 TXPOWER_G_TO_DEV(info->tx_power2));
762 }
763
764 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
765
766 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
767 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
768 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
769 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
770
771 udelay(200);
772
773 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
774 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
775 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
776 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
777
778 udelay(200);
779
780 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
781 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
782 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
783 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
784}
785
786static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
787 struct ieee80211_conf *conf,
788 struct rf_channel *rf,
789 struct channel_info *info)
790{
791 u8 rfcsr;
792
793 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 794 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 795
796 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
797 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
798 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
799
800 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
801 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
802 TXPOWER_G_TO_DEV(info->tx_power1));
803 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
804
805 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
806 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
807 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
808
809 rt2800_rfcsr_write(rt2x00dev, 24,
810 rt2x00dev->calibration[conf_is_ht40(conf)]);
811
812 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
813 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
814 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
815}
816
817static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
818 struct ieee80211_conf *conf,
819 struct rf_channel *rf,
820 struct channel_info *info)
821{
822 u32 reg;
823 unsigned int tx_pin;
824 u8 bbp;
825
5122d898
GW		 826 if ((rt2x00_rt(rt2x00dev, RT3070) ||
827 rt2x00_rt(rt2x00dev, RT3090)) &&
828 (rt2x00_rf(rt2x00dev, RF2020) ||
829 rt2x00_rf(rt2x00dev, RF3020) ||
830 rt2x00_rf(rt2x00dev, RF3021) ||
831 rt2x00_rf(rt2x00dev, RF3022)))
f4450616 832 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
fa6f632f
GW		 833 else
834 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
f4450616
BZ		 835
836 /*
837 * Change BBP settings
838 */
839 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
840 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
841 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
842 rt2800_bbp_write(rt2x00dev, 86, 0);
843
844 if (rf->channel <= 14) {
845 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
846 rt2800_bbp_write(rt2x00dev, 82, 0x62);
847 rt2800_bbp_write(rt2x00dev, 75, 0x46);
848 } else {
849 rt2800_bbp_write(rt2x00dev, 82, 0x84);
850 rt2800_bbp_write(rt2x00dev, 75, 0x50);
851 }
852 } else {
853 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
854
855 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
856 rt2800_bbp_write(rt2x00dev, 75, 0x46);
857 else
858 rt2800_bbp_write(rt2x00dev, 75, 0x50);
859 }
860
861 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
862 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
863 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
864 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
865 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
866
867 tx_pin = 0;
868
869 /* Turn on unused PA or LNA when not using 1T or 1R */
870 if (rt2x00dev->default_ant.tx != 1) {
871 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
872 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
873 }
874
875 /* Turn on unused PA or LNA when not using 1T or 1R */
876 if (rt2x00dev->default_ant.rx != 1) {
877 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
878 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
879 }
880
881 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
882 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
883 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
884 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
885 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
886 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
887
888 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
889
890 rt2800_bbp_read(rt2x00dev, 4, &bbp);
891 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
892 rt2800_bbp_write(rt2x00dev, 4, bbp);
893
894 rt2800_bbp_read(rt2x00dev, 3, &bbp);
895 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
896 rt2800_bbp_write(rt2x00dev, 3, bbp);
897
5122d898 898 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
f4450616
BZ		 899 if (conf_is_ht40(conf)) {
900 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
901 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
902 rt2800_bbp_write(rt2x00dev, 73, 0x16);
903 } else {
904 rt2800_bbp_write(rt2x00dev, 69, 0x16);
905 rt2800_bbp_write(rt2x00dev, 70, 0x08);
906 rt2800_bbp_write(rt2x00dev, 73, 0x11);
907 }
908 }
909
910 msleep(1);
911}
912
913static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
914 const int txpower)
915{
916 u32 reg;
917 u32 value = TXPOWER_G_TO_DEV(txpower);
918 u8 r1;
919
920 rt2800_bbp_read(rt2x00dev, 1, &r1);
921 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
922 rt2800_bbp_write(rt2x00dev, 1, r1);
923
924 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
933 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
934
935 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
938 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
939 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
940 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
941 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
944 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
945
946 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
947 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
948 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
949 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
950 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
951 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
952 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
953 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
954 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
955 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
956
957 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
958 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
959 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
960 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
961 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
962 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
963 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
964 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
965 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
966 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
967
968 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
969 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
970 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
971 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
972 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
973 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
974}
975
976static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
977 struct rt2x00lib_conf *libconf)
978{
979 u32 reg;
980
981 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
982 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
983 libconf->conf->short_frame_max_tx_count);
984 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
985 libconf->conf->long_frame_max_tx_count);
986 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
987 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
988 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
989 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
990 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
991}
992
993static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
994 struct rt2x00lib_conf *libconf)
995{
996 enum dev_state state =
997 (libconf->conf->flags & IEEE80211_CONF_PS) ?
998 STATE_SLEEP : STATE_AWAKE;
999 u32 reg;
1000
1001 if (state == STATE_SLEEP) {
1002 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1003
1004 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1005 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1006 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1007 libconf->conf->listen_interval - 1);
1008 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1009 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1010
1011 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1012 } else {
1013 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1014
1015 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1016 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1017 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1018 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1019 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1020 }
1021}
1022
1023void rt2800_config(struct rt2x00_dev *rt2x00dev,
1024 struct rt2x00lib_conf *libconf,
1025 const unsigned int flags)
1026{
1027 /* Always recalculate LNA gain before changing configuration */
1028 rt2800_config_lna_gain(rt2x00dev, libconf);
1029
1030 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1031 rt2800_config_channel(rt2x00dev, libconf->conf,
1032 &libconf->rf, &libconf->channel);
1033 if (flags & IEEE80211_CONF_CHANGE_POWER)
1034 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1035 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1036 rt2800_config_retry_limit(rt2x00dev, libconf);
1037 if (flags & IEEE80211_CONF_CHANGE_PS)
1038 rt2800_config_ps(rt2x00dev, libconf);
1039}
1040EXPORT_SYMBOL_GPL(rt2800_config);
1041
1042/*
1043 * Link tuning
1044 */
1045void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1046{
1047 u32 reg;
1048
1049 /*
1050 * Update FCS error count from register.
1051 */
1052 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1053 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1054}
1055EXPORT_SYMBOL_GPL(rt2800_link_stats);
1056
1057static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1058{
1059 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1060 if (rt2x00_intf_is_usb(rt2x00dev) &&
5122d898 1061 rt2x00_rev(rt2x00dev) == RT3070_VERSION)
f4450616
BZ		 1062 return 0x1c + (2 * rt2x00dev->lna_gain);
1063 else
1064 return 0x2e + rt2x00dev->lna_gain;
1065 }
1066
1067 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1068 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1069 else
1070 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1071}
1072
1073static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1074 struct link_qual *qual, u8 vgc_level)
1075{
1076 if (qual->vgc_level != vgc_level) {
1077 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1078 qual->vgc_level = vgc_level;
1079 qual->vgc_level_reg = vgc_level;
1080 }
1081}
1082
1083void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1084{
1085 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1086}
1087EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1088
1089void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1090 const u32 count)
1091{
5122d898 1092 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)
f4450616
BZ		 1093 return;
1094
1095 /*
1096 * When RSSI is better then -80 increase VGC level with 0x10
1097 */
1098 rt2800_set_vgc(rt2x00dev, qual,
1099 rt2800_get_default_vgc(rt2x00dev) +
1100 ((qual->rssi > -80) * 0x10));
1101}
1102EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1103
1104/*
1105 * Initialization functions.
1106 */
1107int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1108{
1109 u32 reg;
1110 unsigned int i;
1111
1112 if (rt2x00_intf_is_usb(rt2x00dev)) {
1113 /*
235faf9b 1114 * Wait until BBP and RF are ready.
fcf51541
BZ		 1115 */
1116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1117 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1118 if (reg && reg != ~0)
1119 break;
1120 msleep(1);
1121 }
1122
1123 if (i == REGISTER_BUSY_COUNT) {
1124 ERROR(rt2x00dev, "Unstable hardware.\n");
1125 return -EBUSY;
1126 }
1127
1128 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1129 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1130 reg & ~0x00002000);
1131 } else if (rt2x00_intf_is_pci(rt2x00dev))
1132 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1133
1134 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1135 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1136 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1137 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1138
1139 if (rt2x00_intf_is_usb(rt2x00dev)) {
1140 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
ac394917 1141#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 1142 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1143 USB_MODE_RESET, REGISTER_TIMEOUT);
1144#endif
1145 }
1146
1147 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1148
1149 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1150 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1151 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1152 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1153 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1154 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1155
1156 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1157 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1158 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1159 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1160 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1161 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1162
1163 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1164 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1165
1166 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1167
1168 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1169 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1170 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1171 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1172 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1173 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1174 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1175 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1176
1177 if (rt2x00_intf_is_usb(rt2x00dev) &&
5122d898 1178 rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
fcf51541
BZ		 1179 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1180 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1181 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1182 } else {
1183 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1184 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1185 }
1186
1187 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1188 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1189 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1190 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1191 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1192 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1193 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1194 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1195 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1196 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1197
1198 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1199 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1200 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1201 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1202
1203 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1204 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5122d898
GW		 1205 if (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION &&
1206 rt2x00_rev(rt2x00dev) < RT3070_VERSION)
fcf51541
BZ		 1207 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1208 else
1209 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1210 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1211 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1212 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1213
1214 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1215
1216 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1217 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1218 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1219 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1220 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1221 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1222 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1223
1224 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1225 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1226 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1227 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1228 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1229 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1230 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1231 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1232 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1233 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1234 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1235
1236 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1237 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1238 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1239 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1240 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1241 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1242 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1243 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1244 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1245 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1246 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1247
1248 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1249 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1250 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1251 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1252 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1253 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1254 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1255 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1256 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1257 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1258 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1259
1260 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1261 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1262 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1263 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1264 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1265 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1266 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1267 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1268 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1269 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1270 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1271
1272 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1273 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1274 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1275 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1276 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1277 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1278 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1279 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1280 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1281 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1282 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1283
1284 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1285 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1286 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1287 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1288 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1289 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1290 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1291 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1292 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1293 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1294 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1295
1296 if (rt2x00_intf_is_usb(rt2x00dev)) {
1297 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1298
1299 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1300 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1301 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1302 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1308 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1309 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1310 }
1311
1312 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1313 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1314
1315 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1316 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1317 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1318 IEEE80211_MAX_RTS_THRESHOLD);
1319 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1320 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1321
1322 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1323 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1324
1325 /*
1326 * ASIC will keep garbage value after boot, clear encryption keys.
1327 */
1328 for (i = 0; i < 4; i++)
1329 rt2800_register_write(rt2x00dev,
1330 SHARED_KEY_MODE_ENTRY(i), 0);
1331
1332 for (i = 0; i < 256; i++) {
1333 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1334 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1335 wcid, sizeof(wcid));
1336
1337 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1338 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1339 }
1340
1341 /*
1342 * Clear all beacons
1343 * For the Beacon base registers we only need to clear
1344 * the first byte since that byte contains the VALID and OWNER
1345 * bits which (when set to 0) will invalidate the entire beacon.
1346 */
1347 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1348 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1349 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1350 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1351 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1352 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1353 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1354 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1355
1356 if (rt2x00_intf_is_usb(rt2x00dev)) {
1357 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1358 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1359 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1360 }
1361
1362 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1363 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1364 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1365 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1366 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1367 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1368 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1369 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1370 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1371 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1372
1373 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1374 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1375 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1376 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1377 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1378 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1379 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1380 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1381 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1382 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1383
1384 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1385 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1386 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1387 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1388 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1389 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1390 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1391 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1392 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1393 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1394
1395 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1396 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1397 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1398 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1399 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1400 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1401
1402 /*
1403 * We must clear the error counters.
1404 * These registers are cleared on read,
1405 * so we may pass a useless variable to store the value.
1406 */
1407 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1408 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1409 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1410 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1411 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1412 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1413
1414 return 0;
1415}
1416EXPORT_SYMBOL_GPL(rt2800_init_registers);
1417
1418static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1419{
1420 unsigned int i;
1421 u32 reg;
1422
1423 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1424 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1425 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1426 return 0;
1427
1428 udelay(REGISTER_BUSY_DELAY);
1429 }
1430
1431 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1432 return -EACCES;
1433}
1434
1435static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1436{
1437 unsigned int i;
1438 u8 value;
1439
1440 /*
1441 * BBP was enabled after firmware was loaded,
1442 * but we need to reactivate it now.
1443 */
1444 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1445 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1446 msleep(1);
1447
1448 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1449 rt2800_bbp_read(rt2x00dev, 0, &value);
1450 if ((value != 0xff) && (value != 0x00))
1451 return 0;
1452 udelay(REGISTER_BUSY_DELAY);
1453 }
1454
1455 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1456 return -EACCES;
1457}
1458
1459int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1460{
1461 unsigned int i;
1462 u16 eeprom;
1463 u8 reg_id;
1464 u8 value;
1465
1466 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1467 rt2800_wait_bbp_ready(rt2x00dev)))
1468 return -EACCES;
1469
1470 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1471 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1472 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1473 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1474 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1475 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1476 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1477 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1478 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1479 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1480 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1481 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1482 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1483 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1484
5122d898 1485 if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
fcf51541
BZ		 1486 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1487 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1488 }
1489
5122d898 1490 if (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)
fcf51541
BZ		 1491 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1492
1493 if (rt2x00_intf_is_usb(rt2x00dev) &&
5122d898 1494 rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
fcf51541
BZ		 1495 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1496 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1497 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1498 }
1499
5122d898 1500 if (rt2x00_rt(rt2x00dev, RT3052)) {
fcf51541
BZ		 1501 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1502 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1503 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1504 }
1505
1506 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1507 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1508
1509 if (eeprom != 0xffff && eeprom != 0x0000) {
1510 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1511 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1512 rt2800_bbp_write(rt2x00dev, reg_id, value);
1513 }
1514 }
1515
1516 return 0;
1517}
1518EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1519
1520static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1521 bool bw40, u8 rfcsr24, u8 filter_target)
1522{
1523 unsigned int i;
1524 u8 bbp;
1525 u8 rfcsr;
1526 u8 passband;
1527 u8 stopband;
1528 u8 overtuned = 0;
1529
1530 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1531
1532 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1533 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1534 rt2800_bbp_write(rt2x00dev, 4, bbp);
1535
1536 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1537 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1538 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1539
1540 /*
1541 * Set power & frequency of passband test tone
1542 */
1543 rt2800_bbp_write(rt2x00dev, 24, 0);
1544
1545 for (i = 0; i < 100; i++) {
1546 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1547 msleep(1);
1548
1549 rt2800_bbp_read(rt2x00dev, 55, &passband);
1550 if (passband)
1551 break;
1552 }
1553
1554 /*
1555 * Set power & frequency of stopband test tone
1556 */
1557 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1558
1559 for (i = 0; i < 100; i++) {
1560 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1561 msleep(1);
1562
1563 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1564
1565 if ((passband - stopband) <= filter_target) {
1566 rfcsr24++;
1567 overtuned += ((passband - stopband) == filter_target);
1568 } else
1569 break;
1570
1571 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1572 }
1573
1574 rfcsr24 -= !!overtuned;
1575
1576 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1577 return rfcsr24;
1578}
1579
1580int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1581{
1582 u8 rfcsr;
1583 u8 bbp;
1584
1585 if (rt2x00_intf_is_usb(rt2x00dev) &&
5122d898 1586 rt2x00_rev(rt2x00dev) != RT3070_VERSION)
fcf51541
BZ		 1587 return 0;
1588
1589 if (rt2x00_intf_is_pci(rt2x00dev)) {
5122d898
GW		 1590 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1591 !rt2x00_rf(rt2x00dev, RF3021) &&
1592 !rt2x00_rf(rt2x00dev, RF3022))
fcf51541
BZ		 1593 return 0;
1594 }
1595
1596 /*
1597 * Init RF calibration.
1598 */
1599 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1600 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1601 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1602 msleep(1);
1603 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1604 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1605
1606 if (rt2x00_intf_is_usb(rt2x00dev)) {
1607 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1608 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1609 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1610 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1611 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1612 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1613 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1614 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1615 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1616 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1617 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1618 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1619 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1620 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1621 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1622 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1623 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1624 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1625 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1626 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1627 } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1628 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1629 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1630 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1631 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1632 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1633 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1634 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1635 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1636 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1637 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1638 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1639 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1640 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1641 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1642 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1643 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1644 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1645 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1646 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1647 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1648 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1649 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1650 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1651 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1652 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1653 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1654 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1655 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1656 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1657 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1658 }
1659
1660 /*
1661 * Set RX Filter calibration for 20MHz and 40MHz
1662 */
1663 rt2x00dev->calibration[0] =
1664 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1665 rt2x00dev->calibration[1] =
1666 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1667
1668 /*
1669 * Set back to initial state
1670 */
1671 rt2800_bbp_write(rt2x00dev, 24, 0);
1672
1673 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1674 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1675 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1676
1677 /*
1678 * set BBP back to BW20
1679 */
1680 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1681 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1682 rt2800_bbp_write(rt2x00dev, 4, bbp);
1683
1684 return 0;
1685}
1686EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 1687
30e84034
BZ		 1688int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1689{
1690 u32 reg;
1691
1692 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1693
1694 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1695}
1696EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1697
1698static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1699{
1700 u32 reg;
1701
31a4cf1f
GW		 1702 mutex_lock(&rt2x00dev->csr_mutex);
1703
1704 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 1705 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1706 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1707 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 1708 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 1709
1710 /* Wait until the EEPROM has been loaded */
1711 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1712
1713 /* Apparently the data is read from end to start */
31a4cf1f
GW		 1714 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1715 (u32 *)&rt2x00dev->eeprom[i]);
1716 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1717 (u32 *)&rt2x00dev->eeprom[i + 2]);
1718 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1719 (u32 *)&rt2x00dev->eeprom[i + 4]);
1720 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1721 (u32 *)&rt2x00dev->eeprom[i + 6]);
1722
1723 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 1724}
1725
1726void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1727{
1728 unsigned int i;
1729
1730 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1731 rt2800_efuse_read(rt2x00dev, i);
1732}
1733EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1734
38bd7b8a
BZ		 1735int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1736{
1737 u16 word;
1738 u8 *mac;
1739 u8 default_lna_gain;
1740
1741 /*
1742 * Start validation of the data that has been read.
1743 */
1744 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1745 if (!is_valid_ether_addr(mac)) {
1746 random_ether_addr(mac);
1747 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1748 }
1749
1750 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1751 if (word == 0xffff) {
1752 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1753 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1754 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1755 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1756 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5122d898 1757 } else if (rt2x00_rev(rt2x00dev) < RT2883_VERSION) {
38bd7b8a
BZ		 1758 /*
1759 * There is a max of 2 RX streams for RT28x0 series
1760 */
1761 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1762 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1763 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1764 }
1765
1766 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1767 if (word == 0xffff) {
1768 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1769 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1770 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1771 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1772 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1773 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1774 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1775 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1776 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1777 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1778 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1779 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1780 }
1781
1782 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1783 if ((word & 0x00ff) == 0x00ff) {
1784 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1785 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1786 LED_MODE_TXRX_ACTIVITY);
1787 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1788 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1789 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1790 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1791 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1792 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1793 }
1794
1795 /*
1796 * During the LNA validation we are going to use
1797 * lna0 as correct value. Note that EEPROM_LNA
1798 * is never validated.
1799 */
1800 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1801 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1802
1803 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1804 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1805 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1806 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1807 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1808 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1809
1810 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1811 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1812 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1813 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1814 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1815 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1816 default_lna_gain);
1817 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1818
1819 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1820 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1821 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1822 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1823 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1824 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1825
1826 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1827 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1828 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1829 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1830 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1831 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1832 default_lna_gain);
1833 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1834
1835 return 0;
1836}
1837EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1838
1839int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1840{
1841 u32 reg;
1842 u16 value;
1843 u16 eeprom;
1844
1845 /*
1846 * Read EEPROM word for configuration.
1847 */
1848 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1849
1850 /*
1851 * Identify RF chipset.
1852 */
1853 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1854 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1855
f273fe55
GW		 1856 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1857
38bd7b8a 1858 if (rt2x00_intf_is_usb(rt2x00dev)) {
38bd7b8a
BZ		 1859 /*
1860 * The check for rt2860 is not a typo, some rt2870 hardware
1861 * identifies itself as rt2860 in the CSR register.
1862 */
5122d898
GW		 1863 if (rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28600000) ||
1864 rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28700000) ||
1865 rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28800000)) {
f273fe55 1866 rt2x00_set_chip_rt(rt2x00dev, RT2870);
5122d898 1867 } else if (rt2x00_check_rev(rt2x00dev, 0xffff0000, 0x30700000)) {
f273fe55
GW		 1868 rt2x00_set_chip_rt(rt2x00dev, RT3070);
1869 } else {
38bd7b8a
BZ		 1870 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1871 return -ENODEV;
1872 }
f273fe55 1873 }
16475b09 1874 rt2x00_print_chip(rt2x00dev);
38bd7b8a 1875
5122d898
GW		 1876 if (!rt2x00_rf(rt2x00dev, RF2820) &&
1877 !rt2x00_rf(rt2x00dev, RF2850) &&
1878 !rt2x00_rf(rt2x00dev, RF2720) &&
1879 !rt2x00_rf(rt2x00dev, RF2750) &&
1880 !rt2x00_rf(rt2x00dev, RF3020) &&
1881 !rt2x00_rf(rt2x00dev, RF2020) &&
1882 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 1883 !rt2x00_rf(rt2x00dev, RF3022) &&
1884 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 1885 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1886 return -ENODEV;
1887 }
1888
1889 /*
1890 * Identify default antenna configuration.
1891 */
1892 rt2x00dev->default_ant.tx =
1893 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1894 rt2x00dev->default_ant.rx =
1895 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1896
1897 /*
1898 * Read frequency offset and RF programming sequence.
1899 */
1900 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1901 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1902
1903 /*
1904 * Read external LNA informations.
1905 */
1906 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1907
1908 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1909 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1910 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1911 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1912
1913 /*
1914 * Detect if this device has an hardware controlled radio.
1915 */
1916 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1917 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1918
1919 /*
1920 * Store led settings, for correct led behaviour.
1921 */
1922#ifdef CONFIG_RT2X00_LIB_LEDS
1923 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1924 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1925 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1926
1927 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1928#endif /* CONFIG_RT2X00_LIB_LEDS */
1929
1930 return 0;
1931}
1932EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1933
4da2933f
BZ		 1934/*
1935 * RF value list for rt28x0
1936 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1937 */
1938static const struct rf_channel rf_vals[] = {
1939 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1940 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1941 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1942 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1943 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1944 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1945 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1946 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1947 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1948 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1949 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1950 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1951 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1952 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1953
1954 /* 802.11 UNI / HyperLan 2 */
1955 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1956 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1957 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1958 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1959 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1960 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1961 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1962 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1963 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1964 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1965 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1966 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1967
1968 /* 802.11 HyperLan 2 */
1969 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1970 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1971 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1972 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1973 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1974 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1975 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1976 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1977 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1978 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1979 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1980 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1981 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1982 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1983 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1984 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1985
1986 /* 802.11 UNII */
1987 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1988 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1989 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1990 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1991 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1992 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1993 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1994 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1995 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1996 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1997 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1998
1999 /* 802.11 Japan */
2000 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2001 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2002 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2003 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2004 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2005 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2006 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2007};
2008
2009/*
2010 * RF value list for rt3070
2011 * Supports: 2.4 GHz
2012 */
cce5fc45 2013static const struct rf_channel rf_vals_302x[] = {
4da2933f
BZ		 2014 {1, 241, 2, 2 },
2015 {2, 241, 2, 7 },
2016 {3, 242, 2, 2 },
2017 {4, 242, 2, 7 },
2018 {5, 243, 2, 2 },
2019 {6, 243, 2, 7 },
2020 {7, 244, 2, 2 },
2021 {8, 244, 2, 7 },
2022 {9, 245, 2, 2 },
2023 {10, 245, 2, 7 },
2024 {11, 246, 2, 2 },
2025 {12, 246, 2, 7 },
2026 {13, 247, 2, 2 },
2027 {14, 248, 2, 4 },
2028};
2029
2030int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2031{
4da2933f
BZ		 2032 struct hw_mode_spec *spec = &rt2x00dev->spec;
2033 struct channel_info *info;
2034 char *tx_power1;
2035 char *tx_power2;
2036 unsigned int i;
2037 u16 eeprom;
2038
93b6bd26
GW		 2039 /*
2040 * Disable powersaving as default on PCI devices.
2041 */
2042 if (rt2x00_intf_is_pci(rt2x00dev))
2043 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2044
4da2933f
BZ		 2045 /*
2046 * Initialize all hw fields.
2047 */
2048 rt2x00dev->hw->flags =
2049 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2050 IEEE80211_HW_SIGNAL_DBM |
2051 IEEE80211_HW_SUPPORTS_PS |
2052 IEEE80211_HW_PS_NULLFUNC_STACK;
2053
4da2933f
BZ		 2054 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2055 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2056 rt2x00_eeprom_addr(rt2x00dev,
2057 EEPROM_MAC_ADDR_0));
2058
2059 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2060
2061 /*
2062 * Initialize hw_mode information.
2063 */
2064 spec->supported_bands = SUPPORT_BAND_2GHZ;
2065 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2066
5122d898
GW		 2067 if (rt2x00_rf(rt2x00dev, RF2820) ||
2068 rt2x00_rf(rt2x00dev, RF2720) ||
6c0fe265 2069 rt2x00_rf(rt2x00dev, RF3052)) {
4da2933f
BZ		 2070 spec->num_channels = 14;
2071 spec->channels = rf_vals;
5122d898 2072 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2073 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2074 spec->num_channels = ARRAY_SIZE(rf_vals);
2075 spec->channels = rf_vals;
5122d898
GW		 2076 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2077 rt2x00_rf(rt2x00dev, RF2020) ||
2078 rt2x00_rf(rt2x00dev, RF3021) ||
2079 rt2x00_rf(rt2x00dev, RF3022)) {
cce5fc45
GW		 2080 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2081 spec->channels = rf_vals_302x;
4da2933f
BZ		 2082 }
2083
2084 /*
2085 * Initialize HT information.
2086 */
5122d898 2087 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2088 spec->ht.ht_supported = true;
2089 else
2090 spec->ht.ht_supported = false;
2091
4da2933f
BZ		 2092 spec->ht.cap =
2093 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2094 IEEE80211_HT_CAP_GRN_FLD |
2095 IEEE80211_HT_CAP_SGI_20 |
2096 IEEE80211_HT_CAP_SGI_40 |
2097 IEEE80211_HT_CAP_TX_STBC |
9a418af5 2098 IEEE80211_HT_CAP_RX_STBC;
4da2933f
BZ		 2099 spec->ht.ampdu_factor = 3;
2100 spec->ht.ampdu_density = 4;
2101 spec->ht.mcs.tx_params =
2102 IEEE80211_HT_MCS_TX_DEFINED |
2103 IEEE80211_HT_MCS_TX_RX_DIFF |
2104 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2105 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2106
2107 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2108 case 3:
2109 spec->ht.mcs.rx_mask[2] = 0xff;
2110 case 2:
2111 spec->ht.mcs.rx_mask[1] = 0xff;
2112 case 1:
2113 spec->ht.mcs.rx_mask[0] = 0xff;
2114 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2115 break;
2116 }
2117
2118 /*
2119 * Create channel information array
2120 */
2121 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2122 if (!info)
2123 return -ENOMEM;
2124
2125 spec->channels_info = info;
2126
2127 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2128 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2129
2130 for (i = 0; i < 14; i++) {
2131 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2132 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2133 }
2134
2135 if (spec->num_channels > 14) {
2136 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2137 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2138
2139 for (i = 14; i < spec->num_channels; i++) {
2140 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2141 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2142 }
2143 }
2144
2145 return 0;
2146}
2147EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2148
2ce33995
BZ		 2149/*
2150 * IEEE80211 stack callback functions.
2151 */
2152static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2153 u32 *iv32, u16 *iv16)
2154{
2155 struct rt2x00_dev *rt2x00dev = hw->priv;
2156 struct mac_iveiv_entry iveiv_entry;
2157 u32 offset;
2158
2159 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2160 rt2800_register_multiread(rt2x00dev, offset,
2161 &iveiv_entry, sizeof(iveiv_entry));
2162
855da5e0
JL		 2163 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2164 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2165}
2166
2167static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2168{
2169 struct rt2x00_dev *rt2x00dev = hw->priv;
2170 u32 reg;
2171 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2172
2173 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2174 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2175 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2176
2177 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2178 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2179 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2180
2181 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2182 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2183 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2184
2185 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2186 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2187 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2188
2189 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2190 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2191 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2192
2193 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2194 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2195 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2196
2197 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2198 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2199 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2200
2201 return 0;
2202}
2203
2204static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2205 const struct ieee80211_tx_queue_params *params)
2206{
2207 struct rt2x00_dev *rt2x00dev = hw->priv;
2208 struct data_queue *queue;
2209 struct rt2x00_field32 field;
2210 int retval;
2211 u32 reg;
2212 u32 offset;
2213
2214 /*
2215 * First pass the configuration through rt2x00lib, that will
2216 * update the queue settings and validate the input. After that
2217 * we are free to update the registers based on the value
2218 * in the queue parameter.
2219 */
2220 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2221 if (retval)
2222 return retval;
2223
2224 /*
2225 * We only need to perform additional register initialization
2226 * for WMM queues/
2227 */
2228 if (queue_idx >= 4)
2229 return 0;
2230
2231 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2232
2233 /* Update WMM TXOP register */
2234 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2235 field.bit_offset = (queue_idx & 1) * 16;
2236 field.bit_mask = 0xffff << field.bit_offset;
2237
2238 rt2800_register_read(rt2x00dev, offset, &reg);
2239 rt2x00_set_field32(&reg, field, queue->txop);
2240 rt2800_register_write(rt2x00dev, offset, reg);
2241
2242 /* Update WMM registers */
2243 field.bit_offset = queue_idx * 4;
2244 field.bit_mask = 0xf << field.bit_offset;
2245
2246 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2247 rt2x00_set_field32(&reg, field, queue->aifs);
2248 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2249
2250 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2251 rt2x00_set_field32(&reg, field, queue->cw_min);
2252 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2253
2254 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2255 rt2x00_set_field32(&reg, field, queue->cw_max);
2256 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2257
2258 /* Update EDCA registers */
2259 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2260
2261 rt2800_register_read(rt2x00dev, offset, &reg);
2262 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2263 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2264 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2265 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2266 rt2800_register_write(rt2x00dev, offset, reg);
2267
2268 return 0;
2269}
2270
2271static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2272{
2273 struct rt2x00_dev *rt2x00dev = hw->priv;
2274 u64 tsf;
2275 u32 reg;
2276
2277 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2278 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2279 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2280 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2281
2282 return tsf;
2283}
2284
2285const struct ieee80211_ops rt2800_mac80211_ops = {
2286 .tx = rt2x00mac_tx,
2287 .start = rt2x00mac_start,
2288 .stop = rt2x00mac_stop,
2289 .add_interface = rt2x00mac_add_interface,
2290 .remove_interface = rt2x00mac_remove_interface,
2291 .config = rt2x00mac_config,
2292 .configure_filter = rt2x00mac_configure_filter,
2293 .set_tim = rt2x00mac_set_tim,
2294 .set_key = rt2x00mac_set_key,
2295 .get_stats = rt2x00mac_get_stats,
2296 .get_tkip_seq = rt2800_get_tkip_seq,
2297 .set_rts_threshold = rt2800_set_rts_threshold,
2298 .bss_info_changed = rt2x00mac_bss_info_changed,
2299 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2300 .get_tsf = rt2800_get_tsf,
2301 .rfkill_poll = rt2x00mac_rfkill_poll,
2302};
2303EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
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