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rt2x00: Don't overwrite beacon buffers in pairwise key setup
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
b9eca242
ID		 387 /*
388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
390 */
391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
392
f31c9a8c
ID		 393 /*
394 * Wait for stable hardware.
395 */
5ffddc49 396 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 397 return -EBUSY;
f31c9a8c
ID		 398
399 if (rt2x00_is_pci(rt2x00dev))
400 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
401
402 /*
403 * Disable DMA, will be reenabled later when enabling
404 * the radio.
405 */
406 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
408 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Initialize firmware.
436 */
437 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
438 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
439 msleep(1);
440
441 return 0;
442}
443EXPORT_SYMBOL_GPL(rt2800_load_firmware);
444
0c5879bc
ID		 445void rt2800_write_tx_data(struct queue_entry *entry,
446 struct txentry_desc *txdesc)
59679b91 447{
0c5879bc 448 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 449 u32 word;
450
451 /*
452 * Initialize TX Info descriptor
453 */
454 rt2x00_desc_read(txwi, 0, &word);
455 rt2x00_set_field32(&word, TXWI_W0_FRAG,
456 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 457 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
458 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 459 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
460 rt2x00_set_field32(&word, TXWI_W0_TS,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
463 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
464 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
465 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
466 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
467 rt2x00_set_field32(&word, TXWI_W0_BW,
468 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
469 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
470 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
471 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
472 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
473 rt2x00_desc_write(txwi, 0, word);
474
475 rt2x00_desc_read(txwi, 1, &word);
476 rt2x00_set_field32(&word, TXWI_W1_ACK,
477 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
478 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
479 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
481 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
482 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
483 txdesc->key_idx : 0xff);
484 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
485 txdesc->length);
a908a743 486 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
59679b91
GW		 487 rt2x00_desc_write(txwi, 1, word);
488
489 /*
490 * Always write 0 to IV/EIV fields, hardware will insert the IV
491 * from the IVEIV register when TXD_W3_WIV is set to 0.
492 * When TXD_W3_WIV is set to 1 it will use the IV data
493 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
494 * crypto entry in the registers should be used to encrypt the frame.
495 */
496 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
497 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
498}
0c5879bc 499EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 500
74861922 501static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 502{
74861922
ID		 503 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
504 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
505 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
506 u16 eeprom;
507 u8 offset0;
508 u8 offset1;
509 u8 offset2;
510
e5ef5bad 511 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
513 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
514 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
515 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
516 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
517 } else {
518 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
519 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
520 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
521 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
522 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
523 }
524
525 /*
526 * Convert the value from the descriptor into the RSSI value
527 * If the value in the descriptor is 0, it is considered invalid
528 * and the default (extremely low) rssi value is assumed
529 */
530 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
531 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
532 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
533
534 /*
535 * mac80211 only accepts a single RSSI value. Calculating the
536 * average doesn't deliver a fair answer either since -60:-60 would
537 * be considered equally good as -50:-70 while the second is the one
538 * which gives less energy...
539 */
540 rssi0 = max(rssi0, rssi1);
541 return max(rssi0, rssi2);
542}
543
544void rt2800_process_rxwi(struct queue_entry *entry,
545 struct rxdone_entry_desc *rxdesc)
546{
547 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 548 u32 word;
549
550 rt2x00_desc_read(rxwi, 0, &word);
551
552 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
553 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
554
555 rt2x00_desc_read(rxwi, 1, &word);
556
557 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
558 rxdesc->flags |= RX_FLAG_SHORT_GI;
559
560 if (rt2x00_get_field32(word, RXWI_W1_BW))
561 rxdesc->flags |= RX_FLAG_40MHZ;
562
563 /*
564 * Detect RX rate, always use MCS as signal type.
565 */
566 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
567 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
568 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
569
570 /*
571 * Mask of 0x8 bit to remove the short preamble flag.
572 */
573 if (rxdesc->rate_mode == RATE_MODE_CCK)
574 rxdesc->signal &= ~0x8;
575
576 rt2x00_desc_read(rxwi, 2, &word);
577
74861922
ID		 578 /*
579 * Convert descriptor AGC value to RSSI value.
580 */
581 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 582
583 /*
584 * Remove RXWI descriptor from start of buffer.
585 */
74861922 586 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 587}
588EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
589
3613884d
ID		 590static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
591{
592 __le32 *txwi;
593 u32 word;
594 int wcid, ack, pid;
595 int tx_wcid, tx_ack, tx_pid;
596
597 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
598 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
599 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
600
601 /*
602 * This frames has returned with an IO error,
603 * so the status report is not intended for this
604 * frame.
605 */
606 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
607 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
608 return false;
609 }
610
611 /*
612 * Validate if this TX status report is intended for
613 * this entry by comparing the WCID/ACK/PID fields.
614 */
615 txwi = rt2800_drv_get_txwi(entry);
616
617 rt2x00_desc_read(txwi, 1, &word);
618 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
619 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
620 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
621
622 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
623 WARNING(entry->queue->rt2x00dev,
624 "TX status report missed for queue %d entry %d\n",
625 entry->queue->qid, entry->entry_idx);
626 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
627 return false;
628 }
629
630 return true;
631}
632
96481b20
ID		 633void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
634{
635 struct data_queue *queue;
636 struct queue_entry *entry;
637 __le32 *txwi;
638 struct txdone_entry_desc txdesc;
639 u32 word;
640 u32 reg;
96481b20 641 u16 mcs, real_mcs;
3613884d 642 u8 pid;
96481b20
ID		 643 int i;
644
645 /*
646 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
647 * at most X times and also stop processing once the TX_STA_FIFO_VALID
648 * flag is not set anymore.
649 *
650 * The legacy drivers use X=TX_RING_SIZE but state in a comment
651 * that the TX_STA_FIFO stack has a size of 16. We stick to our
652 * tx ring size for now.
653 */
654 for (i = 0; i < TX_ENTRIES; i++) {
655 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
656 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
657 break;
658
96481b20
ID		 659 /*
660 * Skip this entry when it contains an invalid
661 * queue identication number.
662 */
3613884d
ID		 663 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
664 if (pid >= QID_RX)
96481b20
ID		 665 continue;
666
3613884d 667 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 668 if (unlikely(!queue))
669 continue;
670
671 /*
672 * Inside each queue, we process each entry in a chronological
673 * order. We first check that the queue is not empty.
674 */
675 entry = NULL;
3613884d 676 txwi = NULL;
96481b20
ID		 677 while (!rt2x00queue_empty(queue)) {
678 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 679 if (rt2800_txdone_entry_check(entry, reg))
96481b20 680 break;
96481b20
ID		 681 }
682
683 if (!entry || rt2x00queue_empty(queue))
684 break;
685
96481b20
ID		 686
687 /*
688 * Obtain the status about this packet.
689 */
690 txdesc.flags = 0;
3613884d 691 txwi = rt2800_drv_get_txwi(entry);
96481b20
ID		 692 rt2x00_desc_read(txwi, 0, &word);
693 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
96481b20
ID		 694 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
695
696 /*
697 * Ralink has a retry mechanism using a global fallback
698 * table. We setup this fallback table to try the immediate
699 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
700 * always contains the MCS used for the last transmission, be
701 * it successful or not.
702 */
703 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
704 /*
705 * Transmission succeeded. The number of retries is
706 * mcs - real_mcs
707 */
708 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
709 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
710 } else {
711 /*
712 * Transmission failed. The number of retries is
713 * always 7 in this case (for a total number of 8
714 * frames sent).
715 */
716 __set_bit(TXDONE_FAILURE, &txdesc.flags);
717 txdesc.retry = rt2x00dev->long_retry;
718 }
719
720 /*
721 * the frame was retried at least once
722 * -> hw used fallback rates
723 */
724 if (txdesc.retry)
725 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
726
727 rt2x00lib_txdone(entry, &txdesc);
728 }
729}
730EXPORT_SYMBOL_GPL(rt2800_txdone);
731
f0194b2d
GW		 732void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
733{
734 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
735 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
736 unsigned int beacon_base;
737 u32 reg;
738
739 /*
740 * Disable beaconing while we are reloading the beacon data,
741 * otherwise we might be sending out invalid data.
742 */
743 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
744 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
745 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
746
747 /*
748 * Add space for the TXWI in front of the skb.
749 */
750 skb_push(entry->skb, TXWI_DESC_SIZE);
751 memset(entry->skb, 0, TXWI_DESC_SIZE);
752
753 /*
754 * Register descriptor details in skb frame descriptor.
755 */
756 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
757 skbdesc->desc = entry->skb->data;
758 skbdesc->desc_len = TXWI_DESC_SIZE;
759
760 /*
761 * Add the TXWI for the beacon to the skb.
762 */
0c5879bc 763 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 764
765 /*
766 * Dump beacon to userspace through debugfs.
767 */
768 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
769
770 /*
771 * Write entire beacon with TXWI to register.
772 */
773 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
774 rt2800_register_multiwrite(rt2x00dev, beacon_base,
775 entry->skb->data, entry->skb->len);
776
777 /*
778 * Enable beaconing again.
779 */
780 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
781 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
782 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
783 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
784
785 /*
786 * Clean up beacon skb.
787 */
788 dev_kfree_skb_any(entry->skb);
789 entry->skb = NULL;
790}
50e888ea 791EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 792
fdb87251
HS		 793static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
794 unsigned int beacon_base)
795{
796 int i;
797
798 /*
799 * For the Beacon base registers we only need to clear
800 * the whole TXWI which (when set to 0) will invalidate
801 * the entire beacon.
802 */
803 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
804 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
805}
806
f4450616
BZ		 807#ifdef CONFIG_RT2X00_LIB_DEBUGFS
808const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
810 .csr = {
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
817 },
818 .eeprom = {
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
824 },
825 .bbp = {
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
831 },
832 .rf = {
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
838 },
839};
840EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
841#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
842
843int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
844{
845 u32 reg;
846
847 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
848 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
849}
850EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
851
852#ifdef CONFIG_RT2X00_LIB_LEDS
853static void rt2800_brightness_set(struct led_classdev *led_cdev,
854 enum led_brightness brightness)
855{
856 struct rt2x00_led *led =
857 container_of(led_cdev, struct rt2x00_led, led_dev);
858 unsigned int enabled = brightness != LED_OFF;
859 unsigned int bg_mode =
860 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
861 unsigned int polarity =
862 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
863 EEPROM_FREQ_LED_POLARITY);
864 unsigned int ledmode =
865 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
866 EEPROM_FREQ_LED_MODE);
867
868 if (led->type == LED_TYPE_RADIO) {
869 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
870 enabled ? 0x20 : 0);
871 } else if (led->type == LED_TYPE_ASSOC) {
872 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
873 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
874 } else if (led->type == LED_TYPE_QUALITY) {
875 /*
876 * The brightness is divided into 6 levels (0 - 5),
877 * The specs tell us the following levels:
878 * 0, 1 ,3, 7, 15, 31
879 * to determine the level in a simple way we can simply
880 * work with bitshifting:
881 * (1 << level) - 1
882 */
883 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
884 (1 << brightness / (LED_FULL / 6)) - 1,
885 polarity);
886 }
887}
888
889static int rt2800_blink_set(struct led_classdev *led_cdev,
890 unsigned long *delay_on, unsigned long *delay_off)
891{
892 struct rt2x00_led *led =
893 container_of(led_cdev, struct rt2x00_led, led_dev);
894 u32 reg;
895
896 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
897 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
898 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 899 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
900
901 return 0;
902}
903
b3579d6a 904static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 905 struct rt2x00_led *led, enum led_type type)
906{
907 led->rt2x00dev = rt2x00dev;
908 led->type = type;
909 led->led_dev.brightness_set = rt2800_brightness_set;
910 led->led_dev.blink_set = rt2800_blink_set;
911 led->flags = LED_INITIALIZED;
912}
f4450616
BZ		 913#endif /* CONFIG_RT2X00_LIB_LEDS */
914
915/*
916 * Configuration handlers.
917 */
918static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
919 struct rt2x00lib_crypto *crypto,
920 struct ieee80211_key_conf *key)
921{
922 struct mac_wcid_entry wcid_entry;
923 struct mac_iveiv_entry iveiv_entry;
924 u32 offset;
925 u32 reg;
926
927 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
928
e4a0ab34
ID		 929 if (crypto->cmd == SET_KEY) {
930 rt2800_register_read(rt2x00dev, offset, &reg);
931 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
932 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
933 /*
934 * Both the cipher as the BSS Idx numbers are split in a main
935 * value of 3 bits, and a extended field for adding one additional
936 * bit to the value.
937 */
938 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
939 (crypto->cipher & 0x7));
940 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
941 (crypto->cipher & 0x8) >> 3);
942 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
943 (crypto->bssidx & 0x7));
944 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
945 (crypto->bssidx & 0x8) >> 3);
946 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
947 rt2800_register_write(rt2x00dev, offset, reg);
948 } else {
949 rt2800_register_write(rt2x00dev, offset, 0);
950 }
f4450616
BZ		 951
952 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
953
954 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
955 if ((crypto->cipher == CIPHER_TKIP) ||
956 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
957 (crypto->cipher == CIPHER_AES))
958 iveiv_entry.iv[3] |= 0x20;
959 iveiv_entry.iv[3] |= key->keyidx << 6;
960 rt2800_register_multiwrite(rt2x00dev, offset,
961 &iveiv_entry, sizeof(iveiv_entry));
962
963 offset = MAC_WCID_ENTRY(key->hw_key_idx);
964
965 memset(&wcid_entry, 0, sizeof(wcid_entry));
966 if (crypto->cmd == SET_KEY)
967 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
968 rt2800_register_multiwrite(rt2x00dev, offset,
969 &wcid_entry, sizeof(wcid_entry));
970}
971
972int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
973 struct rt2x00lib_crypto *crypto,
974 struct ieee80211_key_conf *key)
975{
976 struct hw_key_entry key_entry;
977 struct rt2x00_field32 field;
978 u32 offset;
979 u32 reg;
980
981 if (crypto->cmd == SET_KEY) {
982 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
983
984 memcpy(key_entry.key, crypto->key,
985 sizeof(key_entry.key));
986 memcpy(key_entry.tx_mic, crypto->tx_mic,
987 sizeof(key_entry.tx_mic));
988 memcpy(key_entry.rx_mic, crypto->rx_mic,
989 sizeof(key_entry.rx_mic));
990
991 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
992 rt2800_register_multiwrite(rt2x00dev, offset,
993 &key_entry, sizeof(key_entry));
994 }
995
996 /*
997 * The cipher types are stored over multiple registers
998 * starting with SHARED_KEY_MODE_BASE each word will have
999 * 32 bits and contains the cipher types for 2 bssidx each.
1000 * Using the correct defines correctly will cause overhead,
1001 * so just calculate the correct offset.
1002 */
1003 field.bit_offset = 4 * (key->hw_key_idx % 8);
1004 field.bit_mask = 0x7 << field.bit_offset;
1005
1006 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1007
1008 rt2800_register_read(rt2x00dev, offset, &reg);
1009 rt2x00_set_field32(&reg, field,
1010 (crypto->cmd == SET_KEY) * crypto->cipher);
1011 rt2800_register_write(rt2x00dev, offset, reg);
1012
1013 /*
1014 * Update WCID information
1015 */
1016 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1017
1018 return 0;
1019}
1020EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1021
1022int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1023 struct rt2x00lib_crypto *crypto,
1024 struct ieee80211_key_conf *key)
1025{
1026 struct hw_key_entry key_entry;
1027 u32 offset;
1028
1029 if (crypto->cmd == SET_KEY) {
1030 /*
1031 * 1 pairwise key is possible per AID, this means that the AID
1032 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1033 * last possible shared key entry.
2a0cfeb8
HS		 1034 *
1035 * Since parts of the pairwise key table might be shared with
1036 * the beacon frame buffers 6 & 7 we should only write into the
1037 * first 222 entries.
f4450616 1038 */
2a0cfeb8 1039 if (crypto->aid > (222 - 32))
f4450616
BZ		 1040 return -ENOSPC;
1041
1042 key->hw_key_idx = 32 + crypto->aid;
1043
1044 memcpy(key_entry.key, crypto->key,
1045 sizeof(key_entry.key));
1046 memcpy(key_entry.tx_mic, crypto->tx_mic,
1047 sizeof(key_entry.tx_mic));
1048 memcpy(key_entry.rx_mic, crypto->rx_mic,
1049 sizeof(key_entry.rx_mic));
1050
1051 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1052 rt2800_register_multiwrite(rt2x00dev, offset,
1053 &key_entry, sizeof(key_entry));
1054 }
1055
1056 /*
1057 * Update WCID information
1058 */
1059 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1064
1065void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1066 const unsigned int filter_flags)
1067{
1068 u32 reg;
1069
1070 /*
1071 * Start configuration steps.
1072 * Note that the version error will always be dropped
1073 * and broadcast frames will always be accepted since
1074 * there is no filter for it at this time.
1075 */
1076 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1077 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1078 !(filter_flags & FIF_FCSFAIL));
1079 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1080 !(filter_flags & FIF_PLCPFAIL));
1081 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1082 !(filter_flags & FIF_PROMISC_IN_BSS));
1083 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1084 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1085 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1086 !(filter_flags & FIF_ALLMULTI));
1087 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1088 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1089 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1090 !(filter_flags & FIF_CONTROL));
1091 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1092 !(filter_flags & FIF_CONTROL));
1093 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1094 !(filter_flags & FIF_CONTROL));
1095 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1096 !(filter_flags & FIF_CONTROL));
1097 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1098 !(filter_flags & FIF_CONTROL));
1099 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1100 !(filter_flags & FIF_PSPOLL));
1101 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1102 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1103 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1104 !(filter_flags & FIF_CONTROL));
1105 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1106}
1107EXPORT_SYMBOL_GPL(rt2800_config_filter);
1108
1109void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1110 struct rt2x00intf_conf *conf, const unsigned int flags)
1111{
f4450616
BZ		 1112 u32 reg;
1113
1114 if (flags & CONFIG_UPDATE_TYPE) {
1115 /*
1116 * Clear current synchronisation setup.
f4450616 1117 */
fdb87251
HS		 1118 rt2800_clear_beacon(rt2x00dev,
1119 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1120 /*
1121 * Enable synchronisation.
1122 */
1123 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1124 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1125 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1126 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1127 (conf->sync == TSF_SYNC_ADHOC ||
1128 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1129 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1130
1131 /*
1132 * Enable pre tbtt interrupt for beaconing modes
1133 */
1134 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1135 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1136 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1137 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1138
f4450616
BZ		 1139 }
1140
1141 if (flags & CONFIG_UPDATE_MAC) {
c600c826
ID		 1142 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1143 reg = le32_to_cpu(conf->mac[1]);
1144 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1145 conf->mac[1] = cpu_to_le32(reg);
1146 }
f4450616
BZ		 1147
1148 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1149 conf->mac, sizeof(conf->mac));
1150 }
1151
1152 if (flags & CONFIG_UPDATE_BSSID) {
c600c826
ID		 1153 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1154 reg = le32_to_cpu(conf->bssid[1]);
1155 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1156 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1157 conf->bssid[1] = cpu_to_le32(reg);
1158 }
f4450616
BZ		 1159
1160 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1161 conf->bssid, sizeof(conf->bssid));
1162 }
1163}
1164EXPORT_SYMBOL_GPL(rt2800_config_intf);
1165
02044643
HS		 1166void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1167 u32 changed)
f4450616
BZ		 1168{
1169 u32 reg;
1170
02044643
HS		 1171 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1172 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1173 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1174 !!erp->short_preamble);
1175 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1176 !!erp->short_preamble);
1177 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1178 }
f4450616 1179
02044643
HS		 1180 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1181 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1182 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1183 erp->cts_protection ? 2 : 0);
1184 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1185 }
f4450616 1186
02044643
HS		 1187 if (changed & BSS_CHANGED_BASIC_RATES) {
1188 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1189 erp->basic_rates);
1190 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1191 }
f4450616 1192
02044643
HS		 1193 if (changed & BSS_CHANGED_ERP_SLOT) {
1194 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1195 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1196 erp->slot_time);
1197 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1198
02044643
HS		 1199 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1200 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1201 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1202 }
f4450616 1203
02044643
HS		 1204 if (changed & BSS_CHANGED_BEACON_INT) {
1205 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1206 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1207 erp->beacon_int * 16);
1208 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1209 }
f4450616
BZ		 1210}
1211EXPORT_SYMBOL_GPL(rt2800_config_erp);
1212
1213void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1214{
1215 u8 r1;
1216 u8 r3;
1217
1218 rt2800_bbp_read(rt2x00dev, 1, &r1);
1219 rt2800_bbp_read(rt2x00dev, 3, &r3);
1220
1221 /*
1222 * Configure the TX antenna.
1223 */
1224 switch ((int)ant->tx) {
1225 case 1:
1226 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1227 break;
1228 case 2:
1229 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1230 break;
1231 case 3:
e22557f2 1232 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1233 break;
1234 }
1235
1236 /*
1237 * Configure the RX antenna.
1238 */
1239 switch ((int)ant->rx) {
1240 case 1:
1241 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1242 break;
1243 case 2:
1244 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1245 break;
1246 case 3:
1247 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1248 break;
1249 }
1250
1251 rt2800_bbp_write(rt2x00dev, 3, r3);
1252 rt2800_bbp_write(rt2x00dev, 1, r1);
1253}
1254EXPORT_SYMBOL_GPL(rt2800_config_ant);
1255
1256static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1257 struct rt2x00lib_conf *libconf)
1258{
1259 u16 eeprom;
1260 short lna_gain;
1261
1262 if (libconf->rf.channel <= 14) {
1263 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1264 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1265 } else if (libconf->rf.channel <= 64) {
1266 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1267 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1268 } else if (libconf->rf.channel <= 128) {
1269 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1270 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1271 } else {
1272 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1273 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1274 }
1275
1276 rt2x00dev->lna_gain = lna_gain;
1277}
1278
06855ef4
GW		 1279static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1280 struct ieee80211_conf *conf,
1281 struct rf_channel *rf,
1282 struct channel_info *info)
f4450616
BZ		 1283{
1284 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1285
1286 if (rt2x00dev->default_ant.tx == 1)
1287 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1288
1289 if (rt2x00dev->default_ant.rx == 1) {
1290 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1291 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1292 } else if (rt2x00dev->default_ant.rx == 2)
1293 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1294
1295 if (rf->channel > 14) {
1296 /*
1297 * When TX power is below 0, we should increase it by 7 to
1298 * make it a positive value (Minumum value is -7).
1299 * However this means that values between 0 and 7 have
1300 * double meaning, and we should set a 7DBm boost flag.
1301 */
1302 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1303 (info->default_power1 >= 0));
f4450616 1304
8d1331b3
ID		 1305 if (info->default_power1 < 0)
1306 info->default_power1 += 7;
f4450616 1307
8d1331b3 1308 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1309
1310 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1311 (info->default_power2 >= 0));
f4450616 1312
8d1331b3
ID		 1313 if (info->default_power2 < 0)
1314 info->default_power2 += 7;
f4450616 1315
8d1331b3 1316 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1317 } else {
8d1331b3
ID		 1318 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1319 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1320 }
1321
1322 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1323
1324 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1325 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1326 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1327 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1328
1329 udelay(200);
1330
1331 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1332 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1333 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1334 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1335
1336 udelay(200);
1337
1338 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1339 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1340 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1341 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1342}
1343
06855ef4
GW		 1344static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1345 struct ieee80211_conf *conf,
1346 struct rf_channel *rf,
1347 struct channel_info *info)
f4450616
BZ		 1348{
1349 u8 rfcsr;
1350
1351 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1352 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1353
1354 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1355 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1356 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1357
1358 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1359 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1360 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1361
5a673964 1362 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1363 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1364 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1365
f4450616
BZ		 1366 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1367 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1368 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1369
1370 rt2800_rfcsr_write(rt2x00dev, 24,
1371 rt2x00dev->calibration[conf_is_ht40(conf)]);
1372
71976907 1373 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1374 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1375 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1376}
1377
1378static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1379 struct ieee80211_conf *conf,
1380 struct rf_channel *rf,
1381 struct channel_info *info)
1382{
1383 u32 reg;
1384 unsigned int tx_pin;
1385 u8 bbp;
1386
46323e11 1387 if (rf->channel <= 14) {
8d1331b3
ID		 1388 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1389 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1390 } else {
8d1331b3
ID		 1391 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1392 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1393 }
1394
06855ef4
GW		 1395 if (rt2x00_rf(rt2x00dev, RF2020) ||
1396 rt2x00_rf(rt2x00dev, RF3020) ||
1397 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1398 rt2x00_rf(rt2x00dev, RF3022) ||
1399 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1400 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1401 else
06855ef4 1402 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1403
1404 /*
1405 * Change BBP settings
1406 */
1407 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1408 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1409 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1410 rt2800_bbp_write(rt2x00dev, 86, 0);
1411
1412 if (rf->channel <= 14) {
1413 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1414 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1415 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1416 } else {
1417 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1418 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1419 }
1420 } else {
1421 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1422
1423 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1424 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1425 else
1426 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1427 }
1428
1429 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1430 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1431 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1432 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1433 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1434
1435 tx_pin = 0;
1436
1437 /* Turn on unused PA or LNA when not using 1T or 1R */
1438 if (rt2x00dev->default_ant.tx != 1) {
1439 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1440 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1441 }
1442
1443 /* Turn on unused PA or LNA when not using 1T or 1R */
1444 if (rt2x00dev->default_ant.rx != 1) {
1445 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1446 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1447 }
1448
1449 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1450 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1451 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1452 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1453 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1454 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1455
1456 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1457
1458 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1459 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1460 rt2800_bbp_write(rt2x00dev, 4, bbp);
1461
1462 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1463 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1464 rt2800_bbp_write(rt2x00dev, 3, bbp);
1465
8d0c9b65 1466 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1467 if (conf_is_ht40(conf)) {
1468 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1469 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1470 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1471 } else {
1472 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1473 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1474 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1475 }
1476 }
1477
1478 msleep(1);
1479}
1480
1481static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1482 const int max_txpower)
f4450616 1483{
5e846004
HS		 1484 u8 txpower;
1485 u8 max_value = (u8)max_txpower;
1486 u16 eeprom;
1487 int i;
f4450616 1488 u32 reg;
f4450616 1489 u8 r1;
5e846004 1490 u32 offset;
f4450616 1491
5e846004
HS		 1492 /*
1493 * set to normal tx power mode: +/- 0dBm
1494 */
f4450616 1495 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1496 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1497 rt2800_bbp_write(rt2x00dev, 1, r1);
1498
5e846004
HS		 1499 /*
1500 * The eeprom contains the tx power values for each rate. These
1501 * values map to 100% tx power. Each 16bit word contains four tx
1502 * power values and the order is the same as used in the TX_PWR_CFG
1503 * registers.
1504 */
1505 offset = TX_PWR_CFG_0;
1506
1507 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1508 /* just to be safe */
1509 if (offset > TX_PWR_CFG_4)
1510 break;
1511
1512 rt2800_register_read(rt2x00dev, offset, &reg);
1513
1514 /* read the next four txpower values */
1515 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1516 &eeprom);
1517
1518 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1519 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1520 * TX_PWR_CFG_4: unknown */
1521 txpower = rt2x00_get_field16(eeprom,
1522 EEPROM_TXPOWER_BYRATE_RATE0);
1523 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1524 min(txpower, max_value));
1525
1526 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1527 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1528 * TX_PWR_CFG_4: unknown */
1529 txpower = rt2x00_get_field16(eeprom,
1530 EEPROM_TXPOWER_BYRATE_RATE1);
1531 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1532 min(txpower, max_value));
1533
1534 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1535 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1536 * TX_PWR_CFG_4: unknown */
1537 txpower = rt2x00_get_field16(eeprom,
1538 EEPROM_TXPOWER_BYRATE_RATE2);
1539 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1540 min(txpower, max_value));
1541
1542 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1543 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1544 * TX_PWR_CFG_4: unknown */
1545 txpower = rt2x00_get_field16(eeprom,
1546 EEPROM_TXPOWER_BYRATE_RATE3);
1547 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1548 min(txpower, max_value));
1549
1550 /* read the next four txpower values */
1551 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1552 &eeprom);
1553
1554 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1555 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1556 * TX_PWR_CFG_4: unknown */
1557 txpower = rt2x00_get_field16(eeprom,
1558 EEPROM_TXPOWER_BYRATE_RATE0);
1559 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1560 min(txpower, max_value));
1561
1562 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1563 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1564 * TX_PWR_CFG_4: unknown */
1565 txpower = rt2x00_get_field16(eeprom,
1566 EEPROM_TXPOWER_BYRATE_RATE1);
1567 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1568 min(txpower, max_value));
1569
1570 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1571 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1572 * TX_PWR_CFG_4: unknown */
1573 txpower = rt2x00_get_field16(eeprom,
1574 EEPROM_TXPOWER_BYRATE_RATE2);
1575 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1576 min(txpower, max_value));
1577
1578 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1579 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1580 * TX_PWR_CFG_4: unknown */
1581 txpower = rt2x00_get_field16(eeprom,
1582 EEPROM_TXPOWER_BYRATE_RATE3);
1583 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1584 min(txpower, max_value));
1585
1586 rt2800_register_write(rt2x00dev, offset, reg);
1587
1588 /* next TX_PWR_CFG register */
1589 offset += 4;
1590 }
f4450616
BZ		 1591}
1592
1593static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1594 struct rt2x00lib_conf *libconf)
1595{
1596 u32 reg;
1597
1598 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1599 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1600 libconf->conf->short_frame_max_tx_count);
1601 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1602 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1603 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1604}
1605
1606static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1607 struct rt2x00lib_conf *libconf)
1608{
1609 enum dev_state state =
1610 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1611 STATE_SLEEP : STATE_AWAKE;
1612 u32 reg;
1613
1614 if (state == STATE_SLEEP) {
1615 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1616
1617 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1618 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1619 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1620 libconf->conf->listen_interval - 1);
1621 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1622 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1623
1624 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1625 } else {
f4450616
BZ		 1626 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1627 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1628 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1629 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1630 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1631
1632 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1633 }
1634}
1635
1636void rt2800_config(struct rt2x00_dev *rt2x00dev,
1637 struct rt2x00lib_conf *libconf,
1638 const unsigned int flags)
1639{
1640 /* Always recalculate LNA gain before changing configuration */
1641 rt2800_config_lna_gain(rt2x00dev, libconf);
1642
1643 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1644 rt2800_config_channel(rt2x00dev, libconf->conf,
1645 &libconf->rf, &libconf->channel);
1646 if (flags & IEEE80211_CONF_CHANGE_POWER)
1647 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1648 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1649 rt2800_config_retry_limit(rt2x00dev, libconf);
1650 if (flags & IEEE80211_CONF_CHANGE_PS)
1651 rt2800_config_ps(rt2x00dev, libconf);
1652}
1653EXPORT_SYMBOL_GPL(rt2800_config);
1654
1655/*
1656 * Link tuning
1657 */
1658void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1659{
1660 u32 reg;
1661
1662 /*
1663 * Update FCS error count from register.
1664 */
1665 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1666 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1667}
1668EXPORT_SYMBOL_GPL(rt2800_link_stats);
1669
1670static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1671{
1672 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1673 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1674 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1675 rt2x00_rt(rt2x00dev, RT3090) ||
1676 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1677 return 0x1c + (2 * rt2x00dev->lna_gain);
1678 else
1679 return 0x2e + rt2x00dev->lna_gain;
1680 }
1681
1682 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1683 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1684 else
1685 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1686}
1687
1688static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1689 struct link_qual *qual, u8 vgc_level)
1690{
1691 if (qual->vgc_level != vgc_level) {
1692 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1693 qual->vgc_level = vgc_level;
1694 qual->vgc_level_reg = vgc_level;
1695 }
1696}
1697
1698void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1699{
1700 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1701}
1702EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1703
1704void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1705 const u32 count)
1706{
8d0c9b65 1707 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1708 return;
1709
1710 /*
1711 * When RSSI is better then -80 increase VGC level with 0x10
1712 */
1713 rt2800_set_vgc(rt2x00dev, qual,
1714 rt2800_get_default_vgc(rt2x00dev) +
1715 ((qual->rssi > -80) * 0x10));
1716}
1717EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1718
1719/*
1720 * Initialization functions.
1721 */
b9a07ae9 1722static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1723{
1724 u32 reg;
d5385bfc 1725 u16 eeprom;
fcf51541 1726 unsigned int i;
e3a896b9 1727 int ret;
fcf51541 1728
a9dce149
GW		 1729 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1730 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1731 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1732 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1733 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1734 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1735 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1736
e3a896b9
GW		 1737 ret = rt2800_drv_init_registers(rt2x00dev);
1738 if (ret)
1739 return ret;
fcf51541
BZ		 1740
1741 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1742 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1743 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1744 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1745 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1746 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1747
1748 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1749 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1750 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1751 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1752 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1753 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1754
1755 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1756 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1757
1758 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1759
1760 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1761 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1762 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1763 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1764 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1765 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1766 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1767 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1768
a9dce149
GW		 1769 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1770
1771 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1772 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1773 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1774 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1775
64522957 1776 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1777 rt2x00_rt(rt2x00dev, RT3090) ||
1778 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1779 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1780 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1781 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1782 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1783 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1784 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1785 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1786 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1787 0x0000002c);
1788 else
1789 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1790 0x0000000f);
1791 } else {
1792 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1793 }
d5385bfc 1794 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1795 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1796
1797 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1798 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1799 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1800 } else {
1801 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1802 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1803 }
c295a81d
HS		 1804 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1805 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1806 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1807 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1808 } else {
1809 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1810 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1811 }
1812
1813 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1814 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1815 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1816 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1817 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1818 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1819 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1820 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1821 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1822 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1823
1824 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1825 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1826 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1827 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1828 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1829
1830 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1831 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1832 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1833 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1834 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1835 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1836 else
1837 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1838 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1839 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1840 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1841
a9dce149
GW		 1842 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1843 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1844 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1845 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1846 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1847 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1848 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1849 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1850 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1851
fcf51541
BZ		 1852 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1853
a9dce149
GW		 1854 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1855 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1856 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1857 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1858 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1859 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1860 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1861 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1862
fcf51541
BZ		 1863 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1864 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1865 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1866 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1867 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1868 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1869 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1870 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1871 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1872
1873 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1874 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1875 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1876 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1877 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1878 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1879 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1880 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1881 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1882 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1883 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1884 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1885
1886 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1887 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1888 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1889 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1890 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1891 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1892 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1893 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1894 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1895 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1896 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1897 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1898
1899 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1900 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1901 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1902 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1903 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1904 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1905 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1906 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1907 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1908 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1909 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1910 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1911
1912 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1913 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1914 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1915 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1916 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1917 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1918 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1919 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1920 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1921 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1922 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1923 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1924 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1925
1926 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1927 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1928 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1929 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1930 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1931 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1932 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1933 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1934 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1935 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1936 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1937 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1938
1939 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1940 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1941 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1942 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1943 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1944 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1945 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1946 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1947 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1948 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1949 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1950 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1951
cea90e55 1952 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1953 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1954
1955 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1956 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1957 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1958 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1959 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1960 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1961 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1962 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1963 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1964 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1965 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1966 }
1967
1968 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1969 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1970
1971 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1972 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1973 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1974 IEEE80211_MAX_RTS_THRESHOLD);
1975 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1976 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1977
1978 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1979
a21c2ab4
HS		 1980 /*
1981 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1982 * time should be set to 16. However, the original Ralink driver uses
1983 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1984 * connection problems with 11g + CTS protection. Hence, use the same
1985 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1986 */
a9dce149 1987 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1988 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1989 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1990 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1991 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1992 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1993 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1994
fcf51541
BZ		 1995 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1996
1997 /*
1998 * ASIC will keep garbage value after boot, clear encryption keys.
1999 */
2000 for (i = 0; i < 4; i++)
2001 rt2800_register_write(rt2x00dev,
2002 SHARED_KEY_MODE_ENTRY(i), 0);
2003
2004 for (i = 0; i < 256; i++) {
2005 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2006 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2007 wcid, sizeof(wcid));
2008
2009 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2010 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2011 }
2012
2013 /*
2014 * Clear all beacons
fcf51541 2015 */
fdb87251
HS		 2016 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2017 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2018 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2019 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2020 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2021 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2022 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2023 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2024
cea90e55 2025 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2026 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2027 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2028 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2029 }
2030
2031 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2032 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2033 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2034 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2035 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2036 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2037 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2038 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2039 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2040 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2041
2042 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2043 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2044 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2045 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2046 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2047 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2048 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2049 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2050 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2051 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2052
2053 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2054 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2055 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2056 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2057 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2058 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2059 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2060 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2061 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2062 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2063
2064 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2065 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2066 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2067 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2068 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2069 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2070
47ee3eb1
HS		 2071 /*
2072 * Do not force the BA window size, we use the TXWI to set it
2073 */
2074 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2075 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2076 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2077 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2078
fcf51541
BZ		 2079 /*
2080 * We must clear the error counters.
2081 * These registers are cleared on read,
2082 * so we may pass a useless variable to store the value.
2083 */
2084 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2085 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2086 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2087 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2088 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2089 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2090
9f926fb5
HS		 2091 /*
2092 * Setup leadtime for pre tbtt interrupt to 6ms
2093 */
2094 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2095 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2096 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2097
fcf51541
BZ		 2098 return 0;
2099}
fcf51541
BZ		 2100
2101static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2102{
2103 unsigned int i;
2104 u32 reg;
2105
2106 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2107 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2108 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2109 return 0;
2110
2111 udelay(REGISTER_BUSY_DELAY);
2112 }
2113
2114 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2115 return -EACCES;
2116}
2117
2118static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2119{
2120 unsigned int i;
2121 u8 value;
2122
2123 /*
2124 * BBP was enabled after firmware was loaded,
2125 * but we need to reactivate it now.
2126 */
2127 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2128 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2129 msleep(1);
2130
2131 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2132 rt2800_bbp_read(rt2x00dev, 0, &value);
2133 if ((value != 0xff) && (value != 0x00))
2134 return 0;
2135 udelay(REGISTER_BUSY_DELAY);
2136 }
2137
2138 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2139 return -EACCES;
2140}
2141
b9a07ae9 2142static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2143{
2144 unsigned int i;
2145 u16 eeprom;
2146 u8 reg_id;
2147 u8 value;
2148
2149 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2150 rt2800_wait_bbp_ready(rt2x00dev)))
2151 return -EACCES;
2152
baff8006
HS		 2153 if (rt2800_is_305x_soc(rt2x00dev))
2154 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2155
fcf51541
BZ		 2156 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2157 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2158
2159 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2160 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2161 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2162 } else {
2163 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2164 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2165 }
2166
fcf51541 2167 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2168
d5385bfc 2169 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2170 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2171 rt2x00_rt(rt2x00dev, RT3090) ||
2172 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2173 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2174 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2175 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2176 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2177 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2178 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2179 } else {
2180 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2181 }
2182
fcf51541
BZ		 2183 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2184 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2185
5ed8f458 2186 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2187 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2188 else
2189 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2190
fcf51541
BZ		 2191 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2192 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2193 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2194
d5385bfc 2195 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2196 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2197 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2198 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2199 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2200 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2201 else
2202 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2203
baff8006
HS		 2204 if (rt2800_is_305x_soc(rt2x00dev))
2205 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2206 else
2207 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2208 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2209
64522957 2210 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2211 rt2x00_rt(rt2x00dev, RT3090) ||
2212 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2213 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2214
d5385bfc
GW		 2215 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2216 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2217 value |= 0x20;
2218 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2219 value &= ~0x02;
fcf51541 2220
d5385bfc 2221 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2222 }
2223
fcf51541
BZ		 2224
2225 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2226 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2227
2228 if (eeprom != 0xffff && eeprom != 0x0000) {
2229 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2230 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2231 rt2800_bbp_write(rt2x00dev, reg_id, value);
2232 }
2233 }
2234
2235 return 0;
2236}
fcf51541
BZ		 2237
2238static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2239 bool bw40, u8 rfcsr24, u8 filter_target)
2240{
2241 unsigned int i;
2242 u8 bbp;
2243 u8 rfcsr;
2244 u8 passband;
2245 u8 stopband;
2246 u8 overtuned = 0;
2247
2248 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2249
2250 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2251 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2252 rt2800_bbp_write(rt2x00dev, 4, bbp);
2253
2254 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2255 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2256 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2257
2258 /*
2259 * Set power & frequency of passband test tone
2260 */
2261 rt2800_bbp_write(rt2x00dev, 24, 0);
2262
2263 for (i = 0; i < 100; i++) {
2264 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2265 msleep(1);
2266
2267 rt2800_bbp_read(rt2x00dev, 55, &passband);
2268 if (passband)
2269 break;
2270 }
2271
2272 /*
2273 * Set power & frequency of stopband test tone
2274 */
2275 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2276
2277 for (i = 0; i < 100; i++) {
2278 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2279 msleep(1);
2280
2281 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2282
2283 if ((passband - stopband) <= filter_target) {
2284 rfcsr24++;
2285 overtuned += ((passband - stopband) == filter_target);
2286 } else
2287 break;
2288
2289 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2290 }
2291
2292 rfcsr24 -= !!overtuned;
2293
2294 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2295 return rfcsr24;
2296}
2297
b9a07ae9 2298static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2299{
2300 u8 rfcsr;
2301 u8 bbp;
8cdd15e0
GW		 2302 u32 reg;
2303 u16 eeprom;
fcf51541 2304
d5385bfc 2305 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2306 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2307 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2308 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2309 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2310 return 0;
2311
fcf51541
BZ		 2312 /*
2313 * Init RF calibration.
2314 */
2315 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2316 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2317 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2318 msleep(1);
2319 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2320 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2321
d5385bfc 2322 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2323 rt2x00_rt(rt2x00dev, RT3071) ||
2324 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2325 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2326 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2327 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2328 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2329 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2330 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2331 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2332 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2333 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2334 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2335 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2336 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2337 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2338 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2339 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2340 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2341 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2342 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2343 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2344 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2345 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2346 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2347 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2348 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2349 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2350 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2351 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2352 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2353 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2354 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2355 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2356 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2357 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2358 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2359 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2360 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2361 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2362 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2363 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2364 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2365 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2366 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2367 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2368 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2369 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2370 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2371 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2372 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2373 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2374 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2375 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2376 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2377 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2378 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2379 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2380 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2381 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2382 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2383 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2384 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2385 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2386 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2387 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2388 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2389 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2390 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2391 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2392 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2393 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2394 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2395 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2396 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2397 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2398 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2399 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2400 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2401 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2402 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2403 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2404 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2405 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2406 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2407 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2408 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2409 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2410 return 0;
8cdd15e0
GW		 2411 }
2412
2413 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2414 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2415 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2416 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2417 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2418 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2419 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2420 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2421 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2422 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2423
2424 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2425
2426 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2427 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2428 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2429 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2430 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2431 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2432 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2433 else
2434 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2435 }
2436 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2437 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2438 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2439 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2440 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2441 }
2442
2443 /*
2444 * Set RX Filter calibration for 20MHz and 40MHz
2445 */
8cdd15e0
GW		 2446 if (rt2x00_rt(rt2x00dev, RT3070)) {
2447 rt2x00dev->calibration[0] =
2448 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2449 rt2x00dev->calibration[1] =
2450 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2451 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2452 rt2x00_rt(rt2x00dev, RT3090) ||
2453 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2454 rt2x00dev->calibration[0] =
2455 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2456 rt2x00dev->calibration[1] =
2457 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2458 }
fcf51541
BZ		 2459
2460 /*
2461 * Set back to initial state
2462 */
2463 rt2800_bbp_write(rt2x00dev, 24, 0);
2464
2465 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2466 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2467 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2468
2469 /*
2470 * set BBP back to BW20
2471 */
2472 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2473 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2474 rt2800_bbp_write(rt2x00dev, 4, bbp);
2475
d5385bfc 2476 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2477 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2478 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2479 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2480 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2481
2482 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2483 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2484 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2485
2486 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2487 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2488 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2489 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2490 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2491 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2492 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2493 }
8cdd15e0
GW		 2494 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2495 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2496 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2497 rt2x00_get_field16(eeprom,
2498 EEPROM_TXMIXER_GAIN_BG_VAL));
2499 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2500
64522957
GW		 2501 if (rt2x00_rt(rt2x00dev, RT3090)) {
2502 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2503
2504 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2505 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2506 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2507 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2508 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2509
2510 rt2800_bbp_write(rt2x00dev, 138, bbp);
2511 }
2512
2513 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2514 rt2x00_rt(rt2x00dev, RT3090) ||
2515 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2516 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2517 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2518 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2519 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2520 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2522 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2523
2524 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2525 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2526 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2527
2528 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2529 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2530 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2531
2532 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2533 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2534 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2535 }
2536
2537 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2538 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2539 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2540 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2541 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2542 else
2543 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2544 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2545 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2546 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2547 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2548 }
2549
fcf51541
BZ		 2550 return 0;
2551}
b9a07ae9
ID		 2552
2553int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2554{
2555 u32 reg;
2556 u16 word;
2557
2558 /*
2559 * Initialize all registers.
2560 */
2561 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2562 rt2800_init_registers(rt2x00dev) ||
2563 rt2800_init_bbp(rt2x00dev) ||
2564 rt2800_init_rfcsr(rt2x00dev)))
2565 return -EIO;
2566
2567 /*
2568 * Send signal to firmware during boot time.
2569 */
2570 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2571
2572 if (rt2x00_is_usb(rt2x00dev) &&
2573 (rt2x00_rt(rt2x00dev, RT3070) ||
2574 rt2x00_rt(rt2x00dev, RT3071) ||
2575 rt2x00_rt(rt2x00dev, RT3572))) {
2576 udelay(200);
2577 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2578 udelay(10);
2579 }
2580
2581 /*
2582 * Enable RX.
2583 */
2584 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2585 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2586 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2587 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2588
2589 udelay(50);
2590
2591 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2592 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2593 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2594 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2595 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2596 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2597
2598 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2599 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2600 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2601 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2602
2603 /*
2604 * Initialize LED control
2605 */
2606 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2607 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2608 word & 0xff, (word >> 8) & 0xff);
2609
2610 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2611 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2612 word & 0xff, (word >> 8) & 0xff);
2613
2614 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2615 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2616 word & 0xff, (word >> 8) & 0xff);
2617
2618 return 0;
2619}
2620EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2621
2622void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2623{
2624 u32 reg;
2625
2626 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2627 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2628 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2629 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2630 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2631 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2632 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2633
2634 /* Wait for DMA, ignore error */
2635 rt2800_wait_wpdma_ready(rt2x00dev);
2636
2637 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2638 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2639 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2640 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2641
2642 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2643 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2644}
2645EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2646
30e84034
BZ		 2647int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2648{
2649 u32 reg;
2650
2651 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2652
2653 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2654}
2655EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2656
2657static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2658{
2659 u32 reg;
2660
31a4cf1f
GW		 2661 mutex_lock(&rt2x00dev->csr_mutex);
2662
2663 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2664 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2665 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2666 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2667 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2668
2669 /* Wait until the EEPROM has been loaded */
2670 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2671
2672 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2673 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2674 (u32 *)&rt2x00dev->eeprom[i]);
2675 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2676 (u32 *)&rt2x00dev->eeprom[i + 2]);
2677 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2678 (u32 *)&rt2x00dev->eeprom[i + 4]);
2679 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2680 (u32 *)&rt2x00dev->eeprom[i + 6]);
2681
2682 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2683}
2684
2685void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2686{
2687 unsigned int i;
2688
2689 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2690 rt2800_efuse_read(rt2x00dev, i);
2691}
2692EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2693
38bd7b8a
BZ		 2694int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2695{
2696 u16 word;
2697 u8 *mac;
2698 u8 default_lna_gain;
2699
2700 /*
2701 * Start validation of the data that has been read.
2702 */
2703 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2704 if (!is_valid_ether_addr(mac)) {
2705 random_ether_addr(mac);
2706 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2707 }
2708
2709 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2710 if (word == 0xffff) {
2711 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2712 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2713 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2714 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2715 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2716 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2717 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2718 /*
2719 * There is a max of 2 RX streams for RT28x0 series
2720 */
2721 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2722 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2723 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2724 }
2725
2726 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2727 if (word == 0xffff) {
2728 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2729 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2730 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2731 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2732 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2733 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2734 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2735 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2736 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2737 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2738 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2739 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2740 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2741 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2742 }
2743
2744 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2745 if ((word & 0x00ff) == 0x00ff) {
2746 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2747 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2748 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2749 }
2750 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2751 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2752 LED_MODE_TXRX_ACTIVITY);
2753 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2754 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2755 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2756 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2757 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2758 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2759 }
2760
2761 /*
2762 * During the LNA validation we are going to use
2763 * lna0 as correct value. Note that EEPROM_LNA
2764 * is never validated.
2765 */
2766 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2767 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2768
2769 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2770 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2771 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2772 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2773 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2774 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2775
2776 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2777 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2778 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2779 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2780 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2781 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2782 default_lna_gain);
2783 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2784
2785 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2786 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2787 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2788 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2789 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2790 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2791
2792 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2793 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2794 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2795 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2796 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2797 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2798 default_lna_gain);
2799 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2800
8d1331b3
ID		 2801 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2802 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2803 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2804 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2805 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2806 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2807
38bd7b8a
BZ		 2808 return 0;
2809}
2810EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2811
2812int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2813{
2814 u32 reg;
2815 u16 value;
2816 u16 eeprom;
2817
2818 /*
2819 * Read EEPROM word for configuration.
2820 */
2821 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2822
2823 /*
2824 * Identify RF chipset.
2825 */
2826 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2827 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2828
49e721ec
GW		 2829 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2830 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2831
2832 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2833 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2834 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2835 !rt2x00_rt(rt2x00dev, RT3070) &&
2836 !rt2x00_rt(rt2x00dev, RT3071) &&
2837 !rt2x00_rt(rt2x00dev, RT3090) &&
2838 !rt2x00_rt(rt2x00dev, RT3390) &&
2839 !rt2x00_rt(rt2x00dev, RT3572)) {
2840 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2841 return -ENODEV;
f273fe55 2842 }
714fa663 2843
5122d898
GW		 2844 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2845 !rt2x00_rf(rt2x00dev, RF2850) &&
2846 !rt2x00_rf(rt2x00dev, RF2720) &&
2847 !rt2x00_rf(rt2x00dev, RF2750) &&
2848 !rt2x00_rf(rt2x00dev, RF3020) &&
2849 !rt2x00_rf(rt2x00dev, RF2020) &&
2850 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2851 !rt2x00_rf(rt2x00dev, RF3022) &&
2852 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2853 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2854 return -ENODEV;
2855 }
2856
2857 /*
2858 * Identify default antenna configuration.
2859 */
2860 rt2x00dev->default_ant.tx =
2861 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2862 rt2x00dev->default_ant.rx =
2863 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2864
2865 /*
2866 * Read frequency offset and RF programming sequence.
2867 */
2868 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2869 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2870
2871 /*
2872 * Read external LNA informations.
2873 */
2874 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2875
2876 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2877 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2878 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2879 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2880
2881 /*
2882 * Detect if this device has an hardware controlled radio.
2883 */
2884 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2885 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2886
2887 /*
2888 * Store led settings, for correct led behaviour.
2889 */
2890#ifdef CONFIG_RT2X00_LIB_LEDS
2891 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2892 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2893 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2894
2895 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2896#endif /* CONFIG_RT2X00_LIB_LEDS */
2897
2898 return 0;
2899}
2900EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2901
4da2933f 2902/*
55f9321a 2903 * RF value list for rt28xx
4da2933f
BZ		 2904 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2905 */
2906static const struct rf_channel rf_vals[] = {
2907 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2908 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2909 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2910 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2911 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2912 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2913 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2914 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2915 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2916 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2917 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2918 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2919 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2920 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2921
2922 /* 802.11 UNI / HyperLan 2 */
2923 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2924 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2925 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2926 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2927 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2928 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2929 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2930 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2931 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2932 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2933 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2934 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2935
2936 /* 802.11 HyperLan 2 */
2937 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2938 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2939 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2940 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2941 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2942 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2943 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2944 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2945 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2946 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2947 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2948 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2949 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2950 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2951 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2952 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2953
2954 /* 802.11 UNII */
2955 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2956 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2957 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2958 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2959 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2960 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2961 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2962 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2963 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2964 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2965 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2966
2967 /* 802.11 Japan */
2968 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2969 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2970 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2971 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2972 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2973 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2974 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2975};
2976
2977/*
55f9321a
ID		 2978 * RF value list for rt3xxx
2979 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2980 */
55f9321a 2981static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2982 {1, 241, 2, 2 },
2983 {2, 241, 2, 7 },
2984 {3, 242, 2, 2 },
2985 {4, 242, 2, 7 },
2986 {5, 243, 2, 2 },
2987 {6, 243, 2, 7 },
2988 {7, 244, 2, 2 },
2989 {8, 244, 2, 7 },
2990 {9, 245, 2, 2 },
2991 {10, 245, 2, 7 },
2992 {11, 246, 2, 2 },
2993 {12, 246, 2, 7 },
2994 {13, 247, 2, 2 },
2995 {14, 248, 2, 4 },
55f9321a
ID		 2996
2997 /* 802.11 UNI / HyperLan 2 */
2998 {36, 0x56, 0, 4},
2999 {38, 0x56, 0, 6},
3000 {40, 0x56, 0, 8},
3001 {44, 0x57, 0, 0},
3002 {46, 0x57, 0, 2},
3003 {48, 0x57, 0, 4},
3004 {52, 0x57, 0, 8},
3005 {54, 0x57, 0, 10},
3006 {56, 0x58, 0, 0},
3007 {60, 0x58, 0, 4},
3008 {62, 0x58, 0, 6},
3009 {64, 0x58, 0, 8},
3010
3011 /* 802.11 HyperLan 2 */
3012 {100, 0x5b, 0, 8},
3013 {102, 0x5b, 0, 10},
3014 {104, 0x5c, 0, 0},
3015 {108, 0x5c, 0, 4},
3016 {110, 0x5c, 0, 6},
3017 {112, 0x5c, 0, 8},
3018 {116, 0x5d, 0, 0},
3019 {118, 0x5d, 0, 2},
3020 {120, 0x5d, 0, 4},
3021 {124, 0x5d, 0, 8},
3022 {126, 0x5d, 0, 10},
3023 {128, 0x5e, 0, 0},
3024 {132, 0x5e, 0, 4},
3025 {134, 0x5e, 0, 6},
3026 {136, 0x5e, 0, 8},
3027 {140, 0x5f, 0, 0},
3028
3029 /* 802.11 UNII */
3030 {149, 0x5f, 0, 9},
3031 {151, 0x5f, 0, 11},
3032 {153, 0x60, 0, 1},
3033 {157, 0x60, 0, 5},
3034 {159, 0x60, 0, 7},
3035 {161, 0x60, 0, 9},
3036 {165, 0x61, 0, 1},
3037 {167, 0x61, 0, 3},
3038 {169, 0x61, 0, 5},
3039 {171, 0x61, 0, 7},
3040 {173, 0x61, 0, 9},
4da2933f
BZ		 3041};
3042
3043int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3044{
4da2933f
BZ		 3045 struct hw_mode_spec *spec = &rt2x00dev->spec;
3046 struct channel_info *info;
8d1331b3
ID		 3047 char *default_power1;
3048 char *default_power2;
4da2933f 3049 unsigned int i;
8d1331b3 3050 unsigned short max_power;
4da2933f
BZ		 3051 u16 eeprom;
3052
93b6bd26
GW		 3053 /*
3054 * Disable powersaving as default on PCI devices.
3055 */
cea90e55 3056 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3057 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3058
4da2933f
BZ		 3059 /*
3060 * Initialize all hw fields.
3061 */
3062 rt2x00dev->hw->flags =
3063 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3064 IEEE80211_HW_SIGNAL_DBM |
3065 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3066 IEEE80211_HW_PS_NULLFUNC_STACK |
3067 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 3068
4da2933f
BZ		 3069 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3070 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3071 rt2x00_eeprom_addr(rt2x00dev,
3072 EEPROM_MAC_ADDR_0));
3073
3f2bee24
HS		 3074 /*
3075 * As rt2800 has a global fallback table we cannot specify
3076 * more then one tx rate per frame but since the hw will
3077 * try several rates (based on the fallback table) we should
3078 * still initialize max_rates to the maximum number of rates
3079 * we are going to try. Otherwise mac80211 will truncate our
3080 * reported tx rates and the rc algortihm will end up with
3081 * incorrect data.
3082 */
3083 rt2x00dev->hw->max_rates = 7;
3084 rt2x00dev->hw->max_rate_tries = 1;
3085
4da2933f
BZ		 3086 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3087
3088 /*
3089 * Initialize hw_mode information.
3090 */
3091 spec->supported_bands = SUPPORT_BAND_2GHZ;
3092 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3093
5122d898 3094 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3095 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3096 spec->num_channels = 14;
3097 spec->channels = rf_vals;
55f9321a
ID		 3098 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3099 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3100 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3101 spec->num_channels = ARRAY_SIZE(rf_vals);
3102 spec->channels = rf_vals;
5122d898
GW		 3103 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3104 rt2x00_rf(rt2x00dev, RF2020) ||
3105 rt2x00_rf(rt2x00dev, RF3021) ||
3106 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3107 spec->num_channels = 14;
3108 spec->channels = rf_vals_3x;
3109 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3110 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3111 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3112 spec->channels = rf_vals_3x;
4da2933f
BZ		 3113 }
3114
3115 /*
3116 * Initialize HT information.
3117 */
5122d898 3118 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3119 spec->ht.ht_supported = true;
3120 else
3121 spec->ht.ht_supported = false;
3122
4da2933f 3123 spec->ht.cap =
06443e46 3124 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3125 IEEE80211_HT_CAP_GRN_FLD |
3126 IEEE80211_HT_CAP_SGI_20 |
aa674631 3127 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3128
3129 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3130 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3131
aa674631
ID		 3132 spec->ht.cap |=
3133 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3134 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3135
4da2933f
BZ		 3136 spec->ht.ampdu_factor = 3;
3137 spec->ht.ampdu_density = 4;
3138 spec->ht.mcs.tx_params =
3139 IEEE80211_HT_MCS_TX_DEFINED |
3140 IEEE80211_HT_MCS_TX_RX_DIFF |
3141 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3142 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3143
3144 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3145 case 3:
3146 spec->ht.mcs.rx_mask[2] = 0xff;
3147 case 2:
3148 spec->ht.mcs.rx_mask[1] = 0xff;
3149 case 1:
3150 spec->ht.mcs.rx_mask[0] = 0xff;
3151 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3152 break;
3153 }
3154
3155 /*
3156 * Create channel information array
3157 */
3158 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3159 if (!info)
3160 return -ENOMEM;
3161
3162 spec->channels_info = info;
3163
8d1331b3
ID		 3164 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3165 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3166 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3167 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3168
3169 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3170 info[i].max_power = max_power;
3171 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3172 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3173 }
3174
3175 if (spec->num_channels > 14) {
8d1331b3
ID		 3176 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3177 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3178 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3179
3180 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3181 info[i].max_power = max_power;
3182 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3183 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3184 }
3185 }
3186
3187 return 0;
3188}
3189EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3190
2ce33995
BZ		 3191/*
3192 * IEEE80211 stack callback functions.
3193 */
e783619e
HS		 3194void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3195 u16 *iv16)
2ce33995
BZ		 3196{
3197 struct rt2x00_dev *rt2x00dev = hw->priv;
3198 struct mac_iveiv_entry iveiv_entry;
3199 u32 offset;
3200
3201 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3202 rt2800_register_multiread(rt2x00dev, offset,
3203 &iveiv_entry, sizeof(iveiv_entry));
3204
855da5e0
JL		 3205 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3206 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3207}
e783619e 3208EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3209
e783619e 3210int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3211{
3212 struct rt2x00_dev *rt2x00dev = hw->priv;
3213 u32 reg;
3214 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3215
3216 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3217 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3218 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3219
3220 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3221 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3222 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3223
3224 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3225 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3226 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3227
3228 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3229 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3230 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3231
3232 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3233 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3234 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3235
3236 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3237 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3238 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3239
3240 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3241 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3242 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3243
3244 return 0;
3245}
e783619e 3246EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3247
e783619e
HS		 3248int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3249 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3250{
3251 struct rt2x00_dev *rt2x00dev = hw->priv;
3252 struct data_queue *queue;
3253 struct rt2x00_field32 field;
3254 int retval;
3255 u32 reg;
3256 u32 offset;
3257
3258 /*
3259 * First pass the configuration through rt2x00lib, that will
3260 * update the queue settings and validate the input. After that
3261 * we are free to update the registers based on the value
3262 * in the queue parameter.
3263 */
3264 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3265 if (retval)
3266 return retval;
3267
3268 /*
3269 * We only need to perform additional register initialization
3270 * for WMM queues/
3271 */
3272 if (queue_idx >= 4)
3273 return 0;
3274
3275 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3276
3277 /* Update WMM TXOP register */
3278 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3279 field.bit_offset = (queue_idx & 1) * 16;
3280 field.bit_mask = 0xffff << field.bit_offset;
3281
3282 rt2800_register_read(rt2x00dev, offset, &reg);
3283 rt2x00_set_field32(&reg, field, queue->txop);
3284 rt2800_register_write(rt2x00dev, offset, reg);
3285
3286 /* Update WMM registers */
3287 field.bit_offset = queue_idx * 4;
3288 field.bit_mask = 0xf << field.bit_offset;
3289
3290 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3291 rt2x00_set_field32(&reg, field, queue->aifs);
3292 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3293
3294 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3295 rt2x00_set_field32(&reg, field, queue->cw_min);
3296 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3297
3298 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3299 rt2x00_set_field32(&reg, field, queue->cw_max);
3300 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3301
3302 /* Update EDCA registers */
3303 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3304
3305 rt2800_register_read(rt2x00dev, offset, &reg);
3306 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3307 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3308 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3309 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3310 rt2800_register_write(rt2x00dev, offset, reg);
3311
3312 return 0;
3313}
e783619e 3314EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3315
e783619e 3316u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3317{
3318 struct rt2x00_dev *rt2x00dev = hw->priv;
3319 u64 tsf;
3320 u32 reg;
3321
3322 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3323 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3324 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3325 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3326
3327 return tsf;
3328}
e783619e 3329EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3330
e783619e
HS		 3331int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3332 enum ieee80211_ampdu_mlme_action action,
3333 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3334{
1df90809
HS		 3335 int ret = 0;
3336
3337 switch (action) {
3338 case IEEE80211_AMPDU_RX_START:
3339 case IEEE80211_AMPDU_RX_STOP:
3340 /* we don't support RX aggregation yet */
3341 ret = -ENOTSUPP;
3342 break;
3343 case IEEE80211_AMPDU_TX_START:
3344 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3345 break;
3346 case IEEE80211_AMPDU_TX_STOP:
3347 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3348 break;
3349 case IEEE80211_AMPDU_TX_OPERATIONAL:
3350 break;
3351 default:
4e9e58c6 3352 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3353 }
3354
3355 return ret;
3356}
e783619e 3357EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3358
3359MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3360MODULE_VERSION(DRV_VERSION);
3361MODULE_DESCRIPTION("Ralink RT2800 library");
3362MODULE_LICENSE("GPL");
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