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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
52b8243b 293 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
67a4c1e2
GW		 294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f7b395e9
JK		 298void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
299{
300 u32 reg;
301
302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309}
310EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
311
f31c9a8c
ID		 312static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
313{
314 u16 fw_crc;
315 u16 crc;
316
317 /*
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
320 * algorithm.
321 */
322 fw_crc = (data[len - 2] << 8 | data[len - 1]);
323
324 /*
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
330 */
331 crc = crc_ccitt(~0, data, len - 2);
332
333 /*
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
337 * value.
338 */
339 crc = swab16(crc);
340
341 return fw_crc == crc;
342}
343
344int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
345 const u8 *data, const size_t len)
346{
347 size_t offset = 0;
348 size_t fw_len;
349 bool multiple;
350
351 /*
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb.
358 */
359 if (rt2x00_is_usb(rt2x00dev)) {
360 fw_len = 4096;
361 multiple = true;
362 } else {
363 fw_len = 8192;
364 multiple = true;
365 }
366
367 /*
368 * Validate the firmware length
369 */
370 if (len != fw_len && (!multiple || (len % fw_len) != 0))
371 return FW_BAD_LENGTH;
372
373 /*
374 * Check if the chipset requires one of the upper parts
375 * of the firmware.
376 */
377 if (rt2x00_is_usb(rt2x00dev) &&
378 !rt2x00_rt(rt2x00dev, RT2860) &&
379 !rt2x00_rt(rt2x00dev, RT2872) &&
380 !rt2x00_rt(rt2x00dev, RT3070) &&
381 ((len / fw_len) == 1))
382 return FW_BAD_VERSION;
383
384 /*
385 * 8kb firmware files must be checked as if it were
386 * 2 separate firmware files.
387 */
388 while (offset < len) {
389 if (!rt2800_check_firmware_crc(data + offset, fw_len))
390 return FW_BAD_CRC;
391
392 offset += fw_len;
393 }
394
395 return FW_OK;
396}
397EXPORT_SYMBOL_GPL(rt2800_check_firmware);
398
399int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 const u8 *data, const size_t len)
401{
402 unsigned int i;
403 u32 reg;
404
405 /*
b9eca242
ID		 406 * If driver doesn't wake up firmware here,
407 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 408 */
b9eca242 409 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 410
f31c9a8c
ID		 411 /*
412 * Wait for stable hardware.
413 */
5ffddc49 414 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 415 return -EBUSY;
f31c9a8c 416
adde5882 417 if (rt2x00_is_pci(rt2x00dev)) {
872834df 418 if (rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
422 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
423 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
424 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
425 }
f31c9a8c 426 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 427 }
f31c9a8c 428
b7e1d225
JK		 429 rt2800_disable_wpdma(rt2x00dev);
430
f31c9a8c
ID		 431 /*
432 * Write firmware to the device.
433 */
434 rt2800_drv_write_firmware(rt2x00dev, data, len);
435
436 /*
437 * Wait for device to stabilize.
438 */
439 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
440 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
441 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
442 break;
443 msleep(1);
444 }
445
446 if (i == REGISTER_BUSY_COUNT) {
447 ERROR(rt2x00dev, "PBF system register not ready.\n");
448 return -EBUSY;
449 }
450
4ed1dd2a
SG		 451 /*
452 * Disable DMA, will be reenabled later when enabling
453 * the radio.
454 */
f7b395e9 455 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 456
f31c9a8c
ID		 457 /*
458 * Initialize firmware.
459 */
460 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
461 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 462 if (rt2x00_is_usb(rt2x00dev))
463 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 464 msleep(1);
465
466 return 0;
467}
468EXPORT_SYMBOL_GPL(rt2800_load_firmware);
469
0c5879bc
ID		 470void rt2800_write_tx_data(struct queue_entry *entry,
471 struct txentry_desc *txdesc)
59679b91 472{
0c5879bc 473 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 474 u32 word;
475
476 /*
477 * Initialize TX Info descriptor
478 */
479 rt2x00_desc_read(txwi, 0, &word);
480 rt2x00_set_field32(&word, TXWI_W0_FRAG,
481 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 482 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
483 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 484 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
485 rt2x00_set_field32(&word, TXWI_W0_TS,
486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
487 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
488 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 489 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
490 txdesc->u.ht.mpdu_density);
491 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
492 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 493 rt2x00_set_field32(&word, TXWI_W0_BW,
494 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
495 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
496 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 497 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 498 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
499 rt2x00_desc_write(txwi, 0, word);
500
501 rt2x00_desc_read(txwi, 1, &word);
502 rt2x00_set_field32(&word, TXWI_W1_ACK,
503 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
504 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
505 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 506 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 507 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
508 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 509 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 510 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
511 txdesc->length);
2b23cdaa 512 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 513 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 514 rt2x00_desc_write(txwi, 1, word);
515
516 /*
517 * Always write 0 to IV/EIV fields, hardware will insert the IV
518 * from the IVEIV register when TXD_W3_WIV is set to 0.
519 * When TXD_W3_WIV is set to 1 it will use the IV data
520 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
521 * crypto entry in the registers should be used to encrypt the frame.
522 */
523 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
524 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
525}
0c5879bc 526EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 527
ff6133be 528static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 529{
7fc41755
LT		 530 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
531 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
532 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 533 u16 eeprom;
534 u8 offset0;
535 u8 offset1;
536 u8 offset2;
537
e5ef5bad 538 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 539 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
540 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
541 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
542 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
543 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
544 } else {
545 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
546 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
547 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
548 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
549 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
550 }
551
552 /*
553 * Convert the value from the descriptor into the RSSI value
554 * If the value in the descriptor is 0, it is considered invalid
555 * and the default (extremely low) rssi value is assumed
556 */
557 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
558 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
559 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
560
561 /*
562 * mac80211 only accepts a single RSSI value. Calculating the
563 * average doesn't deliver a fair answer either since -60:-60 would
564 * be considered equally good as -50:-70 while the second is the one
565 * which gives less energy...
566 */
567 rssi0 = max(rssi0, rssi1);
7fc41755 568 return (int)max(rssi0, rssi2);
74861922
ID		 569}
570
571void rt2800_process_rxwi(struct queue_entry *entry,
572 struct rxdone_entry_desc *rxdesc)
573{
574 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 575 u32 word;
576
577 rt2x00_desc_read(rxwi, 0, &word);
578
579 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
580 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
581
582 rt2x00_desc_read(rxwi, 1, &word);
583
584 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
585 rxdesc->flags |= RX_FLAG_SHORT_GI;
586
587 if (rt2x00_get_field32(word, RXWI_W1_BW))
588 rxdesc->flags |= RX_FLAG_40MHZ;
589
590 /*
591 * Detect RX rate, always use MCS as signal type.
592 */
593 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
594 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
595 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
596
597 /*
598 * Mask of 0x8 bit to remove the short preamble flag.
599 */
600 if (rxdesc->rate_mode == RATE_MODE_CCK)
601 rxdesc->signal &= ~0x8;
602
603 rt2x00_desc_read(rxwi, 2, &word);
604
74861922
ID		 605 /*
606 * Convert descriptor AGC value to RSSI value.
607 */
608 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 609
610 /*
611 * Remove RXWI descriptor from start of buffer.
612 */
74861922 613 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 614}
615EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
616
31937c42 617void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 618{
619 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 620 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 621 struct txdone_entry_desc txdesc;
622 u32 word;
623 u16 mcs, real_mcs;
b34793ee 624 int aggr, ampdu;
14433331
HS		 625
626 /*
627 * Obtain the status about this packet.
628 */
629 txdesc.flags = 0;
14433331 630 rt2x00_desc_read(txwi, 0, &word);
b34793ee 631
14433331 632 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 633 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
634
14433331 635 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 636 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
637
638 /*
639 * If a frame was meant to be sent as a single non-aggregated MPDU
640 * but ended up in an aggregate the used tx rate doesn't correlate
641 * with the one specified in the TXWI as the whole aggregate is sent
642 * with the same rate.
643 *
644 * For example: two frames are sent to rt2x00, the first one sets
645 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
646 * and requests MCS15. If the hw aggregates both frames into one
647 * AMDPU the tx status for both frames will contain MCS7 although
648 * the frame was sent successfully.
649 *
650 * Hence, replace the requested rate with the real tx rate to not
651 * confuse the rate control algortihm by providing clearly wrong
652 * data.
653 */
5356d963 654 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 655 skbdesc->tx_rate_idx = real_mcs;
656 mcs = real_mcs;
657 }
14433331 658
f16d2db7
HS		 659 if (aggr == 1 || ampdu == 1)
660 __set_bit(TXDONE_AMPDU, &txdesc.flags);
661
14433331
HS		 662 /*
663 * Ralink has a retry mechanism using a global fallback
664 * table. We setup this fallback table to try the immediate
665 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
666 * always contains the MCS used for the last transmission, be
667 * it successful or not.
668 */
669 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
670 /*
671 * Transmission succeeded. The number of retries is
672 * mcs - real_mcs
673 */
674 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
675 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
676 } else {
677 /*
678 * Transmission failed. The number of retries is
679 * always 7 in this case (for a total number of 8
680 * frames sent).
681 */
682 __set_bit(TXDONE_FAILURE, &txdesc.flags);
683 txdesc.retry = rt2x00dev->long_retry;
684 }
685
686 /*
687 * the frame was retried at least once
688 * -> hw used fallback rates
689 */
690 if (txdesc.retry)
691 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
692
693 rt2x00lib_txdone(entry, &txdesc);
694}
695EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
696
f0194b2d
GW		 697void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
698{
699 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
700 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
701 unsigned int beacon_base;
739fd940 702 unsigned int padding_len;
d76dfc61 703 u32 orig_reg, reg;
f0194b2d
GW		 704
705 /*
706 * Disable beaconing while we are reloading the beacon data,
707 * otherwise we might be sending out invalid data.
708 */
709 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 710 orig_reg = reg;
f0194b2d
GW		 711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
712 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
713
714 /*
715 * Add space for the TXWI in front of the skb.
716 */
b52398b6 717 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 718
719 /*
720 * Register descriptor details in skb frame descriptor.
721 */
722 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
723 skbdesc->desc = entry->skb->data;
724 skbdesc->desc_len = TXWI_DESC_SIZE;
725
726 /*
727 * Add the TXWI for the beacon to the skb.
728 */
0c5879bc 729 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 730
731 /*
732 * Dump beacon to userspace through debugfs.
733 */
734 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
735
736 /*
739fd940 737 * Write entire beacon with TXWI and padding to register.
f0194b2d 738 */
739fd940 739 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 740 if (padding_len && skb_pad(entry->skb, padding_len)) {
741 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
742 /* skb freed by skb_pad() on failure */
743 entry->skb = NULL;
744 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
745 return;
746 }
747
f0194b2d 748 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 749 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
750 entry->skb->len + padding_len);
f0194b2d
GW		 751
752 /*
753 * Enable beaconing again.
754 */
f0194b2d
GW		 755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
756 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
757
758 /*
759 * Clean up beacon skb.
760 */
761 dev_kfree_skb_any(entry->skb);
762 entry->skb = NULL;
763}
50e888ea 764EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 765
69cf36a4
HS		 766static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
767 unsigned int beacon_base)
fdb87251
HS		 768{
769 int i;
770
771 /*
772 * For the Beacon base registers we only need to clear
773 * the whole TXWI which (when set to 0) will invalidate
774 * the entire beacon.
775 */
776 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
777 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
778}
779
69cf36a4
HS		 780void rt2800_clear_beacon(struct queue_entry *entry)
781{
782 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
783 u32 reg;
784
785 /*
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
788 */
789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
790 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
791 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
792
793 /*
794 * Clear beacon.
795 */
796 rt2800_clear_beacon_register(rt2x00dev,
797 HW_BEACON_OFFSET(entry->entry_idx));
798
799 /*
800 * Enabled beaconing again.
801 */
802 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
803 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
804}
805EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
806
f4450616
BZ		 807#ifdef CONFIG_RT2X00_LIB_DEBUGFS
808const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
810 .csr = {
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
817 },
818 .eeprom = {
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
824 },
825 .bbp = {
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
831 },
832 .rf = {
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
838 },
f2bd7f16
AA		 839 .rfcsr = {
840 .read = rt2800_rfcsr_read,
841 .write = rt2800_rfcsr_write,
842 .word_base = RFCSR_BASE,
843 .word_size = sizeof(u8),
844 .word_count = RFCSR_SIZE / sizeof(u8),
845 },
f4450616
BZ		 846};
847EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
848#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
849
850int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
851{
852 u32 reg;
853
854 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
855 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
856}
857EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
858
859#ifdef CONFIG_RT2X00_LIB_LEDS
860static void rt2800_brightness_set(struct led_classdev *led_cdev,
861 enum led_brightness brightness)
862{
863 struct rt2x00_led *led =
864 container_of(led_cdev, struct rt2x00_led, led_dev);
865 unsigned int enabled = brightness != LED_OFF;
866 unsigned int bg_mode =
867 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
868 unsigned int polarity =
869 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
870 EEPROM_FREQ_LED_POLARITY);
871 unsigned int ledmode =
872 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
873 EEPROM_FREQ_LED_MODE);
44704e5d 874 u32 reg;
f4450616 875
44704e5d
LE		 876 /* Check for SoC (SOC devices don't support MCU requests) */
877 if (rt2x00_is_soc(led->rt2x00dev)) {
878 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
879
880 /* Set LED Polarity */
881 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
882
883 /* Set LED Mode */
884 if (led->type == LED_TYPE_RADIO) {
885 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
886 enabled ? 3 : 0);
887 } else if (led->type == LED_TYPE_ASSOC) {
888 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
889 enabled ? 3 : 0);
890 } else if (led->type == LED_TYPE_QUALITY) {
891 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
892 enabled ? 3 : 0);
893 }
894
895 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
896
897 } else {
898 if (led->type == LED_TYPE_RADIO) {
899 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
900 enabled ? 0x20 : 0);
901 } else if (led->type == LED_TYPE_ASSOC) {
902 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
903 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
904 } else if (led->type == LED_TYPE_QUALITY) {
905 /*
906 * The brightness is divided into 6 levels (0 - 5),
907 * The specs tell us the following levels:
908 * 0, 1 ,3, 7, 15, 31
909 * to determine the level in a simple way we can simply
910 * work with bitshifting:
911 * (1 << level) - 1
912 */
913 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
914 (1 << brightness / (LED_FULL / 6)) - 1,
915 polarity);
916 }
f4450616
BZ		 917 }
918}
919
b3579d6a 920static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 921 struct rt2x00_led *led, enum led_type type)
922{
923 led->rt2x00dev = rt2x00dev;
924 led->type = type;
925 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 926 led->flags = LED_INITIALIZED;
927}
f4450616
BZ		 928#endif /* CONFIG_RT2X00_LIB_LEDS */
929
930/*
931 * Configuration handlers.
932 */
a2b1328a
HS		 933static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
934 const u8 *address,
935 int wcid)
f4450616
BZ		 936{
937 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 938 u32 offset;
939
940 offset = MAC_WCID_ENTRY(wcid);
941
942 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
943 if (address)
944 memcpy(wcid_entry.mac, address, ETH_ALEN);
945
946 rt2800_register_multiwrite(rt2x00dev, offset,
947 &wcid_entry, sizeof(wcid_entry));
948}
949
950static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
951{
952 u32 offset;
953 offset = MAC_WCID_ATTR_ENTRY(wcid);
954 rt2800_register_write(rt2x00dev, offset, 0);
955}
956
957static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
958 int wcid, u32 bssidx)
959{
960 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
961 u32 reg;
962
963 /*
964 * The BSS Idx numbers is split in a main value of 3 bits,
965 * and a extended field for adding one additional bit to the value.
966 */
967 rt2800_register_read(rt2x00dev, offset, &reg);
968 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
969 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
970 (bssidx & 0x8) >> 3);
971 rt2800_register_write(rt2x00dev, offset, reg);
972}
973
974static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
975 struct rt2x00lib_crypto *crypto,
976 struct ieee80211_key_conf *key)
977{
f4450616
BZ		 978 struct mac_iveiv_entry iveiv_entry;
979 u32 offset;
980 u32 reg;
981
982 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
983
e4a0ab34
ID		 984 if (crypto->cmd == SET_KEY) {
985 rt2800_register_read(rt2x00dev, offset, &reg);
986 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
987 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
988 /*
989 * Both the cipher as the BSS Idx numbers are split in a main
990 * value of 3 bits, and a extended field for adding one additional
991 * bit to the value.
992 */
993 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
994 (crypto->cipher & 0x7));
995 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
996 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 997 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
998 rt2800_register_write(rt2x00dev, offset, reg);
999 } else {
a2b1328a
HS		 1000 /* Delete the cipher without touching the bssidx */
1001 rt2800_register_read(rt2x00dev, offset, &reg);
1002 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1003 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1004 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1005 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1006 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1007 }
f4450616
BZ		 1008
1009 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1010
1011 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1012 if ((crypto->cipher == CIPHER_TKIP) ||
1013 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1014 (crypto->cipher == CIPHER_AES))
1015 iveiv_entry.iv[3] |= 0x20;
1016 iveiv_entry.iv[3] |= key->keyidx << 6;
1017 rt2800_register_multiwrite(rt2x00dev, offset,
1018 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1019}
1020
1021int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1022 struct rt2x00lib_crypto *crypto,
1023 struct ieee80211_key_conf *key)
1024{
1025 struct hw_key_entry key_entry;
1026 struct rt2x00_field32 field;
1027 u32 offset;
1028 u32 reg;
1029
1030 if (crypto->cmd == SET_KEY) {
1031 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1032
1033 memcpy(key_entry.key, crypto->key,
1034 sizeof(key_entry.key));
1035 memcpy(key_entry.tx_mic, crypto->tx_mic,
1036 sizeof(key_entry.tx_mic));
1037 memcpy(key_entry.rx_mic, crypto->rx_mic,
1038 sizeof(key_entry.rx_mic));
1039
1040 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1041 rt2800_register_multiwrite(rt2x00dev, offset,
1042 &key_entry, sizeof(key_entry));
1043 }
1044
1045 /*
1046 * The cipher types are stored over multiple registers
1047 * starting with SHARED_KEY_MODE_BASE each word will have
1048 * 32 bits and contains the cipher types for 2 bssidx each.
1049 * Using the correct defines correctly will cause overhead,
1050 * so just calculate the correct offset.
1051 */
1052 field.bit_offset = 4 * (key->hw_key_idx % 8);
1053 field.bit_mask = 0x7 << field.bit_offset;
1054
1055 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1056
1057 rt2800_register_read(rt2x00dev, offset, &reg);
1058 rt2x00_set_field32(&reg, field,
1059 (crypto->cmd == SET_KEY) * crypto->cipher);
1060 rt2800_register_write(rt2x00dev, offset, reg);
1061
1062 /*
1063 * Update WCID information
1064 */
a2b1328a
HS		 1065 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1066 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1067 crypto->bssidx);
1068 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1069
1070 return 0;
1071}
1072EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1073
a2b1328a 1074static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1075{
a2b1328a 1076 struct mac_wcid_entry wcid_entry;
1ed3811c 1077 int idx;
a2b1328a 1078 u32 offset;
1ed3811c
HS		 1079
1080 /*
a2b1328a
HS		 1081 * Search for the first free WCID entry and return the corresponding
1082 * index.
1ed3811c
HS		 1083 *
1084 * Make sure the WCID starts _after_ the last possible shared key
1085 * entry (>32).
1086 *
1087 * Since parts of the pairwise key table might be shared with
1088 * the beacon frame buffers 6 & 7 we should only write into the
1089 * first 222 entries.
1090 */
1091 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1092 offset = MAC_WCID_ENTRY(idx);
1093 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1094 sizeof(wcid_entry));
1095 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1096 return idx;
1097 }
a2b1328a
HS		 1098
1099 /*
1100 * Use -1 to indicate that we don't have any more space in the WCID
1101 * table.
1102 */
1ed3811c
HS		 1103 return -1;
1104}
1105
f4450616
BZ		 1106int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1107 struct rt2x00lib_crypto *crypto,
1108 struct ieee80211_key_conf *key)
1109{
1110 struct hw_key_entry key_entry;
1111 u32 offset;
1112
1113 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1114 /*
1115 * Allow key configuration only for STAs that are
1116 * known by the hw.
1117 */
1118 if (crypto->wcid < 0)
f4450616 1119 return -ENOSPC;
a2b1328a 1120 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1121
1122 memcpy(key_entry.key, crypto->key,
1123 sizeof(key_entry.key));
1124 memcpy(key_entry.tx_mic, crypto->tx_mic,
1125 sizeof(key_entry.tx_mic));
1126 memcpy(key_entry.rx_mic, crypto->rx_mic,
1127 sizeof(key_entry.rx_mic));
1128
1129 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1130 rt2800_register_multiwrite(rt2x00dev, offset,
1131 &key_entry, sizeof(key_entry));
1132 }
1133
1134 /*
1135 * Update WCID information
1136 */
a2b1328a 1137 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1138
1139 return 0;
1140}
1141EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1142
a2b1328a
HS		 1143int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1144 struct ieee80211_sta *sta)
1145{
1146 int wcid;
1147 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1148
1149 /*
1150 * Find next free WCID.
1151 */
1152 wcid = rt2800_find_wcid(rt2x00dev);
1153
1154 /*
1155 * Store selected wcid even if it is invalid so that we can
1156 * later decide if the STA is uploaded into the hw.
1157 */
1158 sta_priv->wcid = wcid;
1159
1160 /*
1161 * No space left in the device, however, we can still communicate
1162 * with the STA -> No error.
1163 */
1164 if (wcid < 0)
1165 return 0;
1166
1167 /*
1168 * Clean up WCID attributes and write STA address to the device.
1169 */
1170 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1171 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1172 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1173 rt2x00lib_get_bssidx(rt2x00dev, vif));
1174 return 0;
1175}
1176EXPORT_SYMBOL_GPL(rt2800_sta_add);
1177
1178int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1179{
1180 /*
1181 * Remove WCID entry, no need to clean the attributes as they will
1182 * get renewed when the WCID is reused.
1183 */
1184 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1185
1186 return 0;
1187}
1188EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1189
f4450616
BZ		 1190void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1191 const unsigned int filter_flags)
1192{
1193 u32 reg;
1194
1195 /*
1196 * Start configuration steps.
1197 * Note that the version error will always be dropped
1198 * and broadcast frames will always be accepted since
1199 * there is no filter for it at this time.
1200 */
1201 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1202 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1203 !(filter_flags & FIF_FCSFAIL));
1204 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1205 !(filter_flags & FIF_PLCPFAIL));
1206 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1207 !(filter_flags & FIF_PROMISC_IN_BSS));
1208 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1210 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1211 !(filter_flags & FIF_ALLMULTI));
1212 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1213 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1214 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1215 !(filter_flags & FIF_CONTROL));
1216 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1217 !(filter_flags & FIF_CONTROL));
1218 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1219 !(filter_flags & FIF_CONTROL));
1220 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1221 !(filter_flags & FIF_CONTROL));
1222 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1223 !(filter_flags & FIF_CONTROL));
1224 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1225 !(filter_flags & FIF_PSPOLL));
48839938
HS		 1226 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1227 !(filter_flags & FIF_CONTROL));
1228 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1229 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1230 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1231 !(filter_flags & FIF_CONTROL));
1232 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1233}
1234EXPORT_SYMBOL_GPL(rt2800_config_filter);
1235
1236void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1237 struct rt2x00intf_conf *conf, const unsigned int flags)
1238{
f4450616 1239 u32 reg;
fa8b4b22 1240 bool update_bssid = false;
f4450616
BZ		 1241
1242 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1243 /*
1244 * Enable synchronisation.
1245 */
1246 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1247 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1248 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1249
1250 if (conf->sync == TSF_SYNC_AP_NONE) {
1251 /*
1252 * Tune beacon queue transmit parameters for AP mode
1253 */
1254 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1255 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1256 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1257 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1258 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1259 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1260 } else {
1261 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1262 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1263 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1264 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1265 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1266 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1267 }
f4450616
BZ		 1268 }
1269
1270 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1271 if (flags & CONFIG_UPDATE_TYPE &&
1272 conf->sync == TSF_SYNC_AP_NONE) {
1273 /*
1274 * The BSSID register has to be set to our own mac
1275 * address in AP mode.
1276 */
1277 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1278 update_bssid = true;
1279 }
1280
c600c826
ID		 1281 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1282 reg = le32_to_cpu(conf->mac[1]);
1283 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1284 conf->mac[1] = cpu_to_le32(reg);
1285 }
f4450616
BZ		 1286
1287 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1288 conf->mac, sizeof(conf->mac));
1289 }
1290
fa8b4b22 1291 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1292 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1293 reg = le32_to_cpu(conf->bssid[1]);
1294 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1295 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1296 conf->bssid[1] = cpu_to_le32(reg);
1297 }
f4450616
BZ		 1298
1299 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1300 conf->bssid, sizeof(conf->bssid));
1301 }
1302}
1303EXPORT_SYMBOL_GPL(rt2800_config_intf);
1304
87c1915d
HS		 1305static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1306 struct rt2x00lib_erp *erp)
1307{
1308 bool any_sta_nongf = !!(erp->ht_opmode &
1309 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1310 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1311 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1312 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1313 u32 reg;
1314
1315 /* default protection rate for HT20: OFDM 24M */
1316 mm20_rate = gf20_rate = 0x4004;
1317
1318 /* default protection rate for HT40: duplicate OFDM 24M */
1319 mm40_rate = gf40_rate = 0x4084;
1320
1321 switch (protection) {
1322 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1323 /*
1324 * All STAs in this BSS are HT20/40 but there might be
1325 * STAs not supporting greenfield mode.
1326 * => Disable protection for HT transmissions.
1327 */
1328 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1329
1330 break;
1331 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1332 /*
1333 * All STAs in this BSS are HT20 or HT20/40 but there
1334 * might be STAs not supporting greenfield mode.
1335 * => Protect all HT40 transmissions.
1336 */
1337 mm20_mode = gf20_mode = 0;
1338 mm40_mode = gf40_mode = 2;
1339
1340 break;
1341 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1342 /*
1343 * Nonmember protection:
1344 * According to 802.11n we _should_ protect all
1345 * HT transmissions (but we don't have to).
1346 *
1347 * But if cts_protection is enabled we _shall_ protect
1348 * all HT transmissions using a CCK rate.
1349 *
1350 * And if any station is non GF we _shall_ protect
1351 * GF transmissions.
1352 *
1353 * We decide to protect everything
1354 * -> fall through to mixed mode.
1355 */
1356 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1357 /*
1358 * Legacy STAs are present
1359 * => Protect all HT transmissions.
1360 */
1361 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1362
1363 /*
1364 * If erp protection is needed we have to protect HT
1365 * transmissions with CCK 11M long preamble.
1366 */
1367 if (erp->cts_protection) {
1368 /* don't duplicate RTS/CTS in CCK mode */
1369 mm20_rate = mm40_rate = 0x0003;
1370 gf20_rate = gf40_rate = 0x0003;
1371 }
1372 break;
6403eab1 1373 }
87c1915d
HS		 1374
1375 /* check for STAs not supporting greenfield mode */
1376 if (any_sta_nongf)
1377 gf20_mode = gf40_mode = 2;
1378
1379 /* Update HT protection config */
1380 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1381 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1382 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1383 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1384
1385 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1386 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1387 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1388 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1389
1390 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1391 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1392 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1393 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1394
1395 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1396 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1397 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1398 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1399}
1400
02044643
HS		 1401void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1402 u32 changed)
f4450616
BZ		 1403{
1404 u32 reg;
1405
02044643
HS		 1406 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1407 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1408 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1409 !!erp->short_preamble);
1410 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1411 !!erp->short_preamble);
1412 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1413 }
f4450616 1414
02044643
HS		 1415 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1416 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1417 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1418 erp->cts_protection ? 2 : 0);
1419 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1420 }
f4450616 1421
02044643
HS		 1422 if (changed & BSS_CHANGED_BASIC_RATES) {
1423 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1424 erp->basic_rates);
1425 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1426 }
f4450616 1427
02044643
HS		 1428 if (changed & BSS_CHANGED_ERP_SLOT) {
1429 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1430 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1431 erp->slot_time);
1432 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1433
02044643
HS		 1434 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1435 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1436 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1437 }
f4450616 1438
02044643
HS		 1439 if (changed & BSS_CHANGED_BEACON_INT) {
1440 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1441 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1442 erp->beacon_int * 16);
1443 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1444 }
87c1915d
HS		 1445
1446 if (changed & BSS_CHANGED_HT)
1447 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1448}
1449EXPORT_SYMBOL_GPL(rt2800_config_erp);
1450
872834df
GW		 1451static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1452{
1453 u32 reg;
1454 u16 eeprom;
1455 u8 led_ctrl, led_g_mode, led_r_mode;
1456
1457 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1458 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1459 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1460 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1461 } else {
1462 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1463 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1464 }
1465 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1466
1467 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1468 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1469 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1470 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1471 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1472 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1473 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1474 if (led_ctrl == 0 || led_ctrl > 0x40) {
1475 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1476 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1477 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1478 } else {
1479 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1480 (led_g_mode << 2) | led_r_mode, 1);
1481 }
1482 }
1483}
1484
d96aa640
RJH		 1485static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1486 enum antenna ant)
1487{
1488 u32 reg;
1489 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1490 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1491
1492 if (rt2x00_is_pci(rt2x00dev)) {
1493 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1494 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1495 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1496 } else if (rt2x00_is_usb(rt2x00dev))
1497 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1498 eesk_pin, 0);
1499
1500 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1501 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1502 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1503 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1504}
1505
f4450616
BZ		 1506void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1507{
1508 u8 r1;
1509 u8 r3;
d96aa640 1510 u16 eeprom;
f4450616
BZ		 1511
1512 rt2800_bbp_read(rt2x00dev, 1, &r1);
1513 rt2800_bbp_read(rt2x00dev, 3, &r3);
1514
872834df
GW		 1515 if (rt2x00_rt(rt2x00dev, RT3572) &&
1516 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1517 rt2800_config_3572bt_ant(rt2x00dev);
1518
f4450616
BZ		 1519 /*
1520 * Configure the TX antenna.
1521 */
d96aa640 1522 switch (ant->tx_chain_num) {
f4450616
BZ		 1523 case 1:
1524 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1525 break;
1526 case 2:
872834df
GW		 1527 if (rt2x00_rt(rt2x00dev, RT3572) &&
1528 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1529 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1530 else
1531 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1532 break;
1533 case 3:
e22557f2 1534 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1535 break;
1536 }
1537
1538 /*
1539 * Configure the RX antenna.
1540 */
d96aa640 1541 switch (ant->rx_chain_num) {
f4450616 1542 case 1:
d96aa640
RJH		 1543 if (rt2x00_rt(rt2x00dev, RT3070) ||
1544 rt2x00_rt(rt2x00dev, RT3090) ||
1545 rt2x00_rt(rt2x00dev, RT3390)) {
1546 rt2x00_eeprom_read(rt2x00dev,
1547 EEPROM_NIC_CONF1, &eeprom);
1548 if (rt2x00_get_field16(eeprom,
1549 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1550 rt2800_set_ant_diversity(rt2x00dev,
1551 rt2x00dev->default_ant.rx);
1552 }
f4450616
BZ		 1553 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1554 break;
1555 case 2:
872834df
GW		 1556 if (rt2x00_rt(rt2x00dev, RT3572) &&
1557 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1558 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1559 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1560 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1561 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1562 } else {
1563 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1564 }
f4450616
BZ		 1565 break;
1566 case 3:
1567 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1568 break;
1569 }
1570
1571 rt2800_bbp_write(rt2x00dev, 3, r3);
1572 rt2800_bbp_write(rt2x00dev, 1, r1);
1573}
1574EXPORT_SYMBOL_GPL(rt2800_config_ant);
1575
1576static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1577 struct rt2x00lib_conf *libconf)
1578{
1579 u16 eeprom;
1580 short lna_gain;
1581
1582 if (libconf->rf.channel <= 14) {
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1584 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1585 } else if (libconf->rf.channel <= 64) {
1586 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1587 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1588 } else if (libconf->rf.channel <= 128) {
1589 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1590 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1591 } else {
1592 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1593 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1594 }
1595
1596 rt2x00dev->lna_gain = lna_gain;
1597}
1598
06855ef4
GW		 1599static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1600 struct ieee80211_conf *conf,
1601 struct rf_channel *rf,
1602 struct channel_info *info)
f4450616
BZ		 1603{
1604 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1605
d96aa640 1606 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1607 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1608
d96aa640 1609 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1610 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1611 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1612 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1613 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1614
1615 if (rf->channel > 14) {
1616 /*
1617 * When TX power is below 0, we should increase it by 7 to
25985edc 1618 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1619 * However this means that values between 0 and 7 have
1620 * double meaning, and we should set a 7DBm boost flag.
1621 */
1622 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1623 (info->default_power1 >= 0));
f4450616 1624
8d1331b3
ID		 1625 if (info->default_power1 < 0)
1626 info->default_power1 += 7;
f4450616 1627
8d1331b3 1628 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1629
1630 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1631 (info->default_power2 >= 0));
f4450616 1632
8d1331b3
ID		 1633 if (info->default_power2 < 0)
1634 info->default_power2 += 7;
f4450616 1635
8d1331b3 1636 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1637 } else {
8d1331b3
ID		 1638 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1639 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1640 }
1641
1642 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1643
1644 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1645 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1646 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1647 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1648
1649 udelay(200);
1650
1651 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1652 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1653 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1654 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1655
1656 udelay(200);
1657
1658 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1659 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1660 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1661 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1662}
1663
06855ef4
GW		 1664static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1665 struct ieee80211_conf *conf,
1666 struct rf_channel *rf,
1667 struct channel_info *info)
f4450616 1668{
3a1c0128 1669 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1670 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1671
1672 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1673
1674 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1675 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1676 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1677
1678 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1679 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1680 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1681
1682 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1683 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1684 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1685
5a673964 1686 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1687 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1688 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1689
1690 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1691 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1692 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1693 if (rt2x00_rt(rt2x00dev, RT3390)) {
1694 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1695 rt2x00dev->default_ant.rx_chain_num == 1);
1696 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1697 rt2x00dev->default_ant.tx_chain_num == 1);
1698 } else {
1699 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1700 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1701 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1702 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1703
1704 switch (rt2x00dev->default_ant.tx_chain_num) {
1705 case 1:
1706 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1707 /* fall through */
1708 case 2:
1709 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1710 break;
1711 }
1712
1713 switch (rt2x00dev->default_ant.rx_chain_num) {
1714 case 1:
1715 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1716 /* fall through */
1717 case 2:
1718 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1719 break;
1720 }
1721 }
1722 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1723
3e0c7643
SG		 1724 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1725 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1726 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1727 msleep(1);
1728 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1729 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1730
f4450616
BZ		 1731 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1732 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1733 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1734
f1f12f98
SG		 1735 if (rt2x00_rt(rt2x00dev, RT3390)) {
1736 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1737 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1738 } else {
3a1c0128
GW		 1739 if (conf_is_ht40(conf)) {
1740 calib_tx = drv_data->calibration_bw40;
1741 calib_rx = drv_data->calibration_bw40;
1742 } else {
1743 calib_tx = drv_data->calibration_bw20;
1744 calib_rx = drv_data->calibration_bw20;
1745 }
f1f12f98
SG		 1746 }
1747
1748 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1749 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1750 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1751
1752 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1753 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1754 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1755
71976907 1756 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1757 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1758 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1759
1760 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1761 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1762 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1763 msleep(1);
1764 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1765 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1766}
1767
872834df
GW		 1768static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1769 struct ieee80211_conf *conf,
1770 struct rf_channel *rf,
1771 struct channel_info *info)
1772{
3a1c0128 1773 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1774 u8 rfcsr;
1775 u32 reg;
1776
1777 if (rf->channel <= 14) {
5d137dff
GW		 1778 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1779 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1780 } else {
1781 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1782 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1783 }
1784
1785 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1786 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1787
1788 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1789 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1790 if (rf->channel <= 14)
1791 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1792 else
1793 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1794 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1795
1796 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1797 if (rf->channel <= 14)
1798 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1799 else
1800 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1801 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1802
1803 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1804 if (rf->channel <= 14) {
1805 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1806 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1807 info->default_power1);
872834df
GW		 1808 } else {
1809 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1810 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1811 (info->default_power1 & 0x3) |
1812 ((info->default_power1 & 0xC) << 1));
1813 }
1814 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1815
1816 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1817 if (rf->channel <= 14) {
1818 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1819 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1820 info->default_power2);
872834df
GW		 1821 } else {
1822 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1823 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1824 (info->default_power2 & 0x3) |
1825 ((info->default_power2 & 0xC) << 1));
1826 }
1827 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1828
1829 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1830 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1831 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1832 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1833 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1834 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1835 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1836 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1837 if (rf->channel <= 14) {
1838 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1839 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1840 }
1841 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1842 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1843 } else {
1844 switch (rt2x00dev->default_ant.tx_chain_num) {
1845 case 1:
1846 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1847 case 2:
1848 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1849 break;
1850 }
1851
1852 switch (rt2x00dev->default_ant.rx_chain_num) {
1853 case 1:
1854 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1855 case 2:
1856 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1857 break;
1858 }
1859 }
1860 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1861
1862 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1863 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1864 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1865
3a1c0128
GW		 1866 if (conf_is_ht40(conf)) {
1867 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1868 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1869 } else {
1870 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1871 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1872 }
872834df
GW		 1873
1874 if (rf->channel <= 14) {
1875 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1876 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1877 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1878 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1879 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1880 rfcsr = 0x4c;
1881 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1882 drv_data->txmixer_gain_24g);
1883 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1884 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1885 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1886 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1887 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1888 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1889 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1890 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1891 } else {
58b8ae14
GW		 1892 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1893 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1894 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1895 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1896 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1897 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1898 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1899 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1900 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1901 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1902 rfcsr = 0x7a;
1903 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1904 drv_data->txmixer_gain_5g);
1905 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1906 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1907 if (rf->channel <= 64) {
1908 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1909 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1910 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1911 } else if (rf->channel <= 128) {
1912 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1913 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1914 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1915 } else {
1916 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1917 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1918 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1919 }
1920 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1921 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1922 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1923 }
1924
1925 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1926 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1927 if (rf->channel <= 14)
1928 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1929 else
1930 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1931 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1932
1933 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1934 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1935 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1936}
60687ba7
RST		 1937
1938#define RT5390_POWER_BOUND 0x27
1939#define RT5390_FREQ_OFFSET_BOUND 0x5f
1940
1941static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1942 struct ieee80211_conf *conf,
1943 struct rf_channel *rf,
1944 struct channel_info *info)
1945{
1946 u8 rfcsr;
adde5882
GJ		 1947
1948 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1949 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1950 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1951 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1952 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1953
1954 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1955 if (info->default_power1 > RT5390_POWER_BOUND)
1956 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1957 else
1958 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1959 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1960
cff3d1f0
ZL		 1961 if (rt2x00_rt(rt2x00dev, RT5392)) {
1962 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
1963 if (info->default_power1 > RT5390_POWER_BOUND)
1964 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
1965 RT5390_POWER_BOUND);
1966 else
1967 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
1968 info->default_power2);
1969 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
1970 }
1971
adde5882 1972 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 1973 if (rt2x00_rt(rt2x00dev, RT5392)) {
1974 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1975 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1976 }
adde5882
GJ		 1977 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1978 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1979 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1980 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1981 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1982
1983 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1984 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1985 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1986 RT5390_FREQ_OFFSET_BOUND);
1987 else
1988 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1989 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1990
adde5882
GJ		 1991 if (rf->channel <= 14) {
1992 int idx = rf->channel-1;
1993
fdbc7b0a 1994 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 1995 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1996 /* r55/r59 value array of channel 1~14 */
1997 static const char r55_bt_rev[] = {0x83, 0x83,
1998 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1999 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2000 static const char r59_bt_rev[] = {0x0e, 0x0e,
2001 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2002 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2003
2004 rt2800_rfcsr_write(rt2x00dev, 55,
2005 r55_bt_rev[idx]);
2006 rt2800_rfcsr_write(rt2x00dev, 59,
2007 r59_bt_rev[idx]);
2008 } else {
2009 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2010 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2011 0x88, 0x88, 0x86, 0x85, 0x84};
2012
2013 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2014 }
2015 } else {
2016 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2017 static const char r55_nonbt_rev[] = {0x23, 0x23,
2018 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2019 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2020 static const char r59_nonbt_rev[] = {0x07, 0x07,
2021 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2022 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2023
2024 rt2800_rfcsr_write(rt2x00dev, 55,
2025 r55_nonbt_rev[idx]);
2026 rt2800_rfcsr_write(rt2x00dev, 59,
2027 r59_nonbt_rev[idx]);
2ed71884
JL		 2028 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2029 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2030 static const char r59_non_bt[] = {0x8f, 0x8f,
2031 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2032 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2033
2034 rt2800_rfcsr_write(rt2x00dev, 59,
2035 r59_non_bt[idx]);
2036 }
2037 }
2038 }
2039
2040 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2041 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2042 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2043 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2044
2045 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2046 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2047 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 2048}
2049
f4450616
BZ		 2050static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2051 struct ieee80211_conf *conf,
2052 struct rf_channel *rf,
2053 struct channel_info *info)
2054{
2055 u32 reg;
2056 unsigned int tx_pin;
2057 u8 bbp;
2058
46323e11 2059 if (rf->channel <= 14) {
8d1331b3
ID		 2060 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2061 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2062 } else {
8d1331b3
ID		 2063 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2064 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2065 }
2066
5aa57015
GW		 2067 switch (rt2x00dev->chip.rf) {
2068 case RF2020:
2069 case RF3020:
2070 case RF3021:
2071 case RF3022:
2072 case RF3320:
06855ef4 2073 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2074 break;
2075 case RF3052:
872834df 2076 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2077 break;
ccf91bd6 2078 case RF5360:
5aa57015 2079 case RF5370:
2ed71884 2080 case RF5372:
5aa57015 2081 case RF5390:
cff3d1f0 2082 case RF5392:
adde5882 2083 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2084 break;
2085 default:
06855ef4 2086 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2087 }
f4450616
BZ		 2088
2089 /*
2090 * Change BBP settings
2091 */
2092 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2093 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2094 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2095 rt2800_bbp_write(rt2x00dev, 86, 0);
2096
2097 if (rf->channel <= 14) {
2ed71884
JL		 2098 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2099 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2100 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2101 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2102 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2103 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2104 } else {
2105 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2106 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2107 }
f4450616
BZ		 2108 }
2109 } else {
872834df
GW		 2110 if (rt2x00_rt(rt2x00dev, RT3572))
2111 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2112 else
2113 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2114
7dab73b3 2115 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2116 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2117 else
2118 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2119 }
2120
2121 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2122 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2123 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2124 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2125 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2126
872834df
GW		 2127 if (rt2x00_rt(rt2x00dev, RT3572))
2128 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2129
f4450616
BZ		 2130 tx_pin = 0;
2131
2132 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2133 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2134 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2135 rf->channel > 14);
2136 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2137 rf->channel <= 14);
f4450616
BZ		 2138 }
2139
2140 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2141 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2142 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2143 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2144 }
2145
2146 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2147 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2148 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2149 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2150 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2151 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2152 else
2153 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2154 rf->channel <= 14);
f4450616
BZ		 2155 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2156
2157 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2158
872834df
GW		 2159 if (rt2x00_rt(rt2x00dev, RT3572))
2160 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2161
f4450616
BZ		 2162 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2163 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2164 rt2800_bbp_write(rt2x00dev, 4, bbp);
2165
2166 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2167 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2168 rt2800_bbp_write(rt2x00dev, 3, bbp);
2169
8d0c9b65 2170 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2171 if (conf_is_ht40(conf)) {
2172 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2173 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2174 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2175 } else {
2176 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2177 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2178 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2179 }
2180 }
2181
2182 msleep(1);
977206d7
HS		 2183
2184 /*
2185 * Clear channel statistic counters
2186 */
2187 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2188 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2189 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 2190}
2191
9e33a355
HS		 2192static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2193{
2194 u8 tssi_bounds[9];
2195 u8 current_tssi;
2196 u16 eeprom;
2197 u8 step;
2198 int i;
2199
2200 /*
2201 * Read TSSI boundaries for temperature compensation from
2202 * the EEPROM.
2203 *
2204 * Array idx 0 1 2 3 4 5 6 7 8
2205 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2206 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2207 */
2208 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2209 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2210 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2211 EEPROM_TSSI_BOUND_BG1_MINUS4);
2212 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2213 EEPROM_TSSI_BOUND_BG1_MINUS3);
2214
2215 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2216 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2217 EEPROM_TSSI_BOUND_BG2_MINUS2);
2218 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2219 EEPROM_TSSI_BOUND_BG2_MINUS1);
2220
2221 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2222 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2223 EEPROM_TSSI_BOUND_BG3_REF);
2224 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2225 EEPROM_TSSI_BOUND_BG3_PLUS1);
2226
2227 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2228 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2229 EEPROM_TSSI_BOUND_BG4_PLUS2);
2230 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2231 EEPROM_TSSI_BOUND_BG4_PLUS3);
2232
2233 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2234 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2235 EEPROM_TSSI_BOUND_BG5_PLUS4);
2236
2237 step = rt2x00_get_field16(eeprom,
2238 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2239 } else {
2240 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2241 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2242 EEPROM_TSSI_BOUND_A1_MINUS4);
2243 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2244 EEPROM_TSSI_BOUND_A1_MINUS3);
2245
2246 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2247 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2248 EEPROM_TSSI_BOUND_A2_MINUS2);
2249 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2250 EEPROM_TSSI_BOUND_A2_MINUS1);
2251
2252 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2253 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2254 EEPROM_TSSI_BOUND_A3_REF);
2255 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2256 EEPROM_TSSI_BOUND_A3_PLUS1);
2257
2258 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2259 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2260 EEPROM_TSSI_BOUND_A4_PLUS2);
2261 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2262 EEPROM_TSSI_BOUND_A4_PLUS3);
2263
2264 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2265 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2266 EEPROM_TSSI_BOUND_A5_PLUS4);
2267
2268 step = rt2x00_get_field16(eeprom,
2269 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2270 }
2271
2272 /*
2273 * Check if temperature compensation is supported.
2274 */
2275 if (tssi_bounds[4] == 0xff)
2276 return 0;
2277
2278 /*
2279 * Read current TSSI (BBP 49).
2280 */
2281 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2282
2283 /*
2284 * Compare TSSI value (BBP49) with the compensation boundaries
2285 * from the EEPROM and increase or decrease tx power.
2286 */
2287 for (i = 0; i <= 3; i++) {
2288 if (current_tssi > tssi_bounds[i])
2289 break;
2290 }
2291
2292 if (i == 4) {
2293 for (i = 8; i >= 5; i--) {
2294 if (current_tssi < tssi_bounds[i])
2295 break;
2296 }
2297 }
2298
2299 return (i - 4) * step;
2300}
2301
e90c54b2
RJH		 2302static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2303 enum ieee80211_band band)
2304{
2305 u16 eeprom;
2306 u8 comp_en;
2307 u8 comp_type;
75faae8b 2308 int comp_value = 0;
e90c54b2
RJH		 2309
2310 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2311
75faae8b
HS		 2312 /*
2313 * HT40 compensation not required.
2314 */
2315 if (eeprom == 0xffff ||
2316 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2317 return 0;
2318
2319 if (band == IEEE80211_BAND_2GHZ) {
2320 comp_en = rt2x00_get_field16(eeprom,
2321 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2322 if (comp_en) {
2323 comp_type = rt2x00_get_field16(eeprom,
2324 EEPROM_TXPOWER_DELTA_TYPE_2G);
2325 comp_value = rt2x00_get_field16(eeprom,
2326 EEPROM_TXPOWER_DELTA_VALUE_2G);
2327 if (!comp_type)
2328 comp_value = -comp_value;
2329 }
2330 } else {
2331 comp_en = rt2x00_get_field16(eeprom,
2332 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2333 if (comp_en) {
2334 comp_type = rt2x00_get_field16(eeprom,
2335 EEPROM_TXPOWER_DELTA_TYPE_5G);
2336 comp_value = rt2x00_get_field16(eeprom,
2337 EEPROM_TXPOWER_DELTA_VALUE_5G);
2338 if (!comp_type)
2339 comp_value = -comp_value;
2340 }
2341 }
2342
2343 return comp_value;
2344}
2345
fa71a160
HS		 2346static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2347 enum ieee80211_band band, int power_level,
2348 u8 txpower, int delta)
e90c54b2
RJH		 2349{
2350 u32 reg;
2351 u16 eeprom;
2352 u8 criterion;
2353 u8 eirp_txpower;
2354 u8 eirp_txpower_criterion;
2355 u8 reg_limit;
e90c54b2
RJH		 2356
2357 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2358 return txpower;
2359
7dab73b3 2360 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2361 /*
2362 * Check if eirp txpower exceed txpower_limit.
2363 * We use OFDM 6M as criterion and its eirp txpower
2364 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2365 * .11b data rate need add additional 4dbm
2366 * when calculating eirp txpower.
2367 */
2368 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2369 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2370
2371 rt2x00_eeprom_read(rt2x00dev,
2372 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2373
2374 if (band == IEEE80211_BAND_2GHZ)
2375 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2376 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2377 else
2378 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2379 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2380
2381 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2382 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2383
2384 reg_limit = (eirp_txpower > power_level) ?
2385 (eirp_txpower - power_level) : 0;
2386 } else
2387 reg_limit = 0;
2388
2af242e1 2389 return txpower + delta - reg_limit;
e90c54b2
RJH		 2390}
2391
f4450616 2392static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2393 enum ieee80211_band band,
2394 int power_level)
f4450616 2395{
5e846004 2396 u8 txpower;
5e846004 2397 u16 eeprom;
e90c54b2 2398 int i, is_rate_b;
f4450616 2399 u32 reg;
f4450616 2400 u8 r1;
5e846004 2401 u32 offset;
2af242e1
HS		 2402 int delta;
2403
2404 /*
2405 * Calculate HT40 compensation delta
2406 */
2407 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2408
9e33a355
HS		 2409 /*
2410 * calculate temperature compensation delta
2411 */
2412 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2413
5e846004 2414 /*
e90c54b2 2415 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2416 */
f4450616 2417 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2418 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2419 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2420 offset = TX_PWR_CFG_0;
2421
2422 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2423 /* just to be safe */
2424 if (offset > TX_PWR_CFG_4)
2425 break;
2426
2427 rt2800_register_read(rt2x00dev, offset, &reg);
2428
2429 /* read the next four txpower values */
2430 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2431 &eeprom);
2432
e90c54b2
RJH		 2433 is_rate_b = i ? 0 : 1;
2434 /*
2435 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2436 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2437 * TX_PWR_CFG_4: unknown
2438 */
5e846004
HS		 2439 txpower = rt2x00_get_field16(eeprom,
2440 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2441 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2442 power_level, txpower, delta);
e90c54b2 2443 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2444
e90c54b2
RJH		 2445 /*
2446 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2447 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2448 * TX_PWR_CFG_4: unknown
2449 */
5e846004
HS		 2450 txpower = rt2x00_get_field16(eeprom,
2451 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2452 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2453 power_level, txpower, delta);
e90c54b2 2454 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2455
e90c54b2
RJH		 2456 /*
2457 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2458 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2459 * TX_PWR_CFG_4: unknown
2460 */
5e846004
HS		 2461 txpower = rt2x00_get_field16(eeprom,
2462 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2463 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2464 power_level, txpower, delta);
e90c54b2 2465 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2466
e90c54b2
RJH		 2467 /*
2468 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2469 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2470 * TX_PWR_CFG_4: unknown
2471 */
5e846004
HS		 2472 txpower = rt2x00_get_field16(eeprom,
2473 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2474 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2475 power_level, txpower, delta);
e90c54b2 2476 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2477
2478 /* read the next four txpower values */
2479 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2480 &eeprom);
2481
e90c54b2
RJH		 2482 is_rate_b = 0;
2483 /*
2484 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2485 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2486 * TX_PWR_CFG_4: unknown
2487 */
5e846004
HS		 2488 txpower = rt2x00_get_field16(eeprom,
2489 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2490 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2491 power_level, txpower, delta);
e90c54b2 2492 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2493
e90c54b2
RJH		 2494 /*
2495 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2496 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2497 * TX_PWR_CFG_4: unknown
2498 */
5e846004
HS		 2499 txpower = rt2x00_get_field16(eeprom,
2500 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2501 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2502 power_level, txpower, delta);
e90c54b2 2503 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2504
e90c54b2
RJH		 2505 /*
2506 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2507 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2508 * TX_PWR_CFG_4: unknown
2509 */
5e846004
HS		 2510 txpower = rt2x00_get_field16(eeprom,
2511 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2512 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2513 power_level, txpower, delta);
e90c54b2 2514 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2515
e90c54b2
RJH		 2516 /*
2517 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2518 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2519 * TX_PWR_CFG_4: unknown
2520 */
5e846004
HS		 2521 txpower = rt2x00_get_field16(eeprom,
2522 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2523 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2524 power_level, txpower, delta);
e90c54b2 2525 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2526
2527 rt2800_register_write(rt2x00dev, offset, reg);
2528
2529 /* next TX_PWR_CFG register */
2530 offset += 4;
2531 }
f4450616
BZ		 2532}
2533
9e33a355
HS		 2534void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2535{
2536 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2537 rt2x00dev->tx_power);
2538}
2539EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2540
2e9c43dd
JL		 2541void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2542{
2543 u32 tx_pin;
2544 u8 rfcsr;
2545
2546 /*
2547 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2548 * designed to be controlled in oscillation frequency by a voltage
2549 * input. Maybe the temperature will affect the frequency of
2550 * oscillation to be shifted. The VCO calibration will be called
2551 * periodically to adjust the frequency to be precision.
2552 */
2553
2554 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2555 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2556 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2557
2558 switch (rt2x00dev->chip.rf) {
2559 case RF2020:
2560 case RF3020:
2561 case RF3021:
2562 case RF3022:
2563 case RF3320:
2564 case RF3052:
2565 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2566 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2567 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2568 break;
ccf91bd6 2569 case RF5360:
2e9c43dd
JL		 2570 case RF5370:
2571 case RF5372:
2572 case RF5390:
cff3d1f0 2573 case RF5392:
2e9c43dd
JL		 2574 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2575 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2576 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2577 break;
2578 default:
2579 return;
2580 }
2581
2582 mdelay(1);
2583
2584 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2585 if (rt2x00dev->rf_channel <= 14) {
2586 switch (rt2x00dev->default_ant.tx_chain_num) {
2587 case 3:
2588 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2589 /* fall through */
2590 case 2:
2591 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2592 /* fall through */
2593 case 1:
2594 default:
2595 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2596 break;
2597 }
2598 } else {
2599 switch (rt2x00dev->default_ant.tx_chain_num) {
2600 case 3:
2601 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2602 /* fall through */
2603 case 2:
2604 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2605 /* fall through */
2606 case 1:
2607 default:
2608 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2609 break;
2610 }
2611 }
2612 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2613
2614}
2615EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2616
f4450616
BZ		 2617static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2618 struct rt2x00lib_conf *libconf)
2619{
2620 u32 reg;
2621
2622 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2623 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2624 libconf->conf->short_frame_max_tx_count);
2625 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2626 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2627 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2628}
2629
2630static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2631 struct rt2x00lib_conf *libconf)
2632{
2633 enum dev_state state =
2634 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2635 STATE_SLEEP : STATE_AWAKE;
2636 u32 reg;
2637
2638 if (state == STATE_SLEEP) {
2639 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2640
2641 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2642 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2643 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2644 libconf->conf->listen_interval - 1);
2645 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2646 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2647
2648 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2649 } else {
f4450616
BZ		 2650 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2651 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2652 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2653 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2654 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2655
2656 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2657 }
2658}
2659
2660void rt2800_config(struct rt2x00_dev *rt2x00dev,
2661 struct rt2x00lib_conf *libconf,
2662 const unsigned int flags)
2663{
2664 /* Always recalculate LNA gain before changing configuration */
2665 rt2800_config_lna_gain(rt2x00dev, libconf);
2666
e90c54b2 2667 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2668 rt2800_config_channel(rt2x00dev, libconf->conf,
2669 &libconf->rf, &libconf->channel);
9e33a355
HS		 2670 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2671 libconf->conf->power_level);
e90c54b2 2672 }
f4450616 2673 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2674 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2675 libconf->conf->power_level);
f4450616
BZ		 2676 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2677 rt2800_config_retry_limit(rt2x00dev, libconf);
2678 if (flags & IEEE80211_CONF_CHANGE_PS)
2679 rt2800_config_ps(rt2x00dev, libconf);
2680}
2681EXPORT_SYMBOL_GPL(rt2800_config);
2682
2683/*
2684 * Link tuning
2685 */
2686void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2687{
2688 u32 reg;
2689
2690 /*
2691 * Update FCS error count from register.
2692 */
2693 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2694 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2695}
2696EXPORT_SYMBOL_GPL(rt2800_link_stats);
2697
2698static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2699{
2700 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2701 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2702 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2703 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 2704 rt2x00_rt(rt2x00dev, RT3390) ||
2ed71884
JL		 2705 rt2x00_rt(rt2x00dev, RT5390) ||
2706 rt2x00_rt(rt2x00dev, RT5392))
f4450616
BZ		 2707 return 0x1c + (2 * rt2x00dev->lna_gain);
2708 else
2709 return 0x2e + rt2x00dev->lna_gain;
2710 }
2711
2712 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2713 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2714 else
2715 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2716}
2717
2718static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2719 struct link_qual *qual, u8 vgc_level)
2720{
2721 if (qual->vgc_level != vgc_level) {
2722 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2723 qual->vgc_level = vgc_level;
2724 qual->vgc_level_reg = vgc_level;
2725 }
2726}
2727
2728void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2729{
2730 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2731}
2732EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2733
2734void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2735 const u32 count)
2736{
8d0c9b65 2737 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2738 return;
2739
2740 /*
2741 * When RSSI is better then -80 increase VGC level with 0x10
2742 */
2743 rt2800_set_vgc(rt2x00dev, qual,
2744 rt2800_get_default_vgc(rt2x00dev) +
2745 ((qual->rssi > -80) * 0x10));
2746}
2747EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2748
2749/*
2750 * Initialization functions.
2751 */
b9a07ae9 2752static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2753{
2754 u32 reg;
d5385bfc 2755 u16 eeprom;
fcf51541 2756 unsigned int i;
e3a896b9 2757 int ret;
fcf51541 2758
f7b395e9 2759 rt2800_disable_wpdma(rt2x00dev);
a9dce149 2760
e3a896b9
GW		 2761 ret = rt2800_drv_init_registers(rt2x00dev);
2762 if (ret)
2763 return ret;
fcf51541
BZ		 2764
2765 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2766 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2767 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2768 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2769 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2770 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2771
2772 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2773 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2774 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2775 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2776 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2777 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2778
2779 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2780 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2781
2782 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2783
2784 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2785 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2786 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2787 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2788 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2789 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2790 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2791 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2792
a9dce149
GW		 2793 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2794
2795 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2796 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2797 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2798 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2799
64522957 2800 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2801 rt2x00_rt(rt2x00dev, RT3090) ||
2802 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2803 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2805 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2806 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2807 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2808 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2809 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2810 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2811 0x0000002c);
2812 else
2813 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2814 0x0000000f);
2815 } else {
2816 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2817 }
d5385bfc 2818 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2819 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2820
2821 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2822 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2823 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2824 } else {
2825 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2826 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2827 }
c295a81d
HS		 2828 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2829 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2830 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 2831 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
872834df
GW		 2832 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2833 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2834 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884
JL		 2835 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2836 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2837 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2838 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2839 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2840 } else {
2841 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2842 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2843 }
2844
2845 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2846 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2847 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2848 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2849 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2850 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2851 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2852 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2853 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2854 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2855
2856 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2857 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2858 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2859 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2860 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2861
2862 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2863 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2864 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2865 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2866 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2867 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2868 else
2869 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2870 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2871 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2872 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2873
a9dce149
GW		 2874 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2875 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2876 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2877 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2878 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2879 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2880 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2881 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2882 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2883
fcf51541
BZ		 2884 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2885
a9dce149
GW		 2886 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2887 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2888 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2889 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2890 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2891 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2892 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2893 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2894
fcf51541
BZ		 2895 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2896 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2897 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2898 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2899 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2900 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2901 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2902 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2903 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2904
2905 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2906 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2907 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2908 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2909 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2910 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2911 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2912 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2913 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2914 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2915 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2916 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2917
2918 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2919 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2920 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2921 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2922 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2923 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2924 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2925 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2926 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2927 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2928 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2929 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2930
2931 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2932 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2933 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2934 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2935 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2936 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2937 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2938 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2939 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2940 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2941 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2942 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2943
2944 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2945 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2946 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2947 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2948 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2949 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2950 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2951 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2952 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2953 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2954 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2955 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2956
2957 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2958 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2959 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2960 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2961 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2962 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2963 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2964 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2965 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2966 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2967 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2968 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2969
2970 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2971 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2972 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2973 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2974 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2975 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2976 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2977 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2978 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2979 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2980 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2981 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2982
cea90e55 2983 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2984 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2985
2986 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2987 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2988 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2989 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2990 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2991 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2992 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2993 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2994 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2995 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2996 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2997 }
2998
961621ab
HS		 2999 /*
3000 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3001 * although it is reserved.
3002 */
3003 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3004 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3005 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3006 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3007 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3008 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3009 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3010 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3011 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3012 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3013 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3014 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3015
fcf51541
BZ		 3016 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3017
3018 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3019 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3020 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3021 IEEE80211_MAX_RTS_THRESHOLD);
3022 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3023 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3024
3025 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3026
a21c2ab4
HS		 3027 /*
3028 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3029 * time should be set to 16. However, the original Ralink driver uses
3030 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3031 * connection problems with 11g + CTS protection. Hence, use the same
3032 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3033 */
a9dce149 3034 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3035 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3036 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3037 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3038 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3039 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3040 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3041
fcf51541
BZ		 3042 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3043
3044 /*
3045 * ASIC will keep garbage value after boot, clear encryption keys.
3046 */
3047 for (i = 0; i < 4; i++)
3048 rt2800_register_write(rt2x00dev,
3049 SHARED_KEY_MODE_ENTRY(i), 0);
3050
3051 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3052 rt2800_config_wcid(rt2x00dev, NULL, i);
3053 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3054 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3055 }
3056
3057 /*
3058 * Clear all beacons
fcf51541 3059 */
69cf36a4
HS		 3060 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3061 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3062 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3063 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3064 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3065 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3066 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3067 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3068
cea90e55 3069 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3070 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3071 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3072 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3073 } else if (rt2x00_is_pcie(rt2x00dev)) {
3074 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3075 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3076 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3077 }
3078
3079 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3080 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3081 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3082 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3083 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3084 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3085 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3086 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3087 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3088 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3089
3090 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3091 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3092 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3093 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3094 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3095 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3096 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3097 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3098 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3099 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3100
3101 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3102 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3103 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3104 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3105 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3106 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3107 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3108 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3109 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3110 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3111
3112 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3113 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3114 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3115 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3116 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3117 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3118
47ee3eb1
HS		 3119 /*
3120 * Do not force the BA window size, we use the TXWI to set it
3121 */
3122 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3123 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3124 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3125 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3126
fcf51541
BZ		 3127 /*
3128 * We must clear the error counters.
3129 * These registers are cleared on read,
3130 * so we may pass a useless variable to store the value.
3131 */
3132 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3133 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3134 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3135 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3136 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3137 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3138
9f926fb5
HS		 3139 /*
3140 * Setup leadtime for pre tbtt interrupt to 6ms
3141 */
3142 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3143 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3144 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3145
977206d7
HS		 3146 /*
3147 * Set up channel statistics timer
3148 */
3149 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3150 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3151 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3152 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3153 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3154 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3155 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3156
fcf51541
BZ		 3157 return 0;
3158}
fcf51541
BZ		 3159
3160static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3161{
3162 unsigned int i;
3163 u32 reg;
3164
3165 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3166 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3167 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3168 return 0;
3169
3170 udelay(REGISTER_BUSY_DELAY);
3171 }
3172
3173 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3174 return -EACCES;
3175}
3176
3177static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3178{
3179 unsigned int i;
3180 u8 value;
3181
3182 /*
3183 * BBP was enabled after firmware was loaded,
3184 * but we need to reactivate it now.
3185 */
3186 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3187 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3188 msleep(1);
3189
3190 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3191 rt2800_bbp_read(rt2x00dev, 0, &value);
3192 if ((value != 0xff) && (value != 0x00))
3193 return 0;
3194 udelay(REGISTER_BUSY_DELAY);
3195 }
3196
3197 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3198 return -EACCES;
3199}
3200
b9a07ae9 3201static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3202{
3203 unsigned int i;
3204 u16 eeprom;
3205 u8 reg_id;
3206 u8 value;
3207
3208 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3209 rt2800_wait_bbp_ready(rt2x00dev)))
3210 return -EACCES;
3211
2ed71884
JL		 3212 if (rt2x00_rt(rt2x00dev, RT5390) ||
3213 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3214 rt2800_bbp_read(rt2x00dev, 4, &value);
3215 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3216 rt2800_bbp_write(rt2x00dev, 4, value);
3217 }
60687ba7 3218
adde5882 3219 if (rt2800_is_305x_soc(rt2x00dev) ||
872834df 3220 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3221 rt2x00_rt(rt2x00dev, RT5390) ||
3222 rt2x00_rt(rt2x00dev, RT5392))
baff8006
HS		 3223 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3224
fcf51541
BZ		 3225 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3226 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3227
2ed71884
JL		 3228 if (rt2x00_rt(rt2x00dev, RT5390) ||
3229 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3230 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3231
a9dce149
GW		 3232 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3233 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3234 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2ed71884
JL		 3235 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3236 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3237 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3238 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3239 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3240 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3241 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3242 } else {
3243 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3244 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3245 }
3246
fcf51541 3247 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3248
d5385bfc 3249 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3250 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3251 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3252 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3253 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3254 rt2x00_rt(rt2x00dev, RT5390) ||
3255 rt2x00_rt(rt2x00dev, RT5392)) {
8cdd15e0
GW		 3256 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3257 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3258 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3259 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3260 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3261 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 3262 } else {
3263 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3264 }
3265
fcf51541 3266 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2ed71884
JL		 3267 if (rt2x00_rt(rt2x00dev, RT5390) ||
3268 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3269 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3270 else
3271 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3272
5ed8f458 3273 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3274 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2ed71884
JL		 3275 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3276 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3277 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3278 else
3279 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3280
2ed71884
JL		 3281 if (rt2x00_rt(rt2x00dev, RT5390) ||
3282 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3283 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3284 else
3285 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3286
2ed71884
JL		 3287 if (rt2x00_rt(rt2x00dev, RT5392))
3288 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3289
fcf51541 3290 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3291
2ed71884
JL		 3292 if (rt2x00_rt(rt2x00dev, RT5390) ||
3293 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3294 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3295 else
3296 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3297
2ed71884
JL		 3298 if (rt2x00_rt(rt2x00dev, RT5392)) {
3299 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3300 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3301 }
3302
d5385bfc 3303 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3304 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3305 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3306 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
872834df 3307 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3308 rt2x00_rt(rt2x00dev, RT5390) ||
2ed71884 3309 rt2x00_rt(rt2x00dev, RT5392) ||
baff8006 3310 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3311 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3312 else
3313 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3314
2ed71884
JL		 3315 if (rt2x00_rt(rt2x00dev, RT5390) ||
3316 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3317 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3318
baff8006
HS		 3319 if (rt2800_is_305x_soc(rt2x00dev))
3320 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2ed71884
JL		 3321 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3322 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3323 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3324 else
3325 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3326
adde5882
GJ		 3327 if (rt2x00_rt(rt2x00dev, RT5390))
3328 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2ed71884
JL		 3329 else if (rt2x00_rt(rt2x00dev, RT5392))
3330 rt2800_bbp_write(rt2x00dev, 106, 0x12);
adde5882
GJ		 3331 else
3332 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3333
2ed71884
JL		 3334 if (rt2x00_rt(rt2x00dev, RT5390) ||
3335 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3336 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3337
2ed71884
JL		 3338 if (rt2x00_rt(rt2x00dev, RT5392)) {
3339 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3340 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3341 }
3342
64522957 3343 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3344 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3345 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3346 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3347 rt2x00_rt(rt2x00dev, RT5390) ||
3348 rt2x00_rt(rt2x00dev, RT5392)) {
d5385bfc 3349 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3350
38c8a566
RJH		 3351 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3352 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3353 value |= 0x20;
38c8a566 3354 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3355 value &= ~0x02;
fcf51541 3356
d5385bfc 3357 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3358 }
3359
2ed71884
JL		 3360 if (rt2x00_rt(rt2x00dev, RT5390) ||
3361 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3362 int ant, div_mode;
3363
3364 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3365 div_mode = rt2x00_get_field16(eeprom,
3366 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3367 ant = (div_mode == 3) ? 1 : 0;
3368
3369 /* check if this is a Bluetooth combo card */
fdbc7b0a 3370 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3371 u32 reg;
3372
3373 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3374 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3375 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3376 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3377 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3378 if (ant == 0)
3379 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3380 else if (ant == 1)
3381 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3382 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3383 }
3384
0586a11b
AA		 3385 /* This chip has hardware antenna diversity*/
3386 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3387 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3388 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3389 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3390 }
3391
adde5882
GJ		 3392 rt2800_bbp_read(rt2x00dev, 152, &value);
3393 if (ant == 0)
3394 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3395 else
3396 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3397 rt2800_bbp_write(rt2x00dev, 152, value);
3398
3399 /* Init frequency calibration */
3400 rt2800_bbp_write(rt2x00dev, 142, 1);
3401 rt2800_bbp_write(rt2x00dev, 143, 57);
3402 }
fcf51541
BZ		 3403
3404 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3405 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3406
3407 if (eeprom != 0xffff && eeprom != 0x0000) {
3408 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3409 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3410 rt2800_bbp_write(rt2x00dev, reg_id, value);
3411 }
3412 }
3413
3414 return 0;
3415}
fcf51541
BZ		 3416
3417static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3418 bool bw40, u8 rfcsr24, u8 filter_target)
3419{
3420 unsigned int i;
3421 u8 bbp;
3422 u8 rfcsr;
3423 u8 passband;
3424 u8 stopband;
3425 u8 overtuned = 0;
3426
3427 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3428
3429 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3430 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3431 rt2800_bbp_write(rt2x00dev, 4, bbp);
3432
80d184e6
RJH		 3433 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3434 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3435 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3436
fcf51541
BZ		 3437 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3438 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3439 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3440
3441 /*
3442 * Set power & frequency of passband test tone
3443 */
3444 rt2800_bbp_write(rt2x00dev, 24, 0);
3445
3446 for (i = 0; i < 100; i++) {
3447 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3448 msleep(1);
3449
3450 rt2800_bbp_read(rt2x00dev, 55, &passband);
3451 if (passband)
3452 break;
3453 }
3454
3455 /*
3456 * Set power & frequency of stopband test tone
3457 */
3458 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3459
3460 for (i = 0; i < 100; i++) {
3461 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3462 msleep(1);
3463
3464 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3465
3466 if ((passband - stopband) <= filter_target) {
3467 rfcsr24++;
3468 overtuned += ((passband - stopband) == filter_target);
3469 } else
3470 break;
3471
3472 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3473 }
3474
3475 rfcsr24 -= !!overtuned;
3476
3477 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3478 return rfcsr24;
3479}
3480
b9a07ae9 3481static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 3482{
3a1c0128 3483 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541
BZ		 3484 u8 rfcsr;
3485 u8 bbp;
8cdd15e0
GW		 3486 u32 reg;
3487 u16 eeprom;
fcf51541 3488
d5385bfc 3489 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3490 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3491 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3492 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3493 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3494 !rt2x00_rt(rt2x00dev, RT5390) &&
2ed71884 3495 !rt2x00_rt(rt2x00dev, RT5392) &&
baff8006 3496 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3497 return 0;
3498
fcf51541
BZ		 3499 /*
3500 * Init RF calibration.
3501 */
2ed71884
JL		 3502 if (rt2x00_rt(rt2x00dev, RT5390) ||
3503 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3504 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3505 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3506 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3507 msleep(1);
3508 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3509 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3510 } else {
3511 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3512 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3513 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3514 msleep(1);
3515 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3516 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3517 }
fcf51541 3518
d5385bfc 3519 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3520 rt2x00_rt(rt2x00dev, RT3071) ||
3521 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3522 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3523 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3524 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3525 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3526 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3527 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3528 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3529 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3530 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3531 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3532 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3533 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3534 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3535 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3536 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3537 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3538 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3539 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3540 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3541 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3542 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3543 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3544 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3545 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3546 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3547 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3548 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3549 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3550 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3551 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3552 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3553 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3554 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3555 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3556 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3557 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3558 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3559 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3560 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3561 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3562 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3563 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3564 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3565 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3566 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3567 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3568 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3569 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3570 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3571 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3572 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3573 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3574 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3575 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3576 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3577 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3578 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3579 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3580 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3581 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3582 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3583 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3584 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3585 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3586 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3587 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3588 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3589 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3590 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3591 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3592 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3593 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3594 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3595 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3596 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3597 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3598 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3599 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3600 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3601 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3602 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3603 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3604 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3605 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 3606 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3607 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3608 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3609 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3610 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3611 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3612 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3613 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3614 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3615 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3616 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3617 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3618 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3619 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3620 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3621 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3622 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3623 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3624 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3625 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3626 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3627 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3628 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3629 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3630 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3631 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3632 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3633 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3634 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3635 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3636 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3637 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3638 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3639 return 0;
adde5882
GJ		 3640 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3641 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3642 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3643 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3644 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3645 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3646 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3647 else
3648 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3649 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3650 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3651 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3652 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3653 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3654 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3655 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3656 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3657 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3658 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3659
3660 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3661 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3662 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3663 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3664 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3665 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3666 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3667 else
3668 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3669 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3670 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3671 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3672 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3673
3674 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3675 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3676 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3677 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3678 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3679 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3680 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3681 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3682 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3683 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3684
3685 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3686 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3687 else
3688 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3689 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3690 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3691 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3692 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3693 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3694 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3695 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3696 else
3697 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3698 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3699 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3700 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3701
3702 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3703 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3704 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3705 else
3706 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3707 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3708 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3709 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3710 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3711 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3712 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3713
3714 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3715 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3716 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3717 else
3718 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3719 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3720 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2ed71884
JL		 3721 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3722 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3723 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3724 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3725 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3726 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3727 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3728 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3729 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3730 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3731 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3732 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3733 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3734 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3735 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3736 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3737 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3738 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3739 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3740 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3741 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3742 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3743 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3744 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3745 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3746 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3747 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3748 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3749 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3750 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3751 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3752 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3753 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3754 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3755 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3756 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3757 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3758 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3759 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3760 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3761 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3762 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3763 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3764 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3765 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3766 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3767 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3768 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3769 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3770 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3771 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3772 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3773 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3774 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3775 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3776 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3777 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3778 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3779 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3780 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8cdd15e0
GW		 3781 }
3782
3783 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3784 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3785 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3786 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3787 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3788 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3789 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3790 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3791
d5385bfc
GW		 3792 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3793 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3794 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3795
d5385bfc
GW		 3796 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3797 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3798 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3799 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3800 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3801 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3802 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3803 else
3804 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3805 }
3806 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3807
3808 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3809 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3810 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3811 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3812 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3813 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3814 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 3815 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3816 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3817 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3818 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3819
3820 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3821 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3822 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3823 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3824 msleep(1);
3825 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3826 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3827 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 3828 }
3829
3830 /*
3831 * Set RX Filter calibration for 20MHz and 40MHz
3832 */
8cdd15e0 3833 if (rt2x00_rt(rt2x00dev, RT3070)) {
3a1c0128 3834 drv_data->calibration_bw20 =
8cdd15e0 3835 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3a1c0128 3836 drv_data->calibration_bw40 =
8cdd15e0 3837 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3838 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3839 rt2x00_rt(rt2x00dev, RT3090) ||
872834df
GW		 3840 rt2x00_rt(rt2x00dev, RT3390) ||
3841 rt2x00_rt(rt2x00dev, RT3572)) {
3a1c0128 3842 drv_data->calibration_bw20 =
d5385bfc 3843 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3a1c0128 3844 drv_data->calibration_bw40 =
d5385bfc 3845 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3846 }
fcf51541 3847
5d137dff
GW		 3848 /*
3849 * Save BBP 25 & 26 values for later use in channel switching
3850 */
3851 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3852 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3853
2ed71884
JL		 3854 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3855 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3856 /*
3857 * Set back to initial state
3858 */
3859 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3860
adde5882
GJ		 3861 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3862 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3863 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3864
adde5882
GJ		 3865 /*
3866 * Set BBP back to BW20
3867 */
3868 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3869 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3870 rt2800_bbp_write(rt2x00dev, 4, bbp);
3871 }
fcf51541 3872
d5385bfc 3873 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3874 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3875 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3876 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3877 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3878
3879 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3880 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3881 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3882
2ed71884
JL		 3883 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3884 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3885 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3886 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3887 if (rt2x00_rt(rt2x00dev, RT3070) ||
3888 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3889 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3890 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3891 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3892 &rt2x00dev->cap_flags))
adde5882
GJ		 3893 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3894 }
77c06c2c
GW		 3895 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3896 drv_data->txmixer_gain_24g);
adde5882
GJ		 3897 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3898 }
8cdd15e0 3899
64522957
GW		 3900 if (rt2x00_rt(rt2x00dev, RT3090)) {
3901 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3902
80d184e6 3903 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3904 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3905 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3906 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3907 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3908 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3909
3910 rt2800_bbp_write(rt2x00dev, 138, bbp);
3911 }
3912
3913 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3914 rt2x00_rt(rt2x00dev, RT3090) ||
3915 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3916 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3917 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3918 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3919 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3920 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3921 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3922 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3923
3924 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3925 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3926 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3927
3928 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3929 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3930 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3931
3932 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3933 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3934 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3935 }
3936
80d184e6 3937 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3938 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3939 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3940 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3941 else
3942 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3943 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3944 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3945 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3946 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3947 }
3948
2ed71884
JL		 3949 if (rt2x00_rt(rt2x00dev, RT5390) ||
3950 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3951 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3952 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3953 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3954
adde5882
GJ		 3955 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3956 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3957 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3958
adde5882
GJ		 3959 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3960 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3961 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3962 }
60687ba7 3963
fcf51541
BZ		 3964 return 0;
3965}
b9a07ae9
ID		 3966
3967int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3968{
3969 u32 reg;
3970 u16 word;
3971
3972 /*
3973 * Initialize all registers.
3974 */
3975 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3976 rt2800_init_registers(rt2x00dev) ||
3977 rt2800_init_bbp(rt2x00dev) ||
3978 rt2800_init_rfcsr(rt2x00dev)))
3979 return -EIO;
3980
3981 /*
3982 * Send signal to firmware during boot time.
3983 */
3984 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3985
3986 if (rt2x00_is_usb(rt2x00dev) &&
3987 (rt2x00_rt(rt2x00dev, RT3070) ||
3988 rt2x00_rt(rt2x00dev, RT3071) ||
3989 rt2x00_rt(rt2x00dev, RT3572))) {
3990 udelay(200);
3991 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3992 udelay(10);
3993 }
3994
3995 /*
3996 * Enable RX.
3997 */
3998 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3999 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4000 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4001 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4002
4003 udelay(50);
4004
4005 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4006 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4007 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4008 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4009 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4010 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4011
4012 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4013 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4014 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4015 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4016
4017 /*
4018 * Initialize LED control
4019 */
38c8a566
RJH		 4020 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4021 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 4022 word & 0xff, (word >> 8) & 0xff);
4023
38c8a566
RJH		 4024 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4025 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 4026 word & 0xff, (word >> 8) & 0xff);
4027
38c8a566
RJH		 4028 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4029 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 4030 word & 0xff, (word >> 8) & 0xff);
4031
4032 return 0;
4033}
4034EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4035
4036void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4037{
4038 u32 reg;
4039
f7b395e9 4040 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 4041
4042 /* Wait for DMA, ignore error */
4043 rt2800_wait_wpdma_ready(rt2x00dev);
4044
4045 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4046 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4047 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4048 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 4049}
4050EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 4051
30e84034
BZ		 4052int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4053{
4054 u32 reg;
4055
4056 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
4057
4058 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4059}
4060EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4061
4062static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4063{
4064 u32 reg;
4065
31a4cf1f
GW		 4066 mutex_lock(&rt2x00dev->csr_mutex);
4067
4068 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 4069 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4070 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4071 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 4072 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 4073
4074 /* Wait until the EEPROM has been loaded */
4075 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
4076
4077 /* Apparently the data is read from end to start */
daabead1
LF		 4078 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
4079 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 4080 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
daabead1
LF		 4081 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
4082 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4083 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
4084 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4085 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
4086 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 4087
4088 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 4089}
4090
4091void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4092{
4093 unsigned int i;
4094
4095 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4096 rt2800_efuse_read(rt2x00dev, i);
4097}
4098EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4099
38bd7b8a
BZ		 4100int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4101{
77c06c2c 4102 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 4103 u16 word;
4104 u8 *mac;
4105 u8 default_lna_gain;
4106
4107 /*
4108 * Start validation of the data that has been read.
4109 */
4110 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4111 if (!is_valid_ether_addr(mac)) {
4112 random_ether_addr(mac);
4113 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4114 }
4115
38c8a566 4116 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 4117 if (word == 0xffff) {
38c8a566
RJH		 4118 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4119 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4120 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4121 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 4122 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 4123 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 4124 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 4125 /*
4126 * There is a max of 2 RX streams for RT28x0 series
4127 */
38c8a566
RJH		 4128 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4129 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4130 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 4131 }
4132
38c8a566 4133 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 4134 if (word == 0xffff) {
38c8a566
RJH		 4135 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4136 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4137 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4138 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4139 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4140 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4141 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4142 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4143 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4144 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4145 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4146 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4147 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4148 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4149 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4150 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 4151 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4152 }
4153
4154 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4155 if ((word & 0x00ff) == 0x00ff) {
4156 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 4157 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4158 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4159 }
4160 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 4161 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4162 LED_MODE_TXRX_ACTIVITY);
4163 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4164 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 4165 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4166 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4167 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 4168 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 4169 }
4170
4171 /*
4172 * During the LNA validation we are going to use
4173 * lna0 as correct value. Note that EEPROM_LNA
4174 * is never validated.
4175 */
4176 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4177 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4178
4179 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4180 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4181 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4182 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4183 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4184 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4185
77c06c2c
GW		 4186 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4187 if ((word & 0x00ff) != 0x00ff) {
4188 drv_data->txmixer_gain_24g =
4189 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4190 } else {
4191 drv_data->txmixer_gain_24g = 0;
4192 }
4193
38bd7b8a
BZ		 4194 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4195 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4196 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4197 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4198 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4199 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4200 default_lna_gain);
4201 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4202
77c06c2c
GW		 4203 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4204 if ((word & 0x00ff) != 0x00ff) {
4205 drv_data->txmixer_gain_5g =
4206 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4207 } else {
4208 drv_data->txmixer_gain_5g = 0;
4209 }
4210
38bd7b8a
BZ		 4211 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4212 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4213 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4214 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4215 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4216 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4217
4218 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4219 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4220 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4221 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4222 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4223 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4224 default_lna_gain);
4225 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4226
4227 return 0;
4228}
4229EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4230
4231int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4232{
4233 u32 reg;
4234 u16 value;
4235 u16 eeprom;
4236
4237 /*
4238 * Read EEPROM word for configuration.
4239 */
38c8a566 4240 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 4241
4242 /*
adde5882
GJ		 4243 * Identify RF chipset by EEPROM value
4244 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4245 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 4246 */
38bd7b8a 4247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2ed71884
JL		 4248 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4249 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
adde5882
GJ		 4250 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4251 else
4252 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 4253
49e721ec
GW		 4254 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4255 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4256
5aa57015
GW		 4257 switch (rt2x00dev->chip.rt) {
4258 case RT2860:
4259 case RT2872:
4260 case RT2883:
4261 case RT3070:
4262 case RT3071:
4263 case RT3090:
4264 case RT3390:
4265 case RT3572:
4266 case RT5390:
2ed71884 4267 case RT5392:
5aa57015
GW		 4268 break;
4269 default:
b6df7f1d 4270 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
49e721ec 4271 return -ENODEV;
f273fe55 4272 }
714fa663 4273
d331eb51
LF		 4274 switch (rt2x00dev->chip.rf) {
4275 case RF2820:
4276 case RF2850:
4277 case RF2720:
4278 case RF2750:
4279 case RF3020:
4280 case RF2020:
4281 case RF3021:
4282 case RF3022:
4283 case RF3052:
4284 case RF3320:
ccf91bd6 4285 case RF5360:
d331eb51 4286 case RF5370:
2ed71884 4287 case RF5372:
d331eb51 4288 case RF5390:
cff3d1f0 4289 case RF5392:
d331eb51
LF		 4290 break;
4291 default:
b6df7f1d 4292 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
d331eb51 4293 rt2x00dev->chip.rf);
38bd7b8a
BZ		 4294 return -ENODEV;
4295 }
4296
4297 /*
4298 * Identify default antenna configuration.
4299 */
d96aa640 4300 rt2x00dev->default_ant.tx_chain_num =
38c8a566 4301 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 4302 rt2x00dev->default_ant.rx_chain_num =
38c8a566 4303 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 4304
d96aa640
RJH		 4305 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4306
4307 if (rt2x00_rt(rt2x00dev, RT3070) ||
4308 rt2x00_rt(rt2x00dev, RT3090) ||
4309 rt2x00_rt(rt2x00dev, RT3390)) {
4310 value = rt2x00_get_field16(eeprom,
4311 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4312 switch (value) {
4313 case 0:
4314 case 1:
4315 case 2:
4316 rt2x00dev->default_ant.tx = ANTENNA_A;
4317 rt2x00dev->default_ant.rx = ANTENNA_A;
4318 break;
4319 case 3:
4320 rt2x00dev->default_ant.tx = ANTENNA_A;
4321 rt2x00dev->default_ant.rx = ANTENNA_B;
4322 break;
4323 }
4324 } else {
4325 rt2x00dev->default_ant.tx = ANTENNA_A;
4326 rt2x00dev->default_ant.rx = ANTENNA_A;
4327 }
4328
0586a11b
AA		 4329 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4330 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4331 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4332 }
4333
38bd7b8a 4334 /*
9328fdac 4335 * Determine external LNA informations.
38bd7b8a 4336 */
38c8a566 4337 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4338 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4339 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4340 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4341
4342 /*
4343 * Detect if this device has an hardware controlled radio.
4344 */
38c8a566 4345 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4346 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4347
fdbc7b0a
GW		 4348 /*
4349 * Detect if this device has Bluetooth co-existence.
4350 */
4351 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4352 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4353
9328fdac
GW		 4354 /*
4355 * Read frequency offset and RF programming sequence.
4356 */
4357 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4358 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4359
38bd7b8a
BZ		 4360 /*
4361 * Store led settings, for correct led behaviour.
4362 */
4363#ifdef CONFIG_RT2X00_LIB_LEDS
4364 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4365 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4366 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4367
9328fdac 4368 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4369#endif /* CONFIG_RT2X00_LIB_LEDS */
4370
e90c54b2
RJH		 4371 /*
4372 * Check if support EIRP tx power limit feature.
4373 */
4374 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4375
4376 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4377 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4378 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4379
38bd7b8a
BZ		 4380 return 0;
4381}
4382EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4383
4da2933f 4384/*
55f9321a 4385 * RF value list for rt28xx
4da2933f
BZ		 4386 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4387 */
4388static const struct rf_channel rf_vals[] = {
4389 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4390 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4391 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4392 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4393 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4394 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4395 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4396 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4397 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4398 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4399 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4400 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4401 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4402 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4403
4404 /* 802.11 UNI / HyperLan 2 */
4405 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4406 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4407 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4408 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4409 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4410 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4411 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4412 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4413 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4414 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4415 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4416 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4417
4418 /* 802.11 HyperLan 2 */
4419 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4420 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4421 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4422 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4423 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4424 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4425 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4426 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4427 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4428 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4429 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4430 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4431 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4432 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4433 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4434 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4435
4436 /* 802.11 UNII */
4437 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4438 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4439 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4440 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4441 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4442 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4443 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4444 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4445 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4446 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4447 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4448
4449 /* 802.11 Japan */
4450 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4451 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4452 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4453 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4454 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4455 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4456 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4457};
4458
4459/*
55f9321a
ID		 4460 * RF value list for rt3xxx
4461 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4462 */
55f9321a 4463static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4464 {1, 241, 2, 2 },
4465 {2, 241, 2, 7 },
4466 {3, 242, 2, 2 },
4467 {4, 242, 2, 7 },
4468 {5, 243, 2, 2 },
4469 {6, 243, 2, 7 },
4470 {7, 244, 2, 2 },
4471 {8, 244, 2, 7 },
4472 {9, 245, 2, 2 },
4473 {10, 245, 2, 7 },
4474 {11, 246, 2, 2 },
4475 {12, 246, 2, 7 },
4476 {13, 247, 2, 2 },
4477 {14, 248, 2, 4 },
55f9321a
ID		 4478
4479 /* 802.11 UNI / HyperLan 2 */
4480 {36, 0x56, 0, 4},
4481 {38, 0x56, 0, 6},
4482 {40, 0x56, 0, 8},
4483 {44, 0x57, 0, 0},
4484 {46, 0x57, 0, 2},
4485 {48, 0x57, 0, 4},
4486 {52, 0x57, 0, 8},
4487 {54, 0x57, 0, 10},
4488 {56, 0x58, 0, 0},
4489 {60, 0x58, 0, 4},
4490 {62, 0x58, 0, 6},
4491 {64, 0x58, 0, 8},
4492
4493 /* 802.11 HyperLan 2 */
4494 {100, 0x5b, 0, 8},
4495 {102, 0x5b, 0, 10},
4496 {104, 0x5c, 0, 0},
4497 {108, 0x5c, 0, 4},
4498 {110, 0x5c, 0, 6},
4499 {112, 0x5c, 0, 8},
4500 {116, 0x5d, 0, 0},
4501 {118, 0x5d, 0, 2},
4502 {120, 0x5d, 0, 4},
4503 {124, 0x5d, 0, 8},
4504 {126, 0x5d, 0, 10},
4505 {128, 0x5e, 0, 0},
4506 {132, 0x5e, 0, 4},
4507 {134, 0x5e, 0, 6},
4508 {136, 0x5e, 0, 8},
4509 {140, 0x5f, 0, 0},
4510
4511 /* 802.11 UNII */
4512 {149, 0x5f, 0, 9},
4513 {151, 0x5f, 0, 11},
4514 {153, 0x60, 0, 1},
4515 {157, 0x60, 0, 5},
4516 {159, 0x60, 0, 7},
4517 {161, 0x60, 0, 9},
4518 {165, 0x61, 0, 1},
4519 {167, 0x61, 0, 3},
4520 {169, 0x61, 0, 5},
4521 {171, 0x61, 0, 7},
4522 {173, 0x61, 0, 9},
4da2933f
BZ		 4523};
4524
4525int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4526{
4da2933f
BZ		 4527 struct hw_mode_spec *spec = &rt2x00dev->spec;
4528 struct channel_info *info;
8d1331b3
ID		 4529 char *default_power1;
4530 char *default_power2;
4da2933f
BZ		 4531 unsigned int i;
4532 u16 eeprom;
4533
93b6bd26
GW		 4534 /*
4535 * Disable powersaving as default on PCI devices.
4536 */
cea90e55 4537 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 4538 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4539
4da2933f
BZ		 4540 /*
4541 * Initialize all hw fields.
4542 */
4543 rt2x00dev->hw->flags =
4da2933f
BZ		 4544 IEEE80211_HW_SIGNAL_DBM |
4545 IEEE80211_HW_SUPPORTS_PS |
1df90809 4546 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8
HS		 4547 IEEE80211_HW_AMPDU_AGGREGATION |
4548 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4549
5a5b6ed6
HS		 4550 /*
4551 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4552 * unless we are capable of sending the buffered frames out after the
4553 * DTIM transmission using rt2x00lib_beacondone. This will send out
4554 * multicast and broadcast traffic immediately instead of buffering it
4555 * infinitly and thus dropping it after some time.
4556 */
4557 if (!rt2x00_is_usb(rt2x00dev))
4558 rt2x00dev->hw->flags |=
4559 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 4560
4da2933f
BZ		 4561 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4562 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4563 rt2x00_eeprom_addr(rt2x00dev,
4564 EEPROM_MAC_ADDR_0));
4565
3f2bee24
HS		 4566 /*
4567 * As rt2800 has a global fallback table we cannot specify
4568 * more then one tx rate per frame but since the hw will
4569 * try several rates (based on the fallback table) we should
ba3b9e5e 4570 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 4571 * we are going to try. Otherwise mac80211 will truncate our
4572 * reported tx rates and the rc algortihm will end up with
4573 * incorrect data.
4574 */
ba3b9e5e
HS		 4575 rt2x00dev->hw->max_rates = 1;
4576 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 4577 rt2x00dev->hw->max_rate_tries = 1;
4578
38c8a566 4579 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 4580
4581 /*
4582 * Initialize hw_mode information.
4583 */
4584 spec->supported_bands = SUPPORT_BAND_2GHZ;
4585 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4586
5122d898 4587 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 4588 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 4589 spec->num_channels = 14;
4590 spec->channels = rf_vals;
55f9321a
ID		 4591 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4592 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 4593 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4594 spec->num_channels = ARRAY_SIZE(rf_vals);
4595 spec->channels = rf_vals;
5122d898
GW		 4596 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4597 rt2x00_rf(rt2x00dev, RF2020) ||
4598 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4599 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882 4600 rt2x00_rf(rt2x00dev, RF3320) ||
ccf91bd6 4601 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 4602 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 4603 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 4604 rt2x00_rf(rt2x00dev, RF5390) ||
4605 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 4606 spec->num_channels = 14;
4607 spec->channels = rf_vals_3x;
4608 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4609 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4610 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4611 spec->channels = rf_vals_3x;
4da2933f
BZ		 4612 }
4613
4614 /*
4615 * Initialize HT information.
4616 */
5122d898 4617 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4618 spec->ht.ht_supported = true;
4619 else
4620 spec->ht.ht_supported = false;
4621
4da2933f 4622 spec->ht.cap =
06443e46 4623 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4624 IEEE80211_HT_CAP_GRN_FLD |
4625 IEEE80211_HT_CAP_SGI_20 |
aa674631 4626 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4627
38c8a566 4628 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4629 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4630
aa674631 4631 spec->ht.cap |=
38c8a566 4632 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4633 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4634
4da2933f
BZ		 4635 spec->ht.ampdu_factor = 3;
4636 spec->ht.ampdu_density = 4;
4637 spec->ht.mcs.tx_params =
4638 IEEE80211_HT_MCS_TX_DEFINED |
4639 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4640 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4641 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4642
38c8a566 4643 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4644 case 3:
4645 spec->ht.mcs.rx_mask[2] = 0xff;
4646 case 2:
4647 spec->ht.mcs.rx_mask[1] = 0xff;
4648 case 1:
4649 spec->ht.mcs.rx_mask[0] = 0xff;
4650 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4651 break;
4652 }
4653
4654 /*
4655 * Create channel information array
4656 */
baeb2ffa 4657 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4658 if (!info)
4659 return -ENOMEM;
4660
4661 spec->channels_info = info;
4662
8d1331b3
ID		 4663 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4664 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4665
4666 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4667 info[i].default_power1 = default_power1[i];
4668 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4669 }
4670
4671 if (spec->num_channels > 14) {
8d1331b3
ID		 4672 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4673 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4674
4675 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4676 info[i].default_power1 = default_power1[i];
4677 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4678 }
4679 }
4680
2e9c43dd
JL		 4681 switch (rt2x00dev->chip.rf) {
4682 case RF2020:
4683 case RF3020:
4684 case RF3021:
4685 case RF3022:
4686 case RF3320:
4687 case RF3052:
ccf91bd6 4688 case RF5360:
2e9c43dd
JL		 4689 case RF5370:
4690 case RF5372:
4691 case RF5390:
cff3d1f0 4692 case RF5392:
2e9c43dd
JL		 4693 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4694 break;
4695 }
4696
4da2933f
BZ		 4697 return 0;
4698}
4699EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4700
2ce33995
BZ		 4701/*
4702 * IEEE80211 stack callback functions.
4703 */
e783619e
HS		 4704void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4705 u16 *iv16)
2ce33995
BZ		 4706{
4707 struct rt2x00_dev *rt2x00dev = hw->priv;
4708 struct mac_iveiv_entry iveiv_entry;
4709 u32 offset;
4710
4711 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4712 rt2800_register_multiread(rt2x00dev, offset,
4713 &iveiv_entry, sizeof(iveiv_entry));
4714
855da5e0
JL		 4715 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4716 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4717}
e783619e 4718EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4719
e783619e 4720int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4721{
4722 struct rt2x00_dev *rt2x00dev = hw->priv;
4723 u32 reg;
4724 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4725
4726 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4727 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4728 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4729
4730 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4731 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4732 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4733
4734 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4735 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4736 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4737
4738 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4739 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4740 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4741
4742 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4743 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4744 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4745
4746 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4747 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4748 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4749
4750 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4751 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4752 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4753
4754 return 0;
4755}
e783619e 4756EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4757
8a3a3c85
EP		 4758int rt2800_conf_tx(struct ieee80211_hw *hw,
4759 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 4760 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4761{
4762 struct rt2x00_dev *rt2x00dev = hw->priv;
4763 struct data_queue *queue;
4764 struct rt2x00_field32 field;
4765 int retval;
4766 u32 reg;
4767 u32 offset;
4768
4769 /*
4770 * First pass the configuration through rt2x00lib, that will
4771 * update the queue settings and validate the input. After that
4772 * we are free to update the registers based on the value
4773 * in the queue parameter.
4774 */
8a3a3c85 4775 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 4776 if (retval)
4777 return retval;
4778
4779 /*
4780 * We only need to perform additional register initialization
4781 * for WMM queues/
4782 */
4783 if (queue_idx >= 4)
4784 return 0;
4785
11f818e0 4786 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4787
4788 /* Update WMM TXOP register */
4789 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4790 field.bit_offset = (queue_idx & 1) * 16;
4791 field.bit_mask = 0xffff << field.bit_offset;
4792
4793 rt2800_register_read(rt2x00dev, offset, &reg);
4794 rt2x00_set_field32(&reg, field, queue->txop);
4795 rt2800_register_write(rt2x00dev, offset, reg);
4796
4797 /* Update WMM registers */
4798 field.bit_offset = queue_idx * 4;
4799 field.bit_mask = 0xf << field.bit_offset;
4800
4801 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4802 rt2x00_set_field32(&reg, field, queue->aifs);
4803 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4804
4805 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4806 rt2x00_set_field32(&reg, field, queue->cw_min);
4807 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4808
4809 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4810 rt2x00_set_field32(&reg, field, queue->cw_max);
4811 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4812
4813 /* Update EDCA registers */
4814 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4815
4816 rt2800_register_read(rt2x00dev, offset, &reg);
4817 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4818 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4819 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4820 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4821 rt2800_register_write(rt2x00dev, offset, reg);
4822
4823 return 0;
4824}
e783619e 4825EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4826
37a41b4a 4827u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 4828{
4829 struct rt2x00_dev *rt2x00dev = hw->priv;
4830 u64 tsf;
4831 u32 reg;
4832
4833 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4834 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4835 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4836 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4837
4838 return tsf;
4839}
e783619e 4840EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4841
e783619e
HS		 4842int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4843 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4844 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4845 u8 buf_size)
1df90809 4846{
af35323d 4847 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 4848 int ret = 0;
4849
af35323d
HS		 4850 /*
4851 * Don't allow aggregation for stations the hardware isn't aware
4852 * of because tx status reports for frames to an unknown station
4853 * always contain wcid=255 and thus we can't distinguish between
4854 * multiple stations which leads to unwanted situations when the
4855 * hw reorders frames due to aggregation.
4856 */
4857 if (sta_priv->wcid < 0)
4858 return 1;
4859
1df90809
HS		 4860 switch (action) {
4861 case IEEE80211_AMPDU_RX_START:
4862 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4863 /*
4864 * The hw itself takes care of setting up BlockAck mechanisms.
4865 * So, we only have to allow mac80211 to nagotiate a BlockAck
4866 * agreement. Once that is done, the hw will BlockAck incoming
4867 * AMPDUs without further setup.
4868 */
1df90809
HS		 4869 break;
4870 case IEEE80211_AMPDU_TX_START:
4871 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4872 break;
4873 case IEEE80211_AMPDU_TX_STOP:
4874 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4875 break;
4876 case IEEE80211_AMPDU_TX_OPERATIONAL:
4877 break;
4878 default:
4e9e58c6 4879 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4880 }
4881
4882 return ret;
4883}
e783619e 4884EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4885
977206d7
HS		 4886int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4887 struct survey_info *survey)
4888{
4889 struct rt2x00_dev *rt2x00dev = hw->priv;
4890 struct ieee80211_conf *conf = &hw->conf;
4891 u32 idle, busy, busy_ext;
4892
4893 if (idx != 0)
4894 return -ENOENT;
4895
4896 survey->channel = conf->channel;
4897
4898 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4899 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4900 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4901
4902 if (idle || busy) {
4903 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4904 SURVEY_INFO_CHANNEL_TIME_BUSY |
4905 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4906
4907 survey->channel_time = (idle + busy) / 1000;
4908 survey->channel_time_busy = busy / 1000;
4909 survey->channel_time_ext_busy = busy_ext / 1000;
4910 }
4911
9931df26
HS		 4912 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4913 survey->filled |= SURVEY_INFO_IN_USE;
4914
977206d7
HS		 4915 return 0;
4916
4917}
4918EXPORT_SYMBOL_GPL(rt2800_get_survey);
4919
a5ea2f02
ID		 4920MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4921MODULE_VERSION(DRV_VERSION);
4922MODULE_DESCRIPTION("Ralink RT2800 library");
4923MODULE_LICENSE("GPL");
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