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rt2x00: rt2800lib: introduce rt2800_eeprom_word_index helper
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
ec9c4989 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
379448fe
GJ		 224static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262};
263
264static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
265 const enum rt2800_eeprom_word word)
266{
267 const unsigned int *map;
268 unsigned int index;
269
270 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
271 "%s: invalid EEPROM word %d\n",
272 wiphy_name(rt2x00dev->hw->wiphy), word))
273 return 0;
274
275 map = rt2800_eeprom_map;
276 index = map[word];
277
278 /* Index 0 is valid only for EEPROM_CHIP_ID.
279 * Otherwise it means that the offset of the
280 * given word is not initialized in the map,
281 * or that the field is not usable on the
282 * actual chipset.
283 */
284 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
285 "%s: invalid access of EEPROM word %d\n",
286 wiphy_name(rt2x00dev->hw->wiphy), word);
287
288 return index;
289}
290
3e38d3da
GJ		 291static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
292 const enum rt2800_eeprom_word word)
293{
379448fe
GJ		 294 unsigned int index;
295
296 index = rt2800_eeprom_word_index(rt2x00dev, word);
297 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 298}
299
300static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
301 const enum rt2800_eeprom_word word, u16 *data)
302{
379448fe
GJ		 303 unsigned int index;
304
305 index = rt2800_eeprom_word_index(rt2x00dev, word);
306 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 307}
308
309static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
310 const enum rt2800_eeprom_word word, u16 data)
311{
379448fe
GJ		 312 unsigned int index;
313
314 index = rt2800_eeprom_word_index(rt2x00dev, word);
315 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 316}
317
022138ca
GJ		 318static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
319 const enum rt2800_eeprom_word array,
320 unsigned int offset,
321 u16 *data)
322{
379448fe
GJ		 323 unsigned int index;
324
325 index = rt2800_eeprom_word_index(rt2x00dev, array);
326 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 327}
328
16ebd608
WH		 329static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
330{
331 u32 reg;
332 int i, count;
333
334 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
335 if (rt2x00_get_field32(reg, WLAN_EN))
336 return 0;
337
338 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
339 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
340 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
341 rt2x00_set_field32(&reg, WLAN_EN, 1);
342 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
343
344 udelay(REGISTER_BUSY_DELAY);
345
346 count = 0;
347 do {
348 /*
349 * Check PLL_LD & XTAL_RDY.
350 */
351 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
352 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
353 if (rt2x00_get_field32(reg, PLL_LD) &&
354 rt2x00_get_field32(reg, XTAL_RDY))
355 break;
356 udelay(REGISTER_BUSY_DELAY);
357 }
358
359 if (i >= REGISTER_BUSY_COUNT) {
360
361 if (count >= 10)
362 return -EIO;
363
364 rt2800_register_write(rt2x00dev, 0x58, 0x018);
365 udelay(REGISTER_BUSY_DELAY);
366 rt2800_register_write(rt2x00dev, 0x58, 0x418);
367 udelay(REGISTER_BUSY_DELAY);
368 rt2800_register_write(rt2x00dev, 0x58, 0x618);
369 udelay(REGISTER_BUSY_DELAY);
370 count++;
371 } else {
372 count = 0;
373 }
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
377 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
378 rt2x00_set_field32(&reg, WLAN_RESET, 1);
379 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
380 udelay(10);
381 rt2x00_set_field32(&reg, WLAN_RESET, 0);
382 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
383 udelay(10);
384 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
385 } while (count != 0);
386
387 return 0;
388}
389
89297425
BZ		 390void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
391 const u8 command, const u8 token,
392 const u8 arg0, const u8 arg1)
393{
394 u32 reg;
395
ee303e54 396 /*
cea90e55 397 * SOC devices don't support MCU requests.
ee303e54 398 */
cea90e55 399 if (rt2x00_is_soc(rt2x00dev))
ee303e54 400 return;
89297425
BZ		 401
402 mutex_lock(&rt2x00dev->csr_mutex);
403
404 /*
405 * Wait until the MCU becomes available, afterwards we
406 * can safely write the new data into the register.
407 */
408 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
409 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
410 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
411 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
412 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
413 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
414
415 reg = 0;
416 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
417 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
418 }
419
420 mutex_unlock(&rt2x00dev->csr_mutex);
421}
422EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 423
5ffddc49
ID		 424int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
425{
426 unsigned int i = 0;
427 u32 reg;
428
429 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
430 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
431 if (reg && reg != ~0)
432 return 0;
433 msleep(1);
434 }
435
ec9c4989 436 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 437 return -EBUSY;
438}
439EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
440
67a4c1e2
GW		 441int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
442{
443 unsigned int i;
444 u32 reg;
445
08e53100
HS		 446 /*
447 * Some devices are really slow to respond here. Wait a whole second
448 * before timing out.
449 */
67a4c1e2
GW		 450 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
451 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
452 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
453 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
454 return 0;
455
08e53100 456 msleep(10);
67a4c1e2
GW		 457 }
458
ec9c4989 459 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 460 return -EACCES;
461}
462EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
463
f7b395e9
JK		 464void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
465{
466 u32 reg;
467
468 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
469 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
470 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
471 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
472 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
473 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
474 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
475}
476EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
477
f31c9a8c
ID		 478static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
479{
480 u16 fw_crc;
481 u16 crc;
482
483 /*
484 * The last 2 bytes in the firmware array are the crc checksum itself,
485 * this means that we should never pass those 2 bytes to the crc
486 * algorithm.
487 */
488 fw_crc = (data[len - 2] << 8 | data[len - 1]);
489
490 /*
491 * Use the crc ccitt algorithm.
492 * This will return the same value as the legacy driver which
493 * used bit ordering reversion on the both the firmware bytes
494 * before input input as well as on the final output.
495 * Obviously using crc ccitt directly is much more efficient.
496 */
497 crc = crc_ccitt(~0, data, len - 2);
498
499 /*
500 * There is a small difference between the crc-itu-t + bitrev and
501 * the crc-ccitt crc calculation. In the latter method the 2 bytes
502 * will be swapped, use swab16 to convert the crc to the correct
503 * value.
504 */
505 crc = swab16(crc);
506
507 return fw_crc == crc;
508}
509
510int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
511 const u8 *data, const size_t len)
512{
513 size_t offset = 0;
514 size_t fw_len;
515 bool multiple;
516
517 /*
518 * PCI(e) & SOC devices require firmware with a length
519 * of 8kb. USB devices require firmware files with a length
520 * of 4kb. Certain USB chipsets however require different firmware,
521 * which Ralink only provides attached to the original firmware
522 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 523 * which is a multiple of 4kb. The firmware for rt3290 chip also
524 * have a length which is a multiple of 4kb.
f31c9a8c 525 */
a89534ed 526 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 527 fw_len = 4096;
a89534ed 528 else
f31c9a8c 529 fw_len = 8192;
f31c9a8c 530
a89534ed 531 multiple = true;
f31c9a8c
ID		 532 /*
533 * Validate the firmware length
534 */
535 if (len != fw_len && (!multiple || (len % fw_len) != 0))
536 return FW_BAD_LENGTH;
537
538 /*
539 * Check if the chipset requires one of the upper parts
540 * of the firmware.
541 */
542 if (rt2x00_is_usb(rt2x00dev) &&
543 !rt2x00_rt(rt2x00dev, RT2860) &&
544 !rt2x00_rt(rt2x00dev, RT2872) &&
545 !rt2x00_rt(rt2x00dev, RT3070) &&
546 ((len / fw_len) == 1))
547 return FW_BAD_VERSION;
548
549 /*
550 * 8kb firmware files must be checked as if it were
551 * 2 separate firmware files.
552 */
553 while (offset < len) {
554 if (!rt2800_check_firmware_crc(data + offset, fw_len))
555 return FW_BAD_CRC;
556
557 offset += fw_len;
558 }
559
560 return FW_OK;
561}
562EXPORT_SYMBOL_GPL(rt2800_check_firmware);
563
564int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
565 const u8 *data, const size_t len)
566{
567 unsigned int i;
568 u32 reg;
16ebd608
WH		 569 int retval;
570
571 if (rt2x00_rt(rt2x00dev, RT3290)) {
572 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
573 if (retval)
574 return -EBUSY;
575 }
f31c9a8c
ID		 576
577 /*
b9eca242
ID		 578 * If driver doesn't wake up firmware here,
579 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 580 */
b9eca242 581 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 582
f31c9a8c
ID		 583 /*
584 * Wait for stable hardware.
585 */
5ffddc49 586 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 587 return -EBUSY;
f31c9a8c 588
adde5882 589 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 590 if (rt2x00_rt(rt2x00dev, RT3290) ||
591 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 592 rt2x00_rt(rt2x00dev, RT5390) ||
593 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 594 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
595 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
596 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
597 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
598 }
f31c9a8c 599 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 600 }
f31c9a8c 601
b7e1d225
JK		 602 rt2800_disable_wpdma(rt2x00dev);
603
f31c9a8c
ID		 604 /*
605 * Write firmware to the device.
606 */
607 rt2800_drv_write_firmware(rt2x00dev, data, len);
608
609 /*
610 * Wait for device to stabilize.
611 */
612 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
613 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
614 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
615 break;
616 msleep(1);
617 }
618
619 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 620 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 621 return -EBUSY;
622 }
623
4ed1dd2a
SG		 624 /*
625 * Disable DMA, will be reenabled later when enabling
626 * the radio.
627 */
f7b395e9 628 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 629
f31c9a8c
ID		 630 /*
631 * Initialize firmware.
632 */
633 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
634 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 635 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 636 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 637 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
638 }
f31c9a8c
ID		 639 msleep(1);
640
641 return 0;
642}
643EXPORT_SYMBOL_GPL(rt2800_load_firmware);
644
0c5879bc
ID		 645void rt2800_write_tx_data(struct queue_entry *entry,
646 struct txentry_desc *txdesc)
59679b91 647{
0c5879bc 648 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 649 u32 word;
557985ae 650 int i;
59679b91
GW		 651
652 /*
653 * Initialize TX Info descriptor
654 */
655 rt2x00_desc_read(txwi, 0, &word);
656 rt2x00_set_field32(&word, TXWI_W0_FRAG,
657 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 658 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
659 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 660 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
661 rt2x00_set_field32(&word, TXWI_W0_TS,
662 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
663 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
664 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 665 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
666 txdesc->u.ht.mpdu_density);
667 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
668 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 669 rt2x00_set_field32(&word, TXWI_W0_BW,
670 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
671 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
672 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 673 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 674 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
675 rt2x00_desc_write(txwi, 0, word);
676
677 rt2x00_desc_read(txwi, 1, &word);
678 rt2x00_set_field32(&word, TXWI_W1_ACK,
679 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
680 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
681 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 682 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 683 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
684 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 685 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 686 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
687 txdesc->length);
2b23cdaa 688 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 689 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 690 rt2x00_desc_write(txwi, 1, word);
691
692 /*
557985ae
SG		 693 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
694 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 695 * When TXD_W3_WIV is set to 1 it will use the IV data
696 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
697 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 698 *
699 * Nulify all remaining words as well, we don't know how to program them.
59679b91 700 */
557985ae
SG		 701 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
702 _rt2x00_desc_write(txwi, i, 0);
59679b91 703}
0c5879bc 704EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 705
ff6133be 706static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 707{
7fc41755
LT		 708 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
709 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
710 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 711 u16 eeprom;
712 u8 offset0;
713 u8 offset1;
714 u8 offset2;
715
e5ef5bad 716 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 717 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 718 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
719 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 720 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 721 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
722 } else {
3e38d3da 723 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 724 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
725 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 726 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 727 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
728 }
729
730 /*
731 * Convert the value from the descriptor into the RSSI value
732 * If the value in the descriptor is 0, it is considered invalid
733 * and the default (extremely low) rssi value is assumed
734 */
735 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
736 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
737 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
738
739 /*
740 * mac80211 only accepts a single RSSI value. Calculating the
741 * average doesn't deliver a fair answer either since -60:-60 would
742 * be considered equally good as -50:-70 while the second is the one
743 * which gives less energy...
744 */
745 rssi0 = max(rssi0, rssi1);
7fc41755 746 return (int)max(rssi0, rssi2);
74861922
ID		 747}
748
749void rt2800_process_rxwi(struct queue_entry *entry,
750 struct rxdone_entry_desc *rxdesc)
751{
752 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 753 u32 word;
754
755 rt2x00_desc_read(rxwi, 0, &word);
756
757 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
758 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
759
760 rt2x00_desc_read(rxwi, 1, &word);
761
762 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
763 rxdesc->flags |= RX_FLAG_SHORT_GI;
764
765 if (rt2x00_get_field32(word, RXWI_W1_BW))
766 rxdesc->flags |= RX_FLAG_40MHZ;
767
768 /*
769 * Detect RX rate, always use MCS as signal type.
770 */
771 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
772 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
773 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
774
775 /*
776 * Mask of 0x8 bit to remove the short preamble flag.
777 */
778 if (rxdesc->rate_mode == RATE_MODE_CCK)
779 rxdesc->signal &= ~0x8;
780
781 rt2x00_desc_read(rxwi, 2, &word);
782
74861922
ID		 783 /*
784 * Convert descriptor AGC value to RSSI value.
785 */
786 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 787 /*
788 * Remove RXWI descriptor from start of the buffer.
789 */
790 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 791}
792EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
793
31937c42 794void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 795{
796 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 797 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 798 struct txdone_entry_desc txdesc;
799 u32 word;
800 u16 mcs, real_mcs;
b34793ee 801 int aggr, ampdu;
14433331
HS		 802
803 /*
804 * Obtain the status about this packet.
805 */
806 txdesc.flags = 0;
14433331 807 rt2x00_desc_read(txwi, 0, &word);
b34793ee 808
14433331 809 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 810 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
811
14433331 812 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 813 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
814
815 /*
816 * If a frame was meant to be sent as a single non-aggregated MPDU
817 * but ended up in an aggregate the used tx rate doesn't correlate
818 * with the one specified in the TXWI as the whole aggregate is sent
819 * with the same rate.
820 *
821 * For example: two frames are sent to rt2x00, the first one sets
822 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
823 * and requests MCS15. If the hw aggregates both frames into one
824 * AMDPU the tx status for both frames will contain MCS7 although
825 * the frame was sent successfully.
826 *
827 * Hence, replace the requested rate with the real tx rate to not
828 * confuse the rate control algortihm by providing clearly wrong
829 * data.
830 */
5356d963 831 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 832 skbdesc->tx_rate_idx = real_mcs;
833 mcs = real_mcs;
834 }
14433331 835
f16d2db7
HS		 836 if (aggr == 1 || ampdu == 1)
837 __set_bit(TXDONE_AMPDU, &txdesc.flags);
838
14433331
HS		 839 /*
840 * Ralink has a retry mechanism using a global fallback
841 * table. We setup this fallback table to try the immediate
842 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
843 * always contains the MCS used for the last transmission, be
844 * it successful or not.
845 */
846 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
847 /*
848 * Transmission succeeded. The number of retries is
849 * mcs - real_mcs
850 */
851 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
852 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
853 } else {
854 /*
855 * Transmission failed. The number of retries is
856 * always 7 in this case (for a total number of 8
857 * frames sent).
858 */
859 __set_bit(TXDONE_FAILURE, &txdesc.flags);
860 txdesc.retry = rt2x00dev->long_retry;
861 }
862
863 /*
864 * the frame was retried at least once
865 * -> hw used fallback rates
866 */
867 if (txdesc.retry)
868 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
869
870 rt2x00lib_txdone(entry, &txdesc);
871}
872EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
873
f0194b2d
GW		 874void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
875{
876 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
877 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
878 unsigned int beacon_base;
739fd940 879 unsigned int padding_len;
d76dfc61 880 u32 orig_reg, reg;
f0bda571 881 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 882
883 /*
884 * Disable beaconing while we are reloading the beacon data,
885 * otherwise we might be sending out invalid data.
886 */
887 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 888 orig_reg = reg;
f0194b2d
GW		 889 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
890 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
891
892 /*
893 * Add space for the TXWI in front of the skb.
894 */
f0bda571 895 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 896
897 /*
898 * Register descriptor details in skb frame descriptor.
899 */
900 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
901 skbdesc->desc = entry->skb->data;
f0bda571 902 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 903
904 /*
905 * Add the TXWI for the beacon to the skb.
906 */
0c5879bc 907 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 908
909 /*
910 * Dump beacon to userspace through debugfs.
911 */
912 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
913
914 /*
739fd940 915 * Write entire beacon with TXWI and padding to register.
f0194b2d 916 */
739fd940 917 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 918 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 919 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 920 /* skb freed by skb_pad() on failure */
921 entry->skb = NULL;
922 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
923 return;
924 }
925
f0194b2d 926 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 927 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
928 entry->skb->len + padding_len);
f0194b2d
GW		 929
930 /*
931 * Enable beaconing again.
932 */
f0194b2d
GW		 933 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
934 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
935
936 /*
937 * Clean up beacon skb.
938 */
939 dev_kfree_skb_any(entry->skb);
940 entry->skb = NULL;
941}
50e888ea 942EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 943
69cf36a4
HS		 944static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
945 unsigned int beacon_base)
fdb87251
HS		 946{
947 int i;
0879f875 948 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
fdb87251
HS		 949
950 /*
951 * For the Beacon base registers we only need to clear
952 * the whole TXWI which (when set to 0) will invalidate
953 * the entire beacon.
954 */
f0bda571 955 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 956 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
957}
958
69cf36a4
HS		 959void rt2800_clear_beacon(struct queue_entry *entry)
960{
961 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
962 u32 reg;
963
964 /*
965 * Disable beaconing while we are reloading the beacon data,
966 * otherwise we might be sending out invalid data.
967 */
968 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
969 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
970 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
971
972 /*
973 * Clear beacon.
974 */
975 rt2800_clear_beacon_register(rt2x00dev,
976 HW_BEACON_OFFSET(entry->entry_idx));
977
978 /*
979 * Enabled beaconing again.
980 */
981 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
982 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
983}
984EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
985
f4450616
BZ		 986#ifdef CONFIG_RT2X00_LIB_DEBUGFS
987const struct rt2x00debug rt2800_rt2x00debug = {
988 .owner = THIS_MODULE,
989 .csr = {
990 .read = rt2800_register_read,
991 .write = rt2800_register_write,
992 .flags = RT2X00DEBUGFS_OFFSET,
993 .word_base = CSR_REG_BASE,
994 .word_size = sizeof(u32),
995 .word_count = CSR_REG_SIZE / sizeof(u32),
996 },
997 .eeprom = {
3e38d3da
GJ		 998 /* NOTE: The local EEPROM access functions can't
999 * be used here, use the generic versions instead.
1000 */
f4450616
BZ		 1001 .read = rt2x00_eeprom_read,
1002 .write = rt2x00_eeprom_write,
1003 .word_base = EEPROM_BASE,
1004 .word_size = sizeof(u16),
1005 .word_count = EEPROM_SIZE / sizeof(u16),
1006 },
1007 .bbp = {
1008 .read = rt2800_bbp_read,
1009 .write = rt2800_bbp_write,
1010 .word_base = BBP_BASE,
1011 .word_size = sizeof(u8),
1012 .word_count = BBP_SIZE / sizeof(u8),
1013 },
1014 .rf = {
1015 .read = rt2x00_rf_read,
1016 .write = rt2800_rf_write,
1017 .word_base = RF_BASE,
1018 .word_size = sizeof(u32),
1019 .word_count = RF_SIZE / sizeof(u32),
1020 },
f2bd7f16
AA		 1021 .rfcsr = {
1022 .read = rt2800_rfcsr_read,
1023 .write = rt2800_rfcsr_write,
1024 .word_base = RFCSR_BASE,
1025 .word_size = sizeof(u8),
1026 .word_count = RFCSR_SIZE / sizeof(u8),
1027 },
f4450616
BZ		 1028};
1029EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1030#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1031
1032int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1033{
1034 u32 reg;
1035
a89534ed
WH		 1036 if (rt2x00_rt(rt2x00dev, RT3290)) {
1037 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1038 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1039 } else {
99bdf51a
GW		 1040 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1041 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1042 }
f4450616
BZ		 1043}
1044EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1045
1046#ifdef CONFIG_RT2X00_LIB_LEDS
1047static void rt2800_brightness_set(struct led_classdev *led_cdev,
1048 enum led_brightness brightness)
1049{
1050 struct rt2x00_led *led =
1051 container_of(led_cdev, struct rt2x00_led, led_dev);
1052 unsigned int enabled = brightness != LED_OFF;
1053 unsigned int bg_mode =
1054 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1055 unsigned int polarity =
1056 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1057 EEPROM_FREQ_LED_POLARITY);
1058 unsigned int ledmode =
1059 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1060 EEPROM_FREQ_LED_MODE);
44704e5d 1061 u32 reg;
f4450616 1062
44704e5d
LE		 1063 /* Check for SoC (SOC devices don't support MCU requests) */
1064 if (rt2x00_is_soc(led->rt2x00dev)) {
1065 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1066
1067 /* Set LED Polarity */
1068 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1069
1070 /* Set LED Mode */
1071 if (led->type == LED_TYPE_RADIO) {
1072 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1073 enabled ? 3 : 0);
1074 } else if (led->type == LED_TYPE_ASSOC) {
1075 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1076 enabled ? 3 : 0);
1077 } else if (led->type == LED_TYPE_QUALITY) {
1078 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1079 enabled ? 3 : 0);
1080 }
1081
1082 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1083
1084 } else {
1085 if (led->type == LED_TYPE_RADIO) {
1086 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1087 enabled ? 0x20 : 0);
1088 } else if (led->type == LED_TYPE_ASSOC) {
1089 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1090 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1091 } else if (led->type == LED_TYPE_QUALITY) {
1092 /*
1093 * The brightness is divided into 6 levels (0 - 5),
1094 * The specs tell us the following levels:
1095 * 0, 1 ,3, 7, 15, 31
1096 * to determine the level in a simple way we can simply
1097 * work with bitshifting:
1098 * (1 << level) - 1
1099 */
1100 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1101 (1 << brightness / (LED_FULL / 6)) - 1,
1102 polarity);
1103 }
f4450616
BZ		 1104 }
1105}
1106
b3579d6a 1107static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1108 struct rt2x00_led *led, enum led_type type)
1109{
1110 led->rt2x00dev = rt2x00dev;
1111 led->type = type;
1112 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1113 led->flags = LED_INITIALIZED;
1114}
f4450616
BZ		 1115#endif /* CONFIG_RT2X00_LIB_LEDS */
1116
1117/*
1118 * Configuration handlers.
1119 */
a2b1328a
HS		 1120static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1121 const u8 *address,
1122 int wcid)
f4450616
BZ		 1123{
1124 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1125 u32 offset;
1126
1127 offset = MAC_WCID_ENTRY(wcid);
1128
1129 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1130 if (address)
1131 memcpy(wcid_entry.mac, address, ETH_ALEN);
1132
1133 rt2800_register_multiwrite(rt2x00dev, offset,
1134 &wcid_entry, sizeof(wcid_entry));
1135}
1136
1137static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1138{
1139 u32 offset;
1140 offset = MAC_WCID_ATTR_ENTRY(wcid);
1141 rt2800_register_write(rt2x00dev, offset, 0);
1142}
1143
1144static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1145 int wcid, u32 bssidx)
1146{
1147 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1148 u32 reg;
1149
1150 /*
1151 * The BSS Idx numbers is split in a main value of 3 bits,
1152 * and a extended field for adding one additional bit to the value.
1153 */
1154 rt2800_register_read(rt2x00dev, offset, &reg);
1155 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1156 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1157 (bssidx & 0x8) >> 3);
1158 rt2800_register_write(rt2x00dev, offset, reg);
1159}
1160
1161static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1162 struct rt2x00lib_crypto *crypto,
1163 struct ieee80211_key_conf *key)
1164{
f4450616
BZ		 1165 struct mac_iveiv_entry iveiv_entry;
1166 u32 offset;
1167 u32 reg;
1168
1169 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1170
e4a0ab34
ID		 1171 if (crypto->cmd == SET_KEY) {
1172 rt2800_register_read(rt2x00dev, offset, &reg);
1173 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1174 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1175 /*
1176 * Both the cipher as the BSS Idx numbers are split in a main
1177 * value of 3 bits, and a extended field for adding one additional
1178 * bit to the value.
1179 */
1180 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1181 (crypto->cipher & 0x7));
1182 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1183 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1184 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1185 rt2800_register_write(rt2x00dev, offset, reg);
1186 } else {
a2b1328a
HS		 1187 /* Delete the cipher without touching the bssidx */
1188 rt2800_register_read(rt2x00dev, offset, &reg);
1189 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1190 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1191 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1192 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1193 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1194 }
f4450616
BZ		 1195
1196 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1197
1198 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1199 if ((crypto->cipher == CIPHER_TKIP) ||
1200 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1201 (crypto->cipher == CIPHER_AES))
1202 iveiv_entry.iv[3] |= 0x20;
1203 iveiv_entry.iv[3] |= key->keyidx << 6;
1204 rt2800_register_multiwrite(rt2x00dev, offset,
1205 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1206}
1207
1208int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1209 struct rt2x00lib_crypto *crypto,
1210 struct ieee80211_key_conf *key)
1211{
1212 struct hw_key_entry key_entry;
1213 struct rt2x00_field32 field;
1214 u32 offset;
1215 u32 reg;
1216
1217 if (crypto->cmd == SET_KEY) {
1218 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1219
1220 memcpy(key_entry.key, crypto->key,
1221 sizeof(key_entry.key));
1222 memcpy(key_entry.tx_mic, crypto->tx_mic,
1223 sizeof(key_entry.tx_mic));
1224 memcpy(key_entry.rx_mic, crypto->rx_mic,
1225 sizeof(key_entry.rx_mic));
1226
1227 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1228 rt2800_register_multiwrite(rt2x00dev, offset,
1229 &key_entry, sizeof(key_entry));
1230 }
1231
1232 /*
1233 * The cipher types are stored over multiple registers
1234 * starting with SHARED_KEY_MODE_BASE each word will have
1235 * 32 bits and contains the cipher types for 2 bssidx each.
1236 * Using the correct defines correctly will cause overhead,
1237 * so just calculate the correct offset.
1238 */
1239 field.bit_offset = 4 * (key->hw_key_idx % 8);
1240 field.bit_mask = 0x7 << field.bit_offset;
1241
1242 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1243
1244 rt2800_register_read(rt2x00dev, offset, &reg);
1245 rt2x00_set_field32(&reg, field,
1246 (crypto->cmd == SET_KEY) * crypto->cipher);
1247 rt2800_register_write(rt2x00dev, offset, reg);
1248
1249 /*
1250 * Update WCID information
1251 */
a2b1328a
HS		 1252 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1253 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1254 crypto->bssidx);
1255 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1256
1257 return 0;
1258}
1259EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1260
a2b1328a 1261static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1262{
a2b1328a 1263 struct mac_wcid_entry wcid_entry;
1ed3811c 1264 int idx;
a2b1328a 1265 u32 offset;
1ed3811c
HS		 1266
1267 /*
a2b1328a
HS		 1268 * Search for the first free WCID entry and return the corresponding
1269 * index.
1ed3811c
HS		 1270 *
1271 * Make sure the WCID starts _after_ the last possible shared key
1272 * entry (>32).
1273 *
1274 * Since parts of the pairwise key table might be shared with
1275 * the beacon frame buffers 6 & 7 we should only write into the
1276 * first 222 entries.
1277 */
1278 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1279 offset = MAC_WCID_ENTRY(idx);
1280 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1281 sizeof(wcid_entry));
1282 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1283 return idx;
1284 }
a2b1328a
HS		 1285
1286 /*
1287 * Use -1 to indicate that we don't have any more space in the WCID
1288 * table.
1289 */
1ed3811c
HS		 1290 return -1;
1291}
1292
f4450616
BZ		 1293int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1294 struct rt2x00lib_crypto *crypto,
1295 struct ieee80211_key_conf *key)
1296{
1297 struct hw_key_entry key_entry;
1298 u32 offset;
1299
1300 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1301 /*
1302 * Allow key configuration only for STAs that are
1303 * known by the hw.
1304 */
1305 if (crypto->wcid < 0)
f4450616 1306 return -ENOSPC;
a2b1328a 1307 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1308
1309 memcpy(key_entry.key, crypto->key,
1310 sizeof(key_entry.key));
1311 memcpy(key_entry.tx_mic, crypto->tx_mic,
1312 sizeof(key_entry.tx_mic));
1313 memcpy(key_entry.rx_mic, crypto->rx_mic,
1314 sizeof(key_entry.rx_mic));
1315
1316 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1317 rt2800_register_multiwrite(rt2x00dev, offset,
1318 &key_entry, sizeof(key_entry));
1319 }
1320
1321 /*
1322 * Update WCID information
1323 */
a2b1328a 1324 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1325
1326 return 0;
1327}
1328EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1329
a2b1328a
HS		 1330int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1331 struct ieee80211_sta *sta)
1332{
1333 int wcid;
1334 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1335
1336 /*
1337 * Find next free WCID.
1338 */
1339 wcid = rt2800_find_wcid(rt2x00dev);
1340
1341 /*
1342 * Store selected wcid even if it is invalid so that we can
1343 * later decide if the STA is uploaded into the hw.
1344 */
1345 sta_priv->wcid = wcid;
1346
1347 /*
1348 * No space left in the device, however, we can still communicate
1349 * with the STA -> No error.
1350 */
1351 if (wcid < 0)
1352 return 0;
1353
1354 /*
1355 * Clean up WCID attributes and write STA address to the device.
1356 */
1357 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1358 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1359 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1360 rt2x00lib_get_bssidx(rt2x00dev, vif));
1361 return 0;
1362}
1363EXPORT_SYMBOL_GPL(rt2800_sta_add);
1364
1365int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1366{
1367 /*
1368 * Remove WCID entry, no need to clean the attributes as they will
1369 * get renewed when the WCID is reused.
1370 */
1371 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1372
1373 return 0;
1374}
1375EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1376
f4450616
BZ		 1377void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1378 const unsigned int filter_flags)
1379{
1380 u32 reg;
1381
1382 /*
1383 * Start configuration steps.
1384 * Note that the version error will always be dropped
1385 * and broadcast frames will always be accepted since
1386 * there is no filter for it at this time.
1387 */
1388 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1389 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1390 !(filter_flags & FIF_FCSFAIL));
1391 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1392 !(filter_flags & FIF_PLCPFAIL));
1393 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1394 !(filter_flags & FIF_PROMISC_IN_BSS));
1395 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1396 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1397 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1398 !(filter_flags & FIF_ALLMULTI));
1399 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1400 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1401 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1402 !(filter_flags & FIF_CONTROL));
1403 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1404 !(filter_flags & FIF_CONTROL));
1405 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1406 !(filter_flags & FIF_CONTROL));
1407 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1408 !(filter_flags & FIF_CONTROL));
1409 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1410 !(filter_flags & FIF_CONTROL));
1411 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1412 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1413 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1414 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1415 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1416 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1417 !(filter_flags & FIF_CONTROL));
1418 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1419}
1420EXPORT_SYMBOL_GPL(rt2800_config_filter);
1421
1422void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1423 struct rt2x00intf_conf *conf, const unsigned int flags)
1424{
f4450616 1425 u32 reg;
fa8b4b22 1426 bool update_bssid = false;
f4450616
BZ		 1427
1428 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1429 /*
1430 * Enable synchronisation.
1431 */
1432 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1433 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1434 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1435
1436 if (conf->sync == TSF_SYNC_AP_NONE) {
1437 /*
1438 * Tune beacon queue transmit parameters for AP mode
1439 */
1440 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1441 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1442 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1443 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1444 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1445 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1446 } else {
1447 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1448 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1449 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1450 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1451 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1452 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1453 }
f4450616
BZ		 1454 }
1455
1456 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1457 if (flags & CONFIG_UPDATE_TYPE &&
1458 conf->sync == TSF_SYNC_AP_NONE) {
1459 /*
1460 * The BSSID register has to be set to our own mac
1461 * address in AP mode.
1462 */
1463 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1464 update_bssid = true;
1465 }
1466
c600c826
ID		 1467 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1468 reg = le32_to_cpu(conf->mac[1]);
1469 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1470 conf->mac[1] = cpu_to_le32(reg);
1471 }
f4450616
BZ		 1472
1473 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1474 conf->mac, sizeof(conf->mac));
1475 }
1476
fa8b4b22 1477 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1478 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1479 reg = le32_to_cpu(conf->bssid[1]);
1480 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1481 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1482 conf->bssid[1] = cpu_to_le32(reg);
1483 }
f4450616
BZ		 1484
1485 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1486 conf->bssid, sizeof(conf->bssid));
1487 }
1488}
1489EXPORT_SYMBOL_GPL(rt2800_config_intf);
1490
87c1915d
HS		 1491static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1492 struct rt2x00lib_erp *erp)
1493{
1494 bool any_sta_nongf = !!(erp->ht_opmode &
1495 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1496 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1497 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1498 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1499 u32 reg;
1500
1501 /* default protection rate for HT20: OFDM 24M */
1502 mm20_rate = gf20_rate = 0x4004;
1503
1504 /* default protection rate for HT40: duplicate OFDM 24M */
1505 mm40_rate = gf40_rate = 0x4084;
1506
1507 switch (protection) {
1508 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1509 /*
1510 * All STAs in this BSS are HT20/40 but there might be
1511 * STAs not supporting greenfield mode.
1512 * => Disable protection for HT transmissions.
1513 */
1514 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1515
1516 break;
1517 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1518 /*
1519 * All STAs in this BSS are HT20 or HT20/40 but there
1520 * might be STAs not supporting greenfield mode.
1521 * => Protect all HT40 transmissions.
1522 */
1523 mm20_mode = gf20_mode = 0;
1524 mm40_mode = gf40_mode = 2;
1525
1526 break;
1527 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1528 /*
1529 * Nonmember protection:
1530 * According to 802.11n we _should_ protect all
1531 * HT transmissions (but we don't have to).
1532 *
1533 * But if cts_protection is enabled we _shall_ protect
1534 * all HT transmissions using a CCK rate.
1535 *
1536 * And if any station is non GF we _shall_ protect
1537 * GF transmissions.
1538 *
1539 * We decide to protect everything
1540 * -> fall through to mixed mode.
1541 */
1542 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1543 /*
1544 * Legacy STAs are present
1545 * => Protect all HT transmissions.
1546 */
1547 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1548
1549 /*
1550 * If erp protection is needed we have to protect HT
1551 * transmissions with CCK 11M long preamble.
1552 */
1553 if (erp->cts_protection) {
1554 /* don't duplicate RTS/CTS in CCK mode */
1555 mm20_rate = mm40_rate = 0x0003;
1556 gf20_rate = gf40_rate = 0x0003;
1557 }
1558 break;
6403eab1 1559 }
87c1915d
HS		 1560
1561 /* check for STAs not supporting greenfield mode */
1562 if (any_sta_nongf)
1563 gf20_mode = gf40_mode = 2;
1564
1565 /* Update HT protection config */
1566 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1567 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1568 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1569 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1570
1571 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1572 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1573 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1574 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1575
1576 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1577 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1578 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1579 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1580
1581 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1584 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1585}
1586
02044643
HS		 1587void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1588 u32 changed)
f4450616
BZ		 1589{
1590 u32 reg;
1591
02044643
HS		 1592 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1593 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1595 !!erp->short_preamble);
1596 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1597 !!erp->short_preamble);
1598 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1599 }
f4450616 1600
02044643
HS		 1601 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1602 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1603 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1604 erp->cts_protection ? 2 : 0);
1605 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1606 }
f4450616 1607
02044643
HS		 1608 if (changed & BSS_CHANGED_BASIC_RATES) {
1609 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1610 erp->basic_rates);
1611 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1612 }
f4450616 1613
02044643
HS		 1614 if (changed & BSS_CHANGED_ERP_SLOT) {
1615 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1616 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1617 erp->slot_time);
1618 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1619
02044643
HS		 1620 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1621 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1622 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1623 }
f4450616 1624
02044643
HS		 1625 if (changed & BSS_CHANGED_BEACON_INT) {
1626 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1627 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1628 erp->beacon_int * 16);
1629 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1630 }
87c1915d
HS		 1631
1632 if (changed & BSS_CHANGED_HT)
1633 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1634}
1635EXPORT_SYMBOL_GPL(rt2800_config_erp);
1636
872834df
GW		 1637static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1638{
1639 u32 reg;
1640 u16 eeprom;
1641 u8 led_ctrl, led_g_mode, led_r_mode;
1642
1643 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1644 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1645 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1646 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1647 } else {
1648 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1649 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1650 }
1651 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1652
1653 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1654 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1655 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1656 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1657 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1658 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1659 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1660 if (led_ctrl == 0 || led_ctrl > 0x40) {
1661 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1662 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1663 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1664 } else {
1665 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1666 (led_g_mode << 2) | led_r_mode, 1);
1667 }
1668 }
1669}
1670
d96aa640
RJH		 1671static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1672 enum antenna ant)
1673{
1674 u32 reg;
1675 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1676 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1677
1678 if (rt2x00_is_pci(rt2x00dev)) {
1679 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1680 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1681 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1682 } else if (rt2x00_is_usb(rt2x00dev))
1683 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1684 eesk_pin, 0);
1685
99bdf51a
GW		 1686 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1687 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1688 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1689 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1690}
1691
f4450616
BZ		 1692void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1693{
1694 u8 r1;
1695 u8 r3;
d96aa640 1696 u16 eeprom;
f4450616
BZ		 1697
1698 rt2800_bbp_read(rt2x00dev, 1, &r1);
1699 rt2800_bbp_read(rt2x00dev, 3, &r3);
1700
872834df
GW		 1701 if (rt2x00_rt(rt2x00dev, RT3572) &&
1702 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1703 rt2800_config_3572bt_ant(rt2x00dev);
1704
f4450616
BZ		 1705 /*
1706 * Configure the TX antenna.
1707 */
d96aa640 1708 switch (ant->tx_chain_num) {
f4450616
BZ		 1709 case 1:
1710 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1711 break;
1712 case 2:
872834df
GW		 1713 if (rt2x00_rt(rt2x00dev, RT3572) &&
1714 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1715 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1716 else
1717 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1718 break;
1719 case 3:
e22557f2 1720 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1721 break;
1722 }
1723
1724 /*
1725 * Configure the RX antenna.
1726 */
d96aa640 1727 switch (ant->rx_chain_num) {
f4450616 1728 case 1:
d96aa640
RJH		 1729 if (rt2x00_rt(rt2x00dev, RT3070) ||
1730 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1731 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1732 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1733 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1734 EEPROM_NIC_CONF1, &eeprom);
1735 if (rt2x00_get_field16(eeprom,
1736 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1737 rt2800_set_ant_diversity(rt2x00dev,
1738 rt2x00dev->default_ant.rx);
1739 }
f4450616
BZ		 1740 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1741 break;
1742 case 2:
872834df
GW		 1743 if (rt2x00_rt(rt2x00dev, RT3572) &&
1744 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1745 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1746 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1747 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1748 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1749 } else {
1750 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1751 }
f4450616
BZ		 1752 break;
1753 case 3:
1754 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1755 break;
1756 }
1757
1758 rt2800_bbp_write(rt2x00dev, 3, r3);
1759 rt2800_bbp_write(rt2x00dev, 1, r1);
1760}
1761EXPORT_SYMBOL_GPL(rt2800_config_ant);
1762
1763static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1764 struct rt2x00lib_conf *libconf)
1765{
1766 u16 eeprom;
1767 short lna_gain;
1768
1769 if (libconf->rf.channel <= 14) {
3e38d3da 1770 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1771 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1772 } else if (libconf->rf.channel <= 64) {
3e38d3da 1773 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1774 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1775 } else if (libconf->rf.channel <= 128) {
3e38d3da 1776 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
f4450616
BZ		 1777 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1778 } else {
3e38d3da 1779 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
f4450616
BZ		 1780 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1781 }
1782
1783 rt2x00dev->lna_gain = lna_gain;
1784}
1785
06855ef4
GW		 1786static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1787 struct ieee80211_conf *conf,
1788 struct rf_channel *rf,
1789 struct channel_info *info)
f4450616
BZ		 1790{
1791 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1792
d96aa640 1793 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1794 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1795
d96aa640 1796 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1797 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1798 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1799 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1800 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1801
1802 if (rf->channel > 14) {
1803 /*
1804 * When TX power is below 0, we should increase it by 7 to
25985edc 1805 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1806 * However this means that values between 0 and 7 have
1807 * double meaning, and we should set a 7DBm boost flag.
1808 */
1809 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1810 (info->default_power1 >= 0));
f4450616 1811
8d1331b3
ID		 1812 if (info->default_power1 < 0)
1813 info->default_power1 += 7;
f4450616 1814
8d1331b3 1815 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1816
1817 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1818 (info->default_power2 >= 0));
f4450616 1819
8d1331b3
ID		 1820 if (info->default_power2 < 0)
1821 info->default_power2 += 7;
f4450616 1822
8d1331b3 1823 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1824 } else {
8d1331b3
ID		 1825 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1826 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1827 }
1828
1829 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1830
1831 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1832 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1833 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1834 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1835
1836 udelay(200);
1837
1838 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1839 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1840 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1841 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1842
1843 udelay(200);
1844
1845 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1846 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1847 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1848 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1849}
1850
06855ef4
GW		 1851static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1852 struct ieee80211_conf *conf,
1853 struct rf_channel *rf,
1854 struct channel_info *info)
f4450616 1855{
3a1c0128 1856 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1857 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1858
1859 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1860
1861 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1862 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1863 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1864
1865 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1866 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1867 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1868
1869 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1870 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1871 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1872
5a673964 1873 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1874 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1875 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1876
1877 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1878 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 1879 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1880 rt2x00dev->default_ant.rx_chain_num <= 1);
1881 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1882 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 1883 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 1884 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1885 rt2x00dev->default_ant.tx_chain_num <= 1);
1886 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1887 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 1888 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1889
3e0c7643
SG		 1890 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1891 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1892 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1893 msleep(1);
1894 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1895 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1896
f4450616
BZ		 1897 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1898 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1899 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1900
f1f12f98
SG		 1901 if (rt2x00_rt(rt2x00dev, RT3390)) {
1902 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1903 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1904 } else {
3a1c0128
GW		 1905 if (conf_is_ht40(conf)) {
1906 calib_tx = drv_data->calibration_bw40;
1907 calib_rx = drv_data->calibration_bw40;
1908 } else {
1909 calib_tx = drv_data->calibration_bw20;
1910 calib_rx = drv_data->calibration_bw20;
1911 }
f1f12f98
SG		 1912 }
1913
1914 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1915 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1916 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1917
1918 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1919 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1920 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1921
71976907 1922 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1923 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1924 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1925
1926 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1927 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1928 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1929 msleep(1);
1930 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1931 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1932}
1933
872834df
GW		 1934static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1935 struct ieee80211_conf *conf,
1936 struct rf_channel *rf,
1937 struct channel_info *info)
1938{
3a1c0128 1939 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1940 u8 rfcsr;
1941 u32 reg;
1942
1943 if (rf->channel <= 14) {
5d137dff
GW		 1944 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1945 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1946 } else {
1947 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1948 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1949 }
1950
1951 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1952 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1953
1954 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1955 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1956 if (rf->channel <= 14)
1957 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1958 else
1959 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1960 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1961
1962 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1963 if (rf->channel <= 14)
1964 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1965 else
1966 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1967 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1968
1969 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1970 if (rf->channel <= 14) {
1971 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1972 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1973 info->default_power1);
872834df
GW		 1974 } else {
1975 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1976 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1977 (info->default_power1 & 0x3) |
1978 ((info->default_power1 & 0xC) << 1));
1979 }
1980 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1981
1982 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1983 if (rf->channel <= 14) {
1984 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1985 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1986 info->default_power2);
872834df
GW		 1987 } else {
1988 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1989 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1990 (info->default_power2 & 0x3) |
1991 ((info->default_power2 & 0xC) << 1));
1992 }
1993 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1994
1995 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1996 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1997 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1998 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1999 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2000 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2001 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 2002 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2003 if (rf->channel <= 14) {
2004 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2005 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2006 }
2007 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2008 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2009 } else {
2010 switch (rt2x00dev->default_ant.tx_chain_num) {
2011 case 1:
2012 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2013 case 2:
2014 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2015 break;
2016 }
2017
2018 switch (rt2x00dev->default_ant.rx_chain_num) {
2019 case 1:
2020 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2021 case 2:
2022 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2023 break;
2024 }
2025 }
2026 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2027
2028 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2029 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2030 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2031
3a1c0128
GW		 2032 if (conf_is_ht40(conf)) {
2033 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2034 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2035 } else {
2036 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2037 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2038 }
872834df
GW		 2039
2040 if (rf->channel <= 14) {
2041 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2042 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2043 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2044 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2045 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2046 rfcsr = 0x4c;
2047 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2048 drv_data->txmixer_gain_24g);
2049 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2050 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2051 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2052 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2053 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2054 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2055 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2056 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2057 } else {
58b8ae14
GW		 2058 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2059 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2060 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2061 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2062 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2063 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2064 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2065 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2066 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2067 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2068 rfcsr = 0x7a;
2069 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2070 drv_data->txmixer_gain_5g);
2071 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2072 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2073 if (rf->channel <= 64) {
2074 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2075 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2076 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2077 } else if (rf->channel <= 128) {
2078 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2079 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2080 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2081 } else {
2082 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2083 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2084 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2085 }
2086 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2087 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2088 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2089 }
2090
99bdf51a
GW		 2091 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2092 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2093 if (rf->channel <= 14)
99bdf51a 2094 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2095 else
99bdf51a
GW		 2096 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2097 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2098
2099 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2100 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2101 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2102}
60687ba7 2103
7573cb5b 2104#define POWER_BOUND 0x27
8f821098 2105#define POWER_BOUND_5G 0x2b
7573cb5b 2106#define FREQ_OFFSET_BOUND 0x5f
60687ba7 2107
0c9e5fb9
SG		 2108static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2109{
2110 u8 rfcsr;
2111
2112 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2113 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2114 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2115 else
2116 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2117 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2118}
2119
a89534ed
WH		 2120static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2121 struct ieee80211_conf *conf,
2122 struct rf_channel *rf,
2123 struct channel_info *info)
2124{
2125 u8 rfcsr;
2126
2127 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2128 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2129 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2130 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2131 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2132
2133 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2134 if (info->default_power1 > POWER_BOUND)
2135 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2136 else
2137 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2138 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2139
0c9e5fb9 2140 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2141
2142 if (rf->channel <= 14) {
2143 if (rf->channel == 6)
2144 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2145 else
2146 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2147
2148 if (rf->channel >= 1 && rf->channel <= 6)
2149 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2150 else if (rf->channel >= 7 && rf->channel <= 11)
2151 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2152 else if (rf->channel >= 12 && rf->channel <= 14)
2153 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2154 }
2155}
2156
03839951
DG		 2157static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2158 struct ieee80211_conf *conf,
2159 struct rf_channel *rf,
2160 struct channel_info *info)
2161{
2162 u8 rfcsr;
2163
2164 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2165 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2166
2167 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2168 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2169 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2170
2171 if (info->default_power1 > POWER_BOUND)
2172 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2173 else
2174 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2175
2176 if (info->default_power2 > POWER_BOUND)
2177 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2178 else
2179 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2180
0c9e5fb9 2181 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2182
2183 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2184 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2185 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2186
2187 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2188 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2189 else
2190 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2191
2192 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2193 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2194 else
2195 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2196
2197 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2198 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2199
2200 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2201
2202 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2203}
2204
60687ba7 2205static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2206 struct ieee80211_conf *conf,
2207 struct rf_channel *rf,
2208 struct channel_info *info)
2209{
2210 u8 rfcsr;
adde5882
GJ		 2211
2212 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2213 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2214 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2215 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2216 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2217
2218 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2219 if (info->default_power1 > POWER_BOUND)
2220 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2221 else
2222 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2223 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2224
cff3d1f0
ZL		 2225 if (rt2x00_rt(rt2x00dev, RT5392)) {
2226 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2227 if (info->default_power1 > POWER_BOUND)
2228 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2229 else
2230 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2231 info->default_power2);
2232 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2233 }
2234
adde5882 2235 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2236 if (rt2x00_rt(rt2x00dev, RT5392)) {
2237 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2238 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2239 }
adde5882
GJ		 2240 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2241 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2242 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2243 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2244 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2245
0c9e5fb9 2246 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2247
adde5882
GJ		 2248 if (rf->channel <= 14) {
2249 int idx = rf->channel-1;
2250
fdbc7b0a 2251 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2252 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2253 /* r55/r59 value array of channel 1~14 */
2254 static const char r55_bt_rev[] = {0x83, 0x83,
2255 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2256 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2257 static const char r59_bt_rev[] = {0x0e, 0x0e,
2258 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2259 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2260
2261 rt2800_rfcsr_write(rt2x00dev, 55,
2262 r55_bt_rev[idx]);
2263 rt2800_rfcsr_write(rt2x00dev, 59,
2264 r59_bt_rev[idx]);
2265 } else {
2266 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2267 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2268 0x88, 0x88, 0x86, 0x85, 0x84};
2269
2270 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2271 }
2272 } else {
2273 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2274 static const char r55_nonbt_rev[] = {0x23, 0x23,
2275 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2276 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2277 static const char r59_nonbt_rev[] = {0x07, 0x07,
2278 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2279 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2280
2281 rt2800_rfcsr_write(rt2x00dev, 55,
2282 r55_nonbt_rev[idx]);
2283 rt2800_rfcsr_write(rt2x00dev, 59,
2284 r59_nonbt_rev[idx]);
2ed71884 2285 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2286 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2287 static const char r59_non_bt[] = {0x8f, 0x8f,
2288 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2289 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2290
2291 rt2800_rfcsr_write(rt2x00dev, 59,
2292 r59_non_bt[idx]);
2293 }
2294 }
2295 }
60687ba7
RST		 2296}
2297
8f821098
SG		 2298static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2299 struct ieee80211_conf *conf,
2300 struct rf_channel *rf,
2301 struct channel_info *info)
2302{
2303 u8 rfcsr, ep_reg;
d5ae7a6b 2304 u32 reg;
8f821098
SG		 2305 int power_bound;
2306
2307 /* TODO */
2308 const bool is_11b = false;
2309 const bool is_type_ep = false;
2310
d5ae7a6b
SG		 2311 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2312 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2313 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2314 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2315
2316 /* Order of values on rf_channel entry: N, K, mod, R */
2317 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2318
2319 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2320 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2321 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2322 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2323 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2324
2325 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2326 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2327 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2328 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2329
2330 if (rf->channel <= 14) {
2331 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2332 /* FIXME: RF11 owerwrite ? */
2333 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2334 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2335 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2336 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2337 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2338 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2339 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2340 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2341 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2342 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2343 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2344 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2345 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2346 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2347 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2348 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2349 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2350 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2351 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2352 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2353 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2354 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2355 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2356 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2357 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2358 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2359 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2360 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2361
2362 /* TODO RF27 <- tssi */
2363
2364 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2365 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2366 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2367
2368 if (is_11b) {
2369 /* CCK */
2370 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2371 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2372 if (is_type_ep)
2373 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2374 else
2375 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2376 } else {
2377 /* OFDM */
2378 if (is_type_ep)
2379 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2380 else
2381 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2382 }
2383
2384 power_bound = POWER_BOUND;
2385 ep_reg = 0x2;
2386 } else {
2387 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2388 /* FIMXE: RF11 overwrite */
2389 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2390 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2391 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2392 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2393 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2394 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2395 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2396 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2397 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2398 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2399 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2400 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2401 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2402 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2403
2404 /* TODO RF27 <- tssi */
2405
2406 if (rf->channel >= 36 && rf->channel <= 64) {
2407
2408 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2409 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2410 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2411 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2412 if (rf->channel <= 50)
2413 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2414 else if (rf->channel >= 52)
2415 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2416 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2417 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2418 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2419 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2420 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2421 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2422 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2423 if (rf->channel <= 50) {
2424 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2425 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2426 } else if (rf->channel >= 52) {
2427 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2428 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2429 }
2430
2431 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2432 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2433 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2434
2435 } else if (rf->channel >= 100 && rf->channel <= 165) {
2436
2437 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2438 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2439 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2440 if (rf->channel <= 153) {
2441 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2442 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2443 } else if (rf->channel >= 155) {
2444 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2445 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2446 }
2447 if (rf->channel <= 138) {
2448 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2449 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2450 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2451 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2452 } else if (rf->channel >= 140) {
2453 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2454 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2455 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2456 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2457 }
2458 if (rf->channel <= 124)
2459 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2460 else if (rf->channel >= 126)
2461 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2462 if (rf->channel <= 138)
2463 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2464 else if (rf->channel >= 140)
2465 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2466 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2467 if (rf->channel <= 138)
2468 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2469 else if (rf->channel >= 140)
2470 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2471 if (rf->channel <= 128)
2472 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2473 else if (rf->channel >= 130)
2474 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2475 if (rf->channel <= 116)
2476 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2477 else if (rf->channel >= 118)
2478 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2479 if (rf->channel <= 138)
2480 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2481 else if (rf->channel >= 140)
2482 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2483 if (rf->channel <= 116)
2484 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2485 else if (rf->channel >= 118)
2486 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2487 }
2488
2489 power_bound = POWER_BOUND_5G;
2490 ep_reg = 0x3;
2491 }
2492
2493 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2494 if (info->default_power1 > power_bound)
2495 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2496 else
2497 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2498 if (is_type_ep)
2499 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2500 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2501
2502 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2503 if (info->default_power2 > power_bound)
8f821098
SG		 2504 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2505 else
2506 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2507 if (is_type_ep)
2508 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2509 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2510
2511 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2512 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2513 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2514
2515 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2516 rt2x00dev->default_ant.tx_chain_num >= 1);
2517 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2518 rt2x00dev->default_ant.tx_chain_num == 2);
2519 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2520
2521 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2522 rt2x00dev->default_ant.rx_chain_num >= 1);
2523 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2524 rt2x00dev->default_ant.rx_chain_num == 2);
2525 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2526
2527 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2528 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2529
2530 if (conf_is_ht40(conf))
2531 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2532 else
2533 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2534
2535 if (!is_11b) {
2536 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2537 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2538 }
2539
2540 /* TODO proper frequency adjustment */
0c9e5fb9 2541 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2542
2543 /* TODO merge with others */
2544 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2545 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2546 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2547
2548 /* BBP settings */
2549 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2550 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2551 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2552
2553 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2554 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2555 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2556 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2557
2558 /* GLRT band configuration */
2559 rt2800_bbp_write(rt2x00dev, 195, 128);
2560 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2561 rt2800_bbp_write(rt2x00dev, 195, 129);
2562 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2563 rt2800_bbp_write(rt2x00dev, 195, 130);
2564 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2565 rt2800_bbp_write(rt2x00dev, 195, 131);
2566 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2567 rt2800_bbp_write(rt2x00dev, 195, 133);
2568 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2569 rt2800_bbp_write(rt2x00dev, 195, 124);
2570 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2571}
2572
5bc2dd06
SG		 2573static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2574 const unsigned int word,
2575 const u8 value)
2576{
2577 u8 chain, reg;
2578
2579 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2580 rt2800_bbp_read(rt2x00dev, 27, &reg);
2581 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2582 rt2800_bbp_write(rt2x00dev, 27, reg);
2583
2584 rt2800_bbp_write(rt2x00dev, word, value);
2585 }
2586}
2587
8756130b
SG		 2588static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2589{
2590 u8 cal;
2591
415e3f2f 2592 /* TX0 IQ Gain */
8756130b 2593 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 2594 if (channel <= 14)
2595 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2596 else if (channel >= 36 && channel <= 64)
2597 cal = rt2x00_eeprom_byte(rt2x00dev,
2598 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2599 else if (channel >= 100 && channel <= 138)
2600 cal = rt2x00_eeprom_byte(rt2x00dev,
2601 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2602 else if (channel >= 140 && channel <= 165)
2603 cal = rt2x00_eeprom_byte(rt2x00dev,
2604 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2605 else
2606 cal = 0;
8756130b
SG		 2607 rt2800_bbp_write(rt2x00dev, 159, cal);
2608
415e3f2f 2609 /* TX0 IQ Phase */
8756130b 2610 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 2611 if (channel <= 14)
2612 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2613 else if (channel >= 36 && channel <= 64)
2614 cal = rt2x00_eeprom_byte(rt2x00dev,
2615 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2616 else if (channel >= 100 && channel <= 138)
2617 cal = rt2x00_eeprom_byte(rt2x00dev,
2618 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2619 else if (channel >= 140 && channel <= 165)
2620 cal = rt2x00_eeprom_byte(rt2x00dev,
2621 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2622 else
2623 cal = 0;
8756130b
SG		 2624 rt2800_bbp_write(rt2x00dev, 159, cal);
2625
415e3f2f 2626 /* TX1 IQ Gain */
8756130b 2627 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 2628 if (channel <= 14)
2629 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2630 else if (channel >= 36 && channel <= 64)
2631 cal = rt2x00_eeprom_byte(rt2x00dev,
2632 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2633 else if (channel >= 100 && channel <= 138)
2634 cal = rt2x00_eeprom_byte(rt2x00dev,
2635 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2636 else if (channel >= 140 && channel <= 165)
2637 cal = rt2x00_eeprom_byte(rt2x00dev,
2638 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2639 else
2640 cal = 0;
8756130b
SG		 2641 rt2800_bbp_write(rt2x00dev, 159, cal);
2642
415e3f2f 2643 /* TX1 IQ Phase */
8756130b 2644 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 2645 if (channel <= 14)
2646 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2647 else if (channel >= 36 && channel <= 64)
2648 cal = rt2x00_eeprom_byte(rt2x00dev,
2649 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2650 else if (channel >= 100 && channel <= 138)
2651 cal = rt2x00_eeprom_byte(rt2x00dev,
2652 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2653 else if (channel >= 140 && channel <= 165)
2654 cal = rt2x00_eeprom_byte(rt2x00dev,
2655 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2656 else
2657 cal = 0;
8756130b
SG		 2658 rt2800_bbp_write(rt2x00dev, 159, cal);
2659
415e3f2f
SG		 2660 /* FIXME: possible RX0, RX1 callibration ? */
2661
8756130b
SG		 2662 /* RF IQ compensation control */
2663 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2664 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2665 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2666
2667 /* RF IQ imbalance compensation control */
2668 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 2669 cal = rt2x00_eeprom_byte(rt2x00dev,
2670 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 2671 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2672}
2673
f4450616
BZ		 2674static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2675 struct ieee80211_conf *conf,
2676 struct rf_channel *rf,
2677 struct channel_info *info)
2678{
2679 u32 reg;
2680 unsigned int tx_pin;
a89534ed 2681 u8 bbp, rfcsr;
f4450616 2682
46323e11 2683 if (rf->channel <= 14) {
8d1331b3
ID		 2684 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2685 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2686 } else {
8d1331b3
ID		 2687 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2688 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2689 }
2690
5aa57015
GW		 2691 switch (rt2x00dev->chip.rf) {
2692 case RF2020:
2693 case RF3020:
2694 case RF3021:
2695 case RF3022:
2696 case RF3320:
06855ef4 2697 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2698 break;
2699 case RF3052:
872834df 2700 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2701 break;
a89534ed
WH		 2702 case RF3290:
2703 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2704 break;
03839951
DG		 2705 case RF3322:
2706 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2707 break;
ccf91bd6 2708 case RF5360:
5aa57015 2709 case RF5370:
2ed71884 2710 case RF5372:
5aa57015 2711 case RF5390:
cff3d1f0 2712 case RF5392:
adde5882 2713 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 2714 break;
8f821098
SG		 2715 case RF5592:
2716 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2717 break;
5aa57015 2718 default:
06855ef4 2719 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2720 }
f4450616 2721
a89534ed 2722 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2723 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2724 rt2x00_rf(rt2x00dev, RF5360) ||
2725 rt2x00_rf(rt2x00dev, RF5370) ||
2726 rt2x00_rf(rt2x00dev, RF5372) ||
2727 rt2x00_rf(rt2x00dev, RF5390) ||
2728 rt2x00_rf(rt2x00dev, RF5392)) {
2729 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2730 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2731 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2732 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2733
2734 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2735 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 2736 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2737 }
2738
f4450616
BZ		 2739 /*
2740 * Change BBP settings
2741 */
03839951
DG		 2742 if (rt2x00_rt(rt2x00dev, RT3352)) {
2743 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 2744 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 2745 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 2746 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951
DG		 2747 } else {
2748 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2749 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2750 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2751 rt2800_bbp_write(rt2x00dev, 86, 0);
2752 }
f4450616
BZ		 2753
2754 if (rf->channel <= 14) {
2ed71884 2755 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 2756 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2757 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2758 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2759 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2760 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2761 } else {
2762 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2763 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2764 }
f4450616
BZ		 2765 }
2766 } else {
872834df
GW		 2767 if (rt2x00_rt(rt2x00dev, RT3572))
2768 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2769 else
2770 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2771
7dab73b3 2772 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2773 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2774 else
2775 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2776 }
2777
2778 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2779 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2780 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2781 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2782 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2783
872834df
GW		 2784 if (rt2x00_rt(rt2x00dev, RT3572))
2785 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2786
f4450616
BZ		 2787 tx_pin = 0;
2788
bb16d488
GJ		 2789 switch (rt2x00dev->default_ant.tx_chain_num) {
2790 case 3:
2791 /* Turn on tertiary PAs */
2792 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
2793 rf->channel > 14);
2794 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
2795 rf->channel <= 14);
2796 /* fall-through */
2797 case 2:
2798 /* Turn on secondary PAs */
65f31b5e
GW		 2799 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2800 rf->channel > 14);
2801 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2802 rf->channel <= 14);
bb16d488
GJ		 2803 /* fall-through */
2804 case 1:
2805 /* Turn on primary PAs */
2806 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
2807 rf->channel > 14);
2808 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2809 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2810 else
2811 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2812 rf->channel <= 14);
2813 break;
f4450616
BZ		 2814 }
2815
bb16d488
GJ		 2816 switch (rt2x00dev->default_ant.rx_chain_num) {
2817 case 3:
2818 /* Turn on tertiary LNAs */
2819 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
2820 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
2821 /* fall-through */
2822 case 2:
2823 /* Turn on secondary LNAs */
f4450616
BZ		 2824 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2825 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 2826 /* fall-through */
2827 case 1:
2828 /* Turn on primary LNAs */
2829 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2830 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2831 break;
f4450616
BZ		 2832 }
2833
f4450616
BZ		 2834 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2835 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 2836
2837 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2838
872834df
GW		 2839 if (rt2x00_rt(rt2x00dev, RT3572))
2840 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2841
6803141b
SG		 2842 if (rt2x00_rt(rt2x00dev, RT5592)) {
2843 rt2800_bbp_write(rt2x00dev, 195, 141);
2844 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2845
8ba0ebf3
SG		 2846 /* AGC init */
2847 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2848 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2849
8756130b 2850 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 2851 }
2852
f4450616
BZ		 2853 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2854 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2855 rt2800_bbp_write(rt2x00dev, 4, bbp);
2856
2857 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2858 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2859 rt2800_bbp_write(rt2x00dev, 3, bbp);
2860
8d0c9b65 2861 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2862 if (conf_is_ht40(conf)) {
2863 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2864 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2865 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2866 } else {
2867 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2868 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2869 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2870 }
2871 }
2872
2873 msleep(1);
977206d7
HS		 2874
2875 /*
2876 * Clear channel statistic counters
2877 */
2878 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2879 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2880 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2881
2882 /*
2883 * Clear update flag
2884 */
2885 if (rt2x00_rt(rt2x00dev, RT3352)) {
2886 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2887 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2888 rt2800_bbp_write(rt2x00dev, 49, bbp);
2889 }
f4450616
BZ		 2890}
2891
9e33a355
HS		 2892static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2893{
2894 u8 tssi_bounds[9];
2895 u8 current_tssi;
2896 u16 eeprom;
2897 u8 step;
2898 int i;
2899
2900 /*
2901 * Read TSSI boundaries for temperature compensation from
2902 * the EEPROM.
2903 *
2904 * Array idx 0 1 2 3 4 5 6 7 8
2905 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2906 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2907 */
2908 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 2909 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 2910 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2911 EEPROM_TSSI_BOUND_BG1_MINUS4);
2912 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2913 EEPROM_TSSI_BOUND_BG1_MINUS3);
2914
3e38d3da 2915 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 2916 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2917 EEPROM_TSSI_BOUND_BG2_MINUS2);
2918 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2919 EEPROM_TSSI_BOUND_BG2_MINUS1);
2920
3e38d3da 2921 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 2922 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2923 EEPROM_TSSI_BOUND_BG3_REF);
2924 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2925 EEPROM_TSSI_BOUND_BG3_PLUS1);
2926
3e38d3da 2927 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 2928 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2929 EEPROM_TSSI_BOUND_BG4_PLUS2);
2930 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2931 EEPROM_TSSI_BOUND_BG4_PLUS3);
2932
3e38d3da 2933 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 2934 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2935 EEPROM_TSSI_BOUND_BG5_PLUS4);
2936
2937 step = rt2x00_get_field16(eeprom,
2938 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2939 } else {
3e38d3da 2940 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 2941 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2942 EEPROM_TSSI_BOUND_A1_MINUS4);
2943 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2944 EEPROM_TSSI_BOUND_A1_MINUS3);
2945
3e38d3da 2946 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 2947 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2948 EEPROM_TSSI_BOUND_A2_MINUS2);
2949 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2950 EEPROM_TSSI_BOUND_A2_MINUS1);
2951
3e38d3da 2952 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 2953 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2954 EEPROM_TSSI_BOUND_A3_REF);
2955 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2956 EEPROM_TSSI_BOUND_A3_PLUS1);
2957
3e38d3da 2958 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 2959 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2960 EEPROM_TSSI_BOUND_A4_PLUS2);
2961 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2962 EEPROM_TSSI_BOUND_A4_PLUS3);
2963
3e38d3da 2964 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 2965 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2966 EEPROM_TSSI_BOUND_A5_PLUS4);
2967
2968 step = rt2x00_get_field16(eeprom,
2969 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2970 }
2971
2972 /*
2973 * Check if temperature compensation is supported.
2974 */
bf7e1abe 2975 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 2976 return 0;
2977
2978 /*
2979 * Read current TSSI (BBP 49).
2980 */
2981 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2982
2983 /*
2984 * Compare TSSI value (BBP49) with the compensation boundaries
2985 * from the EEPROM and increase or decrease tx power.
2986 */
2987 for (i = 0; i <= 3; i++) {
2988 if (current_tssi > tssi_bounds[i])
2989 break;
2990 }
2991
2992 if (i == 4) {
2993 for (i = 8; i >= 5; i--) {
2994 if (current_tssi < tssi_bounds[i])
2995 break;
2996 }
2997 }
2998
2999 return (i - 4) * step;
3000}
3001
e90c54b2
RJH		 3002static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3003 enum ieee80211_band band)
3004{
3005 u16 eeprom;
3006 u8 comp_en;
3007 u8 comp_type;
75faae8b 3008 int comp_value = 0;
e90c54b2 3009
3e38d3da 3010 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3011
75faae8b
HS		 3012 /*
3013 * HT40 compensation not required.
3014 */
3015 if (eeprom == 0xffff ||
3016 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3017 return 0;
3018
3019 if (band == IEEE80211_BAND_2GHZ) {
3020 comp_en = rt2x00_get_field16(eeprom,
3021 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3022 if (comp_en) {
3023 comp_type = rt2x00_get_field16(eeprom,
3024 EEPROM_TXPOWER_DELTA_TYPE_2G);
3025 comp_value = rt2x00_get_field16(eeprom,
3026 EEPROM_TXPOWER_DELTA_VALUE_2G);
3027 if (!comp_type)
3028 comp_value = -comp_value;
3029 }
3030 } else {
3031 comp_en = rt2x00_get_field16(eeprom,
3032 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3033 if (comp_en) {
3034 comp_type = rt2x00_get_field16(eeprom,
3035 EEPROM_TXPOWER_DELTA_TYPE_5G);
3036 comp_value = rt2x00_get_field16(eeprom,
3037 EEPROM_TXPOWER_DELTA_VALUE_5G);
3038 if (!comp_type)
3039 comp_value = -comp_value;
3040 }
3041 }
3042
3043 return comp_value;
3044}
3045
1e4cf249
SG		 3046static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3047 int power_level, int max_power)
3048{
3049 int delta;
3050
3051 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3052 return 0;
3053
3054 /*
3055 * XXX: We don't know the maximum transmit power of our hardware since
3056 * the EEPROM doesn't expose it. We only know that we are calibrated
3057 * to 100% tx power.
3058 *
3059 * Hence, we assume the regulatory limit that cfg80211 calulated for
3060 * the current channel is our maximum and if we are requested to lower
3061 * the value we just reduce our tx power accordingly.
3062 */
3063 delta = power_level - max_power;
3064 return min(delta, 0);
3065}
3066
fa71a160
HS		 3067static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3068 enum ieee80211_band band, int power_level,
3069 u8 txpower, int delta)
e90c54b2 3070{
e90c54b2
RJH		 3071 u16 eeprom;
3072 u8 criterion;
3073 u8 eirp_txpower;
3074 u8 eirp_txpower_criterion;
3075 u8 reg_limit;
e90c54b2 3076
7dab73b3 3077 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 3078 /*
3079 * Check if eirp txpower exceed txpower_limit.
3080 * We use OFDM 6M as criterion and its eirp txpower
3081 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3082 * .11b data rate need add additional 4dbm
3083 * when calculating eirp txpower.
3084 */
022138ca
GJ		 3085 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3086 1, &eeprom);
d9bceaeb
SG		 3087 criterion = rt2x00_get_field16(eeprom,
3088 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3089
3e38d3da 3090 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3091 &eeprom);
e90c54b2
RJH		 3092
3093 if (band == IEEE80211_BAND_2GHZ)
3094 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3095 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3096 else
3097 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3098 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3099
3100 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3101 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3102
3103 reg_limit = (eirp_txpower > power_level) ?
3104 (eirp_txpower - power_level) : 0;
3105 } else
3106 reg_limit = 0;
3107
19f3fa24
SG		 3108 txpower = max(0, txpower + delta - reg_limit);
3109 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3110}
3111
7a66205a
SG		 3112/*
3113 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3114 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3115 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3116 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3117 * Reference per rate transmit power values are located in the EEPROM at
3118 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3119 * current conditions (i.e. band, bandwidth, temperature, user settings).
3120 */
f4450616 3121static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
146c3b0c 3122 struct ieee80211_channel *chan,
9e33a355 3123 int power_level)
f4450616 3124{
cee2c731 3125 u8 txpower, r1;
5e846004 3126 u16 eeprom;
cee2c731
SG		 3127 u32 reg, offset;
3128 int i, is_rate_b, delta, power_ctrl;
146c3b0c 3129 enum ieee80211_band band = chan->band;
2af242e1
HS		 3130
3131 /*
7a66205a
SG		 3132 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3133 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 3134 */
3135 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 3136
9e33a355 3137 /*
7a66205a
SG		 3138 * Calculate temperature compensation. Depends on measurement of current
3139 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3140 * to temperature or maybe other factors) is smaller or bigger than
3141 * expected. We adjust it, based on TSSI reference and boundaries values
3142 * provided in EEPROM.
9e33a355
HS		 3143 */
3144 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 3145
1e4cf249 3146 /*
7a66205a
SG		 3147 * Decrease power according to user settings, on devices with unknown
3148 * maximum tx power. For other devices we take user power_level into
3149 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 3150 */
3151 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3152 chan->max_power);
3153
5e846004 3154 /*
cee2c731
SG		 3155 * BBP_R1 controls TX power for all rates, it allow to set the following
3156 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3157 *
3158 * TODO: we do not use +6 dBm option to do not increase power beyond
3159 * regulatory limit, however this could be utilized for devices with
3160 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 3161 *
3162 * TODO: add different temperature compensation code for RT3290 & RT5390
3163 * to allow to use BBP_R1 for those chips.
3164 */
3165 if (!rt2x00_rt(rt2x00dev, RT3290) &&
3166 !rt2x00_rt(rt2x00dev, RT5390)) {
3167 rt2800_bbp_read(rt2x00dev, 1, &r1);
3168 if (delta <= -12) {
3169 power_ctrl = 2;
3170 delta += 12;
3171 } else if (delta <= -6) {
3172 power_ctrl = 1;
3173 delta += 6;
3174 } else {
3175 power_ctrl = 0;
3176 }
3177 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3178 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 3179 }
8c8d2017 3180
5e846004
HS		 3181 offset = TX_PWR_CFG_0;
3182
3183 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3184 /* just to be safe */
3185 if (offset > TX_PWR_CFG_4)
3186 break;
3187
3188 rt2800_register_read(rt2x00dev, offset, &reg);
3189
3190 /* read the next four txpower values */
022138ca
GJ		 3191 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3192 i, &eeprom);
5e846004 3193
e90c54b2
RJH		 3194 is_rate_b = i ? 0 : 1;
3195 /*
3196 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 3197 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 3198 * TX_PWR_CFG_4: unknown
3199 */
5e846004
HS		 3200 txpower = rt2x00_get_field16(eeprom,
3201 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3202 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3203 power_level, txpower, delta);
e90c54b2 3204 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 3205
e90c54b2
RJH		 3206 /*
3207 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 3208 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 3209 * TX_PWR_CFG_4: unknown
3210 */
5e846004
HS		 3211 txpower = rt2x00_get_field16(eeprom,
3212 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3213 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3214 power_level, txpower, delta);
e90c54b2 3215 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 3216
e90c54b2
RJH		 3217 /*
3218 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 3219 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 3220 * TX_PWR_CFG_4: unknown
3221 */
5e846004
HS		 3222 txpower = rt2x00_get_field16(eeprom,
3223 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3224 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3225 power_level, txpower, delta);
e90c54b2 3226 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 3227
e90c54b2
RJH		 3228 /*
3229 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 3230 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 3231 * TX_PWR_CFG_4: unknown
3232 */
5e846004
HS		 3233 txpower = rt2x00_get_field16(eeprom,
3234 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3235 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3236 power_level, txpower, delta);
e90c54b2 3237 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 3238
3239 /* read the next four txpower values */
022138ca
GJ		 3240 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3241 i + 1, &eeprom);
5e846004 3242
e90c54b2
RJH		 3243 is_rate_b = 0;
3244 /*
3245 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 3246 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3247 * TX_PWR_CFG_4: unknown
3248 */
5e846004
HS		 3249 txpower = rt2x00_get_field16(eeprom,
3250 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 3251 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3252 power_level, txpower, delta);
e90c54b2 3253 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 3254
e90c54b2
RJH		 3255 /*
3256 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 3257 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3258 * TX_PWR_CFG_4: unknown
3259 */
5e846004
HS		 3260 txpower = rt2x00_get_field16(eeprom,
3261 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 3262 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3263 power_level, txpower, delta);
e90c54b2 3264 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 3265
e90c54b2
RJH		 3266 /*
3267 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 3268 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3269 * TX_PWR_CFG_4: unknown
3270 */
5e846004
HS		 3271 txpower = rt2x00_get_field16(eeprom,
3272 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 3273 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3274 power_level, txpower, delta);
e90c54b2 3275 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 3276
e90c54b2
RJH		 3277 /*
3278 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 3279 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 3280 * TX_PWR_CFG_4: unknown
3281 */
5e846004
HS		 3282 txpower = rt2x00_get_field16(eeprom,
3283 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 3284 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 3285 power_level, txpower, delta);
e90c54b2 3286 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 3287
3288 rt2800_register_write(rt2x00dev, offset, reg);
3289
3290 /* next TX_PWR_CFG register */
3291 offset += 4;
3292 }
f4450616
BZ		 3293}
3294
9e33a355
HS		 3295void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3296{
675a0b04 3297 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 3298 rt2x00dev->tx_power);
3299}
3300EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3301
2e9c43dd
JL		 3302void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3303{
3304 u32 tx_pin;
3305 u8 rfcsr;
3306
3307 /*
3308 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3309 * designed to be controlled in oscillation frequency by a voltage
3310 * input. Maybe the temperature will affect the frequency of
3311 * oscillation to be shifted. The VCO calibration will be called
3312 * periodically to adjust the frequency to be precision.
3313 */
3314
3315 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3316 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3317 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3318
3319 switch (rt2x00dev->chip.rf) {
3320 case RF2020:
3321 case RF3020:
3322 case RF3021:
3323 case RF3022:
3324 case RF3320:
3325 case RF3052:
3326 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3327 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3328 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3329 break;
a89534ed 3330 case RF3290:
ccf91bd6 3331 case RF5360:
2e9c43dd
JL		 3332 case RF5370:
3333 case RF5372:
3334 case RF5390:
cff3d1f0 3335 case RF5392:
2e9c43dd 3336 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3337 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 3338 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3339 break;
3340 default:
3341 return;
3342 }
3343
3344 mdelay(1);
3345
3346 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3347 if (rt2x00dev->rf_channel <= 14) {
3348 switch (rt2x00dev->default_ant.tx_chain_num) {
3349 case 3:
3350 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3351 /* fall through */
3352 case 2:
3353 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3354 /* fall through */
3355 case 1:
3356 default:
3357 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3358 break;
3359 }
3360 } else {
3361 switch (rt2x00dev->default_ant.tx_chain_num) {
3362 case 3:
3363 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3364 /* fall through */
3365 case 2:
3366 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3367 /* fall through */
3368 case 1:
3369 default:
3370 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3371 break;
3372 }
3373 }
3374 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3375
3376}
3377EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3378
f4450616
BZ		 3379static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3380 struct rt2x00lib_conf *libconf)
3381{
3382 u32 reg;
3383
3384 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3385 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3386 libconf->conf->short_frame_max_tx_count);
3387 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3388 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 3389 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3390}
3391
3392static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3393 struct rt2x00lib_conf *libconf)
3394{
3395 enum dev_state state =
3396 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3397 STATE_SLEEP : STATE_AWAKE;
3398 u32 reg;
3399
3400 if (state == STATE_SLEEP) {
3401 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3402
3403 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3404 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3405 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3406 libconf->conf->listen_interval - 1);
3407 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3408 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3409
3410 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3411 } else {
f4450616
BZ		 3412 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3413 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3414 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3415 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3416 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 3417
3418 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 3419 }
3420}
3421
3422void rt2800_config(struct rt2x00_dev *rt2x00dev,
3423 struct rt2x00lib_conf *libconf,
3424 const unsigned int flags)
3425{
3426 /* Always recalculate LNA gain before changing configuration */
3427 rt2800_config_lna_gain(rt2x00dev, libconf);
3428
e90c54b2 3429 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 3430 rt2800_config_channel(rt2x00dev, libconf->conf,
3431 &libconf->rf, &libconf->channel);
675a0b04 3432 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3433 libconf->conf->power_level);
e90c54b2 3434 }
f4450616 3435 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 3436 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 3437 libconf->conf->power_level);
f4450616
BZ		 3438 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3439 rt2800_config_retry_limit(rt2x00dev, libconf);
3440 if (flags & IEEE80211_CONF_CHANGE_PS)
3441 rt2800_config_ps(rt2x00dev, libconf);
3442}
3443EXPORT_SYMBOL_GPL(rt2800_config);
3444
3445/*
3446 * Link tuning
3447 */
3448void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3449{
3450 u32 reg;
3451
3452 /*
3453 * Update FCS error count from register.
3454 */
3455 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3456 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3457}
3458EXPORT_SYMBOL_GPL(rt2800_link_stats);
3459
3460static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3461{
8c6728b0
GW		 3462 u8 vgc;
3463
f4450616 3464 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 3465 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3466 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3467 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3468 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 3469 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 3470 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884 3471 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 3472 rt2x00_rt(rt2x00dev, RT5392) ||
3473 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 3474 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3475 else
3476 vgc = 0x2e + rt2x00dev->lna_gain;
3477 } else { /* 5GHZ band */
d961e447
GW		 3478 if (rt2x00_rt(rt2x00dev, RT3572))
3479 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 3480 else if (rt2x00_rt(rt2x00dev, RT5592))
3481 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 3482 else {
3483 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3484 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3485 else
3486 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3487 }
f4450616
BZ		 3488 }
3489
8c6728b0 3490 return vgc;
f4450616
BZ		 3491}
3492
3493static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3494 struct link_qual *qual, u8 vgc_level)
3495{
3496 if (qual->vgc_level != vgc_level) {
3d81535e
SG		 3497 if (rt2x00_rt(rt2x00dev, RT5592)) {
3498 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3499 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3500 } else
3501 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
f4450616
BZ		 3502 qual->vgc_level = vgc_level;
3503 qual->vgc_level_reg = vgc_level;
3504 }
3505}
3506
3507void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3508{
3509 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3510}
3511EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3512
3513void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3514 const u32 count)
3515{
3d81535e
SG		 3516 u8 vgc;
3517
8d0c9b65 3518 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 3519 return;
f4450616 3520 /*
3d81535e
SG		 3521 * When RSSI is better then -80 increase VGC level with 0x10, except
3522 * for rt5592 chip.
f4450616 3523 */
3d81535e
SG		 3524
3525 vgc = rt2800_get_default_vgc(rt2x00dev);
3526
3527 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3528 vgc += 0x20;
3529 else if (qual->rssi > -80)
3530 vgc += 0x10;
3531
3532 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 3533}
3534EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 3535
3536/*
3537 * Initialization functions.
3538 */
b9a07ae9 3539static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3540{
3541 u32 reg;
d5385bfc 3542 u16 eeprom;
fcf51541 3543 unsigned int i;
e3a896b9 3544 int ret;
fcf51541 3545
f7b395e9 3546 rt2800_disable_wpdma(rt2x00dev);
a9dce149 3547
e3a896b9
GW		 3548 ret = rt2800_drv_init_registers(rt2x00dev);
3549 if (ret)
3550 return ret;
fcf51541
BZ		 3551
3552 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3553 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3554 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3555 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3556 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3557 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3558
3559 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3560 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3561 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3562 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3563 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3564 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3565
3566 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3567 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3568
3569 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3570
3571 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 3572 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 3573 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3574 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3575 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3576 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3577 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3578 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3579
a9dce149
GW		 3580 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3581
3582 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3583 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3584 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3585 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3586
a89534ed
WH		 3587 if (rt2x00_rt(rt2x00dev, RT3290)) {
3588 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3589 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3590 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3591 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3592 }
3593
3594 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3595 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3596 rt2x00_set_field32(&reg, LDO0_EN, 1);
3597 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3598 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3599 }
3600
3601 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3602 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3603 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3604 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3605 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3606
3607 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3608 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3609 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3610
3611 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3612 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3613 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3614 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3615 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3616 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3617
3618 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3619 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3620 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3621 }
3622
64522957 3623 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3624 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3625 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 3626 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 3627
3628 if (rt2x00_rt(rt2x00dev, RT3290))
3629 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3630 0x00000404);
3631 else
3632 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3633 0x00000400);
3634
fcf51541 3635 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 3636 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3637 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3638 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 3639 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
3640 &eeprom);
38c8a566 3641 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3642 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3643 0x0000002c);
3644 else
3645 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3646 0x0000000f);
3647 } else {
3648 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3649 }
d5385bfc 3650 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 3651 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 3652
3653 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3654 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3655 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3656 } else {
3657 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3658 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3659 }
c295a81d
HS		 3660 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3661 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3662 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 3663 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 3664 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3665 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3666 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3667 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 3668 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3669 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3670 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884 3671 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 3672 rt2x00_rt(rt2x00dev, RT5392) ||
3673 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 3674 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3675 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3676 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 3677 } else {
3678 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3679 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3680 }
3681
3682 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3683 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3684 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3685 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3686 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3687 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3688 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3689 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3690 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3691 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3692
3693 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3694 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 3695 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 3696 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3697 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3698
3699 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3700 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 3701 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 3702 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 3703 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 3704 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3705 else
3706 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3707 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3708 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3709 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3710
a9dce149
GW		 3711 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3712 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3713 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3714 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3715 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3716 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3717 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3718 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3719 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3720
fcf51541
BZ		 3721 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3722
a9dce149
GW		 3723 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3724 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3725 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3726 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3727 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3728 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3729 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3730 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3731
fcf51541
BZ		 3732 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3733 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 3734 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 3735 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3736 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 3737 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 3738 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3739 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3740 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3741
3742 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 3743 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3744 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3745 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3746 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3747 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3748 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3749 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3750 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3751 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3752 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3753 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3754
3755 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 3756 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3757 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3758 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3759 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3760 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3761 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3762 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3763 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3764 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3765 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3766 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3767
3768 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3769 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3770 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3771 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3772 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3773 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3774 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3775 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3776 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3777 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3778 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3779 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3780
3781 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3782 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 3783 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3784 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3785 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3786 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3787 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3788 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3789 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3790 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3791 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3792 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3793
3794 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3795 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3796 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3797 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3798 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3799 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3800 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3801 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3802 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3803 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3804 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3805 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3806
3807 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3808 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3809 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3810 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3811 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3812 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3813 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3814 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3815 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3816 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3817 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3818 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3819
cea90e55 3820 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 3821 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3822
3823 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3824 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3825 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3826 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3827 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3830 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3831 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3832 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3833 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3834 }
3835
961621ab
HS		 3836 /*
3837 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3838 * although it is reserved.
3839 */
3840 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3841 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3842 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3843 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3844 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3845 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3846 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3847 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3848 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3849 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3850 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3851 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3852
7641328d
SG		 3853 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3854 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 3855
3856 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3857 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3858 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3859 IEEE80211_MAX_RTS_THRESHOLD);
3860 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3861 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3862
3863 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3864
a21c2ab4
HS		 3865 /*
3866 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3867 * time should be set to 16. However, the original Ralink driver uses
3868 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3869 * connection problems with 11g + CTS protection. Hence, use the same
3870 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3871 */
a9dce149 3872 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3873 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3874 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3875 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3876 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3877 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3878 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3879
fcf51541
BZ		 3880 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3881
3882 /*
3883 * ASIC will keep garbage value after boot, clear encryption keys.
3884 */
3885 for (i = 0; i < 4; i++)
3886 rt2800_register_write(rt2x00dev,
3887 SHARED_KEY_MODE_ENTRY(i), 0);
3888
3889 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3890 rt2800_config_wcid(rt2x00dev, NULL, i);
3891 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3892 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3893 }
3894
3895 /*
3896 * Clear all beacons
fcf51541 3897 */
69cf36a4
HS		 3898 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3899 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3900 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3901 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3902 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3903 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3904 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3905 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3906
cea90e55 3907 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3908 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3909 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3910 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3911 } else if (rt2x00_is_pcie(rt2x00dev)) {
3912 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3913 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3914 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3915 }
3916
3917 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3918 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3919 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3920 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3921 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3922 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3923 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3924 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3925 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3926 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3927
3928 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3929 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3930 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3931 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3932 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3933 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3934 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3935 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3936 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3937 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3938
3939 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3940 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3941 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3942 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3943 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3944 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3945 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3946 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3947 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3948 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3949
3950 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3951 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3952 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3953 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3954 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3955 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3956
47ee3eb1
HS		 3957 /*
3958 * Do not force the BA window size, we use the TXWI to set it
3959 */
3960 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3961 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3962 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3963 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3964
fcf51541
BZ		 3965 /*
3966 * We must clear the error counters.
3967 * These registers are cleared on read,
3968 * so we may pass a useless variable to store the value.
3969 */
3970 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3971 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3972 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3973 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3974 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3975 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3976
9f926fb5
HS		 3977 /*
3978 * Setup leadtime for pre tbtt interrupt to 6ms
3979 */
3980 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3981 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3982 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3983
977206d7
HS		 3984 /*
3985 * Set up channel statistics timer
3986 */
3987 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3988 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3989 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3990 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3991 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3992 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3993 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3994
fcf51541
BZ		 3995 return 0;
3996}
fcf51541
BZ		 3997
3998static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3999{
4000 unsigned int i;
4001 u32 reg;
4002
4003 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4004 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4005 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4006 return 0;
4007
4008 udelay(REGISTER_BUSY_DELAY);
4009 }
4010
ec9c4989 4011 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 4012 return -EACCES;
4013}
4014
4015static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4016{
4017 unsigned int i;
4018 u8 value;
4019
4020 /*
4021 * BBP was enabled after firmware was loaded,
4022 * but we need to reactivate it now.
4023 */
4024 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4025 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4026 msleep(1);
4027
4028 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4029 rt2800_bbp_read(rt2x00dev, 0, &value);
4030 if ((value != 0xff) && (value != 0x00))
4031 return 0;
4032 udelay(REGISTER_BUSY_DELAY);
4033 }
4034
ec9c4989 4035 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 4036 return -EACCES;
4037}
4038
a7bbbe5c
SG		 4039static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
4040{
4041 u8 value;
4042
4043 rt2800_bbp_read(rt2x00dev, 4, &value);
4044 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
4045 rt2800_bbp_write(rt2x00dev, 4, value);
4046}
4047
c2675487
SG		 4048static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
4049{
4050 rt2800_bbp_write(rt2x00dev, 142, 1);
4051 rt2800_bbp_write(rt2x00dev, 143, 57);
4052}
4053
a7bbbe5c
SG		 4054static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
4055{
4056 const u8 glrt_table[] = {
4057 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4058 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4059 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4060 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4061 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4062 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4064 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4065 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4066 };
4067 int i;
4068
4069 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
4070 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
4071 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
4072 }
4073};
4074
624708b8 4075static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 4076{
4077 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4078 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4079 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
4080 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4081 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4082 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4083 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4084 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4085 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
4086 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4087 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4088 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4089 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4090 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4091 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4092 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4093}
4094
5df1ff3a
SG		 4095static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
4096{
4097 u16 eeprom;
4098 u8 value;
4099
4100 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 4101 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 4102 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4103 value |= 0x20;
4104 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4105 value &= ~0x02;
4106 rt2800_bbp_write(rt2x00dev, 138, value);
4107}
4108
dae62957
SG		 4109static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
4110{
b2f8e0bd 4111 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4112
4113 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4114 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4115
4116 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4117 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4118
4119 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4120
4121 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4122 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 4123
4124 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4125
4126 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4127
4128 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4129
4130 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4131
4132 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4133
4134 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4135
4136 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4137
4138 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 4139
4140 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 4141}
4142
39ab3e8b
SG		 4143static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
4144{
e379de12
SG		 4145 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4146 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4147
4148 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4149 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4150 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4151 } else {
4152 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4153 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4154 }
8d97be38
SG		 4155
4156 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4157
4158 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4159
4160 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4161
4162 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4163
4164 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4165 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4166 else
4167 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4168
4169 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4170
4171 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4172
4173 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4174
4175 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4176
4177 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4178
4179 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 4180}
4181
4182static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
4183{
e379de12
SG		 4184 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4185 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4186
4187 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4188 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4189
4190 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4191
4192 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4193 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4194 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4195
4196 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4197
4198 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4199
4200 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4201
4202 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4203
4204 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4205
4206 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4207
4208 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4209 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4210 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
4211 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4212 else
4213 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4214
4215 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4216
4217 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4218
4219 if (rt2x00_rt(rt2x00dev, RT3071) ||
4220 rt2x00_rt(rt2x00dev, RT3090))
4221 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4222}
4223
4224static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
4225{
6addb24e
SG		 4226 u8 value;
4227
c3223573 4228 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4229
4230 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4231
4232 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4233 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4234
4235 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4236
4237 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4238 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4239 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4240 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4241
4242 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 4243
4244 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4245
4246 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4247 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4248 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4249 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4250
4251 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4252
4253 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 4254
4255 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 4256
4257 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 4258
4259 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4260
4261 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4262
4263 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4264
4265 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4266
4267 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 4268
4269 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 4270
4271 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 4272
4273 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4274 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4275 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4276 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4277 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4278 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4279 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4280 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4281 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4282 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4283
4284 rt2800_bbp_read(rt2x00dev, 47, &value);
4285 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4286 rt2800_bbp_write(rt2x00dev, 47, value);
4287
4288 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4289 rt2800_bbp_read(rt2x00dev, 3, &value);
4290 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4291 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4292 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 4293}
4294
4295static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
4296{
29f3a58b
SG		 4297 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4298 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 4299
4300 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 4301
4302 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 4303
4304 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4305 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4306
4307 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4308
4309 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4310 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4311 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4312 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4313
4314 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4315
4316 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4317
4318 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4319 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4320 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 4321
4322 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4323
4324 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4325
4326 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4327
4328 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 4329
4330 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 4331
4332 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4333
4334 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 4335
4336 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4337
4338 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4339
4340 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 4341
4342 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 4343
4344 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 4345
4346 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 4347
4348 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4349 /* Set ITxBF timeout to 0x9c40=1000msec */
4350 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4351 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4352 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4353 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4354 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4355 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4356 /* Reprogram the inband interface to put right values in RXWI */
4357 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4358 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4359 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4360 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4361 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4362 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4363 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4364 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4365
4366 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 4367}
4368
4369static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
4370{
e379de12
SG		 4371 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4372 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4373
4374 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4375 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4376
4377 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4378
4379 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4380 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4381 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4382
4383 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4384
4385 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4386
4387 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4388
4389 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4390
4391 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4392
4393 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4394
4395 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
4396 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4397 else
4398 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 4399
4400 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4401
4402 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4403
4404 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4405}
4406
4407static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
4408{
b2f8e0bd 4409 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4410
4411 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4412 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 4413
4414 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4415 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 4416
4417 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4418
4419 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4420 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4421 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4422
4423 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4424
4425 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 4426
4427 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 4428
4429 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 4430
4431 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4432
4433 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 4434
4435 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 4436
4437 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 4438
4439 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 4440
4441 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 4442}
4443
4444static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
4445{
32ef8f49
SG		 4446 int ant, div_mode;
4447 u16 eeprom;
4448 u8 value;
4449
c3223573 4450 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 4451
4452 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 4453
4454 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4455 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 4456
4457 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 4458
4459 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4460 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4461 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4462 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4463
4464 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 4465
4466 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 4467
4468 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4469 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4470 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 4471
4472 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 4473
4474 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 4475
4476 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 4477
4478 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 4479
4480 if (rt2x00_rt(rt2x00dev, RT5392))
4481 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 4482
4483 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 4484
4485 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 4486
4487 if (rt2x00_rt(rt2x00dev, RT5392)) {
4488 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4489 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4490 }
672d1188
SG		 4491
4492 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 4493
4494 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 4495
4496 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 4497
4498 if (rt2x00_rt(rt2x00dev, RT5390))
4499 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4500 else if (rt2x00_rt(rt2x00dev, RT5392))
4501 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4502 else
4503 WARN_ON(1);
f2b6777c
SG		 4504
4505 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 4506
4507 if (rt2x00_rt(rt2x00dev, RT5392)) {
4508 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4509 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4510 }
5df1ff3a
SG		 4511
4512 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 4513
3e38d3da 4514 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 4515 div_mode = rt2x00_get_field16(eeprom,
4516 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4517 ant = (div_mode == 3) ? 1 : 0;
4518
4519 /* check if this is a Bluetooth combo card */
4520 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4521 u32 reg;
4522
4523 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4524 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4525 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4526 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4527 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4528 if (ant == 0)
4529 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4530 else if (ant == 1)
4531 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4532 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4533 }
4534
4535 /* This chip has hardware antenna diversity*/
4536 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4537 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4538 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4539 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4540 }
4541
4542 rt2800_bbp_read(rt2x00dev, 152, &value);
4543 if (ant == 0)
4544 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4545 else
4546 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4547 rt2800_bbp_write(rt2x00dev, 152, value);
4548
4549 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 4550}
4551
a7bbbe5c
SG		 4552static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
4553{
4554 int ant, div_mode;
4555 u16 eeprom;
4556 u8 value;
4557
624708b8 4558 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 4559
a7bbbe5c
SG		 4560 rt2800_bbp_read(rt2x00dev, 105, &value);
4561 rt2x00_set_field8(&value, BBP105_MLD,
4562 rt2x00dev->default_ant.rx_chain_num == 2);
4563 rt2800_bbp_write(rt2x00dev, 105, value);
4564
4565 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4566
4567 rt2800_bbp_write(rt2x00dev, 20, 0x06);
4568 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4569 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
4570 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
4571 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
4572 rt2800_bbp_write(rt2x00dev, 70, 0x05);
4573 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4574 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
4575 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
4576 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4577 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4578 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
4579 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4580 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4581 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4582 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4583 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4584 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4585 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
4586 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4587 /* FIXME BBP105 owerwrite */
4588 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
4589 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4590 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4591 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
4592 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
4593 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
4594
4595 /* Initialize GLRT (Generalized Likehood Radio Test) */
4596 rt2800_init_bbp_5592_glrt(rt2x00dev);
4597
4598 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4599
3e38d3da 4600 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 4601 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
4602 ant = (div_mode == 3) ? 1 : 0;
4603 rt2800_bbp_read(rt2x00dev, 152, &value);
4604 if (ant == 0) {
4605 /* Main antenna */
4606 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4607 } else {
4608 /* Auxiliary antenna */
4609 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4610 }
4611 rt2800_bbp_write(rt2x00dev, 152, value);
4612
4613 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4614 rt2800_bbp_read(rt2x00dev, 254, &value);
4615 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4616 rt2800_bbp_write(rt2x00dev, 254, value);
4617 }
4618
c2675487
SG		 4619 rt2800_init_freq_calibration(rt2x00dev);
4620
a7bbbe5c 4621 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 4622 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4623 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 4624}
4625
a1ef5039 4626static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4627{
4628 unsigned int i;
4629 u16 eeprom;
4630 u8 reg_id;
4631 u8 value;
4632
dae62957
SG		 4633 if (rt2800_is_305x_soc(rt2x00dev))
4634 rt2800_init_bbp_305x_soc(rt2x00dev);
4635
39ab3e8b
SG		 4636 switch (rt2x00dev->chip.rt) {
4637 case RT2860:
4638 case RT2872:
4639 case RT2883:
4640 rt2800_init_bbp_28xx(rt2x00dev);
4641 break;
4642 case RT3070:
4643 case RT3071:
4644 case RT3090:
4645 rt2800_init_bbp_30xx(rt2x00dev);
4646 break;
4647 case RT3290:
4648 rt2800_init_bbp_3290(rt2x00dev);
4649 break;
4650 case RT3352:
4651 rt2800_init_bbp_3352(rt2x00dev);
4652 break;
4653 case RT3390:
4654 rt2800_init_bbp_3390(rt2x00dev);
4655 break;
4656 case RT3572:
4657 rt2800_init_bbp_3572(rt2x00dev);
4658 break;
4659 case RT5390:
4660 case RT5392:
4661 rt2800_init_bbp_53xx(rt2x00dev);
4662 break;
4663 case RT5592:
a7bbbe5c 4664 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 4665 return;
a7bbbe5c
SG		 4666 }
4667
fcf51541 4668 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 4669 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
4670 &eeprom);
fcf51541
BZ		 4671
4672 if (eeprom != 0xffff && eeprom != 0x0000) {
4673 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4674 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4675 rt2800_bbp_write(rt2x00dev, reg_id, value);
4676 }
4677 }
fcf51541 4678}
fcf51541 4679
d9517f2f
SG		 4680static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
4681{
4682 u32 reg;
4683
4684 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4685 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4686 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4687}
4688
c5b3c350
SG		 4689static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
4690 u8 filter_target)
fcf51541
BZ		 4691{
4692 unsigned int i;
4693 u8 bbp;
4694 u8 rfcsr;
4695 u8 passband;
4696 u8 stopband;
4697 u8 overtuned = 0;
c5b3c350 4698 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 4699
4700 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4701
4702 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4703 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4704 rt2800_bbp_write(rt2x00dev, 4, bbp);
4705
80d184e6
RJH		 4706 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4707 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4708 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4709
fcf51541
BZ		 4710 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4711 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4712 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4713
4714 /*
4715 * Set power & frequency of passband test tone
4716 */
4717 rt2800_bbp_write(rt2x00dev, 24, 0);
4718
4719 for (i = 0; i < 100; i++) {
4720 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4721 msleep(1);
4722
4723 rt2800_bbp_read(rt2x00dev, 55, &passband);
4724 if (passband)
4725 break;
4726 }
4727
4728 /*
4729 * Set power & frequency of stopband test tone
4730 */
4731 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4732
4733 for (i = 0; i < 100; i++) {
4734 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4735 msleep(1);
4736
4737 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4738
4739 if ((passband - stopband) <= filter_target) {
4740 rfcsr24++;
4741 overtuned += ((passband - stopband) == filter_target);
4742 } else
4743 break;
4744
4745 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4746 }
4747
4748 rfcsr24 -= !!overtuned;
4749
4750 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4751 return rfcsr24;
4752}
4753
ce94ede9
SG		 4754static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
4755 const unsigned int rf_reg)
4756{
4757 u8 rfcsr;
4758
4759 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
4760 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
4761 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4762 msleep(1);
4763 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
4764 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4765}
4766
c5b3c350
SG		 4767static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
4768{
4769 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4770 u8 filter_tgt_bw20;
4771 u8 filter_tgt_bw40;
4772 u8 rfcsr, bbp;
4773
4774 /*
4775 * TODO: sync filter_tgt values with vendor driver
4776 */
4777 if (rt2x00_rt(rt2x00dev, RT3070)) {
4778 filter_tgt_bw20 = 0x16;
4779 filter_tgt_bw40 = 0x19;
4780 } else {
4781 filter_tgt_bw20 = 0x13;
4782 filter_tgt_bw40 = 0x15;
4783 }
4784
4785 drv_data->calibration_bw20 =
4786 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
4787 drv_data->calibration_bw40 =
4788 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
4789
4790 /*
4791 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4792 */
4793 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4794 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4795
4796 /*
4797 * Set back to initial state
4798 */
4799 rt2800_bbp_write(rt2x00dev, 24, 0);
4800
4801 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4802 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4803 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4804
4805 /*
4806 * Set BBP back to BW20
4807 */
4808 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4809 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4810 rt2800_bbp_write(rt2x00dev, 4, bbp);
4811}
4812
da8064c2
SG		 4813static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
4814{
4815 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4816 u8 min_gain, rfcsr, bbp;
4817 u16 eeprom;
4818
4819 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4820
4821 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4822 if (rt2x00_rt(rt2x00dev, RT3070) ||
4823 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4824 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4825 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4826 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
4827 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4828 }
4829
4830 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
4831 if (drv_data->txmixer_gain_24g >= min_gain) {
4832 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4833 drv_data->txmixer_gain_24g);
4834 }
4835
4836 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4837
4838 if (rt2x00_rt(rt2x00dev, RT3090)) {
4839 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4840 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 4841 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 4842 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4843 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4844 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4845 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4846 rt2800_bbp_write(rt2x00dev, 138, bbp);
4847 }
4848
4849 if (rt2x00_rt(rt2x00dev, RT3070)) {
4850 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4851 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4852 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4853 else
4854 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4855 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4856 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4857 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4858 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4859 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4860 rt2x00_rt(rt2x00dev, RT3090) ||
4861 rt2x00_rt(rt2x00dev, RT3390)) {
4862 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4863 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4864 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4865 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4866 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4867 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4868 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4869
4870 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4871 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4872 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4873
4874 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4875 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4876 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4877
4878 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4879 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4880 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4881 }
4882}
4883
f7df8fe5
SG		 4884static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
4885{
4886 u8 reg;
4887 u16 eeprom;
4888
4889 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4890 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 4891 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 4892 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4893 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4894 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4895 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4896 rt2800_bbp_write(rt2x00dev, 138, reg);
4897
4898 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4899 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4900 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4901
4902 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4903 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4904 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4905
4906 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4907
4908 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4909 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4910 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4911}
4912
d5374ef1
SG		 4913static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4914{
ce94ede9
SG		 4915 rt2800_rf_init_calibration(rt2x00dev, 30);
4916
d5374ef1
SG		 4917 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4918 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4919 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4920 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4921 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4922 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4923 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4924 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4925 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4926 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4927 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4928 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4929 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4930 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4931 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4932 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4933 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4934 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4935 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4936 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4937 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4938 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4939 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4940 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4941 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4942 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4943 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4944 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4945 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4946 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4947 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4948 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4949}
4950
4951static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4952{
c9a221b2
SG		 4953 u8 rfcsr;
4954 u16 eeprom;
4955 u32 reg;
4956
ce94ede9
SG		 4957 /* XXX vendor driver do this only for 3070 */
4958 rt2800_rf_init_calibration(rt2x00dev, 30);
4959
d5374ef1
SG		 4960 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4961 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4962 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4963 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4964 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4965 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4966 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4967 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4968 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4969 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4970 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4971 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4972 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4973 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4974 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4975 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4976 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4977 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4978 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 4979
4980 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4981 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4982 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4983 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4984 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4985 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4986 rt2x00_rt(rt2x00dev, RT3090)) {
4987 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4988
4989 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4990 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4991 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4992
4993 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4994 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4995 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4996 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 4997 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4998 &eeprom);
c9a221b2
SG		 4999 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5000 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5001 else
5002 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5003 }
5004 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5005
5006 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5007 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5008 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
5009 }
c5b3c350
SG		 5010
5011 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 5012
5013 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5014 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5015 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
5016 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5017
5018 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5019 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5020}
5021
5022static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
5023{
f9cdcbb1
SG		 5024 u8 rfcsr;
5025
ce94ede9
SG		 5026 rt2800_rf_init_calibration(rt2x00dev, 2);
5027
d5374ef1
SG		 5028 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5029 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5030 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5031 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5032 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5033 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
5034 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5035 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5036 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5037 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5038 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5039 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
5040 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5041 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
5042 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5043 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5044 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5045 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5046 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5047 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5048 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5049 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
5050 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5051 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5052 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5053 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5054 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5055 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5056 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5057 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
5058 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5059 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5060 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5061 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5062 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5063 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
5064 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5065 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5066 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5067 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5068 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
5069 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5070 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5071 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
5072 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5073 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 5074
5075 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5076 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5077 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 5078
5079 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5080 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5081}
5082
5083static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
5084{
ce94ede9
SG		 5085 rt2800_rf_init_calibration(rt2x00dev, 30);
5086
d5374ef1
SG		 5087 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
5088 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
5089 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
5090 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
5091 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
5092 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
5093 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
5094 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5095 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
5096 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
5097 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
5098 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
5099 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
5100 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
5101 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
5102 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5103 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
5104 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
5105 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5106 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5107 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5108 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5109 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5110 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5111 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5112 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5113 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5114 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
5115 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
5116 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5117 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5118 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5119 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5120 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
5121 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
5122 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
5123 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
5124 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
5125 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
5126 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
5127 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
5128 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
5129 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
5130 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
5131 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
5132 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
5133 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
5134 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
5135 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
5136 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
5137 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
5138 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
5139 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
5140 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
5141 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
5142 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
5143 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
5144 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
5145 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
5146 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
5147 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
5148 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5149 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 5150
5151 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5152 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5153 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5154}
5155
5156static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
5157{
2971e66f
SG		 5158 u32 reg;
5159
ce94ede9
SG		 5160 rt2800_rf_init_calibration(rt2x00dev, 30);
5161
d5374ef1
SG		 5162 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
5163 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
5164 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5165 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
5166 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5167 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
5168 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
5169 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
5170 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
5171 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
5172 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
5173 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5174 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
5175 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
5176 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5177 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5178 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
5179 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
5180 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
5181 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
5182 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
5183 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
5184 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5185 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
5186 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5187 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
5188 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5189 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5190 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
5191 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
5192 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
5193 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 5194
5195 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
5196 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
5197 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 5198
5199 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 5200
5201 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
5202 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5203
5204 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5205 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5206}
5207
5208static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
5209{
87d91db9
SG		 5210 u8 rfcsr;
5211 u32 reg;
5212
ce94ede9
SG		 5213 rt2800_rf_init_calibration(rt2x00dev, 30);
5214
d5374ef1
SG		 5215 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
5216 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
5217 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
5218 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
5219 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
5220 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
5221 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
5222 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
5223 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
5224 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
5225 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
5226 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
5227 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
5228 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
5229 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
5230 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
5231 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
5232 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
5233 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
5234 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
5235 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
5236 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5237 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
5238 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5239 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
5240 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
5241 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
5242 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5243 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
5244 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
5245 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 5246
5247 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
5248 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
5249 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
5250
5251 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5252 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
5253 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5254 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
5255 msleep(1);
5256 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5257 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
5258 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
5259 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 5260
5261 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 5262 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 5263 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 5264}
5265
5266static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
5267{
ce94ede9
SG		 5268 rt2800_rf_init_calibration(rt2x00dev, 2);
5269
d5374ef1
SG		 5270 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
5271 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5272 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5273 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5274 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5275 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5276 else
5277 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
5278 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5279 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5280 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5281 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
5282 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5283 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5284 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5285 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5286 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5287 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
5288
5289 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5290 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
5291 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5292 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
5293 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
5294 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5295 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5296 else
5297 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
5298 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
5299 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5300 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5301 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5302
5303 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5304 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5305 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
5306 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
5307 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5308 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5309 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5310 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5311 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
5312 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5313
5314 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5315 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
5316 else
5317 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
5318 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5319 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
5320 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
5321 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5322 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5323 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5324 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5325 else
5326 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
5327 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
5328 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5329 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5330
5331 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
5332 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5333 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
5334 else
5335 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
5336 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5337 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
5338 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
5339 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5340 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5341 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
5342
5343 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5344 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5345 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
5346 else
5347 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
5348 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5349 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 5350
5351 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5352
5353 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5354}
5355
5356static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
5357{
ce94ede9
SG		 5358 rt2800_rf_init_calibration(rt2x00dev, 2);
5359
d5374ef1
SG		 5360 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
5361 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5362 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5363 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5364 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5365 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5366 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5367 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5368 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5369 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5370 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5371 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5372 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5373 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5374 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
5375 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5376 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
5377 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5378 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
5379 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
5380 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5381 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5382 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5383 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5384 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5385 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5386 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5387 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
5388 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5389 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5390 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5391 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5392 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5393 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
5394 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5395 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
5396 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5397 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5398 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
5399 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5400 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5401 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5402 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
5403 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5404 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5405 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
5406 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
5407 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
5408 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
5409 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
5410 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5411 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
5412 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
5413 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
5414 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
5415 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5416 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
5417 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
5418 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 5419
5420 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 5421
5422 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 5423}
5424
0c9e5fb9
SG		 5425static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
5426{
ce94ede9
SG		 5427 rt2800_rf_init_calibration(rt2x00dev, 30);
5428
0c9e5fb9
SG		 5429 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
5430 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5431 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5432 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5433 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
5434 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5435 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5436 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5437 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5438 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5439 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
5440 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
5441 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
5442 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5443 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5444 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5445 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5446 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5447 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5448 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
5449 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
5450 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5451
5452 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5453 msleep(1);
5454
5455 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 5456
c630ccf1
SG		 5457 /* Enable DC filter */
5458 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5459 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5460
f7df8fe5 5461 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 5462
5463 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
5464 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 5465
5466 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 5467}
5468
074f2529 5469static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 5470{
d5374ef1
SG		 5471 if (rt2800_is_305x_soc(rt2x00dev)) {
5472 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 5473 return;
d5374ef1
SG		 5474 }
5475
5476 switch (rt2x00dev->chip.rt) {
5477 case RT3070:
5478 case RT3071:
5479 case RT3090:
5480 rt2800_init_rfcsr_30xx(rt2x00dev);
5481 break;
5482 case RT3290:
5483 rt2800_init_rfcsr_3290(rt2x00dev);
5484 break;
5485 case RT3352:
5486 rt2800_init_rfcsr_3352(rt2x00dev);
5487 break;
5488 case RT3390:
5489 rt2800_init_rfcsr_3390(rt2x00dev);
5490 break;
5491 case RT3572:
5492 rt2800_init_rfcsr_3572(rt2x00dev);
5493 break;
5494 case RT5390:
5495 rt2800_init_rfcsr_5390(rt2x00dev);
5496 break;
5497 case RT5392:
5498 rt2800_init_rfcsr_5392(rt2x00dev);
5499 break;
0c9e5fb9
SG		 5500 case RT5592:
5501 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 5502 break;
8cdd15e0 5503 }
fcf51541 5504}
b9a07ae9
ID		 5505
5506int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5507{
5508 u32 reg;
5509 u16 word;
5510
5511 /*
5512 * Initialize all registers.
5513 */
5514 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 5515 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 5516 return -EIO;
5517
5518 /*
5519 * Send signal to firmware during boot time.
5520 */
c630ccf1
SG		 5521 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5522 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5523 if (rt2x00_is_usb(rt2x00dev)) {
5524 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5525 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5526 }
5527 msleep(1);
5528
a1ef5039
SG		 5529 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
5530 rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 5531 return -EIO;
b9a07ae9 5532
a1ef5039 5533 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 5534 rt2800_init_rfcsr(rt2x00dev);
5535
b9a07ae9
ID		 5536 if (rt2x00_is_usb(rt2x00dev) &&
5537 (rt2x00_rt(rt2x00dev, RT3070) ||
5538 rt2x00_rt(rt2x00dev, RT3071) ||
5539 rt2x00_rt(rt2x00dev, RT3572))) {
5540 udelay(200);
5541 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5542 udelay(10);
5543 }
5544
5545 /*
5546 * Enable RX.
5547 */
5548 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5549 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5550 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5551 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5552
5553 udelay(50);
5554
5555 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5556 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5560 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5561
5562 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5563 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5564 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5565 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5566
5567 /*
5568 * Initialize LED control
5569 */
3e38d3da 5570 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 5571 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 5572 word & 0xff, (word >> 8) & 0xff);
5573
3e38d3da 5574 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 5575 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 5576 word & 0xff, (word >> 8) & 0xff);
5577
3e38d3da 5578 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 5579 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 5580 word & 0xff, (word >> 8) & 0xff);
5581
5582 return 0;
5583}
5584EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5585
5586void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5587{
5588 u32 reg;
5589
f7b395e9 5590 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 5591
5592 /* Wait for DMA, ignore error */
5593 rt2800_wait_wpdma_ready(rt2x00dev);
5594
5595 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5596 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5597 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5598 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 5599}
5600EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 5601
30e84034
BZ		 5602int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5603{
5604 u32 reg;
a89534ed 5605 u16 efuse_ctrl_reg;
30e84034 5606
a89534ed
WH		 5607 if (rt2x00_rt(rt2x00dev, RT3290))
5608 efuse_ctrl_reg = EFUSE_CTRL_3290;
5609 else
5610 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 5611
a89534ed 5612 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5613 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5614}
5615EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5616
5617static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5618{
5619 u32 reg;
a89534ed
WH		 5620 u16 efuse_ctrl_reg;
5621 u16 efuse_data0_reg;
5622 u16 efuse_data1_reg;
5623 u16 efuse_data2_reg;
5624 u16 efuse_data3_reg;
5625
5626 if (rt2x00_rt(rt2x00dev, RT3290)) {
5627 efuse_ctrl_reg = EFUSE_CTRL_3290;
5628 efuse_data0_reg = EFUSE_DATA0_3290;
5629 efuse_data1_reg = EFUSE_DATA1_3290;
5630 efuse_data2_reg = EFUSE_DATA2_3290;
5631 efuse_data3_reg = EFUSE_DATA3_3290;
5632 } else {
5633 efuse_ctrl_reg = EFUSE_CTRL;
5634 efuse_data0_reg = EFUSE_DATA0;
5635 efuse_data1_reg = EFUSE_DATA1;
5636 efuse_data2_reg = EFUSE_DATA2;
5637 efuse_data3_reg = EFUSE_DATA3;
5638 }
31a4cf1f
GW		 5639 mutex_lock(&rt2x00dev->csr_mutex);
5640
a89534ed 5641 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 5642 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5643 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5644 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 5645 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 5646
5647 /* Wait until the EEPROM has been loaded */
a89534ed 5648 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 5649 /* Apparently the data is read from end to start */
a89534ed 5650 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 5651 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 5652 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 5653 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 5654 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 5655 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 5656 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 5657 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 5658 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 5659
5660 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 5661}
5662
a02308e9 5663int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 5664{
5665 unsigned int i;
5666
5667 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5668 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 5669
5670 return 0;
30e84034
BZ		 5671}
5672EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5673
ad417a53 5674static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5675{
77c06c2c 5676 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 5677 u16 word;
5678 u8 *mac;
5679 u8 default_lna_gain;
a02308e9 5680 int retval;
38bd7b8a 5681
ad417a53
GW		 5682 /*
5683 * Read the EEPROM.
5684 */
a02308e9
GJ		 5685 retval = rt2800_read_eeprom(rt2x00dev);
5686 if (retval)
5687 return retval;
ad417a53 5688
38bd7b8a
BZ		 5689 /*
5690 * Start validation of the data that has been read.
5691 */
3e38d3da 5692 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 5693 if (!is_valid_ether_addr(mac)) {
f4f7f414 5694 eth_random_addr(mac);
ec9c4989 5695 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 5696 }
5697
3e38d3da 5698 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 5699 if (word == 0xffff) {
38c8a566
RJH		 5700 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5701 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5702 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 5703 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 5704 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 5705 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 5706 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 5707 /*
5708 * There is a max of 2 RX streams for RT28x0 series
5709 */
38c8a566
RJH		 5710 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5711 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 5712 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 5713 }
5714
3e38d3da 5715 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 5716 if (word == 0xffff) {
38c8a566
RJH		 5717 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5718 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5719 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5720 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5721 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5722 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5723 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5724 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5725 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5726 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5727 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5730 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5731 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 5732 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 5733 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 5734 }
5735
3e38d3da 5736 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 5737 if ((word & 0x00ff) == 0x00ff) {
5738 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 5739 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 5740 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 5741 }
5742 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 5743 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5744 LED_MODE_TXRX_ACTIVITY);
5745 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 5746 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5747 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5748 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5749 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 5750 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 5751 }
5752
5753 /*
5754 * During the LNA validation we are going to use
5755 * lna0 as correct value. Note that EEPROM_LNA
5756 * is never validated.
5757 */
3e38d3da 5758 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 5759 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5760
3e38d3da 5761 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 5762 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5763 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5764 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5765 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 5766 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 5767
3e38d3da 5768 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
77c06c2c
GW		 5769 if ((word & 0x00ff) != 0x00ff) {
5770 drv_data->txmixer_gain_24g =
5771 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5772 } else {
5773 drv_data->txmixer_gain_24g = 0;
5774 }
5775
3e38d3da 5776 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 5777 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5778 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5779 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5780 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5781 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5782 default_lna_gain);
3e38d3da 5783 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 5784
3e38d3da 5785 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
77c06c2c
GW		 5786 if ((word & 0x00ff) != 0x00ff) {
5787 drv_data->txmixer_gain_5g =
5788 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5789 } else {
5790 drv_data->txmixer_gain_5g = 0;
5791 }
5792
3e38d3da 5793 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 5794 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5795 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5796 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5797 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 5798 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 5799
3e38d3da 5800 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 5801 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5802 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5803 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5804 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5805 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5806 default_lna_gain);
3e38d3da 5807 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a
BZ		 5808
5809 return 0;
5810}
38bd7b8a 5811
ad417a53 5812static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 5813{
38bd7b8a
BZ		 5814 u16 value;
5815 u16 eeprom;
86868b26 5816 u16 rf;
38bd7b8a 5817
86868b26
GJ		 5818 /*
5819 * Read EEPROM word for configuration.
5820 */
3e38d3da 5821 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 5822
5823 /*
5824 * Identify RF chipset by EEPROM value
5825 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5826 * RT53xx: defined in "EEPROM_CHIP_ID" field
5827 */
5828 if (rt2x00_rt(rt2x00dev, RT3290) ||
5829 rt2x00_rt(rt2x00dev, RT5390) ||
5830 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 5831 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 5832 else
5833 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5834
5835 switch (rf) {
d331eb51
LF		 5836 case RF2820:
5837 case RF2850:
5838 case RF2720:
5839 case RF2750:
5840 case RF3020:
5841 case RF2020:
5842 case RF3021:
5843 case RF3022:
5844 case RF3052:
a89534ed 5845 case RF3290:
d331eb51 5846 case RF3320:
03839951 5847 case RF3322:
ccf91bd6 5848 case RF5360:
d331eb51 5849 case RF5370:
2ed71884 5850 case RF5372:
d331eb51 5851 case RF5390:
cff3d1f0 5852 case RF5392:
b8863f8b 5853 case RF5592:
d331eb51
LF		 5854 break;
5855 default:
ec9c4989
JP		 5856 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
5857 rf);
38bd7b8a
BZ		 5858 return -ENODEV;
5859 }
5860
86868b26
GJ		 5861 rt2x00_set_rf(rt2x00dev, rf);
5862
38bd7b8a
BZ		 5863 /*
5864 * Identify default antenna configuration.
5865 */
d96aa640 5866 rt2x00dev->default_ant.tx_chain_num =
38c8a566 5867 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 5868 rt2x00dev->default_ant.rx_chain_num =
38c8a566 5869 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 5870
3e38d3da 5871 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 5872
5873 if (rt2x00_rt(rt2x00dev, RT3070) ||
5874 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 5875 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 5876 rt2x00_rt(rt2x00dev, RT3390)) {
5877 value = rt2x00_get_field16(eeprom,
5878 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5879 switch (value) {
5880 case 0:
5881 case 1:
5882 case 2:
5883 rt2x00dev->default_ant.tx = ANTENNA_A;
5884 rt2x00dev->default_ant.rx = ANTENNA_A;
5885 break;
5886 case 3:
5887 rt2x00dev->default_ant.tx = ANTENNA_A;
5888 rt2x00dev->default_ant.rx = ANTENNA_B;
5889 break;
5890 }
5891 } else {
5892 rt2x00dev->default_ant.tx = ANTENNA_A;
5893 rt2x00dev->default_ant.rx = ANTENNA_A;
5894 }
5895
0586a11b
AA		 5896 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5897 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5898 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5899 }
5900
38bd7b8a 5901 /*
9328fdac 5902 * Determine external LNA informations.
38bd7b8a 5903 */
38c8a566 5904 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 5905 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 5906 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 5907 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 5908
5909 /*
5910 * Detect if this device has an hardware controlled radio.
5911 */
38c8a566 5912 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 5913 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 5914
fdbc7b0a
GW		 5915 /*
5916 * Detect if this device has Bluetooth co-existence.
5917 */
5918 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5919 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5920
9328fdac
GW		 5921 /*
5922 * Read frequency offset and RF programming sequence.
5923 */
3e38d3da 5924 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 5925 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5926
38bd7b8a
BZ		 5927 /*
5928 * Store led settings, for correct led behaviour.
5929 */
5930#ifdef CONFIG_RT2X00_LIB_LEDS
5931 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5932 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5933 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5934
9328fdac 5935 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 5936#endif /* CONFIG_RT2X00_LIB_LEDS */
5937
e90c54b2
RJH		 5938 /*
5939 * Check if support EIRP tx power limit feature.
5940 */
3e38d3da 5941 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 5942
5943 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5944 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 5945 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 5946
38bd7b8a
BZ		 5947 return 0;
5948}
38bd7b8a 5949
4da2933f 5950/*
55f9321a 5951 * RF value list for rt28xx
4da2933f
BZ		 5952 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5953 */
5954static const struct rf_channel rf_vals[] = {
5955 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5956 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5957 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5958 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5959 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5960 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5961 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5962 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5963 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5964 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5965 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5966 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5967 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5968 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5969
5970 /* 802.11 UNI / HyperLan 2 */
5971 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5972 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5973 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5974 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5975 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5976 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5977 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5978 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5979 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5980 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5981 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5982 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5983
5984 /* 802.11 HyperLan 2 */
5985 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5986 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5987 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5988 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5989 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5990 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5991 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5992 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5993 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5994 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5995 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5996 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5997 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5998 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5999 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6000 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6001
6002 /* 802.11 UNII */
6003 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6004 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6005 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6006 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6007 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6008 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6009 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6010 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
6011 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
6012 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
6013 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
6014
6015 /* 802.11 Japan */
6016 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6017 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6018 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6019 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6020 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6021 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6022 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6023};
6024
6025/*
55f9321a
ID		 6026 * RF value list for rt3xxx
6027 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 6028 */
55f9321a 6029static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 6030 {1, 241, 2, 2 },
6031 {2, 241, 2, 7 },
6032 {3, 242, 2, 2 },
6033 {4, 242, 2, 7 },
6034 {5, 243, 2, 2 },
6035 {6, 243, 2, 7 },
6036 {7, 244, 2, 2 },
6037 {8, 244, 2, 7 },
6038 {9, 245, 2, 2 },
6039 {10, 245, 2, 7 },
6040 {11, 246, 2, 2 },
6041 {12, 246, 2, 7 },
6042 {13, 247, 2, 2 },
6043 {14, 248, 2, 4 },
55f9321a
ID		 6044
6045 /* 802.11 UNI / HyperLan 2 */
6046 {36, 0x56, 0, 4},
6047 {38, 0x56, 0, 6},
6048 {40, 0x56, 0, 8},
6049 {44, 0x57, 0, 0},
6050 {46, 0x57, 0, 2},
6051 {48, 0x57, 0, 4},
6052 {52, 0x57, 0, 8},
6053 {54, 0x57, 0, 10},
6054 {56, 0x58, 0, 0},
6055 {60, 0x58, 0, 4},
6056 {62, 0x58, 0, 6},
6057 {64, 0x58, 0, 8},
6058
6059 /* 802.11 HyperLan 2 */
6060 {100, 0x5b, 0, 8},
6061 {102, 0x5b, 0, 10},
6062 {104, 0x5c, 0, 0},
6063 {108, 0x5c, 0, 4},
6064 {110, 0x5c, 0, 6},
6065 {112, 0x5c, 0, 8},
6066 {116, 0x5d, 0, 0},
6067 {118, 0x5d, 0, 2},
6068 {120, 0x5d, 0, 4},
6069 {124, 0x5d, 0, 8},
6070 {126, 0x5d, 0, 10},
6071 {128, 0x5e, 0, 0},
6072 {132, 0x5e, 0, 4},
6073 {134, 0x5e, 0, 6},
6074 {136, 0x5e, 0, 8},
6075 {140, 0x5f, 0, 0},
6076
6077 /* 802.11 UNII */
6078 {149, 0x5f, 0, 9},
6079 {151, 0x5f, 0, 11},
6080 {153, 0x60, 0, 1},
6081 {157, 0x60, 0, 5},
6082 {159, 0x60, 0, 7},
6083 {161, 0x60, 0, 9},
6084 {165, 0x61, 0, 1},
6085 {167, 0x61, 0, 3},
6086 {169, 0x61, 0, 5},
6087 {171, 0x61, 0, 7},
6088 {173, 0x61, 0, 9},
4da2933f
BZ		 6089};
6090
7848b231
SG		 6091static const struct rf_channel rf_vals_5592_xtal20[] = {
6092 /* Channel, N, K, mod, R */
6093 {1, 482, 4, 10, 3},
6094 {2, 483, 4, 10, 3},
6095 {3, 484, 4, 10, 3},
6096 {4, 485, 4, 10, 3},
6097 {5, 486, 4, 10, 3},
6098 {6, 487, 4, 10, 3},
6099 {7, 488, 4, 10, 3},
6100 {8, 489, 4, 10, 3},
6101 {9, 490, 4, 10, 3},
6102 {10, 491, 4, 10, 3},
6103 {11, 492, 4, 10, 3},
6104 {12, 493, 4, 10, 3},
6105 {13, 494, 4, 10, 3},
6106 {14, 496, 8, 10, 3},
6107 {36, 172, 8, 12, 1},
6108 {38, 173, 0, 12, 1},
6109 {40, 173, 4, 12, 1},
6110 {42, 173, 8, 12, 1},
6111 {44, 174, 0, 12, 1},
6112 {46, 174, 4, 12, 1},
6113 {48, 174, 8, 12, 1},
6114 {50, 175, 0, 12, 1},
6115 {52, 175, 4, 12, 1},
6116 {54, 175, 8, 12, 1},
6117 {56, 176, 0, 12, 1},
6118 {58, 176, 4, 12, 1},
6119 {60, 176, 8, 12, 1},
6120 {62, 177, 0, 12, 1},
6121 {64, 177, 4, 12, 1},
6122 {100, 183, 4, 12, 1},
6123 {102, 183, 8, 12, 1},
6124 {104, 184, 0, 12, 1},
6125 {106, 184, 4, 12, 1},
6126 {108, 184, 8, 12, 1},
6127 {110, 185, 0, 12, 1},
6128 {112, 185, 4, 12, 1},
6129 {114, 185, 8, 12, 1},
6130 {116, 186, 0, 12, 1},
6131 {118, 186, 4, 12, 1},
6132 {120, 186, 8, 12, 1},
6133 {122, 187, 0, 12, 1},
6134 {124, 187, 4, 12, 1},
6135 {126, 187, 8, 12, 1},
6136 {128, 188, 0, 12, 1},
6137 {130, 188, 4, 12, 1},
6138 {132, 188, 8, 12, 1},
6139 {134, 189, 0, 12, 1},
6140 {136, 189, 4, 12, 1},
6141 {138, 189, 8, 12, 1},
6142 {140, 190, 0, 12, 1},
6143 {149, 191, 6, 12, 1},
6144 {151, 191, 10, 12, 1},
6145 {153, 192, 2, 12, 1},
6146 {155, 192, 6, 12, 1},
6147 {157, 192, 10, 12, 1},
6148 {159, 193, 2, 12, 1},
6149 {161, 193, 6, 12, 1},
6150 {165, 194, 2, 12, 1},
6151 {184, 164, 0, 12, 1},
6152 {188, 164, 4, 12, 1},
6153 {192, 165, 8, 12, 1},
6154 {196, 166, 0, 12, 1},
6155};
6156
6157static const struct rf_channel rf_vals_5592_xtal40[] = {
6158 /* Channel, N, K, mod, R */
6159 {1, 241, 2, 10, 3},
6160 {2, 241, 7, 10, 3},
6161 {3, 242, 2, 10, 3},
6162 {4, 242, 7, 10, 3},
6163 {5, 243, 2, 10, 3},
6164 {6, 243, 7, 10, 3},
6165 {7, 244, 2, 10, 3},
6166 {8, 244, 7, 10, 3},
6167 {9, 245, 2, 10, 3},
6168 {10, 245, 7, 10, 3},
6169 {11, 246, 2, 10, 3},
6170 {12, 246, 7, 10, 3},
6171 {13, 247, 2, 10, 3},
6172 {14, 248, 4, 10, 3},
6173 {36, 86, 4, 12, 1},
6174 {38, 86, 6, 12, 1},
6175 {40, 86, 8, 12, 1},
6176 {42, 86, 10, 12, 1},
6177 {44, 87, 0, 12, 1},
6178 {46, 87, 2, 12, 1},
6179 {48, 87, 4, 12, 1},
6180 {50, 87, 6, 12, 1},
6181 {52, 87, 8, 12, 1},
6182 {54, 87, 10, 12, 1},
6183 {56, 88, 0, 12, 1},
6184 {58, 88, 2, 12, 1},
6185 {60, 88, 4, 12, 1},
6186 {62, 88, 6, 12, 1},
6187 {64, 88, 8, 12, 1},
6188 {100, 91, 8, 12, 1},
6189 {102, 91, 10, 12, 1},
6190 {104, 92, 0, 12, 1},
6191 {106, 92, 2, 12, 1},
6192 {108, 92, 4, 12, 1},
6193 {110, 92, 6, 12, 1},
6194 {112, 92, 8, 12, 1},
6195 {114, 92, 10, 12, 1},
6196 {116, 93, 0, 12, 1},
6197 {118, 93, 2, 12, 1},
6198 {120, 93, 4, 12, 1},
6199 {122, 93, 6, 12, 1},
6200 {124, 93, 8, 12, 1},
6201 {126, 93, 10, 12, 1},
6202 {128, 94, 0, 12, 1},
6203 {130, 94, 2, 12, 1},
6204 {132, 94, 4, 12, 1},
6205 {134, 94, 6, 12, 1},
6206 {136, 94, 8, 12, 1},
6207 {138, 94, 10, 12, 1},
6208 {140, 95, 0, 12, 1},
6209 {149, 95, 9, 12, 1},
6210 {151, 95, 11, 12, 1},
6211 {153, 96, 1, 12, 1},
6212 {155, 96, 3, 12, 1},
6213 {157, 96, 5, 12, 1},
6214 {159, 96, 7, 12, 1},
6215 {161, 96, 9, 12, 1},
6216 {165, 97, 1, 12, 1},
6217 {184, 82, 0, 12, 1},
6218 {188, 82, 4, 12, 1},
6219 {192, 82, 8, 12, 1},
6220 {196, 83, 0, 12, 1},
6221};
6222
ad417a53 6223static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 6224{
4da2933f
BZ		 6225 struct hw_mode_spec *spec = &rt2x00dev->spec;
6226 struct channel_info *info;
8d1331b3
ID		 6227 char *default_power1;
6228 char *default_power2;
4da2933f
BZ		 6229 unsigned int i;
6230 u16 eeprom;
7848b231 6231 u32 reg;
4da2933f 6232
93b6bd26
GW		 6233 /*
6234 * Disable powersaving as default on PCI devices.
6235 */
cea90e55 6236 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 6237 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
6238
4da2933f
BZ		 6239 /*
6240 * Initialize all hw fields.
6241 */
6242 rt2x00dev->hw->flags =
4da2933f
BZ		 6243 IEEE80211_HW_SIGNAL_DBM |
6244 IEEE80211_HW_SUPPORTS_PS |
1df90809 6245 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 6246 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 6247 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 6248
5a5b6ed6
HS		 6249 /*
6250 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6251 * unless we are capable of sending the buffered frames out after the
6252 * DTIM transmission using rt2x00lib_beacondone. This will send out
6253 * multicast and broadcast traffic immediately instead of buffering it
6254 * infinitly and thus dropping it after some time.
6255 */
6256 if (!rt2x00_is_usb(rt2x00dev))
6257 rt2x00dev->hw->flags |=
6258 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 6259
4da2933f
BZ		 6260 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6261 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 6262 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 6263 EEPROM_MAC_ADDR_0));
6264
3f2bee24
HS		 6265 /*
6266 * As rt2800 has a global fallback table we cannot specify
6267 * more then one tx rate per frame but since the hw will
6268 * try several rates (based on the fallback table) we should
ba3b9e5e 6269 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 6270 * we are going to try. Otherwise mac80211 will truncate our
6271 * reported tx rates and the rc algortihm will end up with
6272 * incorrect data.
6273 */
ba3b9e5e
HS		 6274 rt2x00dev->hw->max_rates = 1;
6275 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 6276 rt2x00dev->hw->max_rate_tries = 1;
6277
3e38d3da 6278 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 6279
6280 /*
6281 * Initialize hw_mode information.
6282 */
6283 spec->supported_bands = SUPPORT_BAND_2GHZ;
6284 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6285
5122d898 6286 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 6287 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 6288 spec->num_channels = 14;
6289 spec->channels = rf_vals;
55f9321a
ID		 6290 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
6291 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 6292 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6293 spec->num_channels = ARRAY_SIZE(rf_vals);
6294 spec->channels = rf_vals;
5122d898
GW		 6295 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
6296 rt2x00_rf(rt2x00dev, RF2020) ||
6297 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 6298 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 6299 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 6300 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 6301 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 6302 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 6303 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 6304 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 6305 rt2x00_rf(rt2x00dev, RF5390) ||
6306 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 6307 spec->num_channels = 14;
6308 spec->channels = rf_vals_3x;
6309 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
6310 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6311 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
6312 spec->channels = rf_vals_3x;
7848b231
SG		 6313 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
6314 spec->supported_bands |= SUPPORT_BAND_5GHZ;
6315
6316 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
6317 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
6318 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
6319 spec->channels = rf_vals_5592_xtal40;
6320 } else {
6321 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
6322 spec->channels = rf_vals_5592_xtal20;
6323 }
4da2933f
BZ		 6324 }
6325
53216d6a
SG		 6326 if (WARN_ON_ONCE(!spec->channels))
6327 return -ENODEV;
6328
4da2933f
BZ		 6329 /*
6330 * Initialize HT information.
6331 */
5122d898 6332 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 6333 spec->ht.ht_supported = true;
6334 else
6335 spec->ht.ht_supported = false;
6336
4da2933f 6337 spec->ht.cap =
06443e46 6338 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 6339 IEEE80211_HT_CAP_GRN_FLD |
6340 IEEE80211_HT_CAP_SGI_20 |
aa674631 6341 IEEE80211_HT_CAP_SGI_40;
22cabaa6 6342
38c8a566 6343 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 6344 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
6345
aa674631 6346 spec->ht.cap |=
38c8a566 6347 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 6348 IEEE80211_HT_CAP_RX_STBC_SHIFT;
6349
4da2933f
BZ		 6350 spec->ht.ampdu_factor = 3;
6351 spec->ht.ampdu_density = 4;
6352 spec->ht.mcs.tx_params =
6353 IEEE80211_HT_MCS_TX_DEFINED |
6354 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 6355 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 6356 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
6357
38c8a566 6358 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 6359 case 3:
6360 spec->ht.mcs.rx_mask[2] = 0xff;
6361 case 2:
6362 spec->ht.mcs.rx_mask[1] = 0xff;
6363 case 1:
6364 spec->ht.mcs.rx_mask[0] = 0xff;
6365 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
6366 break;
6367 }
6368
6369 /*
6370 * Create channel information array
6371 */
baeb2ffa 6372 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 6373 if (!info)
6374 return -ENOMEM;
6375
6376 spec->channels_info = info;
6377
3e38d3da
GJ		 6378 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6379 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 6380
6381 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 6382 info[i].default_power1 = default_power1[i];
6383 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 6384 }
6385
6386 if (spec->num_channels > 14) {
3e38d3da
GJ		 6387 default_power1 = rt2800_eeprom_addr(rt2x00dev,
6388 EEPROM_TXPOWER_A1);
6389 default_power2 = rt2800_eeprom_addr(rt2x00dev,
6390 EEPROM_TXPOWER_A2);
4da2933f
BZ		 6391
6392 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 6393 info[i].default_power1 = default_power1[i - 14];
6394 info[i].default_power2 = default_power2[i - 14];
4da2933f
BZ		 6395 }
6396 }
6397
2e9c43dd
JL		 6398 switch (rt2x00dev->chip.rf) {
6399 case RF2020:
6400 case RF3020:
6401 case RF3021:
6402 case RF3022:
6403 case RF3320:
6404 case RF3052:
a89534ed 6405 case RF3290:
ccf91bd6 6406 case RF5360:
2e9c43dd
JL		 6407 case RF5370:
6408 case RF5372:
6409 case RF5390:
cff3d1f0 6410 case RF5392:
2e9c43dd
JL		 6411 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6412 break;
6413 }
6414
4da2933f
BZ		 6415 return 0;
6416}
ad417a53 6417
cbafb601
GJ		 6418static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
6419{
6420 u32 reg;
6421 u32 rt;
6422 u32 rev;
6423
6424 if (rt2x00_rt(rt2x00dev, RT3290))
6425 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
6426 else
6427 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
6428
6429 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
6430 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
6431
6432 switch (rt) {
6433 case RT2860:
6434 case RT2872:
6435 case RT2883:
6436 case RT3070:
6437 case RT3071:
6438 case RT3090:
6439 case RT3290:
6440 case RT3352:
6441 case RT3390:
6442 case RT3572:
6443 case RT5390:
6444 case RT5392:
6445 case RT5592:
6446 break;
6447 default:
ec9c4989
JP		 6448 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6449 rt, rev);
cbafb601
GJ		 6450 return -ENODEV;
6451 }
6452
6453 rt2x00_set_rt(rt2x00dev, rt, rev);
6454
6455 return 0;
6456}
6457
ad417a53
GW		 6458int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6459{
6460 int retval;
6461 u32 reg;
6462
cbafb601
GJ		 6463 retval = rt2800_probe_rt(rt2x00dev);
6464 if (retval)
6465 return retval;
6466
ad417a53
GW		 6467 /*
6468 * Allocate eeprom data.
6469 */
6470 retval = rt2800_validate_eeprom(rt2x00dev);
6471 if (retval)
6472 return retval;
6473
6474 retval = rt2800_init_eeprom(rt2x00dev);
6475 if (retval)
6476 return retval;
6477
6478 /*
6479 * Enable rfkill polling by setting GPIO direction of the
6480 * rfkill switch GPIO pin correctly.
6481 */
6482 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6483 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6484 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6485
6486 /*
6487 * Initialize hw specifications.
6488 */
6489 retval = rt2800_probe_hw_mode(rt2x00dev);
6490 if (retval)
6491 return retval;
6492
6493 /*
6494 * Set device capabilities.
6495 */
6496 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6497 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6498 if (!rt2x00_is_usb(rt2x00dev))
6499 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6500
6501 /*
6502 * Set device requirements.
6503 */
6504 if (!rt2x00_is_soc(rt2x00dev))
6505 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6506 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6507 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6508 if (!rt2800_hwcrypt_disabled(rt2x00dev))
6509 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6510 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6511 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6512 if (rt2x00_is_usb(rt2x00dev))
6513 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6514 else {
6515 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6516 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6517 }
6518
6519 /*
6520 * Set the rssi offset.
6521 */
6522 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6523
6524 return 0;
6525}
6526EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 6527
2ce33995
BZ		 6528/*
6529 * IEEE80211 stack callback functions.
6530 */
e783619e
HS		 6531void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6532 u16 *iv16)
2ce33995
BZ		 6533{
6534 struct rt2x00_dev *rt2x00dev = hw->priv;
6535 struct mac_iveiv_entry iveiv_entry;
6536 u32 offset;
6537
6538 offset = MAC_IVEIV_ENTRY(hw_key_idx);
6539 rt2800_register_multiread(rt2x00dev, offset,
6540 &iveiv_entry, sizeof(iveiv_entry));
6541
855da5e0
JL		 6542 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6543 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 6544}
e783619e 6545EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 6546
e783619e 6547int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 6548{
6549 struct rt2x00_dev *rt2x00dev = hw->priv;
6550 u32 reg;
6551 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6552
6553 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6554 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6555 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6556
6557 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6558 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6559 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6560
6561 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6562 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6563 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6564
6565 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6566 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6567 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6568
6569 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6570 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6571 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6572
6573 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6574 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6575 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6576
6577 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6578 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6579 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6580
6581 return 0;
6582}
e783619e 6583EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 6584
8a3a3c85
EP		 6585int rt2800_conf_tx(struct ieee80211_hw *hw,
6586 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 6587 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 6588{
6589 struct rt2x00_dev *rt2x00dev = hw->priv;
6590 struct data_queue *queue;
6591 struct rt2x00_field32 field;
6592 int retval;
6593 u32 reg;
6594 u32 offset;
6595
6596 /*
6597 * First pass the configuration through rt2x00lib, that will
6598 * update the queue settings and validate the input. After that
6599 * we are free to update the registers based on the value
6600 * in the queue parameter.
6601 */
8a3a3c85 6602 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 6603 if (retval)
6604 return retval;
6605
6606 /*
6607 * We only need to perform additional register initialization
6608 * for WMM queues/
6609 */
6610 if (queue_idx >= 4)
6611 return 0;
6612
11f818e0 6613 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 6614
6615 /* Update WMM TXOP register */
6616 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6617 field.bit_offset = (queue_idx & 1) * 16;
6618 field.bit_mask = 0xffff << field.bit_offset;
6619
6620 rt2800_register_read(rt2x00dev, offset, &reg);
6621 rt2x00_set_field32(&reg, field, queue->txop);
6622 rt2800_register_write(rt2x00dev, offset, reg);
6623
6624 /* Update WMM registers */
6625 field.bit_offset = queue_idx * 4;
6626 field.bit_mask = 0xf << field.bit_offset;
6627
6628 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6629 rt2x00_set_field32(&reg, field, queue->aifs);
6630 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6631
6632 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6633 rt2x00_set_field32(&reg, field, queue->cw_min);
6634 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6635
6636 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6637 rt2x00_set_field32(&reg, field, queue->cw_max);
6638 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6639
6640 /* Update EDCA registers */
6641 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6642
6643 rt2800_register_read(rt2x00dev, offset, &reg);
6644 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6645 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6646 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6647 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6648 rt2800_register_write(rt2x00dev, offset, reg);
6649
6650 return 0;
6651}
e783619e 6652EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 6653
37a41b4a 6654u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 6655{
6656 struct rt2x00_dev *rt2x00dev = hw->priv;
6657 u64 tsf;
6658 u32 reg;
6659
6660 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6661 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6662 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6663 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6664
6665 return tsf;
6666}
e783619e 6667EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 6668
e783619e
HS		 6669int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6670 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 6671 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6672 u8 buf_size)
1df90809 6673{
af35323d 6674 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 6675 int ret = 0;
6676
af35323d
HS		 6677 /*
6678 * Don't allow aggregation for stations the hardware isn't aware
6679 * of because tx status reports for frames to an unknown station
6680 * always contain wcid=255 and thus we can't distinguish between
6681 * multiple stations which leads to unwanted situations when the
6682 * hw reorders frames due to aggregation.
6683 */
6684 if (sta_priv->wcid < 0)
6685 return 1;
6686
1df90809
HS		 6687 switch (action) {
6688 case IEEE80211_AMPDU_RX_START:
6689 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 6690 /*
6691 * The hw itself takes care of setting up BlockAck mechanisms.
6692 * So, we only have to allow mac80211 to nagotiate a BlockAck
6693 * agreement. Once that is done, the hw will BlockAck incoming
6694 * AMPDUs without further setup.
6695 */
1df90809
HS		 6696 break;
6697 case IEEE80211_AMPDU_TX_START:
6698 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6699 break;
18b559d5
JB		 6700 case IEEE80211_AMPDU_TX_STOP_CONT:
6701 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6702 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 6703 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6704 break;
6705 case IEEE80211_AMPDU_TX_OPERATIONAL:
6706 break;
6707 default:
ec9c4989
JP		 6708 rt2x00_warn((struct rt2x00_dev *)hw->priv,
6709 "Unknown AMPDU action\n");
1df90809
HS		 6710 }
6711
6712 return ret;
6713}
e783619e 6714EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 6715
977206d7
HS		 6716int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6717 struct survey_info *survey)
6718{
6719 struct rt2x00_dev *rt2x00dev = hw->priv;
6720 struct ieee80211_conf *conf = &hw->conf;
6721 u32 idle, busy, busy_ext;
6722
6723 if (idx != 0)
6724 return -ENOENT;
6725
675a0b04 6726 survey->channel = conf->chandef.chan;
977206d7
HS		 6727
6728 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6729 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6730 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6731
6732 if (idle || busy) {
6733 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6734 SURVEY_INFO_CHANNEL_TIME_BUSY |
6735 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6736
6737 survey->channel_time = (idle + busy) / 1000;
6738 survey->channel_time_busy = busy / 1000;
6739 survey->channel_time_ext_busy = busy_ext / 1000;
6740 }
6741
9931df26
HS		 6742 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6743 survey->filled |= SURVEY_INFO_IN_USE;
6744
977206d7
HS		 6745 return 0;
6746
6747}
6748EXPORT_SYMBOL_GPL(rt2800_get_survey);
6749
a5ea2f02
ID		 6750MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6751MODULE_VERSION(DRV_VERSION);
6752MODULE_DESCRIPTION("Ralink RT2800 library");
6753MODULE_LICENSE("GPL");
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