]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/wireless/rt2x00/rt2800lib.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2800: do not crash if spec->channels is NULL
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
92941382 83 WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425 223
16ebd608
WH		 224static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225{
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283}
284
89297425
BZ		 285void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288{
289 u32 reg;
290
ee303e54 291 /*
cea90e55 292 * SOC devices don't support MCU requests.
ee303e54 293 */
cea90e55 294 if (rt2x00_is_soc(rt2x00dev))
ee303e54 295 return;
89297425
BZ		 296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316}
317EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 318
5ffddc49
ID		 319int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320{
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333}
334EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
67a4c1e2
GW		 336int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337{
338 unsigned int i;
339 u32 reg;
340
08e53100
HS		 341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
67a4c1e2
GW		 345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
08e53100 351 msleep(10);
67a4c1e2
GW		 352 }
353
52b8243b 354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
67a4c1e2
GW		 355 return -EACCES;
356}
357EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
f7b395e9
JK		 359void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360{
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370}
371EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
f31c9a8c
ID		 373static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374{
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403}
404
405int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407{
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
f31c9a8c 420 */
a89534ed 421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 422 fw_len = 4096;
a89534ed 423 else
f31c9a8c 424 fw_len = 8192;
f31c9a8c 425
a89534ed 426 multiple = true;
f31c9a8c
ID		 427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456}
457EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461{
462 unsigned int i;
463 u32 reg;
16ebd608
WH		 464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
f31c9a8c
ID		 471
472 /*
b9eca242
ID		 473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 475 */
b9eca242 476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 477
f31c9a8c
ID		 478 /*
479 * Wait for stable hardware.
480 */
5ffddc49 481 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 482 return -EBUSY;
f31c9a8c 483
adde5882 484 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
f31c9a8c 494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 495 }
f31c9a8c 496
b7e1d225
JK		 497 rt2800_disable_wpdma(rt2x00dev);
498
f31c9a8c
ID		 499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
4ed1dd2a
SG		 519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
f7b395e9 523 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 524
f31c9a8c
ID		 525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 530 if (rt2x00_is_usb(rt2x00dev))
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 532 msleep(1);
533
534 return 0;
535}
536EXPORT_SYMBOL_GPL(rt2800_load_firmware);
537
0c5879bc
ID		 538void rt2800_write_tx_data(struct queue_entry *entry,
539 struct txentry_desc *txdesc)
59679b91 540{
0c5879bc 541 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 542 u32 word;
543
544 /*
545 * Initialize TX Info descriptor
546 */
547 rt2x00_desc_read(txwi, 0, &word);
548 rt2x00_set_field32(&word, TXWI_W0_FRAG,
549 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 550 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
551 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 552 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
553 rt2x00_set_field32(&word, TXWI_W0_TS,
554 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
555 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
556 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 557 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
558 txdesc->u.ht.mpdu_density);
559 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
560 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 561 rt2x00_set_field32(&word, TXWI_W0_BW,
562 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
563 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
564 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 565 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 566 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
567 rt2x00_desc_write(txwi, 0, word);
568
569 rt2x00_desc_read(txwi, 1, &word);
570 rt2x00_set_field32(&word, TXWI_W1_ACK,
571 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
572 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
573 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 574 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 575 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
576 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 577 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 578 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
579 txdesc->length);
2b23cdaa 580 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 581 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 582 rt2x00_desc_write(txwi, 1, word);
583
584 /*
585 * Always write 0 to IV/EIV fields, hardware will insert the IV
586 * from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame.
590 */
591 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
592 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
593}
0c5879bc 594EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 595
ff6133be 596static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 597{
7fc41755
LT		 598 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
599 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
600 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 601 u16 eeprom;
602 u8 offset0;
603 u8 offset1;
604 u8 offset2;
605
e5ef5bad 606 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 607 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
608 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
609 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
610 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
611 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
612 } else {
613 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
614 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
615 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
616 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
617 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
618 }
619
620 /*
621 * Convert the value from the descriptor into the RSSI value
622 * If the value in the descriptor is 0, it is considered invalid
623 * and the default (extremely low) rssi value is assumed
624 */
625 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
626 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
627 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
628
629 /*
630 * mac80211 only accepts a single RSSI value. Calculating the
631 * average doesn't deliver a fair answer either since -60:-60 would
632 * be considered equally good as -50:-70 while the second is the one
633 * which gives less energy...
634 */
635 rssi0 = max(rssi0, rssi1);
7fc41755 636 return (int)max(rssi0, rssi2);
74861922
ID		 637}
638
639void rt2800_process_rxwi(struct queue_entry *entry,
640 struct rxdone_entry_desc *rxdesc)
641{
642 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 643 u32 word;
644
645 rt2x00_desc_read(rxwi, 0, &word);
646
647 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
648 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
649
650 rt2x00_desc_read(rxwi, 1, &word);
651
652 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
653 rxdesc->flags |= RX_FLAG_SHORT_GI;
654
655 if (rt2x00_get_field32(word, RXWI_W1_BW))
656 rxdesc->flags |= RX_FLAG_40MHZ;
657
658 /*
659 * Detect RX rate, always use MCS as signal type.
660 */
661 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
662 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
663 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
664
665 /*
666 * Mask of 0x8 bit to remove the short preamble flag.
667 */
668 if (rxdesc->rate_mode == RATE_MODE_CCK)
669 rxdesc->signal &= ~0x8;
670
671 rt2x00_desc_read(rxwi, 2, &word);
672
74861922
ID		 673 /*
674 * Convert descriptor AGC value to RSSI value.
675 */
676 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 677
678 /*
679 * Remove RXWI descriptor from start of buffer.
680 */
74861922 681 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 682}
683EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
684
31937c42 685void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 686{
687 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 688 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 689 struct txdone_entry_desc txdesc;
690 u32 word;
691 u16 mcs, real_mcs;
b34793ee 692 int aggr, ampdu;
14433331
HS		 693
694 /*
695 * Obtain the status about this packet.
696 */
697 txdesc.flags = 0;
14433331 698 rt2x00_desc_read(txwi, 0, &word);
b34793ee 699
14433331 700 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 701 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
702
14433331 703 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 704 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
705
706 /*
707 * If a frame was meant to be sent as a single non-aggregated MPDU
708 * but ended up in an aggregate the used tx rate doesn't correlate
709 * with the one specified in the TXWI as the whole aggregate is sent
710 * with the same rate.
711 *
712 * For example: two frames are sent to rt2x00, the first one sets
713 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
714 * and requests MCS15. If the hw aggregates both frames into one
715 * AMDPU the tx status for both frames will contain MCS7 although
716 * the frame was sent successfully.
717 *
718 * Hence, replace the requested rate with the real tx rate to not
719 * confuse the rate control algortihm by providing clearly wrong
720 * data.
721 */
5356d963 722 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 723 skbdesc->tx_rate_idx = real_mcs;
724 mcs = real_mcs;
725 }
14433331 726
f16d2db7
HS		 727 if (aggr == 1 || ampdu == 1)
728 __set_bit(TXDONE_AMPDU, &txdesc.flags);
729
14433331
HS		 730 /*
731 * Ralink has a retry mechanism using a global fallback
732 * table. We setup this fallback table to try the immediate
733 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
734 * always contains the MCS used for the last transmission, be
735 * it successful or not.
736 */
737 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
738 /*
739 * Transmission succeeded. The number of retries is
740 * mcs - real_mcs
741 */
742 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
743 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
744 } else {
745 /*
746 * Transmission failed. The number of retries is
747 * always 7 in this case (for a total number of 8
748 * frames sent).
749 */
750 __set_bit(TXDONE_FAILURE, &txdesc.flags);
751 txdesc.retry = rt2x00dev->long_retry;
752 }
753
754 /*
755 * the frame was retried at least once
756 * -> hw used fallback rates
757 */
758 if (txdesc.retry)
759 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
760
761 rt2x00lib_txdone(entry, &txdesc);
762}
763EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
764
f0194b2d
GW		 765void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
766{
767 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
769 unsigned int beacon_base;
739fd940 770 unsigned int padding_len;
d76dfc61 771 u32 orig_reg, reg;
f0194b2d
GW		 772
773 /*
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
776 */
777 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 778 orig_reg = reg;
f0194b2d
GW		 779 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
780 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
781
782 /*
783 * Add space for the TXWI in front of the skb.
784 */
b52398b6 785 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 786
787 /*
788 * Register descriptor details in skb frame descriptor.
789 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE;
793
794 /*
795 * Add the TXWI for the beacon to the skb.
796 */
0c5879bc 797 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 798
799 /*
800 * Dump beacon to userspace through debugfs.
801 */
802 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
803
804 /*
739fd940 805 * Write entire beacon with TXWI and padding to register.
f0194b2d 806 */
739fd940 807 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 808 if (padding_len && skb_pad(entry->skb, padding_len)) {
809 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */
811 entry->skb = NULL;
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
813 return;
814 }
815
f0194b2d 816 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 817 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
818 entry->skb->len + padding_len);
f0194b2d
GW		 819
820 /*
821 * Enable beaconing again.
822 */
f0194b2d
GW		 823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
826 /*
827 * Clean up beacon skb.
828 */
829 dev_kfree_skb_any(entry->skb);
830 entry->skb = NULL;
831}
50e888ea 832EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 833
69cf36a4
HS		 834static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base)
fdb87251
HS		 836{
837 int i;
838
839 /*
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon.
843 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846}
847
69cf36a4
HS		 848void rt2800_clear_beacon(struct queue_entry *entry)
849{
850 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
851 u32 reg;
852
853 /*
854 * Disable beaconing while we are reloading the beacon data,
855 * otherwise we might be sending out invalid data.
856 */
857 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
858 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
859 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
860
861 /*
862 * Clear beacon.
863 */
864 rt2800_clear_beacon_register(rt2x00dev,
865 HW_BEACON_OFFSET(entry->entry_idx));
866
867 /*
868 * Enabled beaconing again.
869 */
870 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
871 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
872}
873EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
874
f4450616
BZ		 875#ifdef CONFIG_RT2X00_LIB_DEBUGFS
876const struct rt2x00debug rt2800_rt2x00debug = {
877 .owner = THIS_MODULE,
878 .csr = {
879 .read = rt2800_register_read,
880 .write = rt2800_register_write,
881 .flags = RT2X00DEBUGFS_OFFSET,
882 .word_base = CSR_REG_BASE,
883 .word_size = sizeof(u32),
884 .word_count = CSR_REG_SIZE / sizeof(u32),
885 },
886 .eeprom = {
887 .read = rt2x00_eeprom_read,
888 .write = rt2x00_eeprom_write,
889 .word_base = EEPROM_BASE,
890 .word_size = sizeof(u16),
891 .word_count = EEPROM_SIZE / sizeof(u16),
892 },
893 .bbp = {
894 .read = rt2800_bbp_read,
895 .write = rt2800_bbp_write,
896 .word_base = BBP_BASE,
897 .word_size = sizeof(u8),
898 .word_count = BBP_SIZE / sizeof(u8),
899 },
900 .rf = {
901 .read = rt2x00_rf_read,
902 .write = rt2800_rf_write,
903 .word_base = RF_BASE,
904 .word_size = sizeof(u32),
905 .word_count = RF_SIZE / sizeof(u32),
906 },
f2bd7f16
AA		 907 .rfcsr = {
908 .read = rt2800_rfcsr_read,
909 .write = rt2800_rfcsr_write,
910 .word_base = RFCSR_BASE,
911 .word_size = sizeof(u8),
912 .word_count = RFCSR_SIZE / sizeof(u8),
913 },
f4450616
BZ		 914};
915EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
916#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
917
918int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
919{
920 u32 reg;
921
a89534ed
WH		 922 if (rt2x00_rt(rt2x00dev, RT3290)) {
923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
925 } else {
99bdf51a
GW		 926 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
927 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 928 }
f4450616
BZ		 929}
930EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
931
932#ifdef CONFIG_RT2X00_LIB_LEDS
933static void rt2800_brightness_set(struct led_classdev *led_cdev,
934 enum led_brightness brightness)
935{
936 struct rt2x00_led *led =
937 container_of(led_cdev, struct rt2x00_led, led_dev);
938 unsigned int enabled = brightness != LED_OFF;
939 unsigned int bg_mode =
940 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
941 unsigned int polarity =
942 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
943 EEPROM_FREQ_LED_POLARITY);
944 unsigned int ledmode =
945 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
946 EEPROM_FREQ_LED_MODE);
44704e5d 947 u32 reg;
f4450616 948
44704e5d
LE		 949 /* Check for SoC (SOC devices don't support MCU requests) */
950 if (rt2x00_is_soc(led->rt2x00dev)) {
951 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
952
953 /* Set LED Polarity */
954 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
955
956 /* Set LED Mode */
957 if (led->type == LED_TYPE_RADIO) {
958 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
959 enabled ? 3 : 0);
960 } else if (led->type == LED_TYPE_ASSOC) {
961 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
962 enabled ? 3 : 0);
963 } else if (led->type == LED_TYPE_QUALITY) {
964 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
965 enabled ? 3 : 0);
966 }
967
968 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
969
970 } else {
971 if (led->type == LED_TYPE_RADIO) {
972 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
973 enabled ? 0x20 : 0);
974 } else if (led->type == LED_TYPE_ASSOC) {
975 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
976 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
977 } else if (led->type == LED_TYPE_QUALITY) {
978 /*
979 * The brightness is divided into 6 levels (0 - 5),
980 * The specs tell us the following levels:
981 * 0, 1 ,3, 7, 15, 31
982 * to determine the level in a simple way we can simply
983 * work with bitshifting:
984 * (1 << level) - 1
985 */
986 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
987 (1 << brightness / (LED_FULL / 6)) - 1,
988 polarity);
989 }
f4450616
BZ		 990 }
991}
992
b3579d6a 993static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 994 struct rt2x00_led *led, enum led_type type)
995{
996 led->rt2x00dev = rt2x00dev;
997 led->type = type;
998 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 999 led->flags = LED_INITIALIZED;
1000}
f4450616
BZ		 1001#endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003/*
1004 * Configuration handlers.
1005 */
a2b1328a
HS		 1006static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007 const u8 *address,
1008 int wcid)
f4450616
BZ		 1009{
1010 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1011 u32 offset;
1012
1013 offset = MAC_WCID_ENTRY(wcid);
1014
1015 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016 if (address)
1017 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019 rt2800_register_multiwrite(rt2x00dev, offset,
1020 &wcid_entry, sizeof(wcid_entry));
1021}
1022
1023static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024{
1025 u32 offset;
1026 offset = MAC_WCID_ATTR_ENTRY(wcid);
1027 rt2800_register_write(rt2x00dev, offset, 0);
1028}
1029
1030static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031 int wcid, u32 bssidx)
1032{
1033 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034 u32 reg;
1035
1036 /*
1037 * The BSS Idx numbers is split in a main value of 3 bits,
1038 * and a extended field for adding one additional bit to the value.
1039 */
1040 rt2800_register_read(rt2x00dev, offset, &reg);
1041 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043 (bssidx & 0x8) >> 3);
1044 rt2800_register_write(rt2x00dev, offset, reg);
1045}
1046
1047static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048 struct rt2x00lib_crypto *crypto,
1049 struct ieee80211_key_conf *key)
1050{
f4450616
BZ		 1051 struct mac_iveiv_entry iveiv_entry;
1052 u32 offset;
1053 u32 reg;
1054
1055 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
e4a0ab34
ID		 1057 if (crypto->cmd == SET_KEY) {
1058 rt2800_register_read(rt2x00dev, offset, &reg);
1059 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061 /*
1062 * Both the cipher as the BSS Idx numbers are split in a main
1063 * value of 3 bits, and a extended field for adding one additional
1064 * bit to the value.
1065 */
1066 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067 (crypto->cipher & 0x7));
1068 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1070 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071 rt2800_register_write(rt2x00dev, offset, reg);
1072 } else {
a2b1328a
HS		 1073 /* Delete the cipher without touching the bssidx */
1074 rt2800_register_read(rt2x00dev, offset, &reg);
1075 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1080 }
f4450616
BZ		 1081
1082 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085 if ((crypto->cipher == CIPHER_TKIP) ||
1086 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087 (crypto->cipher == CIPHER_AES))
1088 iveiv_entry.iv[3] |= 0x20;
1089 iveiv_entry.iv[3] |= key->keyidx << 6;
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1092}
1093
1094int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095 struct rt2x00lib_crypto *crypto,
1096 struct ieee80211_key_conf *key)
1097{
1098 struct hw_key_entry key_entry;
1099 struct rt2x00_field32 field;
1100 u32 offset;
1101 u32 reg;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106 memcpy(key_entry.key, crypto->key,
1107 sizeof(key_entry.key));
1108 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109 sizeof(key_entry.tx_mic));
1110 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111 sizeof(key_entry.rx_mic));
1112
1113 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114 rt2800_register_multiwrite(rt2x00dev, offset,
1115 &key_entry, sizeof(key_entry));
1116 }
1117
1118 /*
1119 * The cipher types are stored over multiple registers
1120 * starting with SHARED_KEY_MODE_BASE each word will have
1121 * 32 bits and contains the cipher types for 2 bssidx each.
1122 * Using the correct defines correctly will cause overhead,
1123 * so just calculate the correct offset.
1124 */
1125 field.bit_offset = 4 * (key->hw_key_idx % 8);
1126 field.bit_mask = 0x7 << field.bit_offset;
1127
1128 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130 rt2800_register_read(rt2x00dev, offset, &reg);
1131 rt2x00_set_field32(&reg, field,
1132 (crypto->cmd == SET_KEY) * crypto->cipher);
1133 rt2800_register_write(rt2x00dev, offset, reg);
1134
1135 /*
1136 * Update WCID information
1137 */
a2b1328a
HS		 1138 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140 crypto->bssidx);
1141 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1142
1143 return 0;
1144}
1145EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
a2b1328a 1147static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1148{
a2b1328a 1149 struct mac_wcid_entry wcid_entry;
1ed3811c 1150 int idx;
a2b1328a 1151 u32 offset;
1ed3811c
HS		 1152
1153 /*
a2b1328a
HS		 1154 * Search for the first free WCID entry and return the corresponding
1155 * index.
1ed3811c
HS		 1156 *
1157 * Make sure the WCID starts _after_ the last possible shared key
1158 * entry (>32).
1159 *
1160 * Since parts of the pairwise key table might be shared with
1161 * the beacon frame buffers 6 & 7 we should only write into the
1162 * first 222 entries.
1163 */
1164 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1165 offset = MAC_WCID_ENTRY(idx);
1166 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167 sizeof(wcid_entry));
1168 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1169 return idx;
1170 }
a2b1328a
HS		 1171
1172 /*
1173 * Use -1 to indicate that we don't have any more space in the WCID
1174 * table.
1175 */
1ed3811c
HS		 1176 return -1;
1177}
1178
f4450616
BZ		 1179int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180 struct rt2x00lib_crypto *crypto,
1181 struct ieee80211_key_conf *key)
1182{
1183 struct hw_key_entry key_entry;
1184 u32 offset;
1185
1186 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1187 /*
1188 * Allow key configuration only for STAs that are
1189 * known by the hw.
1190 */
1191 if (crypto->wcid < 0)
f4450616 1192 return -ENOSPC;
a2b1328a 1193 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1194
1195 memcpy(key_entry.key, crypto->key,
1196 sizeof(key_entry.key));
1197 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198 sizeof(key_entry.tx_mic));
1199 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200 sizeof(key_entry.rx_mic));
1201
1202 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203 rt2800_register_multiwrite(rt2x00dev, offset,
1204 &key_entry, sizeof(key_entry));
1205 }
1206
1207 /*
1208 * Update WCID information
1209 */
a2b1328a 1210 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1211
1212 return 0;
1213}
1214EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
a2b1328a
HS		 1216int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217 struct ieee80211_sta *sta)
1218{
1219 int wcid;
1220 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222 /*
1223 * Find next free WCID.
1224 */
1225 wcid = rt2800_find_wcid(rt2x00dev);
1226
1227 /*
1228 * Store selected wcid even if it is invalid so that we can
1229 * later decide if the STA is uploaded into the hw.
1230 */
1231 sta_priv->wcid = wcid;
1232
1233 /*
1234 * No space left in the device, however, we can still communicate
1235 * with the STA -> No error.
1236 */
1237 if (wcid < 0)
1238 return 0;
1239
1240 /*
1241 * Clean up WCID attributes and write STA address to the device.
1242 */
1243 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246 rt2x00lib_get_bssidx(rt2x00dev, vif));
1247 return 0;
1248}
1249EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252{
1253 /*
1254 * Remove WCID entry, no need to clean the attributes as they will
1255 * get renewed when the WCID is reused.
1256 */
1257 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259 return 0;
1260}
1261EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
f4450616
BZ		 1263void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264 const unsigned int filter_flags)
1265{
1266 u32 reg;
1267
1268 /*
1269 * Start configuration steps.
1270 * Note that the version error will always be dropped
1271 * and broadcast frames will always be accepted since
1272 * there is no filter for it at this time.
1273 */
1274 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276 !(filter_flags & FIF_FCSFAIL));
1277 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278 !(filter_flags & FIF_PLCPFAIL));
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280 !(filter_flags & FIF_PROMISC_IN_BSS));
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284 !(filter_flags & FIF_ALLMULTI));
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288 !(filter_flags & FIF_CONTROL));
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290 !(filter_flags & FIF_CONTROL));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292 !(filter_flags & FIF_CONTROL));
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1300 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1301 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1302 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1303 !(filter_flags & FIF_CONTROL));
1304 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1305}
1306EXPORT_SYMBOL_GPL(rt2800_config_filter);
1307
1308void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1309 struct rt2x00intf_conf *conf, const unsigned int flags)
1310{
f4450616 1311 u32 reg;
fa8b4b22 1312 bool update_bssid = false;
f4450616
BZ		 1313
1314 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1315 /*
1316 * Enable synchronisation.
1317 */
1318 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1319 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1320 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1321
1322 if (conf->sync == TSF_SYNC_AP_NONE) {
1323 /*
1324 * Tune beacon queue transmit parameters for AP mode
1325 */
1326 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1327 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1328 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1329 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1330 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1331 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1332 } else {
1333 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1334 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1335 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1337 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1338 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1339 }
f4450616
BZ		 1340 }
1341
1342 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1343 if (flags & CONFIG_UPDATE_TYPE &&
1344 conf->sync == TSF_SYNC_AP_NONE) {
1345 /*
1346 * The BSSID register has to be set to our own mac
1347 * address in AP mode.
1348 */
1349 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1350 update_bssid = true;
1351 }
1352
c600c826
ID		 1353 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1354 reg = le32_to_cpu(conf->mac[1]);
1355 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1356 conf->mac[1] = cpu_to_le32(reg);
1357 }
f4450616
BZ		 1358
1359 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1360 conf->mac, sizeof(conf->mac));
1361 }
1362
fa8b4b22 1363 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1364 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1365 reg = le32_to_cpu(conf->bssid[1]);
1366 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1367 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1368 conf->bssid[1] = cpu_to_le32(reg);
1369 }
f4450616
BZ		 1370
1371 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1372 conf->bssid, sizeof(conf->bssid));
1373 }
1374}
1375EXPORT_SYMBOL_GPL(rt2800_config_intf);
1376
87c1915d
HS		 1377static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1378 struct rt2x00lib_erp *erp)
1379{
1380 bool any_sta_nongf = !!(erp->ht_opmode &
1381 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1382 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1383 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1384 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1385 u32 reg;
1386
1387 /* default protection rate for HT20: OFDM 24M */
1388 mm20_rate = gf20_rate = 0x4004;
1389
1390 /* default protection rate for HT40: duplicate OFDM 24M */
1391 mm40_rate = gf40_rate = 0x4084;
1392
1393 switch (protection) {
1394 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1395 /*
1396 * All STAs in this BSS are HT20/40 but there might be
1397 * STAs not supporting greenfield mode.
1398 * => Disable protection for HT transmissions.
1399 */
1400 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1401
1402 break;
1403 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1404 /*
1405 * All STAs in this BSS are HT20 or HT20/40 but there
1406 * might be STAs not supporting greenfield mode.
1407 * => Protect all HT40 transmissions.
1408 */
1409 mm20_mode = gf20_mode = 0;
1410 mm40_mode = gf40_mode = 2;
1411
1412 break;
1413 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1414 /*
1415 * Nonmember protection:
1416 * According to 802.11n we _should_ protect all
1417 * HT transmissions (but we don't have to).
1418 *
1419 * But if cts_protection is enabled we _shall_ protect
1420 * all HT transmissions using a CCK rate.
1421 *
1422 * And if any station is non GF we _shall_ protect
1423 * GF transmissions.
1424 *
1425 * We decide to protect everything
1426 * -> fall through to mixed mode.
1427 */
1428 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1429 /*
1430 * Legacy STAs are present
1431 * => Protect all HT transmissions.
1432 */
1433 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1434
1435 /*
1436 * If erp protection is needed we have to protect HT
1437 * transmissions with CCK 11M long preamble.
1438 */
1439 if (erp->cts_protection) {
1440 /* don't duplicate RTS/CTS in CCK mode */
1441 mm20_rate = mm40_rate = 0x0003;
1442 gf20_rate = gf40_rate = 0x0003;
1443 }
1444 break;
6403eab1 1445 }
87c1915d
HS		 1446
1447 /* check for STAs not supporting greenfield mode */
1448 if (any_sta_nongf)
1449 gf20_mode = gf40_mode = 2;
1450
1451 /* Update HT protection config */
1452 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1453 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1454 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1455 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1456
1457 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1458 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1459 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1460 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1461
1462 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1463 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1464 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1465 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1466
1467 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1468 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1469 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1470 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1471}
1472
02044643
HS		 1473void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1474 u32 changed)
f4450616
BZ		 1475{
1476 u32 reg;
1477
02044643
HS		 1478 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1479 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1480 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1481 !!erp->short_preamble);
1482 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1483 !!erp->short_preamble);
1484 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1485 }
f4450616 1486
02044643
HS		 1487 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1488 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1489 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1490 erp->cts_protection ? 2 : 0);
1491 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1492 }
f4450616 1493
02044643
HS		 1494 if (changed & BSS_CHANGED_BASIC_RATES) {
1495 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1496 erp->basic_rates);
1497 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1498 }
f4450616 1499
02044643
HS		 1500 if (changed & BSS_CHANGED_ERP_SLOT) {
1501 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1502 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1503 erp->slot_time);
1504 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1505
02044643
HS		 1506 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1507 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1508 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1509 }
f4450616 1510
02044643
HS		 1511 if (changed & BSS_CHANGED_BEACON_INT) {
1512 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1513 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1514 erp->beacon_int * 16);
1515 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1516 }
87c1915d
HS		 1517
1518 if (changed & BSS_CHANGED_HT)
1519 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1520}
1521EXPORT_SYMBOL_GPL(rt2800_config_erp);
1522
872834df
GW		 1523static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1524{
1525 u32 reg;
1526 u16 eeprom;
1527 u8 led_ctrl, led_g_mode, led_r_mode;
1528
1529 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1530 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1531 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1532 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1533 } else {
1534 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1535 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1536 }
1537 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1538
1539 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1540 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1541 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1542 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1543 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1544 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1545 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1546 if (led_ctrl == 0 || led_ctrl > 0x40) {
1547 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1548 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1549 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1550 } else {
1551 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1552 (led_g_mode << 2) | led_r_mode, 1);
1553 }
1554 }
1555}
1556
d96aa640
RJH		 1557static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1558 enum antenna ant)
1559{
1560 u32 reg;
1561 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1562 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1563
1564 if (rt2x00_is_pci(rt2x00dev)) {
1565 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1566 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1567 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1568 } else if (rt2x00_is_usb(rt2x00dev))
1569 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1570 eesk_pin, 0);
1571
99bdf51a
GW		 1572 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1573 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1574 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1575 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1576}
1577
f4450616
BZ		 1578void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1579{
1580 u8 r1;
1581 u8 r3;
d96aa640 1582 u16 eeprom;
f4450616
BZ		 1583
1584 rt2800_bbp_read(rt2x00dev, 1, &r1);
1585 rt2800_bbp_read(rt2x00dev, 3, &r3);
1586
872834df
GW		 1587 if (rt2x00_rt(rt2x00dev, RT3572) &&
1588 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1589 rt2800_config_3572bt_ant(rt2x00dev);
1590
f4450616
BZ		 1591 /*
1592 * Configure the TX antenna.
1593 */
d96aa640 1594 switch (ant->tx_chain_num) {
f4450616
BZ		 1595 case 1:
1596 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1597 break;
1598 case 2:
872834df
GW		 1599 if (rt2x00_rt(rt2x00dev, RT3572) &&
1600 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1601 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1602 else
1603 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1604 break;
1605 case 3:
e22557f2 1606 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1607 break;
1608 }
1609
1610 /*
1611 * Configure the RX antenna.
1612 */
d96aa640 1613 switch (ant->rx_chain_num) {
f4450616 1614 case 1:
d96aa640
RJH		 1615 if (rt2x00_rt(rt2x00dev, RT3070) ||
1616 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1617 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 1618 rt2x00_rt(rt2x00dev, RT3390)) {
1619 rt2x00_eeprom_read(rt2x00dev,
1620 EEPROM_NIC_CONF1, &eeprom);
1621 if (rt2x00_get_field16(eeprom,
1622 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1623 rt2800_set_ant_diversity(rt2x00dev,
1624 rt2x00dev->default_ant.rx);
1625 }
f4450616
BZ		 1626 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1627 break;
1628 case 2:
872834df
GW		 1629 if (rt2x00_rt(rt2x00dev, RT3572) &&
1630 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1631 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1632 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1633 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1634 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1635 } else {
1636 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1637 }
f4450616
BZ		 1638 break;
1639 case 3:
1640 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1641 break;
1642 }
1643
1644 rt2800_bbp_write(rt2x00dev, 3, r3);
1645 rt2800_bbp_write(rt2x00dev, 1, r1);
1646}
1647EXPORT_SYMBOL_GPL(rt2800_config_ant);
1648
1649static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1650 struct rt2x00lib_conf *libconf)
1651{
1652 u16 eeprom;
1653 short lna_gain;
1654
1655 if (libconf->rf.channel <= 14) {
1656 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1658 } else if (libconf->rf.channel <= 64) {
1659 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1660 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1661 } else if (libconf->rf.channel <= 128) {
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1663 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1664 } else {
1665 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1666 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1667 }
1668
1669 rt2x00dev->lna_gain = lna_gain;
1670}
1671
06855ef4
GW		 1672static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1673 struct ieee80211_conf *conf,
1674 struct rf_channel *rf,
1675 struct channel_info *info)
f4450616
BZ		 1676{
1677 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1678
d96aa640 1679 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1680 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1681
d96aa640 1682 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1683 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1684 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1685 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1686 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687
1688 if (rf->channel > 14) {
1689 /*
1690 * When TX power is below 0, we should increase it by 7 to
25985edc 1691 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1692 * However this means that values between 0 and 7 have
1693 * double meaning, and we should set a 7DBm boost flag.
1694 */
1695 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1696 (info->default_power1 >= 0));
f4450616 1697
8d1331b3
ID		 1698 if (info->default_power1 < 0)
1699 info->default_power1 += 7;
f4450616 1700
8d1331b3 1701 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1702
1703 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1704 (info->default_power2 >= 0));
f4450616 1705
8d1331b3
ID		 1706 if (info->default_power2 < 0)
1707 info->default_power2 += 7;
f4450616 1708
8d1331b3 1709 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1710 } else {
8d1331b3
ID		 1711 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1712 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1713 }
1714
1715 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1716
1717 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1718 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1719 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1720 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1721
1722 udelay(200);
1723
1724 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1725 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1726 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1727 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1728
1729 udelay(200);
1730
1731 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1732 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1733 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1734 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1735}
1736
06855ef4
GW		 1737static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1738 struct ieee80211_conf *conf,
1739 struct rf_channel *rf,
1740 struct channel_info *info)
f4450616 1741{
3a1c0128 1742 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1743 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1744
1745 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1746
1747 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1748 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1749 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1750
1751 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1752 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1753 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1754
1755 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1756 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1757 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1758
5a673964 1759 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1760 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1761 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1762
1763 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 1765 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1766 rt2x00dev->default_ant.rx_chain_num <= 1);
1767 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1768 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 1769 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 1770 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1771 rt2x00dev->default_ant.tx_chain_num <= 1);
1772 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1773 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 1774 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1775
3e0c7643
SG		 1776 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1777 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1778 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779 msleep(1);
1780 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1781 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1782
f4450616
BZ		 1783 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1784 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1785 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1786
f1f12f98
SG		 1787 if (rt2x00_rt(rt2x00dev, RT3390)) {
1788 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1789 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1790 } else {
3a1c0128
GW		 1791 if (conf_is_ht40(conf)) {
1792 calib_tx = drv_data->calibration_bw40;
1793 calib_rx = drv_data->calibration_bw40;
1794 } else {
1795 calib_tx = drv_data->calibration_bw20;
1796 calib_rx = drv_data->calibration_bw20;
1797 }
f1f12f98
SG		 1798 }
1799
1800 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1801 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1802 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1803
1804 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1805 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1806 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1807
71976907 1808 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1809 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1810 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1811
1812 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1813 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1814 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815 msleep(1);
1816 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1817 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1818}
1819
872834df
GW		 1820static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1821 struct ieee80211_conf *conf,
1822 struct rf_channel *rf,
1823 struct channel_info *info)
1824{
3a1c0128 1825 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1826 u8 rfcsr;
1827 u32 reg;
1828
1829 if (rf->channel <= 14) {
5d137dff
GW		 1830 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1831 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1832 } else {
1833 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1834 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1835 }
1836
1837 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1838 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1839
1840 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1841 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1842 if (rf->channel <= 14)
1843 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1844 else
1845 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1846 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1847
1848 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1849 if (rf->channel <= 14)
1850 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1851 else
1852 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1853 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1854
1855 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1856 if (rf->channel <= 14) {
1857 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1858 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1859 info->default_power1);
872834df
GW		 1860 } else {
1861 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1862 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1863 (info->default_power1 & 0x3) |
1864 ((info->default_power1 & 0xC) << 1));
1865 }
1866 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1867
1868 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1869 if (rf->channel <= 14) {
1870 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1871 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1872 info->default_power2);
872834df
GW		 1873 } else {
1874 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1875 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1876 (info->default_power2 & 0x3) |
1877 ((info->default_power2 & 0xC) << 1));
1878 }
1879 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1880
1881 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1882 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1885 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1886 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1887 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1888 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1889 if (rf->channel <= 14) {
1890 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1891 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1892 }
1893 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1894 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1895 } else {
1896 switch (rt2x00dev->default_ant.tx_chain_num) {
1897 case 1:
1898 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1899 case 2:
1900 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901 break;
1902 }
1903
1904 switch (rt2x00dev->default_ant.rx_chain_num) {
1905 case 1:
1906 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1907 case 2:
1908 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1909 break;
1910 }
1911 }
1912 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1913
1914 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1915 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1916 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1917
3a1c0128
GW		 1918 if (conf_is_ht40(conf)) {
1919 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1920 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1921 } else {
1922 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1923 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1924 }
872834df
GW		 1925
1926 if (rf->channel <= 14) {
1927 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1928 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1929 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1930 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1931 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1932 rfcsr = 0x4c;
1933 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1934 drv_data->txmixer_gain_24g);
1935 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1936 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1937 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1938 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1939 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1940 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1941 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1942 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1943 } else {
58b8ae14
GW		 1944 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1945 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1946 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1947 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1948 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1949 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1950 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1951 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1952 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1953 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1954 rfcsr = 0x7a;
1955 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1956 drv_data->txmixer_gain_5g);
1957 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1958 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1959 if (rf->channel <= 64) {
1960 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1961 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1962 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1963 } else if (rf->channel <= 128) {
1964 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1965 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1966 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1967 } else {
1968 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1969 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1970 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1971 }
1972 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1973 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1974 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1975 }
1976
99bdf51a
GW		 1977 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1978 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 1979 if (rf->channel <= 14)
99bdf51a 1980 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 1981 else
99bdf51a
GW		 1982 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1983 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 1984
1985 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1986 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1987 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1988}
60687ba7 1989
7573cb5b
SG		 1990#define POWER_BOUND 0x27
1991#define FREQ_OFFSET_BOUND 0x5f
60687ba7 1992
a89534ed
WH		 1993static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1994 struct ieee80211_conf *conf,
1995 struct rf_channel *rf,
1996 struct channel_info *info)
1997{
1998 u8 rfcsr;
1999
2000 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2001 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2002 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2003 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2004 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2005
2006 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2007 if (info->default_power1 > POWER_BOUND)
2008 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2009 else
2010 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2011 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2012
2013 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
7573cb5b
SG		 2014 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2015 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
a89534ed
WH		 2016 else
2017 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2018 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2019
2020 if (rf->channel <= 14) {
2021 if (rf->channel == 6)
2022 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2023 else
2024 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2025
2026 if (rf->channel >= 1 && rf->channel <= 6)
2027 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2028 else if (rf->channel >= 7 && rf->channel <= 11)
2029 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2030 else if (rf->channel >= 12 && rf->channel <= 14)
2031 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2032 }
2033}
2034
03839951
DG		 2035static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2036 struct ieee80211_conf *conf,
2037 struct rf_channel *rf,
2038 struct channel_info *info)
2039{
2040 u8 rfcsr;
2041
2042 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2043 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2044
2045 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2046 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2047 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2048
2049 if (info->default_power1 > POWER_BOUND)
2050 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2051 else
2052 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2053
2054 if (info->default_power2 > POWER_BOUND)
2055 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2056 else
2057 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2058
2059 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2060 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2061 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2062 else
2063 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2064
2065 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2066
2067 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2068 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2069 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2070
2071 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2072 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2073 else
2074 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2075
2076 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2077 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2078 else
2079 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2080
2081 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2082 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2083
2084 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2085
2086 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2087}
2088
60687ba7 2089static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2090 struct ieee80211_conf *conf,
2091 struct rf_channel *rf,
2092 struct channel_info *info)
2093{
2094 u8 rfcsr;
adde5882
GJ		 2095
2096 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2097 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2098 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2099 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2100 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2101
2102 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2103 if (info->default_power1 > POWER_BOUND)
2104 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2105 else
2106 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2107 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2108
cff3d1f0
ZL		 2109 if (rt2x00_rt(rt2x00dev, RT5392)) {
2110 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
7573cb5b
SG		 2111 if (info->default_power1 > POWER_BOUND)
2112 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2113 else
2114 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2115 info->default_power2);
2116 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2117 }
2118
adde5882 2119 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2120 if (rt2x00_rt(rt2x00dev, RT5392)) {
2121 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2122 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2123 }
adde5882
GJ		 2124 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2125 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2126 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2127 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2128 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2129
2130 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
7573cb5b
SG		 2131 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2132 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
adde5882
GJ		 2133 else
2134 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2135 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2136
adde5882
GJ		 2137 if (rf->channel <= 14) {
2138 int idx = rf->channel-1;
2139
fdbc7b0a 2140 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 2141 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2142 /* r55/r59 value array of channel 1~14 */
2143 static const char r55_bt_rev[] = {0x83, 0x83,
2144 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2145 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2146 static const char r59_bt_rev[] = {0x0e, 0x0e,
2147 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2148 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2149
2150 rt2800_rfcsr_write(rt2x00dev, 55,
2151 r55_bt_rev[idx]);
2152 rt2800_rfcsr_write(rt2x00dev, 59,
2153 r59_bt_rev[idx]);
2154 } else {
2155 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2156 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2157 0x88, 0x88, 0x86, 0x85, 0x84};
2158
2159 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2160 }
2161 } else {
2162 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2163 static const char r55_nonbt_rev[] = {0x23, 0x23,
2164 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2165 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2166 static const char r59_nonbt_rev[] = {0x07, 0x07,
2167 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2168 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2169
2170 rt2800_rfcsr_write(rt2x00dev, 55,
2171 r55_nonbt_rev[idx]);
2172 rt2800_rfcsr_write(rt2x00dev, 59,
2173 r59_nonbt_rev[idx]);
2ed71884 2174 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2175 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2176 static const char r59_non_bt[] = {0x8f, 0x8f,
2177 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2178 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2179
2180 rt2800_rfcsr_write(rt2x00dev, 59,
2181 r59_non_bt[idx]);
2182 }
2183 }
2184 }
60687ba7
RST		 2185}
2186
f4450616
BZ		 2187static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2188 struct ieee80211_conf *conf,
2189 struct rf_channel *rf,
2190 struct channel_info *info)
2191{
2192 u32 reg;
2193 unsigned int tx_pin;
a89534ed 2194 u8 bbp, rfcsr;
f4450616 2195
46323e11 2196 if (rf->channel <= 14) {
8d1331b3
ID		 2197 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2198 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2199 } else {
8d1331b3
ID		 2200 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2201 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2202 }
2203
5aa57015
GW		 2204 switch (rt2x00dev->chip.rf) {
2205 case RF2020:
2206 case RF3020:
2207 case RF3021:
2208 case RF3022:
2209 case RF3320:
06855ef4 2210 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2211 break;
2212 case RF3052:
872834df 2213 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 2214 break;
a89534ed
WH		 2215 case RF3290:
2216 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2217 break;
03839951
DG		 2218 case RF3322:
2219 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2220 break;
ccf91bd6 2221 case RF5360:
5aa57015 2222 case RF5370:
2ed71884 2223 case RF5372:
5aa57015 2224 case RF5390:
cff3d1f0 2225 case RF5392:
adde5882 2226 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2227 break;
2228 default:
06855ef4 2229 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2230 }
f4450616 2231
a89534ed 2232 if (rt2x00_rf(rt2x00dev, RF3290) ||
03839951 2233 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 2234 rt2x00_rf(rt2x00dev, RF5360) ||
2235 rt2x00_rf(rt2x00dev, RF5370) ||
2236 rt2x00_rf(rt2x00dev, RF5372) ||
2237 rt2x00_rf(rt2x00dev, RF5390) ||
2238 rt2x00_rf(rt2x00dev, RF5392)) {
2239 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2240 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2241 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2242 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2243
2244 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2245 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 2246 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2247 }
2248
f4450616
BZ		 2249 /*
2250 * Change BBP settings
2251 */
03839951
DG		 2252 if (rt2x00_rt(rt2x00dev, RT3352)) {
2253 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 2254 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 2255 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 2256 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951
DG		 2257 } else {
2258 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2259 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2260 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2261 rt2800_bbp_write(rt2x00dev, 86, 0);
2262 }
f4450616
BZ		 2263
2264 if (rf->channel <= 14) {
2ed71884 2265 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 2266 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2267 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2268 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2269 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2270 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2271 } else {
2272 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2273 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2274 }
f4450616
BZ		 2275 }
2276 } else {
872834df
GW		 2277 if (rt2x00_rt(rt2x00dev, RT3572))
2278 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2279 else
2280 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2281
7dab73b3 2282 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2283 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2284 else
2285 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2286 }
2287
2288 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2289 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2290 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2291 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2292 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2293
872834df
GW		 2294 if (rt2x00_rt(rt2x00dev, RT3572))
2295 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2296
f4450616
BZ		 2297 tx_pin = 0;
2298
2299 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2300 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2301 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2302 rf->channel > 14);
2303 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2304 rf->channel <= 14);
f4450616
BZ		 2305 }
2306
2307 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2308 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2311 }
2312
2313 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2314 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2317 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2318 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2319 else
2320 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2321 rf->channel <= 14);
f4450616
BZ		 2322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2323
2324 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2325
872834df
GW		 2326 if (rt2x00_rt(rt2x00dev, RT3572))
2327 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2328
f4450616
BZ		 2329 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2330 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2331 rt2800_bbp_write(rt2x00dev, 4, bbp);
2332
2333 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2334 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2335 rt2800_bbp_write(rt2x00dev, 3, bbp);
2336
8d0c9b65 2337 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2338 if (conf_is_ht40(conf)) {
2339 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2340 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2341 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2342 } else {
2343 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2344 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2345 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2346 }
2347 }
2348
2349 msleep(1);
977206d7
HS		 2350
2351 /*
2352 * Clear channel statistic counters
2353 */
2354 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2355 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2356 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 2357
2358 /*
2359 * Clear update flag
2360 */
2361 if (rt2x00_rt(rt2x00dev, RT3352)) {
2362 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2363 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2364 rt2800_bbp_write(rt2x00dev, 49, bbp);
2365 }
f4450616
BZ		 2366}
2367
9e33a355
HS		 2368static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2369{
2370 u8 tssi_bounds[9];
2371 u8 current_tssi;
2372 u16 eeprom;
2373 u8 step;
2374 int i;
2375
2376 /*
2377 * Read TSSI boundaries for temperature compensation from
2378 * the EEPROM.
2379 *
2380 * Array idx 0 1 2 3 4 5 6 7 8
2381 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2382 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2383 */
2384 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2385 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2386 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2387 EEPROM_TSSI_BOUND_BG1_MINUS4);
2388 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2389 EEPROM_TSSI_BOUND_BG1_MINUS3);
2390
2391 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2392 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2393 EEPROM_TSSI_BOUND_BG2_MINUS2);
2394 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2395 EEPROM_TSSI_BOUND_BG2_MINUS1);
2396
2397 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2398 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2399 EEPROM_TSSI_BOUND_BG3_REF);
2400 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2401 EEPROM_TSSI_BOUND_BG3_PLUS1);
2402
2403 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2404 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2405 EEPROM_TSSI_BOUND_BG4_PLUS2);
2406 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2407 EEPROM_TSSI_BOUND_BG4_PLUS3);
2408
2409 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2410 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2411 EEPROM_TSSI_BOUND_BG5_PLUS4);
2412
2413 step = rt2x00_get_field16(eeprom,
2414 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2415 } else {
2416 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2417 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2418 EEPROM_TSSI_BOUND_A1_MINUS4);
2419 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2420 EEPROM_TSSI_BOUND_A1_MINUS3);
2421
2422 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2423 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2424 EEPROM_TSSI_BOUND_A2_MINUS2);
2425 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2426 EEPROM_TSSI_BOUND_A2_MINUS1);
2427
2428 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2429 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2430 EEPROM_TSSI_BOUND_A3_REF);
2431 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2432 EEPROM_TSSI_BOUND_A3_PLUS1);
2433
2434 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2435 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2436 EEPROM_TSSI_BOUND_A4_PLUS2);
2437 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2438 EEPROM_TSSI_BOUND_A4_PLUS3);
2439
2440 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2441 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2442 EEPROM_TSSI_BOUND_A5_PLUS4);
2443
2444 step = rt2x00_get_field16(eeprom,
2445 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2446 }
2447
2448 /*
2449 * Check if temperature compensation is supported.
2450 */
bf7e1abe 2451 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 2452 return 0;
2453
2454 /*
2455 * Read current TSSI (BBP 49).
2456 */
2457 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2458
2459 /*
2460 * Compare TSSI value (BBP49) with the compensation boundaries
2461 * from the EEPROM and increase or decrease tx power.
2462 */
2463 for (i = 0; i <= 3; i++) {
2464 if (current_tssi > tssi_bounds[i])
2465 break;
2466 }
2467
2468 if (i == 4) {
2469 for (i = 8; i >= 5; i--) {
2470 if (current_tssi < tssi_bounds[i])
2471 break;
2472 }
2473 }
2474
2475 return (i - 4) * step;
2476}
2477
e90c54b2
RJH		 2478static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2479 enum ieee80211_band band)
2480{
2481 u16 eeprom;
2482 u8 comp_en;
2483 u8 comp_type;
75faae8b 2484 int comp_value = 0;
e90c54b2
RJH		 2485
2486 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2487
75faae8b
HS		 2488 /*
2489 * HT40 compensation not required.
2490 */
2491 if (eeprom == 0xffff ||
2492 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2493 return 0;
2494
2495 if (band == IEEE80211_BAND_2GHZ) {
2496 comp_en = rt2x00_get_field16(eeprom,
2497 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2498 if (comp_en) {
2499 comp_type = rt2x00_get_field16(eeprom,
2500 EEPROM_TXPOWER_DELTA_TYPE_2G);
2501 comp_value = rt2x00_get_field16(eeprom,
2502 EEPROM_TXPOWER_DELTA_VALUE_2G);
2503 if (!comp_type)
2504 comp_value = -comp_value;
2505 }
2506 } else {
2507 comp_en = rt2x00_get_field16(eeprom,
2508 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2509 if (comp_en) {
2510 comp_type = rt2x00_get_field16(eeprom,
2511 EEPROM_TXPOWER_DELTA_TYPE_5G);
2512 comp_value = rt2x00_get_field16(eeprom,
2513 EEPROM_TXPOWER_DELTA_VALUE_5G);
2514 if (!comp_type)
2515 comp_value = -comp_value;
2516 }
2517 }
2518
2519 return comp_value;
2520}
2521
1e4cf249
SG		 2522static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2523 int power_level, int max_power)
2524{
2525 int delta;
2526
2527 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2528 return 0;
2529
2530 /*
2531 * XXX: We don't know the maximum transmit power of our hardware since
2532 * the EEPROM doesn't expose it. We only know that we are calibrated
2533 * to 100% tx power.
2534 *
2535 * Hence, we assume the regulatory limit that cfg80211 calulated for
2536 * the current channel is our maximum and if we are requested to lower
2537 * the value we just reduce our tx power accordingly.
2538 */
2539 delta = power_level - max_power;
2540 return min(delta, 0);
2541}
2542
fa71a160
HS		 2543static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2544 enum ieee80211_band band, int power_level,
2545 u8 txpower, int delta)
e90c54b2 2546{
e90c54b2
RJH		 2547 u16 eeprom;
2548 u8 criterion;
2549 u8 eirp_txpower;
2550 u8 eirp_txpower_criterion;
2551 u8 reg_limit;
e90c54b2 2552
7dab73b3 2553 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2554 /*
2555 * Check if eirp txpower exceed txpower_limit.
2556 * We use OFDM 6M as criterion and its eirp txpower
2557 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2558 * .11b data rate need add additional 4dbm
2559 * when calculating eirp txpower.
2560 */
d9bceaeb
SG		 2561 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2562 &eeprom);
2563 criterion = rt2x00_get_field16(eeprom,
2564 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 2565
d9bceaeb
SG		 2566 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2567 &eeprom);
e90c54b2
RJH		 2568
2569 if (band == IEEE80211_BAND_2GHZ)
2570 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2571 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2572 else
2573 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2574 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2575
2576 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2577 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2578
2579 reg_limit = (eirp_txpower > power_level) ?
2580 (eirp_txpower - power_level) : 0;
2581 } else
2582 reg_limit = 0;
2583
19f3fa24
SG		 2584 txpower = max(0, txpower + delta - reg_limit);
2585 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 2586}
2587
7a66205a
SG		 2588/*
2589 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2590 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2591 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2592 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2593 * Reference per rate transmit power values are located in the EEPROM at
2594 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2595 * current conditions (i.e. band, bandwidth, temperature, user settings).
2596 */
f4450616 2597static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
146c3b0c 2598 struct ieee80211_channel *chan,
9e33a355 2599 int power_level)
f4450616 2600{
cee2c731 2601 u8 txpower, r1;
5e846004 2602 u16 eeprom;
cee2c731
SG		 2603 u32 reg, offset;
2604 int i, is_rate_b, delta, power_ctrl;
146c3b0c 2605 enum ieee80211_band band = chan->band;
2af242e1
HS		 2606
2607 /*
7a66205a
SG		 2608 * Calculate HT40 compensation. For 40MHz we need to add or subtract
2609 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 2610 */
2611 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2612
9e33a355 2613 /*
7a66205a
SG		 2614 * Calculate temperature compensation. Depends on measurement of current
2615 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2616 * to temperature or maybe other factors) is smaller or bigger than
2617 * expected. We adjust it, based on TSSI reference and boundaries values
2618 * provided in EEPROM.
9e33a355
HS		 2619 */
2620 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2621
1e4cf249 2622 /*
7a66205a
SG		 2623 * Decrease power according to user settings, on devices with unknown
2624 * maximum tx power. For other devices we take user power_level into
2625 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 2626 */
2627 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2628 chan->max_power);
2629
5e846004 2630 /*
cee2c731
SG		 2631 * BBP_R1 controls TX power for all rates, it allow to set the following
2632 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2633 *
2634 * TODO: we do not use +6 dBm option to do not increase power beyond
2635 * regulatory limit, however this could be utilized for devices with
2636 * CAPABILITY_POWER_LIMIT.
5e846004 2637 */
f4450616 2638 rt2800_bbp_read(rt2x00dev, 1, &r1);
cee2c731
SG		 2639 if (delta <= -12) {
2640 power_ctrl = 2;
2641 delta += 12;
2642 } else if (delta <= -6) {
2643 power_ctrl = 1;
2644 delta += 6;
2645 } else {
2646 power_ctrl = 0;
2647 }
2648 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
f4450616 2649 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2650 offset = TX_PWR_CFG_0;
2651
2652 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2653 /* just to be safe */
2654 if (offset > TX_PWR_CFG_4)
2655 break;
2656
2657 rt2800_register_read(rt2x00dev, offset, &reg);
2658
2659 /* read the next four txpower values */
2660 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2661 &eeprom);
2662
e90c54b2
RJH		 2663 is_rate_b = i ? 0 : 1;
2664 /*
2665 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2666 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2667 * TX_PWR_CFG_4: unknown
2668 */
5e846004
HS		 2669 txpower = rt2x00_get_field16(eeprom,
2670 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2671 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2672 power_level, txpower, delta);
e90c54b2 2673 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2674
e90c54b2
RJH		 2675 /*
2676 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2677 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2678 * TX_PWR_CFG_4: unknown
2679 */
5e846004
HS		 2680 txpower = rt2x00_get_field16(eeprom,
2681 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2682 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2683 power_level, txpower, delta);
e90c54b2 2684 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2685
e90c54b2
RJH		 2686 /*
2687 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2688 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2689 * TX_PWR_CFG_4: unknown
2690 */
5e846004
HS		 2691 txpower = rt2x00_get_field16(eeprom,
2692 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2693 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2694 power_level, txpower, delta);
e90c54b2 2695 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2696
e90c54b2
RJH		 2697 /*
2698 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2699 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2700 * TX_PWR_CFG_4: unknown
2701 */
5e846004
HS		 2702 txpower = rt2x00_get_field16(eeprom,
2703 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2704 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2705 power_level, txpower, delta);
e90c54b2 2706 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2707
2708 /* read the next four txpower values */
2709 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2710 &eeprom);
2711
e90c54b2
RJH		 2712 is_rate_b = 0;
2713 /*
2714 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2715 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2716 * TX_PWR_CFG_4: unknown
2717 */
5e846004
HS		 2718 txpower = rt2x00_get_field16(eeprom,
2719 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2720 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2721 power_level, txpower, delta);
e90c54b2 2722 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2723
e90c54b2
RJH		 2724 /*
2725 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2726 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2727 * TX_PWR_CFG_4: unknown
2728 */
5e846004
HS		 2729 txpower = rt2x00_get_field16(eeprom,
2730 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2731 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2732 power_level, txpower, delta);
e90c54b2 2733 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2734
e90c54b2
RJH		 2735 /*
2736 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2737 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2738 * TX_PWR_CFG_4: unknown
2739 */
5e846004
HS		 2740 txpower = rt2x00_get_field16(eeprom,
2741 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2742 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2743 power_level, txpower, delta);
e90c54b2 2744 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2745
e90c54b2
RJH		 2746 /*
2747 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2748 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2749 * TX_PWR_CFG_4: unknown
2750 */
5e846004
HS		 2751 txpower = rt2x00_get_field16(eeprom,
2752 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2753 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2754 power_level, txpower, delta);
e90c54b2 2755 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2756
2757 rt2800_register_write(rt2x00dev, offset, reg);
2758
2759 /* next TX_PWR_CFG register */
2760 offset += 4;
2761 }
f4450616
BZ		 2762}
2763
9e33a355
HS		 2764void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2765{
146c3b0c 2766 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
9e33a355
HS		 2767 rt2x00dev->tx_power);
2768}
2769EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2770
2e9c43dd
JL		 2771void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2772{
2773 u32 tx_pin;
2774 u8 rfcsr;
2775
2776 /*
2777 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2778 * designed to be controlled in oscillation frequency by a voltage
2779 * input. Maybe the temperature will affect the frequency of
2780 * oscillation to be shifted. The VCO calibration will be called
2781 * periodically to adjust the frequency to be precision.
2782 */
2783
2784 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2785 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2786 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2787
2788 switch (rt2x00dev->chip.rf) {
2789 case RF2020:
2790 case RF3020:
2791 case RF3021:
2792 case RF3022:
2793 case RF3320:
2794 case RF3052:
2795 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2796 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2797 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2798 break;
a89534ed 2799 case RF3290:
ccf91bd6 2800 case RF5360:
2e9c43dd
JL		 2801 case RF5370:
2802 case RF5372:
2803 case RF5390:
cff3d1f0 2804 case RF5392:
2e9c43dd 2805 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 2806 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 2807 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2808 break;
2809 default:
2810 return;
2811 }
2812
2813 mdelay(1);
2814
2815 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2816 if (rt2x00dev->rf_channel <= 14) {
2817 switch (rt2x00dev->default_ant.tx_chain_num) {
2818 case 3:
2819 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2820 /* fall through */
2821 case 2:
2822 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2823 /* fall through */
2824 case 1:
2825 default:
2826 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2827 break;
2828 }
2829 } else {
2830 switch (rt2x00dev->default_ant.tx_chain_num) {
2831 case 3:
2832 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2833 /* fall through */
2834 case 2:
2835 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2836 /* fall through */
2837 case 1:
2838 default:
2839 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2840 break;
2841 }
2842 }
2843 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2844
2845}
2846EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2847
f4450616
BZ		 2848static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2849 struct rt2x00lib_conf *libconf)
2850{
2851 u32 reg;
2852
2853 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2854 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2855 libconf->conf->short_frame_max_tx_count);
2856 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2857 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2858 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2859}
2860
2861static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2862 struct rt2x00lib_conf *libconf)
2863{
2864 enum dev_state state =
2865 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2866 STATE_SLEEP : STATE_AWAKE;
2867 u32 reg;
2868
2869 if (state == STATE_SLEEP) {
2870 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2871
2872 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2873 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2874 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2875 libconf->conf->listen_interval - 1);
2876 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2877 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2878
2879 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2880 } else {
f4450616
BZ		 2881 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2882 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2883 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2884 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2885 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2886
2887 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2888 }
2889}
2890
2891void rt2800_config(struct rt2x00_dev *rt2x00dev,
2892 struct rt2x00lib_conf *libconf,
2893 const unsigned int flags)
2894{
2895 /* Always recalculate LNA gain before changing configuration */
2896 rt2800_config_lna_gain(rt2x00dev, libconf);
2897
e90c54b2 2898 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2899 rt2800_config_channel(rt2x00dev, libconf->conf,
2900 &libconf->rf, &libconf->channel);
146c3b0c 2901 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
9e33a355 2902 libconf->conf->power_level);
e90c54b2 2903 }
f4450616 2904 if (flags & IEEE80211_CONF_CHANGE_POWER)
146c3b0c 2905 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
9e33a355 2906 libconf->conf->power_level);
f4450616
BZ		 2907 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2908 rt2800_config_retry_limit(rt2x00dev, libconf);
2909 if (flags & IEEE80211_CONF_CHANGE_PS)
2910 rt2800_config_ps(rt2x00dev, libconf);
2911}
2912EXPORT_SYMBOL_GPL(rt2800_config);
2913
2914/*
2915 * Link tuning
2916 */
2917void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2918{
2919 u32 reg;
2920
2921 /*
2922 * Update FCS error count from register.
2923 */
2924 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2925 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2926}
2927EXPORT_SYMBOL_GPL(rt2800_link_stats);
2928
2929static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2930{
8c6728b0
GW		 2931 u8 vgc;
2932
f4450616 2933 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2934 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2935 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2936 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 2937 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 2938 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 2939 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 2940 rt2x00_rt(rt2x00dev, RT5390) ||
2941 rt2x00_rt(rt2x00dev, RT5392))
8c6728b0
GW		 2942 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
2943 else
2944 vgc = 0x2e + rt2x00dev->lna_gain;
2945 } else { /* 5GHZ band */
d961e447
GW		 2946 if (rt2x00_rt(rt2x00dev, RT3572))
2947 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
2948 else {
2949 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2950 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2951 else
2952 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2953 }
f4450616
BZ		 2954 }
2955
8c6728b0 2956 return vgc;
f4450616
BZ		 2957}
2958
2959static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2960 struct link_qual *qual, u8 vgc_level)
2961{
2962 if (qual->vgc_level != vgc_level) {
2963 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2964 qual->vgc_level = vgc_level;
2965 qual->vgc_level_reg = vgc_level;
2966 }
2967}
2968
2969void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2970{
2971 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2972}
2973EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2974
2975void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2976 const u32 count)
2977{
8d0c9b65 2978 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2979 return;
2980
2981 /*
2982 * When RSSI is better then -80 increase VGC level with 0x10
2983 */
2984 rt2800_set_vgc(rt2x00dev, qual,
2985 rt2800_get_default_vgc(rt2x00dev) +
2986 ((qual->rssi > -80) * 0x10));
2987}
2988EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2989
2990/*
2991 * Initialization functions.
2992 */
b9a07ae9 2993static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2994{
2995 u32 reg;
d5385bfc 2996 u16 eeprom;
fcf51541 2997 unsigned int i;
e3a896b9 2998 int ret;
fcf51541 2999
f7b395e9 3000 rt2800_disable_wpdma(rt2x00dev);
a9dce149 3001
e3a896b9
GW		 3002 ret = rt2800_drv_init_registers(rt2x00dev);
3003 if (ret)
3004 return ret;
fcf51541
BZ		 3005
3006 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3007 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3008 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3009 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3010 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3011 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3012
3013 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3014 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3015 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3016 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3017 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3018 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3019
3020 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3021 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3022
3023 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3024
3025 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 3026 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 3027 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3028 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3029 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3030 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3031 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3033
a9dce149
GW		 3034 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3035
3036 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3037 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3038 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3039 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3040
a89534ed
WH		 3041 if (rt2x00_rt(rt2x00dev, RT3290)) {
3042 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3043 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3044 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3045 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3046 }
3047
3048 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3049 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3050 rt2x00_set_field32(&reg, LDO0_EN, 1);
3051 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3052 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3053 }
3054
3055 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3056 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3057 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3058 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3059 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3060
3061 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3062 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3063 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3064
3065 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3066 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3067 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3068 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3069 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3070 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3071
3072 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3073 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3074 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3075 }
3076
64522957 3077 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3078 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 3079 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 3080 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 3081
3082 if (rt2x00_rt(rt2x00dev, RT3290))
3083 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3084 0x00000404);
3085 else
3086 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3087 0x00000400);
3088
fcf51541 3089 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 3090 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3091 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3092 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 3093 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3094 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3095 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3096 0x0000002c);
3097 else
3098 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3099 0x0000000f);
3100 } else {
3101 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3102 }
d5385bfc 3103 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 3104 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 3105
3106 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3107 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3108 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3109 } else {
3110 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3111 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3112 }
c295a81d
HS		 3113 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3114 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3115 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 3116 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 3117 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3118 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3119 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3120 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 3121 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3122 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3123 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884 3124 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5b196139 3125 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3126 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3127 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3128 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 3129 } else {
3130 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3131 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3132 }
3133
3134 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3135 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3136 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3137 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3138 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3139 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3140 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3141 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3142 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3143 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3144
3145 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3146 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 3147 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 3148 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3149 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3150
3151 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3152 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 3153 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 3154 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 3155 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 3156 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3157 else
3158 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3159 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3160 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3161 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3162
a9dce149
GW		 3163 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3164 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3165 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3166 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3167 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3168 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3169 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3170 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3171 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3172
fcf51541
BZ		 3173 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3174
a9dce149
GW		 3175 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3176 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3177 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3178 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3179 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3180 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3181 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3182 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3183
fcf51541
BZ		 3184 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3185 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 3186 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 3187 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3188 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 3189 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 3190 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3191 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3192 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3193
3194 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 3195 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3196 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3197 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3198 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3199 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3200 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3201 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3202 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3203 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3204 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3205 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3206
3207 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 3208 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 3209 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3210 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3211 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3212 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3213 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 3214 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 3215 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 3216 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3217 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 3218 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3219
3220 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3221 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3222 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3223 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3224 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3225 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3226 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3227 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3228 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3229 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3230 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3231 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3232
3233 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3234 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 3235 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3236 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3237 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3238 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3239 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3240 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3241 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3242 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3243 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3244 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3245
3246 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3247 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3248 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3249 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3250 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3251 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3252 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3253 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3254 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3255 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 3256 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3257 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3258
3259 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3260 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3261 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 3262 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 3263 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3264 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3265 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3266 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3267 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3268 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 3269 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 3270 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3271
cea90e55 3272 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 3273 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3274
3275 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3285 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3286 }
3287
961621ab
HS		 3288 /*
3289 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3290 * although it is reserved.
3291 */
3292 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3293 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3294 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3295 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3296 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3297 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3298 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3299 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3300 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3301 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3302 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3303 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3304
fcf51541
BZ		 3305 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3306
3307 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3308 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3309 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3310 IEEE80211_MAX_RTS_THRESHOLD);
3311 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3312 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3313
3314 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 3315
a21c2ab4
HS		 3316 /*
3317 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3318 * time should be set to 16. However, the original Ralink driver uses
3319 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3320 * connection problems with 11g + CTS protection. Hence, use the same
3321 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3322 */
a9dce149 3323 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3324 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3325 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3326 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3327 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3328 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3329 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3330
fcf51541
BZ		 3331 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3332
3333 /*
3334 * ASIC will keep garbage value after boot, clear encryption keys.
3335 */
3336 for (i = 0; i < 4; i++)
3337 rt2800_register_write(rt2x00dev,
3338 SHARED_KEY_MODE_ENTRY(i), 0);
3339
3340 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3341 rt2800_config_wcid(rt2x00dev, NULL, i);
3342 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3343 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3344 }
3345
3346 /*
3347 * Clear all beacons
fcf51541 3348 */
69cf36a4
HS		 3349 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3350 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3351 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3352 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3353 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3354 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3355 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3356 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3357
cea90e55 3358 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3359 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3360 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3361 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3362 } else if (rt2x00_is_pcie(rt2x00dev)) {
3363 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3364 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3365 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3366 }
3367
3368 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3369 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3370 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3371 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3372 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3373 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3374 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3375 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3376 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3377 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3378
3379 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3380 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3381 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3382 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3383 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3384 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3385 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3386 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3387 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3388 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3389
3390 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3391 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3392 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3393 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3394 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3395 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3396 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3397 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3398 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3399 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3400
3401 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3402 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3403 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3404 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3405 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3406 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3407
47ee3eb1
HS		 3408 /*
3409 * Do not force the BA window size, we use the TXWI to set it
3410 */
3411 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3412 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3413 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3414 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3415
fcf51541
BZ		 3416 /*
3417 * We must clear the error counters.
3418 * These registers are cleared on read,
3419 * so we may pass a useless variable to store the value.
3420 */
3421 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3422 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3423 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3424 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3425 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3426 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3427
9f926fb5
HS		 3428 /*
3429 * Setup leadtime for pre tbtt interrupt to 6ms
3430 */
3431 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3432 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3433 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3434
977206d7
HS		 3435 /*
3436 * Set up channel statistics timer
3437 */
3438 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3439 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3440 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3441 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3442 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3443 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3444 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3445
fcf51541
BZ		 3446 return 0;
3447}
fcf51541
BZ		 3448
3449static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3450{
3451 unsigned int i;
3452 u32 reg;
3453
3454 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3455 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3456 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3457 return 0;
3458
3459 udelay(REGISTER_BUSY_DELAY);
3460 }
3461
3462 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3463 return -EACCES;
3464}
3465
3466static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3467{
3468 unsigned int i;
3469 u8 value;
3470
3471 /*
3472 * BBP was enabled after firmware was loaded,
3473 * but we need to reactivate it now.
3474 */
3475 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3476 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3477 msleep(1);
3478
3479 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3480 rt2800_bbp_read(rt2x00dev, 0, &value);
3481 if ((value != 0xff) && (value != 0x00))
3482 return 0;
3483 udelay(REGISTER_BUSY_DELAY);
3484 }
3485
3486 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3487 return -EACCES;
3488}
3489
b9a07ae9 3490static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3491{
3492 unsigned int i;
3493 u16 eeprom;
3494 u8 reg_id;
3495 u8 value;
3496
3497 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3498 rt2800_wait_bbp_ready(rt2x00dev)))
3499 return -EACCES;
3500
03839951
DG		 3501 if (rt2x00_rt(rt2x00dev, RT3352)) {
3502 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3503 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3504 }
3505
a89534ed
WH		 3506 if (rt2x00_rt(rt2x00dev, RT3290) ||
3507 rt2x00_rt(rt2x00dev, RT5390) ||
3508 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3509 rt2800_bbp_read(rt2x00dev, 4, &value);
3510 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3511 rt2800_bbp_write(rt2x00dev, 4, value);
3512 }
60687ba7 3513
adde5882 3514 if (rt2800_is_305x_soc(rt2x00dev) ||
a89534ed 3515 rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3516 rt2x00_rt(rt2x00dev, RT3352) ||
872834df 3517 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3518 rt2x00_rt(rt2x00dev, RT5390) ||
3519 rt2x00_rt(rt2x00dev, RT5392))
baff8006
HS		 3520 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3521
03839951
DG		 3522 if (rt2x00_rt(rt2x00dev, RT3352))
3523 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3524
fcf51541
BZ		 3525 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3526 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3527
a89534ed 3528 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3529 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3530 rt2x00_rt(rt2x00dev, RT5390) ||
3531 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3532 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3533
a9dce149
GW		 3534 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3535 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3536 rt2800_bbp_write(rt2x00dev, 73, 0x12);
a89534ed 3537 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3538 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3539 rt2x00_rt(rt2x00dev, RT5390) ||
3540 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3541 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3542 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3543 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3544 rt2800_bbp_write(rt2x00dev, 76, 0x28);
a89534ed
WH		 3545
3546 if (rt2x00_rt(rt2x00dev, RT3290))
3547 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3548 else
3549 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3550 } else {
3551 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3552 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3553 }
3554
fcf51541 3555 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3556
d5385bfc 3557 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3558 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3559 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3560 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3561 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3562 rt2x00_rt(rt2x00dev, RT5390) ||
3563 rt2x00_rt(rt2x00dev, RT5392)) {
8cdd15e0
GW		 3564 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3565 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3566 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3567 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3568 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3569 rt2800_bbp_write(rt2x00dev, 80, 0x08);
59d12874
GW		 3570 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3571 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3572 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3573 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3574 rt2800_bbp_write(rt2x00dev, 81, 0x33);
03839951
DG		 3575 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3576 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3577 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3578 rt2800_bbp_write(rt2x00dev, 81, 0x37);
8cdd15e0
GW		 3579 } else {
3580 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3581 }
3582
fcf51541 3583 rt2800_bbp_write(rt2x00dev, 82, 0x62);
a89534ed
WH		 3584 if (rt2x00_rt(rt2x00dev, RT3290) ||
3585 rt2x00_rt(rt2x00dev, RT5390) ||
3586 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3587 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3588 else
3589 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3590
5ed8f458 3591 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3592 rt2800_bbp_write(rt2x00dev, 84, 0x19);
a89534ed 3593 else if (rt2x00_rt(rt2x00dev, RT3290) ||
e6d227b9
GJ		 3594 rt2x00_rt(rt2x00dev, RT5390) ||
3595 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3596 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3597 else
3598 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3599
a89534ed 3600 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3601 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3602 rt2x00_rt(rt2x00dev, RT5390) ||
3603 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3604 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3605 else
3606 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3607
03839951
DG		 3608 if (rt2x00_rt(rt2x00dev, RT3352) ||
3609 rt2x00_rt(rt2x00dev, RT5392))
2ed71884
JL		 3610 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3611
fcf51541 3612 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3613
a89534ed 3614 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3615 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3616 rt2x00_rt(rt2x00dev, RT5390) ||
3617 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3618 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3619 else
3620 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3621
2ed71884
JL		 3622 if (rt2x00_rt(rt2x00dev, RT5392)) {
3623 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3624 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3625 }
3626
d5385bfc 3627 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3628 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3629 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3630 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
a89534ed 3631 rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3632 rt2x00_rt(rt2x00dev, RT3352) ||
872834df 3633 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3634 rt2x00_rt(rt2x00dev, RT5390) ||
2ed71884 3635 rt2x00_rt(rt2x00dev, RT5392) ||
baff8006 3636 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3637 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3638 else
3639 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3640
a89534ed 3641 if (rt2x00_rt(rt2x00dev, RT3290) ||
03839951 3642 rt2x00_rt(rt2x00dev, RT3352) ||
a89534ed
WH		 3643 rt2x00_rt(rt2x00dev, RT5390) ||
3644 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3645 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3646
baff8006
HS		 3647 if (rt2800_is_305x_soc(rt2x00dev))
3648 rt2800_bbp_write(rt2x00dev, 105, 0x01);
a89534ed
WH		 3649 else if (rt2x00_rt(rt2x00dev, RT3290))
3650 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
03839951
DG		 3651 else if (rt2x00_rt(rt2x00dev, RT3352))
3652 rt2800_bbp_write(rt2x00dev, 105, 0x34);
2ed71884 3653 else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 3654 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3655 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3656 else
3657 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3658
a89534ed
WH		 3659 if (rt2x00_rt(rt2x00dev, RT3290) ||
3660 rt2x00_rt(rt2x00dev, RT5390))
adde5882 3661 rt2800_bbp_write(rt2x00dev, 106, 0x03);
03839951
DG		 3662 else if (rt2x00_rt(rt2x00dev, RT3352))
3663 rt2800_bbp_write(rt2x00dev, 106, 0x05);
2ed71884
JL		 3664 else if (rt2x00_rt(rt2x00dev, RT5392))
3665 rt2800_bbp_write(rt2x00dev, 106, 0x12);
adde5882
GJ		 3666 else
3667 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3668
03839951
DG		 3669 if (rt2x00_rt(rt2x00dev, RT3352))
3670 rt2800_bbp_write(rt2x00dev, 120, 0x50);
3671
a89534ed
WH		 3672 if (rt2x00_rt(rt2x00dev, RT3290) ||
3673 rt2x00_rt(rt2x00dev, RT5390) ||
3674 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3675 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3676
2ed71884
JL		 3677 if (rt2x00_rt(rt2x00dev, RT5392)) {
3678 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3679 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3680 }
3681
03839951
DG		 3682 if (rt2x00_rt(rt2x00dev, RT3352))
3683 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
3684
64522957 3685 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3686 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3687 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3688 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3689 rt2x00_rt(rt2x00dev, RT5390) ||
3690 rt2x00_rt(rt2x00dev, RT5392)) {
d5385bfc 3691 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3692
38c8a566
RJH		 3693 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3694 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3695 value |= 0x20;
38c8a566 3696 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3697 value &= ~0x02;
fcf51541 3698
d5385bfc 3699 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3700 }
3701
a89534ed
WH		 3702 if (rt2x00_rt(rt2x00dev, RT3290)) {
3703 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3704 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3705 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3706 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3707 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3708 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3709 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3710 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3711 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3712 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3713
3714 rt2800_bbp_read(rt2x00dev, 47, &value);
3715 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3716 rt2800_bbp_write(rt2x00dev, 47, value);
3717
3718 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3719 rt2800_bbp_read(rt2x00dev, 3, &value);
3720 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3721 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3722 rt2800_bbp_write(rt2x00dev, 3, value);
3723 }
3724
03839951
DG		 3725 if (rt2x00_rt(rt2x00dev, RT3352)) {
3726 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
3727 /* Set ITxBF timeout to 0x9c40=1000msec */
3728 rt2800_bbp_write(rt2x00dev, 179, 0x02);
3729 rt2800_bbp_write(rt2x00dev, 180, 0x00);
3730 rt2800_bbp_write(rt2x00dev, 182, 0x40);
3731 rt2800_bbp_write(rt2x00dev, 180, 0x01);
3732 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
3733 rt2800_bbp_write(rt2x00dev, 179, 0x00);
3734 /* Reprogram the inband interface to put right values in RXWI */
3735 rt2800_bbp_write(rt2x00dev, 142, 0x04);
3736 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
3737 rt2800_bbp_write(rt2x00dev, 142, 0x06);
3738 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
3739 rt2800_bbp_write(rt2x00dev, 142, 0x07);
3740 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
3741 rt2800_bbp_write(rt2x00dev, 142, 0x08);
3742 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
3743
3744 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
3745 }
3746
2ed71884 3747 if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 3748 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3749 int ant, div_mode;
3750
3751 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3752 div_mode = rt2x00_get_field16(eeprom,
3753 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3754 ant = (div_mode == 3) ? 1 : 0;
3755
3756 /* check if this is a Bluetooth combo card */
fdbc7b0a 3757 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3758 u32 reg;
3759
99bdf51a
GW		 3760 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3761 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
3762 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
3763 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
3764 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
adde5882 3765 if (ant == 0)
99bdf51a 3766 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
adde5882 3767 else if (ant == 1)
99bdf51a
GW		 3768 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
3769 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
adde5882
GJ		 3770 }
3771
0586a11b
AA		 3772 /* This chip has hardware antenna diversity*/
3773 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3774 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3775 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3776 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3777 }
3778
adde5882
GJ		 3779 rt2800_bbp_read(rt2x00dev, 152, &value);
3780 if (ant == 0)
3781 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3782 else
3783 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3784 rt2800_bbp_write(rt2x00dev, 152, value);
3785
3786 /* Init frequency calibration */
3787 rt2800_bbp_write(rt2x00dev, 142, 1);
3788 rt2800_bbp_write(rt2x00dev, 143, 57);
3789 }
fcf51541
BZ		 3790
3791 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3792 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3793
3794 if (eeprom != 0xffff && eeprom != 0x0000) {
3795 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3796 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3797 rt2800_bbp_write(rt2x00dev, reg_id, value);
3798 }
3799 }
3800
3801 return 0;
3802}
fcf51541
BZ		 3803
3804static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3805 bool bw40, u8 rfcsr24, u8 filter_target)
3806{
3807 unsigned int i;
3808 u8 bbp;
3809 u8 rfcsr;
3810 u8 passband;
3811 u8 stopband;
3812 u8 overtuned = 0;
3813
3814 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3815
3816 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3817 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3818 rt2800_bbp_write(rt2x00dev, 4, bbp);
3819
80d184e6
RJH		 3820 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3821 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3822 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3823
fcf51541
BZ		 3824 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3825 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3826 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3827
3828 /*
3829 * Set power & frequency of passband test tone
3830 */
3831 rt2800_bbp_write(rt2x00dev, 24, 0);
3832
3833 for (i = 0; i < 100; i++) {
3834 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3835 msleep(1);
3836
3837 rt2800_bbp_read(rt2x00dev, 55, &passband);
3838 if (passband)
3839 break;
3840 }
3841
3842 /*
3843 * Set power & frequency of stopband test tone
3844 */
3845 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3846
3847 for (i = 0; i < 100; i++) {
3848 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3849 msleep(1);
3850
3851 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3852
3853 if ((passband - stopband) <= filter_target) {
3854 rfcsr24++;
3855 overtuned += ((passband - stopband) == filter_target);
3856 } else
3857 break;
3858
3859 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3860 }
3861
3862 rfcsr24 -= !!overtuned;
3863
3864 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3865 return rfcsr24;
3866}
3867
d5374ef1
SG		 3868static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
3869{
3870 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3871 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3872 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3873 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3874 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3875 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3876 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3877 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3878 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3879 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3880 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3881 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3882 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3883 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3884 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3885 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3886 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3887 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3888 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3889 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3890 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3891 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3892 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3893 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3894 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3895 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3896 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3897 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3898 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3899 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3900 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3901 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3902}
3903
3904static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
3905{
3906 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3907 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3908 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3909 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3910 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3911 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3912 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3913 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3914 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3915 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3916 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3917 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3918 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3919 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3920 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3921 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3922 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3923 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3924 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3925}
3926
3927static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
3928{
3929 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3930 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3931 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3932 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3933 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3934 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3935 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3936 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3937 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3938 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3939 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3940 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3941 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3942 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3943 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3944 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3945 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3946 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3947 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3948 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3949 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3950 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3951 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3952 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3953 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3954 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3955 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3956 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3957 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3958 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3959 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3960 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3961 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3962 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3963 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3964 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3965 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3966 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3967 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3968 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3969 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3970 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3971 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3972 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3973 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3974 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3975}
3976
3977static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
3978{
3979 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
3980 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
3981 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
3982 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
3983 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3984 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
3985 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
3986 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3987 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
3988 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3989 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
3990 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3991 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3992 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3993 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
3994 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3995 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
3996 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
3997 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3998 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3999 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4000 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4001 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4002 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4003 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4004 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4005 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4006 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4007 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4008 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4009 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4010 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4011 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4012 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4013 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4014 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4015 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4016 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4017 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4018 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4019 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4020 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4021 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4022 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4023 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4024 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4025 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4026 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4027 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4028 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4029 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4030 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4031 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4032 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4033 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4034 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4035 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4036 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4037 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4038 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4039 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4040 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4041 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4042}
4043
4044static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4045{
4046 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4047 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4048 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4049 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4050 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4051 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4052 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4053 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4054 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4055 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4056 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4057 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4058 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4059 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4060 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4061 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4062 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4063 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4064 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4065 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4066 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4067 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4068 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4069 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4070 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4071 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4072 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4073 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4074 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4075 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4076 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4077 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4078}
4079
4080static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4081{
4082 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4083 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4084 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4085 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4086 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4087 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4088 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4089 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4090 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4091 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4092 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4093 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4094 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4095 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4096 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4097 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4098 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4099 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4100 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4101 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4102 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4103 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4104 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4105 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4106 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4107 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4108 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4109 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4110 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4111 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4112 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4113}
4114
4115static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4116{
4117 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4118 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4119 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4120 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4121 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4122 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4123 else
4124 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4125 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4126 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4127 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4128 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4129 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4130 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4131 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4132 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4133 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4134 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4135
4136 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4137 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4138 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4139 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4140 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4141 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4142 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4143 else
4144 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4145 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4146 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4147 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4148 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4149
4150 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4151 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4152 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4153 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4154 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4155 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4156 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4157 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4158 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4159 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4160
4161 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4162 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4163 else
4164 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4165 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4166 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4167 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4168 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4169 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4170 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4171 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4172 else
4173 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4174 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4175 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4176 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4177
4178 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4179 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4180 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4181 else
4182 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4183 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4184 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4185 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4186 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4187 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4188 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4189
4190 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4191 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4192 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4193 else
4194 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4195 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4196 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4197}
4198
4199static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4200{
4201 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4202 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4203 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4204 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4205 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4206 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4207 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4208 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4209 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4210 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4211 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4212 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4213 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4214 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4215 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4216 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4217 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4218 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4219 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4220 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4221 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4222 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4223 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4224 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4225 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4226 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4227 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4228 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4229 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4230 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4231 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4232 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4233 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4234 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4235 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4236 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4237 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4238 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4239 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4240 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4241 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4242 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4243 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4244 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4245 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4246 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4247 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4248 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4249 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4250 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4251 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4252 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4253 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4254 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4255 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4256 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4257 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4258 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4259 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4260}
4261
b9a07ae9 4262static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 4263{
3a1c0128 4264 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541
BZ		 4265 u8 rfcsr;
4266 u8 bbp;
8cdd15e0
GW		 4267 u32 reg;
4268 u16 eeprom;
fcf51541 4269
d5385bfc 4270 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 4271 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 4272 !rt2x00_rt(rt2x00dev, RT3090) &&
a89534ed 4273 !rt2x00_rt(rt2x00dev, RT3290) &&
03839951 4274 !rt2x00_rt(rt2x00dev, RT3352) &&
23812383 4275 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 4276 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 4277 !rt2x00_rt(rt2x00dev, RT5390) &&
2ed71884 4278 !rt2x00_rt(rt2x00dev, RT5392) &&
baff8006 4279 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 4280 return 0;
4281
fcf51541
BZ		 4282 /*
4283 * Init RF calibration.
4284 */
d5374ef1 4285
a89534ed
WH		 4286 if (rt2x00_rt(rt2x00dev, RT3290) ||
4287 rt2x00_rt(rt2x00dev, RT5390) ||
4288 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4289 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4290 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4291 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4292 msleep(1);
4293 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4294 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4295 } else {
4296 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4297 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4298 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4299 msleep(1);
4300 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4301 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4302 }
fcf51541 4303
d5374ef1
SG		 4304 if (rt2800_is_305x_soc(rt2x00dev)) {
4305 rt2800_init_rfcsr_305x_soc(rt2x00dev);
baff8006 4306 return 0;
d5374ef1
SG		 4307 }
4308
4309 switch (rt2x00dev->chip.rt) {
4310 case RT3070:
4311 case RT3071:
4312 case RT3090:
4313 rt2800_init_rfcsr_30xx(rt2x00dev);
4314 break;
4315 case RT3290:
4316 rt2800_init_rfcsr_3290(rt2x00dev);
4317 break;
4318 case RT3352:
4319 rt2800_init_rfcsr_3352(rt2x00dev);
4320 break;
4321 case RT3390:
4322 rt2800_init_rfcsr_3390(rt2x00dev);
4323 break;
4324 case RT3572:
4325 rt2800_init_rfcsr_3572(rt2x00dev);
4326 break;
4327 case RT5390:
4328 rt2800_init_rfcsr_5390(rt2x00dev);
4329 break;
4330 case RT5392:
4331 rt2800_init_rfcsr_5392(rt2x00dev);
4332 break;
8cdd15e0
GW		 4333 }
4334
4335 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4336 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4337 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4338 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4339 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 4340 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4341 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 4342 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4343
d5385bfc
GW		 4344 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4345 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4346 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4347
d5385bfc
GW		 4348 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4349 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 4350 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4351 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 4352 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4353 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4354 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4355 else
4356 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4357 }
4358 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 4359
4360 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4361 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4362 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 4363 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4364 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4365 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4366 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 4367 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4368 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4369 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4370 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4371
4372 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4373 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4374 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4375 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4376 msleep(1);
4377 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
d0f21fe6 4378 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
872834df
GW		 4379 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4380 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 4381 }
4382
4383 /*
4384 * Set RX Filter calibration for 20MHz and 40MHz
4385 */
8cdd15e0 4386 if (rt2x00_rt(rt2x00dev, RT3070)) {
3a1c0128 4387 drv_data->calibration_bw20 =
8cdd15e0 4388 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3a1c0128 4389 drv_data->calibration_bw40 =
8cdd15e0 4390 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 4391 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4392 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 4393 rt2x00_rt(rt2x00dev, RT3352) ||
872834df
GW		 4394 rt2x00_rt(rt2x00dev, RT3390) ||
4395 rt2x00_rt(rt2x00dev, RT3572)) {
3a1c0128 4396 drv_data->calibration_bw20 =
d5385bfc 4397 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3a1c0128 4398 drv_data->calibration_bw40 =
d5385bfc 4399 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 4400 }
fcf51541 4401
5d137dff
GW		 4402 /*
4403 * Save BBP 25 & 26 values for later use in channel switching
4404 */
4405 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4406 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4407
2ed71884 4408 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 4409 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4410 /*
4411 * Set back to initial state
4412 */
4413 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 4414
adde5882
GJ		 4415 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4416 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4417 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 4418
adde5882
GJ		 4419 /*
4420 * Set BBP back to BW20
4421 */
4422 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4423 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4424 rt2800_bbp_write(rt2x00dev, 4, bbp);
4425 }
fcf51541 4426
d5385bfc 4427 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 4428 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4429 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4430 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 4431 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4432
4433 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4434 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4435 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4436
2ed71884 4437 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 4438 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4439 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4440 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4441 if (rt2x00_rt(rt2x00dev, RT3070) ||
4442 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4443 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4444 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 4445 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4446 &rt2x00dev->cap_flags))
adde5882
GJ		 4447 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4448 }
77c06c2c
GW		 4449 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4450 drv_data->txmixer_gain_24g);
adde5882
GJ		 4451 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4452 }
8cdd15e0 4453
64522957
GW		 4454 if (rt2x00_rt(rt2x00dev, RT3090)) {
4455 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4456
80d184e6 4457 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 4458 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4459 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 4460 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 4461 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 4462 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4463
4464 rt2800_bbp_write(rt2x00dev, 138, bbp);
4465 }
4466
4467 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 4468 rt2x00_rt(rt2x00dev, RT3090) ||
4469 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 4470 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4471 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4472 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4473 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4474 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4475 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4476 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4477
4478 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4479 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4480 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4481
4482 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4483 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4484 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4485
4486 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4487 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4488 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4489 }
4490
80d184e6 4491 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 4492 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 4493 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 4494 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4495 else
4496 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4497 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4498 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4499 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4500 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4501 }
4502
a89534ed
WH		 4503 if (rt2x00_rt(rt2x00dev, RT3290)) {
4504 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4505 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4506 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4507 }
4508
2ed71884 4509 if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 4510 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 4511 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4512 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4513 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 4514
adde5882
GJ		 4515 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4516 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4517 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 4518
adde5882
GJ		 4519 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4520 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4521 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4522 }
60687ba7 4523
fcf51541
BZ		 4524 return 0;
4525}
b9a07ae9
ID		 4526
4527int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4528{
4529 u32 reg;
4530 u16 word;
4531
4532 /*
4533 * Initialize all registers.
4534 */
4535 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4536 rt2800_init_registers(rt2x00dev) ||
4537 rt2800_init_bbp(rt2x00dev) ||
4538 rt2800_init_rfcsr(rt2x00dev)))
4539 return -EIO;
4540
4541 /*
4542 * Send signal to firmware during boot time.
4543 */
4544 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4545
4546 if (rt2x00_is_usb(rt2x00dev) &&
4547 (rt2x00_rt(rt2x00dev, RT3070) ||
4548 rt2x00_rt(rt2x00dev, RT3071) ||
4549 rt2x00_rt(rt2x00dev, RT3572))) {
4550 udelay(200);
4551 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4552 udelay(10);
4553 }
4554
4555 /*
4556 * Enable RX.
4557 */
4558 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4559 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4560 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4561 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4562
4563 udelay(50);
4564
4565 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4566 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4567 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4568 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4569 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4570 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4571
4572 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4573 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4574 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4575 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4576
4577 /*
4578 * Initialize LED control
4579 */
38c8a566
RJH		 4580 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4581 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 4582 word & 0xff, (word >> 8) & 0xff);
4583
38c8a566
RJH		 4584 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4585 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 4586 word & 0xff, (word >> 8) & 0xff);
4587
38c8a566
RJH		 4588 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4589 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 4590 word & 0xff, (word >> 8) & 0xff);
4591
4592 return 0;
4593}
4594EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4595
4596void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4597{
4598 u32 reg;
4599
f7b395e9 4600 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 4601
4602 /* Wait for DMA, ignore error */
4603 rt2800_wait_wpdma_ready(rt2x00dev);
4604
4605 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4606 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4607 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4608 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 4609}
4610EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 4611
30e84034
BZ		 4612int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4613{
4614 u32 reg;
a89534ed 4615 u16 efuse_ctrl_reg;
30e84034 4616
a89534ed
WH		 4617 if (rt2x00_rt(rt2x00dev, RT3290))
4618 efuse_ctrl_reg = EFUSE_CTRL_3290;
4619 else
4620 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 4621
a89534ed 4622 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 4623 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4624}
4625EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4626
4627static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4628{
4629 u32 reg;
a89534ed
WH		 4630 u16 efuse_ctrl_reg;
4631 u16 efuse_data0_reg;
4632 u16 efuse_data1_reg;
4633 u16 efuse_data2_reg;
4634 u16 efuse_data3_reg;
4635
4636 if (rt2x00_rt(rt2x00dev, RT3290)) {
4637 efuse_ctrl_reg = EFUSE_CTRL_3290;
4638 efuse_data0_reg = EFUSE_DATA0_3290;
4639 efuse_data1_reg = EFUSE_DATA1_3290;
4640 efuse_data2_reg = EFUSE_DATA2_3290;
4641 efuse_data3_reg = EFUSE_DATA3_3290;
4642 } else {
4643 efuse_ctrl_reg = EFUSE_CTRL;
4644 efuse_data0_reg = EFUSE_DATA0;
4645 efuse_data1_reg = EFUSE_DATA1;
4646 efuse_data2_reg = EFUSE_DATA2;
4647 efuse_data3_reg = EFUSE_DATA3;
4648 }
31a4cf1f
GW		 4649 mutex_lock(&rt2x00dev->csr_mutex);
4650
a89534ed 4651 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 4652 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4653 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4654 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 4655 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 4656
4657 /* Wait until the EEPROM has been loaded */
a89534ed 4658 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 4659 /* Apparently the data is read from end to start */
a89534ed 4660 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 4661 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 4662 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 4663 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 4664 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 4665 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 4666 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 4667 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 4668 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 4669
4670 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 4671}
4672
a02308e9 4673int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 4674{
4675 unsigned int i;
4676
4677 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4678 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 4679
4680 return 0;
30e84034
BZ		 4681}
4682EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4683
ad417a53 4684static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 4685{
77c06c2c 4686 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 4687 u16 word;
4688 u8 *mac;
4689 u8 default_lna_gain;
a02308e9 4690 int retval;
38bd7b8a 4691
ad417a53
GW		 4692 /*
4693 * Read the EEPROM.
4694 */
a02308e9
GJ		 4695 retval = rt2800_read_eeprom(rt2x00dev);
4696 if (retval)
4697 return retval;
ad417a53 4698
38bd7b8a
BZ		 4699 /*
4700 * Start validation of the data that has been read.
4701 */
4702 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4703 if (!is_valid_ether_addr(mac)) {
f4f7f414 4704 eth_random_addr(mac);
38bd7b8a
BZ		 4705 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4706 }
4707
38c8a566 4708 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 4709 if (word == 0xffff) {
38c8a566
RJH		 4710 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4711 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4712 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4713 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 4714 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 4715 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 4716 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 4717 /*
4718 * There is a max of 2 RX streams for RT28x0 series
4719 */
38c8a566
RJH		 4720 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4721 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4722 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 4723 }
4724
38c8a566 4725 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 4726 if (word == 0xffff) {
38c8a566
RJH		 4727 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4728 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4729 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4730 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4731 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4732 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4733 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4734 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4735 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4736 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4737 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4738 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4739 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4740 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4741 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4742 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 4743 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4744 }
4745
4746 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4747 if ((word & 0x00ff) == 0x00ff) {
4748 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 4749 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4750 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4751 }
4752 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 4753 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4754 LED_MODE_TXRX_ACTIVITY);
4755 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4756 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 4757 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4758 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4759 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 4760 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 4761 }
4762
4763 /*
4764 * During the LNA validation we are going to use
4765 * lna0 as correct value. Note that EEPROM_LNA
4766 * is never validated.
4767 */
4768 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4769 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4770
4771 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4772 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4773 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4774 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4775 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4776 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4777
77c06c2c
GW		 4778 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4779 if ((word & 0x00ff) != 0x00ff) {
4780 drv_data->txmixer_gain_24g =
4781 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4782 } else {
4783 drv_data->txmixer_gain_24g = 0;
4784 }
4785
38bd7b8a
BZ		 4786 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4787 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4788 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4789 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4790 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4791 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4792 default_lna_gain);
4793 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4794
77c06c2c
GW		 4795 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4796 if ((word & 0x00ff) != 0x00ff) {
4797 drv_data->txmixer_gain_5g =
4798 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4799 } else {
4800 drv_data->txmixer_gain_5g = 0;
4801 }
4802
38bd7b8a
BZ		 4803 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4804 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4805 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4806 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4807 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4808 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4809
4810 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4811 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4812 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4813 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4814 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4815 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4816 default_lna_gain);
4817 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4818
4819 return 0;
4820}
38bd7b8a 4821
ad417a53 4822static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a
BZ		 4823{
4824 u32 reg;
4825 u16 value;
4826 u16 eeprom;
4827
4828 /*
4829 * Read EEPROM word for configuration.
4830 */
38c8a566 4831 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 4832
4833 /*
adde5882
GJ		 4834 * Identify RF chipset by EEPROM value
4835 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4836 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 4837 */
a89534ed
WH		 4838 if (rt2x00_rt(rt2x00dev, RT3290))
4839 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4840 else
4841 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4842
4843 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4844 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4845 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
adde5882
GJ		 4846 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4847 else
4848 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 4849
49e721ec
GW		 4850 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4851 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4852
5aa57015
GW		 4853 switch (rt2x00dev->chip.rt) {
4854 case RT2860:
4855 case RT2872:
4856 case RT2883:
4857 case RT3070:
4858 case RT3071:
4859 case RT3090:
a89534ed 4860 case RT3290:
03839951 4861 case RT3352:
5aa57015
GW		 4862 case RT3390:
4863 case RT3572:
4864 case RT5390:
2ed71884 4865 case RT5392:
5aa57015
GW		 4866 break;
4867 default:
b6df7f1d 4868 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
49e721ec 4869 return -ENODEV;
f273fe55 4870 }
714fa663 4871
d331eb51
LF		 4872 switch (rt2x00dev->chip.rf) {
4873 case RF2820:
4874 case RF2850:
4875 case RF2720:
4876 case RF2750:
4877 case RF3020:
4878 case RF2020:
4879 case RF3021:
4880 case RF3022:
4881 case RF3052:
a89534ed 4882 case RF3290:
d331eb51 4883 case RF3320:
03839951 4884 case RF3322:
ccf91bd6 4885 case RF5360:
d331eb51 4886 case RF5370:
2ed71884 4887 case RF5372:
d331eb51 4888 case RF5390:
cff3d1f0 4889 case RF5392:
d331eb51
LF		 4890 break;
4891 default:
b6df7f1d 4892 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
d331eb51 4893 rt2x00dev->chip.rf);
38bd7b8a
BZ		 4894 return -ENODEV;
4895 }
4896
4897 /*
4898 * Identify default antenna configuration.
4899 */
d96aa640 4900 rt2x00dev->default_ant.tx_chain_num =
38c8a566 4901 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 4902 rt2x00dev->default_ant.rx_chain_num =
38c8a566 4903 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 4904
d96aa640
RJH		 4905 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4906
4907 if (rt2x00_rt(rt2x00dev, RT3070) ||
4908 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 4909 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 4910 rt2x00_rt(rt2x00dev, RT3390)) {
4911 value = rt2x00_get_field16(eeprom,
4912 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4913 switch (value) {
4914 case 0:
4915 case 1:
4916 case 2:
4917 rt2x00dev->default_ant.tx = ANTENNA_A;
4918 rt2x00dev->default_ant.rx = ANTENNA_A;
4919 break;
4920 case 3:
4921 rt2x00dev->default_ant.tx = ANTENNA_A;
4922 rt2x00dev->default_ant.rx = ANTENNA_B;
4923 break;
4924 }
4925 } else {
4926 rt2x00dev->default_ant.tx = ANTENNA_A;
4927 rt2x00dev->default_ant.rx = ANTENNA_A;
4928 }
4929
0586a11b
AA		 4930 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4931 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4932 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4933 }
4934
38bd7b8a 4935 /*
9328fdac 4936 * Determine external LNA informations.
38bd7b8a 4937 */
38c8a566 4938 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4939 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4940 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4941 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4942
4943 /*
4944 * Detect if this device has an hardware controlled radio.
4945 */
38c8a566 4946 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4947 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4948
fdbc7b0a
GW		 4949 /*
4950 * Detect if this device has Bluetooth co-existence.
4951 */
4952 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4953 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4954
9328fdac
GW		 4955 /*
4956 * Read frequency offset and RF programming sequence.
4957 */
4958 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4959 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4960
38bd7b8a
BZ		 4961 /*
4962 * Store led settings, for correct led behaviour.
4963 */
4964#ifdef CONFIG_RT2X00_LIB_LEDS
4965 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4966 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4967 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4968
9328fdac 4969 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4970#endif /* CONFIG_RT2X00_LIB_LEDS */
4971
e90c54b2
RJH		 4972 /*
4973 * Check if support EIRP tx power limit feature.
4974 */
4975 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4976
4977 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4978 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4979 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4980
38bd7b8a
BZ		 4981 return 0;
4982}
38bd7b8a 4983
4da2933f 4984/*
55f9321a 4985 * RF value list for rt28xx
4da2933f
BZ		 4986 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4987 */
4988static const struct rf_channel rf_vals[] = {
4989 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4990 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4991 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4992 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4993 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4994 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4995 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4996 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4997 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4998 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4999 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5000 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5001 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5002 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5003
5004 /* 802.11 UNI / HyperLan 2 */
5005 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5006 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5007 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5008 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5009 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5010 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5011 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5012 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5013 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5014 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5015 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5016 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5017
5018 /* 802.11 HyperLan 2 */
5019 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5020 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5021 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5022 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5023 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5024 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5025 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5026 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5027 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5028 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5029 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5030 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5031 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5032 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5033 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5034 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5035
5036 /* 802.11 UNII */
5037 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5038 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5039 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5040 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5041 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5042 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5043 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5044 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5045 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5046 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5047 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5048
5049 /* 802.11 Japan */
5050 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5051 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5052 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5053 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5054 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5055 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5056 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5057};
5058
5059/*
55f9321a
ID		 5060 * RF value list for rt3xxx
5061 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 5062 */
55f9321a 5063static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 5064 {1, 241, 2, 2 },
5065 {2, 241, 2, 7 },
5066 {3, 242, 2, 2 },
5067 {4, 242, 2, 7 },
5068 {5, 243, 2, 2 },
5069 {6, 243, 2, 7 },
5070 {7, 244, 2, 2 },
5071 {8, 244, 2, 7 },
5072 {9, 245, 2, 2 },
5073 {10, 245, 2, 7 },
5074 {11, 246, 2, 2 },
5075 {12, 246, 2, 7 },
5076 {13, 247, 2, 2 },
5077 {14, 248, 2, 4 },
55f9321a
ID		 5078
5079 /* 802.11 UNI / HyperLan 2 */
5080 {36, 0x56, 0, 4},
5081 {38, 0x56, 0, 6},
5082 {40, 0x56, 0, 8},
5083 {44, 0x57, 0, 0},
5084 {46, 0x57, 0, 2},
5085 {48, 0x57, 0, 4},
5086 {52, 0x57, 0, 8},
5087 {54, 0x57, 0, 10},
5088 {56, 0x58, 0, 0},
5089 {60, 0x58, 0, 4},
5090 {62, 0x58, 0, 6},
5091 {64, 0x58, 0, 8},
5092
5093 /* 802.11 HyperLan 2 */
5094 {100, 0x5b, 0, 8},
5095 {102, 0x5b, 0, 10},
5096 {104, 0x5c, 0, 0},
5097 {108, 0x5c, 0, 4},
5098 {110, 0x5c, 0, 6},
5099 {112, 0x5c, 0, 8},
5100 {116, 0x5d, 0, 0},
5101 {118, 0x5d, 0, 2},
5102 {120, 0x5d, 0, 4},
5103 {124, 0x5d, 0, 8},
5104 {126, 0x5d, 0, 10},
5105 {128, 0x5e, 0, 0},
5106 {132, 0x5e, 0, 4},
5107 {134, 0x5e, 0, 6},
5108 {136, 0x5e, 0, 8},
5109 {140, 0x5f, 0, 0},
5110
5111 /* 802.11 UNII */
5112 {149, 0x5f, 0, 9},
5113 {151, 0x5f, 0, 11},
5114 {153, 0x60, 0, 1},
5115 {157, 0x60, 0, 5},
5116 {159, 0x60, 0, 7},
5117 {161, 0x60, 0, 9},
5118 {165, 0x61, 0, 1},
5119 {167, 0x61, 0, 3},
5120 {169, 0x61, 0, 5},
5121 {171, 0x61, 0, 7},
5122 {173, 0x61, 0, 9},
4da2933f
BZ		 5123};
5124
ad417a53 5125static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 5126{
4da2933f
BZ		 5127 struct hw_mode_spec *spec = &rt2x00dev->spec;
5128 struct channel_info *info;
8d1331b3
ID		 5129 char *default_power1;
5130 char *default_power2;
4da2933f
BZ		 5131 unsigned int i;
5132 u16 eeprom;
5133
93b6bd26
GW		 5134 /*
5135 * Disable powersaving as default on PCI devices.
5136 */
cea90e55 5137 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 5138 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5139
4da2933f
BZ		 5140 /*
5141 * Initialize all hw fields.
5142 */
5143 rt2x00dev->hw->flags =
4da2933f
BZ		 5144 IEEE80211_HW_SIGNAL_DBM |
5145 IEEE80211_HW_SUPPORTS_PS |
1df90809 5146 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 5147 IEEE80211_HW_AMPDU_AGGREGATION |
84e9e8eb 5148 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
9d4f09b8 5149
5a5b6ed6
HS		 5150 /*
5151 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5152 * unless we are capable of sending the buffered frames out after the
5153 * DTIM transmission using rt2x00lib_beacondone. This will send out
5154 * multicast and broadcast traffic immediately instead of buffering it
5155 * infinitly and thus dropping it after some time.
5156 */
5157 if (!rt2x00_is_usb(rt2x00dev))
5158 rt2x00dev->hw->flags |=
5159 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 5160
4da2933f
BZ		 5161 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5162 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5163 rt2x00_eeprom_addr(rt2x00dev,
5164 EEPROM_MAC_ADDR_0));
5165
3f2bee24
HS		 5166 /*
5167 * As rt2800 has a global fallback table we cannot specify
5168 * more then one tx rate per frame but since the hw will
5169 * try several rates (based on the fallback table) we should
ba3b9e5e 5170 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 5171 * we are going to try. Otherwise mac80211 will truncate our
5172 * reported tx rates and the rc algortihm will end up with
5173 * incorrect data.
5174 */
ba3b9e5e
HS		 5175 rt2x00dev->hw->max_rates = 1;
5176 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 5177 rt2x00dev->hw->max_rate_tries = 1;
5178
38c8a566 5179 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 5180
5181 /*
5182 * Initialize hw_mode information.
5183 */
5184 spec->supported_bands = SUPPORT_BAND_2GHZ;
5185 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5186
5122d898 5187 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 5188 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 5189 spec->num_channels = 14;
5190 spec->channels = rf_vals;
55f9321a
ID		 5191 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5192 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 5193 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5194 spec->num_channels = ARRAY_SIZE(rf_vals);
5195 spec->channels = rf_vals;
5122d898
GW		 5196 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5197 rt2x00_rf(rt2x00dev, RF2020) ||
5198 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 5199 rt2x00_rf(rt2x00dev, RF3022) ||
a89534ed 5200 rt2x00_rf(rt2x00dev, RF3290) ||
adde5882 5201 rt2x00_rf(rt2x00dev, RF3320) ||
03839951 5202 rt2x00_rf(rt2x00dev, RF3322) ||
ccf91bd6 5203 rt2x00_rf(rt2x00dev, RF5360) ||
aca355b9 5204 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 5205 rt2x00_rf(rt2x00dev, RF5372) ||
cff3d1f0
ZL		 5206 rt2x00_rf(rt2x00dev, RF5390) ||
5207 rt2x00_rf(rt2x00dev, RF5392)) {
55f9321a
ID		 5208 spec->num_channels = 14;
5209 spec->channels = rf_vals_3x;
5210 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5211 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5212 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5213 spec->channels = rf_vals_3x;
4da2933f
BZ		 5214 }
5215
53216d6a
SG		 5216 if (WARN_ON_ONCE(!spec->channels))
5217 return -ENODEV;
5218
4da2933f
BZ		 5219 /*
5220 * Initialize HT information.
5221 */
5122d898 5222 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 5223 spec->ht.ht_supported = true;
5224 else
5225 spec->ht.ht_supported = false;
5226
4da2933f 5227 spec->ht.cap =
06443e46 5228 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 5229 IEEE80211_HT_CAP_GRN_FLD |
5230 IEEE80211_HT_CAP_SGI_20 |
aa674631 5231 IEEE80211_HT_CAP_SGI_40;
22cabaa6 5232
38c8a566 5233 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 5234 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5235
aa674631 5236 spec->ht.cap |=
38c8a566 5237 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 5238 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5239
4da2933f
BZ		 5240 spec->ht.ampdu_factor = 3;
5241 spec->ht.ampdu_density = 4;
5242 spec->ht.mcs.tx_params =
5243 IEEE80211_HT_MCS_TX_DEFINED |
5244 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 5245 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 5246 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5247
38c8a566 5248 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 5249 case 3:
5250 spec->ht.mcs.rx_mask[2] = 0xff;
5251 case 2:
5252 spec->ht.mcs.rx_mask[1] = 0xff;
5253 case 1:
5254 spec->ht.mcs.rx_mask[0] = 0xff;
5255 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5256 break;
5257 }
5258
5259 /*
5260 * Create channel information array
5261 */
baeb2ffa 5262 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 5263 if (!info)
5264 return -ENOMEM;
5265
5266 spec->channels_info = info;
5267
8d1331b3
ID		 5268 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5269 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 5270
5271 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 5272 info[i].default_power1 = default_power1[i];
5273 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 5274 }
5275
5276 if (spec->num_channels > 14) {
8d1331b3
ID		 5277 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5278 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 5279
5280 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 5281 info[i].default_power1 = default_power1[i];
5282 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 5283 }
5284 }
5285
2e9c43dd
JL		 5286 switch (rt2x00dev->chip.rf) {
5287 case RF2020:
5288 case RF3020:
5289 case RF3021:
5290 case RF3022:
5291 case RF3320:
5292 case RF3052:
a89534ed 5293 case RF3290:
ccf91bd6 5294 case RF5360:
2e9c43dd
JL		 5295 case RF5370:
5296 case RF5372:
5297 case RF5390:
cff3d1f0 5298 case RF5392:
2e9c43dd
JL		 5299 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5300 break;
5301 }
5302
4da2933f
BZ		 5303 return 0;
5304}
ad417a53
GW		 5305
5306int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5307{
5308 int retval;
5309 u32 reg;
5310
5311 /*
5312 * Allocate eeprom data.
5313 */
5314 retval = rt2800_validate_eeprom(rt2x00dev);
5315 if (retval)
5316 return retval;
5317
5318 retval = rt2800_init_eeprom(rt2x00dev);
5319 if (retval)
5320 return retval;
5321
5322 /*
5323 * Enable rfkill polling by setting GPIO direction of the
5324 * rfkill switch GPIO pin correctly.
5325 */
5326 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5327 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5328 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5329
5330 /*
5331 * Initialize hw specifications.
5332 */
5333 retval = rt2800_probe_hw_mode(rt2x00dev);
5334 if (retval)
5335 return retval;
5336
5337 /*
5338 * Set device capabilities.
5339 */
5340 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5341 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5342 if (!rt2x00_is_usb(rt2x00dev))
5343 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5344
5345 /*
5346 * Set device requirements.
5347 */
5348 if (!rt2x00_is_soc(rt2x00dev))
5349 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5350 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5351 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5352 if (!rt2800_hwcrypt_disabled(rt2x00dev))
5353 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5354 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5355 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5356 if (rt2x00_is_usb(rt2x00dev))
5357 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5358 else {
5359 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5360 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5361 }
5362
5363 /*
5364 * Set the rssi offset.
5365 */
5366 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5367
5368 return 0;
5369}
5370EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 5371
2ce33995
BZ		 5372/*
5373 * IEEE80211 stack callback functions.
5374 */
e783619e
HS		 5375void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5376 u16 *iv16)
2ce33995
BZ		 5377{
5378 struct rt2x00_dev *rt2x00dev = hw->priv;
5379 struct mac_iveiv_entry iveiv_entry;
5380 u32 offset;
5381
5382 offset = MAC_IVEIV_ENTRY(hw_key_idx);
5383 rt2800_register_multiread(rt2x00dev, offset,
5384 &iveiv_entry, sizeof(iveiv_entry));
5385
855da5e0
JL		 5386 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5387 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 5388}
e783619e 5389EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 5390
e783619e 5391int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 5392{
5393 struct rt2x00_dev *rt2x00dev = hw->priv;
5394 u32 reg;
5395 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5396
5397 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5398 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5399 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5400
5401 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5402 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5403 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5404
5405 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5406 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5407 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5408
5409 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5410 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5411 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5412
5413 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5414 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5415 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5416
5417 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5418 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5419 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5420
5421 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5422 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5423 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5424
5425 return 0;
5426}
e783619e 5427EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 5428
8a3a3c85
EP		 5429int rt2800_conf_tx(struct ieee80211_hw *hw,
5430 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 5431 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 5432{
5433 struct rt2x00_dev *rt2x00dev = hw->priv;
5434 struct data_queue *queue;
5435 struct rt2x00_field32 field;
5436 int retval;
5437 u32 reg;
5438 u32 offset;
5439
5440 /*
5441 * First pass the configuration through rt2x00lib, that will
5442 * update the queue settings and validate the input. After that
5443 * we are free to update the registers based on the value
5444 * in the queue parameter.
5445 */
8a3a3c85 5446 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 5447 if (retval)
5448 return retval;
5449
5450 /*
5451 * We only need to perform additional register initialization
5452 * for WMM queues/
5453 */
5454 if (queue_idx >= 4)
5455 return 0;
5456
11f818e0 5457 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 5458
5459 /* Update WMM TXOP register */
5460 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5461 field.bit_offset = (queue_idx & 1) * 16;
5462 field.bit_mask = 0xffff << field.bit_offset;
5463
5464 rt2800_register_read(rt2x00dev, offset, &reg);
5465 rt2x00_set_field32(&reg, field, queue->txop);
5466 rt2800_register_write(rt2x00dev, offset, reg);
5467
5468 /* Update WMM registers */
5469 field.bit_offset = queue_idx * 4;
5470 field.bit_mask = 0xf << field.bit_offset;
5471
5472 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5473 rt2x00_set_field32(&reg, field, queue->aifs);
5474 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5475
5476 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5477 rt2x00_set_field32(&reg, field, queue->cw_min);
5478 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5479
5480 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5481 rt2x00_set_field32(&reg, field, queue->cw_max);
5482 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5483
5484 /* Update EDCA registers */
5485 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5486
5487 rt2800_register_read(rt2x00dev, offset, &reg);
5488 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5489 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5490 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5491 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5492 rt2800_register_write(rt2x00dev, offset, reg);
5493
5494 return 0;
5495}
e783619e 5496EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 5497
37a41b4a 5498u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 5499{
5500 struct rt2x00_dev *rt2x00dev = hw->priv;
5501 u64 tsf;
5502 u32 reg;
5503
5504 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
5505 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5506 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
5507 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5508
5509 return tsf;
5510}
e783619e 5511EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 5512
e783619e
HS		 5513int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5514 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5515 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5516 u8 buf_size)
1df90809 5517{
af35323d 5518 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 5519 int ret = 0;
5520
af35323d
HS		 5521 /*
5522 * Don't allow aggregation for stations the hardware isn't aware
5523 * of because tx status reports for frames to an unknown station
5524 * always contain wcid=255 and thus we can't distinguish between
5525 * multiple stations which leads to unwanted situations when the
5526 * hw reorders frames due to aggregation.
5527 */
5528 if (sta_priv->wcid < 0)
5529 return 1;
5530
1df90809
HS		 5531 switch (action) {
5532 case IEEE80211_AMPDU_RX_START:
5533 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 5534 /*
5535 * The hw itself takes care of setting up BlockAck mechanisms.
5536 * So, we only have to allow mac80211 to nagotiate a BlockAck
5537 * agreement. Once that is done, the hw will BlockAck incoming
5538 * AMPDUs without further setup.
5539 */
1df90809
HS		 5540 break;
5541 case IEEE80211_AMPDU_TX_START:
5542 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5543 break;
18b559d5
JB		 5544 case IEEE80211_AMPDU_TX_STOP_CONT:
5545 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5546 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 5547 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5548 break;
5549 case IEEE80211_AMPDU_TX_OPERATIONAL:
5550 break;
5551 default:
4e9e58c6 5552 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 5553 }
5554
5555 return ret;
5556}
e783619e 5557EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 5558
977206d7
HS		 5559int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5560 struct survey_info *survey)
5561{
5562 struct rt2x00_dev *rt2x00dev = hw->priv;
5563 struct ieee80211_conf *conf = &hw->conf;
5564 u32 idle, busy, busy_ext;
5565
5566 if (idx != 0)
5567 return -ENOENT;
5568
5569 survey->channel = conf->channel;
5570
5571 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5572 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5573 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5574
5575 if (idle || busy) {
5576 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5577 SURVEY_INFO_CHANNEL_TIME_BUSY |
5578 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5579
5580 survey->channel_time = (idle + busy) / 1000;
5581 survey->channel_time_busy = busy / 1000;
5582 survey->channel_time_ext_busy = busy_ext / 1000;
5583 }
5584
9931df26
HS		 5585 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5586 survey->filled |= SURVEY_INFO_IN_USE;
5587
977206d7
HS		 5588 return 0;
5589
5590}
5591EXPORT_SYMBOL_GPL(rt2800_get_survey);
5592
a5ea2f02
ID		 5593MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5594MODULE_VERSION(DRV_VERSION);
5595MODULE_DESCRIPTION("Ralink RT2800 library");
5596MODULE_LICENSE("GPL");
Ubuntu Jammy Linux kernel mirror