]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/wireless/rt2x00/rt2800lib.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: Remove RT2870 chipset identification.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
9c9a0d14 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 4
9c9a0d14
GW		 5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
ac394917 41#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 42#include "rt2x00usb.h"
43#endif
89297425
BZ		 44#include "rt2800lib.h"
45#include "rt2800.h"
fcf51541 46#include "rt2800usb.h"
89297425
BZ		 47
48MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
49MODULE_DESCRIPTION("rt2800 library");
50MODULE_LICENSE("GPL");
51
52/*
53 * Register access.
54 * All access to the CSR registers will go through the methods
55 * rt2800_register_read and rt2800_register_write.
56 * BBP and RF register require indirect register access,
57 * and use the CSR registers BBPCSR and RFCSR to achieve this.
58 * These indirect registers work with busy bits,
59 * and we will try maximal REGISTER_BUSY_COUNT times to access
60 * the register while taking a REGISTER_BUSY_DELAY us delay
61 * between each attampt. When the busy bit is still set at that time,
62 * the access attempt is considered to have failed,
63 * and we will print an error.
64 * The _lock versions must be used if you already hold the csr_mutex
65 */
66#define WAIT_FOR_BBP(__dev, __reg) \
67 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
68#define WAIT_FOR_RFCSR(__dev, __reg) \
69 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RF(__dev, __reg) \
71 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
72#define WAIT_FOR_MCU(__dev, __reg) \
73 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
74 H2M_MAILBOX_CSR_OWNER, (__reg))
75
baff8006
HS		 76static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
77{
78 /* check for rt2872 on SoC */
79 if (!rt2x00_is_soc(rt2x00dev) ||
80 !rt2x00_rt(rt2x00dev, RT2872))
81 return false;
82
83 /* we know for sure that these rf chipsets are used on rt305x boards */
84 if (rt2x00_rf(rt2x00dev, RF3020) ||
85 rt2x00_rf(rt2x00dev, RF3021) ||
86 rt2x00_rf(rt2x00dev, RF3022))
87 return true;
88
89 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
90 return false;
91}
92
fcf51541
BZ		 93static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, const u8 value)
89297425
BZ		 95{
96 u32 reg;
97
98 mutex_lock(&rt2x00dev->csr_mutex);
99
100 /*
101 * Wait until the BBP becomes available, afterwards we
102 * can safely write the new data into the register.
103 */
104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
107 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
108 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
109 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 110 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 111 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
112
113 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
114 }
115
116 mutex_unlock(&rt2x00dev->csr_mutex);
117}
89297425 118
fcf51541
BZ		 119static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
120 const unsigned int word, u8 *value)
89297425
BZ		 121{
122 u32 reg;
123
124 mutex_lock(&rt2x00dev->csr_mutex);
125
126 /*
127 * Wait until the BBP becomes available, afterwards we
128 * can safely write the read request into the register.
129 * After the data has been written, we wait until hardware
130 * returns the correct value, if at any time the register
131 * doesn't become available in time, reg will be 0xffffffff
132 * which means we return 0xff to the caller.
133 */
134 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
137 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
138 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 139 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 140 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
141
142 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
143
144 WAIT_FOR_BBP(rt2x00dev, &reg);
145 }
146
147 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
148
149 mutex_unlock(&rt2x00dev->csr_mutex);
150}
89297425 151
fcf51541
BZ		 152static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
153 const unsigned int word, const u8 value)
89297425
BZ		 154{
155 u32 reg;
156
157 mutex_lock(&rt2x00dev->csr_mutex);
158
159 /*
160 * Wait until the RFCSR becomes available, afterwards we
161 * can safely write the new data into the register.
162 */
163 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
164 reg = 0;
165 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
171 }
172
173 mutex_unlock(&rt2x00dev->csr_mutex);
174}
89297425 175
fcf51541
BZ		 176static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
177 const unsigned int word, u8 *value)
89297425
BZ		 178{
179 u32 reg;
180
181 mutex_lock(&rt2x00dev->csr_mutex);
182
183 /*
184 * Wait until the RFCSR becomes available, afterwards we
185 * can safely write the read request into the register.
186 * After the data has been written, we wait until hardware
187 * returns the correct value, if at any time the register
188 * doesn't become available in time, reg will be 0xffffffff
189 * which means we return 0xff to the caller.
190 */
191 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
194 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
196
197 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
198
199 WAIT_FOR_RFCSR(rt2x00dev, &reg);
200 }
201
202 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
203
204 mutex_unlock(&rt2x00dev->csr_mutex);
205}
89297425 206
fcf51541
BZ		 207static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
208 const unsigned int word, const u32 value)
89297425
BZ		 209{
210 u32 reg;
211
212 mutex_lock(&rt2x00dev->csr_mutex);
213
214 /*
215 * Wait until the RF becomes available, afterwards we
216 * can safely write the new data into the register.
217 */
218 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
219 reg = 0;
220 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
221 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
222 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
223 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
224
225 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
226 rt2x00_rf_write(rt2x00dev, word, value);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
89297425
BZ		 231
232void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
233 const u8 command, const u8 token,
234 const u8 arg0, const u8 arg1)
235{
236 u32 reg;
237
ee303e54 238 /*
cea90e55 239 * SOC devices don't support MCU requests.
ee303e54 240 */
cea90e55 241 if (rt2x00_is_soc(rt2x00dev))
ee303e54 242 return;
89297425
BZ		 243
244 mutex_lock(&rt2x00dev->csr_mutex);
245
246 /*
247 * Wait until the MCU becomes available, afterwards we
248 * can safely write the new data into the register.
249 */
250 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
251 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
252 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
253 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
254 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
255 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
256
257 reg = 0;
258 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
259 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
260 }
261
262 mutex_unlock(&rt2x00dev->csr_mutex);
263}
264EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 265
67a4c1e2
GW		 266int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
267{
268 unsigned int i;
269 u32 reg;
270
271 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
272 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
273 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
274 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
275 return 0;
276
277 msleep(1);
278 }
279
280 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
281 return -EACCES;
282}
283EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
284
0b8004aa 285void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
59679b91 286{
59679b91
GW		 287 u32 word;
288
289 /*
290 * Initialize TX Info descriptor
291 */
292 rt2x00_desc_read(txwi, 0, &word);
293 rt2x00_set_field32(&word, TXWI_W0_FRAG,
294 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
295 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
296 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
297 rt2x00_set_field32(&word, TXWI_W0_TS,
298 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
299 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
300 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
301 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
302 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
303 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
304 rt2x00_set_field32(&word, TXWI_W0_BW,
305 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
306 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
307 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
308 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
309 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
310 rt2x00_desc_write(txwi, 0, word);
311
312 rt2x00_desc_read(txwi, 1, &word);
313 rt2x00_set_field32(&word, TXWI_W1_ACK,
314 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
315 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
316 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
317 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
318 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
319 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
320 txdesc->key_idx : 0xff);
321 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
322 txdesc->length);
323 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
324 rt2x00_desc_write(txwi, 1, word);
325
326 /*
327 * Always write 0 to IV/EIV fields, hardware will insert the IV
328 * from the IVEIV register when TXD_W3_WIV is set to 0.
329 * When TXD_W3_WIV is set to 1 it will use the IV data
330 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
331 * crypto entry in the registers should be used to encrypt the frame.
332 */
333 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
334 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
335}
336EXPORT_SYMBOL_GPL(rt2800_write_txwi);
337
2de64dd2
GW		 338void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
339{
340 __le32 *rxwi = (__le32 *) skb->data;
341 u32 word;
342
343 rt2x00_desc_read(rxwi, 0, &word);
344
345 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
346 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
347
348 rt2x00_desc_read(rxwi, 1, &word);
349
350 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
351 rxdesc->flags |= RX_FLAG_SHORT_GI;
352
353 if (rt2x00_get_field32(word, RXWI_W1_BW))
354 rxdesc->flags |= RX_FLAG_40MHZ;
355
356 /*
357 * Detect RX rate, always use MCS as signal type.
358 */
359 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
360 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
361 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
362
363 /*
364 * Mask of 0x8 bit to remove the short preamble flag.
365 */
366 if (rxdesc->rate_mode == RATE_MODE_CCK)
367 rxdesc->signal &= ~0x8;
368
369 rt2x00_desc_read(rxwi, 2, &word);
370
371 rxdesc->rssi =
372 (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
373 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
374
375 /*
376 * Remove RXWI descriptor from start of buffer.
377 */
378 skb_pull(skb, RXWI_DESC_SIZE);
379}
380EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
381
f0194b2d
GW		 382void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
383{
384 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
385 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
386 unsigned int beacon_base;
387 u32 reg;
388
389 /*
390 * Disable beaconing while we are reloading the beacon data,
391 * otherwise we might be sending out invalid data.
392 */
393 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
394 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
395 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
396
397 /*
398 * Add space for the TXWI in front of the skb.
399 */
400 skb_push(entry->skb, TXWI_DESC_SIZE);
401 memset(entry->skb, 0, TXWI_DESC_SIZE);
402
403 /*
404 * Register descriptor details in skb frame descriptor.
405 */
406 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
407 skbdesc->desc = entry->skb->data;
408 skbdesc->desc_len = TXWI_DESC_SIZE;
409
410 /*
411 * Add the TXWI for the beacon to the skb.
412 */
413 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
414
415 /*
416 * Dump beacon to userspace through debugfs.
417 */
418 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
419
420 /*
421 * Write entire beacon with TXWI to register.
422 */
423 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
424 rt2800_register_multiwrite(rt2x00dev, beacon_base,
425 entry->skb->data, entry->skb->len);
426
427 /*
428 * Enable beaconing again.
429 */
430 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
431 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
432 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
433 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
434
435 /*
436 * Clean up beacon skb.
437 */
438 dev_kfree_skb_any(entry->skb);
439 entry->skb = NULL;
440}
441EXPORT_SYMBOL(rt2800_write_beacon);
442
f4450616
BZ		 443#ifdef CONFIG_RT2X00_LIB_DEBUGFS
444const struct rt2x00debug rt2800_rt2x00debug = {
445 .owner = THIS_MODULE,
446 .csr = {
447 .read = rt2800_register_read,
448 .write = rt2800_register_write,
449 .flags = RT2X00DEBUGFS_OFFSET,
450 .word_base = CSR_REG_BASE,
451 .word_size = sizeof(u32),
452 .word_count = CSR_REG_SIZE / sizeof(u32),
453 },
454 .eeprom = {
455 .read = rt2x00_eeprom_read,
456 .write = rt2x00_eeprom_write,
457 .word_base = EEPROM_BASE,
458 .word_size = sizeof(u16),
459 .word_count = EEPROM_SIZE / sizeof(u16),
460 },
461 .bbp = {
462 .read = rt2800_bbp_read,
463 .write = rt2800_bbp_write,
464 .word_base = BBP_BASE,
465 .word_size = sizeof(u8),
466 .word_count = BBP_SIZE / sizeof(u8),
467 },
468 .rf = {
469 .read = rt2x00_rf_read,
470 .write = rt2800_rf_write,
471 .word_base = RF_BASE,
472 .word_size = sizeof(u32),
473 .word_count = RF_SIZE / sizeof(u32),
474 },
475};
476EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
477#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
478
479int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
480{
481 u32 reg;
482
483 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
484 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
485}
486EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
487
488#ifdef CONFIG_RT2X00_LIB_LEDS
489static void rt2800_brightness_set(struct led_classdev *led_cdev,
490 enum led_brightness brightness)
491{
492 struct rt2x00_led *led =
493 container_of(led_cdev, struct rt2x00_led, led_dev);
494 unsigned int enabled = brightness != LED_OFF;
495 unsigned int bg_mode =
496 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
497 unsigned int polarity =
498 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
499 EEPROM_FREQ_LED_POLARITY);
500 unsigned int ledmode =
501 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
502 EEPROM_FREQ_LED_MODE);
503
504 if (led->type == LED_TYPE_RADIO) {
505 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
506 enabled ? 0x20 : 0);
507 } else if (led->type == LED_TYPE_ASSOC) {
508 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
509 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
510 } else if (led->type == LED_TYPE_QUALITY) {
511 /*
512 * The brightness is divided into 6 levels (0 - 5),
513 * The specs tell us the following levels:
514 * 0, 1 ,3, 7, 15, 31
515 * to determine the level in a simple way we can simply
516 * work with bitshifting:
517 * (1 << level) - 1
518 */
519 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
520 (1 << brightness / (LED_FULL / 6)) - 1,
521 polarity);
522 }
523}
524
525static int rt2800_blink_set(struct led_classdev *led_cdev,
526 unsigned long *delay_on, unsigned long *delay_off)
527{
528 struct rt2x00_led *led =
529 container_of(led_cdev, struct rt2x00_led, led_dev);
530 u32 reg;
531
532 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
533 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
534 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 535 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
536
537 return 0;
538}
539
b3579d6a 540static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 541 struct rt2x00_led *led, enum led_type type)
542{
543 led->rt2x00dev = rt2x00dev;
544 led->type = type;
545 led->led_dev.brightness_set = rt2800_brightness_set;
546 led->led_dev.blink_set = rt2800_blink_set;
547 led->flags = LED_INITIALIZED;
548}
f4450616
BZ		 549#endif /* CONFIG_RT2X00_LIB_LEDS */
550
551/*
552 * Configuration handlers.
553 */
554static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
555 struct rt2x00lib_crypto *crypto,
556 struct ieee80211_key_conf *key)
557{
558 struct mac_wcid_entry wcid_entry;
559 struct mac_iveiv_entry iveiv_entry;
560 u32 offset;
561 u32 reg;
562
563 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
564
565 rt2800_register_read(rt2x00dev, offset, &reg);
566 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
567 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
568 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
569 (crypto->cmd == SET_KEY) * crypto->cipher);
570 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
571 (crypto->cmd == SET_KEY) * crypto->bssidx);
572 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
573 rt2800_register_write(rt2x00dev, offset, reg);
574
575 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
576
577 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
578 if ((crypto->cipher == CIPHER_TKIP) ||
579 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
580 (crypto->cipher == CIPHER_AES))
581 iveiv_entry.iv[3] |= 0x20;
582 iveiv_entry.iv[3] |= key->keyidx << 6;
583 rt2800_register_multiwrite(rt2x00dev, offset,
584 &iveiv_entry, sizeof(iveiv_entry));
585
586 offset = MAC_WCID_ENTRY(key->hw_key_idx);
587
588 memset(&wcid_entry, 0, sizeof(wcid_entry));
589 if (crypto->cmd == SET_KEY)
590 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
591 rt2800_register_multiwrite(rt2x00dev, offset,
592 &wcid_entry, sizeof(wcid_entry));
593}
594
595int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
596 struct rt2x00lib_crypto *crypto,
597 struct ieee80211_key_conf *key)
598{
599 struct hw_key_entry key_entry;
600 struct rt2x00_field32 field;
601 u32 offset;
602 u32 reg;
603
604 if (crypto->cmd == SET_KEY) {
605 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
606
607 memcpy(key_entry.key, crypto->key,
608 sizeof(key_entry.key));
609 memcpy(key_entry.tx_mic, crypto->tx_mic,
610 sizeof(key_entry.tx_mic));
611 memcpy(key_entry.rx_mic, crypto->rx_mic,
612 sizeof(key_entry.rx_mic));
613
614 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
615 rt2800_register_multiwrite(rt2x00dev, offset,
616 &key_entry, sizeof(key_entry));
617 }
618
619 /*
620 * The cipher types are stored over multiple registers
621 * starting with SHARED_KEY_MODE_BASE each word will have
622 * 32 bits and contains the cipher types for 2 bssidx each.
623 * Using the correct defines correctly will cause overhead,
624 * so just calculate the correct offset.
625 */
626 field.bit_offset = 4 * (key->hw_key_idx % 8);
627 field.bit_mask = 0x7 << field.bit_offset;
628
629 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
630
631 rt2800_register_read(rt2x00dev, offset, &reg);
632 rt2x00_set_field32(&reg, field,
633 (crypto->cmd == SET_KEY) * crypto->cipher);
634 rt2800_register_write(rt2x00dev, offset, reg);
635
636 /*
637 * Update WCID information
638 */
639 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
640
641 return 0;
642}
643EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
644
645int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
646 struct rt2x00lib_crypto *crypto,
647 struct ieee80211_key_conf *key)
648{
649 struct hw_key_entry key_entry;
650 u32 offset;
651
652 if (crypto->cmd == SET_KEY) {
653 /*
654 * 1 pairwise key is possible per AID, this means that the AID
655 * equals our hw_key_idx. Make sure the WCID starts _after_ the
656 * last possible shared key entry.
657 */
658 if (crypto->aid > (256 - 32))
659 return -ENOSPC;
660
661 key->hw_key_idx = 32 + crypto->aid;
662
663 memcpy(key_entry.key, crypto->key,
664 sizeof(key_entry.key));
665 memcpy(key_entry.tx_mic, crypto->tx_mic,
666 sizeof(key_entry.tx_mic));
667 memcpy(key_entry.rx_mic, crypto->rx_mic,
668 sizeof(key_entry.rx_mic));
669
670 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
671 rt2800_register_multiwrite(rt2x00dev, offset,
672 &key_entry, sizeof(key_entry));
673 }
674
675 /*
676 * Update WCID information
677 */
678 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
679
680 return 0;
681}
682EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
683
684void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
685 const unsigned int filter_flags)
686{
687 u32 reg;
688
689 /*
690 * Start configuration steps.
691 * Note that the version error will always be dropped
692 * and broadcast frames will always be accepted since
693 * there is no filter for it at this time.
694 */
695 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
696 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
697 !(filter_flags & FIF_FCSFAIL));
698 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
699 !(filter_flags & FIF_PLCPFAIL));
700 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
701 !(filter_flags & FIF_PROMISC_IN_BSS));
702 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
703 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
704 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
705 !(filter_flags & FIF_ALLMULTI));
706 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
707 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
708 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
709 !(filter_flags & FIF_CONTROL));
710 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
711 !(filter_flags & FIF_CONTROL));
712 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
713 !(filter_flags & FIF_CONTROL));
714 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
715 !(filter_flags & FIF_CONTROL));
716 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
717 !(filter_flags & FIF_CONTROL));
718 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
719 !(filter_flags & FIF_PSPOLL));
720 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
721 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
722 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
723 !(filter_flags & FIF_CONTROL));
724 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
725}
726EXPORT_SYMBOL_GPL(rt2800_config_filter);
727
728void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
729 struct rt2x00intf_conf *conf, const unsigned int flags)
730{
731 unsigned int beacon_base;
732 u32 reg;
733
734 if (flags & CONFIG_UPDATE_TYPE) {
735 /*
736 * Clear current synchronisation setup.
737 * For the Beacon base registers we only need to clear
738 * the first byte since that byte contains the VALID and OWNER
739 * bits which (when set to 0) will invalidate the entire beacon.
740 */
741 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
742 rt2800_register_write(rt2x00dev, beacon_base, 0);
743
744 /*
745 * Enable synchronisation.
746 */
747 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
748 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
749 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 750 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
751 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
753 }
754
755 if (flags & CONFIG_UPDATE_MAC) {
756 reg = le32_to_cpu(conf->mac[1]);
757 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
758 conf->mac[1] = cpu_to_le32(reg);
759
760 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
761 conf->mac, sizeof(conf->mac));
762 }
763
764 if (flags & CONFIG_UPDATE_BSSID) {
765 reg = le32_to_cpu(conf->bssid[1]);
766 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
767 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
768 conf->bssid[1] = cpu_to_le32(reg);
769
770 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
771 conf->bssid, sizeof(conf->bssid));
772 }
773}
774EXPORT_SYMBOL_GPL(rt2800_config_intf);
775
776void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
777{
778 u32 reg;
779
f4450616
BZ		 780 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
781 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
782 !!erp->short_preamble);
783 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
784 !!erp->short_preamble);
785 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
786
787 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
788 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
789 erp->cts_protection ? 2 : 0);
790 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
791
792 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
793 erp->basic_rates);
794 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
795
796 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
797 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 798 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
799
800 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 801 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 802 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
803
804 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
805 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
806 erp->beacon_int * 16);
807 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
808}
809EXPORT_SYMBOL_GPL(rt2800_config_erp);
810
811void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
812{
813 u8 r1;
814 u8 r3;
815
816 rt2800_bbp_read(rt2x00dev, 1, &r1);
817 rt2800_bbp_read(rt2x00dev, 3, &r3);
818
819 /*
820 * Configure the TX antenna.
821 */
822 switch ((int)ant->tx) {
823 case 1:
824 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 825 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 826 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
827 break;
828 case 2:
829 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
830 break;
831 case 3:
832 /* Do nothing */
833 break;
834 }
835
836 /*
837 * Configure the RX antenna.
838 */
839 switch ((int)ant->rx) {
840 case 1:
841 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
842 break;
843 case 2:
844 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
845 break;
846 case 3:
847 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
848 break;
849 }
850
851 rt2800_bbp_write(rt2x00dev, 3, r3);
852 rt2800_bbp_write(rt2x00dev, 1, r1);
853}
854EXPORT_SYMBOL_GPL(rt2800_config_ant);
855
856static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf)
858{
859 u16 eeprom;
860 short lna_gain;
861
862 if (libconf->rf.channel <= 14) {
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
864 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
865 } else if (libconf->rf.channel <= 64) {
866 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
867 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
868 } else if (libconf->rf.channel <= 128) {
869 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
870 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
871 } else {
872 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
873 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
874 }
875
876 rt2x00dev->lna_gain = lna_gain;
877}
878
06855ef4
GW		 879static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
880 struct ieee80211_conf *conf,
881 struct rf_channel *rf,
882 struct channel_info *info)
f4450616
BZ		 883{
884 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
885
886 if (rt2x00dev->default_ant.tx == 1)
887 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
888
889 if (rt2x00dev->default_ant.rx == 1) {
890 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
891 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
892 } else if (rt2x00dev->default_ant.rx == 2)
893 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
894
895 if (rf->channel > 14) {
896 /*
897 * When TX power is below 0, we should increase it by 7 to
898 * make it a positive value (Minumum value is -7).
899 * However this means that values between 0 and 7 have
900 * double meaning, and we should set a 7DBm boost flag.
901 */
902 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
903 (info->tx_power1 >= 0));
904
905 if (info->tx_power1 < 0)
906 info->tx_power1 += 7;
907
908 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
909 TXPOWER_A_TO_DEV(info->tx_power1));
910
911 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
912 (info->tx_power2 >= 0));
913
914 if (info->tx_power2 < 0)
915 info->tx_power2 += 7;
916
917 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
918 TXPOWER_A_TO_DEV(info->tx_power2));
919 } else {
920 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
921 TXPOWER_G_TO_DEV(info->tx_power1));
922 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
923 TXPOWER_G_TO_DEV(info->tx_power2));
924 }
925
926 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
927
928 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
929 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
930 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
931 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
932
933 udelay(200);
934
935 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
936 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
937 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
938 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
939
940 udelay(200);
941
942 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
943 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
944 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
945 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
946}
947
06855ef4
GW		 948static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
949 struct ieee80211_conf *conf,
950 struct rf_channel *rf,
951 struct channel_info *info)
f4450616
BZ		 952{
953 u8 rfcsr;
954
955 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 956 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 957
958 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 959 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 960 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
961
962 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
963 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
964 TXPOWER_G_TO_DEV(info->tx_power1));
965 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
966
5a673964
HS		 967 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
968 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
969 TXPOWER_G_TO_DEV(info->tx_power2));
970 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
971
f4450616
BZ		 972 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
973 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
974 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
975
976 rt2800_rfcsr_write(rt2x00dev, 24,
977 rt2x00dev->calibration[conf_is_ht40(conf)]);
978
71976907 979 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 980 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 981 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 982}
983
984static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
985 struct ieee80211_conf *conf,
986 struct rf_channel *rf,
987 struct channel_info *info)
988{
989 u32 reg;
990 unsigned int tx_pin;
991 u8 bbp;
992
06855ef4
GW		 993 if (rt2x00_rf(rt2x00dev, RF2020) ||
994 rt2x00_rf(rt2x00dev, RF3020) ||
995 rt2x00_rf(rt2x00dev, RF3021) ||
996 rt2x00_rf(rt2x00dev, RF3022))
997 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 998 else
06855ef4 999 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1000
1001 /*
1002 * Change BBP settings
1003 */
1004 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1005 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1006 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1007 rt2800_bbp_write(rt2x00dev, 86, 0);
1008
1009 if (rf->channel <= 14) {
1010 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1011 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1012 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1013 } else {
1014 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1015 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1016 }
1017 } else {
1018 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1019
1020 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1021 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1022 else
1023 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1024 }
1025
1026 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1027 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1028 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1029 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1030 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1031
1032 tx_pin = 0;
1033
1034 /* Turn on unused PA or LNA when not using 1T or 1R */
1035 if (rt2x00dev->default_ant.tx != 1) {
1036 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1037 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1038 }
1039
1040 /* Turn on unused PA or LNA when not using 1T or 1R */
1041 if (rt2x00dev->default_ant.rx != 1) {
1042 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1043 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1044 }
1045
1046 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1047 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1048 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1049 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1050 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1051 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1052
1053 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1054
1055 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1056 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1057 rt2800_bbp_write(rt2x00dev, 4, bbp);
1058
1059 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1060 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1061 rt2800_bbp_write(rt2x00dev, 3, bbp);
1062
8d0c9b65 1063 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1064 if (conf_is_ht40(conf)) {
1065 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1066 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1067 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1068 } else {
1069 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1070 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1071 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1072 }
1073 }
1074
1075 msleep(1);
1076}
1077
1078static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1079 const int txpower)
1080{
1081 u32 reg;
1082 u32 value = TXPOWER_G_TO_DEV(txpower);
1083 u8 r1;
1084
1085 rt2800_bbp_read(rt2x00dev, 1, &r1);
1086 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1087 rt2800_bbp_write(rt2x00dev, 1, r1);
1088
1089 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1090 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1091 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1092 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1093 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1094 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1095 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1096 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1097 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1098 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1099
1100 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1101 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1102 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1103 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1104 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1105 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1106 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1107 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1108 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1109 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1110
1111 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1112 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1113 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1114 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1115 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1116 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1117 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1118 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1119 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1120 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1121
1122 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1123 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1124 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1125 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1126 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1127 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1128 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1129 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1130 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1131 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1132
1133 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1134 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1135 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1136 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1137 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1138 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1139}
1140
1141static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1142 struct rt2x00lib_conf *libconf)
1143{
1144 u32 reg;
1145
1146 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1147 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1148 libconf->conf->short_frame_max_tx_count);
1149 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1150 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1151 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1152}
1153
1154static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1155 struct rt2x00lib_conf *libconf)
1156{
1157 enum dev_state state =
1158 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1159 STATE_SLEEP : STATE_AWAKE;
1160 u32 reg;
1161
1162 if (state == STATE_SLEEP) {
1163 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1164
1165 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1166 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1167 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1168 libconf->conf->listen_interval - 1);
1169 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1170 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1171
1172 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1173 } else {
f4450616
BZ		 1174 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1175 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1176 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1177 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1178 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1179
1180 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1181 }
1182}
1183
1184void rt2800_config(struct rt2x00_dev *rt2x00dev,
1185 struct rt2x00lib_conf *libconf,
1186 const unsigned int flags)
1187{
1188 /* Always recalculate LNA gain before changing configuration */
1189 rt2800_config_lna_gain(rt2x00dev, libconf);
1190
1191 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1192 rt2800_config_channel(rt2x00dev, libconf->conf,
1193 &libconf->rf, &libconf->channel);
1194 if (flags & IEEE80211_CONF_CHANGE_POWER)
1195 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1196 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1197 rt2800_config_retry_limit(rt2x00dev, libconf);
1198 if (flags & IEEE80211_CONF_CHANGE_PS)
1199 rt2800_config_ps(rt2x00dev, libconf);
1200}
1201EXPORT_SYMBOL_GPL(rt2800_config);
1202
1203/*
1204 * Link tuning
1205 */
1206void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1207{
1208 u32 reg;
1209
1210 /*
1211 * Update FCS error count from register.
1212 */
1213 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1214 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1215}
1216EXPORT_SYMBOL_GPL(rt2800_link_stats);
1217
1218static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1219{
1220 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1221 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1222 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1223 rt2x00_rt(rt2x00dev, RT3090) ||
1224 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1225 return 0x1c + (2 * rt2x00dev->lna_gain);
1226 else
1227 return 0x2e + rt2x00dev->lna_gain;
1228 }
1229
1230 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1231 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1232 else
1233 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1234}
1235
1236static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1237 struct link_qual *qual, u8 vgc_level)
1238{
1239 if (qual->vgc_level != vgc_level) {
1240 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1241 qual->vgc_level = vgc_level;
1242 qual->vgc_level_reg = vgc_level;
1243 }
1244}
1245
1246void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1247{
1248 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1249}
1250EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1251
1252void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1253 const u32 count)
1254{
8d0c9b65 1255 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1256 return;
1257
1258 /*
1259 * When RSSI is better then -80 increase VGC level with 0x10
1260 */
1261 rt2800_set_vgc(rt2x00dev, qual,
1262 rt2800_get_default_vgc(rt2x00dev) +
1263 ((qual->rssi > -80) * 0x10));
1264}
1265EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1266
1267/*
1268 * Initialization functions.
1269 */
1270int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1271{
1272 u32 reg;
d5385bfc 1273 u16 eeprom;
fcf51541
BZ		 1274 unsigned int i;
1275
a9dce149
GW		 1276 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1282 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1283
cea90e55 1284 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1285 /*
235faf9b 1286 * Wait until BBP and RF are ready.
fcf51541
BZ		 1287 */
1288 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1289 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1290 if (reg && reg != ~0)
1291 break;
1292 msleep(1);
1293 }
1294
1295 if (i == REGISTER_BUSY_COUNT) {
1296 ERROR(rt2x00dev, "Unstable hardware.\n");
1297 return -EBUSY;
1298 }
1299
1300 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1301 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1302 reg & ~0x00002000);
a9dce149
GW		 1303 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1304 /*
1305 * Reset DMA indexes
1306 */
1307 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1308 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1309 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1310 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1311 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1312 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1313 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1314 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1315 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1316
1317 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1318 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1319
fcf51541 1320 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
a9dce149 1321 }
fcf51541
BZ		 1322
1323 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1324 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1325 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1326 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1327
cea90e55 1328 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1329 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
ac394917 1330#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 1331 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1332 USB_MODE_RESET, REGISTER_TIMEOUT);
1333#endif
1334 }
1335
1336 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1337
1338 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1339 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1340 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1341 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1342 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1343 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1344
1345 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1346 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1347 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1348 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1349 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1350 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1351
1352 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1353 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1354
1355 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1356
1357 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1358 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1359 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1360 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1361 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1362 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1363 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1364 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1365
a9dce149
GW		 1366 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1367
1368 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1369 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1370 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1371 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1372
64522957 1373 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1374 rt2x00_rt(rt2x00dev, RT3090) ||
1375 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1376 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1377 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1378 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1379 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1380 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1381 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1382 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1383 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1384 0x0000002c);
1385 else
1386 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1387 0x0000000f);
1388 } else {
1389 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1390 }
1391 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1392 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1393 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1394
1395 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1396 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1397 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1398 } else {
1399 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1400 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1401 }
fcf51541
BZ		 1402 } else {
1403 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1404 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1405 }
1406
1407 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1408 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1409 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1410 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1411 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1412 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1413 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1414 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1415 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1416 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1417
1418 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1419 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1420 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1421 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1422 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1423
1424 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1425 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1426 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1427 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1428 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1429 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1430 else
1431 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1432 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1433 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1434 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1435
a9dce149
GW		 1436 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1437 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1438 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1439 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1440 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1441 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1442 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1443 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1444 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1445
fcf51541
BZ		 1446 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1447
a9dce149
GW		 1448 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1449 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1450 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1451 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1452 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1453 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1454 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1455 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1456
fcf51541
BZ		 1457 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1458 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1459 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1460 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1461 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1462 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1463 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1464 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1465 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1466
1467 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1468 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1469 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1470 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1471 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1472 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1473 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1474 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1475 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1476 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1477 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1478 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1479
1480 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1481 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1482 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1483 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1484 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1485 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1486 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1487 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1488 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1489 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1490 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1491 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1492
1493 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1494 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1495 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1496 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1497 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1498 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1499 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1500 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1501 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1502 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1503 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1504 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1505
1506 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1507 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1508 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1509 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1510 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1511 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1512 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1513 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1514 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1515 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1516 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1517 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1518 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1519
1520 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1521 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1522 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1523 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1524 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1525 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1526 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1527 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1528 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1529 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1530 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1531 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1532
1533 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1534 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1535 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1536 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1537 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1538 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1539 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1540 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1541 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1542 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1543 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1544 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1545
cea90e55 1546 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1547 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1548
1549 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1550 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1551 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1552 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1553 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1554 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1555 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1556 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1559 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1560 }
1561
1562 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1563 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1564
1565 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1566 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1567 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1568 IEEE80211_MAX_RTS_THRESHOLD);
1569 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1570 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1571
1572 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1573
a21c2ab4
HS		 1574 /*
1575 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1576 * time should be set to 16. However, the original Ralink driver uses
1577 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1578 * connection problems with 11g + CTS protection. Hence, use the same
1579 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1580 */
a9dce149 1581 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1582 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1583 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1584 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1585 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1586 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1587 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1588
fcf51541
BZ		 1589 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1590
1591 /*
1592 * ASIC will keep garbage value after boot, clear encryption keys.
1593 */
1594 for (i = 0; i < 4; i++)
1595 rt2800_register_write(rt2x00dev,
1596 SHARED_KEY_MODE_ENTRY(i), 0);
1597
1598 for (i = 0; i < 256; i++) {
1599 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1600 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1601 wcid, sizeof(wcid));
1602
1603 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1604 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1605 }
1606
1607 /*
1608 * Clear all beacons
1609 * For the Beacon base registers we only need to clear
1610 * the first byte since that byte contains the VALID and OWNER
1611 * bits which (when set to 0) will invalidate the entire beacon.
1612 */
1613 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1614 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1615 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1616 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1617 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1618 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1619 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1620 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1621
cea90e55 1622 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1623 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1624 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1625 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1626 }
1627
1628 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1629 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1630 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1631 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1632 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1633 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1634 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1635 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1636 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1637 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1638
1639 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1640 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1641 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1642 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1643 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1644 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1645 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1646 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1647 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1648 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1649
1650 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1651 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1652 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1653 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1654 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1655 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1656 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1657 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1658 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1659 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1660
1661 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1663 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1665 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1666 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1667
1668 /*
1669 * We must clear the error counters.
1670 * These registers are cleared on read,
1671 * so we may pass a useless variable to store the value.
1672 */
1673 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1674 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1675 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1676 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1677 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1678 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1679
1680 return 0;
1681}
1682EXPORT_SYMBOL_GPL(rt2800_init_registers);
1683
1684static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1685{
1686 unsigned int i;
1687 u32 reg;
1688
1689 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1690 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1691 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1692 return 0;
1693
1694 udelay(REGISTER_BUSY_DELAY);
1695 }
1696
1697 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1698 return -EACCES;
1699}
1700
1701static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1702{
1703 unsigned int i;
1704 u8 value;
1705
1706 /*
1707 * BBP was enabled after firmware was loaded,
1708 * but we need to reactivate it now.
1709 */
1710 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1711 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1712 msleep(1);
1713
1714 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1715 rt2800_bbp_read(rt2x00dev, 0, &value);
1716 if ((value != 0xff) && (value != 0x00))
1717 return 0;
1718 udelay(REGISTER_BUSY_DELAY);
1719 }
1720
1721 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1722 return -EACCES;
1723}
1724
1725int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1726{
1727 unsigned int i;
1728 u16 eeprom;
1729 u8 reg_id;
1730 u8 value;
1731
1732 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1733 rt2800_wait_bbp_ready(rt2x00dev)))
1734 return -EACCES;
1735
baff8006
HS		 1736 if (rt2800_is_305x_soc(rt2x00dev))
1737 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1738
fcf51541
BZ		 1739 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1740 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1741
1742 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1743 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1744 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1745 } else {
1746 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1747 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1748 }
1749
fcf51541 1750 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1751
d5385bfc 1752 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1753 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1754 rt2x00_rt(rt2x00dev, RT3090) ||
1755 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1756 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1757 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1758 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1759 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1760 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1761 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1762 } else {
1763 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1764 }
1765
fcf51541
BZ		 1766 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1767 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 1768
5ed8f458 1769 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 1770 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1771 else
1772 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1773
fcf51541
BZ		 1774 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1775 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1776 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1777
d5385bfc 1778 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1779 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 1780 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 1781 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1782 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 1783 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1784 else
1785 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1786
baff8006
HS		 1787 if (rt2800_is_305x_soc(rt2x00dev))
1788 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1789 else
1790 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1791 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1792
64522957 1793 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1794 rt2x00_rt(rt2x00dev, RT3090) ||
1795 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 1796 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 1797
d5385bfc
GW		 1798 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1799 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1800 value |= 0x20;
1801 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1802 value &= ~0x02;
fcf51541 1803
d5385bfc 1804 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 1805 }
1806
fcf51541
BZ		 1807
1808 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1809 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1810
1811 if (eeprom != 0xffff && eeprom != 0x0000) {
1812 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1813 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1814 rt2800_bbp_write(rt2x00dev, reg_id, value);
1815 }
1816 }
1817
1818 return 0;
1819}
1820EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1821
1822static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1823 bool bw40, u8 rfcsr24, u8 filter_target)
1824{
1825 unsigned int i;
1826 u8 bbp;
1827 u8 rfcsr;
1828 u8 passband;
1829 u8 stopband;
1830 u8 overtuned = 0;
1831
1832 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1833
1834 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1835 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1836 rt2800_bbp_write(rt2x00dev, 4, bbp);
1837
1838 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1839 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1840 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1841
1842 /*
1843 * Set power & frequency of passband test tone
1844 */
1845 rt2800_bbp_write(rt2x00dev, 24, 0);
1846
1847 for (i = 0; i < 100; i++) {
1848 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1849 msleep(1);
1850
1851 rt2800_bbp_read(rt2x00dev, 55, &passband);
1852 if (passband)
1853 break;
1854 }
1855
1856 /*
1857 * Set power & frequency of stopband test tone
1858 */
1859 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1860
1861 for (i = 0; i < 100; i++) {
1862 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1863 msleep(1);
1864
1865 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1866
1867 if ((passband - stopband) <= filter_target) {
1868 rfcsr24++;
1869 overtuned += ((passband - stopband) == filter_target);
1870 } else
1871 break;
1872
1873 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1874 }
1875
1876 rfcsr24 -= !!overtuned;
1877
1878 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1879 return rfcsr24;
1880}
1881
1882int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1883{
1884 u8 rfcsr;
1885 u8 bbp;
8cdd15e0
GW		 1886 u32 reg;
1887 u16 eeprom;
fcf51541 1888
d5385bfc 1889 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1890 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1891 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 1892 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 1893 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 1894 return 0;
1895
fcf51541
BZ		 1896 /*
1897 * Init RF calibration.
1898 */
1899 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1900 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1901 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1902 msleep(1);
1903 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1904 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1905
d5385bfc 1906 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1907 rt2x00_rt(rt2x00dev, RT3071) ||
1908 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1909 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1910 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1911 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1912 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1913 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1914 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1915 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1916 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1917 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1918 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1919 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1920 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1921 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1922 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1923 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1924 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1925 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1926 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1927 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1928 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1929 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1930 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1931 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1932 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 1933 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 1934 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1935 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1936 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1937 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1938 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1939 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 1940 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 1941 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1942 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 1943 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 1944 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1945 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1946 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1947 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1948 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1949 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1950 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 1951 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 1952 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 1953 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 1954 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1955 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1956 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1957 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1958 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1959 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1960 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 1961 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 1962 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1963 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1964 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1965 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1966 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1967 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1968 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1969 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1970 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1971 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1972 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1973 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1974 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1975 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1976 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1977 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1978 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1979 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1980 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1981 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1982 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1983 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1984 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1985 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1986 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1987 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1988 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1989 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1990 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1991 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 1992 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1993 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1994 return 0;
8cdd15e0
GW		 1995 }
1996
1997 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1998 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1999 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2000 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2001 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2002 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2003 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2004 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2005 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2006 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2007
2008 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2009
2010 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2011 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2012 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2013 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2014 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2015 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2016 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2017 else
2018 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2019 }
2020 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2021 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2022 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2023 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2024 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2025 }
2026
2027 /*
2028 * Set RX Filter calibration for 20MHz and 40MHz
2029 */
8cdd15e0
GW		 2030 if (rt2x00_rt(rt2x00dev, RT3070)) {
2031 rt2x00dev->calibration[0] =
2032 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2033 rt2x00dev->calibration[1] =
2034 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2035 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2036 rt2x00_rt(rt2x00dev, RT3090) ||
2037 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2038 rt2x00dev->calibration[0] =
2039 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2040 rt2x00dev->calibration[1] =
2041 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2042 }
fcf51541
BZ		 2043
2044 /*
2045 * Set back to initial state
2046 */
2047 rt2800_bbp_write(rt2x00dev, 24, 0);
2048
2049 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2050 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2051 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2052
2053 /*
2054 * set BBP back to BW20
2055 */
2056 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2057 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2058 rt2800_bbp_write(rt2x00dev, 4, bbp);
2059
d5385bfc 2060 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2061 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2062 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2063 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2064 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2065
2066 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2067 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2068 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2069
2070 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2071 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2072 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2073 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2074 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 2075 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2076 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2077 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2078 }
8cdd15e0
GW		 2079 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2080 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2081 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2082 rt2x00_get_field16(eeprom,
2083 EEPROM_TXMIXER_GAIN_BG_VAL));
2084 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2085
64522957
GW		 2086 if (rt2x00_rt(rt2x00dev, RT3090)) {
2087 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2088
2089 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2090 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2091 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2092 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2093 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2094
2095 rt2800_bbp_write(rt2x00dev, 138, bbp);
2096 }
2097
2098 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2099 rt2x00_rt(rt2x00dev, RT3090) ||
2100 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2101 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2102 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2103 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2104 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2105 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2106 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2107 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2108
2109 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2110 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2111 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2112
2113 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2114 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2115 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2116
2117 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2118 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2119 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2120 }
2121
2122 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2123 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2124 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2125 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2126 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2127 else
2128 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2129 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2130 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2131 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2132 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2133 }
2134
fcf51541
BZ		 2135 return 0;
2136}
2137EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 2138
30e84034
BZ		 2139int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2140{
2141 u32 reg;
2142
2143 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2144
2145 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2146}
2147EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2148
2149static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2150{
2151 u32 reg;
2152
31a4cf1f
GW		 2153 mutex_lock(&rt2x00dev->csr_mutex);
2154
2155 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2156 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2157 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2158 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2159 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2160
2161 /* Wait until the EEPROM has been loaded */
2162 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2163
2164 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2165 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2166 (u32 *)&rt2x00dev->eeprom[i]);
2167 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2168 (u32 *)&rt2x00dev->eeprom[i + 2]);
2169 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2170 (u32 *)&rt2x00dev->eeprom[i + 4]);
2171 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2172 (u32 *)&rt2x00dev->eeprom[i + 6]);
2173
2174 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2175}
2176
2177void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2178{
2179 unsigned int i;
2180
2181 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2182 rt2800_efuse_read(rt2x00dev, i);
2183}
2184EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2185
38bd7b8a
BZ		 2186int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2187{
2188 u16 word;
2189 u8 *mac;
2190 u8 default_lna_gain;
2191
2192 /*
2193 * Start validation of the data that has been read.
2194 */
2195 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2196 if (!is_valid_ether_addr(mac)) {
2197 random_ether_addr(mac);
2198 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2199 }
2200
2201 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2202 if (word == 0xffff) {
2203 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2204 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2205 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2206 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2207 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2208 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2209 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2210 /*
2211 * There is a max of 2 RX streams for RT28x0 series
2212 */
2213 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2214 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2215 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2216 }
2217
2218 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2219 if (word == 0xffff) {
2220 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2221 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2222 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2223 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2224 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2225 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2226 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2227 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2228 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2229 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2230 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2231 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2232 }
2233
2234 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2235 if ((word & 0x00ff) == 0x00ff) {
2236 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2237 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2238 LED_MODE_TXRX_ACTIVITY);
2239 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2240 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2241 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2242 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2243 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2244 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2245 }
2246
2247 /*
2248 * During the LNA validation we are going to use
2249 * lna0 as correct value. Note that EEPROM_LNA
2250 * is never validated.
2251 */
2252 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2253 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2254
2255 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2256 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2257 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2258 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2259 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2260 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2261
2262 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2263 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2264 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2265 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2266 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2267 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2268 default_lna_gain);
2269 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2270
2271 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2272 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2273 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2274 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2275 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2276 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2277
2278 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2279 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2280 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2281 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2282 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2283 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2284 default_lna_gain);
2285 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2286
2287 return 0;
2288}
2289EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2290
2291int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2292{
2293 u32 reg;
2294 u16 value;
2295 u16 eeprom;
2296
2297 /*
2298 * Read EEPROM word for configuration.
2299 */
2300 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2301
2302 /*
2303 * Identify RF chipset.
2304 */
2305 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2306 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2307
49e721ec
GW		 2308 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2309 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2310
2311 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2312 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2313 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2314 !rt2x00_rt(rt2x00dev, RT3070) &&
2315 !rt2x00_rt(rt2x00dev, RT3071) &&
2316 !rt2x00_rt(rt2x00dev, RT3090) &&
2317 !rt2x00_rt(rt2x00dev, RT3390) &&
2318 !rt2x00_rt(rt2x00dev, RT3572)) {
2319 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2320 return -ENODEV;
f273fe55 2321 }
714fa663 2322
5122d898
GW		 2323 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2324 !rt2x00_rf(rt2x00dev, RF2850) &&
2325 !rt2x00_rf(rt2x00dev, RF2720) &&
2326 !rt2x00_rf(rt2x00dev, RF2750) &&
2327 !rt2x00_rf(rt2x00dev, RF3020) &&
2328 !rt2x00_rf(rt2x00dev, RF2020) &&
2329 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2330 !rt2x00_rf(rt2x00dev, RF3022) &&
2331 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2332 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2333 return -ENODEV;
2334 }
2335
2336 /*
2337 * Identify default antenna configuration.
2338 */
2339 rt2x00dev->default_ant.tx =
2340 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2341 rt2x00dev->default_ant.rx =
2342 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2343
2344 /*
2345 * Read frequency offset and RF programming sequence.
2346 */
2347 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2348 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2349
2350 /*
2351 * Read external LNA informations.
2352 */
2353 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2354
2355 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2356 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2357 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2358 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2359
2360 /*
2361 * Detect if this device has an hardware controlled radio.
2362 */
2363 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2364 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2365
2366 /*
2367 * Store led settings, for correct led behaviour.
2368 */
2369#ifdef CONFIG_RT2X00_LIB_LEDS
2370 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2371 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2372 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2373
2374 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2375#endif /* CONFIG_RT2X00_LIB_LEDS */
2376
2377 return 0;
2378}
2379EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2380
4da2933f 2381/*
55f9321a 2382 * RF value list for rt28xx
4da2933f
BZ		 2383 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2384 */
2385static const struct rf_channel rf_vals[] = {
2386 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2387 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2388 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2389 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2390 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2391 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2392 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2393 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2394 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2395 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2396 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2397 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2398 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2399 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2400
2401 /* 802.11 UNI / HyperLan 2 */
2402 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2403 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2404 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2405 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2406 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2407 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2408 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2409 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2410 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2411 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2412 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2413 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2414
2415 /* 802.11 HyperLan 2 */
2416 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2417 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2418 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2419 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2420 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2421 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2422 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2423 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2424 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2425 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2426 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2427 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2428 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2429 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2430 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2431 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2432
2433 /* 802.11 UNII */
2434 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2435 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2436 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2437 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2438 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2439 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2440 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2441 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2442 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2443 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2444 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2445
2446 /* 802.11 Japan */
2447 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2448 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2449 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2450 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2451 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2452 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2453 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2454};
2455
2456/*
55f9321a
ID		 2457 * RF value list for rt3xxx
2458 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2459 */
55f9321a 2460static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2461 {1, 241, 2, 2 },
2462 {2, 241, 2, 7 },
2463 {3, 242, 2, 2 },
2464 {4, 242, 2, 7 },
2465 {5, 243, 2, 2 },
2466 {6, 243, 2, 7 },
2467 {7, 244, 2, 2 },
2468 {8, 244, 2, 7 },
2469 {9, 245, 2, 2 },
2470 {10, 245, 2, 7 },
2471 {11, 246, 2, 2 },
2472 {12, 246, 2, 7 },
2473 {13, 247, 2, 2 },
2474 {14, 248, 2, 4 },
55f9321a
ID		 2475
2476 /* 802.11 UNI / HyperLan 2 */
2477 {36, 0x56, 0, 4},
2478 {38, 0x56, 0, 6},
2479 {40, 0x56, 0, 8},
2480 {44, 0x57, 0, 0},
2481 {46, 0x57, 0, 2},
2482 {48, 0x57, 0, 4},
2483 {52, 0x57, 0, 8},
2484 {54, 0x57, 0, 10},
2485 {56, 0x58, 0, 0},
2486 {60, 0x58, 0, 4},
2487 {62, 0x58, 0, 6},
2488 {64, 0x58, 0, 8},
2489
2490 /* 802.11 HyperLan 2 */
2491 {100, 0x5b, 0, 8},
2492 {102, 0x5b, 0, 10},
2493 {104, 0x5c, 0, 0},
2494 {108, 0x5c, 0, 4},
2495 {110, 0x5c, 0, 6},
2496 {112, 0x5c, 0, 8},
2497 {116, 0x5d, 0, 0},
2498 {118, 0x5d, 0, 2},
2499 {120, 0x5d, 0, 4},
2500 {124, 0x5d, 0, 8},
2501 {126, 0x5d, 0, 10},
2502 {128, 0x5e, 0, 0},
2503 {132, 0x5e, 0, 4},
2504 {134, 0x5e, 0, 6},
2505 {136, 0x5e, 0, 8},
2506 {140, 0x5f, 0, 0},
2507
2508 /* 802.11 UNII */
2509 {149, 0x5f, 0, 9},
2510 {151, 0x5f, 0, 11},
2511 {153, 0x60, 0, 1},
2512 {157, 0x60, 0, 5},
2513 {159, 0x60, 0, 7},
2514 {161, 0x60, 0, 9},
2515 {165, 0x61, 0, 1},
2516 {167, 0x61, 0, 3},
2517 {169, 0x61, 0, 5},
2518 {171, 0x61, 0, 7},
2519 {173, 0x61, 0, 9},
4da2933f
BZ		 2520};
2521
2522int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2523{
4da2933f
BZ		 2524 struct hw_mode_spec *spec = &rt2x00dev->spec;
2525 struct channel_info *info;
2526 char *tx_power1;
2527 char *tx_power2;
2528 unsigned int i;
2529 u16 eeprom;
2530
93b6bd26
GW		 2531 /*
2532 * Disable powersaving as default on PCI devices.
2533 */
cea90e55 2534 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2535 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2536
4da2933f
BZ		 2537 /*
2538 * Initialize all hw fields.
2539 */
2540 rt2x00dev->hw->flags =
2541 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2542 IEEE80211_HW_SIGNAL_DBM |
2543 IEEE80211_HW_SUPPORTS_PS |
2544 IEEE80211_HW_PS_NULLFUNC_STACK;
2545
4da2933f
BZ		 2546 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2547 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2548 rt2x00_eeprom_addr(rt2x00dev,
2549 EEPROM_MAC_ADDR_0));
2550
2551 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2552
2553 /*
2554 * Initialize hw_mode information.
2555 */
2556 spec->supported_bands = SUPPORT_BAND_2GHZ;
2557 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2558
5122d898 2559 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 2560 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 2561 spec->num_channels = 14;
2562 spec->channels = rf_vals;
55f9321a
ID		 2563 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2564 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2565 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2566 spec->num_channels = ARRAY_SIZE(rf_vals);
2567 spec->channels = rf_vals;
5122d898
GW		 2568 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2569 rt2x00_rf(rt2x00dev, RF2020) ||
2570 rt2x00_rf(rt2x00dev, RF3021) ||
2571 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 2572 spec->num_channels = 14;
2573 spec->channels = rf_vals_3x;
2574 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2575 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2576 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2577 spec->channels = rf_vals_3x;
4da2933f
BZ		 2578 }
2579
2580 /*
2581 * Initialize HT information.
2582 */
5122d898 2583 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2584 spec->ht.ht_supported = true;
2585 else
2586 spec->ht.ht_supported = false;
2587
2caaa5d3
HS		 2588 /*
2589 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2590 * reception problems with HT40 capable 11n APs
2591 */
4da2933f 2592 spec->ht.cap =
4da2933f
BZ		 2593 IEEE80211_HT_CAP_GRN_FLD |
2594 IEEE80211_HT_CAP_SGI_20 |
2595 IEEE80211_HT_CAP_SGI_40 |
2596 IEEE80211_HT_CAP_TX_STBC |
9a418af5 2597 IEEE80211_HT_CAP_RX_STBC;
4da2933f
BZ		 2598 spec->ht.ampdu_factor = 3;
2599 spec->ht.ampdu_density = 4;
2600 spec->ht.mcs.tx_params =
2601 IEEE80211_HT_MCS_TX_DEFINED |
2602 IEEE80211_HT_MCS_TX_RX_DIFF |
2603 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2604 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2605
2606 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2607 case 3:
2608 spec->ht.mcs.rx_mask[2] = 0xff;
2609 case 2:
2610 spec->ht.mcs.rx_mask[1] = 0xff;
2611 case 1:
2612 spec->ht.mcs.rx_mask[0] = 0xff;
2613 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2614 break;
2615 }
2616
2617 /*
2618 * Create channel information array
2619 */
2620 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2621 if (!info)
2622 return -ENOMEM;
2623
2624 spec->channels_info = info;
2625
2626 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2627 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2628
2629 for (i = 0; i < 14; i++) {
2630 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2631 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2632 }
2633
2634 if (spec->num_channels > 14) {
2635 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2636 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2637
2638 for (i = 14; i < spec->num_channels; i++) {
2639 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2640 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2641 }
2642 }
2643
2644 return 0;
2645}
2646EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2647
2ce33995
BZ		 2648/*
2649 * IEEE80211 stack callback functions.
2650 */
2651static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2652 u32 *iv32, u16 *iv16)
2653{
2654 struct rt2x00_dev *rt2x00dev = hw->priv;
2655 struct mac_iveiv_entry iveiv_entry;
2656 u32 offset;
2657
2658 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2659 rt2800_register_multiread(rt2x00dev, offset,
2660 &iveiv_entry, sizeof(iveiv_entry));
2661
855da5e0
JL		 2662 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2663 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2664}
2665
2666static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2667{
2668 struct rt2x00_dev *rt2x00dev = hw->priv;
2669 u32 reg;
2670 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2671
2672 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2673 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2674 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2675
2676 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2677 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2678 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2679
2680 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2682 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2683
2684 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2685 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2686 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2687
2688 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2689 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2690 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2691
2692 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2693 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2694 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2695
2696 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2697 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2698 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2699
2700 return 0;
2701}
2702
2703static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2704 const struct ieee80211_tx_queue_params *params)
2705{
2706 struct rt2x00_dev *rt2x00dev = hw->priv;
2707 struct data_queue *queue;
2708 struct rt2x00_field32 field;
2709 int retval;
2710 u32 reg;
2711 u32 offset;
2712
2713 /*
2714 * First pass the configuration through rt2x00lib, that will
2715 * update the queue settings and validate the input. After that
2716 * we are free to update the registers based on the value
2717 * in the queue parameter.
2718 */
2719 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2720 if (retval)
2721 return retval;
2722
2723 /*
2724 * We only need to perform additional register initialization
2725 * for WMM queues/
2726 */
2727 if (queue_idx >= 4)
2728 return 0;
2729
2730 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2731
2732 /* Update WMM TXOP register */
2733 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2734 field.bit_offset = (queue_idx & 1) * 16;
2735 field.bit_mask = 0xffff << field.bit_offset;
2736
2737 rt2800_register_read(rt2x00dev, offset, &reg);
2738 rt2x00_set_field32(&reg, field, queue->txop);
2739 rt2800_register_write(rt2x00dev, offset, reg);
2740
2741 /* Update WMM registers */
2742 field.bit_offset = queue_idx * 4;
2743 field.bit_mask = 0xf << field.bit_offset;
2744
2745 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2746 rt2x00_set_field32(&reg, field, queue->aifs);
2747 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2748
2749 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2750 rt2x00_set_field32(&reg, field, queue->cw_min);
2751 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2752
2753 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2754 rt2x00_set_field32(&reg, field, queue->cw_max);
2755 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2756
2757 /* Update EDCA registers */
2758 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2759
2760 rt2800_register_read(rt2x00dev, offset, &reg);
2761 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2762 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2763 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2764 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2765 rt2800_register_write(rt2x00dev, offset, reg);
2766
2767 return 0;
2768}
2769
2770static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2771{
2772 struct rt2x00_dev *rt2x00dev = hw->priv;
2773 u64 tsf;
2774 u32 reg;
2775
2776 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2777 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2778 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2779 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2780
2781 return tsf;
2782}
2783
2784const struct ieee80211_ops rt2800_mac80211_ops = {
2785 .tx = rt2x00mac_tx,
2786 .start = rt2x00mac_start,
2787 .stop = rt2x00mac_stop,
2788 .add_interface = rt2x00mac_add_interface,
2789 .remove_interface = rt2x00mac_remove_interface,
2790 .config = rt2x00mac_config,
2791 .configure_filter = rt2x00mac_configure_filter,
2792 .set_tim = rt2x00mac_set_tim,
2793 .set_key = rt2x00mac_set_key,
2794 .get_stats = rt2x00mac_get_stats,
2795 .get_tkip_seq = rt2800_get_tkip_seq,
2796 .set_rts_threshold = rt2800_set_rts_threshold,
2797 .bss_info_changed = rt2x00mac_bss_info_changed,
2798 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2799 .get_tsf = rt2800_get_tsf,
2800 .rfkill_poll = rt2x00mac_rfkill_poll,
2801};
2802EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
Ubuntu Jammy Linux kernel mirror