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rt2x00: Add rt2800_wait_csr_ready
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
387 /*
388 * Wait for stable hardware.
389 */
5ffddc49 390 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 391 return -EBUSY;
f31c9a8c
ID		 392
393 if (rt2x00_is_pci(rt2x00dev))
394 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
395
396 /*
397 * Disable DMA, will be reenabled later when enabling
398 * the radio.
399 */
400 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
401 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
402 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
403 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
404 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
405 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
406 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
407
408 /*
409 * Write firmware to the device.
410 */
411 rt2800_drv_write_firmware(rt2x00dev, data, len);
412
413 /*
414 * Wait for device to stabilize.
415 */
416 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
417 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
418 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
419 break;
420 msleep(1);
421 }
422
423 if (i == REGISTER_BUSY_COUNT) {
424 ERROR(rt2x00dev, "PBF system register not ready.\n");
425 return -EBUSY;
426 }
427
428 /*
429 * Initialize firmware.
430 */
431 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
432 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
433 msleep(1);
434
435 return 0;
436}
437EXPORT_SYMBOL_GPL(rt2800_load_firmware);
438
0c5879bc
ID		 439void rt2800_write_tx_data(struct queue_entry *entry,
440 struct txentry_desc *txdesc)
59679b91 441{
0c5879bc 442 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 443 u32 word;
444
445 /*
446 * Initialize TX Info descriptor
447 */
448 rt2x00_desc_read(txwi, 0, &word);
449 rt2x00_set_field32(&word, TXWI_W0_FRAG,
450 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 451 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
452 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 453 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
454 rt2x00_set_field32(&word, TXWI_W0_TS,
455 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
456 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
457 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
458 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
459 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
460 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
461 rt2x00_set_field32(&word, TXWI_W0_BW,
462 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
463 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
464 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
465 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
466 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
467 rt2x00_desc_write(txwi, 0, word);
468
469 rt2x00_desc_read(txwi, 1, &word);
470 rt2x00_set_field32(&word, TXWI_W1_ACK,
471 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
472 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
473 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
474 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
475 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
476 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
477 txdesc->key_idx : 0xff);
478 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
479 txdesc->length);
a908a743 480 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
59679b91
GW		 481 rt2x00_desc_write(txwi, 1, word);
482
483 /*
484 * Always write 0 to IV/EIV fields, hardware will insert the IV
485 * from the IVEIV register when TXD_W3_WIV is set to 0.
486 * When TXD_W3_WIV is set to 1 it will use the IV data
487 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
488 * crypto entry in the registers should be used to encrypt the frame.
489 */
490 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
491 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
492}
0c5879bc 493EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 494
74861922 495static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 496{
74861922
ID		 497 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
498 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
499 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
500 u16 eeprom;
501 u8 offset0;
502 u8 offset1;
503 u8 offset2;
504
e5ef5bad 505 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 506 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
507 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
508 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
509 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
510 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
511 } else {
512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
513 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
514 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
515 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
516 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
517 }
518
519 /*
520 * Convert the value from the descriptor into the RSSI value
521 * If the value in the descriptor is 0, it is considered invalid
522 * and the default (extremely low) rssi value is assumed
523 */
524 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
525 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
526 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
527
528 /*
529 * mac80211 only accepts a single RSSI value. Calculating the
530 * average doesn't deliver a fair answer either since -60:-60 would
531 * be considered equally good as -50:-70 while the second is the one
532 * which gives less energy...
533 */
534 rssi0 = max(rssi0, rssi1);
535 return max(rssi0, rssi2);
536}
537
538void rt2800_process_rxwi(struct queue_entry *entry,
539 struct rxdone_entry_desc *rxdesc)
540{
541 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 542 u32 word;
543
544 rt2x00_desc_read(rxwi, 0, &word);
545
546 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
547 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
548
549 rt2x00_desc_read(rxwi, 1, &word);
550
551 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
552 rxdesc->flags |= RX_FLAG_SHORT_GI;
553
554 if (rt2x00_get_field32(word, RXWI_W1_BW))
555 rxdesc->flags |= RX_FLAG_40MHZ;
556
557 /*
558 * Detect RX rate, always use MCS as signal type.
559 */
560 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
561 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
562 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
563
564 /*
565 * Mask of 0x8 bit to remove the short preamble flag.
566 */
567 if (rxdesc->rate_mode == RATE_MODE_CCK)
568 rxdesc->signal &= ~0x8;
569
570 rt2x00_desc_read(rxwi, 2, &word);
571
74861922
ID		 572 /*
573 * Convert descriptor AGC value to RSSI value.
574 */
575 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 576
577 /*
578 * Remove RXWI descriptor from start of buffer.
579 */
74861922 580 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 581}
582EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
583
96481b20
ID		 584void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
585{
586 struct data_queue *queue;
587 struct queue_entry *entry;
588 __le32 *txwi;
589 struct txdone_entry_desc txdesc;
590 u32 word;
591 u32 reg;
592 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
593 u16 mcs, real_mcs;
594 int i;
595
596 /*
597 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
598 * at most X times and also stop processing once the TX_STA_FIFO_VALID
599 * flag is not set anymore.
600 *
601 * The legacy drivers use X=TX_RING_SIZE but state in a comment
602 * that the TX_STA_FIFO stack has a size of 16. We stick to our
603 * tx ring size for now.
604 */
605 for (i = 0; i < TX_ENTRIES; i++) {
606 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
607 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
608 break;
609
610 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614 /*
615 * Skip this entry when it contains an invalid
616 * queue identication number.
617 */
618 if (pid <= 0 || pid > QID_RX)
619 continue;
620
621 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
622 if (unlikely(!queue))
623 continue;
624
625 /*
626 * Inside each queue, we process each entry in a chronological
627 * order. We first check that the queue is not empty.
628 */
629 entry = NULL;
630 while (!rt2x00queue_empty(queue)) {
631 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
632 if (!test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
633 break;
634
635 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
636 }
637
638 if (!entry || rt2x00queue_empty(queue))
639 break;
640
641 /*
642 * Check if we got a match by looking at WCID/ACK/PID
643 * fields
644 */
645 txwi = rt2800_drv_get_txwi(entry);
646
647 rt2x00_desc_read(txwi, 1, &word);
648 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
649 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
650 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
651
652 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
653 WARNING(rt2x00dev, "invalid TX_STA_FIFO content");
654
655 /*
656 * Obtain the status about this packet.
657 */
658 txdesc.flags = 0;
659 rt2x00_desc_read(txwi, 0, &word);
660 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
96481b20
ID		 661 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
662
663 /*
664 * Ralink has a retry mechanism using a global fallback
665 * table. We setup this fallback table to try the immediate
666 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
667 * always contains the MCS used for the last transmission, be
668 * it successful or not.
669 */
670 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
671 /*
672 * Transmission succeeded. The number of retries is
673 * mcs - real_mcs
674 */
675 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
676 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
677 } else {
678 /*
679 * Transmission failed. The number of retries is
680 * always 7 in this case (for a total number of 8
681 * frames sent).
682 */
683 __set_bit(TXDONE_FAILURE, &txdesc.flags);
684 txdesc.retry = rt2x00dev->long_retry;
685 }
686
687 /*
688 * the frame was retried at least once
689 * -> hw used fallback rates
690 */
691 if (txdesc.retry)
692 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
693
694 rt2x00lib_txdone(entry, &txdesc);
695 }
696}
697EXPORT_SYMBOL_GPL(rt2800_txdone);
698
f0194b2d
GW		 699void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
700{
701 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
702 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
703 unsigned int beacon_base;
704 u32 reg;
705
706 /*
707 * Disable beaconing while we are reloading the beacon data,
708 * otherwise we might be sending out invalid data.
709 */
710 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
712 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
713
714 /*
715 * Add space for the TXWI in front of the skb.
716 */
717 skb_push(entry->skb, TXWI_DESC_SIZE);
718 memset(entry->skb, 0, TXWI_DESC_SIZE);
719
720 /*
721 * Register descriptor details in skb frame descriptor.
722 */
723 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
724 skbdesc->desc = entry->skb->data;
725 skbdesc->desc_len = TXWI_DESC_SIZE;
726
727 /*
728 * Add the TXWI for the beacon to the skb.
729 */
0c5879bc 730 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 731
732 /*
733 * Dump beacon to userspace through debugfs.
734 */
735 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
736
737 /*
738 * Write entire beacon with TXWI to register.
739 */
740 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
741 rt2800_register_multiwrite(rt2x00dev, beacon_base,
742 entry->skb->data, entry->skb->len);
743
744 /*
745 * Enable beaconing again.
746 */
747 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
748 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
749 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
750 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
751
752 /*
753 * Clean up beacon skb.
754 */
755 dev_kfree_skb_any(entry->skb);
756 entry->skb = NULL;
757}
50e888ea 758EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 759
fdb87251
HS		 760static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
761 unsigned int beacon_base)
762{
763 int i;
764
765 /*
766 * For the Beacon base registers we only need to clear
767 * the whole TXWI which (when set to 0) will invalidate
768 * the entire beacon.
769 */
770 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
771 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
772}
773
f4450616
BZ		 774#ifdef CONFIG_RT2X00_LIB_DEBUGFS
775const struct rt2x00debug rt2800_rt2x00debug = {
776 .owner = THIS_MODULE,
777 .csr = {
778 .read = rt2800_register_read,
779 .write = rt2800_register_write,
780 .flags = RT2X00DEBUGFS_OFFSET,
781 .word_base = CSR_REG_BASE,
782 .word_size = sizeof(u32),
783 .word_count = CSR_REG_SIZE / sizeof(u32),
784 },
785 .eeprom = {
786 .read = rt2x00_eeprom_read,
787 .write = rt2x00_eeprom_write,
788 .word_base = EEPROM_BASE,
789 .word_size = sizeof(u16),
790 .word_count = EEPROM_SIZE / sizeof(u16),
791 },
792 .bbp = {
793 .read = rt2800_bbp_read,
794 .write = rt2800_bbp_write,
795 .word_base = BBP_BASE,
796 .word_size = sizeof(u8),
797 .word_count = BBP_SIZE / sizeof(u8),
798 },
799 .rf = {
800 .read = rt2x00_rf_read,
801 .write = rt2800_rf_write,
802 .word_base = RF_BASE,
803 .word_size = sizeof(u32),
804 .word_count = RF_SIZE / sizeof(u32),
805 },
806};
807EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
808#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
809
810int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
811{
812 u32 reg;
813
814 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
815 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
816}
817EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
818
819#ifdef CONFIG_RT2X00_LIB_LEDS
820static void rt2800_brightness_set(struct led_classdev *led_cdev,
821 enum led_brightness brightness)
822{
823 struct rt2x00_led *led =
824 container_of(led_cdev, struct rt2x00_led, led_dev);
825 unsigned int enabled = brightness != LED_OFF;
826 unsigned int bg_mode =
827 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
828 unsigned int polarity =
829 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
830 EEPROM_FREQ_LED_POLARITY);
831 unsigned int ledmode =
832 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
833 EEPROM_FREQ_LED_MODE);
834
835 if (led->type == LED_TYPE_RADIO) {
836 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
837 enabled ? 0x20 : 0);
838 } else if (led->type == LED_TYPE_ASSOC) {
839 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
840 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
841 } else if (led->type == LED_TYPE_QUALITY) {
842 /*
843 * The brightness is divided into 6 levels (0 - 5),
844 * The specs tell us the following levels:
845 * 0, 1 ,3, 7, 15, 31
846 * to determine the level in a simple way we can simply
847 * work with bitshifting:
848 * (1 << level) - 1
849 */
850 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
851 (1 << brightness / (LED_FULL / 6)) - 1,
852 polarity);
853 }
854}
855
856static int rt2800_blink_set(struct led_classdev *led_cdev,
857 unsigned long *delay_on, unsigned long *delay_off)
858{
859 struct rt2x00_led *led =
860 container_of(led_cdev, struct rt2x00_led, led_dev);
861 u32 reg;
862
863 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
864 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
865 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 866 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
867
868 return 0;
869}
870
b3579d6a 871static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 872 struct rt2x00_led *led, enum led_type type)
873{
874 led->rt2x00dev = rt2x00dev;
875 led->type = type;
876 led->led_dev.brightness_set = rt2800_brightness_set;
877 led->led_dev.blink_set = rt2800_blink_set;
878 led->flags = LED_INITIALIZED;
879}
f4450616
BZ		 880#endif /* CONFIG_RT2X00_LIB_LEDS */
881
882/*
883 * Configuration handlers.
884 */
885static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
886 struct rt2x00lib_crypto *crypto,
887 struct ieee80211_key_conf *key)
888{
889 struct mac_wcid_entry wcid_entry;
890 struct mac_iveiv_entry iveiv_entry;
891 u32 offset;
892 u32 reg;
893
894 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
895
e4a0ab34
ID		 896 if (crypto->cmd == SET_KEY) {
897 rt2800_register_read(rt2x00dev, offset, &reg);
898 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
899 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
900 /*
901 * Both the cipher as the BSS Idx numbers are split in a main
902 * value of 3 bits, and a extended field for adding one additional
903 * bit to the value.
904 */
905 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
906 (crypto->cipher & 0x7));
907 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
908 (crypto->cipher & 0x8) >> 3);
909 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
910 (crypto->bssidx & 0x7));
911 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
912 (crypto->bssidx & 0x8) >> 3);
913 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
914 rt2800_register_write(rt2x00dev, offset, reg);
915 } else {
916 rt2800_register_write(rt2x00dev, offset, 0);
917 }
f4450616
BZ		 918
919 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
920
921 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
922 if ((crypto->cipher == CIPHER_TKIP) ||
923 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
924 (crypto->cipher == CIPHER_AES))
925 iveiv_entry.iv[3] |= 0x20;
926 iveiv_entry.iv[3] |= key->keyidx << 6;
927 rt2800_register_multiwrite(rt2x00dev, offset,
928 &iveiv_entry, sizeof(iveiv_entry));
929
930 offset = MAC_WCID_ENTRY(key->hw_key_idx);
931
932 memset(&wcid_entry, 0, sizeof(wcid_entry));
933 if (crypto->cmd == SET_KEY)
934 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
935 rt2800_register_multiwrite(rt2x00dev, offset,
936 &wcid_entry, sizeof(wcid_entry));
937}
938
939int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
940 struct rt2x00lib_crypto *crypto,
941 struct ieee80211_key_conf *key)
942{
943 struct hw_key_entry key_entry;
944 struct rt2x00_field32 field;
945 u32 offset;
946 u32 reg;
947
948 if (crypto->cmd == SET_KEY) {
949 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
950
951 memcpy(key_entry.key, crypto->key,
952 sizeof(key_entry.key));
953 memcpy(key_entry.tx_mic, crypto->tx_mic,
954 sizeof(key_entry.tx_mic));
955 memcpy(key_entry.rx_mic, crypto->rx_mic,
956 sizeof(key_entry.rx_mic));
957
958 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
959 rt2800_register_multiwrite(rt2x00dev, offset,
960 &key_entry, sizeof(key_entry));
961 }
962
963 /*
964 * The cipher types are stored over multiple registers
965 * starting with SHARED_KEY_MODE_BASE each word will have
966 * 32 bits and contains the cipher types for 2 bssidx each.
967 * Using the correct defines correctly will cause overhead,
968 * so just calculate the correct offset.
969 */
970 field.bit_offset = 4 * (key->hw_key_idx % 8);
971 field.bit_mask = 0x7 << field.bit_offset;
972
973 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
974
975 rt2800_register_read(rt2x00dev, offset, &reg);
976 rt2x00_set_field32(&reg, field,
977 (crypto->cmd == SET_KEY) * crypto->cipher);
978 rt2800_register_write(rt2x00dev, offset, reg);
979
980 /*
981 * Update WCID information
982 */
983 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
984
985 return 0;
986}
987EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
988
989int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
990 struct rt2x00lib_crypto *crypto,
991 struct ieee80211_key_conf *key)
992{
993 struct hw_key_entry key_entry;
994 u32 offset;
995
996 if (crypto->cmd == SET_KEY) {
997 /*
998 * 1 pairwise key is possible per AID, this means that the AID
999 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1000 * last possible shared key entry.
1001 */
1002 if (crypto->aid > (256 - 32))
1003 return -ENOSPC;
1004
1005 key->hw_key_idx = 32 + crypto->aid;
1006
1007 memcpy(key_entry.key, crypto->key,
1008 sizeof(key_entry.key));
1009 memcpy(key_entry.tx_mic, crypto->tx_mic,
1010 sizeof(key_entry.tx_mic));
1011 memcpy(key_entry.rx_mic, crypto->rx_mic,
1012 sizeof(key_entry.rx_mic));
1013
1014 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1015 rt2800_register_multiwrite(rt2x00dev, offset,
1016 &key_entry, sizeof(key_entry));
1017 }
1018
1019 /*
1020 * Update WCID information
1021 */
1022 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1023
1024 return 0;
1025}
1026EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1027
1028void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1029 const unsigned int filter_flags)
1030{
1031 u32 reg;
1032
1033 /*
1034 * Start configuration steps.
1035 * Note that the version error will always be dropped
1036 * and broadcast frames will always be accepted since
1037 * there is no filter for it at this time.
1038 */
1039 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1040 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1041 !(filter_flags & FIF_FCSFAIL));
1042 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1043 !(filter_flags & FIF_PLCPFAIL));
1044 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1045 !(filter_flags & FIF_PROMISC_IN_BSS));
1046 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1047 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1048 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1049 !(filter_flags & FIF_ALLMULTI));
1050 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1051 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1052 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1053 !(filter_flags & FIF_CONTROL));
1054 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1055 !(filter_flags & FIF_CONTROL));
1056 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1057 !(filter_flags & FIF_CONTROL));
1058 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1059 !(filter_flags & FIF_CONTROL));
1060 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1061 !(filter_flags & FIF_CONTROL));
1062 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1063 !(filter_flags & FIF_PSPOLL));
1064 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1065 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1066 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1067 !(filter_flags & FIF_CONTROL));
1068 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1069}
1070EXPORT_SYMBOL_GPL(rt2800_config_filter);
1071
1072void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1073 struct rt2x00intf_conf *conf, const unsigned int flags)
1074{
f4450616
BZ		 1075 u32 reg;
1076
1077 if (flags & CONFIG_UPDATE_TYPE) {
1078 /*
1079 * Clear current synchronisation setup.
f4450616 1080 */
fdb87251
HS		 1081 rt2800_clear_beacon(rt2x00dev,
1082 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1083 /*
1084 * Enable synchronisation.
1085 */
1086 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1087 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1088 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1090 (conf->sync == TSF_SYNC_ADHOC ||
1091 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1092 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1093
1094 /*
1095 * Enable pre tbtt interrupt for beaconing modes
1096 */
1097 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1098 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1099 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1100 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1101
f4450616
BZ		 1102 }
1103
1104 if (flags & CONFIG_UPDATE_MAC) {
1105 reg = le32_to_cpu(conf->mac[1]);
1106 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1107 conf->mac[1] = cpu_to_le32(reg);
1108
1109 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1110 conf->mac, sizeof(conf->mac));
1111 }
1112
1113 if (flags & CONFIG_UPDATE_BSSID) {
1114 reg = le32_to_cpu(conf->bssid[1]);
d440cb9e
ID		 1115 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1116 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
f4450616
BZ		 1117 conf->bssid[1] = cpu_to_le32(reg);
1118
1119 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1120 conf->bssid, sizeof(conf->bssid));
1121 }
1122}
1123EXPORT_SYMBOL_GPL(rt2800_config_intf);
1124
1125void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
1126{
1127 u32 reg;
1128
f4450616
BZ		 1129 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1130 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1131 !!erp->short_preamble);
1132 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1133 !!erp->short_preamble);
1134 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1135
1136 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1137 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1138 erp->cts_protection ? 2 : 0);
1139 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1140
1141 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1142 erp->basic_rates);
1143 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1144
1145 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1146 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 1147 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1148
1149 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 1150 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 1151 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1152
1153 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1154 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1155 erp->beacon_int * 16);
1156 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1157}
1158EXPORT_SYMBOL_GPL(rt2800_config_erp);
1159
1160void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1161{
1162 u8 r1;
1163 u8 r3;
1164
1165 rt2800_bbp_read(rt2x00dev, 1, &r1);
1166 rt2800_bbp_read(rt2x00dev, 3, &r3);
1167
1168 /*
1169 * Configure the TX antenna.
1170 */
1171 switch ((int)ant->tx) {
1172 case 1:
1173 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1174 break;
1175 case 2:
1176 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1177 break;
1178 case 3:
e22557f2 1179 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1180 break;
1181 }
1182
1183 /*
1184 * Configure the RX antenna.
1185 */
1186 switch ((int)ant->rx) {
1187 case 1:
1188 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1189 break;
1190 case 2:
1191 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1192 break;
1193 case 3:
1194 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1195 break;
1196 }
1197
1198 rt2800_bbp_write(rt2x00dev, 3, r3);
1199 rt2800_bbp_write(rt2x00dev, 1, r1);
1200}
1201EXPORT_SYMBOL_GPL(rt2800_config_ant);
1202
1203static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1204 struct rt2x00lib_conf *libconf)
1205{
1206 u16 eeprom;
1207 short lna_gain;
1208
1209 if (libconf->rf.channel <= 14) {
1210 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1211 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1212 } else if (libconf->rf.channel <= 64) {
1213 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1214 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1215 } else if (libconf->rf.channel <= 128) {
1216 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1217 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1218 } else {
1219 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1220 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1221 }
1222
1223 rt2x00dev->lna_gain = lna_gain;
1224}
1225
06855ef4
GW		 1226static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1227 struct ieee80211_conf *conf,
1228 struct rf_channel *rf,
1229 struct channel_info *info)
f4450616
BZ		 1230{
1231 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1232
1233 if (rt2x00dev->default_ant.tx == 1)
1234 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1235
1236 if (rt2x00dev->default_ant.rx == 1) {
1237 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1238 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1239 } else if (rt2x00dev->default_ant.rx == 2)
1240 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1241
1242 if (rf->channel > 14) {
1243 /*
1244 * When TX power is below 0, we should increase it by 7 to
1245 * make it a positive value (Minumum value is -7).
1246 * However this means that values between 0 and 7 have
1247 * double meaning, and we should set a 7DBm boost flag.
1248 */
1249 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1250 (info->default_power1 >= 0));
f4450616 1251
8d1331b3
ID		 1252 if (info->default_power1 < 0)
1253 info->default_power1 += 7;
f4450616 1254
8d1331b3 1255 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1256
1257 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1258 (info->default_power2 >= 0));
f4450616 1259
8d1331b3
ID		 1260 if (info->default_power2 < 0)
1261 info->default_power2 += 7;
f4450616 1262
8d1331b3 1263 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1264 } else {
8d1331b3
ID		 1265 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1266 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1267 }
1268
1269 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1270
1271 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1272 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1273 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1274 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1275
1276 udelay(200);
1277
1278 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1279 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1280 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1281 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1282
1283 udelay(200);
1284
1285 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1286 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1287 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1288 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1289}
1290
06855ef4
GW		 1291static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1292 struct ieee80211_conf *conf,
1293 struct rf_channel *rf,
1294 struct channel_info *info)
f4450616
BZ		 1295{
1296 u8 rfcsr;
1297
1298 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1299 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1300
1301 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1302 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1303 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1304
1305 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1306 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1307 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1308
5a673964 1309 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1310 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1311 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1312
f4450616
BZ		 1313 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1314 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1315 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1316
1317 rt2800_rfcsr_write(rt2x00dev, 24,
1318 rt2x00dev->calibration[conf_is_ht40(conf)]);
1319
71976907 1320 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1321 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1322 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1323}
1324
1325static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1326 struct ieee80211_conf *conf,
1327 struct rf_channel *rf,
1328 struct channel_info *info)
1329{
1330 u32 reg;
1331 unsigned int tx_pin;
1332 u8 bbp;
1333
46323e11 1334 if (rf->channel <= 14) {
8d1331b3
ID		 1335 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1336 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1337 } else {
8d1331b3
ID		 1338 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1339 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1340 }
1341
06855ef4
GW		 1342 if (rt2x00_rf(rt2x00dev, RF2020) ||
1343 rt2x00_rf(rt2x00dev, RF3020) ||
1344 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1345 rt2x00_rf(rt2x00dev, RF3022) ||
1346 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1347 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1348 else
06855ef4 1349 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1350
1351 /*
1352 * Change BBP settings
1353 */
1354 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1355 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1356 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1357 rt2800_bbp_write(rt2x00dev, 86, 0);
1358
1359 if (rf->channel <= 14) {
1360 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1361 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1362 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1363 } else {
1364 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1365 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1366 }
1367 } else {
1368 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1369
1370 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1371 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1372 else
1373 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1374 }
1375
1376 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1377 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1378 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1379 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1380 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1381
1382 tx_pin = 0;
1383
1384 /* Turn on unused PA or LNA when not using 1T or 1R */
1385 if (rt2x00dev->default_ant.tx != 1) {
1386 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1387 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1388 }
1389
1390 /* Turn on unused PA or LNA when not using 1T or 1R */
1391 if (rt2x00dev->default_ant.rx != 1) {
1392 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1393 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1394 }
1395
1396 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1397 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1398 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1399 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1400 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1401 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1402
1403 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1404
1405 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1406 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1407 rt2800_bbp_write(rt2x00dev, 4, bbp);
1408
1409 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1410 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1411 rt2800_bbp_write(rt2x00dev, 3, bbp);
1412
8d0c9b65 1413 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1414 if (conf_is_ht40(conf)) {
1415 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1416 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1417 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1418 } else {
1419 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1420 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1421 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1422 }
1423 }
1424
1425 msleep(1);
1426}
1427
1428static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1429 const int max_txpower)
f4450616 1430{
5e846004
HS		 1431 u8 txpower;
1432 u8 max_value = (u8)max_txpower;
1433 u16 eeprom;
1434 int i;
f4450616 1435 u32 reg;
f4450616 1436 u8 r1;
5e846004 1437 u32 offset;
f4450616 1438
5e846004
HS		 1439 /*
1440 * set to normal tx power mode: +/- 0dBm
1441 */
f4450616 1442 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1443 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1444 rt2800_bbp_write(rt2x00dev, 1, r1);
1445
5e846004
HS		 1446 /*
1447 * The eeprom contains the tx power values for each rate. These
1448 * values map to 100% tx power. Each 16bit word contains four tx
1449 * power values and the order is the same as used in the TX_PWR_CFG
1450 * registers.
1451 */
1452 offset = TX_PWR_CFG_0;
1453
1454 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1455 /* just to be safe */
1456 if (offset > TX_PWR_CFG_4)
1457 break;
1458
1459 rt2800_register_read(rt2x00dev, offset, &reg);
1460
1461 /* read the next four txpower values */
1462 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1463 &eeprom);
1464
1465 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1466 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1467 * TX_PWR_CFG_4: unknown */
1468 txpower = rt2x00_get_field16(eeprom,
1469 EEPROM_TXPOWER_BYRATE_RATE0);
1470 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1471 min(txpower, max_value));
1472
1473 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1474 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1475 * TX_PWR_CFG_4: unknown */
1476 txpower = rt2x00_get_field16(eeprom,
1477 EEPROM_TXPOWER_BYRATE_RATE1);
1478 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1479 min(txpower, max_value));
1480
1481 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1482 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1483 * TX_PWR_CFG_4: unknown */
1484 txpower = rt2x00_get_field16(eeprom,
1485 EEPROM_TXPOWER_BYRATE_RATE2);
1486 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1487 min(txpower, max_value));
1488
1489 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1490 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1491 * TX_PWR_CFG_4: unknown */
1492 txpower = rt2x00_get_field16(eeprom,
1493 EEPROM_TXPOWER_BYRATE_RATE3);
1494 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1495 min(txpower, max_value));
1496
1497 /* read the next four txpower values */
1498 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1499 &eeprom);
1500
1501 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1502 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1503 * TX_PWR_CFG_4: unknown */
1504 txpower = rt2x00_get_field16(eeprom,
1505 EEPROM_TXPOWER_BYRATE_RATE0);
1506 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1507 min(txpower, max_value));
1508
1509 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1510 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1511 * TX_PWR_CFG_4: unknown */
1512 txpower = rt2x00_get_field16(eeprom,
1513 EEPROM_TXPOWER_BYRATE_RATE1);
1514 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1515 min(txpower, max_value));
1516
1517 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1518 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1519 * TX_PWR_CFG_4: unknown */
1520 txpower = rt2x00_get_field16(eeprom,
1521 EEPROM_TXPOWER_BYRATE_RATE2);
1522 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1523 min(txpower, max_value));
1524
1525 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1526 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1527 * TX_PWR_CFG_4: unknown */
1528 txpower = rt2x00_get_field16(eeprom,
1529 EEPROM_TXPOWER_BYRATE_RATE3);
1530 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1531 min(txpower, max_value));
1532
1533 rt2800_register_write(rt2x00dev, offset, reg);
1534
1535 /* next TX_PWR_CFG register */
1536 offset += 4;
1537 }
f4450616
BZ		 1538}
1539
1540static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1541 struct rt2x00lib_conf *libconf)
1542{
1543 u32 reg;
1544
1545 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1546 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1547 libconf->conf->short_frame_max_tx_count);
1548 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1549 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1550 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1551}
1552
1553static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1554 struct rt2x00lib_conf *libconf)
1555{
1556 enum dev_state state =
1557 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1558 STATE_SLEEP : STATE_AWAKE;
1559 u32 reg;
1560
1561 if (state == STATE_SLEEP) {
1562 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1563
1564 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1565 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1566 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1567 libconf->conf->listen_interval - 1);
1568 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1569 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1570
1571 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1572 } else {
f4450616
BZ		 1573 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1574 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1575 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1576 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1577 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1578
1579 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1580 }
1581}
1582
1583void rt2800_config(struct rt2x00_dev *rt2x00dev,
1584 struct rt2x00lib_conf *libconf,
1585 const unsigned int flags)
1586{
1587 /* Always recalculate LNA gain before changing configuration */
1588 rt2800_config_lna_gain(rt2x00dev, libconf);
1589
1590 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1591 rt2800_config_channel(rt2x00dev, libconf->conf,
1592 &libconf->rf, &libconf->channel);
1593 if (flags & IEEE80211_CONF_CHANGE_POWER)
1594 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1595 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1596 rt2800_config_retry_limit(rt2x00dev, libconf);
1597 if (flags & IEEE80211_CONF_CHANGE_PS)
1598 rt2800_config_ps(rt2x00dev, libconf);
1599}
1600EXPORT_SYMBOL_GPL(rt2800_config);
1601
1602/*
1603 * Link tuning
1604 */
1605void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1606{
1607 u32 reg;
1608
1609 /*
1610 * Update FCS error count from register.
1611 */
1612 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1613 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1614}
1615EXPORT_SYMBOL_GPL(rt2800_link_stats);
1616
1617static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1618{
1619 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1620 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1621 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1622 rt2x00_rt(rt2x00dev, RT3090) ||
1623 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1624 return 0x1c + (2 * rt2x00dev->lna_gain);
1625 else
1626 return 0x2e + rt2x00dev->lna_gain;
1627 }
1628
1629 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1630 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1631 else
1632 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1633}
1634
1635static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1636 struct link_qual *qual, u8 vgc_level)
1637{
1638 if (qual->vgc_level != vgc_level) {
1639 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1640 qual->vgc_level = vgc_level;
1641 qual->vgc_level_reg = vgc_level;
1642 }
1643}
1644
1645void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1646{
1647 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1648}
1649EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1650
1651void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1652 const u32 count)
1653{
8d0c9b65 1654 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1655 return;
1656
1657 /*
1658 * When RSSI is better then -80 increase VGC level with 0x10
1659 */
1660 rt2800_set_vgc(rt2x00dev, qual,
1661 rt2800_get_default_vgc(rt2x00dev) +
1662 ((qual->rssi > -80) * 0x10));
1663}
1664EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1665
1666/*
1667 * Initialization functions.
1668 */
b9a07ae9 1669static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1670{
1671 u32 reg;
d5385bfc 1672 u16 eeprom;
fcf51541 1673 unsigned int i;
e3a896b9 1674 int ret;
fcf51541 1675
a9dce149
GW		 1676 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1677 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1678 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1679 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1680 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1681 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1682 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1683
e3a896b9
GW		 1684 ret = rt2800_drv_init_registers(rt2x00dev);
1685 if (ret)
1686 return ret;
fcf51541
BZ		 1687
1688 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1689 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1690 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1691 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1692 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1693 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1694
1695 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1696 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1697 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1698 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1699 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1700 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1701
1702 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1703 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1704
1705 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1706
1707 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1708 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1709 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1710 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1711 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1712 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1713 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1714 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1715
a9dce149
GW		 1716 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1717
1718 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1719 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1720 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1721 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1722
64522957 1723 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1724 rt2x00_rt(rt2x00dev, RT3090) ||
1725 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1726 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1727 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1728 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1729 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1730 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1731 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1732 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1733 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1734 0x0000002c);
1735 else
1736 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1737 0x0000000f);
1738 } else {
1739 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1740 }
d5385bfc 1741 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1742 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1743
1744 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1745 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1746 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1747 } else {
1748 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1749 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1750 }
c295a81d
HS		 1751 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1752 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1753 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1754 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1755 } else {
1756 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1757 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1758 }
1759
1760 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1761 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1762 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1763 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1764 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1765 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1766 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1767 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1768 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1769 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1770
1771 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1772 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1773 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1774 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1775 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1776
1777 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1778 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1779 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1780 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1781 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1782 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1783 else
1784 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1785 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1786 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1787 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1788
a9dce149
GW		 1789 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1790 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1791 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1792 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1793 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1794 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1795 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1796 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1797 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1798
fcf51541
BZ		 1799 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1800
a9dce149
GW		 1801 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1802 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1803 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1804 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1805 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1806 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1807 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1808 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1809
fcf51541
BZ		 1810 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1811 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1812 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1813 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1814 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1815 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1816 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1817 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1818 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1819
1820 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1821 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1822 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1823 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1824 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1825 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1826 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1827 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1828 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1829 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1830 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1831 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1832
1833 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1834 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1835 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1836 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1837 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1838 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1839 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1840 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1841 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1842 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1843 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1844 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1845
1846 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1847 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1848 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1849 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1850 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1851 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1852 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1853 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1854 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1855 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1856 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1857 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1858
1859 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1860 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1861 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1862 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1863 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1864 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1865 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1866 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1867 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1868 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1869 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1870 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1871 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1872
1873 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1874 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1875 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1876 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1877 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1878 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1879 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1880 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1881 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1882 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1883 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1884 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1885
1886 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1887 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1888 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1889 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1890 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1891 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1892 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1893 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1894 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1895 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1896 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1897 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1898
cea90e55 1899 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1900 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1901
1902 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1903 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1904 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1905 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1906 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1907 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1908 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1909 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1910 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1911 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1912 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1913 }
1914
1915 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1916 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1917
1918 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1919 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1920 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1921 IEEE80211_MAX_RTS_THRESHOLD);
1922 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1923 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1924
1925 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1926
a21c2ab4
HS		 1927 /*
1928 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1929 * time should be set to 16. However, the original Ralink driver uses
1930 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1931 * connection problems with 11g + CTS protection. Hence, use the same
1932 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1933 */
a9dce149 1934 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1935 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1936 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1937 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1938 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1939 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1940 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1941
fcf51541
BZ		 1942 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1943
1944 /*
1945 * ASIC will keep garbage value after boot, clear encryption keys.
1946 */
1947 for (i = 0; i < 4; i++)
1948 rt2800_register_write(rt2x00dev,
1949 SHARED_KEY_MODE_ENTRY(i), 0);
1950
1951 for (i = 0; i < 256; i++) {
1952 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1953 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1954 wcid, sizeof(wcid));
1955
1956 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1957 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1958 }
1959
1960 /*
1961 * Clear all beacons
fcf51541 1962 */
fdb87251
HS		 1963 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1964 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1965 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1966 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1967 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1968 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1969 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1970 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 1971
cea90e55 1972 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 1973 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1974 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1975 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 1976 }
1977
1978 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1979 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1980 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1981 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1982 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1983 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1984 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1985 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1986 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1987 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1988
1989 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1990 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1991 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1992 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1993 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1994 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1995 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1996 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1997 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1998 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1999
2000 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2001 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2002 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2003 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2004 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2005 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2006 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2007 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2008 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2009 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2010
2011 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2012 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2013 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2014 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2015 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2016 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2017
2018 /*
2019 * We must clear the error counters.
2020 * These registers are cleared on read,
2021 * so we may pass a useless variable to store the value.
2022 */
2023 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2024 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2025 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2026 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2027 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2028 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2029
9f926fb5
HS		 2030 /*
2031 * Setup leadtime for pre tbtt interrupt to 6ms
2032 */
2033 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2034 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2035 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2036
fcf51541
BZ		 2037 return 0;
2038}
fcf51541
BZ		 2039
2040static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2041{
2042 unsigned int i;
2043 u32 reg;
2044
2045 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2046 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2047 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2048 return 0;
2049
2050 udelay(REGISTER_BUSY_DELAY);
2051 }
2052
2053 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2054 return -EACCES;
2055}
2056
2057static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2058{
2059 unsigned int i;
2060 u8 value;
2061
2062 /*
2063 * BBP was enabled after firmware was loaded,
2064 * but we need to reactivate it now.
2065 */
2066 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2067 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2068 msleep(1);
2069
2070 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2071 rt2800_bbp_read(rt2x00dev, 0, &value);
2072 if ((value != 0xff) && (value != 0x00))
2073 return 0;
2074 udelay(REGISTER_BUSY_DELAY);
2075 }
2076
2077 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2078 return -EACCES;
2079}
2080
b9a07ae9 2081static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2082{
2083 unsigned int i;
2084 u16 eeprom;
2085 u8 reg_id;
2086 u8 value;
2087
2088 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2089 rt2800_wait_bbp_ready(rt2x00dev)))
2090 return -EACCES;
2091
baff8006
HS		 2092 if (rt2800_is_305x_soc(rt2x00dev))
2093 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2094
fcf51541
BZ		 2095 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2096 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2097
2098 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2099 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2100 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2101 } else {
2102 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2103 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2104 }
2105
fcf51541 2106 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2107
d5385bfc 2108 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2109 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2110 rt2x00_rt(rt2x00dev, RT3090) ||
2111 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2112 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2113 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2114 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2115 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2116 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2117 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2118 } else {
2119 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2120 }
2121
fcf51541
BZ		 2122 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2123 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2124
5ed8f458 2125 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2126 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2127 else
2128 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2129
fcf51541
BZ		 2130 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2131 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2132 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2133
d5385bfc 2134 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2135 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2136 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2137 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2138 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2139 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2140 else
2141 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2142
baff8006
HS		 2143 if (rt2800_is_305x_soc(rt2x00dev))
2144 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2145 else
2146 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2147 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2148
64522957 2149 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2150 rt2x00_rt(rt2x00dev, RT3090) ||
2151 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2152 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2153
d5385bfc
GW		 2154 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2155 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2156 value |= 0x20;
2157 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2158 value &= ~0x02;
fcf51541 2159
d5385bfc 2160 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2161 }
2162
fcf51541
BZ		 2163
2164 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2165 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2166
2167 if (eeprom != 0xffff && eeprom != 0x0000) {
2168 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2169 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2170 rt2800_bbp_write(rt2x00dev, reg_id, value);
2171 }
2172 }
2173
2174 return 0;
2175}
fcf51541
BZ		 2176
2177static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2178 bool bw40, u8 rfcsr24, u8 filter_target)
2179{
2180 unsigned int i;
2181 u8 bbp;
2182 u8 rfcsr;
2183 u8 passband;
2184 u8 stopband;
2185 u8 overtuned = 0;
2186
2187 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2188
2189 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2190 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2191 rt2800_bbp_write(rt2x00dev, 4, bbp);
2192
2193 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2194 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2195 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2196
2197 /*
2198 * Set power & frequency of passband test tone
2199 */
2200 rt2800_bbp_write(rt2x00dev, 24, 0);
2201
2202 for (i = 0; i < 100; i++) {
2203 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2204 msleep(1);
2205
2206 rt2800_bbp_read(rt2x00dev, 55, &passband);
2207 if (passband)
2208 break;
2209 }
2210
2211 /*
2212 * Set power & frequency of stopband test tone
2213 */
2214 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2215
2216 for (i = 0; i < 100; i++) {
2217 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2218 msleep(1);
2219
2220 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2221
2222 if ((passband - stopband) <= filter_target) {
2223 rfcsr24++;
2224 overtuned += ((passband - stopband) == filter_target);
2225 } else
2226 break;
2227
2228 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2229 }
2230
2231 rfcsr24 -= !!overtuned;
2232
2233 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2234 return rfcsr24;
2235}
2236
b9a07ae9 2237static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2238{
2239 u8 rfcsr;
2240 u8 bbp;
8cdd15e0
GW		 2241 u32 reg;
2242 u16 eeprom;
fcf51541 2243
d5385bfc 2244 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2245 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2246 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2247 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2248 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2249 return 0;
2250
fcf51541
BZ		 2251 /*
2252 * Init RF calibration.
2253 */
2254 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2255 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2256 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2257 msleep(1);
2258 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2259 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2260
d5385bfc 2261 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2262 rt2x00_rt(rt2x00dev, RT3071) ||
2263 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2264 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2265 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2266 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2267 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2268 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2269 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2270 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2271 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2272 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2273 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2274 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2275 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2276 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2277 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2278 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2279 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2280 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2281 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2282 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2283 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2284 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2285 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2286 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2287 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2288 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2289 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2290 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2291 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2292 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2293 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2294 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2295 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2296 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2297 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2298 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2299 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2300 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2301 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2302 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2303 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2304 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2305 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2306 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2307 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2308 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2309 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2310 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2311 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2312 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2313 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2314 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2315 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2316 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2317 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2318 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2319 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2320 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2321 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2322 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2323 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2324 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2325 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2326 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2327 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2328 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2329 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2330 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2331 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2332 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2333 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2334 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2335 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2336 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2337 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2338 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2339 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2340 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2341 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2342 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2343 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2344 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2345 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2346 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2347 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2348 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2349 return 0;
8cdd15e0
GW		 2350 }
2351
2352 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2353 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2354 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2355 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2356 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2357 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2358 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2359 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2360 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2361 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2362
2363 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2364
2365 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2366 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2367 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2368 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2369 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2370 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2371 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2372 else
2373 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2374 }
2375 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2376 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2377 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2378 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2379 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2380 }
2381
2382 /*
2383 * Set RX Filter calibration for 20MHz and 40MHz
2384 */
8cdd15e0
GW		 2385 if (rt2x00_rt(rt2x00dev, RT3070)) {
2386 rt2x00dev->calibration[0] =
2387 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2388 rt2x00dev->calibration[1] =
2389 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2390 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2391 rt2x00_rt(rt2x00dev, RT3090) ||
2392 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2393 rt2x00dev->calibration[0] =
2394 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2395 rt2x00dev->calibration[1] =
2396 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2397 }
fcf51541
BZ		 2398
2399 /*
2400 * Set back to initial state
2401 */
2402 rt2800_bbp_write(rt2x00dev, 24, 0);
2403
2404 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2405 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2406 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2407
2408 /*
2409 * set BBP back to BW20
2410 */
2411 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2412 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2413 rt2800_bbp_write(rt2x00dev, 4, bbp);
2414
d5385bfc 2415 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2416 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2417 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2418 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2419 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2420
2421 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2422 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2423 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2424
2425 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2426 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2427 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2428 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2429 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2430 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2431 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2432 }
8cdd15e0
GW		 2433 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2434 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2435 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2436 rt2x00_get_field16(eeprom,
2437 EEPROM_TXMIXER_GAIN_BG_VAL));
2438 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2439
64522957
GW		 2440 if (rt2x00_rt(rt2x00dev, RT3090)) {
2441 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2442
2443 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2444 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2445 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2446 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2447 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2448
2449 rt2800_bbp_write(rt2x00dev, 138, bbp);
2450 }
2451
2452 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2453 rt2x00_rt(rt2x00dev, RT3090) ||
2454 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2455 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2456 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2457 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2458 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2459 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2460 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2461 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2462
2463 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2464 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2465 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2466
2467 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2468 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2469 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2470
2471 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2472 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2473 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2474 }
2475
2476 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2477 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2478 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2479 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2480 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2481 else
2482 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2483 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2484 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2485 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2486 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2487 }
2488
fcf51541
BZ		 2489 return 0;
2490}
b9a07ae9
ID		 2491
2492int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2493{
2494 u32 reg;
2495 u16 word;
2496
2497 /*
2498 * Initialize all registers.
2499 */
2500 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2501 rt2800_init_registers(rt2x00dev) ||
2502 rt2800_init_bbp(rt2x00dev) ||
2503 rt2800_init_rfcsr(rt2x00dev)))
2504 return -EIO;
2505
2506 /*
2507 * Send signal to firmware during boot time.
2508 */
2509 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2510
2511 if (rt2x00_is_usb(rt2x00dev) &&
2512 (rt2x00_rt(rt2x00dev, RT3070) ||
2513 rt2x00_rt(rt2x00dev, RT3071) ||
2514 rt2x00_rt(rt2x00dev, RT3572))) {
2515 udelay(200);
2516 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2517 udelay(10);
2518 }
2519
2520 /*
2521 * Enable RX.
2522 */
2523 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2524 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2525 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2526 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2527
2528 udelay(50);
2529
2530 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2531 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2532 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2533 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2534 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2535 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2536
2537 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2538 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2539 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2540 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2541
2542 /*
2543 * Initialize LED control
2544 */
2545 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2546 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2547 word & 0xff, (word >> 8) & 0xff);
2548
2549 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2550 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2551 word & 0xff, (word >> 8) & 0xff);
2552
2553 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2554 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2555 word & 0xff, (word >> 8) & 0xff);
2556
2557 return 0;
2558}
2559EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2560
2561void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2562{
2563 u32 reg;
2564
2565 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2566 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2567 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2568 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2569 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2570 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2571 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2572
2573 /* Wait for DMA, ignore error */
2574 rt2800_wait_wpdma_ready(rt2x00dev);
2575
2576 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2577 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2578 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2579 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2580
2581 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2582 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2583}
2584EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2585
30e84034
BZ		 2586int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2587{
2588 u32 reg;
2589
2590 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2591
2592 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2593}
2594EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2595
2596static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2597{
2598 u32 reg;
2599
31a4cf1f
GW		 2600 mutex_lock(&rt2x00dev->csr_mutex);
2601
2602 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2603 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2604 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2605 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2606 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2607
2608 /* Wait until the EEPROM has been loaded */
2609 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2610
2611 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2612 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2613 (u32 *)&rt2x00dev->eeprom[i]);
2614 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2615 (u32 *)&rt2x00dev->eeprom[i + 2]);
2616 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2617 (u32 *)&rt2x00dev->eeprom[i + 4]);
2618 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2619 (u32 *)&rt2x00dev->eeprom[i + 6]);
2620
2621 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2622}
2623
2624void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2625{
2626 unsigned int i;
2627
2628 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2629 rt2800_efuse_read(rt2x00dev, i);
2630}
2631EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2632
38bd7b8a
BZ		 2633int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2634{
2635 u16 word;
2636 u8 *mac;
2637 u8 default_lna_gain;
2638
2639 /*
2640 * Start validation of the data that has been read.
2641 */
2642 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2643 if (!is_valid_ether_addr(mac)) {
2644 random_ether_addr(mac);
2645 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2646 }
2647
2648 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2649 if (word == 0xffff) {
2650 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2651 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2652 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2653 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2654 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2655 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2656 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2657 /*
2658 * There is a max of 2 RX streams for RT28x0 series
2659 */
2660 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2661 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2662 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2663 }
2664
2665 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2666 if (word == 0xffff) {
2667 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2668 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2669 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2670 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2671 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2672 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2673 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2674 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2675 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2676 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2677 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2678 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2679 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2680 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2681 }
2682
2683 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2684 if ((word & 0x00ff) == 0x00ff) {
2685 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2686 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2687 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2688 }
2689 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2690 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2691 LED_MODE_TXRX_ACTIVITY);
2692 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2693 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2694 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2695 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2696 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2697 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2698 }
2699
2700 /*
2701 * During the LNA validation we are going to use
2702 * lna0 as correct value. Note that EEPROM_LNA
2703 * is never validated.
2704 */
2705 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2706 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2707
2708 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2709 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2710 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2711 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2712 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2713 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2714
2715 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2716 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2717 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2718 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2719 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2720 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2721 default_lna_gain);
2722 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2723
2724 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2725 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2726 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2727 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2728 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2729 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2730
2731 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2732 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2733 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2734 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2735 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2736 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2737 default_lna_gain);
2738 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2739
8d1331b3
ID		 2740 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2741 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2742 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2743 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2744 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2745 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2746
38bd7b8a
BZ		 2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2750
2751int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2752{
2753 u32 reg;
2754 u16 value;
2755 u16 eeprom;
2756
2757 /*
2758 * Read EEPROM word for configuration.
2759 */
2760 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2761
2762 /*
2763 * Identify RF chipset.
2764 */
2765 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2766 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2767
49e721ec
GW		 2768 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2769 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2770
2771 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2772 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2773 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2774 !rt2x00_rt(rt2x00dev, RT3070) &&
2775 !rt2x00_rt(rt2x00dev, RT3071) &&
2776 !rt2x00_rt(rt2x00dev, RT3090) &&
2777 !rt2x00_rt(rt2x00dev, RT3390) &&
2778 !rt2x00_rt(rt2x00dev, RT3572)) {
2779 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2780 return -ENODEV;
f273fe55 2781 }
714fa663 2782
5122d898
GW		 2783 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2784 !rt2x00_rf(rt2x00dev, RF2850) &&
2785 !rt2x00_rf(rt2x00dev, RF2720) &&
2786 !rt2x00_rf(rt2x00dev, RF2750) &&
2787 !rt2x00_rf(rt2x00dev, RF3020) &&
2788 !rt2x00_rf(rt2x00dev, RF2020) &&
2789 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2790 !rt2x00_rf(rt2x00dev, RF3022) &&
2791 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2792 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2793 return -ENODEV;
2794 }
2795
2796 /*
2797 * Identify default antenna configuration.
2798 */
2799 rt2x00dev->default_ant.tx =
2800 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2801 rt2x00dev->default_ant.rx =
2802 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2803
2804 /*
2805 * Read frequency offset and RF programming sequence.
2806 */
2807 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2808 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2809
2810 /*
2811 * Read external LNA informations.
2812 */
2813 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2814
2815 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2816 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2817 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2818 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2819
2820 /*
2821 * Detect if this device has an hardware controlled radio.
2822 */
2823 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2824 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2825
2826 /*
2827 * Store led settings, for correct led behaviour.
2828 */
2829#ifdef CONFIG_RT2X00_LIB_LEDS
2830 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2831 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2832 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2833
2834 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2835#endif /* CONFIG_RT2X00_LIB_LEDS */
2836
2837 return 0;
2838}
2839EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2840
4da2933f 2841/*
55f9321a 2842 * RF value list for rt28xx
4da2933f
BZ		 2843 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2844 */
2845static const struct rf_channel rf_vals[] = {
2846 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2847 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2848 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2849 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2850 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2851 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2852 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2853 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2854 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2855 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2856 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2857 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2858 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2859 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2860
2861 /* 802.11 UNI / HyperLan 2 */
2862 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2863 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2864 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2865 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2866 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2867 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2868 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2869 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2870 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2871 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2872 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2873 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2874
2875 /* 802.11 HyperLan 2 */
2876 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2877 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2878 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2879 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2880 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2881 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2882 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2883 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2884 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2885 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2886 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2887 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2888 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2889 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2890 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2891 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2892
2893 /* 802.11 UNII */
2894 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2895 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2896 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2897 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2898 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2899 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2900 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2901 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2902 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2903 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2904 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2905
2906 /* 802.11 Japan */
2907 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2908 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2909 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2910 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2911 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2912 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2913 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2914};
2915
2916/*
55f9321a
ID		 2917 * RF value list for rt3xxx
2918 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2919 */
55f9321a 2920static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2921 {1, 241, 2, 2 },
2922 {2, 241, 2, 7 },
2923 {3, 242, 2, 2 },
2924 {4, 242, 2, 7 },
2925 {5, 243, 2, 2 },
2926 {6, 243, 2, 7 },
2927 {7, 244, 2, 2 },
2928 {8, 244, 2, 7 },
2929 {9, 245, 2, 2 },
2930 {10, 245, 2, 7 },
2931 {11, 246, 2, 2 },
2932 {12, 246, 2, 7 },
2933 {13, 247, 2, 2 },
2934 {14, 248, 2, 4 },
55f9321a
ID		 2935
2936 /* 802.11 UNI / HyperLan 2 */
2937 {36, 0x56, 0, 4},
2938 {38, 0x56, 0, 6},
2939 {40, 0x56, 0, 8},
2940 {44, 0x57, 0, 0},
2941 {46, 0x57, 0, 2},
2942 {48, 0x57, 0, 4},
2943 {52, 0x57, 0, 8},
2944 {54, 0x57, 0, 10},
2945 {56, 0x58, 0, 0},
2946 {60, 0x58, 0, 4},
2947 {62, 0x58, 0, 6},
2948 {64, 0x58, 0, 8},
2949
2950 /* 802.11 HyperLan 2 */
2951 {100, 0x5b, 0, 8},
2952 {102, 0x5b, 0, 10},
2953 {104, 0x5c, 0, 0},
2954 {108, 0x5c, 0, 4},
2955 {110, 0x5c, 0, 6},
2956 {112, 0x5c, 0, 8},
2957 {116, 0x5d, 0, 0},
2958 {118, 0x5d, 0, 2},
2959 {120, 0x5d, 0, 4},
2960 {124, 0x5d, 0, 8},
2961 {126, 0x5d, 0, 10},
2962 {128, 0x5e, 0, 0},
2963 {132, 0x5e, 0, 4},
2964 {134, 0x5e, 0, 6},
2965 {136, 0x5e, 0, 8},
2966 {140, 0x5f, 0, 0},
2967
2968 /* 802.11 UNII */
2969 {149, 0x5f, 0, 9},
2970 {151, 0x5f, 0, 11},
2971 {153, 0x60, 0, 1},
2972 {157, 0x60, 0, 5},
2973 {159, 0x60, 0, 7},
2974 {161, 0x60, 0, 9},
2975 {165, 0x61, 0, 1},
2976 {167, 0x61, 0, 3},
2977 {169, 0x61, 0, 5},
2978 {171, 0x61, 0, 7},
2979 {173, 0x61, 0, 9},
4da2933f
BZ		 2980};
2981
2982int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2983{
4da2933f
BZ		 2984 struct hw_mode_spec *spec = &rt2x00dev->spec;
2985 struct channel_info *info;
8d1331b3
ID		 2986 char *default_power1;
2987 char *default_power2;
4da2933f 2988 unsigned int i;
8d1331b3 2989 unsigned short max_power;
4da2933f
BZ		 2990 u16 eeprom;
2991
93b6bd26
GW		 2992 /*
2993 * Disable powersaving as default on PCI devices.
2994 */
cea90e55 2995 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2996 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2997
4da2933f
BZ		 2998 /*
2999 * Initialize all hw fields.
3000 */
3001 rt2x00dev->hw->flags =
3002 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3003 IEEE80211_HW_SIGNAL_DBM |
3004 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3005 IEEE80211_HW_PS_NULLFUNC_STACK |
3006 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 3007
4da2933f
BZ		 3008 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3009 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3010 rt2x00_eeprom_addr(rt2x00dev,
3011 EEPROM_MAC_ADDR_0));
3012
3f2bee24
HS		 3013 /*
3014 * As rt2800 has a global fallback table we cannot specify
3015 * more then one tx rate per frame but since the hw will
3016 * try several rates (based on the fallback table) we should
3017 * still initialize max_rates to the maximum number of rates
3018 * we are going to try. Otherwise mac80211 will truncate our
3019 * reported tx rates and the rc algortihm will end up with
3020 * incorrect data.
3021 */
3022 rt2x00dev->hw->max_rates = 7;
3023 rt2x00dev->hw->max_rate_tries = 1;
3024
4da2933f
BZ		 3025 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3026
3027 /*
3028 * Initialize hw_mode information.
3029 */
3030 spec->supported_bands = SUPPORT_BAND_2GHZ;
3031 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3032
5122d898 3033 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3034 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3035 spec->num_channels = 14;
3036 spec->channels = rf_vals;
55f9321a
ID		 3037 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3038 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3039 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3040 spec->num_channels = ARRAY_SIZE(rf_vals);
3041 spec->channels = rf_vals;
5122d898
GW		 3042 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3043 rt2x00_rf(rt2x00dev, RF2020) ||
3044 rt2x00_rf(rt2x00dev, RF3021) ||
3045 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3046 spec->num_channels = 14;
3047 spec->channels = rf_vals_3x;
3048 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3049 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3050 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3051 spec->channels = rf_vals_3x;
4da2933f
BZ		 3052 }
3053
3054 /*
3055 * Initialize HT information.
3056 */
5122d898 3057 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3058 spec->ht.ht_supported = true;
3059 else
3060 spec->ht.ht_supported = false;
3061
4da2933f 3062 spec->ht.cap =
06443e46 3063 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3064 IEEE80211_HT_CAP_GRN_FLD |
3065 IEEE80211_HT_CAP_SGI_20 |
aa674631 3066 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3067
3068 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3069 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3070
aa674631
ID		 3071 spec->ht.cap |=
3072 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3073 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3074
4da2933f
BZ		 3075 spec->ht.ampdu_factor = 3;
3076 spec->ht.ampdu_density = 4;
3077 spec->ht.mcs.tx_params =
3078 IEEE80211_HT_MCS_TX_DEFINED |
3079 IEEE80211_HT_MCS_TX_RX_DIFF |
3080 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3081 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3082
3083 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3084 case 3:
3085 spec->ht.mcs.rx_mask[2] = 0xff;
3086 case 2:
3087 spec->ht.mcs.rx_mask[1] = 0xff;
3088 case 1:
3089 spec->ht.mcs.rx_mask[0] = 0xff;
3090 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3091 break;
3092 }
3093
3094 /*
3095 * Create channel information array
3096 */
3097 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3098 if (!info)
3099 return -ENOMEM;
3100
3101 spec->channels_info = info;
3102
8d1331b3
ID		 3103 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3104 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3105 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3106 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3107
3108 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3109 info[i].max_power = max_power;
3110 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3111 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3112 }
3113
3114 if (spec->num_channels > 14) {
8d1331b3
ID		 3115 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3116 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3117 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3118
3119 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3120 info[i].max_power = max_power;
3121 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3122 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3123 }
3124 }
3125
3126 return 0;
3127}
3128EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3129
2ce33995
BZ		 3130/*
3131 * IEEE80211 stack callback functions.
3132 */
e783619e
HS		 3133void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3134 u16 *iv16)
2ce33995
BZ		 3135{
3136 struct rt2x00_dev *rt2x00dev = hw->priv;
3137 struct mac_iveiv_entry iveiv_entry;
3138 u32 offset;
3139
3140 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3141 rt2800_register_multiread(rt2x00dev, offset,
3142 &iveiv_entry, sizeof(iveiv_entry));
3143
855da5e0
JL		 3144 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3145 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3146}
e783619e 3147EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3148
e783619e 3149int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3150{
3151 struct rt2x00_dev *rt2x00dev = hw->priv;
3152 u32 reg;
3153 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3154
3155 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3156 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3157 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3158
3159 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3160 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3161 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3162
3163 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3164 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3165 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3166
3167 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3168 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3169 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3170
3171 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3172 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3173 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3174
3175 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3176 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3177 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3178
3179 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3180 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3181 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3182
3183 return 0;
3184}
e783619e 3185EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3186
e783619e
HS		 3187int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3188 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3189{
3190 struct rt2x00_dev *rt2x00dev = hw->priv;
3191 struct data_queue *queue;
3192 struct rt2x00_field32 field;
3193 int retval;
3194 u32 reg;
3195 u32 offset;
3196
3197 /*
3198 * First pass the configuration through rt2x00lib, that will
3199 * update the queue settings and validate the input. After that
3200 * we are free to update the registers based on the value
3201 * in the queue parameter.
3202 */
3203 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3204 if (retval)
3205 return retval;
3206
3207 /*
3208 * We only need to perform additional register initialization
3209 * for WMM queues/
3210 */
3211 if (queue_idx >= 4)
3212 return 0;
3213
3214 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3215
3216 /* Update WMM TXOP register */
3217 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3218 field.bit_offset = (queue_idx & 1) * 16;
3219 field.bit_mask = 0xffff << field.bit_offset;
3220
3221 rt2800_register_read(rt2x00dev, offset, &reg);
3222 rt2x00_set_field32(&reg, field, queue->txop);
3223 rt2800_register_write(rt2x00dev, offset, reg);
3224
3225 /* Update WMM registers */
3226 field.bit_offset = queue_idx * 4;
3227 field.bit_mask = 0xf << field.bit_offset;
3228
3229 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3230 rt2x00_set_field32(&reg, field, queue->aifs);
3231 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3232
3233 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3234 rt2x00_set_field32(&reg, field, queue->cw_min);
3235 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3236
3237 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3238 rt2x00_set_field32(&reg, field, queue->cw_max);
3239 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3240
3241 /* Update EDCA registers */
3242 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3243
3244 rt2800_register_read(rt2x00dev, offset, &reg);
3245 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3246 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3247 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3248 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3249 rt2800_register_write(rt2x00dev, offset, reg);
3250
3251 return 0;
3252}
e783619e 3253EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3254
e783619e 3255u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3256{
3257 struct rt2x00_dev *rt2x00dev = hw->priv;
3258 u64 tsf;
3259 u32 reg;
3260
3261 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3262 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3263 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3264 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3265
3266 return tsf;
3267}
e783619e 3268EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3269
e783619e
HS		 3270int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3271 enum ieee80211_ampdu_mlme_action action,
3272 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3273{
1df90809
HS		 3274 int ret = 0;
3275
3276 switch (action) {
3277 case IEEE80211_AMPDU_RX_START:
3278 case IEEE80211_AMPDU_RX_STOP:
3279 /* we don't support RX aggregation yet */
3280 ret = -ENOTSUPP;
3281 break;
3282 case IEEE80211_AMPDU_TX_START:
3283 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3284 break;
3285 case IEEE80211_AMPDU_TX_STOP:
3286 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3287 break;
3288 case IEEE80211_AMPDU_TX_OPERATIONAL:
3289 break;
3290 default:
4e9e58c6 3291 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3292 }
3293
3294 return ret;
3295}
e783619e 3296EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3297
3298MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3299MODULE_VERSION(DRV_VERSION);
3300MODULE_DESCRIPTION("Ralink RT2800 library");
3301MODULE_LICENSE("GPL");
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