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rt2x00: rt2800: don't overwrite SIFS values on erp changes
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
9c9a0d14 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 4
9c9a0d14
GW		 5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38
39#include "rt2x00.h"
ac394917 40#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 41#include "rt2x00usb.h"
42#endif
89297425
BZ		 43#include "rt2800lib.h"
44#include "rt2800.h"
fcf51541 45#include "rt2800usb.h"
89297425
BZ		 46
47MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
48MODULE_DESCRIPTION("rt2800 library");
49MODULE_LICENSE("GPL");
50
51/*
52 * Register access.
53 * All access to the CSR registers will go through the methods
54 * rt2800_register_read and rt2800_register_write.
55 * BBP and RF register require indirect register access,
56 * and use the CSR registers BBPCSR and RFCSR to achieve this.
57 * These indirect registers work with busy bits,
58 * and we will try maximal REGISTER_BUSY_COUNT times to access
59 * the register while taking a REGISTER_BUSY_DELAY us delay
60 * between each attampt. When the busy bit is still set at that time,
61 * the access attempt is considered to have failed,
62 * and we will print an error.
63 * The _lock versions must be used if you already hold the csr_mutex
64 */
65#define WAIT_FOR_BBP(__dev, __reg) \
66 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
67#define WAIT_FOR_RFCSR(__dev, __reg) \
68 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
69#define WAIT_FOR_RF(__dev, __reg) \
70 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
71#define WAIT_FOR_MCU(__dev, __reg) \
72 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
73 H2M_MAILBOX_CSR_OWNER, (__reg))
74
baff8006
HS		 75static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
76{
77 /* check for rt2872 on SoC */
78 if (!rt2x00_is_soc(rt2x00dev) ||
79 !rt2x00_rt(rt2x00dev, RT2872))
80 return false;
81
82 /* we know for sure that these rf chipsets are used on rt305x boards */
83 if (rt2x00_rf(rt2x00dev, RF3020) ||
84 rt2x00_rf(rt2x00dev, RF3021) ||
85 rt2x00_rf(rt2x00dev, RF3022))
86 return true;
87
88 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
89 return false;
90}
91
fcf51541
BZ		 92static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
93 const unsigned int word, const u8 value)
89297425
BZ		 94{
95 u32 reg;
96
97 mutex_lock(&rt2x00dev->csr_mutex);
98
99 /*
100 * Wait until the BBP becomes available, afterwards we
101 * can safely write the new data into the register.
102 */
103 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
104 reg = 0;
105 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
106 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
107 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
108 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 109 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 110 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
111
112 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
113 }
114
115 mutex_unlock(&rt2x00dev->csr_mutex);
116}
89297425 117
fcf51541
BZ		 118static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
119 const unsigned int word, u8 *value)
89297425
BZ		 120{
121 u32 reg;
122
123 mutex_lock(&rt2x00dev->csr_mutex);
124
125 /*
126 * Wait until the BBP becomes available, afterwards we
127 * can safely write the read request into the register.
128 * After the data has been written, we wait until hardware
129 * returns the correct value, if at any time the register
130 * doesn't become available in time, reg will be 0xffffffff
131 * which means we return 0xff to the caller.
132 */
133 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
136 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
137 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 138 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 139 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
140
141 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
142
143 WAIT_FOR_BBP(rt2x00dev, &reg);
144 }
145
146 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
147
148 mutex_unlock(&rt2x00dev->csr_mutex);
149}
89297425 150
fcf51541
BZ		 151static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
152 const unsigned int word, const u8 value)
89297425
BZ		 153{
154 u32 reg;
155
156 mutex_lock(&rt2x00dev->csr_mutex);
157
158 /*
159 * Wait until the RFCSR becomes available, afterwards we
160 * can safely write the new data into the register.
161 */
162 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
163 reg = 0;
164 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
165 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
166 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
168
169 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
170 }
171
172 mutex_unlock(&rt2x00dev->csr_mutex);
173}
89297425 174
fcf51541
BZ		 175static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
176 const unsigned int word, u8 *value)
89297425
BZ		 177{
178 u32 reg;
179
180 mutex_lock(&rt2x00dev->csr_mutex);
181
182 /*
183 * Wait until the RFCSR becomes available, afterwards we
184 * can safely write the read request into the register.
185 * After the data has been written, we wait until hardware
186 * returns the correct value, if at any time the register
187 * doesn't become available in time, reg will be 0xffffffff
188 * which means we return 0xff to the caller.
189 */
190 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
191 reg = 0;
192 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
193 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
194 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
195
196 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
197
198 WAIT_FOR_RFCSR(rt2x00dev, &reg);
199 }
200
201 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
202
203 mutex_unlock(&rt2x00dev->csr_mutex);
204}
89297425 205
fcf51541
BZ		 206static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
207 const unsigned int word, const u32 value)
89297425
BZ		 208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the RF becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
218 reg = 0;
219 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
220 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
221 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
222 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
223
224 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
225 rt2x00_rf_write(rt2x00dev, word, value);
226 }
227
228 mutex_unlock(&rt2x00dev->csr_mutex);
229}
89297425
BZ		 230
231void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
232 const u8 command, const u8 token,
233 const u8 arg0, const u8 arg1)
234{
235 u32 reg;
236
ee303e54 237 /*
cea90e55 238 * SOC devices don't support MCU requests.
ee303e54 239 */
cea90e55 240 if (rt2x00_is_soc(rt2x00dev))
ee303e54 241 return;
89297425
BZ		 242
243 mutex_lock(&rt2x00dev->csr_mutex);
244
245 /*
246 * Wait until the MCU becomes available, afterwards we
247 * can safely write the new data into the register.
248 */
249 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
250 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
251 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
252 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
253 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
254 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
255
256 reg = 0;
257 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
258 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
259 }
260
261 mutex_unlock(&rt2x00dev->csr_mutex);
262}
263EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 264
67a4c1e2
GW		 265int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
266{
267 unsigned int i;
268 u32 reg;
269
270 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
271 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
272 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
273 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
274 return 0;
275
276 msleep(1);
277 }
278
279 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
280 return -EACCES;
281}
282EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
283
f4450616
BZ		 284#ifdef CONFIG_RT2X00_LIB_DEBUGFS
285const struct rt2x00debug rt2800_rt2x00debug = {
286 .owner = THIS_MODULE,
287 .csr = {
288 .read = rt2800_register_read,
289 .write = rt2800_register_write,
290 .flags = RT2X00DEBUGFS_OFFSET,
291 .word_base = CSR_REG_BASE,
292 .word_size = sizeof(u32),
293 .word_count = CSR_REG_SIZE / sizeof(u32),
294 },
295 .eeprom = {
296 .read = rt2x00_eeprom_read,
297 .write = rt2x00_eeprom_write,
298 .word_base = EEPROM_BASE,
299 .word_size = sizeof(u16),
300 .word_count = EEPROM_SIZE / sizeof(u16),
301 },
302 .bbp = {
303 .read = rt2800_bbp_read,
304 .write = rt2800_bbp_write,
305 .word_base = BBP_BASE,
306 .word_size = sizeof(u8),
307 .word_count = BBP_SIZE / sizeof(u8),
308 },
309 .rf = {
310 .read = rt2x00_rf_read,
311 .write = rt2800_rf_write,
312 .word_base = RF_BASE,
313 .word_size = sizeof(u32),
314 .word_count = RF_SIZE / sizeof(u32),
315 },
316};
317EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
318#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
319
320int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
321{
322 u32 reg;
323
324 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
325 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
326}
327EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
328
329#ifdef CONFIG_RT2X00_LIB_LEDS
330static void rt2800_brightness_set(struct led_classdev *led_cdev,
331 enum led_brightness brightness)
332{
333 struct rt2x00_led *led =
334 container_of(led_cdev, struct rt2x00_led, led_dev);
335 unsigned int enabled = brightness != LED_OFF;
336 unsigned int bg_mode =
337 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
338 unsigned int polarity =
339 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
340 EEPROM_FREQ_LED_POLARITY);
341 unsigned int ledmode =
342 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
343 EEPROM_FREQ_LED_MODE);
344
345 if (led->type == LED_TYPE_RADIO) {
346 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
347 enabled ? 0x20 : 0);
348 } else if (led->type == LED_TYPE_ASSOC) {
349 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
350 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
351 } else if (led->type == LED_TYPE_QUALITY) {
352 /*
353 * The brightness is divided into 6 levels (0 - 5),
354 * The specs tell us the following levels:
355 * 0, 1 ,3, 7, 15, 31
356 * to determine the level in a simple way we can simply
357 * work with bitshifting:
358 * (1 << level) - 1
359 */
360 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
361 (1 << brightness / (LED_FULL / 6)) - 1,
362 polarity);
363 }
364}
365
366static int rt2800_blink_set(struct led_classdev *led_cdev,
367 unsigned long *delay_on, unsigned long *delay_off)
368{
369 struct rt2x00_led *led =
370 container_of(led_cdev, struct rt2x00_led, led_dev);
371 u32 reg;
372
373 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
374 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
375 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 376 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
377
378 return 0;
379}
380
b3579d6a 381static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 382 struct rt2x00_led *led, enum led_type type)
383{
384 led->rt2x00dev = rt2x00dev;
385 led->type = type;
386 led->led_dev.brightness_set = rt2800_brightness_set;
387 led->led_dev.blink_set = rt2800_blink_set;
388 led->flags = LED_INITIALIZED;
389}
f4450616
BZ		 390#endif /* CONFIG_RT2X00_LIB_LEDS */
391
392/*
393 * Configuration handlers.
394 */
395static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
396 struct rt2x00lib_crypto *crypto,
397 struct ieee80211_key_conf *key)
398{
399 struct mac_wcid_entry wcid_entry;
400 struct mac_iveiv_entry iveiv_entry;
401 u32 offset;
402 u32 reg;
403
404 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
405
406 rt2800_register_read(rt2x00dev, offset, &reg);
407 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
408 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
409 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
410 (crypto->cmd == SET_KEY) * crypto->cipher);
411 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
412 (crypto->cmd == SET_KEY) * crypto->bssidx);
413 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
414 rt2800_register_write(rt2x00dev, offset, reg);
415
416 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
417
418 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
419 if ((crypto->cipher == CIPHER_TKIP) ||
420 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
421 (crypto->cipher == CIPHER_AES))
422 iveiv_entry.iv[3] |= 0x20;
423 iveiv_entry.iv[3] |= key->keyidx << 6;
424 rt2800_register_multiwrite(rt2x00dev, offset,
425 &iveiv_entry, sizeof(iveiv_entry));
426
427 offset = MAC_WCID_ENTRY(key->hw_key_idx);
428
429 memset(&wcid_entry, 0, sizeof(wcid_entry));
430 if (crypto->cmd == SET_KEY)
431 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
432 rt2800_register_multiwrite(rt2x00dev, offset,
433 &wcid_entry, sizeof(wcid_entry));
434}
435
436int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
437 struct rt2x00lib_crypto *crypto,
438 struct ieee80211_key_conf *key)
439{
440 struct hw_key_entry key_entry;
441 struct rt2x00_field32 field;
442 u32 offset;
443 u32 reg;
444
445 if (crypto->cmd == SET_KEY) {
446 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
447
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
456 rt2800_register_multiwrite(rt2x00dev, offset,
457 &key_entry, sizeof(key_entry));
458 }
459
460 /*
461 * The cipher types are stored over multiple registers
462 * starting with SHARED_KEY_MODE_BASE each word will have
463 * 32 bits and contains the cipher types for 2 bssidx each.
464 * Using the correct defines correctly will cause overhead,
465 * so just calculate the correct offset.
466 */
467 field.bit_offset = 4 * (key->hw_key_idx % 8);
468 field.bit_mask = 0x7 << field.bit_offset;
469
470 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
471
472 rt2800_register_read(rt2x00dev, offset, &reg);
473 rt2x00_set_field32(&reg, field,
474 (crypto->cmd == SET_KEY) * crypto->cipher);
475 rt2800_register_write(rt2x00dev, offset, reg);
476
477 /*
478 * Update WCID information
479 */
480 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
481
482 return 0;
483}
484EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
485
486int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
487 struct rt2x00lib_crypto *crypto,
488 struct ieee80211_key_conf *key)
489{
490 struct hw_key_entry key_entry;
491 u32 offset;
492
493 if (crypto->cmd == SET_KEY) {
494 /*
495 * 1 pairwise key is possible per AID, this means that the AID
496 * equals our hw_key_idx. Make sure the WCID starts _after_ the
497 * last possible shared key entry.
498 */
499 if (crypto->aid > (256 - 32))
500 return -ENOSPC;
501
502 key->hw_key_idx = 32 + crypto->aid;
503
504 memcpy(key_entry.key, crypto->key,
505 sizeof(key_entry.key));
506 memcpy(key_entry.tx_mic, crypto->tx_mic,
507 sizeof(key_entry.tx_mic));
508 memcpy(key_entry.rx_mic, crypto->rx_mic,
509 sizeof(key_entry.rx_mic));
510
511 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
512 rt2800_register_multiwrite(rt2x00dev, offset,
513 &key_entry, sizeof(key_entry));
514 }
515
516 /*
517 * Update WCID information
518 */
519 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
520
521 return 0;
522}
523EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
524
525void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
526 const unsigned int filter_flags)
527{
528 u32 reg;
529
530 /*
531 * Start configuration steps.
532 * Note that the version error will always be dropped
533 * and broadcast frames will always be accepted since
534 * there is no filter for it at this time.
535 */
536 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
538 !(filter_flags & FIF_FCSFAIL));
539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
540 !(filter_flags & FIF_PLCPFAIL));
541 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
542 !(filter_flags & FIF_PROMISC_IN_BSS));
543 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
544 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
545 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
546 !(filter_flags & FIF_ALLMULTI));
547 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
548 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
549 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
550 !(filter_flags & FIF_CONTROL));
551 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
552 !(filter_flags & FIF_CONTROL));
553 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
554 !(filter_flags & FIF_CONTROL));
555 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
556 !(filter_flags & FIF_CONTROL));
557 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
558 !(filter_flags & FIF_CONTROL));
559 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
560 !(filter_flags & FIF_PSPOLL));
561 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
562 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
563 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
564 !(filter_flags & FIF_CONTROL));
565 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
566}
567EXPORT_SYMBOL_GPL(rt2800_config_filter);
568
569void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
570 struct rt2x00intf_conf *conf, const unsigned int flags)
571{
572 unsigned int beacon_base;
573 u32 reg;
574
575 if (flags & CONFIG_UPDATE_TYPE) {
576 /*
577 * Clear current synchronisation setup.
578 * For the Beacon base registers we only need to clear
579 * the first byte since that byte contains the VALID and OWNER
580 * bits which (when set to 0) will invalidate the entire beacon.
581 */
582 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
583 rt2800_register_write(rt2x00dev, beacon_base, 0);
584
585 /*
586 * Enable synchronisation.
587 */
588 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
589 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
590 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 591 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
592 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 593 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
594 }
595
596 if (flags & CONFIG_UPDATE_MAC) {
597 reg = le32_to_cpu(conf->mac[1]);
598 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
599 conf->mac[1] = cpu_to_le32(reg);
600
601 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
602 conf->mac, sizeof(conf->mac));
603 }
604
605 if (flags & CONFIG_UPDATE_BSSID) {
606 reg = le32_to_cpu(conf->bssid[1]);
607 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
608 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
609 conf->bssid[1] = cpu_to_le32(reg);
610
611 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
612 conf->bssid, sizeof(conf->bssid));
613 }
614}
615EXPORT_SYMBOL_GPL(rt2800_config_intf);
616
617void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
618{
619 u32 reg;
620
f4450616
BZ		 621 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
622 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
623 !!erp->short_preamble);
624 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
625 !!erp->short_preamble);
626 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
627
628 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
629 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
630 erp->cts_protection ? 2 : 0);
631 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
632
633 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
634 erp->basic_rates);
635 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
636
637 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
638 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 639 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
640
641 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 642 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 643 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
644
645 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
646 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
647 erp->beacon_int * 16);
648 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
649}
650EXPORT_SYMBOL_GPL(rt2800_config_erp);
651
652void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
653{
654 u8 r1;
655 u8 r3;
656
657 rt2800_bbp_read(rt2x00dev, 1, &r1);
658 rt2800_bbp_read(rt2x00dev, 3, &r3);
659
660 /*
661 * Configure the TX antenna.
662 */
663 switch ((int)ant->tx) {
664 case 1:
665 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 666 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 667 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
668 break;
669 case 2:
670 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
671 break;
672 case 3:
673 /* Do nothing */
674 break;
675 }
676
677 /*
678 * Configure the RX antenna.
679 */
680 switch ((int)ant->rx) {
681 case 1:
682 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
683 break;
684 case 2:
685 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
686 break;
687 case 3:
688 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
689 break;
690 }
691
692 rt2800_bbp_write(rt2x00dev, 3, r3);
693 rt2800_bbp_write(rt2x00dev, 1, r1);
694}
695EXPORT_SYMBOL_GPL(rt2800_config_ant);
696
697static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
698 struct rt2x00lib_conf *libconf)
699{
700 u16 eeprom;
701 short lna_gain;
702
703 if (libconf->rf.channel <= 14) {
704 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
705 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
706 } else if (libconf->rf.channel <= 64) {
707 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
708 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
709 } else if (libconf->rf.channel <= 128) {
710 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
711 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
712 } else {
713 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
714 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
715 }
716
717 rt2x00dev->lna_gain = lna_gain;
718}
719
06855ef4
GW		 720static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
721 struct ieee80211_conf *conf,
722 struct rf_channel *rf,
723 struct channel_info *info)
f4450616
BZ		 724{
725 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
726
727 if (rt2x00dev->default_ant.tx == 1)
728 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
729
730 if (rt2x00dev->default_ant.rx == 1) {
731 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
732 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
733 } else if (rt2x00dev->default_ant.rx == 2)
734 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
735
736 if (rf->channel > 14) {
737 /*
738 * When TX power is below 0, we should increase it by 7 to
739 * make it a positive value (Minumum value is -7).
740 * However this means that values between 0 and 7 have
741 * double meaning, and we should set a 7DBm boost flag.
742 */
743 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
744 (info->tx_power1 >= 0));
745
746 if (info->tx_power1 < 0)
747 info->tx_power1 += 7;
748
749 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
750 TXPOWER_A_TO_DEV(info->tx_power1));
751
752 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
753 (info->tx_power2 >= 0));
754
755 if (info->tx_power2 < 0)
756 info->tx_power2 += 7;
757
758 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
759 TXPOWER_A_TO_DEV(info->tx_power2));
760 } else {
761 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
762 TXPOWER_G_TO_DEV(info->tx_power1));
763 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
764 TXPOWER_G_TO_DEV(info->tx_power2));
765 }
766
767 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
768
769 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
770 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
771 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
772 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
773
774 udelay(200);
775
776 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
777 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
778 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
779 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
780
781 udelay(200);
782
783 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
784 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
785 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
786 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
787}
788
06855ef4
GW		 789static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
790 struct ieee80211_conf *conf,
791 struct rf_channel *rf,
792 struct channel_info *info)
f4450616
BZ		 793{
794 u8 rfcsr;
795
796 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 797 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 798
799 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 800 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 801 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
802
803 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
804 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
805 TXPOWER_G_TO_DEV(info->tx_power1));
806 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
807
5a673964
HS		 808 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
809 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
810 TXPOWER_G_TO_DEV(info->tx_power2));
811 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
812
f4450616
BZ		 813 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
814 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
815 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
816
817 rt2800_rfcsr_write(rt2x00dev, 24,
818 rt2x00dev->calibration[conf_is_ht40(conf)]);
819
71976907 820 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 821 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 822 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 823}
824
825static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
826 struct ieee80211_conf *conf,
827 struct rf_channel *rf,
828 struct channel_info *info)
829{
830 u32 reg;
831 unsigned int tx_pin;
832 u8 bbp;
833
06855ef4
GW		 834 if (rt2x00_rf(rt2x00dev, RF2020) ||
835 rt2x00_rf(rt2x00dev, RF3020) ||
836 rt2x00_rf(rt2x00dev, RF3021) ||
837 rt2x00_rf(rt2x00dev, RF3022))
838 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 839 else
06855ef4 840 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 841
842 /*
843 * Change BBP settings
844 */
845 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
846 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
847 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
848 rt2800_bbp_write(rt2x00dev, 86, 0);
849
850 if (rf->channel <= 14) {
851 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
852 rt2800_bbp_write(rt2x00dev, 82, 0x62);
853 rt2800_bbp_write(rt2x00dev, 75, 0x46);
854 } else {
855 rt2800_bbp_write(rt2x00dev, 82, 0x84);
856 rt2800_bbp_write(rt2x00dev, 75, 0x50);
857 }
858 } else {
859 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
860
861 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
862 rt2800_bbp_write(rt2x00dev, 75, 0x46);
863 else
864 rt2800_bbp_write(rt2x00dev, 75, 0x50);
865 }
866
867 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 868 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 869 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
870 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
871 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
872
873 tx_pin = 0;
874
875 /* Turn on unused PA or LNA when not using 1T or 1R */
876 if (rt2x00dev->default_ant.tx != 1) {
877 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
878 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
879 }
880
881 /* Turn on unused PA or LNA when not using 1T or 1R */
882 if (rt2x00dev->default_ant.rx != 1) {
883 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
884 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
885 }
886
887 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
888 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
889 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
890 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
891 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
892 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
893
894 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
895
896 rt2800_bbp_read(rt2x00dev, 4, &bbp);
897 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
898 rt2800_bbp_write(rt2x00dev, 4, bbp);
899
900 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 901 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 902 rt2800_bbp_write(rt2x00dev, 3, bbp);
903
8d0c9b65 904 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 905 if (conf_is_ht40(conf)) {
906 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
907 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
908 rt2800_bbp_write(rt2x00dev, 73, 0x16);
909 } else {
910 rt2800_bbp_write(rt2x00dev, 69, 0x16);
911 rt2800_bbp_write(rt2x00dev, 70, 0x08);
912 rt2800_bbp_write(rt2x00dev, 73, 0x11);
913 }
914 }
915
916 msleep(1);
917}
918
919static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
920 const int txpower)
921{
922 u32 reg;
923 u32 value = TXPOWER_G_TO_DEV(txpower);
924 u8 r1;
925
926 rt2800_bbp_read(rt2x00dev, 1, &r1);
927 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
928 rt2800_bbp_write(rt2x00dev, 1, r1);
929
930 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
938 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
939 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
940
941 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
946 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
947 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
948 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
949 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
950 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
951
952 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
953 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
954 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
955 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
956 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
957 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
958 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
959 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
960 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
961 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
962
963 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
964 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
965 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
966 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
967 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
968 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
969 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
970 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
971 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
972 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
973
974 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
975 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
976 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
977 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
978 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
979 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
980}
981
982static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
983 struct rt2x00lib_conf *libconf)
984{
985 u32 reg;
986
987 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
988 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
989 libconf->conf->short_frame_max_tx_count);
990 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
991 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 992 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
993}
994
995static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
996 struct rt2x00lib_conf *libconf)
997{
998 enum dev_state state =
999 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1000 STATE_SLEEP : STATE_AWAKE;
1001 u32 reg;
1002
1003 if (state == STATE_SLEEP) {
1004 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1005
1006 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1007 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1008 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1009 libconf->conf->listen_interval - 1);
1010 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1011 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1012
1013 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1014 } else {
f4450616
BZ		 1015 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1016 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1017 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1018 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1019 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1020
1021 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1022 }
1023}
1024
1025void rt2800_config(struct rt2x00_dev *rt2x00dev,
1026 struct rt2x00lib_conf *libconf,
1027 const unsigned int flags)
1028{
1029 /* Always recalculate LNA gain before changing configuration */
1030 rt2800_config_lna_gain(rt2x00dev, libconf);
1031
1032 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1033 rt2800_config_channel(rt2x00dev, libconf->conf,
1034 &libconf->rf, &libconf->channel);
1035 if (flags & IEEE80211_CONF_CHANGE_POWER)
1036 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1037 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1038 rt2800_config_retry_limit(rt2x00dev, libconf);
1039 if (flags & IEEE80211_CONF_CHANGE_PS)
1040 rt2800_config_ps(rt2x00dev, libconf);
1041}
1042EXPORT_SYMBOL_GPL(rt2800_config);
1043
1044/*
1045 * Link tuning
1046 */
1047void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1048{
1049 u32 reg;
1050
1051 /*
1052 * Update FCS error count from register.
1053 */
1054 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1055 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1056}
1057EXPORT_SYMBOL_GPL(rt2800_link_stats);
1058
1059static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1060{
1061 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1062 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1063 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1064 rt2x00_rt(rt2x00dev, RT3090) ||
1065 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1066 return 0x1c + (2 * rt2x00dev->lna_gain);
1067 else
1068 return 0x2e + rt2x00dev->lna_gain;
1069 }
1070
1071 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1072 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1073 else
1074 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1075}
1076
1077static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1078 struct link_qual *qual, u8 vgc_level)
1079{
1080 if (qual->vgc_level != vgc_level) {
1081 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1082 qual->vgc_level = vgc_level;
1083 qual->vgc_level_reg = vgc_level;
1084 }
1085}
1086
1087void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1088{
1089 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1090}
1091EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1092
1093void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1094 const u32 count)
1095{
8d0c9b65 1096 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1097 return;
1098
1099 /*
1100 * When RSSI is better then -80 increase VGC level with 0x10
1101 */
1102 rt2800_set_vgc(rt2x00dev, qual,
1103 rt2800_get_default_vgc(rt2x00dev) +
1104 ((qual->rssi > -80) * 0x10));
1105}
1106EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1107
1108/*
1109 * Initialization functions.
1110 */
1111int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1112{
1113 u32 reg;
d5385bfc 1114 u16 eeprom;
fcf51541
BZ		 1115 unsigned int i;
1116
a9dce149
GW		 1117 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1118 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1119 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1120 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1121 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1122 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1123 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1124
cea90e55 1125 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1126 /*
235faf9b 1127 * Wait until BBP and RF are ready.
fcf51541
BZ		 1128 */
1129 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1130 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1131 if (reg && reg != ~0)
1132 break;
1133 msleep(1);
1134 }
1135
1136 if (i == REGISTER_BUSY_COUNT) {
1137 ERROR(rt2x00dev, "Unstable hardware.\n");
1138 return -EBUSY;
1139 }
1140
1141 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1142 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1143 reg & ~0x00002000);
a9dce149
GW		 1144 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1145 /*
1146 * Reset DMA indexes
1147 */
1148 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1149 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1150 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1151 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1152 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1153 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1154 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1155 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1156 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1157
1158 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1159 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1160
fcf51541 1161 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
a9dce149 1162 }
fcf51541
BZ		 1163
1164 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1165 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1166 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1167 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1168
cea90e55 1169 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1170 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
ac394917 1171#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 1172 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1173 USB_MODE_RESET, REGISTER_TIMEOUT);
1174#endif
1175 }
1176
1177 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1178
1179 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1180 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1181 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1182 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1183 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1184 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1185
1186 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1187 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1188 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1189 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1190 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1191 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1192
1193 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1194 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1195
1196 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1197
1198 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1199 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1200 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1201 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1202 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1203 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1204 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1205 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1206
a9dce149
GW		 1207 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1208
1209 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1210 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1211 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1212 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1213
64522957 1214 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1215 rt2x00_rt(rt2x00dev, RT3090) ||
1216 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1217 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1218 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1219 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1220 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1221 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1222 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1223 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1224 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1225 0x0000002c);
1226 else
1227 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1228 0x0000000f);
1229 } else {
1230 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1231 }
1232 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1233 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1234 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1235
1236 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1237 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1238 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1239 } else {
1240 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1241 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1242 }
fcf51541
BZ		 1243 } else {
1244 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1245 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1246 }
1247
1248 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1249 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1250 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1251 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1252 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1253 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1254 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1255 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1256 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1257 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1258
1259 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1260 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1261 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1262 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1263 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1264
1265 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1266 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1267 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1268 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1269 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1270 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1271 else
1272 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1273 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1274 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1275 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1276
a9dce149
GW		 1277 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1278 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1279 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1280 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1281 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1282 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1283 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1284 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1285 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1286
fcf51541
BZ		 1287 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1288
a9dce149
GW		 1289 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1290 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1291 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1292 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1293 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1294 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1295 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1296 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1297
fcf51541
BZ		 1298 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1299 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1300 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1301 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1302 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1303 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1304 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1305 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1306 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1307
1308 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1309 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1310 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1311 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1312 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1313 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1314 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1315 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1316 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1317 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1318 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1319 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1320
1321 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1322 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1323 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1324 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1325 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1326 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1327 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1328 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1329 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1330 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1331 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1332 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1333
1334 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1335 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1336 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1337 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1338 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1339 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1340 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1341 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1342 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1343 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1344 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1345 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1346
1347 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1348 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1349 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1350 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1351 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1352 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1353 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1354 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1355 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1356 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1357 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1358 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1359 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1360
1361 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1362 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1363 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1364 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1365 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1366 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1367 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1368 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1369 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1370 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1371 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1372 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1373
1374 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1375 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1376 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1377 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1378 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1379 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1380 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1381 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1382 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1383 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1384 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1385 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1386
cea90e55 1387 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1388 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1389
1390 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1391 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1396 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1397 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1398 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1399 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1400 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1401 }
1402
1403 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1404 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1405
1406 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1407 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1408 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1409 IEEE80211_MAX_RTS_THRESHOLD);
1410 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1411 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1412
1413 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1414
a21c2ab4
HS		 1415 /*
1416 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1417 * time should be set to 16. However, the original Ralink driver uses
1418 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1419 * connection problems with 11g + CTS protection. Hence, use the same
1420 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1421 */
a9dce149 1422 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1423 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1424 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1425 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1426 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1427 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1428 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1429
fcf51541
BZ		 1430 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1431
1432 /*
1433 * ASIC will keep garbage value after boot, clear encryption keys.
1434 */
1435 for (i = 0; i < 4; i++)
1436 rt2800_register_write(rt2x00dev,
1437 SHARED_KEY_MODE_ENTRY(i), 0);
1438
1439 for (i = 0; i < 256; i++) {
1440 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1441 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1442 wcid, sizeof(wcid));
1443
1444 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1445 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1446 }
1447
1448 /*
1449 * Clear all beacons
1450 * For the Beacon base registers we only need to clear
1451 * the first byte since that byte contains the VALID and OWNER
1452 * bits which (when set to 0) will invalidate the entire beacon.
1453 */
1454 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1455 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1456 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1457 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1458 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1459 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1460 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1461 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1462
cea90e55 1463 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1464 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1465 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1466 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1467 }
1468
1469 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1470 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1471 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1472 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1473 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1474 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1475 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1476 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1477 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1478 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1479
1480 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1481 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1482 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1483 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1484 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1485 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1486 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1487 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1488 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1489 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1490
1491 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1492 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1493 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1494 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1495 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1496 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1497 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1498 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1499 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1500 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1501
1502 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1503 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1504 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1505 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1506 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1507 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1508
1509 /*
1510 * We must clear the error counters.
1511 * These registers are cleared on read,
1512 * so we may pass a useless variable to store the value.
1513 */
1514 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1515 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1516 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1517 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1518 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1519 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1520
1521 return 0;
1522}
1523EXPORT_SYMBOL_GPL(rt2800_init_registers);
1524
1525static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1526{
1527 unsigned int i;
1528 u32 reg;
1529
1530 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1531 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1532 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1533 return 0;
1534
1535 udelay(REGISTER_BUSY_DELAY);
1536 }
1537
1538 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1539 return -EACCES;
1540}
1541
1542static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1543{
1544 unsigned int i;
1545 u8 value;
1546
1547 /*
1548 * BBP was enabled after firmware was loaded,
1549 * but we need to reactivate it now.
1550 */
1551 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1552 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1553 msleep(1);
1554
1555 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1556 rt2800_bbp_read(rt2x00dev, 0, &value);
1557 if ((value != 0xff) && (value != 0x00))
1558 return 0;
1559 udelay(REGISTER_BUSY_DELAY);
1560 }
1561
1562 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1563 return -EACCES;
1564}
1565
1566int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1567{
1568 unsigned int i;
1569 u16 eeprom;
1570 u8 reg_id;
1571 u8 value;
1572
1573 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1574 rt2800_wait_bbp_ready(rt2x00dev)))
1575 return -EACCES;
1576
baff8006
HS		 1577 if (rt2800_is_305x_soc(rt2x00dev))
1578 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1579
fcf51541
BZ		 1580 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1581 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1582
1583 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1584 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1585 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1586 } else {
1587 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1588 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1589 }
1590
fcf51541 1591 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1592
d5385bfc 1593 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1594 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1595 rt2x00_rt(rt2x00dev, RT3090) ||
1596 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1597 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1598 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1599 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1600 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1601 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1602 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1603 } else {
1604 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1605 }
1606
fcf51541
BZ		 1607 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1608 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149
GW		 1609
1610 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1611 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1612 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1613 else
1614 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1615
fcf51541
BZ		 1616 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1617 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1618 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1619
d5385bfc 1620 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1621 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 1622 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 1623 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1624 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 1625 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1626 else
1627 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1628
baff8006
HS		 1629 if (rt2800_is_305x_soc(rt2x00dev))
1630 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1631 else
1632 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1633 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1634
64522957 1635 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1636 rt2x00_rt(rt2x00dev, RT3090) ||
1637 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1638 rt2800_bbp_read(rt2x00dev, 138, &value);
1639
1640 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1641 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1642 value |= 0x20;
1643 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1644 value &= ~0x02;
1645
1646 rt2800_bbp_write(rt2x00dev, 138, value);
1647 }
1648
e148b4c8 1649
fcf51541
BZ		 1650 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1651 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1652
1653 if (eeprom != 0xffff && eeprom != 0x0000) {
1654 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1655 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1656 rt2800_bbp_write(rt2x00dev, reg_id, value);
1657 }
1658 }
1659
1660 return 0;
1661}
1662EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1663
1664static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1665 bool bw40, u8 rfcsr24, u8 filter_target)
1666{
1667 unsigned int i;
1668 u8 bbp;
1669 u8 rfcsr;
1670 u8 passband;
1671 u8 stopband;
1672 u8 overtuned = 0;
1673
1674 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1675
1676 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1677 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1678 rt2800_bbp_write(rt2x00dev, 4, bbp);
1679
1680 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1681 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1682 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1683
1684 /*
1685 * Set power & frequency of passband test tone
1686 */
1687 rt2800_bbp_write(rt2x00dev, 24, 0);
1688
1689 for (i = 0; i < 100; i++) {
1690 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1691 msleep(1);
1692
1693 rt2800_bbp_read(rt2x00dev, 55, &passband);
1694 if (passband)
1695 break;
1696 }
1697
1698 /*
1699 * Set power & frequency of stopband test tone
1700 */
1701 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1702
1703 for (i = 0; i < 100; i++) {
1704 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1705 msleep(1);
1706
1707 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1708
1709 if ((passband - stopband) <= filter_target) {
1710 rfcsr24++;
1711 overtuned += ((passband - stopband) == filter_target);
1712 } else
1713 break;
1714
1715 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1716 }
1717
1718 rfcsr24 -= !!overtuned;
1719
1720 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1721 return rfcsr24;
1722}
1723
1724int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1725{
1726 u8 rfcsr;
1727 u8 bbp;
8cdd15e0
GW		 1728 u32 reg;
1729 u16 eeprom;
fcf51541 1730
d5385bfc 1731 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1732 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1733 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 1734 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 1735 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 1736 return 0;
1737
fcf51541
BZ		 1738 /*
1739 * Init RF calibration.
1740 */
1741 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1742 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1743 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1744 msleep(1);
1745 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1746 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1747
d5385bfc 1748 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1749 rt2x00_rt(rt2x00dev, RT3071) ||
1750 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1751 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1752 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1753 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1754 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1755 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1756 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1757 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1758 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1759 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1760 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1761 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1762 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1763 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1764 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1765 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1766 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1767 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1768 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1769 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1770 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1771 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1772 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1773 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1774 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1775 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1776 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1777 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1778 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1779 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1780 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1781 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1782 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1783 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1784 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1785 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1786 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1787 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1788 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1789 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1790 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1791 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1792 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1793 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1794 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1795 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1796 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1797 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1798 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1799 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1800 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1801 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1802 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 1803 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 1804 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1805 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1806 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1807 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1808 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1809 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1810 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1811 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1812 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1813 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1814 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1815 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1816 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1817 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1818 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1819 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1820 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1821 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1822 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1823 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1824 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1825 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1826 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1827 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1828 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1829 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1830 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1831 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1832 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1833 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 1834 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1835 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1836 return 0;
8cdd15e0
GW		 1837 }
1838
1839 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1840 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1841 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1842 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1843 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 1844 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1845 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 1846 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1847 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1848 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1849
1850 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1851
1852 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1853 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 1854 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1855 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 1856 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1857 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1858 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1859 else
1860 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1861 }
1862 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 1863 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1864 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1865 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1866 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 1867 }
1868
1869 /*
1870 * Set RX Filter calibration for 20MHz and 40MHz
1871 */
8cdd15e0
GW		 1872 if (rt2x00_rt(rt2x00dev, RT3070)) {
1873 rt2x00dev->calibration[0] =
1874 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1875 rt2x00dev->calibration[1] =
1876 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 1877 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1878 rt2x00_rt(rt2x00dev, RT3090) ||
1879 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1880 rt2x00dev->calibration[0] =
1881 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1882 rt2x00dev->calibration[1] =
1883 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 1884 }
fcf51541
BZ		 1885
1886 /*
1887 * Set back to initial state
1888 */
1889 rt2800_bbp_write(rt2x00dev, 24, 0);
1890
1891 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1892 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1893 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1894
1895 /*
1896 * set BBP back to BW20
1897 */
1898 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1899 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1900 rt2800_bbp_write(rt2x00dev, 4, bbp);
1901
d5385bfc 1902 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1903 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1904 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1905 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 1906 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1907
1908 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1909 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1910 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1911
1912 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1913 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 1914 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1915 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1916 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1917 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1918 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1919 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1920 }
8cdd15e0
GW		 1921 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1922 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1923 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1924 rt2x00_get_field16(eeprom,
1925 EEPROM_TXMIXER_GAIN_BG_VAL));
1926 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1927
64522957
GW		 1928 if (rt2x00_rt(rt2x00dev, RT3090)) {
1929 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1930
1931 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1932 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1933 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1934 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1935 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1936
1937 rt2800_bbp_write(rt2x00dev, 138, bbp);
1938 }
1939
1940 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1941 rt2x00_rt(rt2x00dev, RT3090) ||
1942 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1943 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1944 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1945 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1946 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1947 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1948 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1949 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1950
1951 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1952 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1953 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1954
1955 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1956 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1957 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1958
1959 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1960 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1961 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1962 }
1963
1964 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 1965 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 1966 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1967 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 1968 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1969 else
1970 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1971 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1972 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1973 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1974 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1975 }
1976
fcf51541
BZ		 1977 return 0;
1978}
1979EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 1980
30e84034
BZ		 1981int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1982{
1983 u32 reg;
1984
1985 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1986
1987 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1988}
1989EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1990
1991static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1992{
1993 u32 reg;
1994
31a4cf1f
GW		 1995 mutex_lock(&rt2x00dev->csr_mutex);
1996
1997 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 1998 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1999 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2000 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2001 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2002
2003 /* Wait until the EEPROM has been loaded */
2004 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2005
2006 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2007 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2008 (u32 *)&rt2x00dev->eeprom[i]);
2009 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2010 (u32 *)&rt2x00dev->eeprom[i + 2]);
2011 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2012 (u32 *)&rt2x00dev->eeprom[i + 4]);
2013 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2014 (u32 *)&rt2x00dev->eeprom[i + 6]);
2015
2016 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2017}
2018
2019void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2020{
2021 unsigned int i;
2022
2023 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2024 rt2800_efuse_read(rt2x00dev, i);
2025}
2026EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2027
38bd7b8a
BZ		 2028int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2029{
2030 u16 word;
2031 u8 *mac;
2032 u8 default_lna_gain;
2033
2034 /*
2035 * Start validation of the data that has been read.
2036 */
2037 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2038 if (!is_valid_ether_addr(mac)) {
2039 random_ether_addr(mac);
2040 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2041 }
2042
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2044 if (word == 0xffff) {
2045 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2046 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2047 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2048 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2049 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec
GW		 2050 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2051 rt2x00_rt(rt2x00dev, RT2870) ||
e148b4c8 2052 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2053 /*
2054 * There is a max of 2 RX streams for RT28x0 series
2055 */
2056 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2057 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2058 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2059 }
2060
2061 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2062 if (word == 0xffff) {
2063 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2064 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2065 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2066 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2067 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2068 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2069 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2070 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2071 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2072 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2073 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2074 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2075 }
2076
2077 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2078 if ((word & 0x00ff) == 0x00ff) {
2079 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2080 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2081 LED_MODE_TXRX_ACTIVITY);
2082 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2083 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2084 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2085 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2086 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2087 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2088 }
2089
2090 /*
2091 * During the LNA validation we are going to use
2092 * lna0 as correct value. Note that EEPROM_LNA
2093 * is never validated.
2094 */
2095 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2096 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2097
2098 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2099 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2100 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2101 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2102 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2103 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2104
2105 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2106 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2107 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2108 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2109 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2110 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2111 default_lna_gain);
2112 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2113
2114 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2115 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2116 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2117 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2118 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2119 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2120
2121 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2122 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2123 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2124 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2125 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2126 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2127 default_lna_gain);
2128 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2129
2130 return 0;
2131}
2132EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2133
2134int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2135{
2136 u32 reg;
2137 u16 value;
2138 u16 eeprom;
2139
2140 /*
2141 * Read EEPROM word for configuration.
2142 */
2143 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2144
2145 /*
2146 * Identify RF chipset.
2147 */
2148 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2149 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2150
49e721ec
GW		 2151 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2152 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2153
2154 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2155 !rt2x00_rt(rt2x00dev, RT2870) &&
2156 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2157 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2158 !rt2x00_rt(rt2x00dev, RT3070) &&
2159 !rt2x00_rt(rt2x00dev, RT3071) &&
2160 !rt2x00_rt(rt2x00dev, RT3090) &&
2161 !rt2x00_rt(rt2x00dev, RT3390) &&
2162 !rt2x00_rt(rt2x00dev, RT3572)) {
2163 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2164 return -ENODEV;
f273fe55 2165 }
714fa663 2166
5122d898
GW		 2167 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2168 !rt2x00_rf(rt2x00dev, RF2850) &&
2169 !rt2x00_rf(rt2x00dev, RF2720) &&
2170 !rt2x00_rf(rt2x00dev, RF2750) &&
2171 !rt2x00_rf(rt2x00dev, RF3020) &&
2172 !rt2x00_rf(rt2x00dev, RF2020) &&
2173 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2174 !rt2x00_rf(rt2x00dev, RF3022) &&
2175 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2176 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2177 return -ENODEV;
2178 }
2179
2180 /*
2181 * Identify default antenna configuration.
2182 */
2183 rt2x00dev->default_ant.tx =
2184 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2185 rt2x00dev->default_ant.rx =
2186 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2187
2188 /*
2189 * Read frequency offset and RF programming sequence.
2190 */
2191 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2192 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2193
2194 /*
2195 * Read external LNA informations.
2196 */
2197 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2198
2199 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2200 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2201 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2202 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2203
2204 /*
2205 * Detect if this device has an hardware controlled radio.
2206 */
2207 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2208 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2209
2210 /*
2211 * Store led settings, for correct led behaviour.
2212 */
2213#ifdef CONFIG_RT2X00_LIB_LEDS
2214 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2215 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2216 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2217
2218 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2219#endif /* CONFIG_RT2X00_LIB_LEDS */
2220
2221 return 0;
2222}
2223EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2224
4da2933f
BZ		 2225/*
2226 * RF value list for rt28x0
2227 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2228 */
2229static const struct rf_channel rf_vals[] = {
2230 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2231 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2232 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2233 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2234 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2235 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2236 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2237 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2238 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2239 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2240 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2241 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2242 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2243 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2244
2245 /* 802.11 UNI / HyperLan 2 */
2246 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2247 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2248 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2249 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2250 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2251 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2252 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2253 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2254 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2255 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2256 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2257 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2258
2259 /* 802.11 HyperLan 2 */
2260 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2261 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2262 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2263 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2264 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2265 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2266 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2267 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2268 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2269 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2270 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2271 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2272 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2273 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2274 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2275 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2276
2277 /* 802.11 UNII */
2278 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2279 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2280 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2281 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2282 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2283 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2284 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2285 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2286 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2287 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2288 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2289
2290 /* 802.11 Japan */
2291 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2292 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2293 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2294 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2295 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2296 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2297 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2298};
2299
2300/*
2301 * RF value list for rt3070
2302 * Supports: 2.4 GHz
2303 */
cce5fc45 2304static const struct rf_channel rf_vals_302x[] = {
4da2933f
BZ		 2305 {1, 241, 2, 2 },
2306 {2, 241, 2, 7 },
2307 {3, 242, 2, 2 },
2308 {4, 242, 2, 7 },
2309 {5, 243, 2, 2 },
2310 {6, 243, 2, 7 },
2311 {7, 244, 2, 2 },
2312 {8, 244, 2, 7 },
2313 {9, 245, 2, 2 },
2314 {10, 245, 2, 7 },
2315 {11, 246, 2, 2 },
2316 {12, 246, 2, 7 },
2317 {13, 247, 2, 2 },
2318 {14, 248, 2, 4 },
2319};
2320
2321int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2322{
4da2933f
BZ		 2323 struct hw_mode_spec *spec = &rt2x00dev->spec;
2324 struct channel_info *info;
2325 char *tx_power1;
2326 char *tx_power2;
2327 unsigned int i;
2328 u16 eeprom;
2329
93b6bd26
GW		 2330 /*
2331 * Disable powersaving as default on PCI devices.
2332 */
cea90e55 2333 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2334 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2335
4da2933f
BZ		 2336 /*
2337 * Initialize all hw fields.
2338 */
2339 rt2x00dev->hw->flags =
2340 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2341 IEEE80211_HW_SIGNAL_DBM |
2342 IEEE80211_HW_SUPPORTS_PS |
2343 IEEE80211_HW_PS_NULLFUNC_STACK;
2344
4da2933f
BZ		 2345 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2346 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2347 rt2x00_eeprom_addr(rt2x00dev,
2348 EEPROM_MAC_ADDR_0));
2349
2350 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2351
2352 /*
2353 * Initialize hw_mode information.
2354 */
2355 spec->supported_bands = SUPPORT_BAND_2GHZ;
2356 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2357
5122d898
GW		 2358 if (rt2x00_rf(rt2x00dev, RF2820) ||
2359 rt2x00_rf(rt2x00dev, RF2720) ||
6c0fe265 2360 rt2x00_rf(rt2x00dev, RF3052)) {
4da2933f
BZ		 2361 spec->num_channels = 14;
2362 spec->channels = rf_vals;
5122d898 2363 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2364 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2365 spec->num_channels = ARRAY_SIZE(rf_vals);
2366 spec->channels = rf_vals;
5122d898
GW		 2367 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2368 rt2x00_rf(rt2x00dev, RF2020) ||
2369 rt2x00_rf(rt2x00dev, RF3021) ||
2370 rt2x00_rf(rt2x00dev, RF3022)) {
cce5fc45
GW		 2371 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2372 spec->channels = rf_vals_302x;
4da2933f
BZ		 2373 }
2374
2375 /*
2376 * Initialize HT information.
2377 */
5122d898 2378 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2379 spec->ht.ht_supported = true;
2380 else
2381 spec->ht.ht_supported = false;
2382
2caaa5d3
HS		 2383 /*
2384 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2385 * reception problems with HT40 capable 11n APs
2386 */
4da2933f 2387 spec->ht.cap =
4da2933f
BZ		 2388 IEEE80211_HT_CAP_GRN_FLD |
2389 IEEE80211_HT_CAP_SGI_20 |
2390 IEEE80211_HT_CAP_SGI_40 |
2391 IEEE80211_HT_CAP_TX_STBC |
9a418af5 2392 IEEE80211_HT_CAP_RX_STBC;
4da2933f
BZ		 2393 spec->ht.ampdu_factor = 3;
2394 spec->ht.ampdu_density = 4;
2395 spec->ht.mcs.tx_params =
2396 IEEE80211_HT_MCS_TX_DEFINED |
2397 IEEE80211_HT_MCS_TX_RX_DIFF |
2398 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2399 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2400
2401 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2402 case 3:
2403 spec->ht.mcs.rx_mask[2] = 0xff;
2404 case 2:
2405 spec->ht.mcs.rx_mask[1] = 0xff;
2406 case 1:
2407 spec->ht.mcs.rx_mask[0] = 0xff;
2408 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2409 break;
2410 }
2411
2412 /*
2413 * Create channel information array
2414 */
2415 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2416 if (!info)
2417 return -ENOMEM;
2418
2419 spec->channels_info = info;
2420
2421 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2422 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2423
2424 for (i = 0; i < 14; i++) {
2425 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2426 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2427 }
2428
2429 if (spec->num_channels > 14) {
2430 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2431 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2432
2433 for (i = 14; i < spec->num_channels; i++) {
2434 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2435 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2436 }
2437 }
2438
2439 return 0;
2440}
2441EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2442
2ce33995
BZ		 2443/*
2444 * IEEE80211 stack callback functions.
2445 */
2446static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2447 u32 *iv32, u16 *iv16)
2448{
2449 struct rt2x00_dev *rt2x00dev = hw->priv;
2450 struct mac_iveiv_entry iveiv_entry;
2451 u32 offset;
2452
2453 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2454 rt2800_register_multiread(rt2x00dev, offset,
2455 &iveiv_entry, sizeof(iveiv_entry));
2456
855da5e0
JL		 2457 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2458 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2459}
2460
2461static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2462{
2463 struct rt2x00_dev *rt2x00dev = hw->priv;
2464 u32 reg;
2465 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2466
2467 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2468 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2469 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2470
2471 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2472 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2473 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2474
2475 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2476 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2477 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2478
2479 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2480 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2481 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2482
2483 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2484 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2485 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2486
2487 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2488 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2489 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2490
2491 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2492 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2493 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2494
2495 return 0;
2496}
2497
2498static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2499 const struct ieee80211_tx_queue_params *params)
2500{
2501 struct rt2x00_dev *rt2x00dev = hw->priv;
2502 struct data_queue *queue;
2503 struct rt2x00_field32 field;
2504 int retval;
2505 u32 reg;
2506 u32 offset;
2507
2508 /*
2509 * First pass the configuration through rt2x00lib, that will
2510 * update the queue settings and validate the input. After that
2511 * we are free to update the registers based on the value
2512 * in the queue parameter.
2513 */
2514 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2515 if (retval)
2516 return retval;
2517
2518 /*
2519 * We only need to perform additional register initialization
2520 * for WMM queues/
2521 */
2522 if (queue_idx >= 4)
2523 return 0;
2524
2525 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2526
2527 /* Update WMM TXOP register */
2528 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2529 field.bit_offset = (queue_idx & 1) * 16;
2530 field.bit_mask = 0xffff << field.bit_offset;
2531
2532 rt2800_register_read(rt2x00dev, offset, &reg);
2533 rt2x00_set_field32(&reg, field, queue->txop);
2534 rt2800_register_write(rt2x00dev, offset, reg);
2535
2536 /* Update WMM registers */
2537 field.bit_offset = queue_idx * 4;
2538 field.bit_mask = 0xf << field.bit_offset;
2539
2540 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2541 rt2x00_set_field32(&reg, field, queue->aifs);
2542 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2543
2544 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2545 rt2x00_set_field32(&reg, field, queue->cw_min);
2546 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2547
2548 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2549 rt2x00_set_field32(&reg, field, queue->cw_max);
2550 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2551
2552 /* Update EDCA registers */
2553 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2554
2555 rt2800_register_read(rt2x00dev, offset, &reg);
2556 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2557 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2558 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2559 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2560 rt2800_register_write(rt2x00dev, offset, reg);
2561
2562 return 0;
2563}
2564
2565static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2566{
2567 struct rt2x00_dev *rt2x00dev = hw->priv;
2568 u64 tsf;
2569 u32 reg;
2570
2571 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2572 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2573 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2574 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2575
2576 return tsf;
2577}
2578
2579const struct ieee80211_ops rt2800_mac80211_ops = {
2580 .tx = rt2x00mac_tx,
2581 .start = rt2x00mac_start,
2582 .stop = rt2x00mac_stop,
2583 .add_interface = rt2x00mac_add_interface,
2584 .remove_interface = rt2x00mac_remove_interface,
2585 .config = rt2x00mac_config,
2586 .configure_filter = rt2x00mac_configure_filter,
2587 .set_tim = rt2x00mac_set_tim,
2588 .set_key = rt2x00mac_set_key,
2589 .get_stats = rt2x00mac_get_stats,
2590 .get_tkip_seq = rt2800_get_tkip_seq,
2591 .set_rts_threshold = rt2800_set_rts_threshold,
2592 .bss_info_changed = rt2x00mac_bss_info_changed,
2593 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2594 .get_tsf = rt2800_get_tsf,
2595 .rfkill_poll = rt2x00mac_rfkill_poll,
2596};
2597EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
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