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wil6210: Fix potential memory leaks on error paths
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
e5ef5bad 780 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
ba08910e
SG		 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
951{
952 struct data_queue *queue = rt2x00dev->bcn;
953 struct queue_entry *entry;
954 int i, bcn_num = 0;
955 u64 off, reg = 0;
956 u32 bssid_dw1;
957
958 /*
959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
960 */
961 for (i = 0; i < queue->limit; i++) {
962 entry = &queue->entries[i];
963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
964 continue;
965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
966 reg |= off << (8 * bcn_num);
967 bcn_num++;
968 }
969
970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
971
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
974
975 /*
976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
977 */
978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
980 bcn_num > 0 ? bcn_num - 1 : 0);
981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
982}
983
f0194b2d
GW		 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
985{
986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
988 unsigned int beacon_base;
739fd940 989 unsigned int padding_len;
d76dfc61 990 u32 orig_reg, reg;
f0bda571 991 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 992
993 /*
994 * Disable beaconing while we are reloading the beacon data,
995 * otherwise we might be sending out invalid data.
996 */
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 998 orig_reg = reg;
f0194b2d
GW		 999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002 /*
1003 * Add space for the TXWI in front of the skb.
1004 */
f0bda571 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1006
1007 /*
1008 * Register descriptor details in skb frame descriptor.
1009 */
1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011 skbdesc->desc = entry->skb->data;
f0bda571 1012 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1013
1014 /*
1015 * Add the TXWI for the beacon to the skb.
1016 */
0c5879bc 1017 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1018
1019 /*
1020 * Dump beacon to userspace through debugfs.
1021 */
1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024 /*
739fd940 1025 * Write entire beacon with TXWI and padding to register.
f0194b2d 1026 */
739fd940 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1028 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1030 /* skb freed by skb_pad() on failure */
1031 entry->skb = NULL;
1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033 return;
1034 }
1035
21c6af6b
GJ		 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
739fd940
WK		 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039 entry->skb->len + padding_len);
ba08910e
SG		 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042 /*
1043 * Change global beacons settings.
1044 */
1045 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1046
1047 /*
bc0df75a 1048 * Restore beaconing state.
f0194b2d 1049 */
bc0df75a 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1051
1052 /*
1053 * Clean up beacon skb.
1054 */
1055 dev_kfree_skb_any(entry->skb);
1056 entry->skb = NULL;
1057}
50e888ea 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1059
69cf36a4 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1061 unsigned int index)
fdb87251
HS		 1062{
1063 int i;
0879f875 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1065 unsigned int beacon_base;
1066
21c6af6b 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1068
1069 /*
1070 * For the Beacon base registers we only need to clear
1071 * the whole TXWI which (when set to 0) will invalidate
1072 * the entire beacon.
1073 */
f0bda571 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076}
1077
69cf36a4
HS		 1078void rt2800_clear_beacon(struct queue_entry *entry)
1079{
1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1081 u32 orig_reg, reg;
69cf36a4
HS		 1082
1083 /*
1084 * Disable beaconing while we are reloading the beacon data,
1085 * otherwise we might be sending out invalid data.
1086 */
bc0df75a
SG		 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088 reg = orig_reg;
69cf36a4
HS		 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092 /*
1093 * Clear beacon.
1094 */
77f7c0f3 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1097
ba08910e
SG		 1098 /*
1099 * Change global beacons settings.
1100 */
1101 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1102 /*
bc0df75a 1103 * Restore beaconing state.
69cf36a4 1104 */
bc0df75a 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1106}
1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
f4450616
BZ		 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110const struct rt2x00debug rt2800_rt2x00debug = {
1111 .owner = THIS_MODULE,
1112 .csr = {
1113 .read = rt2800_register_read,
1114 .write = rt2800_register_write,
1115 .flags = RT2X00DEBUGFS_OFFSET,
1116 .word_base = CSR_REG_BASE,
1117 .word_size = sizeof(u32),
1118 .word_count = CSR_REG_SIZE / sizeof(u32),
1119 },
1120 .eeprom = {
3e38d3da
GJ		 1121 /* NOTE: The local EEPROM access functions can't
1122 * be used here, use the generic versions instead.
1123 */
f4450616
BZ		 1124 .read = rt2x00_eeprom_read,
1125 .write = rt2x00_eeprom_write,
1126 .word_base = EEPROM_BASE,
1127 .word_size = sizeof(u16),
1128 .word_count = EEPROM_SIZE / sizeof(u16),
1129 },
1130 .bbp = {
1131 .read = rt2800_bbp_read,
1132 .write = rt2800_bbp_write,
1133 .word_base = BBP_BASE,
1134 .word_size = sizeof(u8),
1135 .word_count = BBP_SIZE / sizeof(u8),
1136 },
1137 .rf = {
1138 .read = rt2x00_rf_read,
1139 .write = rt2800_rf_write,
1140 .word_base = RF_BASE,
1141 .word_size = sizeof(u32),
1142 .word_count = RF_SIZE / sizeof(u32),
1143 },
f2bd7f16
AA		 1144 .rfcsr = {
1145 .read = rt2800_rfcsr_read,
1146 .write = rt2800_rfcsr_write,
1147 .word_base = RFCSR_BASE,
1148 .word_size = sizeof(u8),
1149 .word_count = RFCSR_SIZE / sizeof(u8),
1150 },
f4450616
BZ		 1151};
1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156{
1157 u32 reg;
1158
a89534ed
WH		 1159 if (rt2x00_rt(rt2x00dev, RT3290)) {
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162 } else {
99bdf51a
GW		 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1165 }
f4450616
BZ		 1166}
1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169#ifdef CONFIG_RT2X00_LIB_LEDS
1170static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171 enum led_brightness brightness)
1172{
1173 struct rt2x00_led *led =
1174 container_of(led_cdev, struct rt2x00_led, led_dev);
1175 unsigned int enabled = brightness != LED_OFF;
1176 unsigned int bg_mode =
1177 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1178 unsigned int polarity =
1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180 EEPROM_FREQ_LED_POLARITY);
1181 unsigned int ledmode =
1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183 EEPROM_FREQ_LED_MODE);
44704e5d 1184 u32 reg;
f4450616 1185
44704e5d
LE		 1186 /* Check for SoC (SOC devices don't support MCU requests) */
1187 if (rt2x00_is_soc(led->rt2x00dev)) {
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190 /* Set LED Polarity */
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193 /* Set LED Mode */
1194 if (led->type == LED_TYPE_RADIO) {
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196 enabled ? 3 : 0);
1197 } else if (led->type == LED_TYPE_ASSOC) {
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199 enabled ? 3 : 0);
1200 } else if (led->type == LED_TYPE_QUALITY) {
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202 enabled ? 3 : 0);
1203 }
1204
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207 } else {
1208 if (led->type == LED_TYPE_RADIO) {
1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210 enabled ? 0x20 : 0);
1211 } else if (led->type == LED_TYPE_ASSOC) {
1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214 } else if (led->type == LED_TYPE_QUALITY) {
1215 /*
1216 * The brightness is divided into 6 levels (0 - 5),
1217 * The specs tell us the following levels:
1218 * 0, 1 ,3, 7, 15, 31
1219 * to determine the level in a simple way we can simply
1220 * work with bitshifting:
1221 * (1 << level) - 1
1222 */
1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224 (1 << brightness / (LED_FULL / 6)) - 1,
1225 polarity);
1226 }
f4450616
BZ		 1227 }
1228}
1229
b3579d6a 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1231 struct rt2x00_led *led, enum led_type type)
1232{
1233 led->rt2x00dev = rt2x00dev;
1234 led->type = type;
1235 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1236 led->flags = LED_INITIALIZED;
1237}
f4450616
BZ		 1238#endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240/*
1241 * Configuration handlers.
1242 */
a2b1328a
HS		 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244 const u8 *address,
1245 int wcid)
f4450616
BZ		 1246{
1247 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1248 u32 offset;
1249
1250 offset = MAC_WCID_ENTRY(wcid);
1251
1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253 if (address)
1254 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256 rt2800_register_multiwrite(rt2x00dev, offset,
1257 &wcid_entry, sizeof(wcid_entry));
1258}
1259
1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261{
1262 u32 offset;
1263 offset = MAC_WCID_ATTR_ENTRY(wcid);
1264 rt2800_register_write(rt2x00dev, offset, 0);
1265}
1266
1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268 int wcid, u32 bssidx)
1269{
1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271 u32 reg;
1272
1273 /*
1274 * The BSS Idx numbers is split in a main value of 3 bits,
1275 * and a extended field for adding one additional bit to the value.
1276 */
1277 rt2800_register_read(rt2x00dev, offset, &reg);
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280 (bssidx & 0x8) >> 3);
1281 rt2800_register_write(rt2x00dev, offset, reg);
1282}
1283
1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_crypto *crypto,
1286 struct ieee80211_key_conf *key)
1287{
f4450616
BZ		 1288 struct mac_iveiv_entry iveiv_entry;
1289 u32 offset;
1290 u32 reg;
1291
1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
e4a0ab34
ID		 1294 if (crypto->cmd == SET_KEY) {
1295 rt2800_register_read(rt2x00dev, offset, &reg);
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298 /*
1299 * Both the cipher as the BSS Idx numbers are split in a main
1300 * value of 3 bits, and a extended field for adding one additional
1301 * bit to the value.
1302 */
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304 (crypto->cipher & 0x7));
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308 rt2800_register_write(rt2x00dev, offset, reg);
1309 } else {
a2b1328a
HS		 1310 /* Delete the cipher without touching the bssidx */
1311 rt2800_register_read(rt2x00dev, offset, &reg);
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1317 }
f4450616
BZ		 1318
1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322 if ((crypto->cipher == CIPHER_TKIP) ||
1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324 (crypto->cipher == CIPHER_AES))
1325 iveiv_entry.iv[3] |= 0x20;
1326 iveiv_entry.iv[3] |= key->keyidx << 6;
1327 rt2800_register_multiwrite(rt2x00dev, offset,
1328 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1329}
1330
1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332 struct rt2x00lib_crypto *crypto,
1333 struct ieee80211_key_conf *key)
1334{
1335 struct hw_key_entry key_entry;
1336 struct rt2x00_field32 field;
1337 u32 offset;
1338 u32 reg;
1339
1340 if (crypto->cmd == SET_KEY) {
1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343 memcpy(key_entry.key, crypto->key,
1344 sizeof(key_entry.key));
1345 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346 sizeof(key_entry.tx_mic));
1347 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348 sizeof(key_entry.rx_mic));
1349
1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351 rt2800_register_multiwrite(rt2x00dev, offset,
1352 &key_entry, sizeof(key_entry));
1353 }
1354
1355 /*
1356 * The cipher types are stored over multiple registers
1357 * starting with SHARED_KEY_MODE_BASE each word will have
1358 * 32 bits and contains the cipher types for 2 bssidx each.
1359 * Using the correct defines correctly will cause overhead,
1360 * so just calculate the correct offset.
1361 */
1362 field.bit_offset = 4 * (key->hw_key_idx % 8);
1363 field.bit_mask = 0x7 << field.bit_offset;
1364
1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367 rt2800_register_read(rt2x00dev, offset, &reg);
1368 rt2x00_set_field32(&reg, field,
1369 (crypto->cmd == SET_KEY) * crypto->cipher);
1370 rt2800_register_write(rt2x00dev, offset, reg);
1371
1372 /*
1373 * Update WCID information
1374 */
a2b1328a
HS		 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377 crypto->bssidx);
1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
a2b1328a 1384static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1385{
a2b1328a 1386 struct mac_wcid_entry wcid_entry;
1ed3811c 1387 int idx;
a2b1328a 1388 u32 offset;
1ed3811c
HS		 1389
1390 /*
a2b1328a
HS		 1391 * Search for the first free WCID entry and return the corresponding
1392 * index.
1ed3811c
HS		 1393 *
1394 * Make sure the WCID starts _after_ the last possible shared key
1395 * entry (>32).
1396 *
1397 * Since parts of the pairwise key table might be shared with
1398 * the beacon frame buffers 6 & 7 we should only write into the
1399 * first 222 entries.
1400 */
1401 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1402 offset = MAC_WCID_ENTRY(idx);
1403 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1404 sizeof(wcid_entry));
1405 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1406 return idx;
1407 }
a2b1328a
HS		 1408
1409 /*
1410 * Use -1 to indicate that we don't have any more space in the WCID
1411 * table.
1412 */
1ed3811c
HS		 1413 return -1;
1414}
1415
f4450616
BZ		 1416int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1417 struct rt2x00lib_crypto *crypto,
1418 struct ieee80211_key_conf *key)
1419{
1420 struct hw_key_entry key_entry;
1421 u32 offset;
1422
1423 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1424 /*
1425 * Allow key configuration only for STAs that are
1426 * known by the hw.
1427 */
1428 if (crypto->wcid < 0)
f4450616 1429 return -ENOSPC;
a2b1328a 1430 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1431
1432 memcpy(key_entry.key, crypto->key,
1433 sizeof(key_entry.key));
1434 memcpy(key_entry.tx_mic, crypto->tx_mic,
1435 sizeof(key_entry.tx_mic));
1436 memcpy(key_entry.rx_mic, crypto->rx_mic,
1437 sizeof(key_entry.rx_mic));
1438
1439 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1440 rt2800_register_multiwrite(rt2x00dev, offset,
1441 &key_entry, sizeof(key_entry));
1442 }
1443
1444 /*
1445 * Update WCID information
1446 */
a2b1328a 1447 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1448
1449 return 0;
1450}
1451EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1452
a2b1328a
HS		 1453int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1454 struct ieee80211_sta *sta)
1455{
1456 int wcid;
1457 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1458
1459 /*
1460 * Find next free WCID.
1461 */
1462 wcid = rt2800_find_wcid(rt2x00dev);
1463
1464 /*
1465 * Store selected wcid even if it is invalid so that we can
1466 * later decide if the STA is uploaded into the hw.
1467 */
1468 sta_priv->wcid = wcid;
1469
1470 /*
1471 * No space left in the device, however, we can still communicate
1472 * with the STA -> No error.
1473 */
1474 if (wcid < 0)
1475 return 0;
1476
1477 /*
1478 * Clean up WCID attributes and write STA address to the device.
1479 */
1480 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1481 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1482 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1483 rt2x00lib_get_bssidx(rt2x00dev, vif));
1484 return 0;
1485}
1486EXPORT_SYMBOL_GPL(rt2800_sta_add);
1487
1488int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1489{
1490 /*
1491 * Remove WCID entry, no need to clean the attributes as they will
1492 * get renewed when the WCID is reused.
1493 */
1494 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1495
1496 return 0;
1497}
1498EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1499
f4450616
BZ		 1500void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1501 const unsigned int filter_flags)
1502{
1503 u32 reg;
1504
1505 /*
1506 * Start configuration steps.
1507 * Note that the version error will always be dropped
1508 * and broadcast frames will always be accepted since
1509 * there is no filter for it at this time.
1510 */
1511 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1513 !(filter_flags & FIF_FCSFAIL));
1514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1515 !(filter_flags & FIF_PLCPFAIL));
1516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1517 !(filter_flags & FIF_PROMISC_IN_BSS));
1518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1519 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1521 !(filter_flags & FIF_ALLMULTI));
1522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1525 !(filter_flags & FIF_CONTROL));
1526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1527 !(filter_flags & FIF_CONTROL));
1528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1529 !(filter_flags & FIF_CONTROL));
1530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1531 !(filter_flags & FIF_CONTROL));
1532 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1533 !(filter_flags & FIF_CONTROL));
1534 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1535 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1538 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1540 !(filter_flags & FIF_CONTROL));
1541 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1542}
1543EXPORT_SYMBOL_GPL(rt2800_config_filter);
1544
1545void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1546 struct rt2x00intf_conf *conf, const unsigned int flags)
1547{
f4450616 1548 u32 reg;
fa8b4b22 1549 bool update_bssid = false;
f4450616
BZ		 1550
1551 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1552 /*
1553 * Enable synchronisation.
1554 */
1555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1557 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1558
1559 if (conf->sync == TSF_SYNC_AP_NONE) {
1560 /*
1561 * Tune beacon queue transmit parameters for AP mode
1562 */
1563 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1564 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1565 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1566 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1567 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1568 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1569 } else {
1570 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1571 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1572 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1573 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1574 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1575 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1576 }
f4450616
BZ		 1577 }
1578
1579 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1580 if (flags & CONFIG_UPDATE_TYPE &&
1581 conf->sync == TSF_SYNC_AP_NONE) {
1582 /*
1583 * The BSSID register has to be set to our own mac
1584 * address in AP mode.
1585 */
1586 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1587 update_bssid = true;
1588 }
1589
c600c826
ID		 1590 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1591 reg = le32_to_cpu(conf->mac[1]);
1592 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1593 conf->mac[1] = cpu_to_le32(reg);
1594 }
f4450616
BZ		 1595
1596 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1597 conf->mac, sizeof(conf->mac));
1598 }
1599
fa8b4b22 1600 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1601 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1602 reg = le32_to_cpu(conf->bssid[1]);
1603 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1604 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1605 conf->bssid[1] = cpu_to_le32(reg);
1606 }
f4450616
BZ		 1607
1608 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1609 conf->bssid, sizeof(conf->bssid));
1610 }
1611}
1612EXPORT_SYMBOL_GPL(rt2800_config_intf);
1613
87c1915d
HS		 1614static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1615 struct rt2x00lib_erp *erp)
1616{
1617 bool any_sta_nongf = !!(erp->ht_opmode &
1618 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1619 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1620 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1621 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1622 u32 reg;
1623
1624 /* default protection rate for HT20: OFDM 24M */
1625 mm20_rate = gf20_rate = 0x4004;
1626
1627 /* default protection rate for HT40: duplicate OFDM 24M */
1628 mm40_rate = gf40_rate = 0x4084;
1629
1630 switch (protection) {
1631 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1632 /*
1633 * All STAs in this BSS are HT20/40 but there might be
1634 * STAs not supporting greenfield mode.
1635 * => Disable protection for HT transmissions.
1636 */
1637 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1638
1639 break;
1640 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1641 /*
1642 * All STAs in this BSS are HT20 or HT20/40 but there
1643 * might be STAs not supporting greenfield mode.
1644 * => Protect all HT40 transmissions.
1645 */
1646 mm20_mode = gf20_mode = 0;
1647 mm40_mode = gf40_mode = 2;
1648
1649 break;
1650 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1651 /*
1652 * Nonmember protection:
1653 * According to 802.11n we _should_ protect all
1654 * HT transmissions (but we don't have to).
1655 *
1656 * But if cts_protection is enabled we _shall_ protect
1657 * all HT transmissions using a CCK rate.
1658 *
1659 * And if any station is non GF we _shall_ protect
1660 * GF transmissions.
1661 *
1662 * We decide to protect everything
1663 * -> fall through to mixed mode.
1664 */
1665 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1666 /*
1667 * Legacy STAs are present
1668 * => Protect all HT transmissions.
1669 */
1670 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1671
1672 /*
1673 * If erp protection is needed we have to protect HT
1674 * transmissions with CCK 11M long preamble.
1675 */
1676 if (erp->cts_protection) {
1677 /* don't duplicate RTS/CTS in CCK mode */
1678 mm20_rate = mm40_rate = 0x0003;
1679 gf20_rate = gf40_rate = 0x0003;
1680 }
1681 break;
6403eab1 1682 }
87c1915d
HS		 1683
1684 /* check for STAs not supporting greenfield mode */
1685 if (any_sta_nongf)
1686 gf20_mode = gf40_mode = 2;
1687
1688 /* Update HT protection config */
1689 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1690 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1691 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1692 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1693
1694 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1695 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1696 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1697 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1698
1699 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1700 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1701 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1702 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1703
1704 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1705 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1706 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1707 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1708}
1709
02044643
HS		 1710void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1711 u32 changed)
f4450616
BZ		 1712{
1713 u32 reg;
1714
02044643
HS		 1715 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1716 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1717 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1718 !!erp->short_preamble);
1719 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1720 !!erp->short_preamble);
1721 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1722 }
f4450616 1723
02044643
HS		 1724 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1725 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1726 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1727 erp->cts_protection ? 2 : 0);
1728 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1729 }
f4450616 1730
02044643
HS		 1731 if (changed & BSS_CHANGED_BASIC_RATES) {
1732 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1733 erp->basic_rates);
1734 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1735 }
f4450616 1736
02044643
HS		 1737 if (changed & BSS_CHANGED_ERP_SLOT) {
1738 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1739 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1740 erp->slot_time);
1741 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1742
02044643
HS		 1743 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1744 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1745 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1746 }
f4450616 1747
02044643
HS		 1748 if (changed & BSS_CHANGED_BEACON_INT) {
1749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1750 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1751 erp->beacon_int * 16);
1752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1753 }
87c1915d
HS		 1754
1755 if (changed & BSS_CHANGED_HT)
1756 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1757}
1758EXPORT_SYMBOL_GPL(rt2800_config_erp);
1759
872834df
GW		 1760static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1761{
1762 u32 reg;
1763 u16 eeprom;
1764 u8 led_ctrl, led_g_mode, led_r_mode;
1765
1766 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1767 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1768 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1769 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1770 } else {
1771 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1772 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1773 }
1774 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1775
1776 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1777 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1778 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1779 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1780 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1781 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1782 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1783 if (led_ctrl == 0 || led_ctrl > 0x40) {
1784 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1785 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1786 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1787 } else {
1788 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1789 (led_g_mode << 2) | led_r_mode, 1);
1790 }
1791 }
1792}
1793
d96aa640
RJH		 1794static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1795 enum antenna ant)
1796{
1797 u32 reg;
1798 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1799 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1800
1801 if (rt2x00_is_pci(rt2x00dev)) {
1802 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1803 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1804 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1805 } else if (rt2x00_is_usb(rt2x00dev))
1806 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1807 eesk_pin, 0);
1808
99bdf51a
GW		 1809 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1810 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1811 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1812 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1813}
1814
f4450616
BZ		 1815void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1816{
1817 u8 r1;
1818 u8 r3;
d96aa640 1819 u16 eeprom;
f4450616
BZ		 1820
1821 rt2800_bbp_read(rt2x00dev, 1, &r1);
1822 rt2800_bbp_read(rt2x00dev, 3, &r3);
1823
872834df 1824 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1825 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1826 rt2800_config_3572bt_ant(rt2x00dev);
1827
f4450616
BZ		 1828 /*
1829 * Configure the TX antenna.
1830 */
d96aa640 1831 switch (ant->tx_chain_num) {
f4450616
BZ		 1832 case 1:
1833 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1834 break;
1835 case 2:
872834df 1836 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1837 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1838 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1839 else
1840 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1841 break;
1842 case 3:
4788ac1e 1843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1844 break;
1845 }
1846
1847 /*
1848 * Configure the RX antenna.
1849 */
d96aa640 1850 switch (ant->rx_chain_num) {
f4450616 1851 case 1:
d96aa640
RJH		 1852 if (rt2x00_rt(rt2x00dev, RT3070) ||
1853 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1854 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1855 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1856 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1857 EEPROM_NIC_CONF1, &eeprom);
1858 if (rt2x00_get_field16(eeprom,
1859 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1860 rt2800_set_ant_diversity(rt2x00dev,
1861 rt2x00dev->default_ant.rx);
1862 }
f4450616
BZ		 1863 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1864 break;
1865 case 2:
872834df 1866 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1867 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1868 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1869 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1870 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1871 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1872 } else {
1873 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1874 }
f4450616
BZ		 1875 break;
1876 case 3:
1877 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1878 break;
1879 }
1880
1881 rt2800_bbp_write(rt2x00dev, 3, r3);
1882 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1883
1884 if (rt2x00_rt(rt2x00dev, RT3593)) {
1885 if (ant->rx_chain_num == 1)
1886 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1887 else
1888 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1889 }
f4450616
BZ		 1890}
1891EXPORT_SYMBOL_GPL(rt2800_config_ant);
1892
1893static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1894 struct rt2x00lib_conf *libconf)
1895{
1896 u16 eeprom;
1897 short lna_gain;
1898
1899 if (libconf->rf.channel <= 14) {
3e38d3da 1900 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1901 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1902 } else if (libconf->rf.channel <= 64) {
3e38d3da 1903 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1904 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1905 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1906 if (rt2x00_rt(rt2x00dev, RT3593)) {
1907 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1908 lna_gain = rt2x00_get_field16(eeprom,
1909 EEPROM_EXT_LNA2_A1);
1910 } else {
1911 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1912 lna_gain = rt2x00_get_field16(eeprom,
1913 EEPROM_RSSI_BG2_LNA_A1);
1914 }
f4450616 1915 } else {
f36bb0ca
GJ		 1916 if (rt2x00_rt(rt2x00dev, RT3593)) {
1917 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1918 lna_gain = rt2x00_get_field16(eeprom,
1919 EEPROM_EXT_LNA2_A2);
1920 } else {
1921 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1922 lna_gain = rt2x00_get_field16(eeprom,
1923 EEPROM_RSSI_A2_LNA_A2);
1924 }
f4450616
BZ		 1925 }
1926
1927 rt2x00dev->lna_gain = lna_gain;
1928}
1929
3f1b8739
GJ		 1930#define FREQ_OFFSET_BOUND 0x5f
1931
1932static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1933{
1934 u8 freq_offset, prev_freq_offset;
1935 u8 rfcsr, prev_rfcsr;
1936
1937 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1938 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1939
1940 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1941 prev_rfcsr = rfcsr;
1942
1943 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1944 if (rfcsr == prev_rfcsr)
1945 return;
1946
1947 if (rt2x00_is_usb(rt2x00dev)) {
1948 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1949 freq_offset, prev_rfcsr);
1950 return;
1951 }
1952
1953 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1954 while (prev_freq_offset != freq_offset) {
1955 if (prev_freq_offset < freq_offset)
1956 prev_freq_offset++;
1957 else
1958 prev_freq_offset--;
1959
1960 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1961 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1962
1963 usleep_range(1000, 1500);
1964 }
1965}
1966
06855ef4
GW		 1967static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1968 struct ieee80211_conf *conf,
1969 struct rf_channel *rf,
1970 struct channel_info *info)
f4450616
BZ		 1971{
1972 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1973
d96aa640 1974 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1975 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1976
d96aa640 1977 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1978 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1979 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1980 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1981 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1982
1983 if (rf->channel > 14) {
1984 /*
1985 * When TX power is below 0, we should increase it by 7 to
25985edc 1986 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1987 * However this means that values between 0 and 7 have
1988 * double meaning, and we should set a 7DBm boost flag.
1989 */
1990 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1991 (info->default_power1 >= 0));
f4450616 1992
8d1331b3
ID		 1993 if (info->default_power1 < 0)
1994 info->default_power1 += 7;
f4450616 1995
8d1331b3 1996 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1997
1998 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1999 (info->default_power2 >= 0));
f4450616 2000
8d1331b3
ID		 2001 if (info->default_power2 < 0)
2002 info->default_power2 += 7;
f4450616 2003
8d1331b3 2004 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 2005 } else {
8d1331b3
ID		 2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2007 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 2008 }
2009
2010 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2011
2012 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2013 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2014 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2015 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2016
2017 udelay(200);
2018
2019 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2020 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2021 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2022 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2023
2024 udelay(200);
2025
2026 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2027 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2028 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2029 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2030}
2031
06855ef4
GW		 2032static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2033 struct ieee80211_conf *conf,
2034 struct rf_channel *rf,
2035 struct channel_info *info)
f4450616 2036{
3a1c0128 2037 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2038 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2039
2040 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2041
2042 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2043 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2044 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2045
2046 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2047 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2048 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2049
2050 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2051 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2052 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2053
5a673964 2054 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2055 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2056 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2057
2058 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2059 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2060 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2061 rt2x00dev->default_ant.rx_chain_num <= 1);
2062 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2063 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2064 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2065 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2066 rt2x00dev->default_ant.tx_chain_num <= 1);
2067 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2068 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2069 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2070
f4450616
BZ		 2071 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2072 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2073 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2074
f1f12f98
SG		 2075 if (rt2x00_rt(rt2x00dev, RT3390)) {
2076 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2077 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2078 } else {
3a1c0128
GW		 2079 if (conf_is_ht40(conf)) {
2080 calib_tx = drv_data->calibration_bw40;
2081 calib_rx = drv_data->calibration_bw40;
2082 } else {
2083 calib_tx = drv_data->calibration_bw20;
2084 calib_rx = drv_data->calibration_bw20;
2085 }
f1f12f98
SG		 2086 }
2087
2088 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2089 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2090 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2091
2092 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2093 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2094 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2095
71976907 2096 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2097 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2098 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2099
2100 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2101 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2102 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2103 msleep(1);
2104 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2105 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2106}
2107
872834df
GW		 2108static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2109 struct ieee80211_conf *conf,
2110 struct rf_channel *rf,
2111 struct channel_info *info)
2112{
3a1c0128 2113 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2114 u8 rfcsr;
2115 u32 reg;
2116
2117 if (rf->channel <= 14) {
5d137dff
GW		 2118 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2119 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2120 } else {
2121 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2122 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2123 }
2124
2125 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2126 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2127
2128 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2129 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2130 if (rf->channel <= 14)
2131 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2132 else
2133 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2134 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2135
2136 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2137 if (rf->channel <= 14)
2138 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2139 else
2140 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2141 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2142
2143 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2144 if (rf->channel <= 14) {
2145 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2146 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2147 info->default_power1);
872834df
GW		 2148 } else {
2149 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2150 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2151 (info->default_power1 & 0x3) |
2152 ((info->default_power1 & 0xC) << 1));
2153 }
2154 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2155
2156 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2157 if (rf->channel <= 14) {
2158 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2159 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2160 info->default_power2);
872834df
GW		 2161 } else {
2162 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2163 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2164 (info->default_power2 & 0x3) |
2165 ((info->default_power2 & 0xC) << 1));
2166 }
2167 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2168
2169 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2170 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2171 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2172 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2173 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2174 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2175 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2176 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2177 if (rf->channel <= 14) {
2178 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2179 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2180 }
2181 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2182 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2183 } else {
2184 switch (rt2x00dev->default_ant.tx_chain_num) {
2185 case 1:
2186 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2187 case 2:
2188 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2189 break;
2190 }
2191
2192 switch (rt2x00dev->default_ant.rx_chain_num) {
2193 case 1:
2194 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2195 case 2:
2196 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2197 break;
2198 }
2199 }
2200 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2201
2202 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2203 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2204 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2205
3a1c0128
GW		 2206 if (conf_is_ht40(conf)) {
2207 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2208 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2209 } else {
2210 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2211 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2212 }
872834df
GW		 2213
2214 if (rf->channel <= 14) {
2215 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2216 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2217 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2218 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2219 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2220 rfcsr = 0x4c;
2221 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2222 drv_data->txmixer_gain_24g);
2223 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2224 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2225 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2226 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2227 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2228 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2229 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2230 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2231 } else {
58b8ae14
GW		 2232 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2233 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2234 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2235 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2236 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2237 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2238 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2239 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2240 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2241 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2242 rfcsr = 0x7a;
2243 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2244 drv_data->txmixer_gain_5g);
2245 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2246 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2247 if (rf->channel <= 64) {
2248 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2249 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2250 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2251 } else if (rf->channel <= 128) {
2252 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2253 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2254 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2255 } else {
2256 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2257 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2258 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2259 }
2260 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2261 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2262 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2263 }
2264
99bdf51a
GW		 2265 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2266 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2267 if (rf->channel <= 14)
99bdf51a 2268 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2269 else
99bdf51a
GW		 2270 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2271 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2272
2273 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2274 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2275 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2276}
60687ba7 2277
f42b0465
GJ		 2278static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2279 struct ieee80211_conf *conf,
2280 struct rf_channel *rf,
2281 struct channel_info *info)
2282{
2283 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2284 u8 txrx_agc_fc;
2285 u8 txrx_h20m;
2286 u8 rfcsr;
2287 u8 bbp;
2288 const bool txbf_enabled = false; /* TODO */
2289
2290 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2291 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2292 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2293 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2294 rt2800_bbp_write(rt2x00dev, 109, bbp);
2295
2296 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2297 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2298 rt2800_bbp_write(rt2x00dev, 110, bbp);
2299
2300 if (rf->channel <= 14) {
2301 /* Restore BBP 25 & 26 for 2.4 GHz */
2302 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2303 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2304 } else {
2305 /* Hard code BBP 25 & 26 for 5GHz */
2306
2307 /* Enable IQ Phase correction */
2308 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2309 /* Setup IQ Phase correction value */
2310 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2311 }
2312
2313 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2314 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2315
2316 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2317 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2318 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2319
2320 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2321 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2322 if (rf->channel <= 14)
2323 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2324 else
2325 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2326 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2327
2328 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2329 if (rf->channel <= 14) {
2330 rfcsr = 0;
2331 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2332 info->default_power1 & 0x1f);
2333 } else {
2334 if (rt2x00_is_usb(rt2x00dev))
2335 rfcsr = 0x40;
2336
2337 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2338 ((info->default_power1 & 0x18) << 1) |
2339 (info->default_power1 & 7));
2340 }
2341 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2342
2343 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2344 if (rf->channel <= 14) {
2345 rfcsr = 0;
2346 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2347 info->default_power2 & 0x1f);
2348 } else {
2349 if (rt2x00_is_usb(rt2x00dev))
2350 rfcsr = 0x40;
2351
2352 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2353 ((info->default_power2 & 0x18) << 1) |
2354 (info->default_power2 & 7));
2355 }
2356 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2357
2358 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2359 if (rf->channel <= 14) {
2360 rfcsr = 0;
2361 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2362 info->default_power3 & 0x1f);
2363 } else {
2364 if (rt2x00_is_usb(rt2x00dev))
2365 rfcsr = 0x40;
2366
2367 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2368 ((info->default_power3 & 0x18) << 1) |
2369 (info->default_power3 & 7));
2370 }
2371 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2372
2373 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2374 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2375 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2376 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2377 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2378 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2379 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2380 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2381 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2382
2383 switch (rt2x00dev->default_ant.tx_chain_num) {
2384 case 3:
2385 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2386 /* fallthrough */
2387 case 2:
2388 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2389 /* fallthrough */
2390 case 1:
2391 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2392 break;
2393 }
2394
2395 switch (rt2x00dev->default_ant.rx_chain_num) {
2396 case 3:
2397 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2398 /* fallthrough */
2399 case 2:
2400 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2401 /* fallthrough */
2402 case 1:
2403 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2404 break;
2405 }
2406 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2407
e979a8ab 2408 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2409
2410 if (conf_is_ht40(conf)) {
2411 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2412 RFCSR24_TX_AGC_FC);
2413 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2414 RFCSR24_TX_H20M);
2415 } else {
2416 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2417 RFCSR24_TX_AGC_FC);
2418 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2419 RFCSR24_TX_H20M);
2420 }
2421
2422 /* NOTE: the reference driver does not writes the new value
2423 * back to RFCSR 32
2424 */
2425 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2426 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2427
2428 if (rf->channel <= 14)
2429 rfcsr = 0xa0;
2430 else
2431 rfcsr = 0x80;
2432 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2433
2434 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2435 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2436 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2437 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2438
2439 /* Band selection */
2440 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2441 if (rf->channel <= 14)
2442 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2443 else
2444 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2445 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2446
2447 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2448 if (rf->channel <= 14)
2449 rfcsr = 0x3c;
2450 else
2451 rfcsr = 0x20;
2452 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2453
2454 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2455 if (rf->channel <= 14)
2456 rfcsr = 0x1a;
2457 else
2458 rfcsr = 0x12;
2459 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2460
2461 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2462 if (rf->channel >= 1 && rf->channel <= 14)
2463 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2464 else if (rf->channel >= 36 && rf->channel <= 64)
2465 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2466 else if (rf->channel >= 100 && rf->channel <= 128)
2467 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2468 else
2469 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2470 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2471
2472 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2473 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2474 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2475
2476 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2477
2478 if (rf->channel <= 14) {
2479 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2480 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2481 } else {
2482 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2483 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2484 }
2485
2486 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2487 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2488 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2489
2490 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2491 if (rf->channel <= 14) {
2492 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2493 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2494 } else {
2495 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2496 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2497 }
2498 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2499
2500 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2501 if (rf->channel <= 14)
2502 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2503 else
2504 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2505
2506 if (txbf_enabled)
2507 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2508
2509 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2510
2511 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2512 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2513 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2514
2515 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2516 if (rf->channel <= 14)
2517 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2518 else
2519 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2520 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2521
2522 if (rf->channel <= 14) {
2523 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2524 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2525 } else {
2526 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2527 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2528 }
2529
2530 /* Initiate VCO calibration */
2531 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2532 if (rf->channel <= 14) {
2533 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2534 } else {
2535 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2536 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2537 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2538 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2539 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2540 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2541 }
2542 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2543
2544 if (rf->channel >= 1 && rf->channel <= 14) {
2545 rfcsr = 0x23;
2546 if (txbf_enabled)
2547 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2548 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2549
2550 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2551 } else if (rf->channel >= 36 && rf->channel <= 64) {
2552 rfcsr = 0x36;
2553 if (txbf_enabled)
2554 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2555 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2556
2557 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2558 } else if (rf->channel >= 100 && rf->channel <= 128) {
2559 rfcsr = 0x32;
2560 if (txbf_enabled)
2561 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2562 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2563
2564 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2565 } else {
2566 rfcsr = 0x30;
2567 if (txbf_enabled)
2568 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2569 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2570
2571 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2572 }
2573}
2574
7573cb5b 2575#define POWER_BOUND 0x27
8f821098 2576#define POWER_BOUND_5G 0x2b
0c9e5fb9 2577
a89534ed
WH		 2578static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2579 struct ieee80211_conf *conf,
2580 struct rf_channel *rf,
2581 struct channel_info *info)
2582{
2583 u8 rfcsr;
2584
2585 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2586 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2587 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2588 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2589 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2590
2591 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2592 if (info->default_power1 > POWER_BOUND)
2593 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2594 else
2595 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2596 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2597
0c9e5fb9 2598 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2599
2600 if (rf->channel <= 14) {
2601 if (rf->channel == 6)
2602 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2603 else
2604 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2605
2606 if (rf->channel >= 1 && rf->channel <= 6)
2607 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2608 else if (rf->channel >= 7 && rf->channel <= 11)
2609 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2610 else if (rf->channel >= 12 && rf->channel <= 14)
2611 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2612 }
2613}
2614
03839951
DG		 2615static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2616 struct ieee80211_conf *conf,
2617 struct rf_channel *rf,
2618 struct channel_info *info)
2619{
2620 u8 rfcsr;
2621
2622 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2623 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2624
2625 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2626 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2627 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2628
2629 if (info->default_power1 > POWER_BOUND)
2630 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2631 else
2632 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2633
2634 if (info->default_power2 > POWER_BOUND)
2635 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2636 else
2637 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2638
0c9e5fb9 2639 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2640
2641 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2642 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2643 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2644
2645 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2646 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2647 else
2648 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2649
2650 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2651 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2652 else
2653 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2654
2655 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2656 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2657
2658 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2659
2660 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2661}
2662
60687ba7 2663static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2664 struct ieee80211_conf *conf,
2665 struct rf_channel *rf,
2666 struct channel_info *info)
2667{
2668 u8 rfcsr;
adde5882
GJ		 2669
2670 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2671 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2672 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2673 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2674 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2675
2676 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2677 if (info->default_power1 > POWER_BOUND)
2678 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2679 else
2680 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2681 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2682
cff3d1f0
ZL		 2683 if (rt2x00_rt(rt2x00dev, RT5392)) {
2684 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2685 if (info->default_power2 > POWER_BOUND)
7573cb5b 2686 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2687 else
2688 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2689 info->default_power2);
2690 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2691 }
2692
adde5882 2693 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2694 if (rt2x00_rt(rt2x00dev, RT5392)) {
2695 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2696 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2697 }
adde5882
GJ		 2698 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2699 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2700 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2701 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2702 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2703
0c9e5fb9 2704 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2705
adde5882
GJ		 2706 if (rf->channel <= 14) {
2707 int idx = rf->channel-1;
2708
c429dfef 2709 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2710 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2711 /* r55/r59 value array of channel 1~14 */
2712 static const char r55_bt_rev[] = {0x83, 0x83,
2713 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2714 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2715 static const char r59_bt_rev[] = {0x0e, 0x0e,
2716 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2717 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2718
2719 rt2800_rfcsr_write(rt2x00dev, 55,
2720 r55_bt_rev[idx]);
2721 rt2800_rfcsr_write(rt2x00dev, 59,
2722 r59_bt_rev[idx]);
2723 } else {
2724 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2725 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2726 0x88, 0x88, 0x86, 0x85, 0x84};
2727
2728 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2729 }
2730 } else {
2731 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2732 static const char r55_nonbt_rev[] = {0x23, 0x23,
2733 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2734 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2735 static const char r59_nonbt_rev[] = {0x07, 0x07,
2736 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2737 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2738
2739 rt2800_rfcsr_write(rt2x00dev, 55,
2740 r55_nonbt_rev[idx]);
2741 rt2800_rfcsr_write(rt2x00dev, 59,
2742 r59_nonbt_rev[idx]);
2ed71884 2743 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2744 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2745 static const char r59_non_bt[] = {0x8f, 0x8f,
2746 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2747 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2748
2749 rt2800_rfcsr_write(rt2x00dev, 59,
2750 r59_non_bt[idx]);
2751 }
2752 }
2753 }
60687ba7
RST		 2754}
2755
8f821098
SG		 2756static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2757 struct ieee80211_conf *conf,
2758 struct rf_channel *rf,
2759 struct channel_info *info)
2760{
2761 u8 rfcsr, ep_reg;
d5ae7a6b 2762 u32 reg;
8f821098
SG		 2763 int power_bound;
2764
2765 /* TODO */
2766 const bool is_11b = false;
2767 const bool is_type_ep = false;
2768
d5ae7a6b
SG		 2769 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2770 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2771 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2772 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2773
2774 /* Order of values on rf_channel entry: N, K, mod, R */
2775 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2776
2777 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2778 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2779 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2780 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2781 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2782
2783 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2784 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2785 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2786 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2787
2788 if (rf->channel <= 14) {
2789 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2790 /* FIXME: RF11 owerwrite ? */
2791 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2792 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2793 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2794 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2795 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2796 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2797 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2798 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2799 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2800 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2801 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2802 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2803 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2804 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2805 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2806 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2807 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2808 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2809 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2810 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2811 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2812 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2813 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2814 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2815 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2816 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2817 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2818 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2819
2820 /* TODO RF27 <- tssi */
2821
2822 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2823 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2824 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2825
2826 if (is_11b) {
2827 /* CCK */
2828 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2829 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2830 if (is_type_ep)
2831 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2832 else
2833 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2834 } else {
2835 /* OFDM */
2836 if (is_type_ep)
2837 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2838 else
2839 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2840 }
2841
2842 power_bound = POWER_BOUND;
2843 ep_reg = 0x2;
2844 } else {
2845 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2846 /* FIMXE: RF11 overwrite */
2847 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2848 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2849 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2850 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2851 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2852 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2853 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2854 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2855 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2856 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2857 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2858 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2859 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2860 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2861
2862 /* TODO RF27 <- tssi */
2863
2864 if (rf->channel >= 36 && rf->channel <= 64) {
2865
2866 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2867 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2868 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2869 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2870 if (rf->channel <= 50)
2871 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2872 else if (rf->channel >= 52)
2873 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2874 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2875 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2876 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2877 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2878 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2879 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2880 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2881 if (rf->channel <= 50) {
2882 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2883 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2884 } else if (rf->channel >= 52) {
2885 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2886 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2887 }
2888
2889 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2890 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2891 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2892
2893 } else if (rf->channel >= 100 && rf->channel <= 165) {
2894
2895 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2896 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2897 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2898 if (rf->channel <= 153) {
2899 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2900 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2901 } else if (rf->channel >= 155) {
2902 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2903 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2904 }
2905 if (rf->channel <= 138) {
2906 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2907 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2908 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2909 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2910 } else if (rf->channel >= 140) {
2911 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2912 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2913 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2914 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2915 }
2916 if (rf->channel <= 124)
2917 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2918 else if (rf->channel >= 126)
2919 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2920 if (rf->channel <= 138)
2921 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2922 else if (rf->channel >= 140)
2923 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2924 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2925 if (rf->channel <= 138)
2926 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2927 else if (rf->channel >= 140)
2928 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2929 if (rf->channel <= 128)
2930 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2931 else if (rf->channel >= 130)
2932 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2933 if (rf->channel <= 116)
2934 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2935 else if (rf->channel >= 118)
2936 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2937 if (rf->channel <= 138)
2938 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2939 else if (rf->channel >= 140)
2940 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2941 if (rf->channel <= 116)
2942 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2943 else if (rf->channel >= 118)
2944 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2945 }
2946
2947 power_bound = POWER_BOUND_5G;
2948 ep_reg = 0x3;
2949 }
2950
2951 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2952 if (info->default_power1 > power_bound)
2953 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2954 else
2955 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2956 if (is_type_ep)
2957 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2958 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2959
2960 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2961 if (info->default_power2 > power_bound)
8f821098
SG		 2962 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2963 else
2964 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2965 if (is_type_ep)
2966 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2967 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2968
2969 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2970 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2971 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2972
2973 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2974 rt2x00dev->default_ant.tx_chain_num >= 1);
2975 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2976 rt2x00dev->default_ant.tx_chain_num == 2);
2977 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2978
2979 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2980 rt2x00dev->default_ant.rx_chain_num >= 1);
2981 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2982 rt2x00dev->default_ant.rx_chain_num == 2);
2983 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2984
2985 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2986 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2987
2988 if (conf_is_ht40(conf))
2989 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2990 else
2991 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2992
2993 if (!is_11b) {
2994 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2995 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2996 }
2997
2998 /* TODO proper frequency adjustment */
0c9e5fb9 2999 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 3000
3001 /* TODO merge with others */
3002 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3003 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3004 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 3005
3006 /* BBP settings */
3007 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3008 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3009 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3010
3011 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3012 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3013 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3014 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3015
3016 /* GLRT band configuration */
3017 rt2800_bbp_write(rt2x00dev, 195, 128);
3018 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3019 rt2800_bbp_write(rt2x00dev, 195, 129);
3020 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3021 rt2800_bbp_write(rt2x00dev, 195, 130);
3022 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3023 rt2800_bbp_write(rt2x00dev, 195, 131);
3024 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3025 rt2800_bbp_write(rt2x00dev, 195, 133);
3026 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3027 rt2800_bbp_write(rt2x00dev, 195, 124);
3028 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3029}
3030
5bc2dd06
SG		 3031static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3032 const unsigned int word,
3033 const u8 value)
3034{
3035 u8 chain, reg;
3036
3037 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3038 rt2800_bbp_read(rt2x00dev, 27, &reg);
3039 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3040 rt2800_bbp_write(rt2x00dev, 27, reg);
3041
3042 rt2800_bbp_write(rt2x00dev, word, value);
3043 }
3044}
3045
8756130b
SG		 3046static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3047{
3048 u8 cal;
3049
415e3f2f 3050 /* TX0 IQ Gain */
8756130b 3051 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3052 if (channel <= 14)
3053 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3054 else if (channel >= 36 && channel <= 64)
3055 cal = rt2x00_eeprom_byte(rt2x00dev,
3056 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3057 else if (channel >= 100 && channel <= 138)
3058 cal = rt2x00_eeprom_byte(rt2x00dev,
3059 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3060 else if (channel >= 140 && channel <= 165)
3061 cal = rt2x00_eeprom_byte(rt2x00dev,
3062 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3063 else
3064 cal = 0;
8756130b
SG		 3065 rt2800_bbp_write(rt2x00dev, 159, cal);
3066
415e3f2f 3067 /* TX0 IQ Phase */
8756130b 3068 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3069 if (channel <= 14)
3070 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3071 else if (channel >= 36 && channel <= 64)
3072 cal = rt2x00_eeprom_byte(rt2x00dev,
3073 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3074 else if (channel >= 100 && channel <= 138)
3075 cal = rt2x00_eeprom_byte(rt2x00dev,
3076 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3077 else if (channel >= 140 && channel <= 165)
3078 cal = rt2x00_eeprom_byte(rt2x00dev,
3079 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3080 else
3081 cal = 0;
8756130b
SG		 3082 rt2800_bbp_write(rt2x00dev, 159, cal);
3083
415e3f2f 3084 /* TX1 IQ Gain */
8756130b 3085 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3086 if (channel <= 14)
3087 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3088 else if (channel >= 36 && channel <= 64)
3089 cal = rt2x00_eeprom_byte(rt2x00dev,
3090 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3091 else if (channel >= 100 && channel <= 138)
3092 cal = rt2x00_eeprom_byte(rt2x00dev,
3093 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3094 else if (channel >= 140 && channel <= 165)
3095 cal = rt2x00_eeprom_byte(rt2x00dev,
3096 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3097 else
3098 cal = 0;
8756130b
SG		 3099 rt2800_bbp_write(rt2x00dev, 159, cal);
3100
415e3f2f 3101 /* TX1 IQ Phase */
8756130b 3102 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3103 if (channel <= 14)
3104 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3105 else if (channel >= 36 && channel <= 64)
3106 cal = rt2x00_eeprom_byte(rt2x00dev,
3107 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3108 else if (channel >= 100 && channel <= 138)
3109 cal = rt2x00_eeprom_byte(rt2x00dev,
3110 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3111 else if (channel >= 140 && channel <= 165)
3112 cal = rt2x00_eeprom_byte(rt2x00dev,
3113 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3114 else
3115 cal = 0;
8756130b
SG		 3116 rt2800_bbp_write(rt2x00dev, 159, cal);
3117
415e3f2f
SG		 3118 /* FIXME: possible RX0, RX1 callibration ? */
3119
8756130b
SG		 3120 /* RF IQ compensation control */
3121 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3122 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3123 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3124
3125 /* RF IQ imbalance compensation control */
3126 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3127 cal = rt2x00_eeprom_byte(rt2x00dev,
3128 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3129 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3130}
3131
97aa03f1
GJ		 3132static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3133 unsigned int channel,
3134 char txpower)
3135{
fc739cfe
GJ		 3136 if (rt2x00_rt(rt2x00dev, RT3593))
3137 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3138
97aa03f1
GJ		 3139 if (channel <= 14)
3140 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3141
3142 if (rt2x00_rt(rt2x00dev, RT3593))
3143 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3144 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3145 else
3146 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3147}
3148
f4450616
BZ		 3149static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3150 struct ieee80211_conf *conf,
3151 struct rf_channel *rf,
3152 struct channel_info *info)
3153{
3154 u32 reg;
3155 unsigned int tx_pin;
a89534ed 3156 u8 bbp, rfcsr;
f4450616 3157
97aa03f1
GJ		 3158 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3159 info->default_power1);
3160 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3161 info->default_power2);
c0a14369
GJ		 3162 if (rt2x00dev->default_ant.tx_chain_num > 2)
3163 info->default_power3 =
3164 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3165 info->default_power3);
46323e11 3166
5aa57015
GW		 3167 switch (rt2x00dev->chip.rf) {
3168 case RF2020:
3169 case RF3020:
3170 case RF3021:
3171 case RF3022:
3172 case RF3320:
06855ef4 3173 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3174 break;
3175 case RF3052:
872834df 3176 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3177 break;
f42b0465
GJ		 3178 case RF3053:
3179 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3180 break;
a89534ed
WH		 3181 case RF3290:
3182 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3183 break;
03839951
DG		 3184 case RF3322:
3185 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3186 break;
3b9b74ba 3187 case RF3070:
ccf91bd6 3188 case RF5360:
ac0372ab 3189 case RF5362:
5aa57015 3190 case RF5370:
2ed71884 3191 case RF5372:
5aa57015 3192 case RF5390:
cff3d1f0 3193 case RF5392:
adde5882 3194 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3195 break;
8f821098
SG		 3196 case RF5592:
3197 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3198 break;
5aa57015 3199 default:
06855ef4 3200 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3201 }
f4450616 3202
3b9b74ba
SG		 3203 if (rt2x00_rf(rt2x00dev, RF3070) ||
3204 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3205 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed 3206 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3207 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3208 rt2x00_rf(rt2x00dev, RF5370) ||
3209 rt2x00_rf(rt2x00dev, RF5372) ||
3210 rt2x00_rf(rt2x00dev, RF5390) ||
3211 rt2x00_rf(rt2x00dev, RF5392)) {
3212 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3213 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3214 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3215 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3216
3217 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3218 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3219 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3220 }
3221
f4450616
BZ		 3222 /*
3223 * Change BBP settings
3224 */
03839951
DG		 3225 if (rt2x00_rt(rt2x00dev, RT3352)) {
3226 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3227 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3228 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3229 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3230 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3231 if (rf->channel > 14) {
3232 /* Disable CCK Packet detection on 5GHz */
3233 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3234 } else {
3235 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3236 }
3237
3238 if (conf_is_ht40(conf))
3239 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3240 else
3241 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3242
3243 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3244 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3245 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3246 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3247 } else {
3248 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3249 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3250 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3251 rt2800_bbp_write(rt2x00dev, 86, 0);
3252 }
f4450616
BZ		 3253
3254 if (rf->channel <= 14) {
2ed71884 3255 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3256 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3257 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3258 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3259 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3260 } else {
f42b0465
GJ		 3261 if (rt2x00_rt(rt2x00dev, RT3593))
3262 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3263 else
3264 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3265 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3266 }
f42b0465
GJ		 3267 if (rt2x00_rt(rt2x00dev, RT3593))
3268 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3269 }
f42b0465 3270
f4450616 3271 } else {
872834df
GW		 3272 if (rt2x00_rt(rt2x00dev, RT3572))
3273 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3274 else if (rt2x00_rt(rt2x00dev, RT3593))
3275 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3276 else
3277 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3278
f42b0465
GJ		 3279 if (rt2x00_rt(rt2x00dev, RT3593))
3280 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3281
c429dfef 3282 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3283 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3284 else
3285 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3286 }
3287
3288 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3289 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3290 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3291 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3292 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3293
872834df
GW		 3294 if (rt2x00_rt(rt2x00dev, RT3572))
3295 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3296
f4450616
BZ		 3297 tx_pin = 0;
3298
bb16d488
GJ		 3299 switch (rt2x00dev->default_ant.tx_chain_num) {
3300 case 3:
3301 /* Turn on tertiary PAs */
3302 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3303 rf->channel > 14);
3304 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3305 rf->channel <= 14);
3306 /* fall-through */
3307 case 2:
3308 /* Turn on secondary PAs */
65f31b5e
GW		 3309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3310 rf->channel > 14);
3311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3312 rf->channel <= 14);
bb16d488
GJ		 3313 /* fall-through */
3314 case 1:
3315 /* Turn on primary PAs */
3316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3317 rf->channel > 14);
c429dfef 3318 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3320 else
3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3322 rf->channel <= 14);
3323 break;
f4450616
BZ		 3324 }
3325
bb16d488
GJ		 3326 switch (rt2x00dev->default_ant.rx_chain_num) {
3327 case 3:
3328 /* Turn on tertiary LNAs */
3329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3331 /* fall-through */
3332 case 2:
3333 /* Turn on secondary LNAs */
f4450616
BZ		 3334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3336 /* fall-through */
3337 case 1:
3338 /* Turn on primary LNAs */
3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3341 break;
f4450616
BZ		 3342 }
3343
f4450616
BZ		 3344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3346
3347 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3348
733aec6a 3349 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3350 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3351
733aec6a
GJ		 3352 /* AGC init */
3353 if (rf->channel <= 14)
3354 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3355 else
3356 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3357
3358 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3359 }
3360
f42b0465 3361 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3362 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3363
60751001
GJ		 3364 /* Band selection */
3365 if (rt2x00_is_usb(rt2x00dev) ||
3366 rt2x00_is_pcie(rt2x00dev)) {
3367 /* GPIO #8 controls all paths */
f42b0465
GJ		 3368 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3369 if (rf->channel <= 14)
3370 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3371 else
3372 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3373 }
f42b0465 3374
60751001
GJ		 3375 /* LNA PE control. */
3376 if (rt2x00_is_usb(rt2x00dev)) {
3377 /* GPIO #4 controls PE0 and PE1,
3378 * GPIO #7 controls PE2
3379 */
f42b0465
GJ		 3380 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3381 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3382
f42b0465
GJ		 3383 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3384 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3385 } else if (rt2x00_is_pcie(rt2x00dev)) {
3386 /* GPIO #4 controls PE0, PE1 and PE2 */
3387 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3388 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3389 }
3390
60751001
GJ		 3391 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3392
f42b0465
GJ		 3393 /* AGC init */
3394 if (rf->channel <= 14)
3395 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3396 else
3397 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3398
3399 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3400
3401 usleep_range(1000, 1500);
3402 }
3403
6803141b
SG		 3404 if (rt2x00_rt(rt2x00dev, RT5592)) {
3405 rt2800_bbp_write(rt2x00dev, 195, 141);
3406 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3407
8ba0ebf3
SG		 3408 /* AGC init */
3409 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3410 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3411
8756130b 3412 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3413 }
3414
f4450616
BZ		 3415 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3416 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3417 rt2800_bbp_write(rt2x00dev, 4, bbp);
3418
3419 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3420 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3421 rt2800_bbp_write(rt2x00dev, 3, bbp);
3422
8d0c9b65 3423 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3424 if (conf_is_ht40(conf)) {
3425 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3426 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3427 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3428 } else {
3429 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3430 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3431 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3432 }
3433 }
3434
3435 msleep(1);
977206d7
HS		 3436
3437 /*
3438 * Clear channel statistic counters
3439 */
3440 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3441 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3442 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3443
3444 /*
3445 * Clear update flag
3446 */
3447 if (rt2x00_rt(rt2x00dev, RT3352)) {
3448 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3449 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3450 rt2800_bbp_write(rt2x00dev, 49, bbp);
3451 }
f4450616
BZ		 3452}
3453
9e33a355
HS		 3454static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3455{
3456 u8 tssi_bounds[9];
3457 u8 current_tssi;
3458 u16 eeprom;
3459 u8 step;
3460 int i;
3461
6e956da2
SG		 3462 /*
3463 * First check if temperature compensation is supported.
3464 */
3465 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3466 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3467 return 0;
3468
9e33a355
HS		 3469 /*
3470 * Read TSSI boundaries for temperature compensation from
3471 * the EEPROM.
3472 *
3473 * Array idx 0 1 2 3 4 5 6 7 8
3474 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3475 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3476 */
3477 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 3478 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3479 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3480 EEPROM_TSSI_BOUND_BG1_MINUS4);
3481 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3482 EEPROM_TSSI_BOUND_BG1_MINUS3);
3483
3e38d3da 3484 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3485 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3486 EEPROM_TSSI_BOUND_BG2_MINUS2);
3487 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3488 EEPROM_TSSI_BOUND_BG2_MINUS1);
3489
3e38d3da 3490 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3491 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3492 EEPROM_TSSI_BOUND_BG3_REF);
3493 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3494 EEPROM_TSSI_BOUND_BG3_PLUS1);
3495
3e38d3da 3496 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3497 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3498 EEPROM_TSSI_BOUND_BG4_PLUS2);
3499 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3500 EEPROM_TSSI_BOUND_BG4_PLUS3);
3501
3e38d3da 3502 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3503 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3504 EEPROM_TSSI_BOUND_BG5_PLUS4);
3505
3506 step = rt2x00_get_field16(eeprom,
3507 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3508 } else {
3e38d3da 3509 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3510 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3511 EEPROM_TSSI_BOUND_A1_MINUS4);
3512 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3513 EEPROM_TSSI_BOUND_A1_MINUS3);
3514
3e38d3da 3515 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3516 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3517 EEPROM_TSSI_BOUND_A2_MINUS2);
3518 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3519 EEPROM_TSSI_BOUND_A2_MINUS1);
3520
3e38d3da 3521 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3522 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3523 EEPROM_TSSI_BOUND_A3_REF);
3524 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3525 EEPROM_TSSI_BOUND_A3_PLUS1);
3526
3e38d3da 3527 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3528 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3529 EEPROM_TSSI_BOUND_A4_PLUS2);
3530 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3531 EEPROM_TSSI_BOUND_A4_PLUS3);
3532
3e38d3da 3533 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3534 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3535 EEPROM_TSSI_BOUND_A5_PLUS4);
3536
3537 step = rt2x00_get_field16(eeprom,
3538 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3539 }
3540
3541 /*
3542 * Check if temperature compensation is supported.
3543 */
bf7e1abe 3544 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3545 return 0;
3546
3547 /*
3548 * Read current TSSI (BBP 49).
3549 */
3550 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3551
3552 /*
3553 * Compare TSSI value (BBP49) with the compensation boundaries
3554 * from the EEPROM and increase or decrease tx power.
3555 */
3556 for (i = 0; i <= 3; i++) {
3557 if (current_tssi > tssi_bounds[i])
3558 break;
3559 }
3560
3561 if (i == 4) {
3562 for (i = 8; i >= 5; i--) {
3563 if (current_tssi < tssi_bounds[i])
3564 break;
3565 }
3566 }
3567
3568 return (i - 4) * step;
3569}
3570
e90c54b2
RJH		 3571static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3572 enum ieee80211_band band)
3573{
3574 u16 eeprom;
3575 u8 comp_en;
3576 u8 comp_type;
75faae8b 3577 int comp_value = 0;
e90c54b2 3578
3e38d3da 3579 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3580
75faae8b
HS		 3581 /*
3582 * HT40 compensation not required.
3583 */
3584 if (eeprom == 0xffff ||
3585 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3586 return 0;
3587
3588 if (band == IEEE80211_BAND_2GHZ) {
3589 comp_en = rt2x00_get_field16(eeprom,
3590 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3591 if (comp_en) {
3592 comp_type = rt2x00_get_field16(eeprom,
3593 EEPROM_TXPOWER_DELTA_TYPE_2G);
3594 comp_value = rt2x00_get_field16(eeprom,
3595 EEPROM_TXPOWER_DELTA_VALUE_2G);
3596 if (!comp_type)
3597 comp_value = -comp_value;
3598 }
3599 } else {
3600 comp_en = rt2x00_get_field16(eeprom,
3601 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3602 if (comp_en) {
3603 comp_type = rt2x00_get_field16(eeprom,
3604 EEPROM_TXPOWER_DELTA_TYPE_5G);
3605 comp_value = rt2x00_get_field16(eeprom,
3606 EEPROM_TXPOWER_DELTA_VALUE_5G);
3607 if (!comp_type)
3608 comp_value = -comp_value;
3609 }
3610 }
3611
3612 return comp_value;
3613}
3614
1e4cf249
SG		 3615static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3616 int power_level, int max_power)
3617{
3618 int delta;
3619
c429dfef 3620 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3621 return 0;
3622
3623 /*
3624 * XXX: We don't know the maximum transmit power of our hardware since
3625 * the EEPROM doesn't expose it. We only know that we are calibrated
3626 * to 100% tx power.
3627 *
3628 * Hence, we assume the regulatory limit that cfg80211 calulated for
3629 * the current channel is our maximum and if we are requested to lower
3630 * the value we just reduce our tx power accordingly.
3631 */
3632 delta = power_level - max_power;
3633 return min(delta, 0);
3634}
3635
fa71a160
HS		 3636static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3637 enum ieee80211_band band, int power_level,
3638 u8 txpower, int delta)
e90c54b2 3639{
e90c54b2
RJH		 3640 u16 eeprom;
3641 u8 criterion;
3642 u8 eirp_txpower;
3643 u8 eirp_txpower_criterion;
3644 u8 reg_limit;
e90c54b2 3645
34542ff5
GJ		 3646 if (rt2x00_rt(rt2x00dev, RT3593))
3647 return min_t(u8, txpower, 0xc);
3648
c429dfef 3649 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3650 /*
3651 * Check if eirp txpower exceed txpower_limit.
3652 * We use OFDM 6M as criterion and its eirp txpower
3653 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3654 * .11b data rate need add additional 4dbm
3655 * when calculating eirp txpower.
3656 */
022138ca
GJ		 3657 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3658 1, &eeprom);
d9bceaeb
SG		 3659 criterion = rt2x00_get_field16(eeprom,
3660 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3661
3e38d3da 3662 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3663 &eeprom);
e90c54b2
RJH		 3664
3665 if (band == IEEE80211_BAND_2GHZ)
3666 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3667 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3668 else
3669 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3670 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3671
3672 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3673 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3674
3675 reg_limit = (eirp_txpower > power_level) ?
3676 (eirp_txpower - power_level) : 0;
3677 } else
3678 reg_limit = 0;
3679
19f3fa24
SG		 3680 txpower = max(0, txpower + delta - reg_limit);
3681 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3682}
3683
34542ff5
GJ		 3684
3685enum {
3686 TX_PWR_CFG_0_IDX,
3687 TX_PWR_CFG_1_IDX,
3688 TX_PWR_CFG_2_IDX,
3689 TX_PWR_CFG_3_IDX,
3690 TX_PWR_CFG_4_IDX,
3691 TX_PWR_CFG_5_IDX,
3692 TX_PWR_CFG_6_IDX,
3693 TX_PWR_CFG_7_IDX,
3694 TX_PWR_CFG_8_IDX,
3695 TX_PWR_CFG_9_IDX,
3696 TX_PWR_CFG_0_EXT_IDX,
3697 TX_PWR_CFG_1_EXT_IDX,
3698 TX_PWR_CFG_2_EXT_IDX,
3699 TX_PWR_CFG_3_EXT_IDX,
3700 TX_PWR_CFG_4_EXT_IDX,
3701 TX_PWR_CFG_IDX_COUNT,
3702};
3703
3704static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3705 struct ieee80211_channel *chan,
3706 int power_level)
3707{
3708 u8 txpower;
3709 u16 eeprom;
3710 u32 regs[TX_PWR_CFG_IDX_COUNT];
3711 unsigned int offset;
3712 enum ieee80211_band band = chan->band;
3713 int delta;
3714 int i;
3715
3716 memset(regs, '\0', sizeof(regs));
3717
3718 /* TODO: adapt TX power reduction from the rt28xx code */
3719
3720 /* calculate temperature compensation delta */
3721 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3722
3723 if (band == IEEE80211_BAND_5GHZ)
3724 offset = 16;
3725 else
3726 offset = 0;
3727
3728 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3729 offset += 8;
3730
3731 /* read the next four txpower values */
3732 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3733 offset, &eeprom);
3734
3735 /* CCK 1MBS,2MBS */
3736 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3737 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3738 txpower, delta);
3739 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3740 TX_PWR_CFG_0_CCK1_CH0, txpower);
3741 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3742 TX_PWR_CFG_0_CCK1_CH1, txpower);
3743 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3744 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3745
3746 /* CCK 5.5MBS,11MBS */
3747 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3748 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3749 txpower, delta);
3750 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3751 TX_PWR_CFG_0_CCK5_CH0, txpower);
3752 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3753 TX_PWR_CFG_0_CCK5_CH1, txpower);
3754 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3755 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3756
3757 /* OFDM 6MBS,9MBS */
3758 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3759 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3760 txpower, delta);
3761 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3762 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3763 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3764 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3765 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3766 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3767
3768 /* OFDM 12MBS,18MBS */
3769 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3770 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3771 txpower, delta);
3772 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3773 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3774 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3775 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3776 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3777 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3778
3779 /* read the next four txpower values */
3780 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3781 offset + 1, &eeprom);
3782
3783 /* OFDM 24MBS,36MBS */
3784 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3785 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3786 txpower, delta);
3787 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3788 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3789 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3790 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3791 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3792 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3793
3794 /* OFDM 48MBS */
3795 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3796 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3797 txpower, delta);
3798 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3799 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3800 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3801 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3802 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3803 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3804
3805 /* OFDM 54MBS */
3806 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3807 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3808 txpower, delta);
3809 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3810 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3811 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3812 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3813 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3814 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3815
3816 /* read the next four txpower values */
3817 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3818 offset + 2, &eeprom);
3819
3820 /* MCS 0,1 */
3821 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3822 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3823 txpower, delta);
3824 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3825 TX_PWR_CFG_1_MCS0_CH0, txpower);
3826 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3827 TX_PWR_CFG_1_MCS0_CH1, txpower);
3828 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3829 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3830
3831 /* MCS 2,3 */
3832 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3833 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3834 txpower, delta);
3835 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3836 TX_PWR_CFG_1_MCS2_CH0, txpower);
3837 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3838 TX_PWR_CFG_1_MCS2_CH1, txpower);
3839 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3840 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3841
3842 /* MCS 4,5 */
3843 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3845 txpower, delta);
3846 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3847 TX_PWR_CFG_2_MCS4_CH0, txpower);
3848 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3849 TX_PWR_CFG_2_MCS4_CH1, txpower);
3850 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3851 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3852
3853 /* MCS 6 */
3854 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3855 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3856 txpower, delta);
3857 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3858 TX_PWR_CFG_2_MCS6_CH0, txpower);
3859 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3860 TX_PWR_CFG_2_MCS6_CH1, txpower);
3861 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3862 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3863
3864 /* read the next four txpower values */
3865 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3866 offset + 3, &eeprom);
3867
3868 /* MCS 7 */
3869 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3870 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3871 txpower, delta);
3872 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3873 TX_PWR_CFG_7_MCS7_CH0, txpower);
3874 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3875 TX_PWR_CFG_7_MCS7_CH1, txpower);
3876 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3877 TX_PWR_CFG_7_MCS7_CH2, txpower);
3878
3879 /* MCS 8,9 */
3880 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3882 txpower, delta);
3883 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3884 TX_PWR_CFG_2_MCS8_CH0, txpower);
3885 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3886 TX_PWR_CFG_2_MCS8_CH1, txpower);
3887 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3888 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3889
3890 /* MCS 10,11 */
3891 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3893 txpower, delta);
3894 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3895 TX_PWR_CFG_2_MCS10_CH0, txpower);
3896 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3897 TX_PWR_CFG_2_MCS10_CH1, txpower);
3898 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3899 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3900
3901 /* MCS 12,13 */
3902 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3903 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3904 txpower, delta);
3905 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3906 TX_PWR_CFG_3_MCS12_CH0, txpower);
3907 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3908 TX_PWR_CFG_3_MCS12_CH1, txpower);
3909 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3910 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3911
3912 /* read the next four txpower values */
3913 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3914 offset + 4, &eeprom);
3915
3916 /* MCS 14 */
3917 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3918 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3919 txpower, delta);
3920 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3921 TX_PWR_CFG_3_MCS14_CH0, txpower);
3922 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3923 TX_PWR_CFG_3_MCS14_CH1, txpower);
3924 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3925 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3926
3927 /* MCS 15 */
3928 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3930 txpower, delta);
3931 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3932 TX_PWR_CFG_8_MCS15_CH0, txpower);
3933 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3934 TX_PWR_CFG_8_MCS15_CH1, txpower);
3935 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3936 TX_PWR_CFG_8_MCS15_CH2, txpower);
3937
3938 /* MCS 16,17 */
3939 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3940 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3941 txpower, delta);
3942 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3943 TX_PWR_CFG_5_MCS16_CH0, txpower);
3944 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3945 TX_PWR_CFG_5_MCS16_CH1, txpower);
3946 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3947 TX_PWR_CFG_5_MCS16_CH2, txpower);
3948
3949 /* MCS 18,19 */
3950 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3951 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3952 txpower, delta);
3953 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3954 TX_PWR_CFG_5_MCS18_CH0, txpower);
3955 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3956 TX_PWR_CFG_5_MCS18_CH1, txpower);
3957 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3958 TX_PWR_CFG_5_MCS18_CH2, txpower);
3959
3960 /* read the next four txpower values */
3961 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3962 offset + 5, &eeprom);
3963
3964 /* MCS 20,21 */
3965 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3966 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3967 txpower, delta);
3968 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3969 TX_PWR_CFG_6_MCS20_CH0, txpower);
3970 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3971 TX_PWR_CFG_6_MCS20_CH1, txpower);
3972 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3973 TX_PWR_CFG_6_MCS20_CH2, txpower);
3974
3975 /* MCS 22 */
3976 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3977 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3978 txpower, delta);
3979 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3980 TX_PWR_CFG_6_MCS22_CH0, txpower);
3981 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3982 TX_PWR_CFG_6_MCS22_CH1, txpower);
3983 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3984 TX_PWR_CFG_6_MCS22_CH2, txpower);
3985
3986 /* MCS 23 */
3987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3989 txpower, delta);
3990 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3991 TX_PWR_CFG_8_MCS23_CH0, txpower);
3992 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3993 TX_PWR_CFG_8_MCS23_CH1, txpower);
3994 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3995 TX_PWR_CFG_8_MCS23_CH2, txpower);
3996
3997 /* read the next four txpower values */
3998 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3999 offset + 6, &eeprom);
4000
4001 /* STBC, MCS 0,1 */
4002 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4003 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4004 txpower, delta);
4005 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4006 TX_PWR_CFG_3_STBC0_CH0, txpower);
4007 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4008 TX_PWR_CFG_3_STBC0_CH1, txpower);
4009 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4010 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4011
4012 /* STBC, MCS 2,3 */
4013 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4014 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4015 txpower, delta);
4016 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4017 TX_PWR_CFG_3_STBC2_CH0, txpower);
4018 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4019 TX_PWR_CFG_3_STBC2_CH1, txpower);
4020 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4021 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4022
4023 /* STBC, MCS 4,5 */
4024 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4025 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4026 txpower, delta);
4027 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4028 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4029 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4030 txpower);
4031
4032 /* STBC, MCS 6 */
4033 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4034 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4035 txpower, delta);
4036 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4037 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4038 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4039 txpower);
4040
4041 /* read the next four txpower values */
4042 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4043 offset + 7, &eeprom);
4044
4045 /* STBC, MCS 7 */
4046 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4047 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4048 txpower, delta);
4049 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4050 TX_PWR_CFG_9_STBC7_CH0, txpower);
4051 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4052 TX_PWR_CFG_9_STBC7_CH1, txpower);
4053 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4054 TX_PWR_CFG_9_STBC7_CH2, txpower);
4055
4056 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4057 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4058 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4059 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4060 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4061 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4062 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4063 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4064 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4065 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4066
4067 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4068 regs[TX_PWR_CFG_0_EXT_IDX]);
4069 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4070 regs[TX_PWR_CFG_1_EXT_IDX]);
4071 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4072 regs[TX_PWR_CFG_2_EXT_IDX]);
4073 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4074 regs[TX_PWR_CFG_3_EXT_IDX]);
4075 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4076 regs[TX_PWR_CFG_4_EXT_IDX]);
4077
4078 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4079 rt2x00_dbg(rt2x00dev,
4080 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4081 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4082 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4083 '4' : '2',
4084 (i > TX_PWR_CFG_9_IDX) ?
4085 (i - TX_PWR_CFG_9_IDX - 1) : i,
4086 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4087 (unsigned long) regs[i]);
4088}
4089
7a66205a
SG		 4090/*
4091 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4092 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4093 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4094 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4095 * Reference per rate transmit power values are located in the EEPROM at
4096 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4097 * current conditions (i.e. band, bandwidth, temperature, user settings).
4098 */
34542ff5
GJ		 4099static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4100 struct ieee80211_channel *chan,
4101 int power_level)
f4450616 4102{
cee2c731 4103 u8 txpower, r1;
5e846004 4104 u16 eeprom;
cee2c731
SG		 4105 u32 reg, offset;
4106 int i, is_rate_b, delta, power_ctrl;
146c3b0c 4107 enum ieee80211_band band = chan->band;
2af242e1
HS		 4108
4109 /*
7a66205a
SG		 4110 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4111 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4112 */
4113 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4114
9e33a355 4115 /*
7a66205a
SG		 4116 * Calculate temperature compensation. Depends on measurement of current
4117 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4118 * to temperature or maybe other factors) is smaller or bigger than
4119 * expected. We adjust it, based on TSSI reference and boundaries values
4120 * provided in EEPROM.
9e33a355
HS		 4121 */
4122 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 4123
1e4cf249 4124 /*
7a66205a
SG		 4125 * Decrease power according to user settings, on devices with unknown
4126 * maximum tx power. For other devices we take user power_level into
4127 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4128 */
4129 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4130 chan->max_power);
4131
5e846004 4132 /*
cee2c731
SG		 4133 * BBP_R1 controls TX power for all rates, it allow to set the following
4134 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4135 *
4136 * TODO: we do not use +6 dBm option to do not increase power beyond
4137 * regulatory limit, however this could be utilized for devices with
4138 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 4139 *
4140 * TODO: add different temperature compensation code for RT3290 & RT5390
4141 * to allow to use BBP_R1 for those chips.
4142 */
4143 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4144 !rt2x00_rt(rt2x00dev, RT5390)) {
4145 rt2800_bbp_read(rt2x00dev, 1, &r1);
4146 if (delta <= -12) {
4147 power_ctrl = 2;
4148 delta += 12;
4149 } else if (delta <= -6) {
4150 power_ctrl = 1;
4151 delta += 6;
4152 } else {
4153 power_ctrl = 0;
4154 }
4155 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4156 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 4157 }
8c8d2017 4158
5e846004
HS		 4159 offset = TX_PWR_CFG_0;
4160
4161 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4162 /* just to be safe */
4163 if (offset > TX_PWR_CFG_4)
4164 break;
4165
4166 rt2800_register_read(rt2x00dev, offset, &reg);
4167
4168 /* read the next four txpower values */
022138ca
GJ		 4169 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4170 i, &eeprom);
5e846004 4171
e90c54b2
RJH		 4172 is_rate_b = i ? 0 : 1;
4173 /*
4174 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4175 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4176 * TX_PWR_CFG_4: unknown
4177 */
5e846004
HS		 4178 txpower = rt2x00_get_field16(eeprom,
4179 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4180 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4181 power_level, txpower, delta);
e90c54b2 4182 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4183
e90c54b2
RJH		 4184 /*
4185 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4186 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4187 * TX_PWR_CFG_4: unknown
4188 */
5e846004
HS		 4189 txpower = rt2x00_get_field16(eeprom,
4190 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4191 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4192 power_level, txpower, delta);
e90c54b2 4193 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4194
e90c54b2
RJH		 4195 /*
4196 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4197 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4198 * TX_PWR_CFG_4: unknown
4199 */
5e846004
HS		 4200 txpower = rt2x00_get_field16(eeprom,
4201 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4202 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4203 power_level, txpower, delta);
e90c54b2 4204 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4205
e90c54b2
RJH		 4206 /*
4207 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4208 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4209 * TX_PWR_CFG_4: unknown
4210 */
5e846004
HS		 4211 txpower = rt2x00_get_field16(eeprom,
4212 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4213 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4214 power_level, txpower, delta);
e90c54b2 4215 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4216
4217 /* read the next four txpower values */
022138ca
GJ		 4218 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4219 i + 1, &eeprom);
5e846004 4220
e90c54b2
RJH		 4221 is_rate_b = 0;
4222 /*
4223 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4224 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4225 * TX_PWR_CFG_4: unknown
4226 */
5e846004
HS		 4227 txpower = rt2x00_get_field16(eeprom,
4228 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4229 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4230 power_level, txpower, delta);
e90c54b2 4231 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4232
e90c54b2
RJH		 4233 /*
4234 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4235 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4236 * TX_PWR_CFG_4: unknown
4237 */
5e846004
HS		 4238 txpower = rt2x00_get_field16(eeprom,
4239 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4240 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4241 power_level, txpower, delta);
e90c54b2 4242 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4243
e90c54b2
RJH		 4244 /*
4245 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4246 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4247 * TX_PWR_CFG_4: unknown
4248 */
5e846004
HS		 4249 txpower = rt2x00_get_field16(eeprom,
4250 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4251 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4252 power_level, txpower, delta);
e90c54b2 4253 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4254
e90c54b2
RJH		 4255 /*
4256 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4257 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4258 * TX_PWR_CFG_4: unknown
4259 */
5e846004
HS		 4260 txpower = rt2x00_get_field16(eeprom,
4261 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4262 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4263 power_level, txpower, delta);
e90c54b2 4264 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4265
4266 rt2800_register_write(rt2x00dev, offset, reg);
4267
4268 /* next TX_PWR_CFG register */
4269 offset += 4;
4270 }
f4450616
BZ		 4271}
4272
34542ff5
GJ		 4273static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4274 struct ieee80211_channel *chan,
4275 int power_level)
4276{
4277 if (rt2x00_rt(rt2x00dev, RT3593))
4278 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4279 else
4280 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4281}
4282
9e33a355
HS		 4283void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4284{
675a0b04 4285 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4286 rt2x00dev->tx_power);
4287}
4288EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4289
2e9c43dd
JL		 4290void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4291{
4292 u32 tx_pin;
4293 u8 rfcsr;
4294
4295 /*
4296 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4297 * designed to be controlled in oscillation frequency by a voltage
4298 * input. Maybe the temperature will affect the frequency of
4299 * oscillation to be shifted. The VCO calibration will be called
4300 * periodically to adjust the frequency to be precision.
4301 */
4302
4303 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4304 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4305 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4306
4307 switch (rt2x00dev->chip.rf) {
4308 case RF2020:
4309 case RF3020:
4310 case RF3021:
4311 case RF3022:
4312 case RF3320:
4313 case RF3052:
4314 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4315 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4316 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4317 break;
1095df07 4318 case RF3053:
3b9b74ba 4319 case RF3070:
a89534ed 4320 case RF3290:
ccf91bd6 4321 case RF5360:
ac0372ab 4322 case RF5362:
2e9c43dd
JL		 4323 case RF5370:
4324 case RF5372:
4325 case RF5390:
cff3d1f0 4326 case RF5392:
2e9c43dd 4327 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4328 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4329 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4330 break;
4331 default:
4332 return;
4333 }
4334
4335 mdelay(1);
4336
4337 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4338 if (rt2x00dev->rf_channel <= 14) {
4339 switch (rt2x00dev->default_ant.tx_chain_num) {
4340 case 3:
4341 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4342 /* fall through */
4343 case 2:
4344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4345 /* fall through */
4346 case 1:
4347 default:
4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4349 break;
4350 }
4351 } else {
4352 switch (rt2x00dev->default_ant.tx_chain_num) {
4353 case 3:
4354 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4355 /* fall through */
4356 case 2:
4357 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4358 /* fall through */
4359 case 1:
4360 default:
4361 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4362 break;
4363 }
4364 }
4365 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4366
4367}
4368EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4369
f4450616
BZ		 4370static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4371 struct rt2x00lib_conf *libconf)
4372{
4373 u32 reg;
4374
4375 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4376 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4377 libconf->conf->short_frame_max_tx_count);
4378 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4379 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4380 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4381}
4382
4383static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4384 struct rt2x00lib_conf *libconf)
4385{
4386 enum dev_state state =
4387 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4388 STATE_SLEEP : STATE_AWAKE;
4389 u32 reg;
4390
4391 if (state == STATE_SLEEP) {
4392 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4393
4394 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4395 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4396 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4397 libconf->conf->listen_interval - 1);
4398 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4399 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4400
4401 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4402 } else {
f4450616
BZ		 4403 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4404 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4405 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4406 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4407 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4408
4409 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4410 }
4411}
4412
4413void rt2800_config(struct rt2x00_dev *rt2x00dev,
4414 struct rt2x00lib_conf *libconf,
4415 const unsigned int flags)
4416{
4417 /* Always recalculate LNA gain before changing configuration */
4418 rt2800_config_lna_gain(rt2x00dev, libconf);
4419
e90c54b2 4420 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4421 rt2800_config_channel(rt2x00dev, libconf->conf,
4422 &libconf->rf, &libconf->channel);
675a0b04 4423 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4424 libconf->conf->power_level);
e90c54b2 4425 }
f4450616 4426 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4427 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4428 libconf->conf->power_level);
f4450616
BZ		 4429 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4430 rt2800_config_retry_limit(rt2x00dev, libconf);
4431 if (flags & IEEE80211_CONF_CHANGE_PS)
4432 rt2800_config_ps(rt2x00dev, libconf);
4433}
4434EXPORT_SYMBOL_GPL(rt2800_config);
4435
4436/*
4437 * Link tuning
4438 */
4439void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4440{
4441 u32 reg;
4442
4443 /*
4444 * Update FCS error count from register.
4445 */
4446 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4447 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4448}
4449EXPORT_SYMBOL_GPL(rt2800_link_stats);
4450
4451static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4452{
8c6728b0
GW		 4453 u8 vgc;
4454
f4450616 4455 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 4456 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4457 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4458 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4459 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4460 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4461 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4462 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4463 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4464 rt2x00_rt(rt2x00dev, RT5392) ||
4465 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4466 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4467 else
4468 vgc = 0x2e + rt2x00dev->lna_gain;
4469 } else { /* 5GHZ band */
733aec6a 4470 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4471 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4472 else if (rt2x00_rt(rt2x00dev, RT5592))
4473 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4474 else {
4475 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4476 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4477 else
4478 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4479 }
f4450616
BZ		 4480 }
4481
8c6728b0 4482 return vgc;
f4450616
BZ		 4483}
4484
4485static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4486 struct link_qual *qual, u8 vgc_level)
4487{
4488 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4489 if (rt2x00_rt(rt2x00dev, RT3572) ||
4490 rt2x00_rt(rt2x00dev, RT3593)) {
4491 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4492 vgc_level);
4493 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4494 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4495 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4496 } else {
3d81535e 4497 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4498 }
4499
f4450616
BZ		 4500 qual->vgc_level = vgc_level;
4501 qual->vgc_level_reg = vgc_level;
4502 }
4503}
4504
4505void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4506{
4507 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4508}
4509EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4510
4511void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4512 const u32 count)
4513{
3d81535e
SG		 4514 u8 vgc;
4515
8d0c9b65 4516 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4517 return;
e25aa82a
GJ		 4518
4519 /* When RSSI is better than a certain threshold, increase VGC
4520 * with a chip specific value in order to improve the balance
4521 * between sensibility and noise isolation.
f4450616 4522 */
3d81535e
SG		 4523
4524 vgc = rt2800_get_default_vgc(rt2x00dev);
4525
e25aa82a
GJ		 4526 switch (rt2x00dev->chip.rt) {
4527 case RT3572:
4528 case RT3593:
4529 if (qual->rssi > -65) {
4530 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4531 vgc += 0x20;
4532 else
4533 vgc += 0x10;
4534 }
4535 break;
4536
4537 case RT5592:
0beb1bbf
GJ		 4538 if (qual->rssi > -65)
4539 vgc += 0x20;
e25aa82a
GJ		 4540 break;
4541
4542 default:
0beb1bbf
GJ		 4543 if (qual->rssi > -80)
4544 vgc += 0x10;
e25aa82a 4545 break;
0beb1bbf 4546 }
3d81535e
SG		 4547
4548 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4549}
4550EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4551
4552/*
4553 * Initialization functions.
4554 */
b9a07ae9 4555static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4556{
4557 u32 reg;
d5385bfc 4558 u16 eeprom;
fcf51541 4559 unsigned int i;
e3a896b9 4560 int ret;
fcf51541 4561
f7b395e9 4562 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4563
e3a896b9
GW		 4564 ret = rt2800_drv_init_registers(rt2x00dev);
4565 if (ret)
4566 return ret;
fcf51541 4567
fcf51541
BZ		 4568 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4569 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4570
4571 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4572
4573 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4574 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4575 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4576 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4577 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4578 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4579 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4580 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4581
a9dce149
GW		 4582 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4583
4584 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4585 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4586 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4587 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4588
a89534ed
WH		 4589 if (rt2x00_rt(rt2x00dev, RT3290)) {
4590 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4591 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4592 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4593 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4594 }
4595
4596 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4597 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4598 rt2x00_set_field32(&reg, LDO0_EN, 1);
4599 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4600 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4601 }
4602
4603 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4604 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4605 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4606 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4607 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4608
4609 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4610 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4611 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4612
4613 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4614 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4615 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4616 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4617 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4618 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4619
4620 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4621 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4622 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4623 }
4624
64522957 4625 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4626 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4627 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4628 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4629
4630 if (rt2x00_rt(rt2x00dev, RT3290))
4631 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4632 0x00000404);
4633 else
4634 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4635 0x00000400);
4636
fcf51541 4637 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4638 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4639 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4640 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4641 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4642 &eeprom);
38c8a566 4643 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4644 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4645 0x0000002c);
4646 else
4647 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4648 0x0000000f);
4649 } else {
4650 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4651 }
d5385bfc 4652 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4653 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4654
4655 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4656 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4657 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4658 } else {
4659 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4660 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4661 }
c295a81d
HS		 4662 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4663 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4664 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4665 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4666 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4667 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4668 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4669 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4670 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4671 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4672 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4673 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4674 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4675 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4676 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4677 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4678 &eeprom);
4679 if (rt2x00_get_field16(eeprom,
4680 EEPROM_NIC_CONF1_DAC_TEST))
4681 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4682 0x0000001f);
4683 else
4684 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4685 0x0000000f);
4686 } else {
4687 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4688 0x00000000);
4689 }
2ed71884 4690 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4691 rt2x00_rt(rt2x00dev, RT5392) ||
4692 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4693 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4694 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4695 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4696 } else {
4697 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4698 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4699 }
4700
4701 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4702 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4703 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4704 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4705 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4706 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4707 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4708 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4709 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4710 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4711
4712 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4713 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4714 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4715 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4716 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4717
4718 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4719 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4720 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4721 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4722 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4723 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4724 else
4725 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4726 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4727 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4728 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4729
a9dce149
GW		 4730 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4731 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4732 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4733 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4734 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4735 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4736 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4737 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4738 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4739
fcf51541
BZ		 4740 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4741
a9dce149
GW		 4742 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4743 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4744 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4745 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4746 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4747 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4748 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4749 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4750
fcf51541
BZ		 4751 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4752 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4753 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4754 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4755 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4756 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4757 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4758 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4759 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4760
4761 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4762 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4763 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4764 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4765 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4766 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4767 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4768 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4769 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4770 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4771 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4772 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4773
4774 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4775 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4776 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4777 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4778 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4779 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4780 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4781 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4782 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4783 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4784 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4785 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4786
4787 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4788 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4789 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4790 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4791 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4792 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4793 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4794 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4795 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4796 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4797 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4798 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4799
4800 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4801 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4802 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4803 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4804 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4805 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4806 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4807 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4808 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4809 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4810 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4811 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4812
4813 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4814 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4815 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4816 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4817 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4818 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4819 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4820 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4821 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4822 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4823 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4824 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4825
4826 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4827 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4828 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4829 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4830 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4831 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4832 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4833 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4834 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4835 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4836 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4837 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4838
cea90e55 4839 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4840 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4841
4842 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4843 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4844 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4845 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4846 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4847 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4848 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4849 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4850 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4851 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4852 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4853 }
4854
961621ab
HS		 4855 /*
4856 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4857 * although it is reserved.
4858 */
4859 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4860 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4861 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4862 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4863 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4864 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4865 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4866 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4867 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4868 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4869 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4870 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4871
7641328d
SG		 4872 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4873 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4874
4875 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4876 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4877 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4878 IEEE80211_MAX_RTS_THRESHOLD);
4879 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4880 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4881
4882 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4883
a21c2ab4
HS		 4884 /*
4885 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4886 * time should be set to 16. However, the original Ralink driver uses
4887 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4888 * connection problems with 11g + CTS protection. Hence, use the same
4889 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4890 */
a9dce149 4891 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4892 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4893 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4894 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4895 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4896 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4897 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4898
fcf51541
BZ		 4899 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4900
4901 /*
4902 * ASIC will keep garbage value after boot, clear encryption keys.
4903 */
4904 for (i = 0; i < 4; i++)
4905 rt2800_register_write(rt2x00dev,
4906 SHARED_KEY_MODE_ENTRY(i), 0);
4907
4908 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4909 rt2800_config_wcid(rt2x00dev, NULL, i);
4910 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4911 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4912 }
4913
4914 /*
4915 * Clear all beacons
fcf51541 4916 */
77f7c0f3
GJ		 4917 for (i = 0; i < 8; i++)
4918 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4919
cea90e55 4920 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4921 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4922 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4923 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4924 } else if (rt2x00_is_pcie(rt2x00dev)) {
4925 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4926 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4927 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4928 }
4929
4930 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4931 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4932 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4933 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4934 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4935 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4936 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4937 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4938 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4939 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4940
4941 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4942 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4943 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4944 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4945 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4946 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4947 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4948 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4949 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4950 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4951
4952 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4953 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4954 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4955 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4956 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4957 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4958 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4959 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4960 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4961 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4962
4963 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4964 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4965 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4966 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4967 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4968 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4969
47ee3eb1
HS		 4970 /*
4971 * Do not force the BA window size, we use the TXWI to set it
4972 */
4973 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4974 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4975 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4976 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4977
fcf51541
BZ		 4978 /*
4979 * We must clear the error counters.
4980 * These registers are cleared on read,
4981 * so we may pass a useless variable to store the value.
4982 */
4983 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4984 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4985 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4986 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4987 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4988 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4989
9f926fb5
HS		 4990 /*
4991 * Setup leadtime for pre tbtt interrupt to 6ms
4992 */
4993 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4994 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4995 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4996
977206d7
HS		 4997 /*
4998 * Set up channel statistics timer
4999 */
5000 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
5001 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5002 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5003 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5004 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5005 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5006 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5007
fcf51541
BZ		 5008 return 0;
5009}
fcf51541
BZ		 5010
5011static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5012{
5013 unsigned int i;
5014 u32 reg;
5015
5016 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5017 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5018 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5019 return 0;
5020
5021 udelay(REGISTER_BUSY_DELAY);
5022 }
5023
ec9c4989 5024 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5025 return -EACCES;
5026}
5027
5028static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5029{
5030 unsigned int i;
5031 u8 value;
5032
5033 /*
5034 * BBP was enabled after firmware was loaded,
5035 * but we need to reactivate it now.
5036 */
5037 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5038 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5039 msleep(1);
5040
5041 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5042 rt2800_bbp_read(rt2x00dev, 0, &value);
5043 if ((value != 0xff) && (value != 0x00))
5044 return 0;
5045 udelay(REGISTER_BUSY_DELAY);
5046 }
5047
ec9c4989 5048 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5049 return -EACCES;
5050}
5051
a7bbbe5c
SG		 5052static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5053{
5054 u8 value;
5055
5056 rt2800_bbp_read(rt2x00dev, 4, &value);
5057 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5058 rt2800_bbp_write(rt2x00dev, 4, value);
5059}
5060
c2675487
SG		 5061static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5062{
5063 rt2800_bbp_write(rt2x00dev, 142, 1);
5064 rt2800_bbp_write(rt2x00dev, 143, 57);
5065}
5066
a7bbbe5c
SG		 5067static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5068{
5069 const u8 glrt_table[] = {
5070 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5071 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5072 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5073 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5074 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5075 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5076 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5077 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5078 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5079 };
5080 int i;
5081
5082 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5083 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5084 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5085 }
5086};
5087
624708b8 5088static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5089{
5090 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5091 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5092 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5093 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5094 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5095 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5096 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5097 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5098 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5099 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5100 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5101 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5102 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5103 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5104 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5105 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5106}
5107
5df1ff3a
SG		 5108static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5109{
5110 u16 eeprom;
5111 u8 value;
5112
5113 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5114 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5115 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5116 value |= 0x20;
5117 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5118 value &= ~0x02;
5119 rt2800_bbp_write(rt2x00dev, 138, value);
5120}
5121
dae62957
SG		 5122static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5123{
b2f8e0bd 5124 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5125
5126 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5127 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5128
5129 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5130 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5131
5132 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5133
5134 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5135 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5136
5137 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5138
5139 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5140
5141 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5142
5143 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5144
5145 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5146
5147 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5148
5149 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5150
5151 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5152
5153 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5154}
5155
39ab3e8b
SG		 5156static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5157{
e379de12
SG		 5158 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5159 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5160
5161 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5162 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5163 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5164 } else {
5165 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5166 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5167 }
8d97be38
SG		 5168
5169 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5170
5171 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5172
5173 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5174
5175 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5176
5177 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5178 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5179 else
5180 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5181
5182 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5183
5184 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5185
5186 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5187
5188 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5189
5190 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5191
5192 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5193}
5194
5195static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5196{
e379de12
SG		 5197 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5198 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5199
5200 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5201 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5202
5203 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5204
5205 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5206 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5207 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5208
5209 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5210
5211 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5212
5213 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5214
5215 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5216
5217 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5218
5219 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5220
5221 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5222 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5223 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5224 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5225 else
5226 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5227
5228 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5229
5230 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5231
5232 if (rt2x00_rt(rt2x00dev, RT3071) ||
5233 rt2x00_rt(rt2x00dev, RT3090))
5234 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5235}
5236
5237static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5238{
6addb24e
SG		 5239 u8 value;
5240
c3223573 5241 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5242
5243 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5244
5245 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5246 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5247
5248 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5249
5250 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5251 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5252 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5253 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5254
5255 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5256
5257 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5258
5259 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5260 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5261 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5262 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5263
5264 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5265
5266 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5267
5268 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5269
5270 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5271
5272 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5273
5274 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5275
5276 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5277
5278 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5279
5280 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5281
5282 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5283
5284 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5285
5286 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5287 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5288 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5289 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5290 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5291 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5292 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5293 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5294 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5295 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5296
5297 rt2800_bbp_read(rt2x00dev, 47, &value);
5298 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5299 rt2800_bbp_write(rt2x00dev, 47, value);
5300
5301 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5302 rt2800_bbp_read(rt2x00dev, 3, &value);
5303 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5304 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5305 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5306}
5307
5308static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5309{
29f3a58b
SG		 5310 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5311 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5312
5313 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5314
5315 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5316
5317 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5318 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5319
5320 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5321
5322 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5323 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5324 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5325 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5326
5327 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5328
5329 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5330
5331 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5332 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5333 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5334
5335 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5336
5337 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5338
5339 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5340
5341 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5342
5343 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5344
5345 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5346
5347 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5348
5349 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5350
5351 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5352
5353 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5354
5355 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5356
5357 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5358
5359 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5360
5361 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5362 /* Set ITxBF timeout to 0x9c40=1000msec */
5363 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5364 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5365 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5366 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5367 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5368 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5369 /* Reprogram the inband interface to put right values in RXWI */
5370 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5371 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5372 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5373 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5374 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5375 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5376 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5377 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5378
5379 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5380}
5381
5382static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5383{
e379de12
SG		 5384 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5385 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5386
5387 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5388 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5389
5390 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5391
5392 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5393 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5394 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5395
5396 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5397
5398 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5399
5400 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5401
5402 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5403
5404 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5405
5406 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5407
5408 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5409 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5410 else
5411 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5412
5413 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5414
5415 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5416
5417 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5418}
5419
5420static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5421{
b2f8e0bd 5422 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5423
5424 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5425 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5426
5427 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5428 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5429
5430 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5431
5432 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5433 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5434 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5435
5436 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5437
5438 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5439
5440 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5441
5442 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5443
5444 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5445
5446 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5447
5448 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5449
5450 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5451
5452 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5453
5454 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5455}
5456
b189a181
GJ		 5457static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5458{
5459 rt2800_init_bbp_early(rt2x00dev);
5460
5461 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5462 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5463 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5464 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5465
5466 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5467
5468 /* Enable DC filter */
5469 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5470 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5471}
5472
39ab3e8b
SG		 5473static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5474{
32ef8f49
SG		 5475 int ant, div_mode;
5476 u16 eeprom;
5477 u8 value;
5478
c3223573 5479 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5480
5481 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5482
5483 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5484 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5485
5486 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5487
58422191 5488 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5489 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5490 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5491 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5492
5493 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5494
58422191
SG		 5495 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5496
43f535e2
SG		 5497 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5498 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5499 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5500
5501 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5502
5503 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5504
5505 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5506
5507 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5508
5509 if (rt2x00_rt(rt2x00dev, RT5392))
5510 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5511
5512 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5513
5514 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5515
5516 if (rt2x00_rt(rt2x00dev, RT5392)) {
5517 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5518 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5519 }
672d1188
SG		 5520
5521 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5522
5523 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5524
5525 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5526
5527 if (rt2x00_rt(rt2x00dev, RT5390))
5528 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5529 else if (rt2x00_rt(rt2x00dev, RT5392))
5530 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5531 else
5532 WARN_ON(1);
f2b6777c
SG		 5533
5534 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5535
5536 if (rt2x00_rt(rt2x00dev, RT5392)) {
5537 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5538 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5539 }
5df1ff3a
SG		 5540
5541 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5542
3e38d3da 5543 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5544 div_mode = rt2x00_get_field16(eeprom,
5545 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5546 ant = (div_mode == 3) ? 1 : 0;
5547
5548 /* check if this is a Bluetooth combo card */
c429dfef 5549 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5550 u32 reg;
5551
5552 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5553 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5554 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5555 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5556 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5557 if (ant == 0)
5558 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5559 else if (ant == 1)
5560 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5561 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5562 }
5563
5564 /* This chip has hardware antenna diversity*/
5565 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5566 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5567 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5568 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5569 }
5570
5571 rt2800_bbp_read(rt2x00dev, 152, &value);
5572 if (ant == 0)
5573 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5574 else
5575 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5576 rt2800_bbp_write(rt2x00dev, 152, value);
5577
5578 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5579}
5580
a7bbbe5c
SG		 5581static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5582{
5583 int ant, div_mode;
5584 u16 eeprom;
5585 u8 value;
5586
624708b8 5587 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5588
a7bbbe5c
SG		 5589 rt2800_bbp_read(rt2x00dev, 105, &value);
5590 rt2x00_set_field8(&value, BBP105_MLD,
5591 rt2x00dev->default_ant.rx_chain_num == 2);
5592 rt2800_bbp_write(rt2x00dev, 105, value);
5593
5594 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5595
5596 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5597 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5598 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5599 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5600 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5601 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5602 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5603 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5604 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5605 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5606 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5607 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5608 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5609 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5610 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5611 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5612 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5613 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5614 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5615 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5616 /* FIXME BBP105 owerwrite */
5617 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5618 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5619 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5620 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5621 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5622 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5623
5624 /* Initialize GLRT (Generalized Likehood Radio Test) */
5625 rt2800_init_bbp_5592_glrt(rt2x00dev);
5626
5627 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5628
3e38d3da 5629 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5630 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5631 ant = (div_mode == 3) ? 1 : 0;
5632 rt2800_bbp_read(rt2x00dev, 152, &value);
5633 if (ant == 0) {
5634 /* Main antenna */
5635 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5636 } else {
5637 /* Auxiliary antenna */
5638 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5639 }
5640 rt2800_bbp_write(rt2x00dev, 152, value);
5641
5642 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5643 rt2800_bbp_read(rt2x00dev, 254, &value);
5644 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5645 rt2800_bbp_write(rt2x00dev, 254, value);
5646 }
5647
c2675487
SG		 5648 rt2800_init_freq_calibration(rt2x00dev);
5649
a7bbbe5c 5650 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5651 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5652 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5653}
5654
a1ef5039 5655static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5656{
5657 unsigned int i;
5658 u16 eeprom;
5659 u8 reg_id;
5660 u8 value;
5661
dae62957
SG		 5662 if (rt2800_is_305x_soc(rt2x00dev))
5663 rt2800_init_bbp_305x_soc(rt2x00dev);
5664
39ab3e8b
SG		 5665 switch (rt2x00dev->chip.rt) {
5666 case RT2860:
5667 case RT2872:
5668 case RT2883:
5669 rt2800_init_bbp_28xx(rt2x00dev);
5670 break;
5671 case RT3070:
5672 case RT3071:
5673 case RT3090:
5674 rt2800_init_bbp_30xx(rt2x00dev);
5675 break;
5676 case RT3290:
5677 rt2800_init_bbp_3290(rt2x00dev);
5678 break;
5679 case RT3352:
5680 rt2800_init_bbp_3352(rt2x00dev);
5681 break;
5682 case RT3390:
5683 rt2800_init_bbp_3390(rt2x00dev);
5684 break;
5685 case RT3572:
5686 rt2800_init_bbp_3572(rt2x00dev);
5687 break;
b189a181
GJ		 5688 case RT3593:
5689 rt2800_init_bbp_3593(rt2x00dev);
5690 return;
39ab3e8b
SG		 5691 case RT5390:
5692 case RT5392:
5693 rt2800_init_bbp_53xx(rt2x00dev);
5694 break;
5695 case RT5592:
a7bbbe5c 5696 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5697 return;
a7bbbe5c
SG		 5698 }
5699
fcf51541 5700 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5701 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5702 &eeprom);
fcf51541
BZ		 5703
5704 if (eeprom != 0xffff && eeprom != 0x0000) {
5705 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5706 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5707 rt2800_bbp_write(rt2x00dev, reg_id, value);
5708 }
5709 }
fcf51541 5710}
fcf51541 5711
d9517f2f
SG		 5712static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5713{
5714 u32 reg;
5715
5716 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5717 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5718 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5719}
5720
c5b3c350
SG		 5721static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5722 u8 filter_target)
fcf51541
BZ		 5723{
5724 unsigned int i;
5725 u8 bbp;
5726 u8 rfcsr;
5727 u8 passband;
5728 u8 stopband;
5729 u8 overtuned = 0;
c5b3c350 5730 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5731
5732 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5733
5734 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5735 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5736 rt2800_bbp_write(rt2x00dev, 4, bbp);
5737
80d184e6
RJH		 5738 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5739 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5740 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5741
fcf51541
BZ		 5742 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5743 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5744 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5745
5746 /*
5747 * Set power & frequency of passband test tone
5748 */
5749 rt2800_bbp_write(rt2x00dev, 24, 0);
5750
5751 for (i = 0; i < 100; i++) {
5752 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5753 msleep(1);
5754
5755 rt2800_bbp_read(rt2x00dev, 55, &passband);
5756 if (passband)
5757 break;
5758 }
5759
5760 /*
5761 * Set power & frequency of stopband test tone
5762 */
5763 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5764
5765 for (i = 0; i < 100; i++) {
5766 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5767 msleep(1);
5768
5769 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5770
5771 if ((passband - stopband) <= filter_target) {
5772 rfcsr24++;
5773 overtuned += ((passband - stopband) == filter_target);
5774 } else
5775 break;
5776
5777 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5778 }
5779
5780 rfcsr24 -= !!overtuned;
5781
5782 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5783 return rfcsr24;
5784}
5785
ce94ede9
SG		 5786static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5787 const unsigned int rf_reg)
5788{
5789 u8 rfcsr;
5790
5791 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5792 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5793 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5794 msleep(1);
5795 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5796 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5797}
5798
c5b3c350
SG		 5799static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5800{
5801 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5802 u8 filter_tgt_bw20;
5803 u8 filter_tgt_bw40;
5804 u8 rfcsr, bbp;
5805
5806 /*
5807 * TODO: sync filter_tgt values with vendor driver
5808 */
5809 if (rt2x00_rt(rt2x00dev, RT3070)) {
5810 filter_tgt_bw20 = 0x16;
5811 filter_tgt_bw40 = 0x19;
5812 } else {
5813 filter_tgt_bw20 = 0x13;
5814 filter_tgt_bw40 = 0x15;
5815 }
5816
5817 drv_data->calibration_bw20 =
5818 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5819 drv_data->calibration_bw40 =
5820 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5821
5822 /*
5823 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5824 */
5825 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5826 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5827
5828 /*
5829 * Set back to initial state
5830 */
5831 rt2800_bbp_write(rt2x00dev, 24, 0);
5832
5833 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5834 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5835 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5836
5837 /*
5838 * Set BBP back to BW20
5839 */
5840 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5841 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5842 rt2800_bbp_write(rt2x00dev, 4, bbp);
5843}
5844
da8064c2
SG		 5845static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5846{
5847 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5848 u8 min_gain, rfcsr, bbp;
5849 u16 eeprom;
5850
5851 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5852
5853 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5854 if (rt2x00_rt(rt2x00dev, RT3070) ||
5855 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5856 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5857 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5858 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5859 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5860 }
5861
5862 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5863 if (drv_data->txmixer_gain_24g >= min_gain) {
5864 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5865 drv_data->txmixer_gain_24g);
5866 }
5867
5868 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5869
5870 if (rt2x00_rt(rt2x00dev, RT3090)) {
5871 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5872 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5873 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5874 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5875 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5876 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5877 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5878 rt2800_bbp_write(rt2x00dev, 138, bbp);
5879 }
5880
5881 if (rt2x00_rt(rt2x00dev, RT3070)) {
5882 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5883 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5884 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5885 else
5886 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5887 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5888 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5889 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5890 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5891 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5892 rt2x00_rt(rt2x00dev, RT3090) ||
5893 rt2x00_rt(rt2x00dev, RT3390)) {
5894 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5895 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5896 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5897 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5898 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5899 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5900 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5901
5902 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5903 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5904 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5905
5906 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5907 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5908 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5909
5910 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5911 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5912 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5913 }
5914}
5915
ab7078ac
GJ		 5916static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5917{
5918 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5919 u8 rfcsr;
5920 u8 tx_gain;
5921
5922 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5923 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5924 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5925
5926 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5927 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5928 RFCSR17_TXMIXER_GAIN);
5929 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5930 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5931
5932 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5933 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5934 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5935
5936 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5937 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5938 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5939
5940 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5941 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5942 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5943 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5944
5945 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5946 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5947 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5948
5949 /* TODO: enable stream mode */
5950}
5951
f7df8fe5
SG		 5952static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5953{
5954 u8 reg;
5955 u16 eeprom;
5956
5957 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5958 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5959 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5960 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5961 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5962 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5963 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5964 rt2800_bbp_write(rt2x00dev, 138, reg);
5965
5966 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5967 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5968 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5969
5970 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5971 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5972 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5973
5974 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5975
5976 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5977 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5978 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5979}
5980
d5374ef1
SG		 5981static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5982{
ce94ede9
SG		 5983 rt2800_rf_init_calibration(rt2x00dev, 30);
5984
d5374ef1
SG		 5985 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5986 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5987 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5988 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5989 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5990 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5991 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5992 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5993 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5994 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5995 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5996 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5997 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5998 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5999 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6000 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6001 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6002 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6003 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6004 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6005 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6006 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6007 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6008 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6009 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6010 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6011 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6012 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6013 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6014 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6015 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6016 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6017}
6018
6019static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6020{
c9a221b2
SG		 6021 u8 rfcsr;
6022 u16 eeprom;
6023 u32 reg;
6024
ce94ede9
SG		 6025 /* XXX vendor driver do this only for 3070 */
6026 rt2800_rf_init_calibration(rt2x00dev, 30);
6027
d5374ef1
SG		 6028 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6029 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6030 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6031 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6032 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6033 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6034 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6035 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6036 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6037 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6038 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6039 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6040 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6041 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6042 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6043 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6044 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6045 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6046 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6047
6048 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6049 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6050 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6051 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6052 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6053 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6054 rt2x00_rt(rt2x00dev, RT3090)) {
6055 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6056
6057 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6058 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6059 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6060
6061 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6062 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6063 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6064 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6065 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6066 &eeprom);
c9a221b2
SG		 6067 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6068 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6069 else
6070 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6071 }
6072 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6073
6074 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6075 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6076 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6077 }
c5b3c350
SG		 6078
6079 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6080
6081 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6082 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6083 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6084 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6085
6086 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6087 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6088}
6089
6090static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6091{
f9cdcbb1
SG		 6092 u8 rfcsr;
6093
ce94ede9
SG		 6094 rt2800_rf_init_calibration(rt2x00dev, 2);
6095
d5374ef1
SG		 6096 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6097 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6098 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6099 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6100 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6101 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6102 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6103 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6104 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6105 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6106 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6107 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6108 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6109 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6110 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6111 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6112 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6113 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6114 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6115 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6116 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6117 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6118 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6119 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6120 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6121 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6122 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6123 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6124 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6125 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6126 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6127 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6128 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6129 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6130 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6131 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6132 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6133 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6134 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6135 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6136 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6137 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6138 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6139 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6140 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6141 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6142
6143 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6144 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6145 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6146
6147 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6148 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6149}
6150
6151static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6152{
ce94ede9
SG		 6153 rt2800_rf_init_calibration(rt2x00dev, 30);
6154
d5374ef1
SG		 6155 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6156 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6157 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6158 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6159 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6160 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6161 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6162 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6163 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6164 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6165 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6166 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6167 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6168 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6169 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6170 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6171 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6172 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6173 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6174 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6175 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6176 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6177 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6178 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6179 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6180 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6181 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6182 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6183 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6184 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6185 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6186 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6187 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6188 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6189 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6190 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6191 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6192 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6193 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6194 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6195 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6196 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6197 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6198 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6199 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6200 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6201 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6202 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6203 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6204 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6205 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6206 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6207 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6208 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6209 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6210 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6211 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6212 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6213 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6214 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6215 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6216 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6217 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6218
6219 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6220 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6221 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6222}
6223
6224static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6225{
2971e66f
SG		 6226 u32 reg;
6227
ce94ede9
SG		 6228 rt2800_rf_init_calibration(rt2x00dev, 30);
6229
d5374ef1
SG		 6230 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6231 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6232 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6233 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6234 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6235 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6236 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6237 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6238 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6239 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6240 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6241 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6242 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6243 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6244 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6245 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6246 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6247 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6248 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6249 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6250 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6251 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6252 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6253 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6254 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6255 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6256 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6257 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6258 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6259 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6260 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6261 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6262
6263 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6264 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6265 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6266
6267 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6268
6269 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6270 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6271
6272 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6273 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6274}
6275
6276static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6277{
87d91db9
SG		 6278 u8 rfcsr;
6279 u32 reg;
6280
ce94ede9
SG		 6281 rt2800_rf_init_calibration(rt2x00dev, 30);
6282
d5374ef1
SG		 6283 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6284 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6285 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6286 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6287 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6288 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6289 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6290 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6291 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6292 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6293 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6294 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6295 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6296 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6297 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6298 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6299 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6300 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6301 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6302 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6303 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6304 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6305 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6306 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6307 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6308 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6309 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6310 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6311 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6312 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6313 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6314
6315 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6316 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6317 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6318
6319 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6320 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6321 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6322 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6323 msleep(1);
6324 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6325 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6326 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6327 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6328
6329 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6330 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6331 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6332}
6333
d63f7e8c
GJ		 6334static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6335{
6336 u8 bbp;
6337 bool txbf_enabled = false; /* FIXME */
6338
6339 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6340 if (rt2x00dev->default_ant.rx_chain_num == 1)
6341 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6342 else
6343 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6344 rt2800_bbp_write(rt2x00dev, 105, bbp);
6345
6346 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6347
6348 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6349 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6350 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6351 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6352 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6353 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6354 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6355 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6356
6357 if (txbf_enabled)
6358 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6359 else
6360 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6361
6362 /* SNR mapping */
6363 rt2800_bbp_write(rt2x00dev, 142, 6);
6364 rt2800_bbp_write(rt2x00dev, 143, 160);
6365 rt2800_bbp_write(rt2x00dev, 142, 7);
6366 rt2800_bbp_write(rt2x00dev, 143, 161);
6367 rt2800_bbp_write(rt2x00dev, 142, 8);
6368 rt2800_bbp_write(rt2x00dev, 143, 162);
6369
6370 /* ADC/DAC control */
6371 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6372
6373 /* RX AGC energy lower bound in log2 */
6374 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6375
6376 /* FIXME: BBP 105 owerwrite? */
6377 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6378
d63f7e8c
GJ		 6379}
6380
ab7078ac
GJ		 6381static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6382{
6383 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6384 u32 reg;
6385 u8 rfcsr;
6386
6387 /* Disable GPIO #4 and #7 function for LAN PE control */
6388 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6389 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6390 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6391 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6392
6393 /* Initialize default register values */
6394 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6395 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6396 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6397 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6398 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6399 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6400 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6401 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6402 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6403 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6404 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6405 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6406 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6407 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6408 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6409 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6410 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6411 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6412 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6413 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6414 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6415 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6416 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6417 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6418 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6419 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6420 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6421 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6422 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6423 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6424 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6425 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6426
6427 /* Initiate calibration */
6428 /* TODO: use rt2800_rf_init_calibration ? */
6429 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6430 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6431 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6432
6433 rt2800_adjust_freq_offset(rt2x00dev);
6434
6435 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6436 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6437 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6438
6439 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6440 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6441 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6442 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6443 usleep_range(1000, 1500);
6444 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6445 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6446 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6447
6448 /* Set initial values for RX filter calibration */
6449 drv_data->calibration_bw20 = 0x1f;
6450 drv_data->calibration_bw40 = 0x2f;
6451
6452 /* Save BBP 25 & 26 values for later use in channel switching */
6453 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6454 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6455
6456 rt2800_led_open_drain_enable(rt2x00dev);
6457 rt2800_normal_mode_setup_3593(rt2x00dev);
6458
d63f7e8c 6459 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6460
6461 /* TODO: enable stream mode support */
6462}
6463
d5374ef1
SG		 6464static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6465{
ce94ede9
SG		 6466 rt2800_rf_init_calibration(rt2x00dev, 2);
6467
d5374ef1
SG		 6468 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6469 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6470 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6471 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6472 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6473 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6474 else
6475 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6476 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6477 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6478 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6479 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6480 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6481 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6482 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6483 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6484 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6485 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6486
6487 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6488 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6489 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6490 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6491 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6492 if (rt2x00_is_usb(rt2x00dev) &&
6493 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6494 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6495 else
6496 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6497 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6498 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6499 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6500 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6501
7122e660 6502 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6503 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6504 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6505 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6506 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6507 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6508 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6509 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6510 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6511 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6512
c8520bcb 6513 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6514 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6515 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6516 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6517 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6518 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6519 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6520 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6521 else
6522 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6523 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6524 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6525 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6526
6527 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6528 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6529 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6530 else
6531 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6532 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6533 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6534 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6535 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6536 else
6537 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6538 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6539 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6540 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6541
6542 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6543 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6544 if (rt2x00_is_usb(rt2x00dev))
6545 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6546 else
6547 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6548 } else {
6549 if (rt2x00_is_usb(rt2x00dev))
6550 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6551 else
6552 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6553 }
d5374ef1
SG		 6554 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6555 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6556
6557 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6558
6559 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6560}
6561
6562static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6563{
ce94ede9
SG		 6564 rt2800_rf_init_calibration(rt2x00dev, 2);
6565
d5374ef1 6566 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6567 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6568 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6569 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6570 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6571 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6572 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6573 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6574 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6575 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6576 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6577 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6578 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6579 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6580 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6581 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6582 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6583 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6584 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6585 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6586 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6587 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6588 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6589 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6590 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6591 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6592 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6593 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6594 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6595 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6596 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6597 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6598 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6599 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6600 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6601 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6602 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6603 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6604 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6605 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6606 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6607 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6608 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6609 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6610 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6611 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6612 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6613 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6614 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6615 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6616 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6617 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6618 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6619 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6620 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6621 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6622 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6623 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6624
6625 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6626
6627 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6628}
6629
0c9e5fb9
SG		 6630static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6631{
ce94ede9
SG		 6632 rt2800_rf_init_calibration(rt2x00dev, 30);
6633
0c9e5fb9
SG		 6634 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6635 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6636 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6637 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6638 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6639 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6640 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6641 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6642 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6643 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6644 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6645 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6646 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6647 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6648 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6649 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6650 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6651 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6652 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6653 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6654 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6655
6656 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6657 msleep(1);
6658
6659 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6660
c630ccf1
SG		 6661 /* Enable DC filter */
6662 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6663 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6664
f7df8fe5 6665 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6666
6667 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6668 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6669
6670 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6671}
6672
074f2529 6673static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6674{
d5374ef1
SG		 6675 if (rt2800_is_305x_soc(rt2x00dev)) {
6676 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6677 return;
d5374ef1
SG		 6678 }
6679
6680 switch (rt2x00dev->chip.rt) {
6681 case RT3070:
6682 case RT3071:
6683 case RT3090:
6684 rt2800_init_rfcsr_30xx(rt2x00dev);
6685 break;
6686 case RT3290:
6687 rt2800_init_rfcsr_3290(rt2x00dev);
6688 break;
6689 case RT3352:
6690 rt2800_init_rfcsr_3352(rt2x00dev);
6691 break;
6692 case RT3390:
6693 rt2800_init_rfcsr_3390(rt2x00dev);
6694 break;
6695 case RT3572:
6696 rt2800_init_rfcsr_3572(rt2x00dev);
6697 break;
ab7078ac
GJ		 6698 case RT3593:
6699 rt2800_init_rfcsr_3593(rt2x00dev);
6700 break;
d5374ef1
SG		 6701 case RT5390:
6702 rt2800_init_rfcsr_5390(rt2x00dev);
6703 break;
6704 case RT5392:
6705 rt2800_init_rfcsr_5392(rt2x00dev);
6706 break;
0c9e5fb9
SG		 6707 case RT5592:
6708 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6709 break;
8cdd15e0 6710 }
fcf51541 6711}
b9a07ae9
ID		 6712
6713int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6714{
6715 u32 reg;
6716 u16 word;
6717
6718 /*
61edc7fa 6719 * Initialize MAC registers.
b9a07ae9
ID		 6720 */
6721 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6722 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6723 return -EIO;
6724
61edc7fa
SG		 6725 /*
6726 * Wait BBP/RF to wake up.
6727 */
f4e1a4d3
SG		 6728 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6729 return -EIO;
6730
b9a07ae9 6731 /*
61edc7fa 6732 * Send signal during boot time to initialize firmware.
b9a07ae9 6733 */
c630ccf1
SG		 6734 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6735 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6736 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6737 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6738 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6739 msleep(1);
6740
61edc7fa
SG		 6741 /*
6742 * Make sure BBP is up and running.
6743 */
f4e1a4d3 6744 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6745 return -EIO;
b9a07ae9 6746
61edc7fa
SG		 6747 /*
6748 * Initialize BBP/RF registers.
6749 */
a1ef5039 6750 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6751 rt2800_init_rfcsr(rt2x00dev);
6752
b9a07ae9
ID		 6753 if (rt2x00_is_usb(rt2x00dev) &&
6754 (rt2x00_rt(rt2x00dev, RT3070) ||
6755 rt2x00_rt(rt2x00dev, RT3071) ||
6756 rt2x00_rt(rt2x00dev, RT3572))) {
6757 udelay(200);
6758 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6759 udelay(10);
6760 }
6761
6762 /*
6763 * Enable RX.
6764 */
6765 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6766 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6767 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6768 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6769
6770 udelay(50);
6771
6772 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6773 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6774 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6775 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6776 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6777 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6778
6779 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6780 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6781 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6782 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6783
6784 /*
6785 * Initialize LED control
6786 */
3e38d3da 6787 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6788 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6789 word & 0xff, (word >> 8) & 0xff);
6790
3e38d3da 6791 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6792 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6793 word & 0xff, (word >> 8) & 0xff);
6794
3e38d3da 6795 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6796 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6797 word & 0xff, (word >> 8) & 0xff);
6798
6799 return 0;
6800}
6801EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6802
6803void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6804{
6805 u32 reg;
6806
f7b395e9 6807 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6808
6809 /* Wait for DMA, ignore error */
6810 rt2800_wait_wpdma_ready(rt2x00dev);
6811
6812 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6813 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6814 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6815 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6816}
6817EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6818
30e84034
BZ		 6819int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6820{
6821 u32 reg;
a89534ed 6822 u16 efuse_ctrl_reg;
30e84034 6823
a89534ed
WH		 6824 if (rt2x00_rt(rt2x00dev, RT3290))
6825 efuse_ctrl_reg = EFUSE_CTRL_3290;
6826 else
6827 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6828
a89534ed 6829 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6830 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6831}
6832EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6833
6834static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6835{
6836 u32 reg;
a89534ed
WH		 6837 u16 efuse_ctrl_reg;
6838 u16 efuse_data0_reg;
6839 u16 efuse_data1_reg;
6840 u16 efuse_data2_reg;
6841 u16 efuse_data3_reg;
6842
6843 if (rt2x00_rt(rt2x00dev, RT3290)) {
6844 efuse_ctrl_reg = EFUSE_CTRL_3290;
6845 efuse_data0_reg = EFUSE_DATA0_3290;
6846 efuse_data1_reg = EFUSE_DATA1_3290;
6847 efuse_data2_reg = EFUSE_DATA2_3290;
6848 efuse_data3_reg = EFUSE_DATA3_3290;
6849 } else {
6850 efuse_ctrl_reg = EFUSE_CTRL;
6851 efuse_data0_reg = EFUSE_DATA0;
6852 efuse_data1_reg = EFUSE_DATA1;
6853 efuse_data2_reg = EFUSE_DATA2;
6854 efuse_data3_reg = EFUSE_DATA3;
6855 }
31a4cf1f
GW		 6856 mutex_lock(&rt2x00dev->csr_mutex);
6857
a89534ed 6858 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6859 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6860 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6861 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6862 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6863
6864 /* Wait until the EEPROM has been loaded */
a89534ed 6865 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6866 /* Apparently the data is read from end to start */
a89534ed 6867 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6868 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6869 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6870 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6871 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6872 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6873 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6874 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6875 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6876
6877 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6878}
6879
a02308e9 6880int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6881{
6882 unsigned int i;
6883
6884 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6885 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6886
6887 return 0;
30e84034
BZ		 6888}
6889EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6890
a3f1625d
GJ		 6891static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6892{
6893 u16 word;
6894
6316c786
GJ		 6895 if (rt2x00_rt(rt2x00dev, RT3593))
6896 return 0;
6897
a3f1625d
GJ		 6898 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6899 if ((word & 0x00ff) != 0x00ff)
6900 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6901
6902 return 0;
6903}
6904
6905static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6906{
6907 u16 word;
6908
6316c786
GJ		 6909 if (rt2x00_rt(rt2x00dev, RT3593))
6910 return 0;
6911
a3f1625d
GJ		 6912 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6913 if ((word & 0x00ff) != 0x00ff)
6914 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6915
6916 return 0;
6917}
6918
ad417a53 6919static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6920{
77c06c2c 6921 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6922 u16 word;
6923 u8 *mac;
6924 u8 default_lna_gain;
a02308e9 6925 int retval;
38bd7b8a 6926
ad417a53
GW		 6927 /*
6928 * Read the EEPROM.
6929 */
a02308e9
GJ		 6930 retval = rt2800_read_eeprom(rt2x00dev);
6931 if (retval)
6932 return retval;
ad417a53 6933
38bd7b8a
BZ		 6934 /*
6935 * Start validation of the data that has been read.
6936 */
3e38d3da 6937 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6938 if (!is_valid_ether_addr(mac)) {
f4f7f414 6939 eth_random_addr(mac);
ec9c4989 6940 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6941 }
6942
3e38d3da 6943 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6944 if (word == 0xffff) {
38c8a566
RJH		 6945 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6946 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6947 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6948 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6949 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6950 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6951 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6952 /*
6953 * There is a max of 2 RX streams for RT28x0 series
6954 */
38c8a566
RJH		 6955 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6956 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6957 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6958 }
6959
3e38d3da 6960 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6961 if (word == 0xffff) {
38c8a566
RJH		 6962 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6963 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6964 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6965 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6966 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6967 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6968 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6969 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6970 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6971 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6972 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6973 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6974 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6975 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6976 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6977 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6978 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6979 }
6980
3e38d3da 6981 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6982 if ((word & 0x00ff) == 0x00ff) {
6983 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6984 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6985 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6986 }
6987 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6988 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6989 LED_MODE_TXRX_ACTIVITY);
6990 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6991 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6992 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6993 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6994 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6995 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6996 }
6997
6998 /*
6999 * During the LNA validation we are going to use
7000 * lna0 as correct value. Note that EEPROM_LNA
7001 * is never validated.
7002 */
3e38d3da 7003 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 7004 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
7005
3e38d3da 7006 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 7007 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
7008 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
7009 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
7010 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 7011 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 7012
a3f1625d 7013 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 7014
3e38d3da 7015 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 7016 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7017 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 7018 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7019 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7020 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7021 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7022 default_lna_gain);
7023 }
3e38d3da 7024 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 7025
a3f1625d 7026 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7027
3e38d3da 7028 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7029 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7030 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7031 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7032 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7033 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7034
3e38d3da 7035 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7036 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7037 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7038 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7039 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7040 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7041 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7042 default_lna_gain);
7043 }
3e38d3da 7044 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7045
f36bb0ca
GJ		 7046 if (rt2x00_rt(rt2x00dev, RT3593)) {
7047 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7048 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7049 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7050 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7051 default_lna_gain);
7052 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7053 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7054 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7055 default_lna_gain);
7056 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7057 }
7058
38bd7b8a
BZ		 7059 return 0;
7060}
38bd7b8a 7061
ad417a53 7062static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7063{
38bd7b8a
BZ		 7064 u16 value;
7065 u16 eeprom;
86868b26 7066 u16 rf;
38bd7b8a 7067
86868b26
GJ		 7068 /*
7069 * Read EEPROM word for configuration.
7070 */
3e38d3da 7071 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7072
7073 /*
7074 * Identify RF chipset by EEPROM value
7075 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7076 * RT53xx: defined in "EEPROM_CHIP_ID" field
7077 */
7078 if (rt2x00_rt(rt2x00dev, RT3290) ||
7079 rt2x00_rt(rt2x00dev, RT5390) ||
7080 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7081 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7082 else
7083 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7084
7085 switch (rf) {
d331eb51
LF		 7086 case RF2820:
7087 case RF2850:
7088 case RF2720:
7089 case RF2750:
7090 case RF3020:
7091 case RF2020:
7092 case RF3021:
7093 case RF3022:
7094 case RF3052:
0f5af26a 7095 case RF3053:
3b9b74ba 7096 case RF3070:
a89534ed 7097 case RF3290:
d331eb51 7098 case RF3320:
03839951 7099 case RF3322:
ccf91bd6 7100 case RF5360:
ac0372ab 7101 case RF5362:
d331eb51 7102 case RF5370:
2ed71884 7103 case RF5372:
d331eb51 7104 case RF5390:
cff3d1f0 7105 case RF5392:
b8863f8b 7106 case RF5592:
d331eb51
LF		 7107 break;
7108 default:
ec9c4989
JP		 7109 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7110 rf);
38bd7b8a
BZ		 7111 return -ENODEV;
7112 }
7113
86868b26
GJ		 7114 rt2x00_set_rf(rt2x00dev, rf);
7115
38bd7b8a
BZ		 7116 /*
7117 * Identify default antenna configuration.
7118 */
d96aa640 7119 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7120 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7121 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7122 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7123
3e38d3da 7124 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7125
7126 if (rt2x00_rt(rt2x00dev, RT3070) ||
7127 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7128 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7129 rt2x00_rt(rt2x00dev, RT3390)) {
7130 value = rt2x00_get_field16(eeprom,
7131 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7132 switch (value) {
7133 case 0:
7134 case 1:
7135 case 2:
7136 rt2x00dev->default_ant.tx = ANTENNA_A;
7137 rt2x00dev->default_ant.rx = ANTENNA_A;
7138 break;
7139 case 3:
7140 rt2x00dev->default_ant.tx = ANTENNA_A;
7141 rt2x00dev->default_ant.rx = ANTENNA_B;
7142 break;
7143 }
7144 } else {
7145 rt2x00dev->default_ant.tx = ANTENNA_A;
7146 rt2x00dev->default_ant.rx = ANTENNA_A;
7147 }
7148
0586a11b
AA		 7149 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7150 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7151 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7152 }
7153
38bd7b8a 7154 /*
9328fdac 7155 * Determine external LNA informations.
38bd7b8a 7156 */
38c8a566 7157 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7158 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7159 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7160 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7161
7162 /*
7163 * Detect if this device has an hardware controlled radio.
7164 */
38c8a566 7165 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7166 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7167
fdbc7b0a
GW		 7168 /*
7169 * Detect if this device has Bluetooth co-existence.
7170 */
7171 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7172 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7173
9328fdac
GW		 7174 /*
7175 * Read frequency offset and RF programming sequence.
7176 */
3e38d3da 7177 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7178 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7179
38bd7b8a
BZ		 7180 /*
7181 * Store led settings, for correct led behaviour.
7182 */
7183#ifdef CONFIG_RT2X00_LIB_LEDS
7184 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7185 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7186 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7187
9328fdac 7188 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7189#endif /* CONFIG_RT2X00_LIB_LEDS */
7190
e90c54b2
RJH		 7191 /*
7192 * Check if support EIRP tx power limit feature.
7193 */
3e38d3da 7194 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7195
7196 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7197 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7198 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7199
38bd7b8a
BZ		 7200 return 0;
7201}
38bd7b8a 7202
4da2933f 7203/*
55f9321a 7204 * RF value list for rt28xx
4da2933f
BZ		 7205 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7206 */
7207static const struct rf_channel rf_vals[] = {
7208 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7209 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7210 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7211 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7212 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7213 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7214 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7215 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7216 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7217 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7218 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7219 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7220 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7221 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7222
7223 /* 802.11 UNI / HyperLan 2 */
7224 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7225 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7226 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7227 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7228 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7229 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7230 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7231 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7232 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7233 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7234 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7235 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7236
7237 /* 802.11 HyperLan 2 */
7238 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7239 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7240 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7241 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7242 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7243 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7244 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7245 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7246 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7247 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7248 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7249 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7250 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7251 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7252 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7253 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7254
7255 /* 802.11 UNII */
7256 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7257 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7258 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7259 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7260 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7261 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7262 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7263 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7264 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7265 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7266 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7267
7268 /* 802.11 Japan */
7269 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7270 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7271 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7272 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7273 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7274 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7275 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7276};
7277
7278/*
55f9321a 7279 * RF value list for rt3xxx
b6b561c3 7280 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7281 */
55f9321a 7282static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7283 {1, 241, 2, 2 },
7284 {2, 241, 2, 7 },
7285 {3, 242, 2, 2 },
7286 {4, 242, 2, 7 },
7287 {5, 243, 2, 2 },
7288 {6, 243, 2, 7 },
7289 {7, 244, 2, 2 },
7290 {8, 244, 2, 7 },
7291 {9, 245, 2, 2 },
7292 {10, 245, 2, 7 },
7293 {11, 246, 2, 2 },
7294 {12, 246, 2, 7 },
7295 {13, 247, 2, 2 },
7296 {14, 248, 2, 4 },
55f9321a
ID		 7297
7298 /* 802.11 UNI / HyperLan 2 */
7299 {36, 0x56, 0, 4},
7300 {38, 0x56, 0, 6},
7301 {40, 0x56, 0, 8},
7302 {44, 0x57, 0, 0},
7303 {46, 0x57, 0, 2},
7304 {48, 0x57, 0, 4},
7305 {52, 0x57, 0, 8},
7306 {54, 0x57, 0, 10},
7307 {56, 0x58, 0, 0},
7308 {60, 0x58, 0, 4},
7309 {62, 0x58, 0, 6},
7310 {64, 0x58, 0, 8},
7311
7312 /* 802.11 HyperLan 2 */
7313 {100, 0x5b, 0, 8},
7314 {102, 0x5b, 0, 10},
7315 {104, 0x5c, 0, 0},
7316 {108, 0x5c, 0, 4},
7317 {110, 0x5c, 0, 6},
7318 {112, 0x5c, 0, 8},
7319 {116, 0x5d, 0, 0},
7320 {118, 0x5d, 0, 2},
7321 {120, 0x5d, 0, 4},
7322 {124, 0x5d, 0, 8},
7323 {126, 0x5d, 0, 10},
7324 {128, 0x5e, 0, 0},
7325 {132, 0x5e, 0, 4},
7326 {134, 0x5e, 0, 6},
7327 {136, 0x5e, 0, 8},
7328 {140, 0x5f, 0, 0},
7329
7330 /* 802.11 UNII */
7331 {149, 0x5f, 0, 9},
7332 {151, 0x5f, 0, 11},
7333 {153, 0x60, 0, 1},
7334 {157, 0x60, 0, 5},
7335 {159, 0x60, 0, 7},
7336 {161, 0x60, 0, 9},
7337 {165, 0x61, 0, 1},
7338 {167, 0x61, 0, 3},
7339 {169, 0x61, 0, 5},
7340 {171, 0x61, 0, 7},
7341 {173, 0x61, 0, 9},
4da2933f
BZ		 7342};
7343
7848b231
SG		 7344static const struct rf_channel rf_vals_5592_xtal20[] = {
7345 /* Channel, N, K, mod, R */
7346 {1, 482, 4, 10, 3},
7347 {2, 483, 4, 10, 3},
7348 {3, 484, 4, 10, 3},
7349 {4, 485, 4, 10, 3},
7350 {5, 486, 4, 10, 3},
7351 {6, 487, 4, 10, 3},
7352 {7, 488, 4, 10, 3},
7353 {8, 489, 4, 10, 3},
7354 {9, 490, 4, 10, 3},
7355 {10, 491, 4, 10, 3},
7356 {11, 492, 4, 10, 3},
7357 {12, 493, 4, 10, 3},
7358 {13, 494, 4, 10, 3},
7359 {14, 496, 8, 10, 3},
7360 {36, 172, 8, 12, 1},
7361 {38, 173, 0, 12, 1},
7362 {40, 173, 4, 12, 1},
7363 {42, 173, 8, 12, 1},
7364 {44, 174, 0, 12, 1},
7365 {46, 174, 4, 12, 1},
7366 {48, 174, 8, 12, 1},
7367 {50, 175, 0, 12, 1},
7368 {52, 175, 4, 12, 1},
7369 {54, 175, 8, 12, 1},
7370 {56, 176, 0, 12, 1},
7371 {58, 176, 4, 12, 1},
7372 {60, 176, 8, 12, 1},
7373 {62, 177, 0, 12, 1},
7374 {64, 177, 4, 12, 1},
7375 {100, 183, 4, 12, 1},
7376 {102, 183, 8, 12, 1},
7377 {104, 184, 0, 12, 1},
7378 {106, 184, 4, 12, 1},
7379 {108, 184, 8, 12, 1},
7380 {110, 185, 0, 12, 1},
7381 {112, 185, 4, 12, 1},
7382 {114, 185, 8, 12, 1},
7383 {116, 186, 0, 12, 1},
7384 {118, 186, 4, 12, 1},
7385 {120, 186, 8, 12, 1},
7386 {122, 187, 0, 12, 1},
7387 {124, 187, 4, 12, 1},
7388 {126, 187, 8, 12, 1},
7389 {128, 188, 0, 12, 1},
7390 {130, 188, 4, 12, 1},
7391 {132, 188, 8, 12, 1},
7392 {134, 189, 0, 12, 1},
7393 {136, 189, 4, 12, 1},
7394 {138, 189, 8, 12, 1},
7395 {140, 190, 0, 12, 1},
7396 {149, 191, 6, 12, 1},
7397 {151, 191, 10, 12, 1},
7398 {153, 192, 2, 12, 1},
7399 {155, 192, 6, 12, 1},
7400 {157, 192, 10, 12, 1},
7401 {159, 193, 2, 12, 1},
7402 {161, 193, 6, 12, 1},
7403 {165, 194, 2, 12, 1},
7404 {184, 164, 0, 12, 1},
7405 {188, 164, 4, 12, 1},
7406 {192, 165, 8, 12, 1},
7407 {196, 166, 0, 12, 1},
7408};
7409
7410static const struct rf_channel rf_vals_5592_xtal40[] = {
7411 /* Channel, N, K, mod, R */
7412 {1, 241, 2, 10, 3},
7413 {2, 241, 7, 10, 3},
7414 {3, 242, 2, 10, 3},
7415 {4, 242, 7, 10, 3},
7416 {5, 243, 2, 10, 3},
7417 {6, 243, 7, 10, 3},
7418 {7, 244, 2, 10, 3},
7419 {8, 244, 7, 10, 3},
7420 {9, 245, 2, 10, 3},
7421 {10, 245, 7, 10, 3},
7422 {11, 246, 2, 10, 3},
7423 {12, 246, 7, 10, 3},
7424 {13, 247, 2, 10, 3},
7425 {14, 248, 4, 10, 3},
7426 {36, 86, 4, 12, 1},
7427 {38, 86, 6, 12, 1},
7428 {40, 86, 8, 12, 1},
7429 {42, 86, 10, 12, 1},
7430 {44, 87, 0, 12, 1},
7431 {46, 87, 2, 12, 1},
7432 {48, 87, 4, 12, 1},
7433 {50, 87, 6, 12, 1},
7434 {52, 87, 8, 12, 1},
7435 {54, 87, 10, 12, 1},
7436 {56, 88, 0, 12, 1},
7437 {58, 88, 2, 12, 1},
7438 {60, 88, 4, 12, 1},
7439 {62, 88, 6, 12, 1},
7440 {64, 88, 8, 12, 1},
7441 {100, 91, 8, 12, 1},
7442 {102, 91, 10, 12, 1},
7443 {104, 92, 0, 12, 1},
7444 {106, 92, 2, 12, 1},
7445 {108, 92, 4, 12, 1},
7446 {110, 92, 6, 12, 1},
7447 {112, 92, 8, 12, 1},
7448 {114, 92, 10, 12, 1},
7449 {116, 93, 0, 12, 1},
7450 {118, 93, 2, 12, 1},
7451 {120, 93, 4, 12, 1},
7452 {122, 93, 6, 12, 1},
7453 {124, 93, 8, 12, 1},
7454 {126, 93, 10, 12, 1},
7455 {128, 94, 0, 12, 1},
7456 {130, 94, 2, 12, 1},
7457 {132, 94, 4, 12, 1},
7458 {134, 94, 6, 12, 1},
7459 {136, 94, 8, 12, 1},
7460 {138, 94, 10, 12, 1},
7461 {140, 95, 0, 12, 1},
7462 {149, 95, 9, 12, 1},
7463 {151, 95, 11, 12, 1},
7464 {153, 96, 1, 12, 1},
7465 {155, 96, 3, 12, 1},
7466 {157, 96, 5, 12, 1},
7467 {159, 96, 7, 12, 1},
7468 {161, 96, 9, 12, 1},
7469 {165, 97, 1, 12, 1},
7470 {184, 82, 0, 12, 1},
7471 {188, 82, 4, 12, 1},
7472 {192, 82, 8, 12, 1},
7473 {196, 83, 0, 12, 1},
7474};
7475
ad417a53 7476static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7477{
4da2933f
BZ		 7478 struct hw_mode_spec *spec = &rt2x00dev->spec;
7479 struct channel_info *info;
8d1331b3
ID		 7480 char *default_power1;
7481 char *default_power2;
c0a14369 7482 char *default_power3;
4da2933f 7483 unsigned int i;
7848b231 7484 u32 reg;
4da2933f 7485
93b6bd26 7486 /*
58e33a21 7487 * Disable powersaving as default.
93b6bd26 7488 */
58e33a21 7489 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7490
4da2933f
BZ		 7491 /*
7492 * Initialize all hw fields.
7493 */
7494 rt2x00dev->hw->flags =
4da2933f
BZ		 7495 IEEE80211_HW_SIGNAL_DBM |
7496 IEEE80211_HW_SUPPORTS_PS |
1df90809 7497 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 7498 IEEE80211_HW_AMPDU_AGGREGATION |
2dfca312
FF		 7499 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7500 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
9d4f09b8 7501
5a5b6ed6
HS		 7502 /*
7503 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7504 * unless we are capable of sending the buffered frames out after the
7505 * DTIM transmission using rt2x00lib_beacondone. This will send out
7506 * multicast and broadcast traffic immediately instead of buffering it
7507 * infinitly and thus dropping it after some time.
7508 */
7509 if (!rt2x00_is_usb(rt2x00dev))
7510 rt2x00dev->hw->flags |=
7511 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 7512
4da2933f
BZ		 7513 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7514 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7515 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7516 EEPROM_MAC_ADDR_0));
7517
3f2bee24
HS		 7518 /*
7519 * As rt2800 has a global fallback table we cannot specify
7520 * more then one tx rate per frame but since the hw will
7521 * try several rates (based on the fallback table) we should
ba3b9e5e 7522 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7523 * we are going to try. Otherwise mac80211 will truncate our
7524 * reported tx rates and the rc algortihm will end up with
7525 * incorrect data.
7526 */
ba3b9e5e
HS		 7527 rt2x00dev->hw->max_rates = 1;
7528 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7529 rt2x00dev->hw->max_rate_tries = 1;
7530
4da2933f
BZ		 7531 /*
7532 * Initialize hw_mode information.
7533 */
4da2933f
BZ		 7534 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7535
4a32c36d
GJ		 7536 switch (rt2x00dev->chip.rf) {
7537 case RF2720:
7538 case RF2820:
4da2933f
BZ		 7539 spec->num_channels = 14;
7540 spec->channels = rf_vals;
4a32c36d
GJ		 7541 break;
7542
7543 case RF2750:
7544 case RF2850:
4da2933f
BZ		 7545 spec->num_channels = ARRAY_SIZE(rf_vals);
7546 spec->channels = rf_vals;
4a32c36d
GJ		 7547 break;
7548
7549 case RF2020:
7550 case RF3020:
7551 case RF3021:
7552 case RF3022:
7553 case RF3070:
7554 case RF3290:
7555 case RF3320:
7556 case RF3322:
7557 case RF5360:
ac0372ab 7558 case RF5362:
4a32c36d
GJ		 7559 case RF5370:
7560 case RF5372:
7561 case RF5390:
7562 case RF5392:
55f9321a
ID		 7563 spec->num_channels = 14;
7564 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7565 break;
7566
7567 case RF3052:
7568 case RF3053:
55f9321a
ID		 7569 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7570 spec->channels = rf_vals_3x;
4a32c36d 7571 break;
7848b231 7572
4a32c36d 7573 case RF5592:
7848b231
SG		 7574 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7575 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7576 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7577 spec->channels = rf_vals_5592_xtal40;
7578 } else {
7579 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7580 spec->channels = rf_vals_5592_xtal20;
7581 }
4a32c36d 7582 break;
4da2933f
BZ		 7583 }
7584
53216d6a
SG		 7585 if (WARN_ON_ONCE(!spec->channels))
7586 return -ENODEV;
7587
53c5a099
GJ		 7588 spec->supported_bands = SUPPORT_BAND_2GHZ;
7589 if (spec->num_channels > 14)
7590 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7591
4da2933f
BZ		 7592 /*
7593 * Initialize HT information.
7594 */
5122d898 7595 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7596 spec->ht.ht_supported = true;
7597 else
7598 spec->ht.ht_supported = false;
7599
4da2933f 7600 spec->ht.cap =
06443e46 7601 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7602 IEEE80211_HT_CAP_GRN_FLD |
7603 IEEE80211_HT_CAP_SGI_20 |
aa674631 7604 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7605
aa10350d 7606 if (rt2x00dev->default_ant.tx_chain_num >= 2)
22cabaa6
HS		 7607 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7608
aa10350d
GJ		 7609 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7610 IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7611
4da2933f
BZ		 7612 spec->ht.ampdu_factor = 3;
7613 spec->ht.ampdu_density = 4;
7614 spec->ht.mcs.tx_params =
7615 IEEE80211_HT_MCS_TX_DEFINED |
7616 IEEE80211_HT_MCS_TX_RX_DIFF |
aa10350d
GJ		 7617 ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7618 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4da2933f 7619
aa10350d 7620 switch (rt2x00dev->default_ant.rx_chain_num) {
4da2933f
BZ		 7621 case 3:
7622 spec->ht.mcs.rx_mask[2] = 0xff;
7623 case 2:
7624 spec->ht.mcs.rx_mask[1] = 0xff;
7625 case 1:
7626 spec->ht.mcs.rx_mask[0] = 0xff;
7627 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7628 break;
7629 }
7630
7631 /*
7632 * Create channel information array
7633 */
baeb2ffa 7634 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7635 if (!info)
7636 return -ENOMEM;
7637
7638 spec->channels_info = info;
7639
3e38d3da
GJ		 7640 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7641 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7642
c0a14369
GJ		 7643 if (rt2x00dev->default_ant.tx_chain_num > 2)
7644 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7645 EEPROM_EXT_TXPOWER_BG3);
7646 else
7647 default_power3 = NULL;
7648
4da2933f 7649 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7650 info[i].default_power1 = default_power1[i];
7651 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7652 if (default_power3)
7653 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7654 }
7655
7656 if (spec->num_channels > 14) {
3e38d3da
GJ		 7657 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7658 EEPROM_TXPOWER_A1);
7659 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7660 EEPROM_TXPOWER_A2);
4da2933f 7661
c0a14369
GJ		 7662 if (rt2x00dev->default_ant.tx_chain_num > 2)
7663 default_power3 =
7664 rt2800_eeprom_addr(rt2x00dev,
7665 EEPROM_EXT_TXPOWER_A3);
7666 else
7667 default_power3 = NULL;
7668
4da2933f 7669 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7670 info[i].default_power1 = default_power1[i - 14];
7671 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7672 if (default_power3)
7673 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7674 }
7675 }
7676
2e9c43dd
JL		 7677 switch (rt2x00dev->chip.rf) {
7678 case RF2020:
7679 case RF3020:
7680 case RF3021:
7681 case RF3022:
7682 case RF3320:
7683 case RF3052:
1095df07 7684 case RF3053:
3b9b74ba 7685 case RF3070:
a89534ed 7686 case RF3290:
ccf91bd6 7687 case RF5360:
ac0372ab 7688 case RF5362:
2e9c43dd
JL		 7689 case RF5370:
7690 case RF5372:
7691 case RF5390:
cff3d1f0 7692 case RF5392:
2e9c43dd
JL		 7693 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7694 break;
7695 }
7696
4da2933f
BZ		 7697 return 0;
7698}
ad417a53 7699
cbafb601
GJ		 7700static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7701{
7702 u32 reg;
7703 u32 rt;
7704 u32 rev;
7705
7706 if (rt2x00_rt(rt2x00dev, RT3290))
7707 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7708 else
7709 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7710
7711 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7712 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7713
7714 switch (rt) {
7715 case RT2860:
7716 case RT2872:
7717 case RT2883:
7718 case RT3070:
7719 case RT3071:
7720 case RT3090:
7721 case RT3290:
7722 case RT3352:
7723 case RT3390:
7724 case RT3572:
2dc2bd2f 7725 case RT3593:
cbafb601
GJ		 7726 case RT5390:
7727 case RT5392:
7728 case RT5592:
7729 break;
7730 default:
ec9c4989
JP		 7731 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7732 rt, rev);
cbafb601
GJ		 7733 return -ENODEV;
7734 }
7735
7736 rt2x00_set_rt(rt2x00dev, rt, rev);
7737
7738 return 0;
7739}
7740
ad417a53
GW		 7741int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7742{
7743 int retval;
7744 u32 reg;
7745
cbafb601
GJ		 7746 retval = rt2800_probe_rt(rt2x00dev);
7747 if (retval)
7748 return retval;
7749
ad417a53
GW		 7750 /*
7751 * Allocate eeprom data.
7752 */
7753 retval = rt2800_validate_eeprom(rt2x00dev);
7754 if (retval)
7755 return retval;
7756
7757 retval = rt2800_init_eeprom(rt2x00dev);
7758 if (retval)
7759 return retval;
7760
7761 /*
7762 * Enable rfkill polling by setting GPIO direction of the
7763 * rfkill switch GPIO pin correctly.
7764 */
7765 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7766 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7767 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7768
7769 /*
7770 * Initialize hw specifications.
7771 */
7772 retval = rt2800_probe_hw_mode(rt2x00dev);
7773 if (retval)
7774 return retval;
7775
7776 /*
7777 * Set device capabilities.
7778 */
7779 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7780 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7781 if (!rt2x00_is_usb(rt2x00dev))
7782 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7783
7784 /*
7785 * Set device requirements.
7786 */
7787 if (!rt2x00_is_soc(rt2x00dev))
7788 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7789 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7790 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7791 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7792 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7793 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7794 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7795 if (rt2x00_is_usb(rt2x00dev))
7796 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7797 else {
7798 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7799 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7800 }
7801
7802 /*
7803 * Set the rssi offset.
7804 */
7805 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7806
7807 return 0;
7808}
7809EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7810
2ce33995
BZ		 7811/*
7812 * IEEE80211 stack callback functions.
7813 */
e783619e
HS		 7814void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7815 u16 *iv16)
2ce33995
BZ		 7816{
7817 struct rt2x00_dev *rt2x00dev = hw->priv;
7818 struct mac_iveiv_entry iveiv_entry;
7819 u32 offset;
7820
7821 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7822 rt2800_register_multiread(rt2x00dev, offset,
7823 &iveiv_entry, sizeof(iveiv_entry));
7824
855da5e0
JL		 7825 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7826 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 7827}
e783619e 7828EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 7829
e783619e 7830int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7831{
7832 struct rt2x00_dev *rt2x00dev = hw->priv;
7833 u32 reg;
7834 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7835
7836 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7837 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7838 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7839
7840 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7841 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7842 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7843
7844 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7845 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7846 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7847
7848 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7849 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7850 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7851
7852 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7853 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7854 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7855
7856 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7857 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7858 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7859
7860 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7861 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7862 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7863
7864 return 0;
7865}
e783619e 7866EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7867
8a3a3c85
EP		 7868int rt2800_conf_tx(struct ieee80211_hw *hw,
7869 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7870 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7871{
7872 struct rt2x00_dev *rt2x00dev = hw->priv;
7873 struct data_queue *queue;
7874 struct rt2x00_field32 field;
7875 int retval;
7876 u32 reg;
7877 u32 offset;
7878
7879 /*
7880 * First pass the configuration through rt2x00lib, that will
7881 * update the queue settings and validate the input. After that
7882 * we are free to update the registers based on the value
7883 * in the queue parameter.
7884 */
8a3a3c85 7885 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7886 if (retval)
7887 return retval;
7888
7889 /*
7890 * We only need to perform additional register initialization
7891 * for WMM queues/
7892 */
7893 if (queue_idx >= 4)
7894 return 0;
7895
11f818e0 7896 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7897
7898 /* Update WMM TXOP register */
7899 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7900 field.bit_offset = (queue_idx & 1) * 16;
7901 field.bit_mask = 0xffff << field.bit_offset;
7902
7903 rt2800_register_read(rt2x00dev, offset, &reg);
7904 rt2x00_set_field32(&reg, field, queue->txop);
7905 rt2800_register_write(rt2x00dev, offset, reg);
7906
7907 /* Update WMM registers */
7908 field.bit_offset = queue_idx * 4;
7909 field.bit_mask = 0xf << field.bit_offset;
7910
7911 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7912 rt2x00_set_field32(&reg, field, queue->aifs);
7913 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7914
7915 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7916 rt2x00_set_field32(&reg, field, queue->cw_min);
7917 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7918
7919 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7920 rt2x00_set_field32(&reg, field, queue->cw_max);
7921 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7922
7923 /* Update EDCA registers */
7924 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7925
7926 rt2800_register_read(rt2x00dev, offset, &reg);
7927 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7928 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7929 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7930 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7931 rt2800_register_write(rt2x00dev, offset, reg);
7932
7933 return 0;
7934}
e783619e 7935EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7936
37a41b4a 7937u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7938{
7939 struct rt2x00_dev *rt2x00dev = hw->priv;
7940 u64 tsf;
7941 u32 reg;
7942
7943 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7944 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7945 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7946 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7947
7948 return tsf;
7949}
e783619e 7950EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7951
e783619e
HS		 7952int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7953 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 7954 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7955 u8 buf_size)
1df90809 7956{
af35323d 7957 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7958 int ret = 0;
7959
af35323d
HS		 7960 /*
7961 * Don't allow aggregation for stations the hardware isn't aware
7962 * of because tx status reports for frames to an unknown station
7963 * always contain wcid=255 and thus we can't distinguish between
7964 * multiple stations which leads to unwanted situations when the
7965 * hw reorders frames due to aggregation.
7966 */
7967 if (sta_priv->wcid < 0)
7968 return 1;
7969
1df90809
HS		 7970 switch (action) {
7971 case IEEE80211_AMPDU_RX_START:
7972 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7973 /*
7974 * The hw itself takes care of setting up BlockAck mechanisms.
7975 * So, we only have to allow mac80211 to nagotiate a BlockAck
7976 * agreement. Once that is done, the hw will BlockAck incoming
7977 * AMPDUs without further setup.
7978 */
1df90809
HS		 7979 break;
7980 case IEEE80211_AMPDU_TX_START:
7981 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7982 break;
18b559d5
JB		 7983 case IEEE80211_AMPDU_TX_STOP_CONT:
7984 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7985 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7986 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7987 break;
7988 case IEEE80211_AMPDU_TX_OPERATIONAL:
7989 break;
7990 default:
ec9c4989
JP		 7991 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7992 "Unknown AMPDU action\n");
1df90809
HS		 7993 }
7994
7995 return ret;
7996}
e783619e 7997EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7998
977206d7
HS		 7999int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
8000 struct survey_info *survey)
8001{
8002 struct rt2x00_dev *rt2x00dev = hw->priv;
8003 struct ieee80211_conf *conf = &hw->conf;
8004 u32 idle, busy, busy_ext;
8005
8006 if (idx != 0)
8007 return -ENOENT;
8008
675a0b04 8009 survey->channel = conf->chandef.chan;
977206d7
HS		 8010
8011 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8012 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8013 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8014
8015 if (idle || busy) {
8016 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8017 SURVEY_INFO_CHANNEL_TIME_BUSY |
8018 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8019
8020 survey->channel_time = (idle + busy) / 1000;
8021 survey->channel_time_busy = busy / 1000;
8022 survey->channel_time_ext_busy = busy_ext / 1000;
8023 }
8024
9931df26
HS		 8025 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8026 survey->filled |= SURVEY_INFO_IN_USE;
8027
977206d7
HS		 8028 return 0;
8029
8030}
8031EXPORT_SYMBOL_GPL(rt2800_get_survey);
8032
a5ea2f02
ID		 8033MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8034MODULE_VERSION(DRV_VERSION);
8035MODULE_DESCRIPTION("Ralink RT2800 library");
8036MODULE_LICENSE("GPL");
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