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rt2x00: Fix SM PS check
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
b9eca242
ID		 387 /*
388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
390 */
391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
392
f31c9a8c
ID		 393 /*
394 * Wait for stable hardware.
395 */
5ffddc49 396 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 397 return -EBUSY;
f31c9a8c
ID		 398
399 if (rt2x00_is_pci(rt2x00dev))
400 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
401
402 /*
403 * Disable DMA, will be reenabled later when enabling
404 * the radio.
405 */
406 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
408 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Initialize firmware.
436 */
437 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
438 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
439 msleep(1);
440
441 return 0;
442}
443EXPORT_SYMBOL_GPL(rt2800_load_firmware);
444
0c5879bc
ID		 445void rt2800_write_tx_data(struct queue_entry *entry,
446 struct txentry_desc *txdesc)
59679b91 447{
0c5879bc 448 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 449 u32 word;
450
451 /*
452 * Initialize TX Info descriptor
453 */
454 rt2x00_desc_read(txwi, 0, &word);
455 rt2x00_set_field32(&word, TXWI_W0_FRAG,
456 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 457 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
458 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 459 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
460 rt2x00_set_field32(&word, TXWI_W0_TS,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
463 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
464 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
465 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
466 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
467 rt2x00_set_field32(&word, TXWI_W0_BW,
468 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
469 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
470 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
471 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
472 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
473 rt2x00_desc_write(txwi, 0, word);
474
475 rt2x00_desc_read(txwi, 1, &word);
476 rt2x00_set_field32(&word, TXWI_W1_ACK,
477 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
478 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
479 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
481 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
482 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
483 txdesc->key_idx : 0xff);
484 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
485 txdesc->length);
a908a743 486 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
59679b91
GW		 487 rt2x00_desc_write(txwi, 1, word);
488
489 /*
490 * Always write 0 to IV/EIV fields, hardware will insert the IV
491 * from the IVEIV register when TXD_W3_WIV is set to 0.
492 * When TXD_W3_WIV is set to 1 it will use the IV data
493 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
494 * crypto entry in the registers should be used to encrypt the frame.
495 */
496 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
497 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
498}
0c5879bc 499EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 500
74861922 501static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 502{
74861922
ID		 503 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
504 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
505 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
506 u16 eeprom;
507 u8 offset0;
508 u8 offset1;
509 u8 offset2;
510
e5ef5bad 511 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
513 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
514 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
515 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
516 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
517 } else {
518 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
519 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
520 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
521 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
522 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
523 }
524
525 /*
526 * Convert the value from the descriptor into the RSSI value
527 * If the value in the descriptor is 0, it is considered invalid
528 * and the default (extremely low) rssi value is assumed
529 */
530 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
531 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
532 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
533
534 /*
535 * mac80211 only accepts a single RSSI value. Calculating the
536 * average doesn't deliver a fair answer either since -60:-60 would
537 * be considered equally good as -50:-70 while the second is the one
538 * which gives less energy...
539 */
540 rssi0 = max(rssi0, rssi1);
541 return max(rssi0, rssi2);
542}
543
544void rt2800_process_rxwi(struct queue_entry *entry,
545 struct rxdone_entry_desc *rxdesc)
546{
547 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 548 u32 word;
549
550 rt2x00_desc_read(rxwi, 0, &word);
551
552 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
553 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
554
555 rt2x00_desc_read(rxwi, 1, &word);
556
557 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
558 rxdesc->flags |= RX_FLAG_SHORT_GI;
559
560 if (rt2x00_get_field32(word, RXWI_W1_BW))
561 rxdesc->flags |= RX_FLAG_40MHZ;
562
563 /*
564 * Detect RX rate, always use MCS as signal type.
565 */
566 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
567 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
568 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
569
570 /*
571 * Mask of 0x8 bit to remove the short preamble flag.
572 */
573 if (rxdesc->rate_mode == RATE_MODE_CCK)
574 rxdesc->signal &= ~0x8;
575
576 rt2x00_desc_read(rxwi, 2, &word);
577
74861922
ID		 578 /*
579 * Convert descriptor AGC value to RSSI value.
580 */
581 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 582
583 /*
584 * Remove RXWI descriptor from start of buffer.
585 */
74861922 586 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 587}
588EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
589
3613884d
ID		 590static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
591{
592 __le32 *txwi;
593 u32 word;
594 int wcid, ack, pid;
595 int tx_wcid, tx_ack, tx_pid;
596
597 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
598 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
599 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
600
601 /*
602 * This frames has returned with an IO error,
603 * so the status report is not intended for this
604 * frame.
605 */
606 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
607 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
608 return false;
609 }
610
611 /*
612 * Validate if this TX status report is intended for
613 * this entry by comparing the WCID/ACK/PID fields.
614 */
615 txwi = rt2800_drv_get_txwi(entry);
616
617 rt2x00_desc_read(txwi, 1, &word);
618 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
619 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
620 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
621
622 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
623 WARNING(entry->queue->rt2x00dev,
624 "TX status report missed for queue %d entry %d\n",
625 entry->queue->qid, entry->entry_idx);
626 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
627 return false;
628 }
629
630 return true;
631}
632
14433331
HS		 633void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
634{
635 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
636 struct txdone_entry_desc txdesc;
637 u32 word;
638 u16 mcs, real_mcs;
639 __le32 *txwi;
640
641 /*
642 * Obtain the status about this packet.
643 */
644 txdesc.flags = 0;
645 txwi = rt2800_drv_get_txwi(entry);
646 rt2x00_desc_read(txwi, 0, &word);
647 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
648 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
649
650 /*
651 * Ralink has a retry mechanism using a global fallback
652 * table. We setup this fallback table to try the immediate
653 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
654 * always contains the MCS used for the last transmission, be
655 * it successful or not.
656 */
657 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
658 /*
659 * Transmission succeeded. The number of retries is
660 * mcs - real_mcs
661 */
662 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
663 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
664 } else {
665 /*
666 * Transmission failed. The number of retries is
667 * always 7 in this case (for a total number of 8
668 * frames sent).
669 */
670 __set_bit(TXDONE_FAILURE, &txdesc.flags);
671 txdesc.retry = rt2x00dev->long_retry;
672 }
673
674 /*
675 * the frame was retried at least once
676 * -> hw used fallback rates
677 */
678 if (txdesc.retry)
679 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
680
681 rt2x00lib_txdone(entry, &txdesc);
682}
683EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
684
96481b20
ID		 685void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
686{
687 struct data_queue *queue;
688 struct queue_entry *entry;
96481b20 689 u32 reg;
3613884d 690 u8 pid;
96481b20
ID		 691 int i;
692
693 /*
694 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
695 * at most X times and also stop processing once the TX_STA_FIFO_VALID
696 * flag is not set anymore.
697 *
698 * The legacy drivers use X=TX_RING_SIZE but state in a comment
699 * that the TX_STA_FIFO stack has a size of 16. We stick to our
700 * tx ring size for now.
701 */
702 for (i = 0; i < TX_ENTRIES; i++) {
703 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
704 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
705 break;
706
96481b20
ID		 707 /*
708 * Skip this entry when it contains an invalid
709 * queue identication number.
710 */
3613884d
ID		 711 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
712 if (pid >= QID_RX)
96481b20
ID		 713 continue;
714
3613884d 715 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 716 if (unlikely(!queue))
717 continue;
718
719 /*
720 * Inside each queue, we process each entry in a chronological
721 * order. We first check that the queue is not empty.
722 */
723 entry = NULL;
724 while (!rt2x00queue_empty(queue)) {
725 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 726 if (rt2800_txdone_entry_check(entry, reg))
96481b20 727 break;
96481b20
ID		 728 }
729
730 if (!entry || rt2x00queue_empty(queue))
731 break;
732
14433331 733 rt2800_txdone_entry(entry, reg);
96481b20
ID		 734 }
735}
736EXPORT_SYMBOL_GPL(rt2800_txdone);
737
f0194b2d
GW		 738void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
739{
740 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
741 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
742 unsigned int beacon_base;
743 u32 reg;
744
745 /*
746 * Disable beaconing while we are reloading the beacon data,
747 * otherwise we might be sending out invalid data.
748 */
749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
750 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
751 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
752
753 /*
754 * Add space for the TXWI in front of the skb.
755 */
756 skb_push(entry->skb, TXWI_DESC_SIZE);
757 memset(entry->skb, 0, TXWI_DESC_SIZE);
758
759 /*
760 * Register descriptor details in skb frame descriptor.
761 */
762 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
763 skbdesc->desc = entry->skb->data;
764 skbdesc->desc_len = TXWI_DESC_SIZE;
765
766 /*
767 * Add the TXWI for the beacon to the skb.
768 */
0c5879bc 769 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 770
771 /*
772 * Dump beacon to userspace through debugfs.
773 */
774 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
775
776 /*
777 * Write entire beacon with TXWI to register.
778 */
779 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
780 rt2800_register_multiwrite(rt2x00dev, beacon_base,
781 entry->skb->data, entry->skb->len);
782
783 /*
784 * Enable beaconing again.
785 */
786 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
787 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
788 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
790
791 /*
792 * Clean up beacon skb.
793 */
794 dev_kfree_skb_any(entry->skb);
795 entry->skb = NULL;
796}
50e888ea 797EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 798
fdb87251
HS		 799static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
800 unsigned int beacon_base)
801{
802 int i;
803
804 /*
805 * For the Beacon base registers we only need to clear
806 * the whole TXWI which (when set to 0) will invalidate
807 * the entire beacon.
808 */
809 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
810 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
811}
812
f4450616
BZ		 813#ifdef CONFIG_RT2X00_LIB_DEBUGFS
814const struct rt2x00debug rt2800_rt2x00debug = {
815 .owner = THIS_MODULE,
816 .csr = {
817 .read = rt2800_register_read,
818 .write = rt2800_register_write,
819 .flags = RT2X00DEBUGFS_OFFSET,
820 .word_base = CSR_REG_BASE,
821 .word_size = sizeof(u32),
822 .word_count = CSR_REG_SIZE / sizeof(u32),
823 },
824 .eeprom = {
825 .read = rt2x00_eeprom_read,
826 .write = rt2x00_eeprom_write,
827 .word_base = EEPROM_BASE,
828 .word_size = sizeof(u16),
829 .word_count = EEPROM_SIZE / sizeof(u16),
830 },
831 .bbp = {
832 .read = rt2800_bbp_read,
833 .write = rt2800_bbp_write,
834 .word_base = BBP_BASE,
835 .word_size = sizeof(u8),
836 .word_count = BBP_SIZE / sizeof(u8),
837 },
838 .rf = {
839 .read = rt2x00_rf_read,
840 .write = rt2800_rf_write,
841 .word_base = RF_BASE,
842 .word_size = sizeof(u32),
843 .word_count = RF_SIZE / sizeof(u32),
844 },
845};
846EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
847#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
848
849int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
850{
851 u32 reg;
852
853 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
854 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
855}
856EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
857
858#ifdef CONFIG_RT2X00_LIB_LEDS
859static void rt2800_brightness_set(struct led_classdev *led_cdev,
860 enum led_brightness brightness)
861{
862 struct rt2x00_led *led =
863 container_of(led_cdev, struct rt2x00_led, led_dev);
864 unsigned int enabled = brightness != LED_OFF;
865 unsigned int bg_mode =
866 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
867 unsigned int polarity =
868 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
869 EEPROM_FREQ_LED_POLARITY);
870 unsigned int ledmode =
871 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
872 EEPROM_FREQ_LED_MODE);
873
874 if (led->type == LED_TYPE_RADIO) {
875 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
876 enabled ? 0x20 : 0);
877 } else if (led->type == LED_TYPE_ASSOC) {
878 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
879 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
880 } else if (led->type == LED_TYPE_QUALITY) {
881 /*
882 * The brightness is divided into 6 levels (0 - 5),
883 * The specs tell us the following levels:
884 * 0, 1 ,3, 7, 15, 31
885 * to determine the level in a simple way we can simply
886 * work with bitshifting:
887 * (1 << level) - 1
888 */
889 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
890 (1 << brightness / (LED_FULL / 6)) - 1,
891 polarity);
892 }
893}
894
895static int rt2800_blink_set(struct led_classdev *led_cdev,
896 unsigned long *delay_on, unsigned long *delay_off)
897{
898 struct rt2x00_led *led =
899 container_of(led_cdev, struct rt2x00_led, led_dev);
900 u32 reg;
901
902 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
903 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
904 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 905 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
906
907 return 0;
908}
909
b3579d6a 910static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 911 struct rt2x00_led *led, enum led_type type)
912{
913 led->rt2x00dev = rt2x00dev;
914 led->type = type;
915 led->led_dev.brightness_set = rt2800_brightness_set;
916 led->led_dev.blink_set = rt2800_blink_set;
917 led->flags = LED_INITIALIZED;
918}
f4450616
BZ		 919#endif /* CONFIG_RT2X00_LIB_LEDS */
920
921/*
922 * Configuration handlers.
923 */
924static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
925 struct rt2x00lib_crypto *crypto,
926 struct ieee80211_key_conf *key)
927{
928 struct mac_wcid_entry wcid_entry;
929 struct mac_iveiv_entry iveiv_entry;
930 u32 offset;
931 u32 reg;
932
933 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
934
e4a0ab34
ID		 935 if (crypto->cmd == SET_KEY) {
936 rt2800_register_read(rt2x00dev, offset, &reg);
937 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
938 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
939 /*
940 * Both the cipher as the BSS Idx numbers are split in a main
941 * value of 3 bits, and a extended field for adding one additional
942 * bit to the value.
943 */
944 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
945 (crypto->cipher & 0x7));
946 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
947 (crypto->cipher & 0x8) >> 3);
948 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
949 (crypto->bssidx & 0x7));
950 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
951 (crypto->bssidx & 0x8) >> 3);
952 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
953 rt2800_register_write(rt2x00dev, offset, reg);
954 } else {
955 rt2800_register_write(rt2x00dev, offset, 0);
956 }
f4450616
BZ		 957
958 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
959
960 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
961 if ((crypto->cipher == CIPHER_TKIP) ||
962 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
963 (crypto->cipher == CIPHER_AES))
964 iveiv_entry.iv[3] |= 0x20;
965 iveiv_entry.iv[3] |= key->keyidx << 6;
966 rt2800_register_multiwrite(rt2x00dev, offset,
967 &iveiv_entry, sizeof(iveiv_entry));
968
969 offset = MAC_WCID_ENTRY(key->hw_key_idx);
970
971 memset(&wcid_entry, 0, sizeof(wcid_entry));
972 if (crypto->cmd == SET_KEY)
973 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
974 rt2800_register_multiwrite(rt2x00dev, offset,
975 &wcid_entry, sizeof(wcid_entry));
976}
977
978int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
979 struct rt2x00lib_crypto *crypto,
980 struct ieee80211_key_conf *key)
981{
982 struct hw_key_entry key_entry;
983 struct rt2x00_field32 field;
984 u32 offset;
985 u32 reg;
986
987 if (crypto->cmd == SET_KEY) {
988 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
989
990 memcpy(key_entry.key, crypto->key,
991 sizeof(key_entry.key));
992 memcpy(key_entry.tx_mic, crypto->tx_mic,
993 sizeof(key_entry.tx_mic));
994 memcpy(key_entry.rx_mic, crypto->rx_mic,
995 sizeof(key_entry.rx_mic));
996
997 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
998 rt2800_register_multiwrite(rt2x00dev, offset,
999 &key_entry, sizeof(key_entry));
1000 }
1001
1002 /*
1003 * The cipher types are stored over multiple registers
1004 * starting with SHARED_KEY_MODE_BASE each word will have
1005 * 32 bits and contains the cipher types for 2 bssidx each.
1006 * Using the correct defines correctly will cause overhead,
1007 * so just calculate the correct offset.
1008 */
1009 field.bit_offset = 4 * (key->hw_key_idx % 8);
1010 field.bit_mask = 0x7 << field.bit_offset;
1011
1012 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1013
1014 rt2800_register_read(rt2x00dev, offset, &reg);
1015 rt2x00_set_field32(&reg, field,
1016 (crypto->cmd == SET_KEY) * crypto->cipher);
1017 rt2800_register_write(rt2x00dev, offset, reg);
1018
1019 /*
1020 * Update WCID information
1021 */
1022 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1023
1024 return 0;
1025}
1026EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1027
1028int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1029 struct rt2x00lib_crypto *crypto,
1030 struct ieee80211_key_conf *key)
1031{
1032 struct hw_key_entry key_entry;
1033 u32 offset;
1034
1035 if (crypto->cmd == SET_KEY) {
1036 /*
1037 * 1 pairwise key is possible per AID, this means that the AID
1038 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1039 * last possible shared key entry.
2a0cfeb8
HS		 1040 *
1041 * Since parts of the pairwise key table might be shared with
1042 * the beacon frame buffers 6 & 7 we should only write into the
1043 * first 222 entries.
f4450616 1044 */
2a0cfeb8 1045 if (crypto->aid > (222 - 32))
f4450616
BZ		 1046 return -ENOSPC;
1047
1048 key->hw_key_idx = 32 + crypto->aid;
1049
1050 memcpy(key_entry.key, crypto->key,
1051 sizeof(key_entry.key));
1052 memcpy(key_entry.tx_mic, crypto->tx_mic,
1053 sizeof(key_entry.tx_mic));
1054 memcpy(key_entry.rx_mic, crypto->rx_mic,
1055 sizeof(key_entry.rx_mic));
1056
1057 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1058 rt2800_register_multiwrite(rt2x00dev, offset,
1059 &key_entry, sizeof(key_entry));
1060 }
1061
1062 /*
1063 * Update WCID information
1064 */
1065 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1066
1067 return 0;
1068}
1069EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1070
1071void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1072 const unsigned int filter_flags)
1073{
1074 u32 reg;
1075
1076 /*
1077 * Start configuration steps.
1078 * Note that the version error will always be dropped
1079 * and broadcast frames will always be accepted since
1080 * there is no filter for it at this time.
1081 */
1082 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1083 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1084 !(filter_flags & FIF_FCSFAIL));
1085 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1086 !(filter_flags & FIF_PLCPFAIL));
1087 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1088 !(filter_flags & FIF_PROMISC_IN_BSS));
1089 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1090 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1091 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1092 !(filter_flags & FIF_ALLMULTI));
1093 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1094 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1095 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1096 !(filter_flags & FIF_CONTROL));
1097 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1098 !(filter_flags & FIF_CONTROL));
1099 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1100 !(filter_flags & FIF_CONTROL));
1101 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1102 !(filter_flags & FIF_CONTROL));
1103 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1104 !(filter_flags & FIF_CONTROL));
1105 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1106 !(filter_flags & FIF_PSPOLL));
1107 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1108 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1109 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1110 !(filter_flags & FIF_CONTROL));
1111 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1112}
1113EXPORT_SYMBOL_GPL(rt2800_config_filter);
1114
1115void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1116 struct rt2x00intf_conf *conf, const unsigned int flags)
1117{
f4450616
BZ		 1118 u32 reg;
1119
1120 if (flags & CONFIG_UPDATE_TYPE) {
1121 /*
1122 * Clear current synchronisation setup.
f4450616 1123 */
fdb87251
HS		 1124 rt2800_clear_beacon(rt2x00dev,
1125 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1126 /*
1127 * Enable synchronisation.
1128 */
1129 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1130 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1131 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1132 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1133 (conf->sync == TSF_SYNC_ADHOC ||
1134 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1135 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1136
1137 /*
1138 * Enable pre tbtt interrupt for beaconing modes
1139 */
1140 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1141 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1142 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1143 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1144
f4450616
BZ		 1145 }
1146
1147 if (flags & CONFIG_UPDATE_MAC) {
c600c826
ID		 1148 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1149 reg = le32_to_cpu(conf->mac[1]);
1150 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1151 conf->mac[1] = cpu_to_le32(reg);
1152 }
f4450616
BZ		 1153
1154 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1155 conf->mac, sizeof(conf->mac));
1156 }
1157
1158 if (flags & CONFIG_UPDATE_BSSID) {
c600c826
ID		 1159 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1160 reg = le32_to_cpu(conf->bssid[1]);
1161 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1162 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1163 conf->bssid[1] = cpu_to_le32(reg);
1164 }
f4450616
BZ		 1165
1166 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1167 conf->bssid, sizeof(conf->bssid));
1168 }
1169}
1170EXPORT_SYMBOL_GPL(rt2800_config_intf);
1171
02044643
HS		 1172void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1173 u32 changed)
f4450616
BZ		 1174{
1175 u32 reg;
1176
02044643
HS		 1177 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1178 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1179 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1180 !!erp->short_preamble);
1181 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1182 !!erp->short_preamble);
1183 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1184 }
f4450616 1185
02044643
HS		 1186 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1187 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1188 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1189 erp->cts_protection ? 2 : 0);
1190 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1191 }
f4450616 1192
02044643
HS		 1193 if (changed & BSS_CHANGED_BASIC_RATES) {
1194 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1195 erp->basic_rates);
1196 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1197 }
f4450616 1198
02044643
HS		 1199 if (changed & BSS_CHANGED_ERP_SLOT) {
1200 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1201 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1202 erp->slot_time);
1203 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1204
02044643
HS		 1205 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1206 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1207 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1208 }
f4450616 1209
02044643
HS		 1210 if (changed & BSS_CHANGED_BEACON_INT) {
1211 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1212 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1213 erp->beacon_int * 16);
1214 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1215 }
f4450616
BZ		 1216}
1217EXPORT_SYMBOL_GPL(rt2800_config_erp);
1218
1219void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1220{
1221 u8 r1;
1222 u8 r3;
1223
1224 rt2800_bbp_read(rt2x00dev, 1, &r1);
1225 rt2800_bbp_read(rt2x00dev, 3, &r3);
1226
1227 /*
1228 * Configure the TX antenna.
1229 */
1230 switch ((int)ant->tx) {
1231 case 1:
1232 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1233 break;
1234 case 2:
1235 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1236 break;
1237 case 3:
e22557f2 1238 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1239 break;
1240 }
1241
1242 /*
1243 * Configure the RX antenna.
1244 */
1245 switch ((int)ant->rx) {
1246 case 1:
1247 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1248 break;
1249 case 2:
1250 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1251 break;
1252 case 3:
1253 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1254 break;
1255 }
1256
1257 rt2800_bbp_write(rt2x00dev, 3, r3);
1258 rt2800_bbp_write(rt2x00dev, 1, r1);
1259}
1260EXPORT_SYMBOL_GPL(rt2800_config_ant);
1261
1262static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1263 struct rt2x00lib_conf *libconf)
1264{
1265 u16 eeprom;
1266 short lna_gain;
1267
1268 if (libconf->rf.channel <= 14) {
1269 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1270 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1271 } else if (libconf->rf.channel <= 64) {
1272 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1273 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1274 } else if (libconf->rf.channel <= 128) {
1275 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1276 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1277 } else {
1278 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1279 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1280 }
1281
1282 rt2x00dev->lna_gain = lna_gain;
1283}
1284
06855ef4
GW		 1285static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1286 struct ieee80211_conf *conf,
1287 struct rf_channel *rf,
1288 struct channel_info *info)
f4450616
BZ		 1289{
1290 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1291
1292 if (rt2x00dev->default_ant.tx == 1)
1293 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1294
1295 if (rt2x00dev->default_ant.rx == 1) {
1296 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1297 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1298 } else if (rt2x00dev->default_ant.rx == 2)
1299 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1300
1301 if (rf->channel > 14) {
1302 /*
1303 * When TX power is below 0, we should increase it by 7 to
1304 * make it a positive value (Minumum value is -7).
1305 * However this means that values between 0 and 7 have
1306 * double meaning, and we should set a 7DBm boost flag.
1307 */
1308 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1309 (info->default_power1 >= 0));
f4450616 1310
8d1331b3
ID		 1311 if (info->default_power1 < 0)
1312 info->default_power1 += 7;
f4450616 1313
8d1331b3 1314 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1315
1316 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1317 (info->default_power2 >= 0));
f4450616 1318
8d1331b3
ID		 1319 if (info->default_power2 < 0)
1320 info->default_power2 += 7;
f4450616 1321
8d1331b3 1322 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1323 } else {
8d1331b3
ID		 1324 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1325 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1326 }
1327
1328 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1329
1330 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1331 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1332 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1333 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1334
1335 udelay(200);
1336
1337 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1338 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1339 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1340 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1341
1342 udelay(200);
1343
1344 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1345 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1346 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1347 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1348}
1349
06855ef4
GW		 1350static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1351 struct ieee80211_conf *conf,
1352 struct rf_channel *rf,
1353 struct channel_info *info)
f4450616
BZ		 1354{
1355 u8 rfcsr;
1356
1357 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1358 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1359
1360 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1361 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1362 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1363
1364 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1365 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1366 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1367
5a673964 1368 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1369 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1370 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1371
f4450616
BZ		 1372 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1373 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1374 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1375
1376 rt2800_rfcsr_write(rt2x00dev, 24,
1377 rt2x00dev->calibration[conf_is_ht40(conf)]);
1378
71976907 1379 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1380 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1381 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1382}
1383
1384static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1385 struct ieee80211_conf *conf,
1386 struct rf_channel *rf,
1387 struct channel_info *info)
1388{
1389 u32 reg;
1390 unsigned int tx_pin;
1391 u8 bbp;
1392
46323e11 1393 if (rf->channel <= 14) {
8d1331b3
ID		 1394 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1395 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1396 } else {
8d1331b3
ID		 1397 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1398 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1399 }
1400
06855ef4
GW		 1401 if (rt2x00_rf(rt2x00dev, RF2020) ||
1402 rt2x00_rf(rt2x00dev, RF3020) ||
1403 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1404 rt2x00_rf(rt2x00dev, RF3022) ||
1405 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1406 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1407 else
06855ef4 1408 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1409
1410 /*
1411 * Change BBP settings
1412 */
1413 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1414 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1415 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1416 rt2800_bbp_write(rt2x00dev, 86, 0);
1417
1418 if (rf->channel <= 14) {
1419 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1420 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1421 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1422 } else {
1423 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1424 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1425 }
1426 } else {
1427 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1428
1429 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1430 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1431 else
1432 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1433 }
1434
1435 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1436 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1437 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1438 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1439 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1440
1441 tx_pin = 0;
1442
1443 /* Turn on unused PA or LNA when not using 1T or 1R */
1444 if (rt2x00dev->default_ant.tx != 1) {
1445 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1446 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1447 }
1448
1449 /* Turn on unused PA or LNA when not using 1T or 1R */
1450 if (rt2x00dev->default_ant.rx != 1) {
1451 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1452 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1453 }
1454
1455 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1456 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1457 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1458 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1459 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1460 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1461
1462 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1463
1464 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1465 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1466 rt2800_bbp_write(rt2x00dev, 4, bbp);
1467
1468 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1469 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1470 rt2800_bbp_write(rt2x00dev, 3, bbp);
1471
8d0c9b65 1472 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1473 if (conf_is_ht40(conf)) {
1474 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1475 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1476 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1477 } else {
1478 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1479 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1480 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1481 }
1482 }
1483
1484 msleep(1);
1485}
1486
1487static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1488 const int max_txpower)
f4450616 1489{
5e846004
HS		 1490 u8 txpower;
1491 u8 max_value = (u8)max_txpower;
1492 u16 eeprom;
1493 int i;
f4450616 1494 u32 reg;
f4450616 1495 u8 r1;
5e846004 1496 u32 offset;
f4450616 1497
5e846004
HS		 1498 /*
1499 * set to normal tx power mode: +/- 0dBm
1500 */
f4450616 1501 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1502 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1503 rt2800_bbp_write(rt2x00dev, 1, r1);
1504
5e846004
HS		 1505 /*
1506 * The eeprom contains the tx power values for each rate. These
1507 * values map to 100% tx power. Each 16bit word contains four tx
1508 * power values and the order is the same as used in the TX_PWR_CFG
1509 * registers.
1510 */
1511 offset = TX_PWR_CFG_0;
1512
1513 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1514 /* just to be safe */
1515 if (offset > TX_PWR_CFG_4)
1516 break;
1517
1518 rt2800_register_read(rt2x00dev, offset, &reg);
1519
1520 /* read the next four txpower values */
1521 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1522 &eeprom);
1523
1524 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1525 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1526 * TX_PWR_CFG_4: unknown */
1527 txpower = rt2x00_get_field16(eeprom,
1528 EEPROM_TXPOWER_BYRATE_RATE0);
1529 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1530 min(txpower, max_value));
1531
1532 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1533 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1534 * TX_PWR_CFG_4: unknown */
1535 txpower = rt2x00_get_field16(eeprom,
1536 EEPROM_TXPOWER_BYRATE_RATE1);
1537 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1538 min(txpower, max_value));
1539
1540 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1541 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1542 * TX_PWR_CFG_4: unknown */
1543 txpower = rt2x00_get_field16(eeprom,
1544 EEPROM_TXPOWER_BYRATE_RATE2);
1545 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1546 min(txpower, max_value));
1547
1548 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1549 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1550 * TX_PWR_CFG_4: unknown */
1551 txpower = rt2x00_get_field16(eeprom,
1552 EEPROM_TXPOWER_BYRATE_RATE3);
1553 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1554 min(txpower, max_value));
1555
1556 /* read the next four txpower values */
1557 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1558 &eeprom);
1559
1560 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1561 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1562 * TX_PWR_CFG_4: unknown */
1563 txpower = rt2x00_get_field16(eeprom,
1564 EEPROM_TXPOWER_BYRATE_RATE0);
1565 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1566 min(txpower, max_value));
1567
1568 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1569 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1570 * TX_PWR_CFG_4: unknown */
1571 txpower = rt2x00_get_field16(eeprom,
1572 EEPROM_TXPOWER_BYRATE_RATE1);
1573 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1574 min(txpower, max_value));
1575
1576 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1577 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1578 * TX_PWR_CFG_4: unknown */
1579 txpower = rt2x00_get_field16(eeprom,
1580 EEPROM_TXPOWER_BYRATE_RATE2);
1581 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1582 min(txpower, max_value));
1583
1584 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1585 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1586 * TX_PWR_CFG_4: unknown */
1587 txpower = rt2x00_get_field16(eeprom,
1588 EEPROM_TXPOWER_BYRATE_RATE3);
1589 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1590 min(txpower, max_value));
1591
1592 rt2800_register_write(rt2x00dev, offset, reg);
1593
1594 /* next TX_PWR_CFG register */
1595 offset += 4;
1596 }
f4450616
BZ		 1597}
1598
1599static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1600 struct rt2x00lib_conf *libconf)
1601{
1602 u32 reg;
1603
1604 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1605 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1606 libconf->conf->short_frame_max_tx_count);
1607 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1608 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1609 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1610}
1611
1612static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1613 struct rt2x00lib_conf *libconf)
1614{
1615 enum dev_state state =
1616 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1617 STATE_SLEEP : STATE_AWAKE;
1618 u32 reg;
1619
1620 if (state == STATE_SLEEP) {
1621 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1622
1623 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1624 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1625 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1626 libconf->conf->listen_interval - 1);
1627 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1628 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1629
1630 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1631 } else {
f4450616
BZ		 1632 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1633 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1634 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1635 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1636 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1637
1638 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1639 }
1640}
1641
1642void rt2800_config(struct rt2x00_dev *rt2x00dev,
1643 struct rt2x00lib_conf *libconf,
1644 const unsigned int flags)
1645{
1646 /* Always recalculate LNA gain before changing configuration */
1647 rt2800_config_lna_gain(rt2x00dev, libconf);
1648
1649 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1650 rt2800_config_channel(rt2x00dev, libconf->conf,
1651 &libconf->rf, &libconf->channel);
1652 if (flags & IEEE80211_CONF_CHANGE_POWER)
1653 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1654 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1655 rt2800_config_retry_limit(rt2x00dev, libconf);
1656 if (flags & IEEE80211_CONF_CHANGE_PS)
1657 rt2800_config_ps(rt2x00dev, libconf);
1658}
1659EXPORT_SYMBOL_GPL(rt2800_config);
1660
1661/*
1662 * Link tuning
1663 */
1664void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1665{
1666 u32 reg;
1667
1668 /*
1669 * Update FCS error count from register.
1670 */
1671 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1672 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1673}
1674EXPORT_SYMBOL_GPL(rt2800_link_stats);
1675
1676static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1677{
1678 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1679 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1680 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1681 rt2x00_rt(rt2x00dev, RT3090) ||
1682 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1683 return 0x1c + (2 * rt2x00dev->lna_gain);
1684 else
1685 return 0x2e + rt2x00dev->lna_gain;
1686 }
1687
1688 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1689 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1690 else
1691 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1692}
1693
1694static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1695 struct link_qual *qual, u8 vgc_level)
1696{
1697 if (qual->vgc_level != vgc_level) {
1698 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1699 qual->vgc_level = vgc_level;
1700 qual->vgc_level_reg = vgc_level;
1701 }
1702}
1703
1704void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1705{
1706 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1707}
1708EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1709
1710void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1711 const u32 count)
1712{
8d0c9b65 1713 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1714 return;
1715
1716 /*
1717 * When RSSI is better then -80 increase VGC level with 0x10
1718 */
1719 rt2800_set_vgc(rt2x00dev, qual,
1720 rt2800_get_default_vgc(rt2x00dev) +
1721 ((qual->rssi > -80) * 0x10));
1722}
1723EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1724
1725/*
1726 * Initialization functions.
1727 */
b9a07ae9 1728static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1729{
1730 u32 reg;
d5385bfc 1731 u16 eeprom;
fcf51541 1732 unsigned int i;
e3a896b9 1733 int ret;
fcf51541 1734
a9dce149
GW		 1735 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1736 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1737 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1738 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1739 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1740 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1741 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1742
e3a896b9
GW		 1743 ret = rt2800_drv_init_registers(rt2x00dev);
1744 if (ret)
1745 return ret;
fcf51541
BZ		 1746
1747 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1748 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1749 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1750 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1751 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1752 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1753
1754 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1755 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1756 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1757 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1758 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1759 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1760
1761 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1762 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1763
1764 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1765
1766 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1767 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1768 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1769 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1770 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1771 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1772 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1773 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1774
a9dce149
GW		 1775 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1776
1777 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1778 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1779 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1780 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1781
64522957 1782 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1783 rt2x00_rt(rt2x00dev, RT3090) ||
1784 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1785 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1786 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1787 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1788 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1789 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1790 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1791 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1792 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1793 0x0000002c);
1794 else
1795 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1796 0x0000000f);
1797 } else {
1798 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1799 }
d5385bfc 1800 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1801 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1802
1803 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1805 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1806 } else {
1807 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1808 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1809 }
c295a81d
HS		 1810 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1811 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1812 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1813 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1814 } else {
1815 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1816 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1817 }
1818
1819 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1820 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1821 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1822 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1823 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1824 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1825 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1826 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1827 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1828 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1829
1830 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1831 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1832 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1833 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1834 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1835
1836 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1837 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1838 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1839 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1840 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1841 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1842 else
1843 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1844 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1845 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1846 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1847
a9dce149
GW		 1848 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1849 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1850 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1851 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1852 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1853 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1854 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1855 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1856 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1857
fcf51541
BZ		 1858 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1859
a9dce149
GW		 1860 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1861 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1862 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1863 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1864 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1865 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1866 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1867 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1868
fcf51541
BZ		 1869 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1870 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1871 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1872 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1873 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1874 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1875 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1876 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1877 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1878
1879 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1880 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1881 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1882 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1883 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1884 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1885 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1886 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1887 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1888 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1889 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1890 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1891
1892 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1893 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1894 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1895 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1896 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1897 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1898 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1899 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1900 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1901 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1902 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1903 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1904
1905 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1906 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1907 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1908 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1909 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1910 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1911 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1912 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1913 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1914 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1915 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1916 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1917
1918 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1919 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1920 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1921 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1922 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1923 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1924 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1925 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1926 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1927 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1928 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1929 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1930 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1931
1932 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1933 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1934 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1935 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1936 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1937 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1938 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1939 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1940 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1941 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1942 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1943 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1944
1945 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1946 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1947 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1948 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1949 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1950 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1951 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1952 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1953 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1954 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1955 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1956 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1957
cea90e55 1958 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1959 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1960
1961 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1962 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1963 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1964 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1965 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1966 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1967 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1968 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1969 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1970 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1971 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1972 }
1973
1974 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1975 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1976
1977 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1978 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1979 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1980 IEEE80211_MAX_RTS_THRESHOLD);
1981 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1982 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1983
1984 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1985
a21c2ab4
HS		 1986 /*
1987 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1988 * time should be set to 16. However, the original Ralink driver uses
1989 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1990 * connection problems with 11g + CTS protection. Hence, use the same
1991 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1992 */
a9dce149 1993 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1994 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1995 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1996 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1997 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1998 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1999 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2000
fcf51541
BZ		 2001 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2002
2003 /*
2004 * ASIC will keep garbage value after boot, clear encryption keys.
2005 */
2006 for (i = 0; i < 4; i++)
2007 rt2800_register_write(rt2x00dev,
2008 SHARED_KEY_MODE_ENTRY(i), 0);
2009
2010 for (i = 0; i < 256; i++) {
2011 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2012 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2013 wcid, sizeof(wcid));
2014
2015 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2016 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2017 }
2018
2019 /*
2020 * Clear all beacons
fcf51541 2021 */
fdb87251
HS		 2022 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2023 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2024 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2025 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2026 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2027 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2028 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2029 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2030
cea90e55 2031 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2032 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2033 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2034 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2035 }
2036
2037 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2038 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2039 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2040 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2041 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2042 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2043 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2044 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2045 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2046 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2047
2048 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2049 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2050 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2051 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2052 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2053 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2054 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2055 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2056 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2057 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2058
2059 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2060 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2061 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2062 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2063 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2064 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2065 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2066 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2067 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2068 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2069
2070 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2071 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2072 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2073 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2074 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2075 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2076
47ee3eb1
HS		 2077 /*
2078 * Do not force the BA window size, we use the TXWI to set it
2079 */
2080 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2081 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2082 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2083 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2084
fcf51541
BZ		 2085 /*
2086 * We must clear the error counters.
2087 * These registers are cleared on read,
2088 * so we may pass a useless variable to store the value.
2089 */
2090 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2091 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2092 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2093 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2094 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2095 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2096
9f926fb5
HS		 2097 /*
2098 * Setup leadtime for pre tbtt interrupt to 6ms
2099 */
2100 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2101 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2102 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2103
fcf51541
BZ		 2104 return 0;
2105}
fcf51541
BZ		 2106
2107static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2108{
2109 unsigned int i;
2110 u32 reg;
2111
2112 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2113 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2114 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2115 return 0;
2116
2117 udelay(REGISTER_BUSY_DELAY);
2118 }
2119
2120 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2121 return -EACCES;
2122}
2123
2124static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2125{
2126 unsigned int i;
2127 u8 value;
2128
2129 /*
2130 * BBP was enabled after firmware was loaded,
2131 * but we need to reactivate it now.
2132 */
2133 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2134 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2135 msleep(1);
2136
2137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2138 rt2800_bbp_read(rt2x00dev, 0, &value);
2139 if ((value != 0xff) && (value != 0x00))
2140 return 0;
2141 udelay(REGISTER_BUSY_DELAY);
2142 }
2143
2144 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2145 return -EACCES;
2146}
2147
b9a07ae9 2148static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2149{
2150 unsigned int i;
2151 u16 eeprom;
2152 u8 reg_id;
2153 u8 value;
2154
2155 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2156 rt2800_wait_bbp_ready(rt2x00dev)))
2157 return -EACCES;
2158
baff8006
HS		 2159 if (rt2800_is_305x_soc(rt2x00dev))
2160 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2161
fcf51541
BZ		 2162 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2163 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2164
2165 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2166 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2167 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2168 } else {
2169 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2170 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2171 }
2172
fcf51541 2173 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2174
d5385bfc 2175 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2176 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2177 rt2x00_rt(rt2x00dev, RT3090) ||
2178 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2179 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2180 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2181 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2182 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2183 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2184 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2185 } else {
2186 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2187 }
2188
fcf51541
BZ		 2189 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2190 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2191
5ed8f458 2192 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2193 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2194 else
2195 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2196
fcf51541
BZ		 2197 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2198 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2199 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2200
d5385bfc 2201 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2202 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2203 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2204 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2205 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2206 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2207 else
2208 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2209
baff8006
HS		 2210 if (rt2800_is_305x_soc(rt2x00dev))
2211 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2212 else
2213 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2214 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2215
64522957 2216 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2217 rt2x00_rt(rt2x00dev, RT3090) ||
2218 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2219 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2220
d5385bfc
GW		 2221 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2222 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2223 value |= 0x20;
2224 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2225 value &= ~0x02;
fcf51541 2226
d5385bfc 2227 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2228 }
2229
fcf51541
BZ		 2230
2231 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2232 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2233
2234 if (eeprom != 0xffff && eeprom != 0x0000) {
2235 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2236 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2237 rt2800_bbp_write(rt2x00dev, reg_id, value);
2238 }
2239 }
2240
2241 return 0;
2242}
fcf51541
BZ		 2243
2244static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2245 bool bw40, u8 rfcsr24, u8 filter_target)
2246{
2247 unsigned int i;
2248 u8 bbp;
2249 u8 rfcsr;
2250 u8 passband;
2251 u8 stopband;
2252 u8 overtuned = 0;
2253
2254 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2255
2256 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2257 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2258 rt2800_bbp_write(rt2x00dev, 4, bbp);
2259
2260 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2261 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2262 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2263
2264 /*
2265 * Set power & frequency of passband test tone
2266 */
2267 rt2800_bbp_write(rt2x00dev, 24, 0);
2268
2269 for (i = 0; i < 100; i++) {
2270 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2271 msleep(1);
2272
2273 rt2800_bbp_read(rt2x00dev, 55, &passband);
2274 if (passband)
2275 break;
2276 }
2277
2278 /*
2279 * Set power & frequency of stopband test tone
2280 */
2281 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2282
2283 for (i = 0; i < 100; i++) {
2284 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2285 msleep(1);
2286
2287 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2288
2289 if ((passband - stopband) <= filter_target) {
2290 rfcsr24++;
2291 overtuned += ((passband - stopband) == filter_target);
2292 } else
2293 break;
2294
2295 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2296 }
2297
2298 rfcsr24 -= !!overtuned;
2299
2300 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2301 return rfcsr24;
2302}
2303
b9a07ae9 2304static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2305{
2306 u8 rfcsr;
2307 u8 bbp;
8cdd15e0
GW		 2308 u32 reg;
2309 u16 eeprom;
fcf51541 2310
d5385bfc 2311 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2312 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2313 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2314 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2315 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2316 return 0;
2317
fcf51541
BZ		 2318 /*
2319 * Init RF calibration.
2320 */
2321 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2322 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2323 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2324 msleep(1);
2325 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2326 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2327
d5385bfc 2328 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2329 rt2x00_rt(rt2x00dev, RT3071) ||
2330 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2331 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2332 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2333 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2334 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2335 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2336 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2337 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2338 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2339 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2340 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2341 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2342 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2343 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2344 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2345 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2346 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2347 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2348 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2349 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2350 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2351 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2352 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2353 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2354 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2355 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2356 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2357 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2358 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2359 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2360 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2361 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2362 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2363 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2364 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2365 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2366 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2367 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2368 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2369 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2370 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2371 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2372 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2373 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2374 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2375 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2376 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2377 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2378 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2379 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2380 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2381 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2382 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2383 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2384 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2385 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2386 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2387 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2388 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2389 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2390 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2391 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2392 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2393 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2394 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2395 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2396 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2397 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2398 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2399 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2400 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2401 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2402 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2403 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2404 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2405 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2406 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2407 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2408 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2409 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2410 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2411 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2412 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2413 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2414 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2415 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2416 return 0;
8cdd15e0
GW		 2417 }
2418
2419 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2420 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2421 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2422 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2423 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2424 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2425 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2426 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2427 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2428 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2429
2430 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2431
2432 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2433 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2434 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2435 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2436 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2437 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2438 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2439 else
2440 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2441 }
2442 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2443 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2444 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2445 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2446 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2447 }
2448
2449 /*
2450 * Set RX Filter calibration for 20MHz and 40MHz
2451 */
8cdd15e0
GW		 2452 if (rt2x00_rt(rt2x00dev, RT3070)) {
2453 rt2x00dev->calibration[0] =
2454 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2455 rt2x00dev->calibration[1] =
2456 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2457 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2458 rt2x00_rt(rt2x00dev, RT3090) ||
2459 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2460 rt2x00dev->calibration[0] =
2461 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2462 rt2x00dev->calibration[1] =
2463 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2464 }
fcf51541
BZ		 2465
2466 /*
2467 * Set back to initial state
2468 */
2469 rt2800_bbp_write(rt2x00dev, 24, 0);
2470
2471 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2472 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2473 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2474
2475 /*
2476 * set BBP back to BW20
2477 */
2478 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2479 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2480 rt2800_bbp_write(rt2x00dev, 4, bbp);
2481
d5385bfc 2482 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2483 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2484 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2485 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2486 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2487
2488 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2489 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2490 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2491
2492 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2493 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2494 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2495 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2496 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2497 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2498 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2499 }
8cdd15e0
GW		 2500 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2501 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2502 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2503 rt2x00_get_field16(eeprom,
2504 EEPROM_TXMIXER_GAIN_BG_VAL));
2505 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2506
64522957
GW		 2507 if (rt2x00_rt(rt2x00dev, RT3090)) {
2508 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2509
2510 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2511 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2512 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2513 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2514 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2515
2516 rt2800_bbp_write(rt2x00dev, 138, bbp);
2517 }
2518
2519 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2520 rt2x00_rt(rt2x00dev, RT3090) ||
2521 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2522 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2523 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2524 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2525 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2526 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2527 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2528 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2529
2530 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2531 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2532 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2533
2534 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2535 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2536 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2537
2538 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2539 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2540 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2541 }
2542
2543 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2544 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2545 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2546 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2547 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2548 else
2549 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2550 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2551 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2552 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2553 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2554 }
2555
fcf51541
BZ		 2556 return 0;
2557}
b9a07ae9
ID		 2558
2559int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2560{
2561 u32 reg;
2562 u16 word;
2563
2564 /*
2565 * Initialize all registers.
2566 */
2567 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2568 rt2800_init_registers(rt2x00dev) ||
2569 rt2800_init_bbp(rt2x00dev) ||
2570 rt2800_init_rfcsr(rt2x00dev)))
2571 return -EIO;
2572
2573 /*
2574 * Send signal to firmware during boot time.
2575 */
2576 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2577
2578 if (rt2x00_is_usb(rt2x00dev) &&
2579 (rt2x00_rt(rt2x00dev, RT3070) ||
2580 rt2x00_rt(rt2x00dev, RT3071) ||
2581 rt2x00_rt(rt2x00dev, RT3572))) {
2582 udelay(200);
2583 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2584 udelay(10);
2585 }
2586
2587 /*
2588 * Enable RX.
2589 */
2590 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2591 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2592 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2593 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2594
2595 udelay(50);
2596
2597 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2598 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2599 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2600 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2601 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2602 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2603
2604 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2605 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2606 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2607 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2608
2609 /*
2610 * Initialize LED control
2611 */
2612 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2613 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2614 word & 0xff, (word >> 8) & 0xff);
2615
2616 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2617 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2618 word & 0xff, (word >> 8) & 0xff);
2619
2620 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2621 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2622 word & 0xff, (word >> 8) & 0xff);
2623
2624 return 0;
2625}
2626EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2627
2628void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2629{
2630 u32 reg;
2631
2632 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2633 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2634 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2635 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2636 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2637 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2638 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2639
2640 /* Wait for DMA, ignore error */
2641 rt2800_wait_wpdma_ready(rt2x00dev);
2642
2643 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2644 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2645 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2646 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2647
2648 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2649 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2650}
2651EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2652
30e84034
BZ		 2653int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2654{
2655 u32 reg;
2656
2657 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2658
2659 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2660}
2661EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2662
2663static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2664{
2665 u32 reg;
2666
31a4cf1f
GW		 2667 mutex_lock(&rt2x00dev->csr_mutex);
2668
2669 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2670 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2671 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2672 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2673 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2674
2675 /* Wait until the EEPROM has been loaded */
2676 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2677
2678 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2679 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2680 (u32 *)&rt2x00dev->eeprom[i]);
2681 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2682 (u32 *)&rt2x00dev->eeprom[i + 2]);
2683 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2684 (u32 *)&rt2x00dev->eeprom[i + 4]);
2685 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2686 (u32 *)&rt2x00dev->eeprom[i + 6]);
2687
2688 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2689}
2690
2691void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2692{
2693 unsigned int i;
2694
2695 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2696 rt2800_efuse_read(rt2x00dev, i);
2697}
2698EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2699
38bd7b8a
BZ		 2700int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2701{
2702 u16 word;
2703 u8 *mac;
2704 u8 default_lna_gain;
2705
2706 /*
2707 * Start validation of the data that has been read.
2708 */
2709 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2710 if (!is_valid_ether_addr(mac)) {
2711 random_ether_addr(mac);
2712 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2713 }
2714
2715 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2716 if (word == 0xffff) {
2717 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2718 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2719 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2720 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2721 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2722 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2723 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2724 /*
2725 * There is a max of 2 RX streams for RT28x0 series
2726 */
2727 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2728 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2729 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2730 }
2731
2732 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2733 if (word == 0xffff) {
2734 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2735 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2736 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2737 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2738 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2739 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2740 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2741 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2742 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2743 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2744 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2745 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2746 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2747 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2748 }
2749
2750 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2751 if ((word & 0x00ff) == 0x00ff) {
2752 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2753 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2754 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2755 }
2756 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2757 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2758 LED_MODE_TXRX_ACTIVITY);
2759 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2760 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2761 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2762 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2763 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2764 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2765 }
2766
2767 /*
2768 * During the LNA validation we are going to use
2769 * lna0 as correct value. Note that EEPROM_LNA
2770 * is never validated.
2771 */
2772 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2773 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2774
2775 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2776 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2777 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2778 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2779 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2780 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2781
2782 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2783 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2784 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2785 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2786 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2787 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2788 default_lna_gain);
2789 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2790
2791 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2792 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2793 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2794 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2795 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2796 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2797
2798 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2799 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2800 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2801 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2802 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2803 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2804 default_lna_gain);
2805 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2806
8d1331b3
ID		 2807 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2808 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2809 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2810 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2811 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2812 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2813
38bd7b8a
BZ		 2814 return 0;
2815}
2816EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2817
2818int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2819{
2820 u32 reg;
2821 u16 value;
2822 u16 eeprom;
2823
2824 /*
2825 * Read EEPROM word for configuration.
2826 */
2827 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2828
2829 /*
2830 * Identify RF chipset.
2831 */
2832 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2833 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2834
49e721ec
GW		 2835 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2836 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2837
2838 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2839 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2840 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2841 !rt2x00_rt(rt2x00dev, RT3070) &&
2842 !rt2x00_rt(rt2x00dev, RT3071) &&
2843 !rt2x00_rt(rt2x00dev, RT3090) &&
2844 !rt2x00_rt(rt2x00dev, RT3390) &&
2845 !rt2x00_rt(rt2x00dev, RT3572)) {
2846 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2847 return -ENODEV;
f273fe55 2848 }
714fa663 2849
5122d898
GW		 2850 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2851 !rt2x00_rf(rt2x00dev, RF2850) &&
2852 !rt2x00_rf(rt2x00dev, RF2720) &&
2853 !rt2x00_rf(rt2x00dev, RF2750) &&
2854 !rt2x00_rf(rt2x00dev, RF3020) &&
2855 !rt2x00_rf(rt2x00dev, RF2020) &&
2856 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2857 !rt2x00_rf(rt2x00dev, RF3022) &&
2858 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2859 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2860 return -ENODEV;
2861 }
2862
2863 /*
2864 * Identify default antenna configuration.
2865 */
2866 rt2x00dev->default_ant.tx =
2867 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2868 rt2x00dev->default_ant.rx =
2869 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2870
2871 /*
2872 * Read frequency offset and RF programming sequence.
2873 */
2874 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2875 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2876
2877 /*
2878 * Read external LNA informations.
2879 */
2880 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2881
2882 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2883 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2884 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2885 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2886
2887 /*
2888 * Detect if this device has an hardware controlled radio.
2889 */
2890 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2891 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2892
2893 /*
2894 * Store led settings, for correct led behaviour.
2895 */
2896#ifdef CONFIG_RT2X00_LIB_LEDS
2897 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2898 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2899 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2900
2901 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2902#endif /* CONFIG_RT2X00_LIB_LEDS */
2903
2904 return 0;
2905}
2906EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2907
4da2933f 2908/*
55f9321a 2909 * RF value list for rt28xx
4da2933f
BZ		 2910 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2911 */
2912static const struct rf_channel rf_vals[] = {
2913 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2914 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2915 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2916 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2917 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2918 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2919 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2920 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2921 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2922 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2923 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2924 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2925 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2926 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2927
2928 /* 802.11 UNI / HyperLan 2 */
2929 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2930 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2931 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2932 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2933 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2934 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2935 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2936 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2937 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2938 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2939 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2940 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2941
2942 /* 802.11 HyperLan 2 */
2943 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2944 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2945 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2946 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2947 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2948 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2949 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2950 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2951 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2952 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2953 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2954 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2955 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2956 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2957 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2958 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2959
2960 /* 802.11 UNII */
2961 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2962 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2963 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2964 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2965 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2966 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2967 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2968 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2969 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2970 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2971 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2972
2973 /* 802.11 Japan */
2974 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2975 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2976 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2977 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2978 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2979 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2980 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2981};
2982
2983/*
55f9321a
ID		 2984 * RF value list for rt3xxx
2985 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2986 */
55f9321a 2987static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2988 {1, 241, 2, 2 },
2989 {2, 241, 2, 7 },
2990 {3, 242, 2, 2 },
2991 {4, 242, 2, 7 },
2992 {5, 243, 2, 2 },
2993 {6, 243, 2, 7 },
2994 {7, 244, 2, 2 },
2995 {8, 244, 2, 7 },
2996 {9, 245, 2, 2 },
2997 {10, 245, 2, 7 },
2998 {11, 246, 2, 2 },
2999 {12, 246, 2, 7 },
3000 {13, 247, 2, 2 },
3001 {14, 248, 2, 4 },
55f9321a
ID		 3002
3003 /* 802.11 UNI / HyperLan 2 */
3004 {36, 0x56, 0, 4},
3005 {38, 0x56, 0, 6},
3006 {40, 0x56, 0, 8},
3007 {44, 0x57, 0, 0},
3008 {46, 0x57, 0, 2},
3009 {48, 0x57, 0, 4},
3010 {52, 0x57, 0, 8},
3011 {54, 0x57, 0, 10},
3012 {56, 0x58, 0, 0},
3013 {60, 0x58, 0, 4},
3014 {62, 0x58, 0, 6},
3015 {64, 0x58, 0, 8},
3016
3017 /* 802.11 HyperLan 2 */
3018 {100, 0x5b, 0, 8},
3019 {102, 0x5b, 0, 10},
3020 {104, 0x5c, 0, 0},
3021 {108, 0x5c, 0, 4},
3022 {110, 0x5c, 0, 6},
3023 {112, 0x5c, 0, 8},
3024 {116, 0x5d, 0, 0},
3025 {118, 0x5d, 0, 2},
3026 {120, 0x5d, 0, 4},
3027 {124, 0x5d, 0, 8},
3028 {126, 0x5d, 0, 10},
3029 {128, 0x5e, 0, 0},
3030 {132, 0x5e, 0, 4},
3031 {134, 0x5e, 0, 6},
3032 {136, 0x5e, 0, 8},
3033 {140, 0x5f, 0, 0},
3034
3035 /* 802.11 UNII */
3036 {149, 0x5f, 0, 9},
3037 {151, 0x5f, 0, 11},
3038 {153, 0x60, 0, 1},
3039 {157, 0x60, 0, 5},
3040 {159, 0x60, 0, 7},
3041 {161, 0x60, 0, 9},
3042 {165, 0x61, 0, 1},
3043 {167, 0x61, 0, 3},
3044 {169, 0x61, 0, 5},
3045 {171, 0x61, 0, 7},
3046 {173, 0x61, 0, 9},
4da2933f
BZ		 3047};
3048
3049int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3050{
4da2933f
BZ		 3051 struct hw_mode_spec *spec = &rt2x00dev->spec;
3052 struct channel_info *info;
8d1331b3
ID		 3053 char *default_power1;
3054 char *default_power2;
4da2933f 3055 unsigned int i;
8d1331b3 3056 unsigned short max_power;
4da2933f
BZ		 3057 u16 eeprom;
3058
93b6bd26
GW		 3059 /*
3060 * Disable powersaving as default on PCI devices.
3061 */
cea90e55 3062 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3063 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3064
4da2933f
BZ		 3065 /*
3066 * Initialize all hw fields.
3067 */
3068 rt2x00dev->hw->flags =
3069 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3070 IEEE80211_HW_SIGNAL_DBM |
3071 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3072 IEEE80211_HW_PS_NULLFUNC_STACK |
3073 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 3074
4da2933f
BZ		 3075 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3076 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3077 rt2x00_eeprom_addr(rt2x00dev,
3078 EEPROM_MAC_ADDR_0));
3079
3f2bee24
HS		 3080 /*
3081 * As rt2800 has a global fallback table we cannot specify
3082 * more then one tx rate per frame but since the hw will
3083 * try several rates (based on the fallback table) we should
3084 * still initialize max_rates to the maximum number of rates
3085 * we are going to try. Otherwise mac80211 will truncate our
3086 * reported tx rates and the rc algortihm will end up with
3087 * incorrect data.
3088 */
3089 rt2x00dev->hw->max_rates = 7;
3090 rt2x00dev->hw->max_rate_tries = 1;
3091
4da2933f
BZ		 3092 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3093
3094 /*
3095 * Initialize hw_mode information.
3096 */
3097 spec->supported_bands = SUPPORT_BAND_2GHZ;
3098 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3099
5122d898 3100 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3101 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3102 spec->num_channels = 14;
3103 spec->channels = rf_vals;
55f9321a
ID		 3104 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3105 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3106 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3107 spec->num_channels = ARRAY_SIZE(rf_vals);
3108 spec->channels = rf_vals;
5122d898
GW		 3109 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3110 rt2x00_rf(rt2x00dev, RF2020) ||
3111 rt2x00_rf(rt2x00dev, RF3021) ||
3112 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3113 spec->num_channels = 14;
3114 spec->channels = rf_vals_3x;
3115 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3116 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3117 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3118 spec->channels = rf_vals_3x;
4da2933f
BZ		 3119 }
3120
3121 /*
3122 * Initialize HT information.
3123 */
5122d898 3124 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3125 spec->ht.ht_supported = true;
3126 else
3127 spec->ht.ht_supported = false;
3128
4da2933f 3129 spec->ht.cap =
06443e46 3130 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3131 IEEE80211_HT_CAP_GRN_FLD |
3132 IEEE80211_HT_CAP_SGI_20 |
aa674631 3133 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3134
3135 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3136 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3137
aa674631
ID		 3138 spec->ht.cap |=
3139 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3140 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3141
4da2933f
BZ		 3142 spec->ht.ampdu_factor = 3;
3143 spec->ht.ampdu_density = 4;
3144 spec->ht.mcs.tx_params =
3145 IEEE80211_HT_MCS_TX_DEFINED |
3146 IEEE80211_HT_MCS_TX_RX_DIFF |
3147 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3148 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3149
3150 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3151 case 3:
3152 spec->ht.mcs.rx_mask[2] = 0xff;
3153 case 2:
3154 spec->ht.mcs.rx_mask[1] = 0xff;
3155 case 1:
3156 spec->ht.mcs.rx_mask[0] = 0xff;
3157 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3158 break;
3159 }
3160
3161 /*
3162 * Create channel information array
3163 */
3164 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3165 if (!info)
3166 return -ENOMEM;
3167
3168 spec->channels_info = info;
3169
8d1331b3
ID		 3170 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3171 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3172 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3173 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3174
3175 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3176 info[i].max_power = max_power;
3177 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3178 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3179 }
3180
3181 if (spec->num_channels > 14) {
8d1331b3
ID		 3182 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3183 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3184 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3185
3186 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3187 info[i].max_power = max_power;
3188 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3189 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3190 }
3191 }
3192
3193 return 0;
3194}
3195EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3196
2ce33995
BZ		 3197/*
3198 * IEEE80211 stack callback functions.
3199 */
e783619e
HS		 3200void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3201 u16 *iv16)
2ce33995
BZ		 3202{
3203 struct rt2x00_dev *rt2x00dev = hw->priv;
3204 struct mac_iveiv_entry iveiv_entry;
3205 u32 offset;
3206
3207 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3208 rt2800_register_multiread(rt2x00dev, offset,
3209 &iveiv_entry, sizeof(iveiv_entry));
3210
855da5e0
JL		 3211 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3212 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3213}
e783619e 3214EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3215
e783619e 3216int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3217{
3218 struct rt2x00_dev *rt2x00dev = hw->priv;
3219 u32 reg;
3220 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3221
3222 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3223 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3224 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3225
3226 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3227 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3228 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3229
3230 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3231 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3232 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3233
3234 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3235 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3236 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3237
3238 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3239 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3240 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3241
3242 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3243 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3244 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3245
3246 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3247 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3248 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3249
3250 return 0;
3251}
e783619e 3252EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3253
e783619e
HS		 3254int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3255 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3256{
3257 struct rt2x00_dev *rt2x00dev = hw->priv;
3258 struct data_queue *queue;
3259 struct rt2x00_field32 field;
3260 int retval;
3261 u32 reg;
3262 u32 offset;
3263
3264 /*
3265 * First pass the configuration through rt2x00lib, that will
3266 * update the queue settings and validate the input. After that
3267 * we are free to update the registers based on the value
3268 * in the queue parameter.
3269 */
3270 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3271 if (retval)
3272 return retval;
3273
3274 /*
3275 * We only need to perform additional register initialization
3276 * for WMM queues/
3277 */
3278 if (queue_idx >= 4)
3279 return 0;
3280
3281 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3282
3283 /* Update WMM TXOP register */
3284 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3285 field.bit_offset = (queue_idx & 1) * 16;
3286 field.bit_mask = 0xffff << field.bit_offset;
3287
3288 rt2800_register_read(rt2x00dev, offset, &reg);
3289 rt2x00_set_field32(&reg, field, queue->txop);
3290 rt2800_register_write(rt2x00dev, offset, reg);
3291
3292 /* Update WMM registers */
3293 field.bit_offset = queue_idx * 4;
3294 field.bit_mask = 0xf << field.bit_offset;
3295
3296 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3297 rt2x00_set_field32(&reg, field, queue->aifs);
3298 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3299
3300 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3301 rt2x00_set_field32(&reg, field, queue->cw_min);
3302 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3303
3304 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3305 rt2x00_set_field32(&reg, field, queue->cw_max);
3306 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3307
3308 /* Update EDCA registers */
3309 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3310
3311 rt2800_register_read(rt2x00dev, offset, &reg);
3312 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3313 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3314 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3315 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3316 rt2800_register_write(rt2x00dev, offset, reg);
3317
3318 return 0;
3319}
e783619e 3320EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3321
e783619e 3322u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3323{
3324 struct rt2x00_dev *rt2x00dev = hw->priv;
3325 u64 tsf;
3326 u32 reg;
3327
3328 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3329 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3330 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3331 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3332
3333 return tsf;
3334}
e783619e 3335EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3336
e783619e
HS		 3337int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3338 enum ieee80211_ampdu_mlme_action action,
3339 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3340{
1df90809
HS		 3341 int ret = 0;
3342
3343 switch (action) {
3344 case IEEE80211_AMPDU_RX_START:
3345 case IEEE80211_AMPDU_RX_STOP:
3346 /* we don't support RX aggregation yet */
3347 ret = -ENOTSUPP;
3348 break;
3349 case IEEE80211_AMPDU_TX_START:
3350 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3351 break;
3352 case IEEE80211_AMPDU_TX_STOP:
3353 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3354 break;
3355 case IEEE80211_AMPDU_TX_OPERATIONAL:
3356 break;
3357 default:
4e9e58c6 3358 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3359 }
3360
3361 return ret;
3362}
e783619e 3363EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3364
3365MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3366MODULE_VERSION(DRV_VERSION);
3367MODULE_DESCRIPTION("Ralink RT2800 library");
3368MODULE_LICENSE("GPL");
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