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Commit | Line | Data |
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89297425 | 1 | /* |
96481b20 | 2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
a5ea2f02 | 3 | Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> |
9c9a0d14 | 4 | Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> |
cce5fc45 | 5 | Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
89297425 | 6 | |
9c9a0d14 | 7 | Based on the original rt2800pci.c and rt2800usb.c. |
9c9a0d14 GW |
8 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
9 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
10 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
11 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
12 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
13 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
89297425 BZ |
14 | <http://rt2x00.serialmonkey.com> |
15 | ||
16 | This program is free software; you can redistribute it and/or modify | |
17 | it under the terms of the GNU General Public License as published by | |
18 | the Free Software Foundation; either version 2 of the License, or | |
19 | (at your option) any later version. | |
20 | ||
21 | This program is distributed in the hope that it will be useful, | |
22 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | GNU General Public License for more details. | |
25 | ||
26 | You should have received a copy of the GNU General Public License | |
27 | along with this program; if not, write to the | |
28 | Free Software Foundation, Inc., | |
29 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
32 | /* | |
33 | Module: rt2800lib | |
34 | Abstract: rt2800 generic device routines. | |
35 | */ | |
36 | ||
f31c9a8c | 37 | #include <linux/crc-ccitt.h> |
89297425 BZ |
38 | #include <linux/kernel.h> |
39 | #include <linux/module.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
89297425 BZ |
41 | |
42 | #include "rt2x00.h" | |
43 | #include "rt2800lib.h" | |
44 | #include "rt2800.h" | |
45 | ||
89297425 BZ |
46 | /* |
47 | * Register access. | |
48 | * All access to the CSR registers will go through the methods | |
49 | * rt2800_register_read and rt2800_register_write. | |
50 | * BBP and RF register require indirect register access, | |
51 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
52 | * These indirect registers work with busy bits, | |
53 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
54 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
55 | * between each attampt. When the busy bit is still set at that time, | |
56 | * the access attempt is considered to have failed, | |
57 | * and we will print an error. | |
58 | * The _lock versions must be used if you already hold the csr_mutex | |
59 | */ | |
60 | #define WAIT_FOR_BBP(__dev, __reg) \ | |
61 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) | |
62 | #define WAIT_FOR_RFCSR(__dev, __reg) \ | |
63 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) | |
64 | #define WAIT_FOR_RF(__dev, __reg) \ | |
65 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) | |
66 | #define WAIT_FOR_MCU(__dev, __reg) \ | |
67 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ | |
68 | H2M_MAILBOX_CSR_OWNER, (__reg)) | |
69 | ||
baff8006 HS |
70 | static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) |
71 | { | |
72 | /* check for rt2872 on SoC */ | |
73 | if (!rt2x00_is_soc(rt2x00dev) || | |
74 | !rt2x00_rt(rt2x00dev, RT2872)) | |
75 | return false; | |
76 | ||
77 | /* we know for sure that these rf chipsets are used on rt305x boards */ | |
78 | if (rt2x00_rf(rt2x00dev, RF3020) || | |
79 | rt2x00_rf(rt2x00dev, RF3021) || | |
80 | rt2x00_rf(rt2x00dev, RF3022)) | |
81 | return true; | |
82 | ||
83 | NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n"); | |
84 | return false; | |
85 | } | |
86 | ||
fcf51541 BZ |
87 | static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
88 | const unsigned int word, const u8 value) | |
89297425 BZ |
89 | { |
90 | u32 reg; | |
91 | ||
92 | mutex_lock(&rt2x00dev->csr_mutex); | |
93 | ||
94 | /* | |
95 | * Wait until the BBP becomes available, afterwards we | |
96 | * can safely write the new data into the register. | |
97 | */ | |
98 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
99 | reg = 0; | |
100 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); | |
101 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
102 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
103 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); | |
efc7d36f | 104 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
105 | |
106 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
107 | } | |
108 | ||
109 | mutex_unlock(&rt2x00dev->csr_mutex); | |
110 | } | |
89297425 | 111 | |
fcf51541 BZ |
112 | static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
113 | const unsigned int word, u8 *value) | |
89297425 BZ |
114 | { |
115 | u32 reg; | |
116 | ||
117 | mutex_lock(&rt2x00dev->csr_mutex); | |
118 | ||
119 | /* | |
120 | * Wait until the BBP becomes available, afterwards we | |
121 | * can safely write the read request into the register. | |
122 | * After the data has been written, we wait until hardware | |
123 | * returns the correct value, if at any time the register | |
124 | * doesn't become available in time, reg will be 0xffffffff | |
125 | * which means we return 0xff to the caller. | |
126 | */ | |
127 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
128 | reg = 0; | |
129 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
130 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
131 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); | |
efc7d36f | 132 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
89297425 BZ |
133 | |
134 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
135 | ||
136 | WAIT_FOR_BBP(rt2x00dev, ®); | |
137 | } | |
138 | ||
139 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); | |
140 | ||
141 | mutex_unlock(&rt2x00dev->csr_mutex); | |
142 | } | |
89297425 | 143 | |
fcf51541 BZ |
144 | static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
145 | const unsigned int word, const u8 value) | |
89297425 BZ |
146 | { |
147 | u32 reg; | |
148 | ||
149 | mutex_lock(&rt2x00dev->csr_mutex); | |
150 | ||
151 | /* | |
152 | * Wait until the RFCSR becomes available, afterwards we | |
153 | * can safely write the new data into the register. | |
154 | */ | |
155 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
156 | reg = 0; | |
157 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); | |
158 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
159 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); | |
160 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
161 | ||
162 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
163 | } | |
164 | ||
165 | mutex_unlock(&rt2x00dev->csr_mutex); | |
166 | } | |
89297425 | 167 | |
fcf51541 BZ |
168 | static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
169 | const unsigned int word, u8 *value) | |
89297425 BZ |
170 | { |
171 | u32 reg; | |
172 | ||
173 | mutex_lock(&rt2x00dev->csr_mutex); | |
174 | ||
175 | /* | |
176 | * Wait until the RFCSR becomes available, afterwards we | |
177 | * can safely write the read request into the register. | |
178 | * After the data has been written, we wait until hardware | |
179 | * returns the correct value, if at any time the register | |
180 | * doesn't become available in time, reg will be 0xffffffff | |
181 | * which means we return 0xff to the caller. | |
182 | */ | |
183 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
184 | reg = 0; | |
185 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
186 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); | |
187 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
188 | ||
189 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
190 | ||
191 | WAIT_FOR_RFCSR(rt2x00dev, ®); | |
192 | } | |
193 | ||
194 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); | |
195 | ||
196 | mutex_unlock(&rt2x00dev->csr_mutex); | |
197 | } | |
89297425 | 198 | |
fcf51541 BZ |
199 | static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
200 | const unsigned int word, const u32 value) | |
89297425 BZ |
201 | { |
202 | u32 reg; | |
203 | ||
204 | mutex_lock(&rt2x00dev->csr_mutex); | |
205 | ||
206 | /* | |
207 | * Wait until the RF becomes available, afterwards we | |
208 | * can safely write the new data into the register. | |
209 | */ | |
210 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
211 | reg = 0; | |
212 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); | |
213 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); | |
214 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); | |
215 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); | |
216 | ||
217 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); | |
218 | rt2x00_rf_write(rt2x00dev, word, value); | |
219 | } | |
220 | ||
221 | mutex_unlock(&rt2x00dev->csr_mutex); | |
222 | } | |
89297425 BZ |
223 | |
224 | void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, | |
225 | const u8 command, const u8 token, | |
226 | const u8 arg0, const u8 arg1) | |
227 | { | |
228 | u32 reg; | |
229 | ||
ee303e54 | 230 | /* |
cea90e55 | 231 | * SOC devices don't support MCU requests. |
ee303e54 | 232 | */ |
cea90e55 | 233 | if (rt2x00_is_soc(rt2x00dev)) |
ee303e54 | 234 | return; |
89297425 BZ |
235 | |
236 | mutex_lock(&rt2x00dev->csr_mutex); | |
237 | ||
238 | /* | |
239 | * Wait until the MCU becomes available, afterwards we | |
240 | * can safely write the new data into the register. | |
241 | */ | |
242 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { | |
243 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
244 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
245 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
246 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
247 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); | |
248 | ||
249 | reg = 0; | |
250 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); | |
251 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); | |
252 | } | |
253 | ||
254 | mutex_unlock(&rt2x00dev->csr_mutex); | |
255 | } | |
256 | EXPORT_SYMBOL_GPL(rt2800_mcu_request); | |
f4450616 | 257 | |
5ffddc49 ID |
258 | int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) |
259 | { | |
260 | unsigned int i = 0; | |
261 | u32 reg; | |
262 | ||
263 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
264 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
265 | if (reg && reg != ~0) | |
266 | return 0; | |
267 | msleep(1); | |
268 | } | |
269 | ||
270 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
271 | return -EBUSY; | |
272 | } | |
273 | EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); | |
274 | ||
67a4c1e2 GW |
275 | int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) |
276 | { | |
277 | unsigned int i; | |
278 | u32 reg; | |
279 | ||
08e53100 HS |
280 | /* |
281 | * Some devices are really slow to respond here. Wait a whole second | |
282 | * before timing out. | |
283 | */ | |
67a4c1e2 GW |
284 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
285 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
286 | if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && | |
287 | !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) | |
288 | return 0; | |
289 | ||
08e53100 | 290 | msleep(10); |
67a4c1e2 GW |
291 | } |
292 | ||
293 | ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); | |
294 | return -EACCES; | |
295 | } | |
296 | EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); | |
297 | ||
f31c9a8c ID |
298 | static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) |
299 | { | |
300 | u16 fw_crc; | |
301 | u16 crc; | |
302 | ||
303 | /* | |
304 | * The last 2 bytes in the firmware array are the crc checksum itself, | |
305 | * this means that we should never pass those 2 bytes to the crc | |
306 | * algorithm. | |
307 | */ | |
308 | fw_crc = (data[len - 2] << 8 | data[len - 1]); | |
309 | ||
310 | /* | |
311 | * Use the crc ccitt algorithm. | |
312 | * This will return the same value as the legacy driver which | |
313 | * used bit ordering reversion on the both the firmware bytes | |
314 | * before input input as well as on the final output. | |
315 | * Obviously using crc ccitt directly is much more efficient. | |
316 | */ | |
317 | crc = crc_ccitt(~0, data, len - 2); | |
318 | ||
319 | /* | |
320 | * There is a small difference between the crc-itu-t + bitrev and | |
321 | * the crc-ccitt crc calculation. In the latter method the 2 bytes | |
322 | * will be swapped, use swab16 to convert the crc to the correct | |
323 | * value. | |
324 | */ | |
325 | crc = swab16(crc); | |
326 | ||
327 | return fw_crc == crc; | |
328 | } | |
329 | ||
330 | int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, | |
331 | const u8 *data, const size_t len) | |
332 | { | |
333 | size_t offset = 0; | |
334 | size_t fw_len; | |
335 | bool multiple; | |
336 | ||
337 | /* | |
338 | * PCI(e) & SOC devices require firmware with a length | |
339 | * of 8kb. USB devices require firmware files with a length | |
340 | * of 4kb. Certain USB chipsets however require different firmware, | |
341 | * which Ralink only provides attached to the original firmware | |
342 | * file. Thus for USB devices, firmware files have a length | |
343 | * which is a multiple of 4kb. | |
344 | */ | |
345 | if (rt2x00_is_usb(rt2x00dev)) { | |
346 | fw_len = 4096; | |
347 | multiple = true; | |
348 | } else { | |
349 | fw_len = 8192; | |
350 | multiple = true; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Validate the firmware length | |
355 | */ | |
356 | if (len != fw_len && (!multiple || (len % fw_len) != 0)) | |
357 | return FW_BAD_LENGTH; | |
358 | ||
359 | /* | |
360 | * Check if the chipset requires one of the upper parts | |
361 | * of the firmware. | |
362 | */ | |
363 | if (rt2x00_is_usb(rt2x00dev) && | |
364 | !rt2x00_rt(rt2x00dev, RT2860) && | |
365 | !rt2x00_rt(rt2x00dev, RT2872) && | |
366 | !rt2x00_rt(rt2x00dev, RT3070) && | |
367 | ((len / fw_len) == 1)) | |
368 | return FW_BAD_VERSION; | |
369 | ||
370 | /* | |
371 | * 8kb firmware files must be checked as if it were | |
372 | * 2 separate firmware files. | |
373 | */ | |
374 | while (offset < len) { | |
375 | if (!rt2800_check_firmware_crc(data + offset, fw_len)) | |
376 | return FW_BAD_CRC; | |
377 | ||
378 | offset += fw_len; | |
379 | } | |
380 | ||
381 | return FW_OK; | |
382 | } | |
383 | EXPORT_SYMBOL_GPL(rt2800_check_firmware); | |
384 | ||
385 | int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, | |
386 | const u8 *data, const size_t len) | |
387 | { | |
388 | unsigned int i; | |
389 | u32 reg; | |
390 | ||
391 | /* | |
b9eca242 ID |
392 | * If driver doesn't wake up firmware here, |
393 | * rt2800_load_firmware will hang forever when interface is up again. | |
f31c9a8c | 394 | */ |
b9eca242 | 395 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); |
f31c9a8c | 396 | |
f31c9a8c ID |
397 | /* |
398 | * Wait for stable hardware. | |
399 | */ | |
5ffddc49 | 400 | if (rt2800_wait_csr_ready(rt2x00dev)) |
f31c9a8c | 401 | return -EBUSY; |
f31c9a8c | 402 | |
adde5882 | 403 | if (rt2x00_is_pci(rt2x00dev)) { |
872834df GW |
404 | if (rt2x00_rt(rt2x00dev, RT3572) || |
405 | rt2x00_rt(rt2x00dev, RT5390)) { | |
adde5882 GJ |
406 | rt2800_register_read(rt2x00dev, AUX_CTRL, ®); |
407 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); | |
408 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); | |
409 | rt2800_register_write(rt2x00dev, AUX_CTRL, reg); | |
410 | } | |
f31c9a8c | 411 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); |
adde5882 | 412 | } |
f31c9a8c ID |
413 | |
414 | /* | |
415 | * Disable DMA, will be reenabled later when enabling | |
416 | * the radio. | |
417 | */ | |
418 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
419 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
420 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
421 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
422 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
423 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
424 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
425 | ||
426 | /* | |
427 | * Write firmware to the device. | |
428 | */ | |
429 | rt2800_drv_write_firmware(rt2x00dev, data, len); | |
430 | ||
431 | /* | |
432 | * Wait for device to stabilize. | |
433 | */ | |
434 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
435 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); | |
436 | if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) | |
437 | break; | |
438 | msleep(1); | |
439 | } | |
440 | ||
441 | if (i == REGISTER_BUSY_COUNT) { | |
442 | ERROR(rt2x00dev, "PBF system register not ready.\n"); | |
443 | return -EBUSY; | |
444 | } | |
445 | ||
446 | /* | |
447 | * Initialize firmware. | |
448 | */ | |
449 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
450 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
451 | msleep(1); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | EXPORT_SYMBOL_GPL(rt2800_load_firmware); | |
456 | ||
0c5879bc ID |
457 | void rt2800_write_tx_data(struct queue_entry *entry, |
458 | struct txentry_desc *txdesc) | |
59679b91 | 459 | { |
0c5879bc | 460 | __le32 *txwi = rt2800_drv_get_txwi(entry); |
59679b91 GW |
461 | u32 word; |
462 | ||
463 | /* | |
464 | * Initialize TX Info descriptor | |
465 | */ | |
466 | rt2x00_desc_read(txwi, 0, &word); | |
467 | rt2x00_set_field32(&word, TXWI_W0_FRAG, | |
468 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
84804cdc ID |
469 | rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, |
470 | test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); | |
59679b91 GW |
471 | rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); |
472 | rt2x00_set_field32(&word, TXWI_W0_TS, | |
473 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
474 | rt2x00_set_field32(&word, TXWI_W0_AMPDU, | |
475 | test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); | |
26a1d07f HS |
476 | rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, |
477 | txdesc->u.ht.mpdu_density); | |
478 | rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); | |
479 | rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); | |
59679b91 GW |
480 | rt2x00_set_field32(&word, TXWI_W0_BW, |
481 | test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); | |
482 | rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, | |
483 | test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); | |
26a1d07f | 484 | rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); |
59679b91 GW |
485 | rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); |
486 | rt2x00_desc_write(txwi, 0, word); | |
487 | ||
488 | rt2x00_desc_read(txwi, 1, &word); | |
489 | rt2x00_set_field32(&word, TXWI_W1_ACK, | |
490 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
491 | rt2x00_set_field32(&word, TXWI_W1_NSEQ, | |
492 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
26a1d07f | 493 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); |
59679b91 GW |
494 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, |
495 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? | |
a2b1328a | 496 | txdesc->key_idx : txdesc->u.ht.wcid); |
59679b91 GW |
497 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, |
498 | txdesc->length); | |
2b23cdaa | 499 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); |
bc8a979e | 500 | rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); |
59679b91 GW |
501 | rt2x00_desc_write(txwi, 1, word); |
502 | ||
503 | /* | |
504 | * Always write 0 to IV/EIV fields, hardware will insert the IV | |
505 | * from the IVEIV register when TXD_W3_WIV is set to 0. | |
506 | * When TXD_W3_WIV is set to 1 it will use the IV data | |
507 | * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which | |
508 | * crypto entry in the registers should be used to encrypt the frame. | |
509 | */ | |
510 | _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); | |
511 | _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); | |
512 | } | |
0c5879bc | 513 | EXPORT_SYMBOL_GPL(rt2800_write_tx_data); |
59679b91 | 514 | |
ff6133be | 515 | static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) |
2de64dd2 | 516 | { |
74861922 ID |
517 | int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); |
518 | int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); | |
519 | int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); | |
520 | u16 eeprom; | |
521 | u8 offset0; | |
522 | u8 offset1; | |
523 | u8 offset2; | |
524 | ||
e5ef5bad | 525 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { |
74861922 ID |
526 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); |
527 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); | |
528 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); | |
529 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
530 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); | |
531 | } else { | |
532 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); | |
533 | offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); | |
534 | offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); | |
535 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
536 | offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); | |
537 | } | |
538 | ||
539 | /* | |
540 | * Convert the value from the descriptor into the RSSI value | |
541 | * If the value in the descriptor is 0, it is considered invalid | |
542 | * and the default (extremely low) rssi value is assumed | |
543 | */ | |
544 | rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; | |
545 | rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; | |
546 | rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; | |
547 | ||
548 | /* | |
549 | * mac80211 only accepts a single RSSI value. Calculating the | |
550 | * average doesn't deliver a fair answer either since -60:-60 would | |
551 | * be considered equally good as -50:-70 while the second is the one | |
552 | * which gives less energy... | |
553 | */ | |
554 | rssi0 = max(rssi0, rssi1); | |
555 | return max(rssi0, rssi2); | |
556 | } | |
557 | ||
558 | void rt2800_process_rxwi(struct queue_entry *entry, | |
559 | struct rxdone_entry_desc *rxdesc) | |
560 | { | |
561 | __le32 *rxwi = (__le32 *) entry->skb->data; | |
2de64dd2 GW |
562 | u32 word; |
563 | ||
564 | rt2x00_desc_read(rxwi, 0, &word); | |
565 | ||
566 | rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); | |
567 | rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); | |
568 | ||
569 | rt2x00_desc_read(rxwi, 1, &word); | |
570 | ||
571 | if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) | |
572 | rxdesc->flags |= RX_FLAG_SHORT_GI; | |
573 | ||
574 | if (rt2x00_get_field32(word, RXWI_W1_BW)) | |
575 | rxdesc->flags |= RX_FLAG_40MHZ; | |
576 | ||
577 | /* | |
578 | * Detect RX rate, always use MCS as signal type. | |
579 | */ | |
580 | rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; | |
581 | rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); | |
582 | rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); | |
583 | ||
584 | /* | |
585 | * Mask of 0x8 bit to remove the short preamble flag. | |
586 | */ | |
587 | if (rxdesc->rate_mode == RATE_MODE_CCK) | |
588 | rxdesc->signal &= ~0x8; | |
589 | ||
590 | rt2x00_desc_read(rxwi, 2, &word); | |
591 | ||
74861922 ID |
592 | /* |
593 | * Convert descriptor AGC value to RSSI value. | |
594 | */ | |
595 | rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); | |
2de64dd2 GW |
596 | |
597 | /* | |
598 | * Remove RXWI descriptor from start of buffer. | |
599 | */ | |
74861922 | 600 | skb_pull(entry->skb, RXWI_DESC_SIZE); |
2de64dd2 GW |
601 | } |
602 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); | |
603 | ||
31937c42 | 604 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) |
14433331 HS |
605 | { |
606 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
b34793ee | 607 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
14433331 HS |
608 | struct txdone_entry_desc txdesc; |
609 | u32 word; | |
610 | u16 mcs, real_mcs; | |
b34793ee | 611 | int aggr, ampdu; |
14433331 HS |
612 | |
613 | /* | |
614 | * Obtain the status about this packet. | |
615 | */ | |
616 | txdesc.flags = 0; | |
14433331 | 617 | rt2x00_desc_read(txwi, 0, &word); |
b34793ee | 618 | |
14433331 | 619 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); |
b34793ee HS |
620 | ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); |
621 | ||
14433331 | 622 | real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); |
b34793ee HS |
623 | aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); |
624 | ||
625 | /* | |
626 | * If a frame was meant to be sent as a single non-aggregated MPDU | |
627 | * but ended up in an aggregate the used tx rate doesn't correlate | |
628 | * with the one specified in the TXWI as the whole aggregate is sent | |
629 | * with the same rate. | |
630 | * | |
631 | * For example: two frames are sent to rt2x00, the first one sets | |
632 | * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 | |
633 | * and requests MCS15. If the hw aggregates both frames into one | |
634 | * AMDPU the tx status for both frames will contain MCS7 although | |
635 | * the frame was sent successfully. | |
636 | * | |
637 | * Hence, replace the requested rate with the real tx rate to not | |
638 | * confuse the rate control algortihm by providing clearly wrong | |
639 | * data. | |
640 | */ | |
5356d963 | 641 | if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { |
b34793ee HS |
642 | skbdesc->tx_rate_idx = real_mcs; |
643 | mcs = real_mcs; | |
644 | } | |
14433331 | 645 | |
f16d2db7 HS |
646 | if (aggr == 1 || ampdu == 1) |
647 | __set_bit(TXDONE_AMPDU, &txdesc.flags); | |
648 | ||
14433331 HS |
649 | /* |
650 | * Ralink has a retry mechanism using a global fallback | |
651 | * table. We setup this fallback table to try the immediate | |
652 | * lower rate for all rates. In the TX_STA_FIFO, the MCS field | |
653 | * always contains the MCS used for the last transmission, be | |
654 | * it successful or not. | |
655 | */ | |
656 | if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { | |
657 | /* | |
658 | * Transmission succeeded. The number of retries is | |
659 | * mcs - real_mcs | |
660 | */ | |
661 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
662 | txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); | |
663 | } else { | |
664 | /* | |
665 | * Transmission failed. The number of retries is | |
666 | * always 7 in this case (for a total number of 8 | |
667 | * frames sent). | |
668 | */ | |
669 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
670 | txdesc.retry = rt2x00dev->long_retry; | |
671 | } | |
672 | ||
673 | /* | |
674 | * the frame was retried at least once | |
675 | * -> hw used fallback rates | |
676 | */ | |
677 | if (txdesc.retry) | |
678 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); | |
679 | ||
680 | rt2x00lib_txdone(entry, &txdesc); | |
681 | } | |
682 | EXPORT_SYMBOL_GPL(rt2800_txdone_entry); | |
683 | ||
f0194b2d GW |
684 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) |
685 | { | |
686 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
687 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
688 | unsigned int beacon_base; | |
739fd940 | 689 | unsigned int padding_len; |
d76dfc61 | 690 | u32 orig_reg, reg; |
f0194b2d GW |
691 | |
692 | /* | |
693 | * Disable beaconing while we are reloading the beacon data, | |
694 | * otherwise we might be sending out invalid data. | |
695 | */ | |
696 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
d76dfc61 | 697 | orig_reg = reg; |
f0194b2d GW |
698 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
699 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
700 | ||
701 | /* | |
702 | * Add space for the TXWI in front of the skb. | |
703 | */ | |
b52398b6 | 704 | memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE); |
f0194b2d GW |
705 | |
706 | /* | |
707 | * Register descriptor details in skb frame descriptor. | |
708 | */ | |
709 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; | |
710 | skbdesc->desc = entry->skb->data; | |
711 | skbdesc->desc_len = TXWI_DESC_SIZE; | |
712 | ||
713 | /* | |
714 | * Add the TXWI for the beacon to the skb. | |
715 | */ | |
0c5879bc | 716 | rt2800_write_tx_data(entry, txdesc); |
f0194b2d GW |
717 | |
718 | /* | |
719 | * Dump beacon to userspace through debugfs. | |
720 | */ | |
721 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
722 | ||
723 | /* | |
739fd940 | 724 | * Write entire beacon with TXWI and padding to register. |
f0194b2d | 725 | */ |
739fd940 | 726 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 SF |
727 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
728 | ERROR(rt2x00dev, "Failure padding beacon, aborting\n"); | |
729 | /* skb freed by skb_pad() on failure */ | |
730 | entry->skb = NULL; | |
731 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); | |
732 | return; | |
733 | } | |
734 | ||
f0194b2d | 735 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
736 | rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
737 | entry->skb->len + padding_len); | |
f0194b2d GW |
738 | |
739 | /* | |
740 | * Enable beaconing again. | |
741 | */ | |
f0194b2d GW |
742 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); |
743 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
744 | ||
745 | /* | |
746 | * Clean up beacon skb. | |
747 | */ | |
748 | dev_kfree_skb_any(entry->skb); | |
749 | entry->skb = NULL; | |
750 | } | |
50e888ea | 751 | EXPORT_SYMBOL_GPL(rt2800_write_beacon); |
f0194b2d | 752 | |
69cf36a4 HS |
753 | static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, |
754 | unsigned int beacon_base) | |
fdb87251 HS |
755 | { |
756 | int i; | |
757 | ||
758 | /* | |
759 | * For the Beacon base registers we only need to clear | |
760 | * the whole TXWI which (when set to 0) will invalidate | |
761 | * the entire beacon. | |
762 | */ | |
763 | for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32)) | |
764 | rt2800_register_write(rt2x00dev, beacon_base + i, 0); | |
765 | } | |
766 | ||
69cf36a4 HS |
767 | void rt2800_clear_beacon(struct queue_entry *entry) |
768 | { | |
769 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
770 | u32 reg; | |
771 | ||
772 | /* | |
773 | * Disable beaconing while we are reloading the beacon data, | |
774 | * otherwise we might be sending out invalid data. | |
775 | */ | |
776 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
777 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
778 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
779 | ||
780 | /* | |
781 | * Clear beacon. | |
782 | */ | |
783 | rt2800_clear_beacon_register(rt2x00dev, | |
784 | HW_BEACON_OFFSET(entry->entry_idx)); | |
785 | ||
786 | /* | |
787 | * Enabled beaconing again. | |
788 | */ | |
789 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); | |
790 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
791 | } | |
792 | EXPORT_SYMBOL_GPL(rt2800_clear_beacon); | |
793 | ||
f4450616 BZ |
794 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
795 | const struct rt2x00debug rt2800_rt2x00debug = { | |
796 | .owner = THIS_MODULE, | |
797 | .csr = { | |
798 | .read = rt2800_register_read, | |
799 | .write = rt2800_register_write, | |
800 | .flags = RT2X00DEBUGFS_OFFSET, | |
801 | .word_base = CSR_REG_BASE, | |
802 | .word_size = sizeof(u32), | |
803 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
804 | }, | |
805 | .eeprom = { | |
806 | .read = rt2x00_eeprom_read, | |
807 | .write = rt2x00_eeprom_write, | |
808 | .word_base = EEPROM_BASE, | |
809 | .word_size = sizeof(u16), | |
810 | .word_count = EEPROM_SIZE / sizeof(u16), | |
811 | }, | |
812 | .bbp = { | |
813 | .read = rt2800_bbp_read, | |
814 | .write = rt2800_bbp_write, | |
815 | .word_base = BBP_BASE, | |
816 | .word_size = sizeof(u8), | |
817 | .word_count = BBP_SIZE / sizeof(u8), | |
818 | }, | |
819 | .rf = { | |
820 | .read = rt2x00_rf_read, | |
821 | .write = rt2800_rf_write, | |
822 | .word_base = RF_BASE, | |
823 | .word_size = sizeof(u32), | |
824 | .word_count = RF_SIZE / sizeof(u32), | |
825 | }, | |
826 | }; | |
827 | EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); | |
828 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
829 | ||
830 | int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) | |
831 | { | |
832 | u32 reg; | |
833 | ||
834 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
835 | return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); | |
836 | } | |
837 | EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); | |
838 | ||
839 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
840 | static void rt2800_brightness_set(struct led_classdev *led_cdev, | |
841 | enum led_brightness brightness) | |
842 | { | |
843 | struct rt2x00_led *led = | |
844 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
845 | unsigned int enabled = brightness != LED_OFF; | |
846 | unsigned int bg_mode = | |
847 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
848 | unsigned int polarity = | |
849 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
850 | EEPROM_FREQ_LED_POLARITY); | |
851 | unsigned int ledmode = | |
852 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
853 | EEPROM_FREQ_LED_MODE); | |
44704e5d | 854 | u32 reg; |
f4450616 | 855 | |
44704e5d LE |
856 | /* Check for SoC (SOC devices don't support MCU requests) */ |
857 | if (rt2x00_is_soc(led->rt2x00dev)) { | |
858 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | |
859 | ||
860 | /* Set LED Polarity */ | |
861 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); | |
862 | ||
863 | /* Set LED Mode */ | |
864 | if (led->type == LED_TYPE_RADIO) { | |
865 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, | |
866 | enabled ? 3 : 0); | |
867 | } else if (led->type == LED_TYPE_ASSOC) { | |
868 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, | |
869 | enabled ? 3 : 0); | |
870 | } else if (led->type == LED_TYPE_QUALITY) { | |
871 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, | |
872 | enabled ? 3 : 0); | |
873 | } | |
874 | ||
875 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); | |
876 | ||
877 | } else { | |
878 | if (led->type == LED_TYPE_RADIO) { | |
879 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
880 | enabled ? 0x20 : 0); | |
881 | } else if (led->type == LED_TYPE_ASSOC) { | |
882 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
883 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); | |
884 | } else if (led->type == LED_TYPE_QUALITY) { | |
885 | /* | |
886 | * The brightness is divided into 6 levels (0 - 5), | |
887 | * The specs tell us the following levels: | |
888 | * 0, 1 ,3, 7, 15, 31 | |
889 | * to determine the level in a simple way we can simply | |
890 | * work with bitshifting: | |
891 | * (1 << level) - 1 | |
892 | */ | |
893 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
894 | (1 << brightness / (LED_FULL / 6)) - 1, | |
895 | polarity); | |
896 | } | |
f4450616 BZ |
897 | } |
898 | } | |
899 | ||
b3579d6a | 900 | static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, |
f4450616 BZ |
901 | struct rt2x00_led *led, enum led_type type) |
902 | { | |
903 | led->rt2x00dev = rt2x00dev; | |
904 | led->type = type; | |
905 | led->led_dev.brightness_set = rt2800_brightness_set; | |
f4450616 BZ |
906 | led->flags = LED_INITIALIZED; |
907 | } | |
f4450616 BZ |
908 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
909 | ||
910 | /* | |
911 | * Configuration handlers. | |
912 | */ | |
a2b1328a HS |
913 | static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, |
914 | const u8 *address, | |
915 | int wcid) | |
f4450616 BZ |
916 | { |
917 | struct mac_wcid_entry wcid_entry; | |
a2b1328a HS |
918 | u32 offset; |
919 | ||
920 | offset = MAC_WCID_ENTRY(wcid); | |
921 | ||
922 | memset(&wcid_entry, 0xff, sizeof(wcid_entry)); | |
923 | if (address) | |
924 | memcpy(wcid_entry.mac, address, ETH_ALEN); | |
925 | ||
926 | rt2800_register_multiwrite(rt2x00dev, offset, | |
927 | &wcid_entry, sizeof(wcid_entry)); | |
928 | } | |
929 | ||
930 | static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) | |
931 | { | |
932 | u32 offset; | |
933 | offset = MAC_WCID_ATTR_ENTRY(wcid); | |
934 | rt2800_register_write(rt2x00dev, offset, 0); | |
935 | } | |
936 | ||
937 | static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, | |
938 | int wcid, u32 bssidx) | |
939 | { | |
940 | u32 offset = MAC_WCID_ATTR_ENTRY(wcid); | |
941 | u32 reg; | |
942 | ||
943 | /* | |
944 | * The BSS Idx numbers is split in a main value of 3 bits, | |
945 | * and a extended field for adding one additional bit to the value. | |
946 | */ | |
947 | rt2800_register_read(rt2x00dev, offset, ®); | |
948 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); | |
949 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, | |
950 | (bssidx & 0x8) >> 3); | |
951 | rt2800_register_write(rt2x00dev, offset, reg); | |
952 | } | |
953 | ||
954 | static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, | |
955 | struct rt2x00lib_crypto *crypto, | |
956 | struct ieee80211_key_conf *key) | |
957 | { | |
f4450616 BZ |
958 | struct mac_iveiv_entry iveiv_entry; |
959 | u32 offset; | |
960 | u32 reg; | |
961 | ||
962 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); | |
963 | ||
e4a0ab34 ID |
964 | if (crypto->cmd == SET_KEY) { |
965 | rt2800_register_read(rt2x00dev, offset, ®); | |
966 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, | |
967 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); | |
968 | /* | |
969 | * Both the cipher as the BSS Idx numbers are split in a main | |
970 | * value of 3 bits, and a extended field for adding one additional | |
971 | * bit to the value. | |
972 | */ | |
973 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, | |
974 | (crypto->cipher & 0x7)); | |
975 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, | |
976 | (crypto->cipher & 0x8) >> 3); | |
e4a0ab34 ID |
977 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); |
978 | rt2800_register_write(rt2x00dev, offset, reg); | |
979 | } else { | |
a2b1328a HS |
980 | /* Delete the cipher without touching the bssidx */ |
981 | rt2800_register_read(rt2x00dev, offset, ®); | |
982 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); | |
983 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); | |
984 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); | |
985 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); | |
986 | rt2800_register_write(rt2x00dev, offset, reg); | |
e4a0ab34 | 987 | } |
f4450616 BZ |
988 | |
989 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); | |
990 | ||
991 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); | |
992 | if ((crypto->cipher == CIPHER_TKIP) || | |
993 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || | |
994 | (crypto->cipher == CIPHER_AES)) | |
995 | iveiv_entry.iv[3] |= 0x20; | |
996 | iveiv_entry.iv[3] |= key->keyidx << 6; | |
997 | rt2800_register_multiwrite(rt2x00dev, offset, | |
998 | &iveiv_entry, sizeof(iveiv_entry)); | |
f4450616 BZ |
999 | } |
1000 | ||
1001 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |
1002 | struct rt2x00lib_crypto *crypto, | |
1003 | struct ieee80211_key_conf *key) | |
1004 | { | |
1005 | struct hw_key_entry key_entry; | |
1006 | struct rt2x00_field32 field; | |
1007 | u32 offset; | |
1008 | u32 reg; | |
1009 | ||
1010 | if (crypto->cmd == SET_KEY) { | |
1011 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; | |
1012 | ||
1013 | memcpy(key_entry.key, crypto->key, | |
1014 | sizeof(key_entry.key)); | |
1015 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1016 | sizeof(key_entry.tx_mic)); | |
1017 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1018 | sizeof(key_entry.rx_mic)); | |
1019 | ||
1020 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); | |
1021 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1022 | &key_entry, sizeof(key_entry)); | |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * The cipher types are stored over multiple registers | |
1027 | * starting with SHARED_KEY_MODE_BASE each word will have | |
1028 | * 32 bits and contains the cipher types for 2 bssidx each. | |
1029 | * Using the correct defines correctly will cause overhead, | |
1030 | * so just calculate the correct offset. | |
1031 | */ | |
1032 | field.bit_offset = 4 * (key->hw_key_idx % 8); | |
1033 | field.bit_mask = 0x7 << field.bit_offset; | |
1034 | ||
1035 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); | |
1036 | ||
1037 | rt2800_register_read(rt2x00dev, offset, ®); | |
1038 | rt2x00_set_field32(®, field, | |
1039 | (crypto->cmd == SET_KEY) * crypto->cipher); | |
1040 | rt2800_register_write(rt2x00dev, offset, reg); | |
1041 | ||
1042 | /* | |
1043 | * Update WCID information | |
1044 | */ | |
a2b1328a HS |
1045 | rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); |
1046 | rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, | |
1047 | crypto->bssidx); | |
1048 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); | |
f4450616 BZ |
1049 | |
1050 | return 0; | |
1051 | } | |
1052 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); | |
1053 | ||
a2b1328a | 1054 | static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev) |
1ed3811c | 1055 | { |
a2b1328a | 1056 | struct mac_wcid_entry wcid_entry; |
1ed3811c | 1057 | int idx; |
a2b1328a | 1058 | u32 offset; |
1ed3811c HS |
1059 | |
1060 | /* | |
a2b1328a HS |
1061 | * Search for the first free WCID entry and return the corresponding |
1062 | * index. | |
1ed3811c HS |
1063 | * |
1064 | * Make sure the WCID starts _after_ the last possible shared key | |
1065 | * entry (>32). | |
1066 | * | |
1067 | * Since parts of the pairwise key table might be shared with | |
1068 | * the beacon frame buffers 6 & 7 we should only write into the | |
1069 | * first 222 entries. | |
1070 | */ | |
1071 | for (idx = 33; idx <= 222; idx++) { | |
a2b1328a HS |
1072 | offset = MAC_WCID_ENTRY(idx); |
1073 | rt2800_register_multiread(rt2x00dev, offset, &wcid_entry, | |
1074 | sizeof(wcid_entry)); | |
1075 | if (is_broadcast_ether_addr(wcid_entry.mac)) | |
1ed3811c HS |
1076 | return idx; |
1077 | } | |
a2b1328a HS |
1078 | |
1079 | /* | |
1080 | * Use -1 to indicate that we don't have any more space in the WCID | |
1081 | * table. | |
1082 | */ | |
1ed3811c HS |
1083 | return -1; |
1084 | } | |
1085 | ||
f4450616 BZ |
1086 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
1087 | struct rt2x00lib_crypto *crypto, | |
1088 | struct ieee80211_key_conf *key) | |
1089 | { | |
1090 | struct hw_key_entry key_entry; | |
1091 | u32 offset; | |
1092 | ||
1093 | if (crypto->cmd == SET_KEY) { | |
a2b1328a HS |
1094 | /* |
1095 | * Allow key configuration only for STAs that are | |
1096 | * known by the hw. | |
1097 | */ | |
1098 | if (crypto->wcid < 0) | |
f4450616 | 1099 | return -ENOSPC; |
a2b1328a | 1100 | key->hw_key_idx = crypto->wcid; |
f4450616 BZ |
1101 | |
1102 | memcpy(key_entry.key, crypto->key, | |
1103 | sizeof(key_entry.key)); | |
1104 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
1105 | sizeof(key_entry.tx_mic)); | |
1106 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
1107 | sizeof(key_entry.rx_mic)); | |
1108 | ||
1109 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
1110 | rt2800_register_multiwrite(rt2x00dev, offset, | |
1111 | &key_entry, sizeof(key_entry)); | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Update WCID information | |
1116 | */ | |
a2b1328a | 1117 | rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); |
f4450616 BZ |
1118 | |
1119 | return 0; | |
1120 | } | |
1121 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); | |
1122 | ||
a2b1328a HS |
1123 | int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, |
1124 | struct ieee80211_sta *sta) | |
1125 | { | |
1126 | int wcid; | |
1127 | struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); | |
1128 | ||
1129 | /* | |
1130 | * Find next free WCID. | |
1131 | */ | |
1132 | wcid = rt2800_find_wcid(rt2x00dev); | |
1133 | ||
1134 | /* | |
1135 | * Store selected wcid even if it is invalid so that we can | |
1136 | * later decide if the STA is uploaded into the hw. | |
1137 | */ | |
1138 | sta_priv->wcid = wcid; | |
1139 | ||
1140 | /* | |
1141 | * No space left in the device, however, we can still communicate | |
1142 | * with the STA -> No error. | |
1143 | */ | |
1144 | if (wcid < 0) | |
1145 | return 0; | |
1146 | ||
1147 | /* | |
1148 | * Clean up WCID attributes and write STA address to the device. | |
1149 | */ | |
1150 | rt2800_delete_wcid_attr(rt2x00dev, wcid); | |
1151 | rt2800_config_wcid(rt2x00dev, sta->addr, wcid); | |
1152 | rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, | |
1153 | rt2x00lib_get_bssidx(rt2x00dev, vif)); | |
1154 | return 0; | |
1155 | } | |
1156 | EXPORT_SYMBOL_GPL(rt2800_sta_add); | |
1157 | ||
1158 | int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) | |
1159 | { | |
1160 | /* | |
1161 | * Remove WCID entry, no need to clean the attributes as they will | |
1162 | * get renewed when the WCID is reused. | |
1163 | */ | |
1164 | rt2800_config_wcid(rt2x00dev, NULL, wcid); | |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | EXPORT_SYMBOL_GPL(rt2800_sta_remove); | |
1169 | ||
f4450616 BZ |
1170 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, |
1171 | const unsigned int filter_flags) | |
1172 | { | |
1173 | u32 reg; | |
1174 | ||
1175 | /* | |
1176 | * Start configuration steps. | |
1177 | * Note that the version error will always be dropped | |
1178 | * and broadcast frames will always be accepted since | |
1179 | * there is no filter for it at this time. | |
1180 | */ | |
1181 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); | |
1182 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, | |
1183 | !(filter_flags & FIF_FCSFAIL)); | |
1184 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, | |
1185 | !(filter_flags & FIF_PLCPFAIL)); | |
1186 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, | |
1187 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
1188 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); | |
1189 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); | |
1190 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, | |
1191 | !(filter_flags & FIF_ALLMULTI)); | |
1192 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); | |
1193 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); | |
1194 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, | |
1195 | !(filter_flags & FIF_CONTROL)); | |
1196 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, | |
1197 | !(filter_flags & FIF_CONTROL)); | |
1198 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, | |
1199 | !(filter_flags & FIF_CONTROL)); | |
1200 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, | |
1201 | !(filter_flags & FIF_CONTROL)); | |
1202 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, | |
1203 | !(filter_flags & FIF_CONTROL)); | |
1204 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, | |
1205 | !(filter_flags & FIF_PSPOLL)); | |
1206 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1); | |
1207 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0); | |
1208 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, | |
1209 | !(filter_flags & FIF_CONTROL)); | |
1210 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); | |
1211 | } | |
1212 | EXPORT_SYMBOL_GPL(rt2800_config_filter); | |
1213 | ||
1214 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, | |
1215 | struct rt2x00intf_conf *conf, const unsigned int flags) | |
1216 | { | |
f4450616 | 1217 | u32 reg; |
fa8b4b22 | 1218 | bool update_bssid = false; |
f4450616 BZ |
1219 | |
1220 | if (flags & CONFIG_UPDATE_TYPE) { | |
f4450616 BZ |
1221 | /* |
1222 | * Enable synchronisation. | |
1223 | */ | |
1224 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
f4450616 | 1225 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); |
f4450616 | 1226 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
15a533c4 HS |
1227 | |
1228 | if (conf->sync == TSF_SYNC_AP_NONE) { | |
1229 | /* | |
1230 | * Tune beacon queue transmit parameters for AP mode | |
1231 | */ | |
1232 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1233 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); | |
1234 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); | |
1235 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1236 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); | |
1237 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1238 | } else { | |
1239 | rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); | |
1240 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); | |
1241 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); | |
1242 | rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); | |
1243 | rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); | |
1244 | rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); | |
1245 | } | |
f4450616 BZ |
1246 | } |
1247 | ||
1248 | if (flags & CONFIG_UPDATE_MAC) { | |
fa8b4b22 HS |
1249 | if (flags & CONFIG_UPDATE_TYPE && |
1250 | conf->sync == TSF_SYNC_AP_NONE) { | |
1251 | /* | |
1252 | * The BSSID register has to be set to our own mac | |
1253 | * address in AP mode. | |
1254 | */ | |
1255 | memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); | |
1256 | update_bssid = true; | |
1257 | } | |
1258 | ||
c600c826 ID |
1259 | if (!is_zero_ether_addr((const u8 *)conf->mac)) { |
1260 | reg = le32_to_cpu(conf->mac[1]); | |
1261 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); | |
1262 | conf->mac[1] = cpu_to_le32(reg); | |
1263 | } | |
f4450616 BZ |
1264 | |
1265 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, | |
1266 | conf->mac, sizeof(conf->mac)); | |
1267 | } | |
1268 | ||
fa8b4b22 | 1269 | if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { |
c600c826 ID |
1270 | if (!is_zero_ether_addr((const u8 *)conf->bssid)) { |
1271 | reg = le32_to_cpu(conf->bssid[1]); | |
1272 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); | |
1273 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7); | |
1274 | conf->bssid[1] = cpu_to_le32(reg); | |
1275 | } | |
f4450616 BZ |
1276 | |
1277 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, | |
1278 | conf->bssid, sizeof(conf->bssid)); | |
1279 | } | |
1280 | } | |
1281 | EXPORT_SYMBOL_GPL(rt2800_config_intf); | |
1282 | ||
87c1915d HS |
1283 | static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, |
1284 | struct rt2x00lib_erp *erp) | |
1285 | { | |
1286 | bool any_sta_nongf = !!(erp->ht_opmode & | |
1287 | IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); | |
1288 | u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; | |
1289 | u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; | |
1290 | u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; | |
1291 | u32 reg; | |
1292 | ||
1293 | /* default protection rate for HT20: OFDM 24M */ | |
1294 | mm20_rate = gf20_rate = 0x4004; | |
1295 | ||
1296 | /* default protection rate for HT40: duplicate OFDM 24M */ | |
1297 | mm40_rate = gf40_rate = 0x4084; | |
1298 | ||
1299 | switch (protection) { | |
1300 | case IEEE80211_HT_OP_MODE_PROTECTION_NONE: | |
1301 | /* | |
1302 | * All STAs in this BSS are HT20/40 but there might be | |
1303 | * STAs not supporting greenfield mode. | |
1304 | * => Disable protection for HT transmissions. | |
1305 | */ | |
1306 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; | |
1307 | ||
1308 | break; | |
1309 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
1310 | /* | |
1311 | * All STAs in this BSS are HT20 or HT20/40 but there | |
1312 | * might be STAs not supporting greenfield mode. | |
1313 | * => Protect all HT40 transmissions. | |
1314 | */ | |
1315 | mm20_mode = gf20_mode = 0; | |
1316 | mm40_mode = gf40_mode = 2; | |
1317 | ||
1318 | break; | |
1319 | case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: | |
1320 | /* | |
1321 | * Nonmember protection: | |
1322 | * According to 802.11n we _should_ protect all | |
1323 | * HT transmissions (but we don't have to). | |
1324 | * | |
1325 | * But if cts_protection is enabled we _shall_ protect | |
1326 | * all HT transmissions using a CCK rate. | |
1327 | * | |
1328 | * And if any station is non GF we _shall_ protect | |
1329 | * GF transmissions. | |
1330 | * | |
1331 | * We decide to protect everything | |
1332 | * -> fall through to mixed mode. | |
1333 | */ | |
1334 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
1335 | /* | |
1336 | * Legacy STAs are present | |
1337 | * => Protect all HT transmissions. | |
1338 | */ | |
1339 | mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2; | |
1340 | ||
1341 | /* | |
1342 | * If erp protection is needed we have to protect HT | |
1343 | * transmissions with CCK 11M long preamble. | |
1344 | */ | |
1345 | if (erp->cts_protection) { | |
1346 | /* don't duplicate RTS/CTS in CCK mode */ | |
1347 | mm20_rate = mm40_rate = 0x0003; | |
1348 | gf20_rate = gf40_rate = 0x0003; | |
1349 | } | |
1350 | break; | |
6403eab1 | 1351 | } |
87c1915d HS |
1352 | |
1353 | /* check for STAs not supporting greenfield mode */ | |
1354 | if (any_sta_nongf) | |
1355 | gf20_mode = gf40_mode = 2; | |
1356 | ||
1357 | /* Update HT protection config */ | |
1358 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
1359 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); | |
1360 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); | |
1361 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
1362 | ||
1363 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
1364 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); | |
1365 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); | |
1366 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
1367 | ||
1368 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
1369 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); | |
1370 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); | |
1371 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
1372 | ||
1373 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
1374 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); | |
1375 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); | |
1376 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
1377 | } | |
1378 | ||
02044643 HS |
1379 | void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, |
1380 | u32 changed) | |
f4450616 BZ |
1381 | { |
1382 | u32 reg; | |
1383 | ||
02044643 HS |
1384 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1385 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); | |
1386 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, | |
1387 | !!erp->short_preamble); | |
1388 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, | |
1389 | !!erp->short_preamble); | |
1390 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
1391 | } | |
f4450616 | 1392 | |
02044643 HS |
1393 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1394 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
1395 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, | |
1396 | erp->cts_protection ? 2 : 0); | |
1397 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
1398 | } | |
f4450616 | 1399 | |
02044643 HS |
1400 | if (changed & BSS_CHANGED_BASIC_RATES) { |
1401 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, | |
1402 | erp->basic_rates); | |
1403 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
1404 | } | |
f4450616 | 1405 | |
02044643 HS |
1406 | if (changed & BSS_CHANGED_ERP_SLOT) { |
1407 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
1408 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, | |
1409 | erp->slot_time); | |
1410 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
f4450616 | 1411 | |
02044643 HS |
1412 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
1413 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); | |
1414 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
1415 | } | |
f4450616 | 1416 | |
02044643 HS |
1417 | if (changed & BSS_CHANGED_BEACON_INT) { |
1418 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
1419 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, | |
1420 | erp->beacon_int * 16); | |
1421 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1422 | } | |
87c1915d HS |
1423 | |
1424 | if (changed & BSS_CHANGED_HT) | |
1425 | rt2800_config_ht_opmode(rt2x00dev, erp); | |
f4450616 BZ |
1426 | } |
1427 | EXPORT_SYMBOL_GPL(rt2800_config_erp); | |
1428 | ||
872834df GW |
1429 | static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) |
1430 | { | |
1431 | u32 reg; | |
1432 | u16 eeprom; | |
1433 | u8 led_ctrl, led_g_mode, led_r_mode; | |
1434 | ||
1435 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
1436 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { | |
1437 | rt2x00_set_field32(®, GPIO_SWITCH_0, 1); | |
1438 | rt2x00_set_field32(®, GPIO_SWITCH_1, 1); | |
1439 | } else { | |
1440 | rt2x00_set_field32(®, GPIO_SWITCH_0, 0); | |
1441 | rt2x00_set_field32(®, GPIO_SWITCH_1, 0); | |
1442 | } | |
1443 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
1444 | ||
1445 | rt2800_register_read(rt2x00dev, LED_CFG, ®); | |
1446 | led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; | |
1447 | led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; | |
1448 | if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || | |
1449 | led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { | |
1450 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1451 | led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); | |
1452 | if (led_ctrl == 0 || led_ctrl > 0x40) { | |
1453 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); | |
1454 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); | |
1455 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | |
1456 | } else { | |
1457 | rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, | |
1458 | (led_g_mode << 2) | led_r_mode, 1); | |
1459 | } | |
1460 | } | |
1461 | } | |
1462 | ||
d96aa640 RJH |
1463 | static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, |
1464 | enum antenna ant) | |
1465 | { | |
1466 | u32 reg; | |
1467 | u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; | |
1468 | u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; | |
1469 | ||
1470 | if (rt2x00_is_pci(rt2x00dev)) { | |
1471 | rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); | |
1472 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); | |
1473 | rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); | |
1474 | } else if (rt2x00_is_usb(rt2x00dev)) | |
1475 | rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, | |
1476 | eesk_pin, 0); | |
1477 | ||
1478 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
fe59147c | 1479 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0); |
d96aa640 RJH |
1480 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, gpio_bit3); |
1481 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | |
1482 | } | |
1483 | ||
f4450616 BZ |
1484 | void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) |
1485 | { | |
1486 | u8 r1; | |
1487 | u8 r3; | |
d96aa640 | 1488 | u16 eeprom; |
f4450616 BZ |
1489 | |
1490 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
1491 | rt2800_bbp_read(rt2x00dev, 3, &r3); | |
1492 | ||
872834df GW |
1493 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1494 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | |
1495 | rt2800_config_3572bt_ant(rt2x00dev); | |
1496 | ||
f4450616 BZ |
1497 | /* |
1498 | * Configure the TX antenna. | |
1499 | */ | |
d96aa640 | 1500 | switch (ant->tx_chain_num) { |
f4450616 BZ |
1501 | case 1: |
1502 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | |
f4450616 BZ |
1503 | break; |
1504 | case 2: | |
872834df GW |
1505 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1506 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | |
1507 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); | |
1508 | else | |
1509 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | |
f4450616 BZ |
1510 | break; |
1511 | case 3: | |
e22557f2 | 1512 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
f4450616 BZ |
1513 | break; |
1514 | } | |
1515 | ||
1516 | /* | |
1517 | * Configure the RX antenna. | |
1518 | */ | |
d96aa640 | 1519 | switch (ant->rx_chain_num) { |
f4450616 | 1520 | case 1: |
d96aa640 RJH |
1521 | if (rt2x00_rt(rt2x00dev, RT3070) || |
1522 | rt2x00_rt(rt2x00dev, RT3090) || | |
1523 | rt2x00_rt(rt2x00dev, RT3390)) { | |
1524 | rt2x00_eeprom_read(rt2x00dev, | |
1525 | EEPROM_NIC_CONF1, &eeprom); | |
1526 | if (rt2x00_get_field16(eeprom, | |
1527 | EEPROM_NIC_CONF1_ANT_DIVERSITY)) | |
1528 | rt2800_set_ant_diversity(rt2x00dev, | |
1529 | rt2x00dev->default_ant.rx); | |
1530 | } | |
f4450616 BZ |
1531 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
1532 | break; | |
1533 | case 2: | |
872834df GW |
1534 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1535 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | |
1536 | rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); | |
1537 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, | |
1538 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
1539 | rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); | |
1540 | } else { | |
1541 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | |
1542 | } | |
f4450616 BZ |
1543 | break; |
1544 | case 3: | |
1545 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); | |
1546 | break; | |
1547 | } | |
1548 | ||
1549 | rt2800_bbp_write(rt2x00dev, 3, r3); | |
1550 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
1551 | } | |
1552 | EXPORT_SYMBOL_GPL(rt2800_config_ant); | |
1553 | ||
1554 | static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, | |
1555 | struct rt2x00lib_conf *libconf) | |
1556 | { | |
1557 | u16 eeprom; | |
1558 | short lna_gain; | |
1559 | ||
1560 | if (libconf->rf.channel <= 14) { | |
1561 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
1562 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); | |
1563 | } else if (libconf->rf.channel <= 64) { | |
1564 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
1565 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); | |
1566 | } else if (libconf->rf.channel <= 128) { | |
1567 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
1568 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); | |
1569 | } else { | |
1570 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
1571 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); | |
1572 | } | |
1573 | ||
1574 | rt2x00dev->lna_gain = lna_gain; | |
1575 | } | |
1576 | ||
06855ef4 GW |
1577 | static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, |
1578 | struct ieee80211_conf *conf, | |
1579 | struct rf_channel *rf, | |
1580 | struct channel_info *info) | |
f4450616 BZ |
1581 | { |
1582 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1583 | ||
d96aa640 | 1584 | if (rt2x00dev->default_ant.tx_chain_num == 1) |
f4450616 BZ |
1585 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); |
1586 | ||
d96aa640 | 1587 | if (rt2x00dev->default_ant.rx_chain_num == 1) { |
f4450616 BZ |
1588 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); |
1589 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); | |
d96aa640 | 1590 | } else if (rt2x00dev->default_ant.rx_chain_num == 2) |
f4450616 BZ |
1591 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
1592 | ||
1593 | if (rf->channel > 14) { | |
1594 | /* | |
1595 | * When TX power is below 0, we should increase it by 7 to | |
25985edc | 1596 | * make it a positive value (Minimum value is -7). |
f4450616 BZ |
1597 | * However this means that values between 0 and 7 have |
1598 | * double meaning, and we should set a 7DBm boost flag. | |
1599 | */ | |
1600 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1601 | (info->default_power1 >= 0)); |
f4450616 | 1602 | |
8d1331b3 ID |
1603 | if (info->default_power1 < 0) |
1604 | info->default_power1 += 7; | |
f4450616 | 1605 | |
8d1331b3 | 1606 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); |
f4450616 BZ |
1607 | |
1608 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, | |
8d1331b3 | 1609 | (info->default_power2 >= 0)); |
f4450616 | 1610 | |
8d1331b3 ID |
1611 | if (info->default_power2 < 0) |
1612 | info->default_power2 += 7; | |
f4450616 | 1613 | |
8d1331b3 | 1614 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); |
f4450616 | 1615 | } else { |
8d1331b3 ID |
1616 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); |
1617 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); | |
f4450616 BZ |
1618 | } |
1619 | ||
1620 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); | |
1621 | ||
1622 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1623 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1624 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1625 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1626 | ||
1627 | udelay(200); | |
1628 | ||
1629 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1630 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1631 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
1632 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1633 | ||
1634 | udelay(200); | |
1635 | ||
1636 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
1637 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
1638 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
1639 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
1640 | } | |
1641 | ||
06855ef4 GW |
1642 | static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, |
1643 | struct ieee80211_conf *conf, | |
1644 | struct rf_channel *rf, | |
1645 | struct channel_info *info) | |
f4450616 BZ |
1646 | { |
1647 | u8 rfcsr; | |
1648 | ||
1649 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
41a26170 | 1650 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); |
f4450616 BZ |
1651 | |
1652 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
fab799c3 | 1653 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); |
f4450616 BZ |
1654 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); |
1655 | ||
1656 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
8d1331b3 | 1657 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); |
f4450616 BZ |
1658 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); |
1659 | ||
5a673964 | 1660 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); |
8d1331b3 | 1661 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); |
5a673964 HS |
1662 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); |
1663 | ||
f4450616 BZ |
1664 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
1665 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1666 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
1667 | ||
1668 | rt2800_rfcsr_write(rt2x00dev, 24, | |
1669 | rt2x00dev->calibration[conf_is_ht40(conf)]); | |
1670 | ||
71976907 | 1671 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); |
f4450616 | 1672 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); |
71976907 | 1673 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
f4450616 BZ |
1674 | } |
1675 | ||
872834df GW |
1676 | static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, |
1677 | struct ieee80211_conf *conf, | |
1678 | struct rf_channel *rf, | |
1679 | struct channel_info *info) | |
1680 | { | |
1681 | u8 rfcsr; | |
1682 | u32 reg; | |
1683 | ||
1684 | if (rf->channel <= 14) { | |
1685 | rt2800_bbp_write(rt2x00dev, 25, 0x15); | |
1686 | rt2800_bbp_write(rt2x00dev, 26, 0x85); | |
1687 | } else { | |
1688 | rt2800_bbp_write(rt2x00dev, 25, 0x09); | |
1689 | rt2800_bbp_write(rt2x00dev, 26, 0xff); | |
1690 | } | |
1691 | ||
1692 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
1693 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); | |
1694 | ||
1695 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
1696 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); | |
1697 | if (rf->channel <= 14) | |
1698 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); | |
1699 | else | |
1700 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); | |
1701 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
1702 | ||
1703 | rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); | |
1704 | if (rf->channel <= 14) | |
1705 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); | |
1706 | else | |
1707 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); | |
1708 | rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); | |
1709 | ||
1710 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
1711 | if (rf->channel <= 14) { | |
1712 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); | |
1713 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | |
1714 | (info->default_power1 & 0x3) | | |
1715 | ((info->default_power1 & 0xC) << 1)); | |
1716 | } else { | |
1717 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); | |
1718 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | |
1719 | (info->default_power1 & 0x3) | | |
1720 | ((info->default_power1 & 0xC) << 1)); | |
1721 | } | |
1722 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); | |
1723 | ||
1724 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); | |
1725 | if (rf->channel <= 14) { | |
1726 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); | |
1727 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | |
1728 | (info->default_power2 & 0x3) | | |
1729 | ((info->default_power2 & 0xC) << 1)); | |
1730 | } else { | |
1731 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); | |
1732 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | |
1733 | (info->default_power2 & 0x3) | | |
1734 | ((info->default_power2 & 0xC) << 1)); | |
1735 | } | |
1736 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); | |
1737 | ||
1738 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
1739 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
1740 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
1741 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
1742 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); | |
1743 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | |
1744 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | |
1745 | if (rf->channel <= 14) { | |
1746 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
1747 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
1748 | } | |
1749 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | |
1750 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | |
1751 | } else { | |
1752 | switch (rt2x00dev->default_ant.tx_chain_num) { | |
1753 | case 1: | |
1754 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
1755 | case 2: | |
1756 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | |
1757 | break; | |
1758 | } | |
1759 | ||
1760 | switch (rt2x00dev->default_ant.rx_chain_num) { | |
1761 | case 1: | |
1762 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
1763 | case 2: | |
1764 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | |
1765 | break; | |
1766 | } | |
1767 | } | |
1768 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
1769 | ||
1770 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | |
1771 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
1772 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
1773 | ||
1774 | rt2800_rfcsr_write(rt2x00dev, 24, | |
1775 | rt2x00dev->calibration[conf_is_ht40(conf)]); | |
1776 | rt2800_rfcsr_write(rt2x00dev, 31, | |
1777 | rt2x00dev->calibration[conf_is_ht40(conf)]); | |
1778 | ||
1779 | if (rf->channel <= 14) { | |
1780 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | |
1781 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | |
1782 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
1783 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | |
1784 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | |
1785 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | |
1786 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | |
1787 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | |
1788 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | |
1789 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | |
1790 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
1791 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
1792 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | |
1793 | } else { | |
1794 | rt2800_rfcsr_write(rt2x00dev, 7, 0x14); | |
1795 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | |
1796 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
1797 | rt2800_rfcsr_write(rt2x00dev, 11, 0x00); | |
1798 | rt2800_rfcsr_write(rt2x00dev, 15, 0x43); | |
1799 | rt2800_rfcsr_write(rt2x00dev, 16, 0x7a); | |
1800 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | |
1801 | if (rf->channel <= 64) { | |
1802 | rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); | |
1803 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); | |
1804 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | |
1805 | } else if (rf->channel <= 128) { | |
1806 | rt2800_rfcsr_write(rt2x00dev, 19, 0x74); | |
1807 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); | |
1808 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
1809 | } else { | |
1810 | rt2800_rfcsr_write(rt2x00dev, 19, 0x72); | |
1811 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); | |
1812 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
1813 | } | |
1814 | rt2800_rfcsr_write(rt2x00dev, 26, 0x87); | |
1815 | rt2800_rfcsr_write(rt2x00dev, 27, 0x01); | |
1816 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); | |
1817 | } | |
1818 | ||
1819 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
1820 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT7, 0); | |
1821 | if (rf->channel <= 14) | |
1822 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 1); | |
1823 | else | |
1824 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 0); | |
1825 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | |
1826 | ||
1827 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); | |
1828 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); | |
1829 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | |
1830 | } | |
60687ba7 RST |
1831 | |
1832 | #define RT5390_POWER_BOUND 0x27 | |
1833 | #define RT5390_FREQ_OFFSET_BOUND 0x5f | |
1834 | ||
1835 | static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, | |
adde5882 GJ |
1836 | struct ieee80211_conf *conf, |
1837 | struct rf_channel *rf, | |
1838 | struct channel_info *info) | |
1839 | { | |
1840 | u8 rfcsr; | |
adde5882 GJ |
1841 | |
1842 | rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); | |
1843 | rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); | |
1844 | rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); | |
1845 | rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); | |
1846 | rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); | |
1847 | ||
1848 | rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); | |
1849 | if (info->default_power1 > RT5390_POWER_BOUND) | |
1850 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND); | |
1851 | else | |
1852 | rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); | |
1853 | rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); | |
1854 | ||
1855 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | |
1856 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
1857 | rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); | |
1858 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | |
1859 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | |
1860 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
1861 | ||
1862 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
1863 | if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND) | |
1864 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, | |
1865 | RT5390_FREQ_OFFSET_BOUND); | |
1866 | else | |
1867 | rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset); | |
1868 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
1869 | ||
adde5882 GJ |
1870 | if (rf->channel <= 14) { |
1871 | int idx = rf->channel-1; | |
1872 | ||
fdbc7b0a | 1873 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
adde5882 GJ |
1874 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { |
1875 | /* r55/r59 value array of channel 1~14 */ | |
1876 | static const char r55_bt_rev[] = {0x83, 0x83, | |
1877 | 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, | |
1878 | 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; | |
1879 | static const char r59_bt_rev[] = {0x0e, 0x0e, | |
1880 | 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, | |
1881 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; | |
1882 | ||
1883 | rt2800_rfcsr_write(rt2x00dev, 55, | |
1884 | r55_bt_rev[idx]); | |
1885 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1886 | r59_bt_rev[idx]); | |
1887 | } else { | |
1888 | static const char r59_bt[] = {0x8b, 0x8b, 0x8b, | |
1889 | 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, | |
1890 | 0x88, 0x88, 0x86, 0x85, 0x84}; | |
1891 | ||
1892 | rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); | |
1893 | } | |
1894 | } else { | |
1895 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { | |
1896 | static const char r55_nonbt_rev[] = {0x23, 0x23, | |
1897 | 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, | |
1898 | 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; | |
1899 | static const char r59_nonbt_rev[] = {0x07, 0x07, | |
1900 | 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, | |
1901 | 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; | |
1902 | ||
1903 | rt2800_rfcsr_write(rt2x00dev, 55, | |
1904 | r55_nonbt_rev[idx]); | |
1905 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1906 | r59_nonbt_rev[idx]); | |
1907 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { | |
1908 | static const char r59_non_bt[] = {0x8f, 0x8f, | |
1909 | 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, | |
1910 | 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; | |
1911 | ||
1912 | rt2800_rfcsr_write(rt2x00dev, 59, | |
1913 | r59_non_bt[idx]); | |
1914 | } | |
1915 | } | |
1916 | } | |
1917 | ||
1918 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
1919 | rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); | |
1920 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); | |
1921 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1922 | ||
1923 | rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); | |
1924 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
1925 | rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); | |
60687ba7 RST |
1926 | } |
1927 | ||
f4450616 BZ |
1928 | static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, |
1929 | struct ieee80211_conf *conf, | |
1930 | struct rf_channel *rf, | |
1931 | struct channel_info *info) | |
1932 | { | |
1933 | u32 reg; | |
1934 | unsigned int tx_pin; | |
1935 | u8 bbp; | |
1936 | ||
46323e11 | 1937 | if (rf->channel <= 14) { |
8d1331b3 ID |
1938 | info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1); |
1939 | info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2); | |
46323e11 | 1940 | } else { |
8d1331b3 ID |
1941 | info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1); |
1942 | info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2); | |
46323e11 ID |
1943 | } |
1944 | ||
06855ef4 GW |
1945 | if (rt2x00_rf(rt2x00dev, RF2020) || |
1946 | rt2x00_rf(rt2x00dev, RF3020) || | |
1947 | rt2x00_rf(rt2x00dev, RF3021) || | |
46323e11 | 1948 | rt2x00_rf(rt2x00dev, RF3022) || |
f93bc9b3 | 1949 | rt2x00_rf(rt2x00dev, RF3320)) |
06855ef4 | 1950 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); |
872834df GW |
1951 | else if (rt2x00_rf(rt2x00dev, RF3052)) |
1952 | rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); | |
aca355b9 GW |
1953 | else if (rt2x00_rf(rt2x00dev, RF5370) || |
1954 | rt2x00_rf(rt2x00dev, RF5390)) | |
adde5882 | 1955 | rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); |
fa6f632f | 1956 | else |
06855ef4 | 1957 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); |
f4450616 BZ |
1958 | |
1959 | /* | |
1960 | * Change BBP settings | |
1961 | */ | |
1962 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
1963 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
1964 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
1965 | rt2800_bbp_write(rt2x00dev, 86, 0); | |
1966 | ||
1967 | if (rf->channel <= 14) { | |
adde5882 | 1968 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
7dab73b3 ID |
1969 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, |
1970 | &rt2x00dev->cap_flags)) { | |
adde5882 GJ |
1971 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
1972 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
1973 | } else { | |
1974 | rt2800_bbp_write(rt2x00dev, 82, 0x84); | |
1975 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
1976 | } | |
f4450616 BZ |
1977 | } |
1978 | } else { | |
872834df GW |
1979 | if (rt2x00_rt(rt2x00dev, RT3572)) |
1980 | rt2800_bbp_write(rt2x00dev, 82, 0x94); | |
1981 | else | |
1982 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | |
f4450616 | 1983 | |
7dab73b3 | 1984 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) |
f4450616 BZ |
1985 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
1986 | else | |
1987 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
1988 | } | |
1989 | ||
1990 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); | |
a21ee724 | 1991 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
1992 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); |
1993 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); | |
1994 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); | |
1995 | ||
872834df GW |
1996 | if (rt2x00_rt(rt2x00dev, RT3572)) |
1997 | rt2800_rfcsr_write(rt2x00dev, 8, 0); | |
1998 | ||
f4450616 BZ |
1999 | tx_pin = 0; |
2000 | ||
2001 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
d96aa640 | 2002 | if (rt2x00dev->default_ant.tx_chain_num == 2) { |
65f31b5e GW |
2003 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, |
2004 | rf->channel > 14); | |
2005 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, | |
2006 | rf->channel <= 14); | |
f4450616 BZ |
2007 | } |
2008 | ||
2009 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
d96aa640 | 2010 | if (rt2x00dev->default_ant.rx_chain_num == 2) { |
f4450616 BZ |
2011 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); |
2012 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); | |
2013 | } | |
2014 | ||
2015 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); | |
2016 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); | |
2017 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); | |
2018 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); | |
8f96e91f GW |
2019 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) |
2020 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); | |
2021 | else | |
2022 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, | |
2023 | rf->channel <= 14); | |
f4450616 BZ |
2024 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); |
2025 | ||
2026 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
2027 | ||
872834df GW |
2028 | if (rt2x00_rt(rt2x00dev, RT3572)) |
2029 | rt2800_rfcsr_write(rt2x00dev, 8, 0x80); | |
2030 | ||
f4450616 BZ |
2031 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
2032 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); | |
2033 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
2034 | ||
2035 | rt2800_bbp_read(rt2x00dev, 3, &bbp); | |
a21ee724 | 2036 | rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); |
f4450616 BZ |
2037 | rt2800_bbp_write(rt2x00dev, 3, bbp); |
2038 | ||
8d0c9b65 | 2039 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
f4450616 BZ |
2040 | if (conf_is_ht40(conf)) { |
2041 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); | |
2042 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
2043 | rt2800_bbp_write(rt2x00dev, 73, 0x16); | |
2044 | } else { | |
2045 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
2046 | rt2800_bbp_write(rt2x00dev, 70, 0x08); | |
2047 | rt2800_bbp_write(rt2x00dev, 73, 0x11); | |
2048 | } | |
2049 | } | |
2050 | ||
2051 | msleep(1); | |
977206d7 HS |
2052 | |
2053 | /* | |
2054 | * Clear channel statistic counters | |
2055 | */ | |
2056 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); | |
2057 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); | |
2058 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); | |
f4450616 BZ |
2059 | } |
2060 | ||
9e33a355 HS |
2061 | static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) |
2062 | { | |
2063 | u8 tssi_bounds[9]; | |
2064 | u8 current_tssi; | |
2065 | u16 eeprom; | |
2066 | u8 step; | |
2067 | int i; | |
2068 | ||
2069 | /* | |
2070 | * Read TSSI boundaries for temperature compensation from | |
2071 | * the EEPROM. | |
2072 | * | |
2073 | * Array idx 0 1 2 3 4 5 6 7 8 | |
2074 | * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 | |
2075 | * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 | |
2076 | */ | |
2077 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
2078 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); | |
2079 | tssi_bounds[0] = rt2x00_get_field16(eeprom, | |
2080 | EEPROM_TSSI_BOUND_BG1_MINUS4); | |
2081 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
2082 | EEPROM_TSSI_BOUND_BG1_MINUS3); | |
2083 | ||
2084 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); | |
2085 | tssi_bounds[2] = rt2x00_get_field16(eeprom, | |
2086 | EEPROM_TSSI_BOUND_BG2_MINUS2); | |
2087 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
2088 | EEPROM_TSSI_BOUND_BG2_MINUS1); | |
2089 | ||
2090 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); | |
2091 | tssi_bounds[4] = rt2x00_get_field16(eeprom, | |
2092 | EEPROM_TSSI_BOUND_BG3_REF); | |
2093 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
2094 | EEPROM_TSSI_BOUND_BG3_PLUS1); | |
2095 | ||
2096 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); | |
2097 | tssi_bounds[6] = rt2x00_get_field16(eeprom, | |
2098 | EEPROM_TSSI_BOUND_BG4_PLUS2); | |
2099 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
2100 | EEPROM_TSSI_BOUND_BG4_PLUS3); | |
2101 | ||
2102 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); | |
2103 | tssi_bounds[8] = rt2x00_get_field16(eeprom, | |
2104 | EEPROM_TSSI_BOUND_BG5_PLUS4); | |
2105 | ||
2106 | step = rt2x00_get_field16(eeprom, | |
2107 | EEPROM_TSSI_BOUND_BG5_AGC_STEP); | |
2108 | } else { | |
2109 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); | |
2110 | tssi_bounds[0] = rt2x00_get_field16(eeprom, | |
2111 | EEPROM_TSSI_BOUND_A1_MINUS4); | |
2112 | tssi_bounds[1] = rt2x00_get_field16(eeprom, | |
2113 | EEPROM_TSSI_BOUND_A1_MINUS3); | |
2114 | ||
2115 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); | |
2116 | tssi_bounds[2] = rt2x00_get_field16(eeprom, | |
2117 | EEPROM_TSSI_BOUND_A2_MINUS2); | |
2118 | tssi_bounds[3] = rt2x00_get_field16(eeprom, | |
2119 | EEPROM_TSSI_BOUND_A2_MINUS1); | |
2120 | ||
2121 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); | |
2122 | tssi_bounds[4] = rt2x00_get_field16(eeprom, | |
2123 | EEPROM_TSSI_BOUND_A3_REF); | |
2124 | tssi_bounds[5] = rt2x00_get_field16(eeprom, | |
2125 | EEPROM_TSSI_BOUND_A3_PLUS1); | |
2126 | ||
2127 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); | |
2128 | tssi_bounds[6] = rt2x00_get_field16(eeprom, | |
2129 | EEPROM_TSSI_BOUND_A4_PLUS2); | |
2130 | tssi_bounds[7] = rt2x00_get_field16(eeprom, | |
2131 | EEPROM_TSSI_BOUND_A4_PLUS3); | |
2132 | ||
2133 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); | |
2134 | tssi_bounds[8] = rt2x00_get_field16(eeprom, | |
2135 | EEPROM_TSSI_BOUND_A5_PLUS4); | |
2136 | ||
2137 | step = rt2x00_get_field16(eeprom, | |
2138 | EEPROM_TSSI_BOUND_A5_AGC_STEP); | |
2139 | } | |
2140 | ||
2141 | /* | |
2142 | * Check if temperature compensation is supported. | |
2143 | */ | |
2144 | if (tssi_bounds[4] == 0xff) | |
2145 | return 0; | |
2146 | ||
2147 | /* | |
2148 | * Read current TSSI (BBP 49). | |
2149 | */ | |
2150 | rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); | |
2151 | ||
2152 | /* | |
2153 | * Compare TSSI value (BBP49) with the compensation boundaries | |
2154 | * from the EEPROM and increase or decrease tx power. | |
2155 | */ | |
2156 | for (i = 0; i <= 3; i++) { | |
2157 | if (current_tssi > tssi_bounds[i]) | |
2158 | break; | |
2159 | } | |
2160 | ||
2161 | if (i == 4) { | |
2162 | for (i = 8; i >= 5; i--) { | |
2163 | if (current_tssi < tssi_bounds[i]) | |
2164 | break; | |
2165 | } | |
2166 | } | |
2167 | ||
2168 | return (i - 4) * step; | |
2169 | } | |
2170 | ||
e90c54b2 RJH |
2171 | static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, |
2172 | enum ieee80211_band band) | |
2173 | { | |
2174 | u16 eeprom; | |
2175 | u8 comp_en; | |
2176 | u8 comp_type; | |
75faae8b | 2177 | int comp_value = 0; |
e90c54b2 RJH |
2178 | |
2179 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); | |
2180 | ||
75faae8b HS |
2181 | /* |
2182 | * HT40 compensation not required. | |
2183 | */ | |
2184 | if (eeprom == 0xffff || | |
2185 | !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
e90c54b2 RJH |
2186 | return 0; |
2187 | ||
2188 | if (band == IEEE80211_BAND_2GHZ) { | |
2189 | comp_en = rt2x00_get_field16(eeprom, | |
2190 | EEPROM_TXPOWER_DELTA_ENABLE_2G); | |
2191 | if (comp_en) { | |
2192 | comp_type = rt2x00_get_field16(eeprom, | |
2193 | EEPROM_TXPOWER_DELTA_TYPE_2G); | |
2194 | comp_value = rt2x00_get_field16(eeprom, | |
2195 | EEPROM_TXPOWER_DELTA_VALUE_2G); | |
2196 | if (!comp_type) | |
2197 | comp_value = -comp_value; | |
2198 | } | |
2199 | } else { | |
2200 | comp_en = rt2x00_get_field16(eeprom, | |
2201 | EEPROM_TXPOWER_DELTA_ENABLE_5G); | |
2202 | if (comp_en) { | |
2203 | comp_type = rt2x00_get_field16(eeprom, | |
2204 | EEPROM_TXPOWER_DELTA_TYPE_5G); | |
2205 | comp_value = rt2x00_get_field16(eeprom, | |
2206 | EEPROM_TXPOWER_DELTA_VALUE_5G); | |
2207 | if (!comp_type) | |
2208 | comp_value = -comp_value; | |
2209 | } | |
2210 | } | |
2211 | ||
2212 | return comp_value; | |
2213 | } | |
2214 | ||
fa71a160 HS |
2215 | static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, |
2216 | enum ieee80211_band band, int power_level, | |
2217 | u8 txpower, int delta) | |
e90c54b2 RJH |
2218 | { |
2219 | u32 reg; | |
2220 | u16 eeprom; | |
2221 | u8 criterion; | |
2222 | u8 eirp_txpower; | |
2223 | u8 eirp_txpower_criterion; | |
2224 | u8 reg_limit; | |
e90c54b2 RJH |
2225 | |
2226 | if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b)) | |
2227 | return txpower; | |
2228 | ||
7dab73b3 | 2229 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) { |
e90c54b2 RJH |
2230 | /* |
2231 | * Check if eirp txpower exceed txpower_limit. | |
2232 | * We use OFDM 6M as criterion and its eirp txpower | |
2233 | * is stored at EEPROM_EIRP_MAX_TX_POWER. | |
2234 | * .11b data rate need add additional 4dbm | |
2235 | * when calculating eirp txpower. | |
2236 | */ | |
2237 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®); | |
2238 | criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS); | |
2239 | ||
2240 | rt2x00_eeprom_read(rt2x00dev, | |
2241 | EEPROM_EIRP_MAX_TX_POWER, &eeprom); | |
2242 | ||
2243 | if (band == IEEE80211_BAND_2GHZ) | |
2244 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
2245 | EEPROM_EIRP_MAX_TX_POWER_2GHZ); | |
2246 | else | |
2247 | eirp_txpower_criterion = rt2x00_get_field16(eeprom, | |
2248 | EEPROM_EIRP_MAX_TX_POWER_5GHZ); | |
2249 | ||
2250 | eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + | |
2af242e1 | 2251 | (is_rate_b ? 4 : 0) + delta; |
e90c54b2 RJH |
2252 | |
2253 | reg_limit = (eirp_txpower > power_level) ? | |
2254 | (eirp_txpower - power_level) : 0; | |
2255 | } else | |
2256 | reg_limit = 0; | |
2257 | ||
2af242e1 | 2258 | return txpower + delta - reg_limit; |
e90c54b2 RJH |
2259 | } |
2260 | ||
f4450616 | 2261 | static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, |
9e33a355 HS |
2262 | enum ieee80211_band band, |
2263 | int power_level) | |
f4450616 | 2264 | { |
5e846004 | 2265 | u8 txpower; |
5e846004 | 2266 | u16 eeprom; |
e90c54b2 | 2267 | int i, is_rate_b; |
f4450616 | 2268 | u32 reg; |
f4450616 | 2269 | u8 r1; |
5e846004 | 2270 | u32 offset; |
2af242e1 HS |
2271 | int delta; |
2272 | ||
2273 | /* | |
2274 | * Calculate HT40 compensation delta | |
2275 | */ | |
2276 | delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); | |
f4450616 | 2277 | |
9e33a355 HS |
2278 | /* |
2279 | * calculate temperature compensation delta | |
2280 | */ | |
2281 | delta += rt2800_get_gain_calibration_delta(rt2x00dev); | |
f4450616 | 2282 | |
5e846004 | 2283 | /* |
e90c54b2 | 2284 | * set to normal bbp tx power control mode: +/- 0dBm |
5e846004 | 2285 | */ |
f4450616 | 2286 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
e90c54b2 | 2287 | rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0); |
f4450616 | 2288 | rt2800_bbp_write(rt2x00dev, 1, r1); |
5e846004 HS |
2289 | offset = TX_PWR_CFG_0; |
2290 | ||
2291 | for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { | |
2292 | /* just to be safe */ | |
2293 | if (offset > TX_PWR_CFG_4) | |
2294 | break; | |
2295 | ||
2296 | rt2800_register_read(rt2x00dev, offset, ®); | |
2297 | ||
2298 | /* read the next four txpower values */ | |
2299 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i, | |
2300 | &eeprom); | |
2301 | ||
e90c54b2 RJH |
2302 | is_rate_b = i ? 0 : 1; |
2303 | /* | |
2304 | * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, | |
5e846004 | 2305 | * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, |
e90c54b2 RJH |
2306 | * TX_PWR_CFG_4: unknown |
2307 | */ | |
5e846004 HS |
2308 | txpower = rt2x00_get_field16(eeprom, |
2309 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 2310 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2311 | power_level, txpower, delta); |
e90c54b2 | 2312 | rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); |
5e846004 | 2313 | |
e90c54b2 RJH |
2314 | /* |
2315 | * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, | |
5e846004 | 2316 | * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, |
e90c54b2 RJH |
2317 | * TX_PWR_CFG_4: unknown |
2318 | */ | |
5e846004 HS |
2319 | txpower = rt2x00_get_field16(eeprom, |
2320 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 2321 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2322 | power_level, txpower, delta); |
e90c54b2 | 2323 | rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); |
5e846004 | 2324 | |
e90c54b2 RJH |
2325 | /* |
2326 | * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, | |
5e846004 | 2327 | * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, |
e90c54b2 RJH |
2328 | * TX_PWR_CFG_4: unknown |
2329 | */ | |
5e846004 HS |
2330 | txpower = rt2x00_get_field16(eeprom, |
2331 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 2332 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2333 | power_level, txpower, delta); |
e90c54b2 | 2334 | rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); |
5e846004 | 2335 | |
e90c54b2 RJH |
2336 | /* |
2337 | * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, | |
5e846004 | 2338 | * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, |
e90c54b2 RJH |
2339 | * TX_PWR_CFG_4: unknown |
2340 | */ | |
5e846004 HS |
2341 | txpower = rt2x00_get_field16(eeprom, |
2342 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 2343 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2344 | power_level, txpower, delta); |
e90c54b2 | 2345 | rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); |
5e846004 HS |
2346 | |
2347 | /* read the next four txpower values */ | |
2348 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1, | |
2349 | &eeprom); | |
2350 | ||
e90c54b2 RJH |
2351 | is_rate_b = 0; |
2352 | /* | |
2353 | * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, | |
5e846004 | 2354 | * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2355 | * TX_PWR_CFG_4: unknown |
2356 | */ | |
5e846004 HS |
2357 | txpower = rt2x00_get_field16(eeprom, |
2358 | EEPROM_TXPOWER_BYRATE_RATE0); | |
fa71a160 | 2359 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2360 | power_level, txpower, delta); |
e90c54b2 | 2361 | rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); |
5e846004 | 2362 | |
e90c54b2 RJH |
2363 | /* |
2364 | * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, | |
5e846004 | 2365 | * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2366 | * TX_PWR_CFG_4: unknown |
2367 | */ | |
5e846004 HS |
2368 | txpower = rt2x00_get_field16(eeprom, |
2369 | EEPROM_TXPOWER_BYRATE_RATE1); | |
fa71a160 | 2370 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2371 | power_level, txpower, delta); |
e90c54b2 | 2372 | rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); |
5e846004 | 2373 | |
e90c54b2 RJH |
2374 | /* |
2375 | * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, | |
5e846004 | 2376 | * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2377 | * TX_PWR_CFG_4: unknown |
2378 | */ | |
5e846004 HS |
2379 | txpower = rt2x00_get_field16(eeprom, |
2380 | EEPROM_TXPOWER_BYRATE_RATE2); | |
fa71a160 | 2381 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2382 | power_level, txpower, delta); |
e90c54b2 | 2383 | rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); |
5e846004 | 2384 | |
e90c54b2 RJH |
2385 | /* |
2386 | * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, | |
5e846004 | 2387 | * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, |
e90c54b2 RJH |
2388 | * TX_PWR_CFG_4: unknown |
2389 | */ | |
5e846004 HS |
2390 | txpower = rt2x00_get_field16(eeprom, |
2391 | EEPROM_TXPOWER_BYRATE_RATE3); | |
fa71a160 | 2392 | txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, |
2af242e1 | 2393 | power_level, txpower, delta); |
e90c54b2 | 2394 | rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); |
5e846004 HS |
2395 | |
2396 | rt2800_register_write(rt2x00dev, offset, reg); | |
2397 | ||
2398 | /* next TX_PWR_CFG register */ | |
2399 | offset += 4; | |
2400 | } | |
f4450616 BZ |
2401 | } |
2402 | ||
9e33a355 HS |
2403 | void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) |
2404 | { | |
2405 | rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band, | |
2406 | rt2x00dev->tx_power); | |
2407 | } | |
2408 | EXPORT_SYMBOL_GPL(rt2800_gain_calibration); | |
2409 | ||
f4450616 BZ |
2410 | static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
2411 | struct rt2x00lib_conf *libconf) | |
2412 | { | |
2413 | u32 reg; | |
2414 | ||
2415 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); | |
2416 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, | |
2417 | libconf->conf->short_frame_max_tx_count); | |
2418 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, | |
2419 | libconf->conf->long_frame_max_tx_count); | |
f4450616 BZ |
2420 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); |
2421 | } | |
2422 | ||
2423 | static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, | |
2424 | struct rt2x00lib_conf *libconf) | |
2425 | { | |
2426 | enum dev_state state = | |
2427 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
2428 | STATE_SLEEP : STATE_AWAKE; | |
2429 | u32 reg; | |
2430 | ||
2431 | if (state == STATE_SLEEP) { | |
2432 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); | |
2433 | ||
2434 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); | |
2435 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); | |
2436 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, | |
2437 | libconf->conf->listen_interval - 1); | |
2438 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); | |
2439 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
2440 | ||
2441 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
2442 | } else { | |
f4450616 BZ |
2443 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
2444 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); | |
2445 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); | |
2446 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); | |
2447 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
5731858d GW |
2448 | |
2449 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
f4450616 BZ |
2450 | } |
2451 | } | |
2452 | ||
2453 | void rt2800_config(struct rt2x00_dev *rt2x00dev, | |
2454 | struct rt2x00lib_conf *libconf, | |
2455 | const unsigned int flags) | |
2456 | { | |
2457 | /* Always recalculate LNA gain before changing configuration */ | |
2458 | rt2800_config_lna_gain(rt2x00dev, libconf); | |
2459 | ||
e90c54b2 | 2460 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { |
f4450616 BZ |
2461 | rt2800_config_channel(rt2x00dev, libconf->conf, |
2462 | &libconf->rf, &libconf->channel); | |
9e33a355 HS |
2463 | rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band, |
2464 | libconf->conf->power_level); | |
e90c54b2 | 2465 | } |
f4450616 | 2466 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
9e33a355 HS |
2467 | rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band, |
2468 | libconf->conf->power_level); | |
f4450616 BZ |
2469 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
2470 | rt2800_config_retry_limit(rt2x00dev, libconf); | |
2471 | if (flags & IEEE80211_CONF_CHANGE_PS) | |
2472 | rt2800_config_ps(rt2x00dev, libconf); | |
2473 | } | |
2474 | EXPORT_SYMBOL_GPL(rt2800_config); | |
2475 | ||
2476 | /* | |
2477 | * Link tuning | |
2478 | */ | |
2479 | void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
2480 | { | |
2481 | u32 reg; | |
2482 | ||
2483 | /* | |
2484 | * Update FCS error count from register. | |
2485 | */ | |
2486 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
2487 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); | |
2488 | } | |
2489 | EXPORT_SYMBOL_GPL(rt2800_link_stats); | |
2490 | ||
2491 | static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |
2492 | { | |
2493 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
d5385bfc | 2494 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 | 2495 | rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 2496 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 GJ |
2497 | rt2x00_rt(rt2x00dev, RT3390) || |
2498 | rt2x00_rt(rt2x00dev, RT5390)) | |
f4450616 BZ |
2499 | return 0x1c + (2 * rt2x00dev->lna_gain); |
2500 | else | |
2501 | return 0x2e + rt2x00dev->lna_gain; | |
2502 | } | |
2503 | ||
2504 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
2505 | return 0x32 + (rt2x00dev->lna_gain * 5) / 3; | |
2506 | else | |
2507 | return 0x3a + (rt2x00dev->lna_gain * 5) / 3; | |
2508 | } | |
2509 | ||
2510 | static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, | |
2511 | struct link_qual *qual, u8 vgc_level) | |
2512 | { | |
2513 | if (qual->vgc_level != vgc_level) { | |
2514 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); | |
2515 | qual->vgc_level = vgc_level; | |
2516 | qual->vgc_level_reg = vgc_level; | |
2517 | } | |
2518 | } | |
2519 | ||
2520 | void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
2521 | { | |
2522 | rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); | |
2523 | } | |
2524 | EXPORT_SYMBOL_GPL(rt2800_reset_tuner); | |
2525 | ||
2526 | void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, | |
2527 | const u32 count) | |
2528 | { | |
8d0c9b65 | 2529 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) |
f4450616 BZ |
2530 | return; |
2531 | ||
2532 | /* | |
2533 | * When RSSI is better then -80 increase VGC level with 0x10 | |
2534 | */ | |
2535 | rt2800_set_vgc(rt2x00dev, qual, | |
2536 | rt2800_get_default_vgc(rt2x00dev) + | |
2537 | ((qual->rssi > -80) * 0x10)); | |
2538 | } | |
2539 | EXPORT_SYMBOL_GPL(rt2800_link_tuner); | |
fcf51541 BZ |
2540 | |
2541 | /* | |
2542 | * Initialization functions. | |
2543 | */ | |
b9a07ae9 | 2544 | static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
2545 | { |
2546 | u32 reg; | |
d5385bfc | 2547 | u16 eeprom; |
fcf51541 | 2548 | unsigned int i; |
e3a896b9 | 2549 | int ret; |
fcf51541 | 2550 | |
a9dce149 GW |
2551 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
2552 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
2553 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
2554 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
2555 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
2556 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
2557 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
2558 | ||
e3a896b9 GW |
2559 | ret = rt2800_drv_init_registers(rt2x00dev); |
2560 | if (ret) | |
2561 | return ret; | |
fcf51541 BZ |
2562 | |
2563 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); | |
2564 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ | |
2565 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ | |
2566 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ | |
2567 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ | |
2568 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); | |
2569 | ||
2570 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); | |
2571 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ | |
2572 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ | |
2573 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ | |
2574 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ | |
2575 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); | |
2576 | ||
2577 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); | |
2578 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
2579 | ||
2580 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); | |
2581 | ||
2582 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
8544df32 | 2583 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); |
fcf51541 BZ |
2584 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); |
2585 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); | |
2586 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); | |
2587 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
2588 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); | |
2589 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
2590 | ||
a9dce149 GW |
2591 | rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); |
2592 | ||
2593 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
2594 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); | |
2595 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); | |
2596 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
2597 | ||
64522957 | 2598 | if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 GW |
2599 | rt2x00_rt(rt2x00dev, RT3090) || |
2600 | rt2x00_rt(rt2x00dev, RT3390)) { | |
fcf51541 BZ |
2601 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
2602 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
64522957 | 2603 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 GW |
2604 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
2605 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
38c8a566 RJH |
2606 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
2607 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) | |
d5385bfc GW |
2608 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, |
2609 | 0x0000002c); | |
2610 | else | |
2611 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, | |
2612 | 0x0000000f); | |
2613 | } else { | |
2614 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
2615 | } | |
d5385bfc | 2616 | } else if (rt2x00_rt(rt2x00dev, RT3070)) { |
fcf51541 | 2617 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
8cdd15e0 GW |
2618 | |
2619 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
2620 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
2621 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); | |
2622 | } else { | |
2623 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2624 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
2625 | } | |
c295a81d HS |
2626 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
2627 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
2628 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
961636ba | 2629 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); |
872834df GW |
2630 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { |
2631 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
2632 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
adde5882 GJ |
2633 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
2634 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); | |
2635 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2636 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
fcf51541 BZ |
2637 | } else { |
2638 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); | |
2639 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
2640 | } | |
2641 | ||
2642 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); | |
2643 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); | |
2644 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); | |
2645 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); | |
2646 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); | |
2647 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); | |
2648 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); | |
2649 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); | |
2650 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); | |
2651 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); | |
2652 | ||
2653 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); | |
2654 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); | |
a9dce149 | 2655 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); |
fcf51541 BZ |
2656 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); |
2657 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); | |
2658 | ||
2659 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); | |
2660 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); | |
8d0c9b65 | 2661 | if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || |
49e721ec | 2662 | rt2x00_rt(rt2x00dev, RT2883) || |
8d0c9b65 | 2663 | rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) |
fcf51541 BZ |
2664 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); |
2665 | else | |
2666 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); | |
2667 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); | |
2668 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); | |
2669 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); | |
2670 | ||
a9dce149 GW |
2671 | rt2800_register_read(rt2x00dev, LED_CFG, ®); |
2672 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); | |
2673 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); | |
2674 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); | |
2675 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); | |
2676 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); | |
2677 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); | |
2678 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); | |
2679 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | |
2680 | ||
fcf51541 BZ |
2681 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); |
2682 | ||
a9dce149 GW |
2683 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); |
2684 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); | |
2685 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); | |
2686 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); | |
2687 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); | |
2688 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); | |
2689 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); | |
2690 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); | |
2691 | ||
fcf51541 BZ |
2692 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
2693 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); | |
a9dce149 | 2694 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); |
fcf51541 BZ |
2695 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); |
2696 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); | |
a9dce149 | 2697 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); |
fcf51541 BZ |
2698 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); |
2699 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); | |
2700 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
2701 | ||
2702 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
a9dce149 | 2703 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 2704 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2705 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2706 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2707 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2708 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 2709 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 2710 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
2711 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
2712 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
2713 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
2714 | ||
2715 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
a9dce149 | 2716 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); |
fcf51541 | 2717 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2718 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2719 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2720 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2721 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
a9dce149 | 2722 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
fcf51541 | 2723 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
a9dce149 GW |
2724 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
2725 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); | |
fcf51541 BZ |
2726 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
2727 | ||
2728 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
2729 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); | |
2730 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2731 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2732 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2733 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2734 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2735 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
2736 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2737 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 2738 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2739 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
2740 | ||
2741 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
2742 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); | |
d13a97f0 | 2743 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); |
6f492b6d | 2744 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2745 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2746 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2747 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2748 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
2749 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2750 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 2751 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2752 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
2753 | ||
2754 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
2755 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); | |
2756 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2757 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2758 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2759 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2760 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2761 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
2762 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2763 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
a9dce149 | 2764 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2765 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
2766 | ||
2767 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
2768 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); | |
2769 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); | |
6f492b6d | 2770 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); |
fcf51541 BZ |
2771 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
2772 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
2773 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
2774 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
2775 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
2776 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
a9dce149 | 2777 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); |
fcf51541 BZ |
2778 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
2779 | ||
cea90e55 | 2780 | if (rt2x00_is_usb(rt2x00dev)) { |
fcf51541 BZ |
2781 | rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); |
2782 | ||
2783 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
2784 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
2785 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
2786 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
2787 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
2788 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); | |
2789 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); | |
2790 | rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); | |
2791 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); | |
2792 | rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); | |
2793 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
2794 | } | |
2795 | ||
961621ab HS |
2796 | /* |
2797 | * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 | |
2798 | * although it is reserved. | |
2799 | */ | |
2800 | rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); | |
2801 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); | |
2802 | rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); | |
2803 | rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); | |
2804 | rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); | |
2805 | rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); | |
2806 | rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); | |
2807 | rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); | |
2808 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); | |
2809 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); | |
2810 | rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); | |
2811 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); | |
2812 | ||
fcf51541 BZ |
2813 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); |
2814 | ||
2815 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
2816 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); | |
2817 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, | |
2818 | IEEE80211_MAX_RTS_THRESHOLD); | |
2819 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); | |
2820 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
2821 | ||
2822 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); | |
a9dce149 | 2823 | |
a21c2ab4 HS |
2824 | /* |
2825 | * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS | |
2826 | * time should be set to 16. However, the original Ralink driver uses | |
2827 | * 16 for both and indeed using a value of 10 for CCK SIFS results in | |
2828 | * connection problems with 11g + CTS protection. Hence, use the same | |
2829 | * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. | |
2830 | */ | |
a9dce149 | 2831 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
a21c2ab4 HS |
2832 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); |
2833 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); | |
a9dce149 GW |
2834 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); |
2835 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); | |
2836 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); | |
2837 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
2838 | ||
fcf51541 BZ |
2839 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
2840 | ||
2841 | /* | |
2842 | * ASIC will keep garbage value after boot, clear encryption keys. | |
2843 | */ | |
2844 | for (i = 0; i < 4; i++) | |
2845 | rt2800_register_write(rt2x00dev, | |
2846 | SHARED_KEY_MODE_ENTRY(i), 0); | |
2847 | ||
2848 | for (i = 0; i < 256; i++) { | |
f4e16e41 | 2849 | static const u32 wcid[2] = { 0xffffffff, 0x00ffffff }; |
fcf51541 BZ |
2850 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), |
2851 | wcid, sizeof(wcid)); | |
2852 | ||
1ed3811c | 2853 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0); |
fcf51541 BZ |
2854 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
2855 | } | |
2856 | ||
2857 | /* | |
2858 | * Clear all beacons | |
fcf51541 | 2859 | */ |
69cf36a4 HS |
2860 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0); |
2861 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1); | |
2862 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2); | |
2863 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3); | |
2864 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4); | |
2865 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5); | |
2866 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6); | |
2867 | rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7); | |
fcf51541 | 2868 | |
cea90e55 | 2869 | if (rt2x00_is_usb(rt2x00dev)) { |
785c3c06 GW |
2870 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); |
2871 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); | |
2872 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
c6fcc0e5 RJH |
2873 | } else if (rt2x00_is_pcie(rt2x00dev)) { |
2874 | rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); | |
2875 | rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); | |
2876 | rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); | |
fcf51541 BZ |
2877 | } |
2878 | ||
2879 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); | |
2880 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); | |
2881 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); | |
2882 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); | |
2883 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); | |
2884 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); | |
2885 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); | |
2886 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); | |
2887 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); | |
2888 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); | |
2889 | ||
2890 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); | |
2891 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); | |
2892 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); | |
2893 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); | |
2894 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); | |
2895 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); | |
2896 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); | |
2897 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); | |
2898 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); | |
2899 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); | |
2900 | ||
2901 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); | |
2902 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); | |
2903 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); | |
2904 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); | |
2905 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); | |
2906 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); | |
2907 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); | |
2908 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); | |
2909 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); | |
2910 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); | |
2911 | ||
2912 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); | |
2913 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); | |
2914 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); | |
2915 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); | |
2916 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); | |
2917 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); | |
2918 | ||
47ee3eb1 HS |
2919 | /* |
2920 | * Do not force the BA window size, we use the TXWI to set it | |
2921 | */ | |
2922 | rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); | |
2923 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); | |
2924 | rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); | |
2925 | rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); | |
2926 | ||
fcf51541 BZ |
2927 | /* |
2928 | * We must clear the error counters. | |
2929 | * These registers are cleared on read, | |
2930 | * so we may pass a useless variable to store the value. | |
2931 | */ | |
2932 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
2933 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); | |
2934 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); | |
2935 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); | |
2936 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); | |
2937 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); | |
2938 | ||
9f926fb5 HS |
2939 | /* |
2940 | * Setup leadtime for pre tbtt interrupt to 6ms | |
2941 | */ | |
2942 | rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); | |
2943 | rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); | |
2944 | rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); | |
2945 | ||
977206d7 HS |
2946 | /* |
2947 | * Set up channel statistics timer | |
2948 | */ | |
2949 | rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); | |
2950 | rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); | |
2951 | rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); | |
2952 | rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); | |
2953 | rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); | |
2954 | rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); | |
2955 | rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); | |
2956 | ||
fcf51541 BZ |
2957 | return 0; |
2958 | } | |
fcf51541 BZ |
2959 | |
2960 | static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) | |
2961 | { | |
2962 | unsigned int i; | |
2963 | u32 reg; | |
2964 | ||
2965 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
2966 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); | |
2967 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) | |
2968 | return 0; | |
2969 | ||
2970 | udelay(REGISTER_BUSY_DELAY); | |
2971 | } | |
2972 | ||
2973 | ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); | |
2974 | return -EACCES; | |
2975 | } | |
2976 | ||
2977 | static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) | |
2978 | { | |
2979 | unsigned int i; | |
2980 | u8 value; | |
2981 | ||
2982 | /* | |
2983 | * BBP was enabled after firmware was loaded, | |
2984 | * but we need to reactivate it now. | |
2985 | */ | |
2986 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
2987 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
2988 | msleep(1); | |
2989 | ||
2990 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
2991 | rt2800_bbp_read(rt2x00dev, 0, &value); | |
2992 | if ((value != 0xff) && (value != 0x00)) | |
2993 | return 0; | |
2994 | udelay(REGISTER_BUSY_DELAY); | |
2995 | } | |
2996 | ||
2997 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
2998 | return -EACCES; | |
2999 | } | |
3000 | ||
b9a07ae9 | 3001 | static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
3002 | { |
3003 | unsigned int i; | |
3004 | u16 eeprom; | |
3005 | u8 reg_id; | |
3006 | u8 value; | |
3007 | ||
3008 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || | |
3009 | rt2800_wait_bbp_ready(rt2x00dev))) | |
3010 | return -EACCES; | |
3011 | ||
adde5882 GJ |
3012 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3013 | rt2800_bbp_read(rt2x00dev, 4, &value); | |
3014 | rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); | |
3015 | rt2800_bbp_write(rt2x00dev, 4, value); | |
3016 | } | |
60687ba7 | 3017 | |
adde5882 | 3018 | if (rt2800_is_305x_soc(rt2x00dev) || |
872834df | 3019 | rt2x00_rt(rt2x00dev, RT3572) || |
adde5882 | 3020 | rt2x00_rt(rt2x00dev, RT5390)) |
baff8006 HS |
3021 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
3022 | ||
fcf51541 BZ |
3023 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
3024 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
a9dce149 | 3025 | |
adde5882 GJ |
3026 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3027 | rt2800_bbp_write(rt2x00dev, 68, 0x0b); | |
60687ba7 | 3028 | |
a9dce149 GW |
3029 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { |
3030 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
3031 | rt2800_bbp_write(rt2x00dev, 73, 0x12); | |
adde5882 GJ |
3032 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
3033 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
3034 | rt2800_bbp_write(rt2x00dev, 73, 0x13); | |
3035 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
3036 | rt2800_bbp_write(rt2x00dev, 76, 0x28); | |
3037 | rt2800_bbp_write(rt2x00dev, 77, 0x59); | |
a9dce149 GW |
3038 | } else { |
3039 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
3040 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
3041 | } | |
3042 | ||
fcf51541 | 3043 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
8cdd15e0 | 3044 | |
d5385bfc | 3045 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 | 3046 | rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 3047 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 | 3048 | rt2x00_rt(rt2x00dev, RT3390) || |
872834df | 3049 | rt2x00_rt(rt2x00dev, RT3572) || |
adde5882 | 3050 | rt2x00_rt(rt2x00dev, RT5390)) { |
8cdd15e0 GW |
3051 | rt2800_bbp_write(rt2x00dev, 79, 0x13); |
3052 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | |
3053 | rt2800_bbp_write(rt2x00dev, 81, 0x33); | |
baff8006 HS |
3054 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
3055 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); | |
3056 | rt2800_bbp_write(rt2x00dev, 80, 0x08); | |
8cdd15e0 GW |
3057 | } else { |
3058 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
3059 | } | |
3060 | ||
fcf51541 | 3061 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
adde5882 GJ |
3062 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3063 | rt2800_bbp_write(rt2x00dev, 83, 0x7a); | |
3064 | else | |
3065 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
a9dce149 | 3066 | |
5ed8f458 | 3067 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) |
a9dce149 | 3068 | rt2800_bbp_write(rt2x00dev, 84, 0x19); |
adde5882 GJ |
3069 | else if (rt2x00_rt(rt2x00dev, RT5390)) |
3070 | rt2800_bbp_write(rt2x00dev, 84, 0x9a); | |
a9dce149 GW |
3071 | else |
3072 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
3073 | ||
adde5882 GJ |
3074 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3075 | rt2800_bbp_write(rt2x00dev, 86, 0x38); | |
3076 | else | |
3077 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
60687ba7 | 3078 | |
fcf51541 | 3079 | rt2800_bbp_write(rt2x00dev, 91, 0x04); |
60687ba7 | 3080 | |
adde5882 GJ |
3081 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3082 | rt2800_bbp_write(rt2x00dev, 92, 0x02); | |
3083 | else | |
3084 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
8cdd15e0 | 3085 | |
d5385bfc | 3086 | if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || |
64522957 | 3087 | rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 | 3088 | rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || |
baff8006 | 3089 | rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || |
872834df | 3090 | rt2x00_rt(rt2x00dev, RT3572) || |
adde5882 | 3091 | rt2x00_rt(rt2x00dev, RT5390) || |
baff8006 | 3092 | rt2800_is_305x_soc(rt2x00dev)) |
8cdd15e0 GW |
3093 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); |
3094 | else | |
3095 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
3096 | ||
adde5882 GJ |
3097 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3098 | rt2800_bbp_write(rt2x00dev, 104, 0x92); | |
60687ba7 | 3099 | |
baff8006 HS |
3100 | if (rt2800_is_305x_soc(rt2x00dev)) |
3101 | rt2800_bbp_write(rt2x00dev, 105, 0x01); | |
adde5882 GJ |
3102 | else if (rt2x00_rt(rt2x00dev, RT5390)) |
3103 | rt2800_bbp_write(rt2x00dev, 105, 0x3c); | |
baff8006 HS |
3104 | else |
3105 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
60687ba7 | 3106 | |
adde5882 GJ |
3107 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3108 | rt2800_bbp_write(rt2x00dev, 106, 0x03); | |
3109 | else | |
3110 | rt2800_bbp_write(rt2x00dev, 106, 0x35); | |
60687ba7 | 3111 | |
adde5882 GJ |
3112 | if (rt2x00_rt(rt2x00dev, RT5390)) |
3113 | rt2800_bbp_write(rt2x00dev, 128, 0x12); | |
fcf51541 | 3114 | |
64522957 | 3115 | if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 3116 | rt2x00_rt(rt2x00dev, RT3090) || |
adde5882 | 3117 | rt2x00_rt(rt2x00dev, RT3390) || |
872834df | 3118 | rt2x00_rt(rt2x00dev, RT3572) || |
adde5882 | 3119 | rt2x00_rt(rt2x00dev, RT5390)) { |
d5385bfc | 3120 | rt2800_bbp_read(rt2x00dev, 138, &value); |
fcf51541 | 3121 | |
38c8a566 RJH |
3122 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
3123 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) | |
d5385bfc | 3124 | value |= 0x20; |
38c8a566 | 3125 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) |
d5385bfc | 3126 | value &= ~0x02; |
fcf51541 | 3127 | |
d5385bfc | 3128 | rt2800_bbp_write(rt2x00dev, 138, value); |
fcf51541 BZ |
3129 | } |
3130 | ||
adde5882 GJ |
3131 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3132 | int ant, div_mode; | |
3133 | ||
3134 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); | |
3135 | div_mode = rt2x00_get_field16(eeprom, | |
3136 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
3137 | ant = (div_mode == 3) ? 1 : 0; | |
3138 | ||
3139 | /* check if this is a Bluetooth combo card */ | |
fdbc7b0a | 3140 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { |
adde5882 GJ |
3141 | u32 reg; |
3142 | ||
3143 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
3144 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0); | |
3145 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT6, 0); | |
3146 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 0); | |
3147 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 0); | |
3148 | if (ant == 0) | |
3149 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 1); | |
3150 | else if (ant == 1) | |
3151 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 1); | |
3152 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | |
3153 | } | |
3154 | ||
3155 | rt2800_bbp_read(rt2x00dev, 152, &value); | |
3156 | if (ant == 0) | |
3157 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); | |
3158 | else | |
3159 | rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); | |
3160 | rt2800_bbp_write(rt2x00dev, 152, value); | |
3161 | ||
3162 | /* Init frequency calibration */ | |
3163 | rt2800_bbp_write(rt2x00dev, 142, 1); | |
3164 | rt2800_bbp_write(rt2x00dev, 143, 57); | |
3165 | } | |
fcf51541 BZ |
3166 | |
3167 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { | |
3168 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
3169 | ||
3170 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
3171 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
3172 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
3173 | rt2800_bbp_write(rt2x00dev, reg_id, value); | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | return 0; | |
3178 | } | |
fcf51541 BZ |
3179 | |
3180 | static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, | |
3181 | bool bw40, u8 rfcsr24, u8 filter_target) | |
3182 | { | |
3183 | unsigned int i; | |
3184 | u8 bbp; | |
3185 | u8 rfcsr; | |
3186 | u8 passband; | |
3187 | u8 stopband; | |
3188 | u8 overtuned = 0; | |
3189 | ||
3190 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
3191 | ||
3192 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
3193 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); | |
3194 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
3195 | ||
80d184e6 RJH |
3196 | rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); |
3197 | rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); | |
3198 | rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); | |
3199 | ||
fcf51541 BZ |
3200 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
3201 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); | |
3202 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
3203 | ||
3204 | /* | |
3205 | * Set power & frequency of passband test tone | |
3206 | */ | |
3207 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
3208 | ||
3209 | for (i = 0; i < 100; i++) { | |
3210 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
3211 | msleep(1); | |
3212 | ||
3213 | rt2800_bbp_read(rt2x00dev, 55, &passband); | |
3214 | if (passband) | |
3215 | break; | |
3216 | } | |
3217 | ||
3218 | /* | |
3219 | * Set power & frequency of stopband test tone | |
3220 | */ | |
3221 | rt2800_bbp_write(rt2x00dev, 24, 0x06); | |
3222 | ||
3223 | for (i = 0; i < 100; i++) { | |
3224 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
3225 | msleep(1); | |
3226 | ||
3227 | rt2800_bbp_read(rt2x00dev, 55, &stopband); | |
3228 | ||
3229 | if ((passband - stopband) <= filter_target) { | |
3230 | rfcsr24++; | |
3231 | overtuned += ((passband - stopband) == filter_target); | |
3232 | } else | |
3233 | break; | |
3234 | ||
3235 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
3236 | } | |
3237 | ||
3238 | rfcsr24 -= !!overtuned; | |
3239 | ||
3240 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
3241 | return rfcsr24; | |
3242 | } | |
3243 | ||
b9a07ae9 | 3244 | static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
fcf51541 BZ |
3245 | { |
3246 | u8 rfcsr; | |
3247 | u8 bbp; | |
8cdd15e0 GW |
3248 | u32 reg; |
3249 | u16 eeprom; | |
fcf51541 | 3250 | |
d5385bfc | 3251 | if (!rt2x00_rt(rt2x00dev, RT3070) && |
64522957 | 3252 | !rt2x00_rt(rt2x00dev, RT3071) && |
cc78e904 | 3253 | !rt2x00_rt(rt2x00dev, RT3090) && |
23812383 | 3254 | !rt2x00_rt(rt2x00dev, RT3390) && |
872834df | 3255 | !rt2x00_rt(rt2x00dev, RT3572) && |
adde5882 | 3256 | !rt2x00_rt(rt2x00dev, RT5390) && |
baff8006 | 3257 | !rt2800_is_305x_soc(rt2x00dev)) |
fcf51541 BZ |
3258 | return 0; |
3259 | ||
fcf51541 BZ |
3260 | /* |
3261 | * Init RF calibration. | |
3262 | */ | |
adde5882 GJ |
3263 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3264 | rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); | |
3265 | rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); | |
3266 | rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); | |
3267 | msleep(1); | |
3268 | rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); | |
3269 | rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); | |
3270 | } else { | |
3271 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
3272 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
3273 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3274 | msleep(1); | |
3275 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | |
3276 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3277 | } | |
fcf51541 | 3278 | |
d5385bfc | 3279 | if (rt2x00_rt(rt2x00dev, RT3070) || |
64522957 GW |
3280 | rt2x00_rt(rt2x00dev, RT3071) || |
3281 | rt2x00_rt(rt2x00dev, RT3090)) { | |
fcf51541 BZ |
3282 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
3283 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
3284 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
80d184e6 | 3285 | rt2800_rfcsr_write(rt2x00dev, 7, 0x60); |
fcf51541 | 3286 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); |
8cdd15e0 | 3287 | rt2800_rfcsr_write(rt2x00dev, 10, 0x41); |
fcf51541 BZ |
3288 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
3289 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | |
3290 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
3291 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
3292 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
3293 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
3294 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
3295 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
3296 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
3297 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
3298 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
3299 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
fcf51541 | 3300 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); |
cc78e904 GW |
3301 | } else if (rt2x00_rt(rt2x00dev, RT3390)) { |
3302 | rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); | |
3303 | rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); | |
3304 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | |
3305 | rt2800_rfcsr_write(rt2x00dev, 3, 0x62); | |
fcf51541 | 3306 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
cc78e904 GW |
3307 | rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); |
3308 | rt2800_rfcsr_write(rt2x00dev, 6, 0x42); | |
3309 | rt2800_rfcsr_write(rt2x00dev, 7, 0x34); | |
3310 | rt2800_rfcsr_write(rt2x00dev, 8, 0x00); | |
3311 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | |
3312 | rt2800_rfcsr_write(rt2x00dev, 10, 0x61); | |
fcf51541 | 3313 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
cc78e904 GW |
3314 | rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); |
3315 | rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); | |
fcf51541 | 3316 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); |
cc78e904 GW |
3317 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); |
3318 | rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); | |
3319 | rt2800_rfcsr_write(rt2x00dev, 17, 0x94); | |
3320 | rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); | |
3321 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); | |
3322 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); | |
3323 | rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); | |
fcf51541 | 3324 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); |
cc78e904 | 3325 | rt2800_rfcsr_write(rt2x00dev, 23, 0x14); |
fcf51541 | 3326 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); |
cc78e904 GW |
3327 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); |
3328 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
3329 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
3330 | rt2800_rfcsr_write(rt2x00dev, 28, 0x41); | |
3331 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | |
3332 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | |
3333 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | |
872834df GW |
3334 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { |
3335 | rt2800_rfcsr_write(rt2x00dev, 0, 0x70); | |
3336 | rt2800_rfcsr_write(rt2x00dev, 1, 0x81); | |
3337 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | |
3338 | rt2800_rfcsr_write(rt2x00dev, 3, 0x02); | |
3339 | rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); | |
3340 | rt2800_rfcsr_write(rt2x00dev, 5, 0x05); | |
3341 | rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); | |
3342 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | |
3343 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | |
3344 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | |
3345 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | |
3346 | rt2800_rfcsr_write(rt2x00dev, 12, 0x70); | |
3347 | rt2800_rfcsr_write(rt2x00dev, 13, 0x65); | |
3348 | rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); | |
3349 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | |
3350 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | |
3351 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | |
3352 | rt2800_rfcsr_write(rt2x00dev, 18, 0xac); | |
3353 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | |
3354 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | |
3355 | rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); | |
3356 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
3357 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); | |
3358 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
3359 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | |
3360 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | |
3361 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | |
3362 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
3363 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | |
3364 | rt2800_rfcsr_write(rt2x00dev, 30, 0x09); | |
3365 | rt2800_rfcsr_write(rt2x00dev, 31, 0x10); | |
baff8006 | 3366 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
23812383 HS |
3367 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
3368 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | |
3369 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | |
3370 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | |
3371 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
3372 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
3373 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
3374 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | |
3375 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | |
3376 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
3377 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | |
3378 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
3379 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | |
3380 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | |
3381 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
3382 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
3383 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
3384 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
3385 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
3386 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
3387 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
3388 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
3389 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
3390 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | |
3391 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | |
3392 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
3393 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | |
3394 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | |
3395 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | |
3396 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | |
baff8006 HS |
3397 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); |
3398 | rt2800_rfcsr_write(rt2x00dev, 31, 0x00); | |
3399 | return 0; | |
adde5882 GJ |
3400 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
3401 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | |
3402 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | |
3403 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | |
3404 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | |
3405 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3406 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | |
3407 | else | |
3408 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | |
3409 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | |
3410 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | |
3411 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | |
3412 | rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); | |
3413 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | |
3414 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | |
3415 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | |
3416 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | |
3417 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | |
3418 | rt2800_rfcsr_write(rt2x00dev, 19, 0x00); | |
3419 | ||
3420 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | |
3421 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | |
3422 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | |
3423 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | |
3424 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | |
3425 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3426 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | |
3427 | else | |
3428 | rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); | |
3429 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | |
3430 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | |
3431 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | |
3432 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | |
3433 | ||
3434 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | |
3435 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | |
3436 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | |
3437 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | |
3438 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | |
3439 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | |
3440 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | |
3441 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | |
3442 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | |
3443 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | |
3444 | ||
3445 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3446 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | |
3447 | else | |
3448 | rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); | |
3449 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | |
3450 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); | |
3451 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); | |
3452 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | |
3453 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | |
3454 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3455 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | |
3456 | else | |
3457 | rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); | |
3458 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | |
3459 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | |
3460 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | |
3461 | ||
3462 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | |
3463 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3464 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | |
3465 | else | |
3466 | rt2800_rfcsr_write(rt2x00dev, 53, 0x84); | |
3467 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | |
3468 | rt2800_rfcsr_write(rt2x00dev, 55, 0x44); | |
3469 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | |
3470 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | |
3471 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | |
3472 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | |
3473 | ||
3474 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | |
3475 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | |
3476 | rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); | |
3477 | else | |
3478 | rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); | |
3479 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | |
3480 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | |
8cdd15e0 GW |
3481 | } |
3482 | ||
3483 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | |
3484 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
3485 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
3486 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
3487 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
64522957 GW |
3488 | } else if (rt2x00_rt(rt2x00dev, RT3071) || |
3489 | rt2x00_rt(rt2x00dev, RT3090)) { | |
80d184e6 RJH |
3490 | rt2800_rfcsr_write(rt2x00dev, 31, 0x14); |
3491 | ||
d5385bfc GW |
3492 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); |
3493 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | |
3494 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
3495 | ||
d5385bfc GW |
3496 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); |
3497 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
64522957 GW |
3498 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
3499 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { | |
38c8a566 RJH |
3500 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
3501 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) | |
d5385bfc GW |
3502 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); |
3503 | else | |
3504 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); | |
3505 | } | |
3506 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
80d184e6 RJH |
3507 | |
3508 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
3509 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
3510 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
cc78e904 GW |
3511 | } else if (rt2x00_rt(rt2x00dev, RT3390)) { |
3512 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | |
3513 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | |
3514 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | |
872834df GW |
3515 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { |
3516 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
3517 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | |
3518 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
3519 | ||
3520 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
3521 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | |
3522 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
3523 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
3524 | msleep(1); | |
3525 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | |
3526 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | |
3527 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | |
fcf51541 BZ |
3528 | } |
3529 | ||
3530 | /* | |
3531 | * Set RX Filter calibration for 20MHz and 40MHz | |
3532 | */ | |
8cdd15e0 GW |
3533 | if (rt2x00_rt(rt2x00dev, RT3070)) { |
3534 | rt2x00dev->calibration[0] = | |
3535 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); | |
3536 | rt2x00dev->calibration[1] = | |
3537 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); | |
64522957 | 3538 | } else if (rt2x00_rt(rt2x00dev, RT3071) || |
cc78e904 | 3539 | rt2x00_rt(rt2x00dev, RT3090) || |
872834df GW |
3540 | rt2x00_rt(rt2x00dev, RT3390) || |
3541 | rt2x00_rt(rt2x00dev, RT3572)) { | |
d5385bfc GW |
3542 | rt2x00dev->calibration[0] = |
3543 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); | |
3544 | rt2x00dev->calibration[1] = | |
3545 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); | |
8cdd15e0 | 3546 | } |
fcf51541 | 3547 | |
adde5882 GJ |
3548 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
3549 | /* | |
3550 | * Set back to initial state | |
3551 | */ | |
3552 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
fcf51541 | 3553 | |
adde5882 GJ |
3554 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
3555 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); | |
3556 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
fcf51541 | 3557 | |
adde5882 GJ |
3558 | /* |
3559 | * Set BBP back to BW20 | |
3560 | */ | |
3561 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
3562 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); | |
3563 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
3564 | } | |
fcf51541 | 3565 | |
d5385bfc | 3566 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || |
64522957 | 3567 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
cc78e904 GW |
3568 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
3569 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) | |
8cdd15e0 GW |
3570 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); |
3571 | ||
3572 | rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); | |
3573 | rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); | |
3574 | rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); | |
3575 | ||
adde5882 GJ |
3576 | if (!rt2x00_rt(rt2x00dev, RT5390)) { |
3577 | rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); | |
3578 | rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); | |
3579 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
3580 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | |
3581 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || | |
3582 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | |
7dab73b3 ID |
3583 | if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, |
3584 | &rt2x00dev->cap_flags)) | |
adde5882 GJ |
3585 | rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); |
3586 | } | |
3587 | rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); | |
3588 | if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) | |
3589 | rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, | |
3590 | rt2x00_get_field16(eeprom, | |
3591 | EEPROM_TXMIXER_GAIN_BG_VAL)); | |
3592 | rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); | |
3593 | } | |
8cdd15e0 | 3594 | |
64522957 GW |
3595 | if (rt2x00_rt(rt2x00dev, RT3090)) { |
3596 | rt2800_bbp_read(rt2x00dev, 138, &bbp); | |
3597 | ||
80d184e6 | 3598 | /* Turn off unused DAC1 and ADC1 to reduce power consumption */ |
38c8a566 RJH |
3599 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
3600 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) | |
64522957 | 3601 | rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); |
38c8a566 | 3602 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) |
64522957 GW |
3603 | rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); |
3604 | ||
3605 | rt2800_bbp_write(rt2x00dev, 138, bbp); | |
3606 | } | |
3607 | ||
3608 | if (rt2x00_rt(rt2x00dev, RT3071) || | |
cc78e904 GW |
3609 | rt2x00_rt(rt2x00dev, RT3090) || |
3610 | rt2x00_rt(rt2x00dev, RT3390)) { | |
d5385bfc GW |
3611 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); |
3612 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | |
3613 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | |
3614 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | |
3615 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | |
3616 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | |
3617 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | |
3618 | ||
3619 | rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); | |
3620 | rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); | |
3621 | rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); | |
3622 | ||
3623 | rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); | |
3624 | rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); | |
3625 | rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); | |
3626 | ||
3627 | rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); | |
3628 | rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); | |
3629 | rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); | |
3630 | } | |
3631 | ||
80d184e6 | 3632 | if (rt2x00_rt(rt2x00dev, RT3070)) { |
8cdd15e0 | 3633 | rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); |
80d184e6 | 3634 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) |
8cdd15e0 GW |
3635 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); |
3636 | else | |
3637 | rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); | |
3638 | rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); | |
3639 | rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); | |
3640 | rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); | |
3641 | rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); | |
3642 | } | |
3643 | ||
adde5882 GJ |
3644 | if (rt2x00_rt(rt2x00dev, RT5390)) { |
3645 | rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); | |
3646 | rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); | |
3647 | rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); | |
60687ba7 | 3648 | |
adde5882 GJ |
3649 | rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); |
3650 | rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); | |
3651 | rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); | |
60687ba7 | 3652 | |
adde5882 GJ |
3653 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); |
3654 | rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); | |
3655 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
3656 | } | |
60687ba7 | 3657 | |
fcf51541 BZ |
3658 | return 0; |
3659 | } | |
b9a07ae9 ID |
3660 | |
3661 | int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) | |
3662 | { | |
3663 | u32 reg; | |
3664 | u16 word; | |
3665 | ||
3666 | /* | |
3667 | * Initialize all registers. | |
3668 | */ | |
3669 | if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || | |
3670 | rt2800_init_registers(rt2x00dev) || | |
3671 | rt2800_init_bbp(rt2x00dev) || | |
3672 | rt2800_init_rfcsr(rt2x00dev))) | |
3673 | return -EIO; | |
3674 | ||
3675 | /* | |
3676 | * Send signal to firmware during boot time. | |
3677 | */ | |
3678 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); | |
3679 | ||
3680 | if (rt2x00_is_usb(rt2x00dev) && | |
3681 | (rt2x00_rt(rt2x00dev, RT3070) || | |
3682 | rt2x00_rt(rt2x00dev, RT3071) || | |
3683 | rt2x00_rt(rt2x00dev, RT3572))) { | |
3684 | udelay(200); | |
3685 | rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); | |
3686 | udelay(10); | |
3687 | } | |
3688 | ||
3689 | /* | |
3690 | * Enable RX. | |
3691 | */ | |
3692 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3693 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
3694 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
3695 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
3696 | ||
3697 | udelay(50); | |
3698 | ||
3699 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
3700 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); | |
3701 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); | |
3702 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); | |
3703 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); | |
3704 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
3705 | ||
3706 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3707 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); | |
3708 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); | |
3709 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
3710 | ||
3711 | /* | |
3712 | * Initialize LED control | |
3713 | */ | |
38c8a566 RJH |
3714 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); |
3715 | rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, | |
b9a07ae9 ID |
3716 | word & 0xff, (word >> 8) & 0xff); |
3717 | ||
38c8a566 RJH |
3718 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); |
3719 | rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, | |
b9a07ae9 ID |
3720 | word & 0xff, (word >> 8) & 0xff); |
3721 | ||
38c8a566 RJH |
3722 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); |
3723 | rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, | |
b9a07ae9 ID |
3724 | word & 0xff, (word >> 8) & 0xff); |
3725 | ||
3726 | return 0; | |
3727 | } | |
3728 | EXPORT_SYMBOL_GPL(rt2800_enable_radio); | |
3729 | ||
3730 | void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) | |
3731 | { | |
3732 | u32 reg; | |
3733 | ||
3734 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
3735 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
b9a07ae9 | 3736 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
b9a07ae9 ID |
3737 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
3738 | ||
3739 | /* Wait for DMA, ignore error */ | |
3740 | rt2800_wait_wpdma_ready(rt2x00dev); | |
3741 | ||
3742 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
3743 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); | |
3744 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); | |
3745 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
b9a07ae9 ID |
3746 | } |
3747 | EXPORT_SYMBOL_GPL(rt2800_disable_radio); | |
2ce33995 | 3748 | |
30e84034 BZ |
3749 | int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) |
3750 | { | |
3751 | u32 reg; | |
3752 | ||
3753 | rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®); | |
3754 | ||
3755 | return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); | |
3756 | } | |
3757 | EXPORT_SYMBOL_GPL(rt2800_efuse_detect); | |
3758 | ||
3759 | static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) | |
3760 | { | |
3761 | u32 reg; | |
3762 | ||
31a4cf1f GW |
3763 | mutex_lock(&rt2x00dev->csr_mutex); |
3764 | ||
3765 | rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®); | |
30e84034 BZ |
3766 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
3767 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); | |
3768 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); | |
31a4cf1f | 3769 | rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); |
30e84034 BZ |
3770 | |
3771 | /* Wait until the EEPROM has been loaded */ | |
3772 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); | |
3773 | ||
3774 | /* Apparently the data is read from end to start */ | |
31a4cf1f GW |
3775 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, |
3776 | (u32 *)&rt2x00dev->eeprom[i]); | |
3777 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, | |
3778 | (u32 *)&rt2x00dev->eeprom[i + 2]); | |
3779 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, | |
3780 | (u32 *)&rt2x00dev->eeprom[i + 4]); | |
3781 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, | |
3782 | (u32 *)&rt2x00dev->eeprom[i + 6]); | |
3783 | ||
3784 | mutex_unlock(&rt2x00dev->csr_mutex); | |
30e84034 BZ |
3785 | } |
3786 | ||
3787 | void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) | |
3788 | { | |
3789 | unsigned int i; | |
3790 | ||
3791 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) | |
3792 | rt2800_efuse_read(rt2x00dev, i); | |
3793 | } | |
3794 | EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); | |
3795 | ||
38bd7b8a BZ |
3796 | int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
3797 | { | |
3798 | u16 word; | |
3799 | u8 *mac; | |
3800 | u8 default_lna_gain; | |
3801 | ||
3802 | /* | |
3803 | * Start validation of the data that has been read. | |
3804 | */ | |
3805 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
3806 | if (!is_valid_ether_addr(mac)) { | |
3807 | random_ether_addr(mac); | |
3808 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); | |
3809 | } | |
3810 | ||
38c8a566 | 3811 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); |
38bd7b8a | 3812 | if (word == 0xffff) { |
38c8a566 RJH |
3813 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); |
3814 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); | |
3815 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); | |
3816 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); | |
38bd7b8a | 3817 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
49e721ec | 3818 | } else if (rt2x00_rt(rt2x00dev, RT2860) || |
e148b4c8 | 3819 | rt2x00_rt(rt2x00dev, RT2872)) { |
38bd7b8a BZ |
3820 | /* |
3821 | * There is a max of 2 RX streams for RT28x0 series | |
3822 | */ | |
38c8a566 RJH |
3823 | if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) |
3824 | rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); | |
3825 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); | |
38bd7b8a BZ |
3826 | } |
3827 | ||
38c8a566 | 3828 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); |
38bd7b8a | 3829 | if (word == 0xffff) { |
38c8a566 RJH |
3830 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); |
3831 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); | |
3832 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); | |
3833 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); | |
3834 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); | |
3835 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); | |
3836 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); | |
3837 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); | |
3838 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); | |
3839 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); | |
3840 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); | |
3841 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); | |
3842 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); | |
3843 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); | |
3844 | rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); | |
3845 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); | |
38bd7b8a BZ |
3846 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
3847 | } | |
3848 | ||
3849 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
3850 | if ((word & 0x00ff) == 0x00ff) { | |
3851 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
ec2d1791 GW |
3852 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
3853 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
3854 | } | |
3855 | if ((word & 0xff00) == 0xff00) { | |
38bd7b8a BZ |
3856 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, |
3857 | LED_MODE_TXRX_ACTIVITY); | |
3858 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); | |
3859 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
38c8a566 RJH |
3860 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); |
3861 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); | |
3862 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); | |
ec2d1791 | 3863 | EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word); |
38bd7b8a BZ |
3864 | } |
3865 | ||
3866 | /* | |
3867 | * During the LNA validation we are going to use | |
3868 | * lna0 as correct value. Note that EEPROM_LNA | |
3869 | * is never validated. | |
3870 | */ | |
3871 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); | |
3872 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); | |
3873 | ||
3874 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); | |
3875 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) | |
3876 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); | |
3877 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) | |
3878 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); | |
3879 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); | |
3880 | ||
3881 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); | |
3882 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) | |
3883 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); | |
3884 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || | |
3885 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) | |
3886 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, | |
3887 | default_lna_gain); | |
3888 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); | |
3889 | ||
3890 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); | |
3891 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) | |
3892 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); | |
3893 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) | |
3894 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); | |
3895 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); | |
3896 | ||
3897 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); | |
3898 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) | |
3899 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); | |
3900 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || | |
3901 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) | |
3902 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, | |
3903 | default_lna_gain); | |
3904 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); | |
3905 | ||
3906 | return 0; | |
3907 | } | |
3908 | EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); | |
3909 | ||
3910 | int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
3911 | { | |
3912 | u32 reg; | |
3913 | u16 value; | |
3914 | u16 eeprom; | |
3915 | ||
3916 | /* | |
3917 | * Read EEPROM word for configuration. | |
3918 | */ | |
38c8a566 | 3919 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
38bd7b8a BZ |
3920 | |
3921 | /* | |
adde5882 GJ |
3922 | * Identify RF chipset by EEPROM value |
3923 | * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field | |
3924 | * RT53xx: defined in "EEPROM_CHIP_ID" field | |
38bd7b8a | 3925 | */ |
38bd7b8a | 3926 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
adde5882 GJ |
3927 | if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390) |
3928 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); | |
3929 | else | |
3930 | value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); | |
38bd7b8a | 3931 | |
49e721ec GW |
3932 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
3933 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
3934 | ||
3935 | if (!rt2x00_rt(rt2x00dev, RT2860) && | |
49e721ec | 3936 | !rt2x00_rt(rt2x00dev, RT2872) && |
49e721ec | 3937 | !rt2x00_rt(rt2x00dev, RT2883) && |
49e721ec GW |
3938 | !rt2x00_rt(rt2x00dev, RT3070) && |
3939 | !rt2x00_rt(rt2x00dev, RT3071) && | |
3940 | !rt2x00_rt(rt2x00dev, RT3090) && | |
3941 | !rt2x00_rt(rt2x00dev, RT3390) && | |
adde5882 GJ |
3942 | !rt2x00_rt(rt2x00dev, RT3572) && |
3943 | !rt2x00_rt(rt2x00dev, RT5390)) { | |
49e721ec GW |
3944 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
3945 | return -ENODEV; | |
f273fe55 | 3946 | } |
714fa663 | 3947 | |
5122d898 GW |
3948 | if (!rt2x00_rf(rt2x00dev, RF2820) && |
3949 | !rt2x00_rf(rt2x00dev, RF2850) && | |
3950 | !rt2x00_rf(rt2x00dev, RF2720) && | |
3951 | !rt2x00_rf(rt2x00dev, RF2750) && | |
3952 | !rt2x00_rf(rt2x00dev, RF3020) && | |
3953 | !rt2x00_rf(rt2x00dev, RF2020) && | |
3954 | !rt2x00_rf(rt2x00dev, RF3021) && | |
6c0fe265 | 3955 | !rt2x00_rf(rt2x00dev, RF3022) && |
f93bc9b3 | 3956 | !rt2x00_rf(rt2x00dev, RF3052) && |
adde5882 | 3957 | !rt2x00_rf(rt2x00dev, RF3320) && |
aca355b9 | 3958 | !rt2x00_rf(rt2x00dev, RF5370) && |
adde5882 | 3959 | !rt2x00_rf(rt2x00dev, RF5390)) { |
38bd7b8a BZ |
3960 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
3961 | return -ENODEV; | |
3962 | } | |
3963 | ||
3964 | /* | |
3965 | * Identify default antenna configuration. | |
3966 | */ | |
d96aa640 | 3967 | rt2x00dev->default_ant.tx_chain_num = |
38c8a566 | 3968 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); |
d96aa640 | 3969 | rt2x00dev->default_ant.rx_chain_num = |
38c8a566 | 3970 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); |
38bd7b8a | 3971 | |
d96aa640 RJH |
3972 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); |
3973 | ||
3974 | if (rt2x00_rt(rt2x00dev, RT3070) || | |
3975 | rt2x00_rt(rt2x00dev, RT3090) || | |
3976 | rt2x00_rt(rt2x00dev, RT3390)) { | |
3977 | value = rt2x00_get_field16(eeprom, | |
3978 | EEPROM_NIC_CONF1_ANT_DIVERSITY); | |
3979 | switch (value) { | |
3980 | case 0: | |
3981 | case 1: | |
3982 | case 2: | |
3983 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3984 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
3985 | break; | |
3986 | case 3: | |
3987 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3988 | rt2x00dev->default_ant.rx = ANTENNA_B; | |
3989 | break; | |
3990 | } | |
3991 | } else { | |
3992 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
3993 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
3994 | } | |
3995 | ||
38bd7b8a | 3996 | /* |
9328fdac | 3997 | * Determine external LNA informations. |
38bd7b8a | 3998 | */ |
38c8a566 | 3999 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) |
7dab73b3 | 4000 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
38c8a566 | 4001 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) |
7dab73b3 | 4002 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); |
38bd7b8a BZ |
4003 | |
4004 | /* | |
4005 | * Detect if this device has an hardware controlled radio. | |
4006 | */ | |
38c8a566 | 4007 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) |
7dab73b3 | 4008 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
38bd7b8a | 4009 | |
fdbc7b0a GW |
4010 | /* |
4011 | * Detect if this device has Bluetooth co-existence. | |
4012 | */ | |
4013 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) | |
4014 | __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); | |
4015 | ||
9328fdac GW |
4016 | /* |
4017 | * Read frequency offset and RF programming sequence. | |
4018 | */ | |
4019 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
4020 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
4021 | ||
38bd7b8a BZ |
4022 | /* |
4023 | * Store led settings, for correct led behaviour. | |
4024 | */ | |
4025 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
4026 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); | |
4027 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
4028 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); | |
4029 | ||
9328fdac | 4030 | rt2x00dev->led_mcu_reg = eeprom; |
38bd7b8a BZ |
4031 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
4032 | ||
e90c54b2 RJH |
4033 | /* |
4034 | * Check if support EIRP tx power limit feature. | |
4035 | */ | |
4036 | rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); | |
4037 | ||
4038 | if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < | |
4039 | EIRP_MAX_TX_POWER_LIMIT) | |
7dab73b3 | 4040 | __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); |
e90c54b2 | 4041 | |
38bd7b8a BZ |
4042 | return 0; |
4043 | } | |
4044 | EXPORT_SYMBOL_GPL(rt2800_init_eeprom); | |
4045 | ||
4da2933f | 4046 | /* |
55f9321a | 4047 | * RF value list for rt28xx |
4da2933f BZ |
4048 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) |
4049 | */ | |
4050 | static const struct rf_channel rf_vals[] = { | |
4051 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, | |
4052 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, | |
4053 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, | |
4054 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, | |
4055 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, | |
4056 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, | |
4057 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, | |
4058 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, | |
4059 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, | |
4060 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, | |
4061 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, | |
4062 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, | |
4063 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, | |
4064 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, | |
4065 | ||
4066 | /* 802.11 UNI / HyperLan 2 */ | |
4067 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, | |
4068 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, | |
4069 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, | |
4070 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, | |
4071 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, | |
4072 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, | |
4073 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, | |
4074 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, | |
4075 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, | |
4076 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, | |
4077 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, | |
4078 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, | |
4079 | ||
4080 | /* 802.11 HyperLan 2 */ | |
4081 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, | |
4082 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, | |
4083 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, | |
4084 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, | |
4085 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, | |
4086 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, | |
4087 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, | |
4088 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, | |
4089 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, | |
4090 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, | |
4091 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, | |
4092 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, | |
4093 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, | |
4094 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, | |
4095 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, | |
4096 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, | |
4097 | ||
4098 | /* 802.11 UNII */ | |
4099 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, | |
4100 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, | |
4101 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, | |
4102 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, | |
4103 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, | |
4104 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, | |
4105 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, | |
4106 | { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, | |
4107 | { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, | |
4108 | { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, | |
4109 | { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, | |
4110 | ||
4111 | /* 802.11 Japan */ | |
4112 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, | |
4113 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, | |
4114 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, | |
4115 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, | |
4116 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, | |
4117 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, | |
4118 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, | |
4119 | }; | |
4120 | ||
4121 | /* | |
55f9321a ID |
4122 | * RF value list for rt3xxx |
4123 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052) | |
4da2933f | 4124 | */ |
55f9321a | 4125 | static const struct rf_channel rf_vals_3x[] = { |
4da2933f BZ |
4126 | {1, 241, 2, 2 }, |
4127 | {2, 241, 2, 7 }, | |
4128 | {3, 242, 2, 2 }, | |
4129 | {4, 242, 2, 7 }, | |
4130 | {5, 243, 2, 2 }, | |
4131 | {6, 243, 2, 7 }, | |
4132 | {7, 244, 2, 2 }, | |
4133 | {8, 244, 2, 7 }, | |
4134 | {9, 245, 2, 2 }, | |
4135 | {10, 245, 2, 7 }, | |
4136 | {11, 246, 2, 2 }, | |
4137 | {12, 246, 2, 7 }, | |
4138 | {13, 247, 2, 2 }, | |
4139 | {14, 248, 2, 4 }, | |
55f9321a ID |
4140 | |
4141 | /* 802.11 UNI / HyperLan 2 */ | |
4142 | {36, 0x56, 0, 4}, | |
4143 | {38, 0x56, 0, 6}, | |
4144 | {40, 0x56, 0, 8}, | |
4145 | {44, 0x57, 0, 0}, | |
4146 | {46, 0x57, 0, 2}, | |
4147 | {48, 0x57, 0, 4}, | |
4148 | {52, 0x57, 0, 8}, | |
4149 | {54, 0x57, 0, 10}, | |
4150 | {56, 0x58, 0, 0}, | |
4151 | {60, 0x58, 0, 4}, | |
4152 | {62, 0x58, 0, 6}, | |
4153 | {64, 0x58, 0, 8}, | |
4154 | ||
4155 | /* 802.11 HyperLan 2 */ | |
4156 | {100, 0x5b, 0, 8}, | |
4157 | {102, 0x5b, 0, 10}, | |
4158 | {104, 0x5c, 0, 0}, | |
4159 | {108, 0x5c, 0, 4}, | |
4160 | {110, 0x5c, 0, 6}, | |
4161 | {112, 0x5c, 0, 8}, | |
4162 | {116, 0x5d, 0, 0}, | |
4163 | {118, 0x5d, 0, 2}, | |
4164 | {120, 0x5d, 0, 4}, | |
4165 | {124, 0x5d, 0, 8}, | |
4166 | {126, 0x5d, 0, 10}, | |
4167 | {128, 0x5e, 0, 0}, | |
4168 | {132, 0x5e, 0, 4}, | |
4169 | {134, 0x5e, 0, 6}, | |
4170 | {136, 0x5e, 0, 8}, | |
4171 | {140, 0x5f, 0, 0}, | |
4172 | ||
4173 | /* 802.11 UNII */ | |
4174 | {149, 0x5f, 0, 9}, | |
4175 | {151, 0x5f, 0, 11}, | |
4176 | {153, 0x60, 0, 1}, | |
4177 | {157, 0x60, 0, 5}, | |
4178 | {159, 0x60, 0, 7}, | |
4179 | {161, 0x60, 0, 9}, | |
4180 | {165, 0x61, 0, 1}, | |
4181 | {167, 0x61, 0, 3}, | |
4182 | {169, 0x61, 0, 5}, | |
4183 | {171, 0x61, 0, 7}, | |
4184 | {173, 0x61, 0, 9}, | |
4da2933f BZ |
4185 | }; |
4186 | ||
4187 | int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |
4188 | { | |
4da2933f BZ |
4189 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
4190 | struct channel_info *info; | |
8d1331b3 ID |
4191 | char *default_power1; |
4192 | char *default_power2; | |
4da2933f BZ |
4193 | unsigned int i; |
4194 | u16 eeprom; | |
4195 | ||
93b6bd26 GW |
4196 | /* |
4197 | * Disable powersaving as default on PCI devices. | |
4198 | */ | |
cea90e55 | 4199 | if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) |
93b6bd26 GW |
4200 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
4201 | ||
4da2933f BZ |
4202 | /* |
4203 | * Initialize all hw fields. | |
4204 | */ | |
4205 | rt2x00dev->hw->flags = | |
4da2933f BZ |
4206 | IEEE80211_HW_SIGNAL_DBM | |
4207 | IEEE80211_HW_SUPPORTS_PS | | |
1df90809 HS |
4208 | IEEE80211_HW_PS_NULLFUNC_STACK | |
4209 | IEEE80211_HW_AMPDU_AGGREGATION; | |
5a5b6ed6 HS |
4210 | /* |
4211 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices | |
4212 | * unless we are capable of sending the buffered frames out after the | |
4213 | * DTIM transmission using rt2x00lib_beacondone. This will send out | |
4214 | * multicast and broadcast traffic immediately instead of buffering it | |
4215 | * infinitly and thus dropping it after some time. | |
4216 | */ | |
4217 | if (!rt2x00_is_usb(rt2x00dev)) | |
4218 | rt2x00dev->hw->flags |= | |
4219 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; | |
4da2933f | 4220 | |
4da2933f BZ |
4221 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
4222 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | |
4223 | rt2x00_eeprom_addr(rt2x00dev, | |
4224 | EEPROM_MAC_ADDR_0)); | |
4225 | ||
3f2bee24 HS |
4226 | /* |
4227 | * As rt2800 has a global fallback table we cannot specify | |
4228 | * more then one tx rate per frame but since the hw will | |
4229 | * try several rates (based on the fallback table) we should | |
ba3b9e5e | 4230 | * initialize max_report_rates to the maximum number of rates |
3f2bee24 HS |
4231 | * we are going to try. Otherwise mac80211 will truncate our |
4232 | * reported tx rates and the rc algortihm will end up with | |
4233 | * incorrect data. | |
4234 | */ | |
ba3b9e5e HS |
4235 | rt2x00dev->hw->max_rates = 1; |
4236 | rt2x00dev->hw->max_report_rates = 7; | |
3f2bee24 HS |
4237 | rt2x00dev->hw->max_rate_tries = 1; |
4238 | ||
38c8a566 | 4239 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); |
4da2933f BZ |
4240 | |
4241 | /* | |
4242 | * Initialize hw_mode information. | |
4243 | */ | |
4244 | spec->supported_bands = SUPPORT_BAND_2GHZ; | |
4245 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
4246 | ||
5122d898 | 4247 | if (rt2x00_rf(rt2x00dev, RF2820) || |
55f9321a | 4248 | rt2x00_rf(rt2x00dev, RF2720)) { |
4da2933f BZ |
4249 | spec->num_channels = 14; |
4250 | spec->channels = rf_vals; | |
55f9321a ID |
4251 | } else if (rt2x00_rf(rt2x00dev, RF2850) || |
4252 | rt2x00_rf(rt2x00dev, RF2750)) { | |
4da2933f BZ |
4253 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
4254 | spec->num_channels = ARRAY_SIZE(rf_vals); | |
4255 | spec->channels = rf_vals; | |
5122d898 GW |
4256 | } else if (rt2x00_rf(rt2x00dev, RF3020) || |
4257 | rt2x00_rf(rt2x00dev, RF2020) || | |
4258 | rt2x00_rf(rt2x00dev, RF3021) || | |
f93bc9b3 | 4259 | rt2x00_rf(rt2x00dev, RF3022) || |
adde5882 | 4260 | rt2x00_rf(rt2x00dev, RF3320) || |
aca355b9 | 4261 | rt2x00_rf(rt2x00dev, RF5370) || |
adde5882 | 4262 | rt2x00_rf(rt2x00dev, RF5390)) { |
55f9321a ID |
4263 | spec->num_channels = 14; |
4264 | spec->channels = rf_vals_3x; | |
4265 | } else if (rt2x00_rf(rt2x00dev, RF3052)) { | |
4266 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | |
4267 | spec->num_channels = ARRAY_SIZE(rf_vals_3x); | |
4268 | spec->channels = rf_vals_3x; | |
4da2933f BZ |
4269 | } |
4270 | ||
4271 | /* | |
4272 | * Initialize HT information. | |
4273 | */ | |
5122d898 | 4274 | if (!rt2x00_rf(rt2x00dev, RF2020)) |
38a522e6 GW |
4275 | spec->ht.ht_supported = true; |
4276 | else | |
4277 | spec->ht.ht_supported = false; | |
4278 | ||
4da2933f | 4279 | spec->ht.cap = |
06443e46 | 4280 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
4da2933f BZ |
4281 | IEEE80211_HT_CAP_GRN_FLD | |
4282 | IEEE80211_HT_CAP_SGI_20 | | |
aa674631 | 4283 | IEEE80211_HT_CAP_SGI_40; |
22cabaa6 | 4284 | |
38c8a566 | 4285 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2) |
22cabaa6 HS |
4286 | spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; |
4287 | ||
aa674631 | 4288 | spec->ht.cap |= |
38c8a566 | 4289 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) << |
aa674631 ID |
4290 | IEEE80211_HT_CAP_RX_STBC_SHIFT; |
4291 | ||
4da2933f BZ |
4292 | spec->ht.ampdu_factor = 3; |
4293 | spec->ht.ampdu_density = 4; | |
4294 | spec->ht.mcs.tx_params = | |
4295 | IEEE80211_HT_MCS_TX_DEFINED | | |
4296 | IEEE80211_HT_MCS_TX_RX_DIFF | | |
38c8a566 | 4297 | ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) << |
4da2933f BZ |
4298 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
4299 | ||
38c8a566 | 4300 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) { |
4da2933f BZ |
4301 | case 3: |
4302 | spec->ht.mcs.rx_mask[2] = 0xff; | |
4303 | case 2: | |
4304 | spec->ht.mcs.rx_mask[1] = 0xff; | |
4305 | case 1: | |
4306 | spec->ht.mcs.rx_mask[0] = 0xff; | |
4307 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ | |
4308 | break; | |
4309 | } | |
4310 | ||
4311 | /* | |
4312 | * Create channel information array | |
4313 | */ | |
baeb2ffa | 4314 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
4da2933f BZ |
4315 | if (!info) |
4316 | return -ENOMEM; | |
4317 | ||
4318 | spec->channels_info = info; | |
4319 | ||
8d1331b3 ID |
4320 | default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); |
4321 | default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); | |
4da2933f BZ |
4322 | |
4323 | for (i = 0; i < 14; i++) { | |
e90c54b2 RJH |
4324 | info[i].default_power1 = default_power1[i]; |
4325 | info[i].default_power2 = default_power2[i]; | |
4da2933f BZ |
4326 | } |
4327 | ||
4328 | if (spec->num_channels > 14) { | |
8d1331b3 ID |
4329 | default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); |
4330 | default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); | |
4da2933f BZ |
4331 | |
4332 | for (i = 14; i < spec->num_channels; i++) { | |
e90c54b2 RJH |
4333 | info[i].default_power1 = default_power1[i]; |
4334 | info[i].default_power2 = default_power2[i]; | |
4da2933f BZ |
4335 | } |
4336 | } | |
4337 | ||
4338 | return 0; | |
4339 | } | |
4340 | EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); | |
4341 | ||
2ce33995 BZ |
4342 | /* |
4343 | * IEEE80211 stack callback functions. | |
4344 | */ | |
e783619e HS |
4345 | void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32, |
4346 | u16 *iv16) | |
2ce33995 BZ |
4347 | { |
4348 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4349 | struct mac_iveiv_entry iveiv_entry; | |
4350 | u32 offset; | |
4351 | ||
4352 | offset = MAC_IVEIV_ENTRY(hw_key_idx); | |
4353 | rt2800_register_multiread(rt2x00dev, offset, | |
4354 | &iveiv_entry, sizeof(iveiv_entry)); | |
4355 | ||
855da5e0 JL |
4356 | memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); |
4357 | memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); | |
2ce33995 | 4358 | } |
e783619e | 4359 | EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq); |
2ce33995 | 4360 | |
e783619e | 4361 | int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
2ce33995 BZ |
4362 | { |
4363 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4364 | u32 reg; | |
4365 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); | |
4366 | ||
4367 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
4368 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); | |
4369 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
4370 | ||
4371 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
4372 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); | |
4373 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); | |
4374 | ||
4375 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
4376 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); | |
4377 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
4378 | ||
4379 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
4380 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); | |
4381 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
4382 | ||
4383 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
4384 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); | |
4385 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
4386 | ||
4387 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
4388 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); | |
4389 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
4390 | ||
4391 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
4392 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); | |
4393 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
4394 | ||
4395 | return 0; | |
4396 | } | |
e783619e | 4397 | EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); |
2ce33995 | 4398 | |
e783619e HS |
4399 | int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
4400 | const struct ieee80211_tx_queue_params *params) | |
2ce33995 BZ |
4401 | { |
4402 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4403 | struct data_queue *queue; | |
4404 | struct rt2x00_field32 field; | |
4405 | int retval; | |
4406 | u32 reg; | |
4407 | u32 offset; | |
4408 | ||
4409 | /* | |
4410 | * First pass the configuration through rt2x00lib, that will | |
4411 | * update the queue settings and validate the input. After that | |
4412 | * we are free to update the registers based on the value | |
4413 | * in the queue parameter. | |
4414 | */ | |
4415 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
4416 | if (retval) | |
4417 | return retval; | |
4418 | ||
4419 | /* | |
4420 | * We only need to perform additional register initialization | |
4421 | * for WMM queues/ | |
4422 | */ | |
4423 | if (queue_idx >= 4) | |
4424 | return 0; | |
4425 | ||
11f818e0 | 4426 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2ce33995 BZ |
4427 | |
4428 | /* Update WMM TXOP register */ | |
4429 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); | |
4430 | field.bit_offset = (queue_idx & 1) * 16; | |
4431 | field.bit_mask = 0xffff << field.bit_offset; | |
4432 | ||
4433 | rt2800_register_read(rt2x00dev, offset, ®); | |
4434 | rt2x00_set_field32(®, field, queue->txop); | |
4435 | rt2800_register_write(rt2x00dev, offset, reg); | |
4436 | ||
4437 | /* Update WMM registers */ | |
4438 | field.bit_offset = queue_idx * 4; | |
4439 | field.bit_mask = 0xf << field.bit_offset; | |
4440 | ||
4441 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); | |
4442 | rt2x00_set_field32(®, field, queue->aifs); | |
4443 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); | |
4444 | ||
4445 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); | |
4446 | rt2x00_set_field32(®, field, queue->cw_min); | |
4447 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); | |
4448 | ||
4449 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); | |
4450 | rt2x00_set_field32(®, field, queue->cw_max); | |
4451 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); | |
4452 | ||
4453 | /* Update EDCA registers */ | |
4454 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); | |
4455 | ||
4456 | rt2800_register_read(rt2x00dev, offset, ®); | |
4457 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); | |
4458 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); | |
4459 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); | |
4460 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); | |
4461 | rt2800_register_write(rt2x00dev, offset, reg); | |
4462 | ||
4463 | return 0; | |
4464 | } | |
e783619e | 4465 | EXPORT_SYMBOL_GPL(rt2800_conf_tx); |
2ce33995 | 4466 | |
e783619e | 4467 | u64 rt2800_get_tsf(struct ieee80211_hw *hw) |
2ce33995 BZ |
4468 | { |
4469 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4470 | u64 tsf; | |
4471 | u32 reg; | |
4472 | ||
4473 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); | |
4474 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; | |
4475 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); | |
4476 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); | |
4477 | ||
4478 | return tsf; | |
4479 | } | |
e783619e | 4480 | EXPORT_SYMBOL_GPL(rt2800_get_tsf); |
2ce33995 | 4481 | |
e783619e HS |
4482 | int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
4483 | enum ieee80211_ampdu_mlme_action action, | |
0b01f030 JB |
4484 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
4485 | u8 buf_size) | |
1df90809 | 4486 | { |
af35323d | 4487 | struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; |
1df90809 HS |
4488 | int ret = 0; |
4489 | ||
af35323d HS |
4490 | /* |
4491 | * Don't allow aggregation for stations the hardware isn't aware | |
4492 | * of because tx status reports for frames to an unknown station | |
4493 | * always contain wcid=255 and thus we can't distinguish between | |
4494 | * multiple stations which leads to unwanted situations when the | |
4495 | * hw reorders frames due to aggregation. | |
4496 | */ | |
4497 | if (sta_priv->wcid < 0) | |
4498 | return 1; | |
4499 | ||
1df90809 HS |
4500 | switch (action) { |
4501 | case IEEE80211_AMPDU_RX_START: | |
4502 | case IEEE80211_AMPDU_RX_STOP: | |
58ed826e HS |
4503 | /* |
4504 | * The hw itself takes care of setting up BlockAck mechanisms. | |
4505 | * So, we only have to allow mac80211 to nagotiate a BlockAck | |
4506 | * agreement. Once that is done, the hw will BlockAck incoming | |
4507 | * AMPDUs without further setup. | |
4508 | */ | |
1df90809 HS |
4509 | break; |
4510 | case IEEE80211_AMPDU_TX_START: | |
4511 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
4512 | break; | |
4513 | case IEEE80211_AMPDU_TX_STOP: | |
4514 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
4515 | break; | |
4516 | case IEEE80211_AMPDU_TX_OPERATIONAL: | |
4517 | break; | |
4518 | default: | |
4e9e58c6 | 4519 | WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n"); |
1df90809 HS |
4520 | } |
4521 | ||
4522 | return ret; | |
4523 | } | |
e783619e | 4524 | EXPORT_SYMBOL_GPL(rt2800_ampdu_action); |
a5ea2f02 | 4525 | |
977206d7 HS |
4526 | int rt2800_get_survey(struct ieee80211_hw *hw, int idx, |
4527 | struct survey_info *survey) | |
4528 | { | |
4529 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
4530 | struct ieee80211_conf *conf = &hw->conf; | |
4531 | u32 idle, busy, busy_ext; | |
4532 | ||
4533 | if (idx != 0) | |
4534 | return -ENOENT; | |
4535 | ||
4536 | survey->channel = conf->channel; | |
4537 | ||
4538 | rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); | |
4539 | rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); | |
4540 | rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); | |
4541 | ||
4542 | if (idle || busy) { | |
4543 | survey->filled = SURVEY_INFO_CHANNEL_TIME | | |
4544 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
4545 | SURVEY_INFO_CHANNEL_TIME_EXT_BUSY; | |
4546 | ||
4547 | survey->channel_time = (idle + busy) / 1000; | |
4548 | survey->channel_time_busy = busy / 1000; | |
4549 | survey->channel_time_ext_busy = busy_ext / 1000; | |
4550 | } | |
4551 | ||
4552 | return 0; | |
4553 | ||
4554 | } | |
4555 | EXPORT_SYMBOL_GPL(rt2800_get_survey); | |
4556 | ||
a5ea2f02 ID |
4557 | MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); |
4558 | MODULE_VERSION(DRV_VERSION); | |
4559 | MODULE_DESCRIPTION("Ralink RT2800 library"); | |
4560 | MODULE_LICENSE("GPL"); |