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rt2x00: restore original beaconing state
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
e5ef5bad 780 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
f0194b2d
GW		 950void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
951{
952 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
953 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
954 unsigned int beacon_base;
739fd940 955 unsigned int padding_len;
d76dfc61 956 u32 orig_reg, reg;
f0bda571 957 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 958
959 /*
960 * Disable beaconing while we are reloading the beacon data,
961 * otherwise we might be sending out invalid data.
962 */
963 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 964 orig_reg = reg;
f0194b2d
GW		 965 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
966 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
967
968 /*
969 * Add space for the TXWI in front of the skb.
970 */
f0bda571 971 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 972
973 /*
974 * Register descriptor details in skb frame descriptor.
975 */
976 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
977 skbdesc->desc = entry->skb->data;
f0bda571 978 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 979
980 /*
981 * Add the TXWI for the beacon to the skb.
982 */
0c5879bc 983 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 984
985 /*
986 * Dump beacon to userspace through debugfs.
987 */
988 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
989
990 /*
739fd940 991 * Write entire beacon with TXWI and padding to register.
f0194b2d 992 */
739fd940 993 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 994 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 995 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 996 /* skb freed by skb_pad() on failure */
997 entry->skb = NULL;
998 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
999 return;
1000 }
1001
21c6af6b
GJ		 1002 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1003
739fd940
WK		 1004 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1005 entry->skb->len + padding_len);
f0194b2d
GW		 1006
1007 /*
bc0df75a 1008 * Restore beaconing state.
f0194b2d 1009 */
bc0df75a 1010 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1011
1012 /*
1013 * Clean up beacon skb.
1014 */
1015 dev_kfree_skb_any(entry->skb);
1016 entry->skb = NULL;
1017}
50e888ea 1018EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1019
69cf36a4 1020static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1021 unsigned int index)
fdb87251
HS		 1022{
1023 int i;
0879f875 1024 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1025 unsigned int beacon_base;
1026
21c6af6b 1027 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1028
1029 /*
1030 * For the Beacon base registers we only need to clear
1031 * the whole TXWI which (when set to 0) will invalidate
1032 * the entire beacon.
1033 */
f0bda571 1034 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1035 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1036}
1037
69cf36a4
HS		 1038void rt2800_clear_beacon(struct queue_entry *entry)
1039{
1040 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1041 u32 orig_reg, reg;
69cf36a4
HS		 1042
1043 /*
1044 * Disable beaconing while we are reloading the beacon data,
1045 * otherwise we might be sending out invalid data.
1046 */
bc0df75a
SG		 1047 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1048 reg = orig_reg;
69cf36a4
HS		 1049 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1051
1052 /*
1053 * Clear beacon.
1054 */
77f7c0f3 1055 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
69cf36a4
HS		 1056
1057 /*
bc0df75a 1058 * Restore beaconing state.
69cf36a4 1059 */
bc0df75a 1060 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1061}
1062EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1063
f4450616
BZ		 1064#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1065const struct rt2x00debug rt2800_rt2x00debug = {
1066 .owner = THIS_MODULE,
1067 .csr = {
1068 .read = rt2800_register_read,
1069 .write = rt2800_register_write,
1070 .flags = RT2X00DEBUGFS_OFFSET,
1071 .word_base = CSR_REG_BASE,
1072 .word_size = sizeof(u32),
1073 .word_count = CSR_REG_SIZE / sizeof(u32),
1074 },
1075 .eeprom = {
3e38d3da
GJ		 1076 /* NOTE: The local EEPROM access functions can't
1077 * be used here, use the generic versions instead.
1078 */
f4450616
BZ		 1079 .read = rt2x00_eeprom_read,
1080 .write = rt2x00_eeprom_write,
1081 .word_base = EEPROM_BASE,
1082 .word_size = sizeof(u16),
1083 .word_count = EEPROM_SIZE / sizeof(u16),
1084 },
1085 .bbp = {
1086 .read = rt2800_bbp_read,
1087 .write = rt2800_bbp_write,
1088 .word_base = BBP_BASE,
1089 .word_size = sizeof(u8),
1090 .word_count = BBP_SIZE / sizeof(u8),
1091 },
1092 .rf = {
1093 .read = rt2x00_rf_read,
1094 .write = rt2800_rf_write,
1095 .word_base = RF_BASE,
1096 .word_size = sizeof(u32),
1097 .word_count = RF_SIZE / sizeof(u32),
1098 },
f2bd7f16
AA		 1099 .rfcsr = {
1100 .read = rt2800_rfcsr_read,
1101 .write = rt2800_rfcsr_write,
1102 .word_base = RFCSR_BASE,
1103 .word_size = sizeof(u8),
1104 .word_count = RFCSR_SIZE / sizeof(u8),
1105 },
f4450616
BZ		 1106};
1107EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1108#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1109
1110int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1111{
1112 u32 reg;
1113
a89534ed
WH		 1114 if (rt2x00_rt(rt2x00dev, RT3290)) {
1115 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1116 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1117 } else {
99bdf51a
GW		 1118 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1119 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1120 }
f4450616
BZ		 1121}
1122EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1123
1124#ifdef CONFIG_RT2X00_LIB_LEDS
1125static void rt2800_brightness_set(struct led_classdev *led_cdev,
1126 enum led_brightness brightness)
1127{
1128 struct rt2x00_led *led =
1129 container_of(led_cdev, struct rt2x00_led, led_dev);
1130 unsigned int enabled = brightness != LED_OFF;
1131 unsigned int bg_mode =
1132 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1133 unsigned int polarity =
1134 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1135 EEPROM_FREQ_LED_POLARITY);
1136 unsigned int ledmode =
1137 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1138 EEPROM_FREQ_LED_MODE);
44704e5d 1139 u32 reg;
f4450616 1140
44704e5d
LE		 1141 /* Check for SoC (SOC devices don't support MCU requests) */
1142 if (rt2x00_is_soc(led->rt2x00dev)) {
1143 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1144
1145 /* Set LED Polarity */
1146 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1147
1148 /* Set LED Mode */
1149 if (led->type == LED_TYPE_RADIO) {
1150 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1151 enabled ? 3 : 0);
1152 } else if (led->type == LED_TYPE_ASSOC) {
1153 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1154 enabled ? 3 : 0);
1155 } else if (led->type == LED_TYPE_QUALITY) {
1156 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1157 enabled ? 3 : 0);
1158 }
1159
1160 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1161
1162 } else {
1163 if (led->type == LED_TYPE_RADIO) {
1164 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1165 enabled ? 0x20 : 0);
1166 } else if (led->type == LED_TYPE_ASSOC) {
1167 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1168 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1169 } else if (led->type == LED_TYPE_QUALITY) {
1170 /*
1171 * The brightness is divided into 6 levels (0 - 5),
1172 * The specs tell us the following levels:
1173 * 0, 1 ,3, 7, 15, 31
1174 * to determine the level in a simple way we can simply
1175 * work with bitshifting:
1176 * (1 << level) - 1
1177 */
1178 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1179 (1 << brightness / (LED_FULL / 6)) - 1,
1180 polarity);
1181 }
f4450616
BZ		 1182 }
1183}
1184
b3579d6a 1185static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1186 struct rt2x00_led *led, enum led_type type)
1187{
1188 led->rt2x00dev = rt2x00dev;
1189 led->type = type;
1190 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1191 led->flags = LED_INITIALIZED;
1192}
f4450616
BZ		 1193#endif /* CONFIG_RT2X00_LIB_LEDS */
1194
1195/*
1196 * Configuration handlers.
1197 */
a2b1328a
HS		 1198static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1199 const u8 *address,
1200 int wcid)
f4450616
BZ		 1201{
1202 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1203 u32 offset;
1204
1205 offset = MAC_WCID_ENTRY(wcid);
1206
1207 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1208 if (address)
1209 memcpy(wcid_entry.mac, address, ETH_ALEN);
1210
1211 rt2800_register_multiwrite(rt2x00dev, offset,
1212 &wcid_entry, sizeof(wcid_entry));
1213}
1214
1215static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1216{
1217 u32 offset;
1218 offset = MAC_WCID_ATTR_ENTRY(wcid);
1219 rt2800_register_write(rt2x00dev, offset, 0);
1220}
1221
1222static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1223 int wcid, u32 bssidx)
1224{
1225 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1226 u32 reg;
1227
1228 /*
1229 * The BSS Idx numbers is split in a main value of 3 bits,
1230 * and a extended field for adding one additional bit to the value.
1231 */
1232 rt2800_register_read(rt2x00dev, offset, &reg);
1233 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1234 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1235 (bssidx & 0x8) >> 3);
1236 rt2800_register_write(rt2x00dev, offset, reg);
1237}
1238
1239static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1240 struct rt2x00lib_crypto *crypto,
1241 struct ieee80211_key_conf *key)
1242{
f4450616
BZ		 1243 struct mac_iveiv_entry iveiv_entry;
1244 u32 offset;
1245 u32 reg;
1246
1247 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1248
e4a0ab34
ID		 1249 if (crypto->cmd == SET_KEY) {
1250 rt2800_register_read(rt2x00dev, offset, &reg);
1251 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1252 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1253 /*
1254 * Both the cipher as the BSS Idx numbers are split in a main
1255 * value of 3 bits, and a extended field for adding one additional
1256 * bit to the value.
1257 */
1258 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1259 (crypto->cipher & 0x7));
1260 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1261 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1262 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1263 rt2800_register_write(rt2x00dev, offset, reg);
1264 } else {
a2b1328a
HS		 1265 /* Delete the cipher without touching the bssidx */
1266 rt2800_register_read(rt2x00dev, offset, &reg);
1267 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1268 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1269 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1270 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1271 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1272 }
f4450616
BZ		 1273
1274 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1275
1276 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1277 if ((crypto->cipher == CIPHER_TKIP) ||
1278 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1279 (crypto->cipher == CIPHER_AES))
1280 iveiv_entry.iv[3] |= 0x20;
1281 iveiv_entry.iv[3] |= key->keyidx << 6;
1282 rt2800_register_multiwrite(rt2x00dev, offset,
1283 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1284}
1285
1286int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1287 struct rt2x00lib_crypto *crypto,
1288 struct ieee80211_key_conf *key)
1289{
1290 struct hw_key_entry key_entry;
1291 struct rt2x00_field32 field;
1292 u32 offset;
1293 u32 reg;
1294
1295 if (crypto->cmd == SET_KEY) {
1296 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1297
1298 memcpy(key_entry.key, crypto->key,
1299 sizeof(key_entry.key));
1300 memcpy(key_entry.tx_mic, crypto->tx_mic,
1301 sizeof(key_entry.tx_mic));
1302 memcpy(key_entry.rx_mic, crypto->rx_mic,
1303 sizeof(key_entry.rx_mic));
1304
1305 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1306 rt2800_register_multiwrite(rt2x00dev, offset,
1307 &key_entry, sizeof(key_entry));
1308 }
1309
1310 /*
1311 * The cipher types are stored over multiple registers
1312 * starting with SHARED_KEY_MODE_BASE each word will have
1313 * 32 bits and contains the cipher types for 2 bssidx each.
1314 * Using the correct defines correctly will cause overhead,
1315 * so just calculate the correct offset.
1316 */
1317 field.bit_offset = 4 * (key->hw_key_idx % 8);
1318 field.bit_mask = 0x7 << field.bit_offset;
1319
1320 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1321
1322 rt2800_register_read(rt2x00dev, offset, &reg);
1323 rt2x00_set_field32(&reg, field,
1324 (crypto->cmd == SET_KEY) * crypto->cipher);
1325 rt2800_register_write(rt2x00dev, offset, reg);
1326
1327 /*
1328 * Update WCID information
1329 */
a2b1328a
HS		 1330 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1331 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1332 crypto->bssidx);
1333 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1334
1335 return 0;
1336}
1337EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1338
a2b1328a 1339static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1340{
a2b1328a 1341 struct mac_wcid_entry wcid_entry;
1ed3811c 1342 int idx;
a2b1328a 1343 u32 offset;
1ed3811c
HS		 1344
1345 /*
a2b1328a
HS		 1346 * Search for the first free WCID entry and return the corresponding
1347 * index.
1ed3811c
HS		 1348 *
1349 * Make sure the WCID starts _after_ the last possible shared key
1350 * entry (>32).
1351 *
1352 * Since parts of the pairwise key table might be shared with
1353 * the beacon frame buffers 6 & 7 we should only write into the
1354 * first 222 entries.
1355 */
1356 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1357 offset = MAC_WCID_ENTRY(idx);
1358 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1359 sizeof(wcid_entry));
1360 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1361 return idx;
1362 }
a2b1328a
HS		 1363
1364 /*
1365 * Use -1 to indicate that we don't have any more space in the WCID
1366 * table.
1367 */
1ed3811c
HS		 1368 return -1;
1369}
1370
f4450616
BZ		 1371int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1372 struct rt2x00lib_crypto *crypto,
1373 struct ieee80211_key_conf *key)
1374{
1375 struct hw_key_entry key_entry;
1376 u32 offset;
1377
1378 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1379 /*
1380 * Allow key configuration only for STAs that are
1381 * known by the hw.
1382 */
1383 if (crypto->wcid < 0)
f4450616 1384 return -ENOSPC;
a2b1328a 1385 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1386
1387 memcpy(key_entry.key, crypto->key,
1388 sizeof(key_entry.key));
1389 memcpy(key_entry.tx_mic, crypto->tx_mic,
1390 sizeof(key_entry.tx_mic));
1391 memcpy(key_entry.rx_mic, crypto->rx_mic,
1392 sizeof(key_entry.rx_mic));
1393
1394 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1395 rt2800_register_multiwrite(rt2x00dev, offset,
1396 &key_entry, sizeof(key_entry));
1397 }
1398
1399 /*
1400 * Update WCID information
1401 */
a2b1328a 1402 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1403
1404 return 0;
1405}
1406EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1407
a2b1328a
HS		 1408int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1409 struct ieee80211_sta *sta)
1410{
1411 int wcid;
1412 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1413
1414 /*
1415 * Find next free WCID.
1416 */
1417 wcid = rt2800_find_wcid(rt2x00dev);
1418
1419 /*
1420 * Store selected wcid even if it is invalid so that we can
1421 * later decide if the STA is uploaded into the hw.
1422 */
1423 sta_priv->wcid = wcid;
1424
1425 /*
1426 * No space left in the device, however, we can still communicate
1427 * with the STA -> No error.
1428 */
1429 if (wcid < 0)
1430 return 0;
1431
1432 /*
1433 * Clean up WCID attributes and write STA address to the device.
1434 */
1435 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1436 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1437 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1438 rt2x00lib_get_bssidx(rt2x00dev, vif));
1439 return 0;
1440}
1441EXPORT_SYMBOL_GPL(rt2800_sta_add);
1442
1443int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1444{
1445 /*
1446 * Remove WCID entry, no need to clean the attributes as they will
1447 * get renewed when the WCID is reused.
1448 */
1449 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1450
1451 return 0;
1452}
1453EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1454
f4450616
BZ		 1455void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1456 const unsigned int filter_flags)
1457{
1458 u32 reg;
1459
1460 /*
1461 * Start configuration steps.
1462 * Note that the version error will always be dropped
1463 * and broadcast frames will always be accepted since
1464 * there is no filter for it at this time.
1465 */
1466 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1467 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1468 !(filter_flags & FIF_FCSFAIL));
1469 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1470 !(filter_flags & FIF_PLCPFAIL));
1471 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1472 !(filter_flags & FIF_PROMISC_IN_BSS));
1473 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1474 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1475 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1476 !(filter_flags & FIF_ALLMULTI));
1477 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1478 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1479 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1480 !(filter_flags & FIF_CONTROL));
1481 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1482 !(filter_flags & FIF_CONTROL));
1483 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1484 !(filter_flags & FIF_CONTROL));
1485 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1486 !(filter_flags & FIF_CONTROL));
1487 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1488 !(filter_flags & FIF_CONTROL));
1489 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1490 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1491 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1492 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1493 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1494 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1495 !(filter_flags & FIF_CONTROL));
1496 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1497}
1498EXPORT_SYMBOL_GPL(rt2800_config_filter);
1499
1500void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1501 struct rt2x00intf_conf *conf, const unsigned int flags)
1502{
f4450616 1503 u32 reg;
fa8b4b22 1504 bool update_bssid = false;
f4450616
BZ		 1505
1506 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1507 /*
1508 * Enable synchronisation.
1509 */
1510 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1511 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1512 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1513
1514 if (conf->sync == TSF_SYNC_AP_NONE) {
1515 /*
1516 * Tune beacon queue transmit parameters for AP mode
1517 */
1518 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1519 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1520 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1521 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1522 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1523 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1524 } else {
1525 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1526 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1527 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1528 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1529 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1530 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1531 }
f4450616
BZ		 1532 }
1533
1534 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1535 if (flags & CONFIG_UPDATE_TYPE &&
1536 conf->sync == TSF_SYNC_AP_NONE) {
1537 /*
1538 * The BSSID register has to be set to our own mac
1539 * address in AP mode.
1540 */
1541 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1542 update_bssid = true;
1543 }
1544
c600c826
ID		 1545 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1546 reg = le32_to_cpu(conf->mac[1]);
1547 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1548 conf->mac[1] = cpu_to_le32(reg);
1549 }
f4450616
BZ		 1550
1551 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1552 conf->mac, sizeof(conf->mac));
1553 }
1554
fa8b4b22 1555 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1556 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1557 reg = le32_to_cpu(conf->bssid[1]);
1558 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1559 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1560 conf->bssid[1] = cpu_to_le32(reg);
1561 }
f4450616
BZ		 1562
1563 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1564 conf->bssid, sizeof(conf->bssid));
1565 }
1566}
1567EXPORT_SYMBOL_GPL(rt2800_config_intf);
1568
87c1915d
HS		 1569static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1570 struct rt2x00lib_erp *erp)
1571{
1572 bool any_sta_nongf = !!(erp->ht_opmode &
1573 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1574 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1575 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1576 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1577 u32 reg;
1578
1579 /* default protection rate for HT20: OFDM 24M */
1580 mm20_rate = gf20_rate = 0x4004;
1581
1582 /* default protection rate for HT40: duplicate OFDM 24M */
1583 mm40_rate = gf40_rate = 0x4084;
1584
1585 switch (protection) {
1586 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1587 /*
1588 * All STAs in this BSS are HT20/40 but there might be
1589 * STAs not supporting greenfield mode.
1590 * => Disable protection for HT transmissions.
1591 */
1592 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1593
1594 break;
1595 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1596 /*
1597 * All STAs in this BSS are HT20 or HT20/40 but there
1598 * might be STAs not supporting greenfield mode.
1599 * => Protect all HT40 transmissions.
1600 */
1601 mm20_mode = gf20_mode = 0;
1602 mm40_mode = gf40_mode = 2;
1603
1604 break;
1605 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1606 /*
1607 * Nonmember protection:
1608 * According to 802.11n we _should_ protect all
1609 * HT transmissions (but we don't have to).
1610 *
1611 * But if cts_protection is enabled we _shall_ protect
1612 * all HT transmissions using a CCK rate.
1613 *
1614 * And if any station is non GF we _shall_ protect
1615 * GF transmissions.
1616 *
1617 * We decide to protect everything
1618 * -> fall through to mixed mode.
1619 */
1620 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1621 /*
1622 * Legacy STAs are present
1623 * => Protect all HT transmissions.
1624 */
1625 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1626
1627 /*
1628 * If erp protection is needed we have to protect HT
1629 * transmissions with CCK 11M long preamble.
1630 */
1631 if (erp->cts_protection) {
1632 /* don't duplicate RTS/CTS in CCK mode */
1633 mm20_rate = mm40_rate = 0x0003;
1634 gf20_rate = gf40_rate = 0x0003;
1635 }
1636 break;
6403eab1 1637 }
87c1915d
HS		 1638
1639 /* check for STAs not supporting greenfield mode */
1640 if (any_sta_nongf)
1641 gf20_mode = gf40_mode = 2;
1642
1643 /* Update HT protection config */
1644 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1645 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1646 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1647 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1648
1649 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1650 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1651 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1652 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1653
1654 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1655 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1656 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1657 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1658
1659 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1660 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1661 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1662 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1663}
1664
02044643
HS		 1665void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1666 u32 changed)
f4450616
BZ		 1667{
1668 u32 reg;
1669
02044643
HS		 1670 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1671 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1672 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1673 !!erp->short_preamble);
1674 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1675 !!erp->short_preamble);
1676 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1677 }
f4450616 1678
02044643
HS		 1679 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1680 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1682 erp->cts_protection ? 2 : 0);
1683 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1684 }
f4450616 1685
02044643
HS		 1686 if (changed & BSS_CHANGED_BASIC_RATES) {
1687 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1688 erp->basic_rates);
1689 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1690 }
f4450616 1691
02044643
HS		 1692 if (changed & BSS_CHANGED_ERP_SLOT) {
1693 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1694 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1695 erp->slot_time);
1696 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1697
02044643
HS		 1698 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1699 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1700 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1701 }
f4450616 1702
02044643
HS		 1703 if (changed & BSS_CHANGED_BEACON_INT) {
1704 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1705 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1706 erp->beacon_int * 16);
1707 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1708 }
87c1915d
HS		 1709
1710 if (changed & BSS_CHANGED_HT)
1711 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1712}
1713EXPORT_SYMBOL_GPL(rt2800_config_erp);
1714
872834df
GW		 1715static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1716{
1717 u32 reg;
1718 u16 eeprom;
1719 u8 led_ctrl, led_g_mode, led_r_mode;
1720
1721 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1722 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1723 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1724 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1725 } else {
1726 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1727 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1728 }
1729 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1730
1731 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1732 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1733 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1734 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1735 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1736 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1737 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1738 if (led_ctrl == 0 || led_ctrl > 0x40) {
1739 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1740 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1741 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1742 } else {
1743 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1744 (led_g_mode << 2) | led_r_mode, 1);
1745 }
1746 }
1747}
1748
d96aa640
RJH		 1749static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1750 enum antenna ant)
1751{
1752 u32 reg;
1753 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1754 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1755
1756 if (rt2x00_is_pci(rt2x00dev)) {
1757 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1758 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1759 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1760 } else if (rt2x00_is_usb(rt2x00dev))
1761 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1762 eesk_pin, 0);
1763
99bdf51a
GW		 1764 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1765 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1766 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1767 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1768}
1769
f4450616
BZ		 1770void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1771{
1772 u8 r1;
1773 u8 r3;
d96aa640 1774 u16 eeprom;
f4450616
BZ		 1775
1776 rt2800_bbp_read(rt2x00dev, 1, &r1);
1777 rt2800_bbp_read(rt2x00dev, 3, &r3);
1778
872834df 1779 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1780 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1781 rt2800_config_3572bt_ant(rt2x00dev);
1782
f4450616
BZ		 1783 /*
1784 * Configure the TX antenna.
1785 */
d96aa640 1786 switch (ant->tx_chain_num) {
f4450616
BZ		 1787 case 1:
1788 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1789 break;
1790 case 2:
872834df 1791 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1792 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1793 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1794 else
1795 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1796 break;
1797 case 3:
4788ac1e 1798 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1799 break;
1800 }
1801
1802 /*
1803 * Configure the RX antenna.
1804 */
d96aa640 1805 switch (ant->rx_chain_num) {
f4450616 1806 case 1:
d96aa640
RJH		 1807 if (rt2x00_rt(rt2x00dev, RT3070) ||
1808 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1809 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1810 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1811 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1812 EEPROM_NIC_CONF1, &eeprom);
1813 if (rt2x00_get_field16(eeprom,
1814 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1815 rt2800_set_ant_diversity(rt2x00dev,
1816 rt2x00dev->default_ant.rx);
1817 }
f4450616
BZ		 1818 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1819 break;
1820 case 2:
872834df 1821 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1822 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1823 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1824 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1825 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1826 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1827 } else {
1828 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1829 }
f4450616
BZ		 1830 break;
1831 case 3:
1832 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1833 break;
1834 }
1835
1836 rt2800_bbp_write(rt2x00dev, 3, r3);
1837 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1838
1839 if (rt2x00_rt(rt2x00dev, RT3593)) {
1840 if (ant->rx_chain_num == 1)
1841 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1842 else
1843 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1844 }
f4450616
BZ		 1845}
1846EXPORT_SYMBOL_GPL(rt2800_config_ant);
1847
1848static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1849 struct rt2x00lib_conf *libconf)
1850{
1851 u16 eeprom;
1852 short lna_gain;
1853
1854 if (libconf->rf.channel <= 14) {
3e38d3da 1855 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1856 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1857 } else if (libconf->rf.channel <= 64) {
3e38d3da 1858 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1859 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1860 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1861 if (rt2x00_rt(rt2x00dev, RT3593)) {
1862 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1863 lna_gain = rt2x00_get_field16(eeprom,
1864 EEPROM_EXT_LNA2_A1);
1865 } else {
1866 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1867 lna_gain = rt2x00_get_field16(eeprom,
1868 EEPROM_RSSI_BG2_LNA_A1);
1869 }
f4450616 1870 } else {
f36bb0ca
GJ		 1871 if (rt2x00_rt(rt2x00dev, RT3593)) {
1872 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1873 lna_gain = rt2x00_get_field16(eeprom,
1874 EEPROM_EXT_LNA2_A2);
1875 } else {
1876 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1877 lna_gain = rt2x00_get_field16(eeprom,
1878 EEPROM_RSSI_A2_LNA_A2);
1879 }
f4450616
BZ		 1880 }
1881
1882 rt2x00dev->lna_gain = lna_gain;
1883}
1884
3f1b8739
GJ		 1885#define FREQ_OFFSET_BOUND 0x5f
1886
1887static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1888{
1889 u8 freq_offset, prev_freq_offset;
1890 u8 rfcsr, prev_rfcsr;
1891
1892 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1893 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1894
1895 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1896 prev_rfcsr = rfcsr;
1897
1898 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1899 if (rfcsr == prev_rfcsr)
1900 return;
1901
1902 if (rt2x00_is_usb(rt2x00dev)) {
1903 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1904 freq_offset, prev_rfcsr);
1905 return;
1906 }
1907
1908 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1909 while (prev_freq_offset != freq_offset) {
1910 if (prev_freq_offset < freq_offset)
1911 prev_freq_offset++;
1912 else
1913 prev_freq_offset--;
1914
1915 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1916 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1917
1918 usleep_range(1000, 1500);
1919 }
1920}
1921
06855ef4
GW		 1922static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1923 struct ieee80211_conf *conf,
1924 struct rf_channel *rf,
1925 struct channel_info *info)
f4450616
BZ		 1926{
1927 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1928
d96aa640 1929 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1930 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1931
d96aa640 1932 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1933 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1934 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1935 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1936 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1937
1938 if (rf->channel > 14) {
1939 /*
1940 * When TX power is below 0, we should increase it by 7 to
25985edc 1941 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1942 * However this means that values between 0 and 7 have
1943 * double meaning, and we should set a 7DBm boost flag.
1944 */
1945 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1946 (info->default_power1 >= 0));
f4450616 1947
8d1331b3
ID		 1948 if (info->default_power1 < 0)
1949 info->default_power1 += 7;
f4450616 1950
8d1331b3 1951 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1952
1953 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1954 (info->default_power2 >= 0));
f4450616 1955
8d1331b3
ID		 1956 if (info->default_power2 < 0)
1957 info->default_power2 += 7;
f4450616 1958
8d1331b3 1959 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1960 } else {
8d1331b3
ID		 1961 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1962 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1963 }
1964
1965 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1966
1967 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1968 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1969 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1970 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1971
1972 udelay(200);
1973
1974 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1975 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1976 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1977 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1978
1979 udelay(200);
1980
1981 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1982 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1983 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1984 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1985}
1986
06855ef4
GW		 1987static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1988 struct ieee80211_conf *conf,
1989 struct rf_channel *rf,
1990 struct channel_info *info)
f4450616 1991{
3a1c0128 1992 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1993 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1994
1995 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1996
1997 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1998 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1999 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2000
2001 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2002 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2003 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2004
2005 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2006 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2007 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2008
5a673964 2009 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2010 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2011 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2012
2013 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2014 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2015 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2016 rt2x00dev->default_ant.rx_chain_num <= 1);
2017 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2018 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2019 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2020 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2021 rt2x00dev->default_ant.tx_chain_num <= 1);
2022 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2023 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2024 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2025
f4450616
BZ		 2026 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2027 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2028 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2029
f1f12f98
SG		 2030 if (rt2x00_rt(rt2x00dev, RT3390)) {
2031 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2032 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2033 } else {
3a1c0128
GW		 2034 if (conf_is_ht40(conf)) {
2035 calib_tx = drv_data->calibration_bw40;
2036 calib_rx = drv_data->calibration_bw40;
2037 } else {
2038 calib_tx = drv_data->calibration_bw20;
2039 calib_rx = drv_data->calibration_bw20;
2040 }
f1f12f98
SG		 2041 }
2042
2043 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2044 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2045 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2046
2047 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2048 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2049 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2050
71976907 2051 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2052 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2053 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2054
2055 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2056 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2057 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2058 msleep(1);
2059 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2060 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2061}
2062
872834df
GW		 2063static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2064 struct ieee80211_conf *conf,
2065 struct rf_channel *rf,
2066 struct channel_info *info)
2067{
3a1c0128 2068 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2069 u8 rfcsr;
2070 u32 reg;
2071
2072 if (rf->channel <= 14) {
5d137dff
GW		 2073 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2074 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2075 } else {
2076 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2077 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2078 }
2079
2080 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2081 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2082
2083 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2084 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2085 if (rf->channel <= 14)
2086 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2087 else
2088 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2089 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2090
2091 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2092 if (rf->channel <= 14)
2093 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2094 else
2095 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2096 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2097
2098 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2099 if (rf->channel <= 14) {
2100 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2101 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2102 info->default_power1);
872834df
GW		 2103 } else {
2104 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2105 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2106 (info->default_power1 & 0x3) |
2107 ((info->default_power1 & 0xC) << 1));
2108 }
2109 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2110
2111 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2112 if (rf->channel <= 14) {
2113 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2114 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2115 info->default_power2);
872834df
GW		 2116 } else {
2117 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2118 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2119 (info->default_power2 & 0x3) |
2120 ((info->default_power2 & 0xC) << 1));
2121 }
2122 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2123
2124 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2125 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2126 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2127 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2128 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2129 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2130 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2131 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2132 if (rf->channel <= 14) {
2133 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2134 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2135 }
2136 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2137 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2138 } else {
2139 switch (rt2x00dev->default_ant.tx_chain_num) {
2140 case 1:
2141 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2142 case 2:
2143 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2144 break;
2145 }
2146
2147 switch (rt2x00dev->default_ant.rx_chain_num) {
2148 case 1:
2149 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2150 case 2:
2151 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2152 break;
2153 }
2154 }
2155 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2156
2157 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2158 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2159 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2160
3a1c0128
GW		 2161 if (conf_is_ht40(conf)) {
2162 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2163 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2164 } else {
2165 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2166 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2167 }
872834df
GW		 2168
2169 if (rf->channel <= 14) {
2170 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2171 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2172 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2173 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2174 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2175 rfcsr = 0x4c;
2176 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2177 drv_data->txmixer_gain_24g);
2178 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2179 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2180 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2181 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2182 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2183 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2184 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2185 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2186 } else {
58b8ae14
GW		 2187 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2188 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2189 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2190 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2191 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2192 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2193 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2194 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2195 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2196 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2197 rfcsr = 0x7a;
2198 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2199 drv_data->txmixer_gain_5g);
2200 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2201 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2202 if (rf->channel <= 64) {
2203 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2204 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2205 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2206 } else if (rf->channel <= 128) {
2207 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2208 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2209 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2210 } else {
2211 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2212 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2213 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2214 }
2215 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2216 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2217 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2218 }
2219
99bdf51a
GW		 2220 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2221 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2222 if (rf->channel <= 14)
99bdf51a 2223 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2224 else
99bdf51a
GW		 2225 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2226 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2227
2228 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2229 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2230 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2231}
60687ba7 2232
f42b0465
GJ		 2233static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2234 struct ieee80211_conf *conf,
2235 struct rf_channel *rf,
2236 struct channel_info *info)
2237{
2238 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2239 u8 txrx_agc_fc;
2240 u8 txrx_h20m;
2241 u8 rfcsr;
2242 u8 bbp;
2243 const bool txbf_enabled = false; /* TODO */
2244
2245 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2246 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2247 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2248 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2249 rt2800_bbp_write(rt2x00dev, 109, bbp);
2250
2251 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2252 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2253 rt2800_bbp_write(rt2x00dev, 110, bbp);
2254
2255 if (rf->channel <= 14) {
2256 /* Restore BBP 25 & 26 for 2.4 GHz */
2257 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2258 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2259 } else {
2260 /* Hard code BBP 25 & 26 for 5GHz */
2261
2262 /* Enable IQ Phase correction */
2263 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2264 /* Setup IQ Phase correction value */
2265 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2266 }
2267
2268 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2269 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2270
2271 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2272 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2273 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2274
2275 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2276 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2277 if (rf->channel <= 14)
2278 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2279 else
2280 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2281 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2282
2283 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2284 if (rf->channel <= 14) {
2285 rfcsr = 0;
2286 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2287 info->default_power1 & 0x1f);
2288 } else {
2289 if (rt2x00_is_usb(rt2x00dev))
2290 rfcsr = 0x40;
2291
2292 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2293 ((info->default_power1 & 0x18) << 1) |
2294 (info->default_power1 & 7));
2295 }
2296 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2297
2298 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2299 if (rf->channel <= 14) {
2300 rfcsr = 0;
2301 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2302 info->default_power2 & 0x1f);
2303 } else {
2304 if (rt2x00_is_usb(rt2x00dev))
2305 rfcsr = 0x40;
2306
2307 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2308 ((info->default_power2 & 0x18) << 1) |
2309 (info->default_power2 & 7));
2310 }
2311 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2312
2313 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2314 if (rf->channel <= 14) {
2315 rfcsr = 0;
2316 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2317 info->default_power3 & 0x1f);
2318 } else {
2319 if (rt2x00_is_usb(rt2x00dev))
2320 rfcsr = 0x40;
2321
2322 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2323 ((info->default_power3 & 0x18) << 1) |
2324 (info->default_power3 & 7));
2325 }
2326 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2327
2328 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2329 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2330 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2331 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2332 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2333 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2334 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2335 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2336 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2337
2338 switch (rt2x00dev->default_ant.tx_chain_num) {
2339 case 3:
2340 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2341 /* fallthrough */
2342 case 2:
2343 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2344 /* fallthrough */
2345 case 1:
2346 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2347 break;
2348 }
2349
2350 switch (rt2x00dev->default_ant.rx_chain_num) {
2351 case 3:
2352 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2353 /* fallthrough */
2354 case 2:
2355 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2356 /* fallthrough */
2357 case 1:
2358 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2359 break;
2360 }
2361 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2362
e979a8ab 2363 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2364
2365 if (conf_is_ht40(conf)) {
2366 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2367 RFCSR24_TX_AGC_FC);
2368 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2369 RFCSR24_TX_H20M);
2370 } else {
2371 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2372 RFCSR24_TX_AGC_FC);
2373 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2374 RFCSR24_TX_H20M);
2375 }
2376
2377 /* NOTE: the reference driver does not writes the new value
2378 * back to RFCSR 32
2379 */
2380 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2381 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2382
2383 if (rf->channel <= 14)
2384 rfcsr = 0xa0;
2385 else
2386 rfcsr = 0x80;
2387 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2388
2389 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2390 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2391 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2392 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2393
2394 /* Band selection */
2395 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2396 if (rf->channel <= 14)
2397 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2398 else
2399 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2400 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2401
2402 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2403 if (rf->channel <= 14)
2404 rfcsr = 0x3c;
2405 else
2406 rfcsr = 0x20;
2407 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2408
2409 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2410 if (rf->channel <= 14)
2411 rfcsr = 0x1a;
2412 else
2413 rfcsr = 0x12;
2414 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2415
2416 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2417 if (rf->channel >= 1 && rf->channel <= 14)
2418 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2419 else if (rf->channel >= 36 && rf->channel <= 64)
2420 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2421 else if (rf->channel >= 100 && rf->channel <= 128)
2422 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2423 else
2424 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2425 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2426
2427 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2428 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2429 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2430
2431 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2432
2433 if (rf->channel <= 14) {
2434 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2435 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2436 } else {
2437 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2438 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2439 }
2440
2441 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2442 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2443 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2444
2445 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2446 if (rf->channel <= 14) {
2447 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2448 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2449 } else {
2450 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2451 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2452 }
2453 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2454
2455 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2456 if (rf->channel <= 14)
2457 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2458 else
2459 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2460
2461 if (txbf_enabled)
2462 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2463
2464 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2465
2466 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2467 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2468 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2469
2470 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2471 if (rf->channel <= 14)
2472 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2473 else
2474 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2475 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2476
2477 if (rf->channel <= 14) {
2478 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2479 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2480 } else {
2481 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2482 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2483 }
2484
2485 /* Initiate VCO calibration */
2486 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2487 if (rf->channel <= 14) {
2488 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2489 } else {
2490 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2491 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2492 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2493 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2494 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2495 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2496 }
2497 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2498
2499 if (rf->channel >= 1 && rf->channel <= 14) {
2500 rfcsr = 0x23;
2501 if (txbf_enabled)
2502 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2503 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2504
2505 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2506 } else if (rf->channel >= 36 && rf->channel <= 64) {
2507 rfcsr = 0x36;
2508 if (txbf_enabled)
2509 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2510 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2511
2512 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2513 } else if (rf->channel >= 100 && rf->channel <= 128) {
2514 rfcsr = 0x32;
2515 if (txbf_enabled)
2516 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2517 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2518
2519 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2520 } else {
2521 rfcsr = 0x30;
2522 if (txbf_enabled)
2523 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2524 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2525
2526 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2527 }
2528}
2529
7573cb5b 2530#define POWER_BOUND 0x27
8f821098 2531#define POWER_BOUND_5G 0x2b
0c9e5fb9 2532
a89534ed
WH		 2533static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2534 struct ieee80211_conf *conf,
2535 struct rf_channel *rf,
2536 struct channel_info *info)
2537{
2538 u8 rfcsr;
2539
2540 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2541 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2542 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2543 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2544 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2545
2546 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2547 if (info->default_power1 > POWER_BOUND)
2548 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2549 else
2550 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2551 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2552
0c9e5fb9 2553 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2554
2555 if (rf->channel <= 14) {
2556 if (rf->channel == 6)
2557 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2558 else
2559 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2560
2561 if (rf->channel >= 1 && rf->channel <= 6)
2562 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2563 else if (rf->channel >= 7 && rf->channel <= 11)
2564 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2565 else if (rf->channel >= 12 && rf->channel <= 14)
2566 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2567 }
2568}
2569
03839951
DG		 2570static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2571 struct ieee80211_conf *conf,
2572 struct rf_channel *rf,
2573 struct channel_info *info)
2574{
2575 u8 rfcsr;
2576
2577 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2578 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2579
2580 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2581 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2582 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2583
2584 if (info->default_power1 > POWER_BOUND)
2585 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2586 else
2587 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2588
2589 if (info->default_power2 > POWER_BOUND)
2590 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2591 else
2592 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2593
0c9e5fb9 2594 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2595
2596 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2597 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2598 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2599
2600 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2601 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2602 else
2603 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2604
2605 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2606 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2607 else
2608 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2609
2610 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2611 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2612
2613 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2614
2615 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2616}
2617
60687ba7 2618static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2619 struct ieee80211_conf *conf,
2620 struct rf_channel *rf,
2621 struct channel_info *info)
2622{
2623 u8 rfcsr;
adde5882
GJ		 2624
2625 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2626 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2627 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2628 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2629 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2630
2631 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2632 if (info->default_power1 > POWER_BOUND)
2633 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2634 else
2635 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2636 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2637
cff3d1f0
ZL		 2638 if (rt2x00_rt(rt2x00dev, RT5392)) {
2639 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2640 if (info->default_power2 > POWER_BOUND)
7573cb5b 2641 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2642 else
2643 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2644 info->default_power2);
2645 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2646 }
2647
adde5882 2648 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2649 if (rt2x00_rt(rt2x00dev, RT5392)) {
2650 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2651 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2652 }
adde5882
GJ		 2653 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2654 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2655 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2656 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2657 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2658
0c9e5fb9 2659 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2660
adde5882
GJ		 2661 if (rf->channel <= 14) {
2662 int idx = rf->channel-1;
2663
c429dfef 2664 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2665 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2666 /* r55/r59 value array of channel 1~14 */
2667 static const char r55_bt_rev[] = {0x83, 0x83,
2668 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2669 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2670 static const char r59_bt_rev[] = {0x0e, 0x0e,
2671 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2672 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2673
2674 rt2800_rfcsr_write(rt2x00dev, 55,
2675 r55_bt_rev[idx]);
2676 rt2800_rfcsr_write(rt2x00dev, 59,
2677 r59_bt_rev[idx]);
2678 } else {
2679 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2680 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2681 0x88, 0x88, 0x86, 0x85, 0x84};
2682
2683 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2684 }
2685 } else {
2686 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2687 static const char r55_nonbt_rev[] = {0x23, 0x23,
2688 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2689 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2690 static const char r59_nonbt_rev[] = {0x07, 0x07,
2691 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2692 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2693
2694 rt2800_rfcsr_write(rt2x00dev, 55,
2695 r55_nonbt_rev[idx]);
2696 rt2800_rfcsr_write(rt2x00dev, 59,
2697 r59_nonbt_rev[idx]);
2ed71884 2698 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2699 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2700 static const char r59_non_bt[] = {0x8f, 0x8f,
2701 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2702 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2703
2704 rt2800_rfcsr_write(rt2x00dev, 59,
2705 r59_non_bt[idx]);
2706 }
2707 }
2708 }
60687ba7
RST		 2709}
2710
8f821098
SG		 2711static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2712 struct ieee80211_conf *conf,
2713 struct rf_channel *rf,
2714 struct channel_info *info)
2715{
2716 u8 rfcsr, ep_reg;
d5ae7a6b 2717 u32 reg;
8f821098
SG		 2718 int power_bound;
2719
2720 /* TODO */
2721 const bool is_11b = false;
2722 const bool is_type_ep = false;
2723
d5ae7a6b
SG		 2724 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2725 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2726 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2727 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2728
2729 /* Order of values on rf_channel entry: N, K, mod, R */
2730 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2731
2732 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2733 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2734 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2735 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2736 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2737
2738 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2739 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2740 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2741 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2742
2743 if (rf->channel <= 14) {
2744 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2745 /* FIXME: RF11 owerwrite ? */
2746 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2747 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2748 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2749 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2750 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2751 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2752 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2753 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2754 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2755 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2756 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2757 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2758 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2759 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2760 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2761 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2762 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2763 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2764 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2765 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2766 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2767 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2768 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2769 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2770 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2771 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2772 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2773 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2774
2775 /* TODO RF27 <- tssi */
2776
2777 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2778 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2779 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2780
2781 if (is_11b) {
2782 /* CCK */
2783 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2784 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2785 if (is_type_ep)
2786 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2787 else
2788 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2789 } else {
2790 /* OFDM */
2791 if (is_type_ep)
2792 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2793 else
2794 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2795 }
2796
2797 power_bound = POWER_BOUND;
2798 ep_reg = 0x2;
2799 } else {
2800 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2801 /* FIMXE: RF11 overwrite */
2802 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2803 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2804 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2805 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2806 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2807 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2808 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2809 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2810 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2811 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2812 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2813 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2814 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2815 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2816
2817 /* TODO RF27 <- tssi */
2818
2819 if (rf->channel >= 36 && rf->channel <= 64) {
2820
2821 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2822 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2823 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2824 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2825 if (rf->channel <= 50)
2826 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2827 else if (rf->channel >= 52)
2828 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2829 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2830 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2831 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2832 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2833 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2834 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2835 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2836 if (rf->channel <= 50) {
2837 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2838 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2839 } else if (rf->channel >= 52) {
2840 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2841 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2842 }
2843
2844 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2845 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2846 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2847
2848 } else if (rf->channel >= 100 && rf->channel <= 165) {
2849
2850 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2851 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2852 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2853 if (rf->channel <= 153) {
2854 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2855 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2856 } else if (rf->channel >= 155) {
2857 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2858 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2859 }
2860 if (rf->channel <= 138) {
2861 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2862 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2863 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2864 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2865 } else if (rf->channel >= 140) {
2866 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2867 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2868 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2869 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2870 }
2871 if (rf->channel <= 124)
2872 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2873 else if (rf->channel >= 126)
2874 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2875 if (rf->channel <= 138)
2876 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2877 else if (rf->channel >= 140)
2878 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2879 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2880 if (rf->channel <= 138)
2881 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2882 else if (rf->channel >= 140)
2883 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2884 if (rf->channel <= 128)
2885 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2886 else if (rf->channel >= 130)
2887 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2888 if (rf->channel <= 116)
2889 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2890 else if (rf->channel >= 118)
2891 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2892 if (rf->channel <= 138)
2893 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2894 else if (rf->channel >= 140)
2895 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2896 if (rf->channel <= 116)
2897 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2898 else if (rf->channel >= 118)
2899 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2900 }
2901
2902 power_bound = POWER_BOUND_5G;
2903 ep_reg = 0x3;
2904 }
2905
2906 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2907 if (info->default_power1 > power_bound)
2908 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2909 else
2910 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2911 if (is_type_ep)
2912 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2913 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2914
2915 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2916 if (info->default_power2 > power_bound)
8f821098
SG		 2917 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2918 else
2919 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2920 if (is_type_ep)
2921 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2922 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2923
2924 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2925 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2926 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2927
2928 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2929 rt2x00dev->default_ant.tx_chain_num >= 1);
2930 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2931 rt2x00dev->default_ant.tx_chain_num == 2);
2932 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2933
2934 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2935 rt2x00dev->default_ant.rx_chain_num >= 1);
2936 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2937 rt2x00dev->default_ant.rx_chain_num == 2);
2938 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2939
2940 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2941 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2942
2943 if (conf_is_ht40(conf))
2944 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2945 else
2946 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2947
2948 if (!is_11b) {
2949 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2950 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2951 }
2952
2953 /* TODO proper frequency adjustment */
0c9e5fb9 2954 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2955
2956 /* TODO merge with others */
2957 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2958 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2959 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 2960
2961 /* BBP settings */
2962 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2963 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2964 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2965
2966 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2967 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2968 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2969 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2970
2971 /* GLRT band configuration */
2972 rt2800_bbp_write(rt2x00dev, 195, 128);
2973 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2974 rt2800_bbp_write(rt2x00dev, 195, 129);
2975 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2976 rt2800_bbp_write(rt2x00dev, 195, 130);
2977 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2978 rt2800_bbp_write(rt2x00dev, 195, 131);
2979 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2980 rt2800_bbp_write(rt2x00dev, 195, 133);
2981 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2982 rt2800_bbp_write(rt2x00dev, 195, 124);
2983 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 2984}
2985
5bc2dd06
SG		 2986static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2987 const unsigned int word,
2988 const u8 value)
2989{
2990 u8 chain, reg;
2991
2992 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2993 rt2800_bbp_read(rt2x00dev, 27, &reg);
2994 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2995 rt2800_bbp_write(rt2x00dev, 27, reg);
2996
2997 rt2800_bbp_write(rt2x00dev, word, value);
2998 }
2999}
3000
8756130b
SG		 3001static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3002{
3003 u8 cal;
3004
415e3f2f 3005 /* TX0 IQ Gain */
8756130b 3006 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3007 if (channel <= 14)
3008 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3009 else if (channel >= 36 && channel <= 64)
3010 cal = rt2x00_eeprom_byte(rt2x00dev,
3011 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3012 else if (channel >= 100 && channel <= 138)
3013 cal = rt2x00_eeprom_byte(rt2x00dev,
3014 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3015 else if (channel >= 140 && channel <= 165)
3016 cal = rt2x00_eeprom_byte(rt2x00dev,
3017 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3018 else
3019 cal = 0;
8756130b
SG		 3020 rt2800_bbp_write(rt2x00dev, 159, cal);
3021
415e3f2f 3022 /* TX0 IQ Phase */
8756130b 3023 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3024 if (channel <= 14)
3025 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3026 else if (channel >= 36 && channel <= 64)
3027 cal = rt2x00_eeprom_byte(rt2x00dev,
3028 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3029 else if (channel >= 100 && channel <= 138)
3030 cal = rt2x00_eeprom_byte(rt2x00dev,
3031 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3032 else if (channel >= 140 && channel <= 165)
3033 cal = rt2x00_eeprom_byte(rt2x00dev,
3034 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3035 else
3036 cal = 0;
8756130b
SG		 3037 rt2800_bbp_write(rt2x00dev, 159, cal);
3038
415e3f2f 3039 /* TX1 IQ Gain */
8756130b 3040 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3041 if (channel <= 14)
3042 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3043 else if (channel >= 36 && channel <= 64)
3044 cal = rt2x00_eeprom_byte(rt2x00dev,
3045 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3046 else if (channel >= 100 && channel <= 138)
3047 cal = rt2x00_eeprom_byte(rt2x00dev,
3048 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3049 else if (channel >= 140 && channel <= 165)
3050 cal = rt2x00_eeprom_byte(rt2x00dev,
3051 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3052 else
3053 cal = 0;
8756130b
SG		 3054 rt2800_bbp_write(rt2x00dev, 159, cal);
3055
415e3f2f 3056 /* TX1 IQ Phase */
8756130b 3057 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3058 if (channel <= 14)
3059 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3060 else if (channel >= 36 && channel <= 64)
3061 cal = rt2x00_eeprom_byte(rt2x00dev,
3062 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3063 else if (channel >= 100 && channel <= 138)
3064 cal = rt2x00_eeprom_byte(rt2x00dev,
3065 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3066 else if (channel >= 140 && channel <= 165)
3067 cal = rt2x00_eeprom_byte(rt2x00dev,
3068 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3069 else
3070 cal = 0;
8756130b
SG		 3071 rt2800_bbp_write(rt2x00dev, 159, cal);
3072
415e3f2f
SG		 3073 /* FIXME: possible RX0, RX1 callibration ? */
3074
8756130b
SG		 3075 /* RF IQ compensation control */
3076 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3077 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3078 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3079
3080 /* RF IQ imbalance compensation control */
3081 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3082 cal = rt2x00_eeprom_byte(rt2x00dev,
3083 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3084 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3085}
3086
97aa03f1
GJ		 3087static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3088 unsigned int channel,
3089 char txpower)
3090{
fc739cfe
GJ		 3091 if (rt2x00_rt(rt2x00dev, RT3593))
3092 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3093
97aa03f1
GJ		 3094 if (channel <= 14)
3095 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3096
3097 if (rt2x00_rt(rt2x00dev, RT3593))
3098 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3099 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3100 else
3101 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3102}
3103
f4450616
BZ		 3104static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3105 struct ieee80211_conf *conf,
3106 struct rf_channel *rf,
3107 struct channel_info *info)
3108{
3109 u32 reg;
3110 unsigned int tx_pin;
a89534ed 3111 u8 bbp, rfcsr;
f4450616 3112
97aa03f1
GJ		 3113 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3114 info->default_power1);
3115 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3116 info->default_power2);
c0a14369
GJ		 3117 if (rt2x00dev->default_ant.tx_chain_num > 2)
3118 info->default_power3 =
3119 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3120 info->default_power3);
46323e11 3121
5aa57015
GW		 3122 switch (rt2x00dev->chip.rf) {
3123 case RF2020:
3124 case RF3020:
3125 case RF3021:
3126 case RF3022:
3127 case RF3320:
06855ef4 3128 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3129 break;
3130 case RF3052:
872834df 3131 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3132 break;
f42b0465
GJ		 3133 case RF3053:
3134 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3135 break;
a89534ed
WH		 3136 case RF3290:
3137 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3138 break;
03839951
DG		 3139 case RF3322:
3140 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3141 break;
3b9b74ba 3142 case RF3070:
ccf91bd6 3143 case RF5360:
5aa57015 3144 case RF5370:
2ed71884 3145 case RF5372:
5aa57015 3146 case RF5390:
cff3d1f0 3147 case RF5392:
adde5882 3148 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3149 break;
8f821098
SG		 3150 case RF5592:
3151 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3152 break;
5aa57015 3153 default:
06855ef4 3154 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3155 }
f4450616 3156
3b9b74ba
SG		 3157 if (rt2x00_rf(rt2x00dev, RF3070) ||
3158 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3159 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed
WH		 3160 rt2x00_rf(rt2x00dev, RF5360) ||
3161 rt2x00_rf(rt2x00dev, RF5370) ||
3162 rt2x00_rf(rt2x00dev, RF5372) ||
3163 rt2x00_rf(rt2x00dev, RF5390) ||
3164 rt2x00_rf(rt2x00dev, RF5392)) {
3165 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3166 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3167 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3168 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3169
3170 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3171 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3172 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3173 }
3174
f4450616
BZ		 3175 /*
3176 * Change BBP settings
3177 */
03839951
DG		 3178 if (rt2x00_rt(rt2x00dev, RT3352)) {
3179 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3180 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3181 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3182 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3183 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3184 if (rf->channel > 14) {
3185 /* Disable CCK Packet detection on 5GHz */
3186 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3187 } else {
3188 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3189 }
3190
3191 if (conf_is_ht40(conf))
3192 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3193 else
3194 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3195
3196 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3197 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3198 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3199 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3200 } else {
3201 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3202 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3203 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3204 rt2800_bbp_write(rt2x00dev, 86, 0);
3205 }
f4450616
BZ		 3206
3207 if (rf->channel <= 14) {
2ed71884 3208 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3209 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3210 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3211 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3212 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3213 } else {
f42b0465
GJ		 3214 if (rt2x00_rt(rt2x00dev, RT3593))
3215 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3216 else
3217 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3218 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3219 }
f42b0465
GJ		 3220 if (rt2x00_rt(rt2x00dev, RT3593))
3221 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3222 }
f42b0465 3223
f4450616 3224 } else {
872834df
GW		 3225 if (rt2x00_rt(rt2x00dev, RT3572))
3226 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3227 else if (rt2x00_rt(rt2x00dev, RT3593))
3228 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3229 else
3230 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3231
f42b0465
GJ		 3232 if (rt2x00_rt(rt2x00dev, RT3593))
3233 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3234
c429dfef 3235 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3236 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3237 else
3238 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3239 }
3240
3241 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3242 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3243 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3244 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3245 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3246
872834df
GW		 3247 if (rt2x00_rt(rt2x00dev, RT3572))
3248 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3249
f4450616
BZ		 3250 tx_pin = 0;
3251
bb16d488
GJ		 3252 switch (rt2x00dev->default_ant.tx_chain_num) {
3253 case 3:
3254 /* Turn on tertiary PAs */
3255 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3256 rf->channel > 14);
3257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3258 rf->channel <= 14);
3259 /* fall-through */
3260 case 2:
3261 /* Turn on secondary PAs */
65f31b5e
GW		 3262 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3263 rf->channel > 14);
3264 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3265 rf->channel <= 14);
bb16d488
GJ		 3266 /* fall-through */
3267 case 1:
3268 /* Turn on primary PAs */
3269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3270 rf->channel > 14);
c429dfef 3271 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3272 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3273 else
3274 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3275 rf->channel <= 14);
3276 break;
f4450616
BZ		 3277 }
3278
bb16d488
GJ		 3279 switch (rt2x00dev->default_ant.rx_chain_num) {
3280 case 3:
3281 /* Turn on tertiary LNAs */
3282 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3283 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3284 /* fall-through */
3285 case 2:
3286 /* Turn on secondary LNAs */
f4450616
BZ		 3287 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3288 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3289 /* fall-through */
3290 case 1:
3291 /* Turn on primary LNAs */
3292 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3294 break;
f4450616
BZ		 3295 }
3296
f4450616
BZ		 3297 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3298 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3299
3300 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3301
733aec6a 3302 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3303 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3304
733aec6a
GJ		 3305 /* AGC init */
3306 if (rf->channel <= 14)
3307 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3308 else
3309 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3310
3311 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3312 }
3313
f42b0465 3314 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3315 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3316
60751001
GJ		 3317 /* Band selection */
3318 if (rt2x00_is_usb(rt2x00dev) ||
3319 rt2x00_is_pcie(rt2x00dev)) {
3320 /* GPIO #8 controls all paths */
f42b0465
GJ		 3321 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3322 if (rf->channel <= 14)
3323 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3324 else
3325 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3326 }
f42b0465 3327
60751001
GJ		 3328 /* LNA PE control. */
3329 if (rt2x00_is_usb(rt2x00dev)) {
3330 /* GPIO #4 controls PE0 and PE1,
3331 * GPIO #7 controls PE2
3332 */
f42b0465
GJ		 3333 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3334 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3335
f42b0465
GJ		 3336 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3337 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3338 } else if (rt2x00_is_pcie(rt2x00dev)) {
3339 /* GPIO #4 controls PE0, PE1 and PE2 */
3340 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3341 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3342 }
3343
60751001
GJ		 3344 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3345
f42b0465
GJ		 3346 /* AGC init */
3347 if (rf->channel <= 14)
3348 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3349 else
3350 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3351
3352 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3353
3354 usleep_range(1000, 1500);
3355 }
3356
6803141b
SG		 3357 if (rt2x00_rt(rt2x00dev, RT5592)) {
3358 rt2800_bbp_write(rt2x00dev, 195, 141);
3359 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3360
8ba0ebf3
SG		 3361 /* AGC init */
3362 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3363 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3364
8756130b 3365 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3366 }
3367
f4450616
BZ		 3368 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3369 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3370 rt2800_bbp_write(rt2x00dev, 4, bbp);
3371
3372 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3373 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3374 rt2800_bbp_write(rt2x00dev, 3, bbp);
3375
8d0c9b65 3376 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3377 if (conf_is_ht40(conf)) {
3378 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3379 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3380 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3381 } else {
3382 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3383 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3384 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3385 }
3386 }
3387
3388 msleep(1);
977206d7
HS		 3389
3390 /*
3391 * Clear channel statistic counters
3392 */
3393 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3394 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3395 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3396
3397 /*
3398 * Clear update flag
3399 */
3400 if (rt2x00_rt(rt2x00dev, RT3352)) {
3401 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3402 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3403 rt2800_bbp_write(rt2x00dev, 49, bbp);
3404 }
f4450616
BZ		 3405}
3406
9e33a355
HS		 3407static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3408{
3409 u8 tssi_bounds[9];
3410 u8 current_tssi;
3411 u16 eeprom;
3412 u8 step;
3413 int i;
3414
6e956da2
SG		 3415 /*
3416 * First check if temperature compensation is supported.
3417 */
3418 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3419 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3420 return 0;
3421
9e33a355
HS		 3422 /*
3423 * Read TSSI boundaries for temperature compensation from
3424 * the EEPROM.
3425 *
3426 * Array idx 0 1 2 3 4 5 6 7 8
3427 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3428 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3429 */
3430 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 3431 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3432 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3433 EEPROM_TSSI_BOUND_BG1_MINUS4);
3434 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3435 EEPROM_TSSI_BOUND_BG1_MINUS3);
3436
3e38d3da 3437 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3438 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3439 EEPROM_TSSI_BOUND_BG2_MINUS2);
3440 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3441 EEPROM_TSSI_BOUND_BG2_MINUS1);
3442
3e38d3da 3443 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3444 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3445 EEPROM_TSSI_BOUND_BG3_REF);
3446 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3447 EEPROM_TSSI_BOUND_BG3_PLUS1);
3448
3e38d3da 3449 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3450 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3451 EEPROM_TSSI_BOUND_BG4_PLUS2);
3452 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3453 EEPROM_TSSI_BOUND_BG4_PLUS3);
3454
3e38d3da 3455 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3456 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3457 EEPROM_TSSI_BOUND_BG5_PLUS4);
3458
3459 step = rt2x00_get_field16(eeprom,
3460 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3461 } else {
3e38d3da 3462 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3463 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3464 EEPROM_TSSI_BOUND_A1_MINUS4);
3465 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3466 EEPROM_TSSI_BOUND_A1_MINUS3);
3467
3e38d3da 3468 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3469 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3470 EEPROM_TSSI_BOUND_A2_MINUS2);
3471 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3472 EEPROM_TSSI_BOUND_A2_MINUS1);
3473
3e38d3da 3474 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3475 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3476 EEPROM_TSSI_BOUND_A3_REF);
3477 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3478 EEPROM_TSSI_BOUND_A3_PLUS1);
3479
3e38d3da 3480 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3481 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3482 EEPROM_TSSI_BOUND_A4_PLUS2);
3483 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3484 EEPROM_TSSI_BOUND_A4_PLUS3);
3485
3e38d3da 3486 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3487 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3488 EEPROM_TSSI_BOUND_A5_PLUS4);
3489
3490 step = rt2x00_get_field16(eeprom,
3491 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3492 }
3493
3494 /*
3495 * Check if temperature compensation is supported.
3496 */
bf7e1abe 3497 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3498 return 0;
3499
3500 /*
3501 * Read current TSSI (BBP 49).
3502 */
3503 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3504
3505 /*
3506 * Compare TSSI value (BBP49) with the compensation boundaries
3507 * from the EEPROM and increase or decrease tx power.
3508 */
3509 for (i = 0; i <= 3; i++) {
3510 if (current_tssi > tssi_bounds[i])
3511 break;
3512 }
3513
3514 if (i == 4) {
3515 for (i = 8; i >= 5; i--) {
3516 if (current_tssi < tssi_bounds[i])
3517 break;
3518 }
3519 }
3520
3521 return (i - 4) * step;
3522}
3523
e90c54b2
RJH		 3524static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3525 enum ieee80211_band band)
3526{
3527 u16 eeprom;
3528 u8 comp_en;
3529 u8 comp_type;
75faae8b 3530 int comp_value = 0;
e90c54b2 3531
3e38d3da 3532 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3533
75faae8b
HS		 3534 /*
3535 * HT40 compensation not required.
3536 */
3537 if (eeprom == 0xffff ||
3538 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3539 return 0;
3540
3541 if (band == IEEE80211_BAND_2GHZ) {
3542 comp_en = rt2x00_get_field16(eeprom,
3543 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3544 if (comp_en) {
3545 comp_type = rt2x00_get_field16(eeprom,
3546 EEPROM_TXPOWER_DELTA_TYPE_2G);
3547 comp_value = rt2x00_get_field16(eeprom,
3548 EEPROM_TXPOWER_DELTA_VALUE_2G);
3549 if (!comp_type)
3550 comp_value = -comp_value;
3551 }
3552 } else {
3553 comp_en = rt2x00_get_field16(eeprom,
3554 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3555 if (comp_en) {
3556 comp_type = rt2x00_get_field16(eeprom,
3557 EEPROM_TXPOWER_DELTA_TYPE_5G);
3558 comp_value = rt2x00_get_field16(eeprom,
3559 EEPROM_TXPOWER_DELTA_VALUE_5G);
3560 if (!comp_type)
3561 comp_value = -comp_value;
3562 }
3563 }
3564
3565 return comp_value;
3566}
3567
1e4cf249
SG		 3568static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3569 int power_level, int max_power)
3570{
3571 int delta;
3572
c429dfef 3573 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3574 return 0;
3575
3576 /*
3577 * XXX: We don't know the maximum transmit power of our hardware since
3578 * the EEPROM doesn't expose it. We only know that we are calibrated
3579 * to 100% tx power.
3580 *
3581 * Hence, we assume the regulatory limit that cfg80211 calulated for
3582 * the current channel is our maximum and if we are requested to lower
3583 * the value we just reduce our tx power accordingly.
3584 */
3585 delta = power_level - max_power;
3586 return min(delta, 0);
3587}
3588
fa71a160
HS		 3589static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3590 enum ieee80211_band band, int power_level,
3591 u8 txpower, int delta)
e90c54b2 3592{
e90c54b2
RJH		 3593 u16 eeprom;
3594 u8 criterion;
3595 u8 eirp_txpower;
3596 u8 eirp_txpower_criterion;
3597 u8 reg_limit;
e90c54b2 3598
34542ff5
GJ		 3599 if (rt2x00_rt(rt2x00dev, RT3593))
3600 return min_t(u8, txpower, 0xc);
3601
c429dfef 3602 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3603 /*
3604 * Check if eirp txpower exceed txpower_limit.
3605 * We use OFDM 6M as criterion and its eirp txpower
3606 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3607 * .11b data rate need add additional 4dbm
3608 * when calculating eirp txpower.
3609 */
022138ca
GJ		 3610 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3611 1, &eeprom);
d9bceaeb
SG		 3612 criterion = rt2x00_get_field16(eeprom,
3613 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3614
3e38d3da 3615 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3616 &eeprom);
e90c54b2
RJH		 3617
3618 if (band == IEEE80211_BAND_2GHZ)
3619 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3620 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3621 else
3622 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3623 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3624
3625 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3626 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3627
3628 reg_limit = (eirp_txpower > power_level) ?
3629 (eirp_txpower - power_level) : 0;
3630 } else
3631 reg_limit = 0;
3632
19f3fa24
SG		 3633 txpower = max(0, txpower + delta - reg_limit);
3634 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3635}
3636
34542ff5
GJ		 3637
3638enum {
3639 TX_PWR_CFG_0_IDX,
3640 TX_PWR_CFG_1_IDX,
3641 TX_PWR_CFG_2_IDX,
3642 TX_PWR_CFG_3_IDX,
3643 TX_PWR_CFG_4_IDX,
3644 TX_PWR_CFG_5_IDX,
3645 TX_PWR_CFG_6_IDX,
3646 TX_PWR_CFG_7_IDX,
3647 TX_PWR_CFG_8_IDX,
3648 TX_PWR_CFG_9_IDX,
3649 TX_PWR_CFG_0_EXT_IDX,
3650 TX_PWR_CFG_1_EXT_IDX,
3651 TX_PWR_CFG_2_EXT_IDX,
3652 TX_PWR_CFG_3_EXT_IDX,
3653 TX_PWR_CFG_4_EXT_IDX,
3654 TX_PWR_CFG_IDX_COUNT,
3655};
3656
3657static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3658 struct ieee80211_channel *chan,
3659 int power_level)
3660{
3661 u8 txpower;
3662 u16 eeprom;
3663 u32 regs[TX_PWR_CFG_IDX_COUNT];
3664 unsigned int offset;
3665 enum ieee80211_band band = chan->band;
3666 int delta;
3667 int i;
3668
3669 memset(regs, '\0', sizeof(regs));
3670
3671 /* TODO: adapt TX power reduction from the rt28xx code */
3672
3673 /* calculate temperature compensation delta */
3674 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3675
3676 if (band == IEEE80211_BAND_5GHZ)
3677 offset = 16;
3678 else
3679 offset = 0;
3680
3681 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3682 offset += 8;
3683
3684 /* read the next four txpower values */
3685 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3686 offset, &eeprom);
3687
3688 /* CCK 1MBS,2MBS */
3689 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3690 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3691 txpower, delta);
3692 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3693 TX_PWR_CFG_0_CCK1_CH0, txpower);
3694 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3695 TX_PWR_CFG_0_CCK1_CH1, txpower);
3696 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3697 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3698
3699 /* CCK 5.5MBS,11MBS */
3700 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3701 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3702 txpower, delta);
3703 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3704 TX_PWR_CFG_0_CCK5_CH0, txpower);
3705 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3706 TX_PWR_CFG_0_CCK5_CH1, txpower);
3707 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3708 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3709
3710 /* OFDM 6MBS,9MBS */
3711 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3712 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3713 txpower, delta);
3714 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3715 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3716 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3717 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3718 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3719 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3720
3721 /* OFDM 12MBS,18MBS */
3722 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3723 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3724 txpower, delta);
3725 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3726 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3727 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3728 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3729 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3730 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3731
3732 /* read the next four txpower values */
3733 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3734 offset + 1, &eeprom);
3735
3736 /* OFDM 24MBS,36MBS */
3737 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3738 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3739 txpower, delta);
3740 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3741 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3742 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3743 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3744 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3745 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3746
3747 /* OFDM 48MBS */
3748 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3749 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3750 txpower, delta);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3752 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3753 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3754 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3755 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3756 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3757
3758 /* OFDM 54MBS */
3759 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3760 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3761 txpower, delta);
3762 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3763 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3765 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3766 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3767 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3768
3769 /* read the next four txpower values */
3770 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3771 offset + 2, &eeprom);
3772
3773 /* MCS 0,1 */
3774 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3775 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3776 txpower, delta);
3777 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3778 TX_PWR_CFG_1_MCS0_CH0, txpower);
3779 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3780 TX_PWR_CFG_1_MCS0_CH1, txpower);
3781 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3782 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3783
3784 /* MCS 2,3 */
3785 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3786 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3787 txpower, delta);
3788 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3789 TX_PWR_CFG_1_MCS2_CH0, txpower);
3790 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3791 TX_PWR_CFG_1_MCS2_CH1, txpower);
3792 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3793 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3794
3795 /* MCS 4,5 */
3796 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3797 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3798 txpower, delta);
3799 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3800 TX_PWR_CFG_2_MCS4_CH0, txpower);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3802 TX_PWR_CFG_2_MCS4_CH1, txpower);
3803 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3804 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3805
3806 /* MCS 6 */
3807 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3808 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3809 txpower, delta);
3810 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3811 TX_PWR_CFG_2_MCS6_CH0, txpower);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3813 TX_PWR_CFG_2_MCS6_CH1, txpower);
3814 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3815 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3816
3817 /* read the next four txpower values */
3818 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3819 offset + 3, &eeprom);
3820
3821 /* MCS 7 */
3822 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3823 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3824 txpower, delta);
3825 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3826 TX_PWR_CFG_7_MCS7_CH0, txpower);
3827 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3828 TX_PWR_CFG_7_MCS7_CH1, txpower);
3829 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3830 TX_PWR_CFG_7_MCS7_CH2, txpower);
3831
3832 /* MCS 8,9 */
3833 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3834 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3835 txpower, delta);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3837 TX_PWR_CFG_2_MCS8_CH0, txpower);
3838 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3839 TX_PWR_CFG_2_MCS8_CH1, txpower);
3840 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3841 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3842
3843 /* MCS 10,11 */
3844 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3845 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3846 txpower, delta);
3847 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3848 TX_PWR_CFG_2_MCS10_CH0, txpower);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3850 TX_PWR_CFG_2_MCS10_CH1, txpower);
3851 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3852 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3853
3854 /* MCS 12,13 */
3855 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3856 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3857 txpower, delta);
3858 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3859 TX_PWR_CFG_3_MCS12_CH0, txpower);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3861 TX_PWR_CFG_3_MCS12_CH1, txpower);
3862 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3863 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3864
3865 /* read the next four txpower values */
3866 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3867 offset + 4, &eeprom);
3868
3869 /* MCS 14 */
3870 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3871 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3872 txpower, delta);
3873 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3874 TX_PWR_CFG_3_MCS14_CH0, txpower);
3875 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3876 TX_PWR_CFG_3_MCS14_CH1, txpower);
3877 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3878 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3879
3880 /* MCS 15 */
3881 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3882 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3883 txpower, delta);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3885 TX_PWR_CFG_8_MCS15_CH0, txpower);
3886 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3887 TX_PWR_CFG_8_MCS15_CH1, txpower);
3888 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3889 TX_PWR_CFG_8_MCS15_CH2, txpower);
3890
3891 /* MCS 16,17 */
3892 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3893 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3894 txpower, delta);
3895 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3896 TX_PWR_CFG_5_MCS16_CH0, txpower);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3898 TX_PWR_CFG_5_MCS16_CH1, txpower);
3899 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3900 TX_PWR_CFG_5_MCS16_CH2, txpower);
3901
3902 /* MCS 18,19 */
3903 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3904 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3905 txpower, delta);
3906 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3907 TX_PWR_CFG_5_MCS18_CH0, txpower);
3908 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3909 TX_PWR_CFG_5_MCS18_CH1, txpower);
3910 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3911 TX_PWR_CFG_5_MCS18_CH2, txpower);
3912
3913 /* read the next four txpower values */
3914 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3915 offset + 5, &eeprom);
3916
3917 /* MCS 20,21 */
3918 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3919 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3920 txpower, delta);
3921 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3922 TX_PWR_CFG_6_MCS20_CH0, txpower);
3923 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3924 TX_PWR_CFG_6_MCS20_CH1, txpower);
3925 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3926 TX_PWR_CFG_6_MCS20_CH2, txpower);
3927
3928 /* MCS 22 */
3929 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3930 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3931 txpower, delta);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3933 TX_PWR_CFG_6_MCS22_CH0, txpower);
3934 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3935 TX_PWR_CFG_6_MCS22_CH1, txpower);
3936 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3937 TX_PWR_CFG_6_MCS22_CH2, txpower);
3938
3939 /* MCS 23 */
3940 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3941 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3942 txpower, delta);
3943 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3944 TX_PWR_CFG_8_MCS23_CH0, txpower);
3945 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3946 TX_PWR_CFG_8_MCS23_CH1, txpower);
3947 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3948 TX_PWR_CFG_8_MCS23_CH2, txpower);
3949
3950 /* read the next four txpower values */
3951 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3952 offset + 6, &eeprom);
3953
3954 /* STBC, MCS 0,1 */
3955 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3956 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3957 txpower, delta);
3958 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3959 TX_PWR_CFG_3_STBC0_CH0, txpower);
3960 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3961 TX_PWR_CFG_3_STBC0_CH1, txpower);
3962 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3963 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3964
3965 /* STBC, MCS 2,3 */
3966 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3967 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3968 txpower, delta);
3969 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3970 TX_PWR_CFG_3_STBC2_CH0, txpower);
3971 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3972 TX_PWR_CFG_3_STBC2_CH1, txpower);
3973 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3974 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3975
3976 /* STBC, MCS 4,5 */
3977 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3978 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3979 txpower, delta);
3980 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3981 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3982 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3983 txpower);
3984
3985 /* STBC, MCS 6 */
3986 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3987 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3988 txpower, delta);
3989 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3990 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3991 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3992 txpower);
3993
3994 /* read the next four txpower values */
3995 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3996 offset + 7, &eeprom);
3997
3998 /* STBC, MCS 7 */
3999 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4000 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4001 txpower, delta);
4002 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4003 TX_PWR_CFG_9_STBC7_CH0, txpower);
4004 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4005 TX_PWR_CFG_9_STBC7_CH1, txpower);
4006 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4007 TX_PWR_CFG_9_STBC7_CH2, txpower);
4008
4009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4017 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4019
4020 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4021 regs[TX_PWR_CFG_0_EXT_IDX]);
4022 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4023 regs[TX_PWR_CFG_1_EXT_IDX]);
4024 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4025 regs[TX_PWR_CFG_2_EXT_IDX]);
4026 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4027 regs[TX_PWR_CFG_3_EXT_IDX]);
4028 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4029 regs[TX_PWR_CFG_4_EXT_IDX]);
4030
4031 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4032 rt2x00_dbg(rt2x00dev,
4033 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4034 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4035 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4036 '4' : '2',
4037 (i > TX_PWR_CFG_9_IDX) ?
4038 (i - TX_PWR_CFG_9_IDX - 1) : i,
4039 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4040 (unsigned long) regs[i]);
4041}
4042
7a66205a
SG		 4043/*
4044 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4045 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4046 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4047 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4048 * Reference per rate transmit power values are located in the EEPROM at
4049 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4050 * current conditions (i.e. band, bandwidth, temperature, user settings).
4051 */
34542ff5
GJ		 4052static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4053 struct ieee80211_channel *chan,
4054 int power_level)
f4450616 4055{
cee2c731 4056 u8 txpower, r1;
5e846004 4057 u16 eeprom;
cee2c731
SG		 4058 u32 reg, offset;
4059 int i, is_rate_b, delta, power_ctrl;
146c3b0c 4060 enum ieee80211_band band = chan->band;
2af242e1
HS		 4061
4062 /*
7a66205a
SG		 4063 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4064 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4065 */
4066 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4067
9e33a355 4068 /*
7a66205a
SG		 4069 * Calculate temperature compensation. Depends on measurement of current
4070 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4071 * to temperature or maybe other factors) is smaller or bigger than
4072 * expected. We adjust it, based on TSSI reference and boundaries values
4073 * provided in EEPROM.
9e33a355
HS		 4074 */
4075 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 4076
1e4cf249 4077 /*
7a66205a
SG		 4078 * Decrease power according to user settings, on devices with unknown
4079 * maximum tx power. For other devices we take user power_level into
4080 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4081 */
4082 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4083 chan->max_power);
4084
5e846004 4085 /*
cee2c731
SG		 4086 * BBP_R1 controls TX power for all rates, it allow to set the following
4087 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4088 *
4089 * TODO: we do not use +6 dBm option to do not increase power beyond
4090 * regulatory limit, however this could be utilized for devices with
4091 * CAPABILITY_POWER_LIMIT.
8c8d2017
SG		 4092 *
4093 * TODO: add different temperature compensation code for RT3290 & RT5390
4094 * to allow to use BBP_R1 for those chips.
4095 */
4096 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4097 !rt2x00_rt(rt2x00dev, RT5390)) {
4098 rt2800_bbp_read(rt2x00dev, 1, &r1);
4099 if (delta <= -12) {
4100 power_ctrl = 2;
4101 delta += 12;
4102 } else if (delta <= -6) {
4103 power_ctrl = 1;
4104 delta += 6;
4105 } else {
4106 power_ctrl = 0;
4107 }
4108 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4109 rt2800_bbp_write(rt2x00dev, 1, r1);
cee2c731 4110 }
8c8d2017 4111
5e846004
HS		 4112 offset = TX_PWR_CFG_0;
4113
4114 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4115 /* just to be safe */
4116 if (offset > TX_PWR_CFG_4)
4117 break;
4118
4119 rt2800_register_read(rt2x00dev, offset, &reg);
4120
4121 /* read the next four txpower values */
022138ca
GJ		 4122 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4123 i, &eeprom);
5e846004 4124
e90c54b2
RJH		 4125 is_rate_b = i ? 0 : 1;
4126 /*
4127 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4128 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4129 * TX_PWR_CFG_4: unknown
4130 */
5e846004
HS		 4131 txpower = rt2x00_get_field16(eeprom,
4132 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4133 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4134 power_level, txpower, delta);
e90c54b2 4135 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4136
e90c54b2
RJH		 4137 /*
4138 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4139 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4140 * TX_PWR_CFG_4: unknown
4141 */
5e846004
HS		 4142 txpower = rt2x00_get_field16(eeprom,
4143 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4144 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4145 power_level, txpower, delta);
e90c54b2 4146 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4147
e90c54b2
RJH		 4148 /*
4149 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4150 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4151 * TX_PWR_CFG_4: unknown
4152 */
5e846004
HS		 4153 txpower = rt2x00_get_field16(eeprom,
4154 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4155 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4156 power_level, txpower, delta);
e90c54b2 4157 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4158
e90c54b2
RJH		 4159 /*
4160 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4161 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4162 * TX_PWR_CFG_4: unknown
4163 */
5e846004
HS		 4164 txpower = rt2x00_get_field16(eeprom,
4165 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4166 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4167 power_level, txpower, delta);
e90c54b2 4168 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4169
4170 /* read the next four txpower values */
022138ca
GJ		 4171 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4172 i + 1, &eeprom);
5e846004 4173
e90c54b2
RJH		 4174 is_rate_b = 0;
4175 /*
4176 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4177 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4178 * TX_PWR_CFG_4: unknown
4179 */
5e846004
HS		 4180 txpower = rt2x00_get_field16(eeprom,
4181 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4182 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4183 power_level, txpower, delta);
e90c54b2 4184 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4185
e90c54b2
RJH		 4186 /*
4187 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4188 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4189 * TX_PWR_CFG_4: unknown
4190 */
5e846004
HS		 4191 txpower = rt2x00_get_field16(eeprom,
4192 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4193 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4194 power_level, txpower, delta);
e90c54b2 4195 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4196
e90c54b2
RJH		 4197 /*
4198 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4199 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4200 * TX_PWR_CFG_4: unknown
4201 */
5e846004
HS		 4202 txpower = rt2x00_get_field16(eeprom,
4203 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4204 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4205 power_level, txpower, delta);
e90c54b2 4206 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4207
e90c54b2
RJH		 4208 /*
4209 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4210 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4211 * TX_PWR_CFG_4: unknown
4212 */
5e846004
HS		 4213 txpower = rt2x00_get_field16(eeprom,
4214 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4215 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4216 power_level, txpower, delta);
e90c54b2 4217 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4218
4219 rt2800_register_write(rt2x00dev, offset, reg);
4220
4221 /* next TX_PWR_CFG register */
4222 offset += 4;
4223 }
f4450616
BZ		 4224}
4225
34542ff5
GJ		 4226static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4227 struct ieee80211_channel *chan,
4228 int power_level)
4229{
4230 if (rt2x00_rt(rt2x00dev, RT3593))
4231 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4232 else
4233 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4234}
4235
9e33a355
HS		 4236void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4237{
675a0b04 4238 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4239 rt2x00dev->tx_power);
4240}
4241EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4242
2e9c43dd
JL		 4243void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4244{
4245 u32 tx_pin;
4246 u8 rfcsr;
4247
4248 /*
4249 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4250 * designed to be controlled in oscillation frequency by a voltage
4251 * input. Maybe the temperature will affect the frequency of
4252 * oscillation to be shifted. The VCO calibration will be called
4253 * periodically to adjust the frequency to be precision.
4254 */
4255
4256 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4257 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4258 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4259
4260 switch (rt2x00dev->chip.rf) {
4261 case RF2020:
4262 case RF3020:
4263 case RF3021:
4264 case RF3022:
4265 case RF3320:
4266 case RF3052:
4267 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4268 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4269 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4270 break;
1095df07 4271 case RF3053:
3b9b74ba 4272 case RF3070:
a89534ed 4273 case RF3290:
ccf91bd6 4274 case RF5360:
2e9c43dd
JL		 4275 case RF5370:
4276 case RF5372:
4277 case RF5390:
cff3d1f0 4278 case RF5392:
2e9c43dd 4279 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4280 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4281 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4282 break;
4283 default:
4284 return;
4285 }
4286
4287 mdelay(1);
4288
4289 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4290 if (rt2x00dev->rf_channel <= 14) {
4291 switch (rt2x00dev->default_ant.tx_chain_num) {
4292 case 3:
4293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4294 /* fall through */
4295 case 2:
4296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4297 /* fall through */
4298 case 1:
4299 default:
4300 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4301 break;
4302 }
4303 } else {
4304 switch (rt2x00dev->default_ant.tx_chain_num) {
4305 case 3:
4306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4307 /* fall through */
4308 case 2:
4309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4310 /* fall through */
4311 case 1:
4312 default:
4313 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4314 break;
4315 }
4316 }
4317 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4318
4319}
4320EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4321
f4450616
BZ		 4322static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4323 struct rt2x00lib_conf *libconf)
4324{
4325 u32 reg;
4326
4327 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4328 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4329 libconf->conf->short_frame_max_tx_count);
4330 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4331 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4332 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4333}
4334
4335static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4336 struct rt2x00lib_conf *libconf)
4337{
4338 enum dev_state state =
4339 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4340 STATE_SLEEP : STATE_AWAKE;
4341 u32 reg;
4342
4343 if (state == STATE_SLEEP) {
4344 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4345
4346 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4347 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4348 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4349 libconf->conf->listen_interval - 1);
4350 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4351 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4352
4353 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4354 } else {
f4450616
BZ		 4355 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4356 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4357 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4358 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4359 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4360
4361 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4362 }
4363}
4364
4365void rt2800_config(struct rt2x00_dev *rt2x00dev,
4366 struct rt2x00lib_conf *libconf,
4367 const unsigned int flags)
4368{
4369 /* Always recalculate LNA gain before changing configuration */
4370 rt2800_config_lna_gain(rt2x00dev, libconf);
4371
e90c54b2 4372 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4373 rt2800_config_channel(rt2x00dev, libconf->conf,
4374 &libconf->rf, &libconf->channel);
675a0b04 4375 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4376 libconf->conf->power_level);
e90c54b2 4377 }
f4450616 4378 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4379 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4380 libconf->conf->power_level);
f4450616
BZ		 4381 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4382 rt2800_config_retry_limit(rt2x00dev, libconf);
4383 if (flags & IEEE80211_CONF_CHANGE_PS)
4384 rt2800_config_ps(rt2x00dev, libconf);
4385}
4386EXPORT_SYMBOL_GPL(rt2800_config);
4387
4388/*
4389 * Link tuning
4390 */
4391void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4392{
4393 u32 reg;
4394
4395 /*
4396 * Update FCS error count from register.
4397 */
4398 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4399 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4400}
4401EXPORT_SYMBOL_GPL(rt2800_link_stats);
4402
4403static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4404{
8c6728b0
GW		 4405 u8 vgc;
4406
f4450616 4407 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 4408 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4409 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4410 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4411 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4412 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4413 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4414 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4415 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4416 rt2x00_rt(rt2x00dev, RT5392) ||
4417 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4418 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4419 else
4420 vgc = 0x2e + rt2x00dev->lna_gain;
4421 } else { /* 5GHZ band */
733aec6a 4422 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4423 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4424 else if (rt2x00_rt(rt2x00dev, RT5592))
4425 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4426 else {
4427 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4428 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4429 else
4430 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4431 }
f4450616
BZ		 4432 }
4433
8c6728b0 4434 return vgc;
f4450616
BZ		 4435}
4436
4437static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4438 struct link_qual *qual, u8 vgc_level)
4439{
4440 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4441 if (rt2x00_rt(rt2x00dev, RT3572) ||
4442 rt2x00_rt(rt2x00dev, RT3593)) {
4443 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4444 vgc_level);
4445 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4446 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4447 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4448 } else {
3d81535e 4449 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4450 }
4451
f4450616
BZ		 4452 qual->vgc_level = vgc_level;
4453 qual->vgc_level_reg = vgc_level;
4454 }
4455}
4456
4457void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4458{
4459 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4460}
4461EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4462
4463void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4464 const u32 count)
4465{
3d81535e
SG		 4466 u8 vgc;
4467
8d0c9b65 4468 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4469 return;
e25aa82a
GJ		 4470
4471 /* When RSSI is better than a certain threshold, increase VGC
4472 * with a chip specific value in order to improve the balance
4473 * between sensibility and noise isolation.
f4450616 4474 */
3d81535e
SG		 4475
4476 vgc = rt2800_get_default_vgc(rt2x00dev);
4477
e25aa82a
GJ		 4478 switch (rt2x00dev->chip.rt) {
4479 case RT3572:
4480 case RT3593:
4481 if (qual->rssi > -65) {
4482 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4483 vgc += 0x20;
4484 else
4485 vgc += 0x10;
4486 }
4487 break;
4488
4489 case RT5592:
0beb1bbf
GJ		 4490 if (qual->rssi > -65)
4491 vgc += 0x20;
e25aa82a
GJ		 4492 break;
4493
4494 default:
0beb1bbf
GJ		 4495 if (qual->rssi > -80)
4496 vgc += 0x10;
e25aa82a 4497 break;
0beb1bbf 4498 }
3d81535e
SG		 4499
4500 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4501}
4502EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4503
4504/*
4505 * Initialization functions.
4506 */
b9a07ae9 4507static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4508{
4509 u32 reg;
d5385bfc 4510 u16 eeprom;
fcf51541 4511 unsigned int i;
e3a896b9 4512 int ret;
fcf51541 4513
f7b395e9 4514 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4515
e3a896b9
GW		 4516 ret = rt2800_drv_init_registers(rt2x00dev);
4517 if (ret)
4518 return ret;
fcf51541
BZ		 4519
4520 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
634b8059
GJ		 4521 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4522 rt2800_get_beacon_offset(rt2x00dev, 0));
4523 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4524 rt2800_get_beacon_offset(rt2x00dev, 1));
4525 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4526 rt2800_get_beacon_offset(rt2x00dev, 2));
4527 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4528 rt2800_get_beacon_offset(rt2x00dev, 3));
fcf51541
BZ		 4529 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4530
4531 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
634b8059
GJ		 4532 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4533 rt2800_get_beacon_offset(rt2x00dev, 4));
4534 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4535 rt2800_get_beacon_offset(rt2x00dev, 5));
4536 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4537 rt2800_get_beacon_offset(rt2x00dev, 6));
4538 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4539 rt2800_get_beacon_offset(rt2x00dev, 7));
fcf51541
BZ		 4540 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4541
4542 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4543 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4544
4545 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4546
4547 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4548 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4549 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4550 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4551 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4552 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4553 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4554 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4555
a9dce149
GW		 4556 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4557
4558 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4559 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4560 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4561 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4562
a89534ed
WH		 4563 if (rt2x00_rt(rt2x00dev, RT3290)) {
4564 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4565 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4566 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4567 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4568 }
4569
4570 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4571 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4572 rt2x00_set_field32(&reg, LDO0_EN, 1);
4573 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4574 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4575 }
4576
4577 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4578 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4579 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4580 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4581 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4582
4583 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4584 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4585 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4586
4587 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4588 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4589 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4590 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4591 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4592 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4593
4594 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4595 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4596 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4597 }
4598
64522957 4599 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4600 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4601 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4602 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4603
4604 if (rt2x00_rt(rt2x00dev, RT3290))
4605 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4606 0x00000404);
4607 else
4608 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4609 0x00000400);
4610
fcf51541 4611 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4612 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4613 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4614 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4615 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4616 &eeprom);
38c8a566 4617 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4618 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4619 0x0000002c);
4620 else
4621 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4622 0x0000000f);
4623 } else {
4624 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4625 }
d5385bfc 4626 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4627 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4628
4629 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4630 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4631 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4632 } else {
4633 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4634 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4635 }
c295a81d
HS		 4636 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4637 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4638 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4639 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4640 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4641 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4642 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4643 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4644 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4645 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4646 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4647 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4648 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4649 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4650 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4651 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4652 &eeprom);
4653 if (rt2x00_get_field16(eeprom,
4654 EEPROM_NIC_CONF1_DAC_TEST))
4655 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4656 0x0000001f);
4657 else
4658 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4659 0x0000000f);
4660 } else {
4661 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4662 0x00000000);
4663 }
2ed71884 4664 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4665 rt2x00_rt(rt2x00dev, RT5392) ||
4666 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4667 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4668 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4669 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4670 } else {
4671 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4672 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4673 }
4674
4675 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4676 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4677 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4678 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4679 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4680 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4681 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4682 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4683 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4684 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4685
4686 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4687 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4688 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4689 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4690 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4691
4692 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4693 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4694 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4695 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4696 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4697 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4698 else
4699 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4700 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4701 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4702 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4703
a9dce149
GW		 4704 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4705 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4706 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4707 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4708 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4709 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4710 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4711 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4712 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4713
fcf51541
BZ		 4714 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4715
a9dce149
GW		 4716 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4717 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4718 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4719 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4720 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4721 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4722 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4723 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4724
fcf51541
BZ		 4725 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4726 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4727 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4729 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4730 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4731 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4732 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4733 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4734
4735 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4736 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4737 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4738 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4739 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4740 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4741 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4742 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4743 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4744 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4745 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4746 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4747
4748 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4749 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4750 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4751 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4752 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4753 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4754 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4755 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4756 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4757 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4758 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4759 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4760
4761 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4762 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4763 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4764 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4765 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4766 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4767 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4768 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4769 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4770 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4771 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4772 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4773
4774 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4775 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4776 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4777 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4778 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4779 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4780 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4781 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4782 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4783 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4784 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4785 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4786
4787 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4788 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4789 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4790 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4791 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4792 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4793 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4794 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4795 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4796 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4797 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4798 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4799
4800 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4801 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4802 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4803 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4804 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4805 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4806 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4807 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4808 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4809 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4810 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4811 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4812
cea90e55 4813 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4814 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4815
4816 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4817 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4818 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4819 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4820 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4821 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4822 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4823 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4824 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4825 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4826 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4827 }
4828
961621ab
HS		 4829 /*
4830 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4831 * although it is reserved.
4832 */
4833 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4834 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4835 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4836 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4837 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4838 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4839 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4840 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4841 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4842 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4843 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4844 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4845
7641328d
SG		 4846 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4847 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4848
4849 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4850 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4851 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4852 IEEE80211_MAX_RTS_THRESHOLD);
4853 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4854 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4855
4856 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4857
a21c2ab4
HS		 4858 /*
4859 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4860 * time should be set to 16. However, the original Ralink driver uses
4861 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4862 * connection problems with 11g + CTS protection. Hence, use the same
4863 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4864 */
a9dce149 4865 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4866 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4867 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4868 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4869 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4870 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4871 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4872
fcf51541
BZ		 4873 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4874
4875 /*
4876 * ASIC will keep garbage value after boot, clear encryption keys.
4877 */
4878 for (i = 0; i < 4; i++)
4879 rt2800_register_write(rt2x00dev,
4880 SHARED_KEY_MODE_ENTRY(i), 0);
4881
4882 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4883 rt2800_config_wcid(rt2x00dev, NULL, i);
4884 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4885 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4886 }
4887
4888 /*
4889 * Clear all beacons
fcf51541 4890 */
77f7c0f3
GJ		 4891 for (i = 0; i < 8; i++)
4892 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4893
cea90e55 4894 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4895 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4896 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4897 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4898 } else if (rt2x00_is_pcie(rt2x00dev)) {
4899 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4900 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4901 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4902 }
4903
4904 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4905 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4906 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4907 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4908 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4909 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4910 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4911 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4912 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4913 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4914
4915 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4916 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4917 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4918 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4919 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4920 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4921 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4922 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4923 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4924 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4925
4926 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4927 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4928 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4929 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4930 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4931 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4932 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4933 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4934 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4935 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4936
4937 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4938 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4939 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4940 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4941 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4942 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4943
47ee3eb1
HS		 4944 /*
4945 * Do not force the BA window size, we use the TXWI to set it
4946 */
4947 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4948 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4949 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4950 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4951
fcf51541
BZ		 4952 /*
4953 * We must clear the error counters.
4954 * These registers are cleared on read,
4955 * so we may pass a useless variable to store the value.
4956 */
4957 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4958 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4959 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4960 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4961 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4962 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4963
9f926fb5
HS		 4964 /*
4965 * Setup leadtime for pre tbtt interrupt to 6ms
4966 */
4967 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4968 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4969 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4970
977206d7
HS		 4971 /*
4972 * Set up channel statistics timer
4973 */
4974 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4975 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4976 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4977 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4978 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4979 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4980 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4981
fcf51541
BZ		 4982 return 0;
4983}
fcf51541
BZ		 4984
4985static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4986{
4987 unsigned int i;
4988 u32 reg;
4989
4990 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4991 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4992 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4993 return 0;
4994
4995 udelay(REGISTER_BUSY_DELAY);
4996 }
4997
ec9c4989 4998 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 4999 return -EACCES;
5000}
5001
5002static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5003{
5004 unsigned int i;
5005 u8 value;
5006
5007 /*
5008 * BBP was enabled after firmware was loaded,
5009 * but we need to reactivate it now.
5010 */
5011 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5012 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5013 msleep(1);
5014
5015 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5016 rt2800_bbp_read(rt2x00dev, 0, &value);
5017 if ((value != 0xff) && (value != 0x00))
5018 return 0;
5019 udelay(REGISTER_BUSY_DELAY);
5020 }
5021
ec9c4989 5022 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5023 return -EACCES;
5024}
5025
a7bbbe5c
SG		 5026static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5027{
5028 u8 value;
5029
5030 rt2800_bbp_read(rt2x00dev, 4, &value);
5031 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5032 rt2800_bbp_write(rt2x00dev, 4, value);
5033}
5034
c2675487
SG		 5035static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5036{
5037 rt2800_bbp_write(rt2x00dev, 142, 1);
5038 rt2800_bbp_write(rt2x00dev, 143, 57);
5039}
5040
a7bbbe5c
SG		 5041static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5042{
5043 const u8 glrt_table[] = {
5044 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5045 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5046 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5047 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5048 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5049 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5051 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5052 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5053 };
5054 int i;
5055
5056 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5057 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5058 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5059 }
5060};
5061
624708b8 5062static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5063{
5064 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5065 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5066 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5067 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5068 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5069 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5070 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5071 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5072 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5073 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5074 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5075 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5076 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5077 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5078 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5079 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5080}
5081
5df1ff3a
SG		 5082static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5083{
5084 u16 eeprom;
5085 u8 value;
5086
5087 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5088 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5089 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5090 value |= 0x20;
5091 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5092 value &= ~0x02;
5093 rt2800_bbp_write(rt2x00dev, 138, value);
5094}
5095
dae62957
SG		 5096static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5097{
b2f8e0bd 5098 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5099
5100 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5101 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5102
5103 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5104 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5105
5106 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5107
5108 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5109 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5110
5111 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5112
5113 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5114
5115 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5116
5117 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5118
5119 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5120
5121 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5122
5123 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5124
5125 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5126
5127 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5128}
5129
39ab3e8b
SG		 5130static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5131{
e379de12
SG		 5132 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5133 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5134
5135 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5136 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5137 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5138 } else {
5139 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5140 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5141 }
8d97be38
SG		 5142
5143 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5144
5145 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5146
5147 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5148
5149 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5150
5151 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5152 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5153 else
5154 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5155
5156 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5157
5158 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5159
5160 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5161
5162 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5163
5164 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5165
5166 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5167}
5168
5169static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5170{
e379de12
SG		 5171 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5172 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5173
5174 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5175 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5176
5177 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5178
5179 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5180 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5181 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5182
5183 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5184
5185 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5186
5187 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5188
5189 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5190
5191 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5192
5193 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5194
5195 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5196 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5197 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5198 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5199 else
5200 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5201
5202 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5203
5204 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5205
5206 if (rt2x00_rt(rt2x00dev, RT3071) ||
5207 rt2x00_rt(rt2x00dev, RT3090))
5208 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5209}
5210
5211static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5212{
6addb24e
SG		 5213 u8 value;
5214
c3223573 5215 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5216
5217 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5218
5219 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5220 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5221
5222 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5223
5224 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5225 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5226 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5227 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5228
5229 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5230
5231 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5232
5233 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5234 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5235 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5236 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5237
5238 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5239
5240 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5241
5242 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5243
5244 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5245
5246 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5247
5248 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5249
5250 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5251
5252 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5253
5254 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5255
5256 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5257
5258 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5259
5260 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5261 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5262 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5263 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5264 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5265 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5266 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5267 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5268 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5269 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5270
5271 rt2800_bbp_read(rt2x00dev, 47, &value);
5272 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5273 rt2800_bbp_write(rt2x00dev, 47, value);
5274
5275 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5276 rt2800_bbp_read(rt2x00dev, 3, &value);
5277 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5278 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5279 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5280}
5281
5282static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5283{
29f3a58b
SG		 5284 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5285 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5286
5287 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5288
5289 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5290
5291 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5292 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5293
5294 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5295
5296 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5297 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5298 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5299 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5300
5301 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5302
5303 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5304
5305 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5306 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5307 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5308
5309 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5310
5311 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5312
5313 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5314
5315 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5316
5317 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5318
5319 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5320
5321 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5322
5323 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5324
5325 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5326
5327 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5328
5329 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5330
5331 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5332
5333 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5334
5335 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5336 /* Set ITxBF timeout to 0x9c40=1000msec */
5337 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5338 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5339 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5340 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5341 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5342 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5343 /* Reprogram the inband interface to put right values in RXWI */
5344 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5345 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5346 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5347 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5348 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5349 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5350 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5351 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5352
5353 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5354}
5355
5356static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5357{
e379de12
SG		 5358 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5359 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5360
5361 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5362 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5363
5364 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5365
5366 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5367 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5368 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5369
5370 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5371
5372 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5373
5374 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5375
5376 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5377
5378 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5379
5380 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5381
5382 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5383 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5384 else
5385 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5386
5387 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5388
5389 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5390
5391 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5392}
5393
5394static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5395{
b2f8e0bd 5396 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5397
5398 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5399 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5400
5401 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5402 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5403
5404 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5405
5406 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5407 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5408 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5409
5410 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5411
5412 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5413
5414 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5415
5416 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5417
5418 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5419
5420 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5421
5422 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5423
5424 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5425
5426 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5427
5428 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5429}
5430
b189a181
GJ		 5431static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5432{
5433 rt2800_init_bbp_early(rt2x00dev);
5434
5435 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5436 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5437 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5438 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5439
5440 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5441
5442 /* Enable DC filter */
5443 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5444 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5445}
5446
39ab3e8b
SG		 5447static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5448{
32ef8f49
SG		 5449 int ant, div_mode;
5450 u16 eeprom;
5451 u8 value;
5452
c3223573 5453 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5454
5455 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5456
5457 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5458 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5459
5460 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5461
58422191 5462 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5463 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5464 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5465 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5466
5467 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5468
58422191
SG		 5469 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5470
43f535e2
SG		 5471 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5472 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5473 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5474
5475 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5476
5477 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5478
5479 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5480
5481 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5482
5483 if (rt2x00_rt(rt2x00dev, RT5392))
5484 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5485
5486 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5487
5488 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5489
5490 if (rt2x00_rt(rt2x00dev, RT5392)) {
5491 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5492 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5493 }
672d1188
SG		 5494
5495 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5496
5497 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5498
5499 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5500
5501 if (rt2x00_rt(rt2x00dev, RT5390))
5502 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5503 else if (rt2x00_rt(rt2x00dev, RT5392))
5504 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5505 else
5506 WARN_ON(1);
f2b6777c
SG		 5507
5508 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5509
5510 if (rt2x00_rt(rt2x00dev, RT5392)) {
5511 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5512 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5513 }
5df1ff3a
SG		 5514
5515 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5516
3e38d3da 5517 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5518 div_mode = rt2x00_get_field16(eeprom,
5519 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5520 ant = (div_mode == 3) ? 1 : 0;
5521
5522 /* check if this is a Bluetooth combo card */
c429dfef 5523 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5524 u32 reg;
5525
5526 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5527 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5528 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5529 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5530 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5531 if (ant == 0)
5532 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5533 else if (ant == 1)
5534 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5535 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5536 }
5537
5538 /* This chip has hardware antenna diversity*/
5539 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5540 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5541 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5542 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5543 }
5544
5545 rt2800_bbp_read(rt2x00dev, 152, &value);
5546 if (ant == 0)
5547 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5548 else
5549 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5550 rt2800_bbp_write(rt2x00dev, 152, value);
5551
5552 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5553}
5554
a7bbbe5c
SG		 5555static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5556{
5557 int ant, div_mode;
5558 u16 eeprom;
5559 u8 value;
5560
624708b8 5561 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5562
a7bbbe5c
SG		 5563 rt2800_bbp_read(rt2x00dev, 105, &value);
5564 rt2x00_set_field8(&value, BBP105_MLD,
5565 rt2x00dev->default_ant.rx_chain_num == 2);
5566 rt2800_bbp_write(rt2x00dev, 105, value);
5567
5568 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5569
5570 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5571 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5572 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5573 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5574 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5575 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5576 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5577 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5578 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5579 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5580 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5581 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5582 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5583 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5584 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5585 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5586 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5587 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5588 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5589 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5590 /* FIXME BBP105 owerwrite */
5591 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5592 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5593 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5594 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5595 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5596 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5597
5598 /* Initialize GLRT (Generalized Likehood Radio Test) */
5599 rt2800_init_bbp_5592_glrt(rt2x00dev);
5600
5601 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5602
3e38d3da 5603 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5604 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5605 ant = (div_mode == 3) ? 1 : 0;
5606 rt2800_bbp_read(rt2x00dev, 152, &value);
5607 if (ant == 0) {
5608 /* Main antenna */
5609 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5610 } else {
5611 /* Auxiliary antenna */
5612 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5613 }
5614 rt2800_bbp_write(rt2x00dev, 152, value);
5615
5616 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5617 rt2800_bbp_read(rt2x00dev, 254, &value);
5618 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5619 rt2800_bbp_write(rt2x00dev, 254, value);
5620 }
5621
c2675487
SG		 5622 rt2800_init_freq_calibration(rt2x00dev);
5623
a7bbbe5c 5624 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5625 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5626 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5627}
5628
a1ef5039 5629static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5630{
5631 unsigned int i;
5632 u16 eeprom;
5633 u8 reg_id;
5634 u8 value;
5635
dae62957
SG		 5636 if (rt2800_is_305x_soc(rt2x00dev))
5637 rt2800_init_bbp_305x_soc(rt2x00dev);
5638
39ab3e8b
SG		 5639 switch (rt2x00dev->chip.rt) {
5640 case RT2860:
5641 case RT2872:
5642 case RT2883:
5643 rt2800_init_bbp_28xx(rt2x00dev);
5644 break;
5645 case RT3070:
5646 case RT3071:
5647 case RT3090:
5648 rt2800_init_bbp_30xx(rt2x00dev);
5649 break;
5650 case RT3290:
5651 rt2800_init_bbp_3290(rt2x00dev);
5652 break;
5653 case RT3352:
5654 rt2800_init_bbp_3352(rt2x00dev);
5655 break;
5656 case RT3390:
5657 rt2800_init_bbp_3390(rt2x00dev);
5658 break;
5659 case RT3572:
5660 rt2800_init_bbp_3572(rt2x00dev);
5661 break;
b189a181
GJ		 5662 case RT3593:
5663 rt2800_init_bbp_3593(rt2x00dev);
5664 return;
39ab3e8b
SG		 5665 case RT5390:
5666 case RT5392:
5667 rt2800_init_bbp_53xx(rt2x00dev);
5668 break;
5669 case RT5592:
a7bbbe5c 5670 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5671 return;
a7bbbe5c
SG		 5672 }
5673
fcf51541 5674 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5675 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5676 &eeprom);
fcf51541
BZ		 5677
5678 if (eeprom != 0xffff && eeprom != 0x0000) {
5679 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5680 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5681 rt2800_bbp_write(rt2x00dev, reg_id, value);
5682 }
5683 }
fcf51541 5684}
fcf51541 5685
d9517f2f
SG		 5686static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5687{
5688 u32 reg;
5689
5690 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5691 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5692 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5693}
5694
c5b3c350
SG		 5695static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5696 u8 filter_target)
fcf51541
BZ		 5697{
5698 unsigned int i;
5699 u8 bbp;
5700 u8 rfcsr;
5701 u8 passband;
5702 u8 stopband;
5703 u8 overtuned = 0;
c5b3c350 5704 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5705
5706 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5707
5708 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5709 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5710 rt2800_bbp_write(rt2x00dev, 4, bbp);
5711
80d184e6
RJH		 5712 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5713 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5714 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5715
fcf51541
BZ		 5716 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5717 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5718 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5719
5720 /*
5721 * Set power & frequency of passband test tone
5722 */
5723 rt2800_bbp_write(rt2x00dev, 24, 0);
5724
5725 for (i = 0; i < 100; i++) {
5726 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5727 msleep(1);
5728
5729 rt2800_bbp_read(rt2x00dev, 55, &passband);
5730 if (passband)
5731 break;
5732 }
5733
5734 /*
5735 * Set power & frequency of stopband test tone
5736 */
5737 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5738
5739 for (i = 0; i < 100; i++) {
5740 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5741 msleep(1);
5742
5743 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5744
5745 if ((passband - stopband) <= filter_target) {
5746 rfcsr24++;
5747 overtuned += ((passband - stopband) == filter_target);
5748 } else
5749 break;
5750
5751 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5752 }
5753
5754 rfcsr24 -= !!overtuned;
5755
5756 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5757 return rfcsr24;
5758}
5759
ce94ede9
SG		 5760static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5761 const unsigned int rf_reg)
5762{
5763 u8 rfcsr;
5764
5765 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5766 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5767 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5768 msleep(1);
5769 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5770 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5771}
5772
c5b3c350
SG		 5773static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5774{
5775 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5776 u8 filter_tgt_bw20;
5777 u8 filter_tgt_bw40;
5778 u8 rfcsr, bbp;
5779
5780 /*
5781 * TODO: sync filter_tgt values with vendor driver
5782 */
5783 if (rt2x00_rt(rt2x00dev, RT3070)) {
5784 filter_tgt_bw20 = 0x16;
5785 filter_tgt_bw40 = 0x19;
5786 } else {
5787 filter_tgt_bw20 = 0x13;
5788 filter_tgt_bw40 = 0x15;
5789 }
5790
5791 drv_data->calibration_bw20 =
5792 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5793 drv_data->calibration_bw40 =
5794 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5795
5796 /*
5797 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5798 */
5799 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5800 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5801
5802 /*
5803 * Set back to initial state
5804 */
5805 rt2800_bbp_write(rt2x00dev, 24, 0);
5806
5807 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5808 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5809 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5810
5811 /*
5812 * Set BBP back to BW20
5813 */
5814 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5815 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5816 rt2800_bbp_write(rt2x00dev, 4, bbp);
5817}
5818
da8064c2
SG		 5819static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5820{
5821 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5822 u8 min_gain, rfcsr, bbp;
5823 u16 eeprom;
5824
5825 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5826
5827 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5828 if (rt2x00_rt(rt2x00dev, RT3070) ||
5829 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5830 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5831 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5832 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5833 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5834 }
5835
5836 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5837 if (drv_data->txmixer_gain_24g >= min_gain) {
5838 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5839 drv_data->txmixer_gain_24g);
5840 }
5841
5842 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5843
5844 if (rt2x00_rt(rt2x00dev, RT3090)) {
5845 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5846 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5847 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5848 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5849 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5850 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5851 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5852 rt2800_bbp_write(rt2x00dev, 138, bbp);
5853 }
5854
5855 if (rt2x00_rt(rt2x00dev, RT3070)) {
5856 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5857 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5858 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5859 else
5860 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5861 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5862 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5863 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5864 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5865 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5866 rt2x00_rt(rt2x00dev, RT3090) ||
5867 rt2x00_rt(rt2x00dev, RT3390)) {
5868 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5869 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5870 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5871 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5872 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5873 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5874 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5875
5876 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5877 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5878 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5879
5880 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5881 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5882 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5883
5884 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5885 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5886 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5887 }
5888}
5889
ab7078ac
GJ		 5890static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5891{
5892 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5893 u8 rfcsr;
5894 u8 tx_gain;
5895
5896 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5897 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5898 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5899
5900 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5901 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5902 RFCSR17_TXMIXER_GAIN);
5903 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5904 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5905
5906 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5907 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5908 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5909
5910 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5911 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5912 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5913
5914 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5915 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5916 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5917 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5918
5919 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5920 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5921 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5922
5923 /* TODO: enable stream mode */
5924}
5925
f7df8fe5
SG		 5926static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5927{
5928 u8 reg;
5929 u16 eeprom;
5930
5931 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5932 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5933 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5934 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5935 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5936 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5937 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5938 rt2800_bbp_write(rt2x00dev, 138, reg);
5939
5940 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5941 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5942 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5943
5944 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5945 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5946 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5947
5948 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5949
5950 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5951 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5952 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5953}
5954
d5374ef1
SG		 5955static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5956{
ce94ede9
SG		 5957 rt2800_rf_init_calibration(rt2x00dev, 30);
5958
d5374ef1
SG		 5959 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5960 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5961 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5962 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5963 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5964 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5965 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5966 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5967 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5968 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5969 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5970 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5971 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5972 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5973 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5974 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5975 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5976 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5977 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5978 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5979 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5980 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5981 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5982 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5983 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5984 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5985 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5986 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5987 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5988 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5989 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5990 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5991}
5992
5993static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5994{
c9a221b2
SG		 5995 u8 rfcsr;
5996 u16 eeprom;
5997 u32 reg;
5998
ce94ede9
SG		 5999 /* XXX vendor driver do this only for 3070 */
6000 rt2800_rf_init_calibration(rt2x00dev, 30);
6001
d5374ef1
SG		 6002 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6003 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6004 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6005 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6006 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6007 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6008 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6009 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6010 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6011 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6012 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6013 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6014 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6015 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6016 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6017 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6018 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6019 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6020 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6021
6022 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6023 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6024 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6025 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6026 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6027 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6028 rt2x00_rt(rt2x00dev, RT3090)) {
6029 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6030
6031 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6032 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6033 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6034
6035 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6036 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6037 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6038 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6039 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6040 &eeprom);
c9a221b2
SG		 6041 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6042 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6043 else
6044 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6045 }
6046 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6047
6048 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6049 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6050 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6051 }
c5b3c350
SG		 6052
6053 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6054
6055 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6056 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6057 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6058 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6059
6060 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6061 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6062}
6063
6064static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6065{
f9cdcbb1
SG		 6066 u8 rfcsr;
6067
ce94ede9
SG		 6068 rt2800_rf_init_calibration(rt2x00dev, 2);
6069
d5374ef1
SG		 6070 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6071 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6072 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6073 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6074 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6075 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6076 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6077 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6078 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6079 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6080 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6081 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6082 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6083 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6084 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6085 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6086 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6087 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6088 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6089 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6090 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6091 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6092 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6093 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6094 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6095 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6096 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6097 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6098 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6099 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6100 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6101 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6102 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6103 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6104 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6105 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6106 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6107 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6108 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6109 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6110 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6111 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6112 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6113 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6114 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6115 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6116
6117 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6118 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6119 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6120
6121 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6122 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6123}
6124
6125static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6126{
ce94ede9
SG		 6127 rt2800_rf_init_calibration(rt2x00dev, 30);
6128
d5374ef1
SG		 6129 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6130 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6131 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6132 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6133 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6134 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6135 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6136 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6137 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6138 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6139 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6140 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6141 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6142 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6143 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6144 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6145 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6146 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6147 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6148 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6149 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6150 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6151 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6152 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6154 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6155 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6156 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6157 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6158 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6159 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6160 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6161 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6162 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6163 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6164 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6165 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6166 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6167 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6168 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6169 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6170 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6171 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6172 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6173 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6174 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6175 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6176 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6177 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6178 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6179 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6180 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6181 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6182 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6183 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6184 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6185 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6186 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6187 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6188 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6189 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6190 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6191 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6192
6193 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6194 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6195 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6196}
6197
6198static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6199{
2971e66f
SG		 6200 u32 reg;
6201
ce94ede9
SG		 6202 rt2800_rf_init_calibration(rt2x00dev, 30);
6203
d5374ef1
SG		 6204 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6205 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6206 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6207 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6208 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6209 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6210 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6211 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6212 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6213 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6214 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6215 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6216 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6217 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6218 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6219 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6220 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6221 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6222 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6223 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6224 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6225 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6226 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6227 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6228 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6229 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6230 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6231 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6232 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6233 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6234 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6235 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6236
6237 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6238 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6239 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6240
6241 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6242
6243 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6244 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6245
6246 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6247 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6248}
6249
6250static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6251{
87d91db9
SG		 6252 u8 rfcsr;
6253 u32 reg;
6254
ce94ede9
SG		 6255 rt2800_rf_init_calibration(rt2x00dev, 30);
6256
d5374ef1
SG		 6257 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6258 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6259 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6260 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6261 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6262 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6263 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6264 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6265 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6266 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6267 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6268 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6269 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6270 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6271 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6272 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6273 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6274 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6275 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6276 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6277 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6278 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6279 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6280 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6281 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6282 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6283 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6284 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6285 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6286 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6287 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6288
6289 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6290 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6291 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6292
6293 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6294 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6295 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6296 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6297 msleep(1);
6298 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6299 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6300 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6301 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6302
6303 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6304 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6305 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6306}
6307
d63f7e8c
GJ		 6308static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6309{
6310 u8 bbp;
6311 bool txbf_enabled = false; /* FIXME */
6312
6313 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6314 if (rt2x00dev->default_ant.rx_chain_num == 1)
6315 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6316 else
6317 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6318 rt2800_bbp_write(rt2x00dev, 105, bbp);
6319
6320 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6321
6322 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6323 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6324 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6325 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6326 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6327 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6328 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6329 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6330
6331 if (txbf_enabled)
6332 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6333 else
6334 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6335
6336 /* SNR mapping */
6337 rt2800_bbp_write(rt2x00dev, 142, 6);
6338 rt2800_bbp_write(rt2x00dev, 143, 160);
6339 rt2800_bbp_write(rt2x00dev, 142, 7);
6340 rt2800_bbp_write(rt2x00dev, 143, 161);
6341 rt2800_bbp_write(rt2x00dev, 142, 8);
6342 rt2800_bbp_write(rt2x00dev, 143, 162);
6343
6344 /* ADC/DAC control */
6345 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6346
6347 /* RX AGC energy lower bound in log2 */
6348 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6349
6350 /* FIXME: BBP 105 owerwrite? */
6351 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6352
d63f7e8c
GJ		 6353}
6354
ab7078ac
GJ		 6355static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6356{
6357 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6358 u32 reg;
6359 u8 rfcsr;
6360
6361 /* Disable GPIO #4 and #7 function for LAN PE control */
6362 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6363 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6364 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6365 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6366
6367 /* Initialize default register values */
6368 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6369 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6370 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6371 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6372 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6373 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6374 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6375 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6376 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6377 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6378 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6379 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6380 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6381 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6382 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6383 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6384 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6385 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6386 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6387 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6388 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6389 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6390 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6391 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6392 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6393 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6394 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6395 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6396 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6397 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6398 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6399 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6400
6401 /* Initiate calibration */
6402 /* TODO: use rt2800_rf_init_calibration ? */
6403 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6404 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6405 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6406
6407 rt2800_adjust_freq_offset(rt2x00dev);
6408
6409 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6410 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6411 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6412
6413 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6414 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6415 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6416 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6417 usleep_range(1000, 1500);
6418 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6419 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6420 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6421
6422 /* Set initial values for RX filter calibration */
6423 drv_data->calibration_bw20 = 0x1f;
6424 drv_data->calibration_bw40 = 0x2f;
6425
6426 /* Save BBP 25 & 26 values for later use in channel switching */
6427 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6428 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6429
6430 rt2800_led_open_drain_enable(rt2x00dev);
6431 rt2800_normal_mode_setup_3593(rt2x00dev);
6432
d63f7e8c 6433 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6434
6435 /* TODO: enable stream mode support */
6436}
6437
d5374ef1
SG		 6438static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6439{
ce94ede9
SG		 6440 rt2800_rf_init_calibration(rt2x00dev, 2);
6441
d5374ef1
SG		 6442 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6443 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6444 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6445 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6446 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6447 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6448 else
6449 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6450 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6451 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6452 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6453 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6454 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6455 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6456 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6457 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6458 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6459 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6460
6461 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6462 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6463 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6464 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6465 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6466 if (rt2x00_is_usb(rt2x00dev) &&
6467 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6468 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6469 else
6470 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6471 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6472 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6473 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6474 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6475
7122e660 6476 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6477 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6478 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6479 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6480 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6481 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6482 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6483 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6484 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6485 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6486
c8520bcb 6487 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6488 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6489 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6490 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6491 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6492 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6493 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6494 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6495 else
6496 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6497 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6498 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6499 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6500
6501 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6502 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6503 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6504 else
6505 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6506 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6507 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6508 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6509 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6510 else
6511 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6512 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6513 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6514 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6515
6516 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6517 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6518 if (rt2x00_is_usb(rt2x00dev))
6519 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6520 else
6521 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6522 } else {
6523 if (rt2x00_is_usb(rt2x00dev))
6524 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6525 else
6526 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6527 }
d5374ef1
SG		 6528 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6529 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6530
6531 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6532
6533 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6534}
6535
6536static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6537{
ce94ede9
SG		 6538 rt2800_rf_init_calibration(rt2x00dev, 2);
6539
d5374ef1 6540 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6541 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6542 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6543 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6544 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6545 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6546 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6547 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6548 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6549 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6550 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6551 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6552 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6553 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6554 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6555 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6556 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6557 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6558 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6559 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6560 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6561 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6562 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6563 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6564 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6565 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6566 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6567 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6568 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6569 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6570 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6571 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6572 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6573 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6574 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6575 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6576 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6577 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6578 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6579 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6580 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6581 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6582 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6583 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6584 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6585 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6586 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6587 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6588 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6589 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6590 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6591 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6592 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6593 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6594 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6595 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6596 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6597 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6598
6599 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6600
6601 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6602}
6603
0c9e5fb9
SG		 6604static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6605{
ce94ede9
SG		 6606 rt2800_rf_init_calibration(rt2x00dev, 30);
6607
0c9e5fb9
SG		 6608 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6609 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6610 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6611 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6612 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6613 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6614 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6615 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6616 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6617 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6618 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6619 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6620 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6621 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6622 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6623 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6624 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6625 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6626 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6627 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6628 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6629
6630 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6631 msleep(1);
6632
6633 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6634
c630ccf1
SG		 6635 /* Enable DC filter */
6636 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6637 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6638
f7df8fe5 6639 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6640
6641 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6642 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6643
6644 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6645}
6646
074f2529 6647static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6648{
d5374ef1
SG		 6649 if (rt2800_is_305x_soc(rt2x00dev)) {
6650 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6651 return;
d5374ef1
SG		 6652 }
6653
6654 switch (rt2x00dev->chip.rt) {
6655 case RT3070:
6656 case RT3071:
6657 case RT3090:
6658 rt2800_init_rfcsr_30xx(rt2x00dev);
6659 break;
6660 case RT3290:
6661 rt2800_init_rfcsr_3290(rt2x00dev);
6662 break;
6663 case RT3352:
6664 rt2800_init_rfcsr_3352(rt2x00dev);
6665 break;
6666 case RT3390:
6667 rt2800_init_rfcsr_3390(rt2x00dev);
6668 break;
6669 case RT3572:
6670 rt2800_init_rfcsr_3572(rt2x00dev);
6671 break;
ab7078ac
GJ		 6672 case RT3593:
6673 rt2800_init_rfcsr_3593(rt2x00dev);
6674 break;
d5374ef1
SG		 6675 case RT5390:
6676 rt2800_init_rfcsr_5390(rt2x00dev);
6677 break;
6678 case RT5392:
6679 rt2800_init_rfcsr_5392(rt2x00dev);
6680 break;
0c9e5fb9
SG		 6681 case RT5592:
6682 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6683 break;
8cdd15e0 6684 }
fcf51541 6685}
b9a07ae9
ID		 6686
6687int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6688{
6689 u32 reg;
6690 u16 word;
6691
6692 /*
61edc7fa 6693 * Initialize MAC registers.
b9a07ae9
ID		 6694 */
6695 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6696 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6697 return -EIO;
6698
61edc7fa
SG		 6699 /*
6700 * Wait BBP/RF to wake up.
6701 */
f4e1a4d3
SG		 6702 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6703 return -EIO;
6704
b9a07ae9 6705 /*
61edc7fa 6706 * Send signal during boot time to initialize firmware.
b9a07ae9 6707 */
c630ccf1
SG		 6708 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6709 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6710 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6711 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6712 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6713 msleep(1);
6714
61edc7fa
SG		 6715 /*
6716 * Make sure BBP is up and running.
6717 */
f4e1a4d3 6718 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6719 return -EIO;
b9a07ae9 6720
61edc7fa
SG		 6721 /*
6722 * Initialize BBP/RF registers.
6723 */
a1ef5039 6724 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6725 rt2800_init_rfcsr(rt2x00dev);
6726
b9a07ae9
ID		 6727 if (rt2x00_is_usb(rt2x00dev) &&
6728 (rt2x00_rt(rt2x00dev, RT3070) ||
6729 rt2x00_rt(rt2x00dev, RT3071) ||
6730 rt2x00_rt(rt2x00dev, RT3572))) {
6731 udelay(200);
6732 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6733 udelay(10);
6734 }
6735
6736 /*
6737 * Enable RX.
6738 */
6739 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6740 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6741 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6742 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6743
6744 udelay(50);
6745
6746 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6747 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6748 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6749 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6750 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6751 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6752
6753 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6754 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6755 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6756 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6757
6758 /*
6759 * Initialize LED control
6760 */
3e38d3da 6761 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6762 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6763 word & 0xff, (word >> 8) & 0xff);
6764
3e38d3da 6765 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6766 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6767 word & 0xff, (word >> 8) & 0xff);
6768
3e38d3da 6769 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6770 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6771 word & 0xff, (word >> 8) & 0xff);
6772
6773 return 0;
6774}
6775EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6776
6777void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6778{
6779 u32 reg;
6780
f7b395e9 6781 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6782
6783 /* Wait for DMA, ignore error */
6784 rt2800_wait_wpdma_ready(rt2x00dev);
6785
6786 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6787 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6788 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6789 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6790}
6791EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6792
30e84034
BZ		 6793int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6794{
6795 u32 reg;
a89534ed 6796 u16 efuse_ctrl_reg;
30e84034 6797
a89534ed
WH		 6798 if (rt2x00_rt(rt2x00dev, RT3290))
6799 efuse_ctrl_reg = EFUSE_CTRL_3290;
6800 else
6801 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6802
a89534ed 6803 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6804 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6805}
6806EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6807
6808static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6809{
6810 u32 reg;
a89534ed
WH		 6811 u16 efuse_ctrl_reg;
6812 u16 efuse_data0_reg;
6813 u16 efuse_data1_reg;
6814 u16 efuse_data2_reg;
6815 u16 efuse_data3_reg;
6816
6817 if (rt2x00_rt(rt2x00dev, RT3290)) {
6818 efuse_ctrl_reg = EFUSE_CTRL_3290;
6819 efuse_data0_reg = EFUSE_DATA0_3290;
6820 efuse_data1_reg = EFUSE_DATA1_3290;
6821 efuse_data2_reg = EFUSE_DATA2_3290;
6822 efuse_data3_reg = EFUSE_DATA3_3290;
6823 } else {
6824 efuse_ctrl_reg = EFUSE_CTRL;
6825 efuse_data0_reg = EFUSE_DATA0;
6826 efuse_data1_reg = EFUSE_DATA1;
6827 efuse_data2_reg = EFUSE_DATA2;
6828 efuse_data3_reg = EFUSE_DATA3;
6829 }
31a4cf1f
GW		 6830 mutex_lock(&rt2x00dev->csr_mutex);
6831
a89534ed 6832 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6833 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6834 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6835 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6836 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6837
6838 /* Wait until the EEPROM has been loaded */
a89534ed 6839 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6840 /* Apparently the data is read from end to start */
a89534ed 6841 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6842 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6843 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6844 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6845 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6846 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6847 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6848 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6849 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6850
6851 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6852}
6853
a02308e9 6854int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6855{
6856 unsigned int i;
6857
6858 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6859 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6860
6861 return 0;
30e84034
BZ		 6862}
6863EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6864
a3f1625d
GJ		 6865static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6866{
6867 u16 word;
6868
6316c786
GJ		 6869 if (rt2x00_rt(rt2x00dev, RT3593))
6870 return 0;
6871
a3f1625d
GJ		 6872 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6873 if ((word & 0x00ff) != 0x00ff)
6874 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6875
6876 return 0;
6877}
6878
6879static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6880{
6881 u16 word;
6882
6316c786
GJ		 6883 if (rt2x00_rt(rt2x00dev, RT3593))
6884 return 0;
6885
a3f1625d
GJ		 6886 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6887 if ((word & 0x00ff) != 0x00ff)
6888 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6889
6890 return 0;
6891}
6892
ad417a53 6893static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6894{
77c06c2c 6895 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6896 u16 word;
6897 u8 *mac;
6898 u8 default_lna_gain;
a02308e9 6899 int retval;
38bd7b8a 6900
ad417a53
GW		 6901 /*
6902 * Read the EEPROM.
6903 */
a02308e9
GJ		 6904 retval = rt2800_read_eeprom(rt2x00dev);
6905 if (retval)
6906 return retval;
ad417a53 6907
38bd7b8a
BZ		 6908 /*
6909 * Start validation of the data that has been read.
6910 */
3e38d3da 6911 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6912 if (!is_valid_ether_addr(mac)) {
f4f7f414 6913 eth_random_addr(mac);
ec9c4989 6914 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6915 }
6916
3e38d3da 6917 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6918 if (word == 0xffff) {
38c8a566
RJH		 6919 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6920 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6921 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6922 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6923 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6924 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6925 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6926 /*
6927 * There is a max of 2 RX streams for RT28x0 series
6928 */
38c8a566
RJH		 6929 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6930 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6931 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6932 }
6933
3e38d3da 6934 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6935 if (word == 0xffff) {
38c8a566
RJH		 6936 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6937 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6938 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6939 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6940 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6941 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6942 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6943 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6944 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6945 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6946 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6947 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6948 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6949 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6950 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6951 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6952 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6953 }
6954
3e38d3da 6955 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6956 if ((word & 0x00ff) == 0x00ff) {
6957 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6958 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6959 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6960 }
6961 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6962 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6963 LED_MODE_TXRX_ACTIVITY);
6964 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6965 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6966 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6967 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6968 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 6969 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 6970 }
6971
6972 /*
6973 * During the LNA validation we are going to use
6974 * lna0 as correct value. Note that EEPROM_LNA
6975 * is never validated.
6976 */
3e38d3da 6977 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 6978 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6979
3e38d3da 6980 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 6981 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6982 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6983 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6984 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 6985 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 6986
a3f1625d 6987 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 6988
3e38d3da 6989 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 6990 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6991 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 6992 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6993 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6994 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6995 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6996 default_lna_gain);
6997 }
3e38d3da 6998 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 6999
a3f1625d 7000 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7001
3e38d3da 7002 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7003 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7004 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7005 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7006 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7007 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7008
3e38d3da 7009 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7010 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7011 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7012 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7013 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7014 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7015 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7016 default_lna_gain);
7017 }
3e38d3da 7018 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7019
f36bb0ca
GJ		 7020 if (rt2x00_rt(rt2x00dev, RT3593)) {
7021 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7022 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7023 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7024 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7025 default_lna_gain);
7026 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7027 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7028 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7029 default_lna_gain);
7030 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7031 }
7032
38bd7b8a
BZ		 7033 return 0;
7034}
38bd7b8a 7035
ad417a53 7036static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7037{
38bd7b8a
BZ		 7038 u16 value;
7039 u16 eeprom;
86868b26 7040 u16 rf;
38bd7b8a 7041
86868b26
GJ		 7042 /*
7043 * Read EEPROM word for configuration.
7044 */
3e38d3da 7045 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7046
7047 /*
7048 * Identify RF chipset by EEPROM value
7049 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7050 * RT53xx: defined in "EEPROM_CHIP_ID" field
7051 */
7052 if (rt2x00_rt(rt2x00dev, RT3290) ||
7053 rt2x00_rt(rt2x00dev, RT5390) ||
7054 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7055 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7056 else
7057 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7058
7059 switch (rf) {
d331eb51
LF		 7060 case RF2820:
7061 case RF2850:
7062 case RF2720:
7063 case RF2750:
7064 case RF3020:
7065 case RF2020:
7066 case RF3021:
7067 case RF3022:
7068 case RF3052:
0f5af26a 7069 case RF3053:
3b9b74ba 7070 case RF3070:
a89534ed 7071 case RF3290:
d331eb51 7072 case RF3320:
03839951 7073 case RF3322:
ccf91bd6 7074 case RF5360:
d331eb51 7075 case RF5370:
2ed71884 7076 case RF5372:
d331eb51 7077 case RF5390:
cff3d1f0 7078 case RF5392:
b8863f8b 7079 case RF5592:
d331eb51
LF		 7080 break;
7081 default:
ec9c4989
JP		 7082 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7083 rf);
38bd7b8a
BZ		 7084 return -ENODEV;
7085 }
7086
86868b26
GJ		 7087 rt2x00_set_rf(rt2x00dev, rf);
7088
38bd7b8a
BZ		 7089 /*
7090 * Identify default antenna configuration.
7091 */
d96aa640 7092 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7093 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7094 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7095 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7096
3e38d3da 7097 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7098
7099 if (rt2x00_rt(rt2x00dev, RT3070) ||
7100 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7101 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7102 rt2x00_rt(rt2x00dev, RT3390)) {
7103 value = rt2x00_get_field16(eeprom,
7104 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7105 switch (value) {
7106 case 0:
7107 case 1:
7108 case 2:
7109 rt2x00dev->default_ant.tx = ANTENNA_A;
7110 rt2x00dev->default_ant.rx = ANTENNA_A;
7111 break;
7112 case 3:
7113 rt2x00dev->default_ant.tx = ANTENNA_A;
7114 rt2x00dev->default_ant.rx = ANTENNA_B;
7115 break;
7116 }
7117 } else {
7118 rt2x00dev->default_ant.tx = ANTENNA_A;
7119 rt2x00dev->default_ant.rx = ANTENNA_A;
7120 }
7121
0586a11b
AA		 7122 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7123 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7124 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7125 }
7126
38bd7b8a 7127 /*
9328fdac 7128 * Determine external LNA informations.
38bd7b8a 7129 */
38c8a566 7130 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7131 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7132 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7133 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7134
7135 /*
7136 * Detect if this device has an hardware controlled radio.
7137 */
38c8a566 7138 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7139 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7140
fdbc7b0a
GW		 7141 /*
7142 * Detect if this device has Bluetooth co-existence.
7143 */
7144 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7145 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7146
9328fdac
GW		 7147 /*
7148 * Read frequency offset and RF programming sequence.
7149 */
3e38d3da 7150 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7151 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7152
38bd7b8a
BZ		 7153 /*
7154 * Store led settings, for correct led behaviour.
7155 */
7156#ifdef CONFIG_RT2X00_LIB_LEDS
7157 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7158 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7159 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7160
9328fdac 7161 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7162#endif /* CONFIG_RT2X00_LIB_LEDS */
7163
e90c54b2
RJH		 7164 /*
7165 * Check if support EIRP tx power limit feature.
7166 */
3e38d3da 7167 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7168
7169 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7170 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7171 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7172
38bd7b8a
BZ		 7173 return 0;
7174}
38bd7b8a 7175
4da2933f 7176/*
55f9321a 7177 * RF value list for rt28xx
4da2933f
BZ		 7178 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7179 */
7180static const struct rf_channel rf_vals[] = {
7181 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7182 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7183 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7184 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7185 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7186 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7187 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7188 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7189 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7190 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7191 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7192 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7193 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7194 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7195
7196 /* 802.11 UNI / HyperLan 2 */
7197 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7198 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7199 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7200 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7201 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7202 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7203 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7204 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7205 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7206 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7207 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7208 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7209
7210 /* 802.11 HyperLan 2 */
7211 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7212 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7213 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7214 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7215 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7216 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7217 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7218 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7219 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7220 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7221 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7222 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7223 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7224 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7225 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7226 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7227
7228 /* 802.11 UNII */
7229 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7230 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7231 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7232 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7233 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7234 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7235 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7236 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7237 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7238 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7239 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7240
7241 /* 802.11 Japan */
7242 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7243 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7244 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7245 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7246 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7247 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7248 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7249};
7250
7251/*
55f9321a 7252 * RF value list for rt3xxx
b6b561c3 7253 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7254 */
55f9321a 7255static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7256 {1, 241, 2, 2 },
7257 {2, 241, 2, 7 },
7258 {3, 242, 2, 2 },
7259 {4, 242, 2, 7 },
7260 {5, 243, 2, 2 },
7261 {6, 243, 2, 7 },
7262 {7, 244, 2, 2 },
7263 {8, 244, 2, 7 },
7264 {9, 245, 2, 2 },
7265 {10, 245, 2, 7 },
7266 {11, 246, 2, 2 },
7267 {12, 246, 2, 7 },
7268 {13, 247, 2, 2 },
7269 {14, 248, 2, 4 },
55f9321a
ID		 7270
7271 /* 802.11 UNI / HyperLan 2 */
7272 {36, 0x56, 0, 4},
7273 {38, 0x56, 0, 6},
7274 {40, 0x56, 0, 8},
7275 {44, 0x57, 0, 0},
7276 {46, 0x57, 0, 2},
7277 {48, 0x57, 0, 4},
7278 {52, 0x57, 0, 8},
7279 {54, 0x57, 0, 10},
7280 {56, 0x58, 0, 0},
7281 {60, 0x58, 0, 4},
7282 {62, 0x58, 0, 6},
7283 {64, 0x58, 0, 8},
7284
7285 /* 802.11 HyperLan 2 */
7286 {100, 0x5b, 0, 8},
7287 {102, 0x5b, 0, 10},
7288 {104, 0x5c, 0, 0},
7289 {108, 0x5c, 0, 4},
7290 {110, 0x5c, 0, 6},
7291 {112, 0x5c, 0, 8},
7292 {116, 0x5d, 0, 0},
7293 {118, 0x5d, 0, 2},
7294 {120, 0x5d, 0, 4},
7295 {124, 0x5d, 0, 8},
7296 {126, 0x5d, 0, 10},
7297 {128, 0x5e, 0, 0},
7298 {132, 0x5e, 0, 4},
7299 {134, 0x5e, 0, 6},
7300 {136, 0x5e, 0, 8},
7301 {140, 0x5f, 0, 0},
7302
7303 /* 802.11 UNII */
7304 {149, 0x5f, 0, 9},
7305 {151, 0x5f, 0, 11},
7306 {153, 0x60, 0, 1},
7307 {157, 0x60, 0, 5},
7308 {159, 0x60, 0, 7},
7309 {161, 0x60, 0, 9},
7310 {165, 0x61, 0, 1},
7311 {167, 0x61, 0, 3},
7312 {169, 0x61, 0, 5},
7313 {171, 0x61, 0, 7},
7314 {173, 0x61, 0, 9},
4da2933f
BZ		 7315};
7316
7848b231
SG		 7317static const struct rf_channel rf_vals_5592_xtal20[] = {
7318 /* Channel, N, K, mod, R */
7319 {1, 482, 4, 10, 3},
7320 {2, 483, 4, 10, 3},
7321 {3, 484, 4, 10, 3},
7322 {4, 485, 4, 10, 3},
7323 {5, 486, 4, 10, 3},
7324 {6, 487, 4, 10, 3},
7325 {7, 488, 4, 10, 3},
7326 {8, 489, 4, 10, 3},
7327 {9, 490, 4, 10, 3},
7328 {10, 491, 4, 10, 3},
7329 {11, 492, 4, 10, 3},
7330 {12, 493, 4, 10, 3},
7331 {13, 494, 4, 10, 3},
7332 {14, 496, 8, 10, 3},
7333 {36, 172, 8, 12, 1},
7334 {38, 173, 0, 12, 1},
7335 {40, 173, 4, 12, 1},
7336 {42, 173, 8, 12, 1},
7337 {44, 174, 0, 12, 1},
7338 {46, 174, 4, 12, 1},
7339 {48, 174, 8, 12, 1},
7340 {50, 175, 0, 12, 1},
7341 {52, 175, 4, 12, 1},
7342 {54, 175, 8, 12, 1},
7343 {56, 176, 0, 12, 1},
7344 {58, 176, 4, 12, 1},
7345 {60, 176, 8, 12, 1},
7346 {62, 177, 0, 12, 1},
7347 {64, 177, 4, 12, 1},
7348 {100, 183, 4, 12, 1},
7349 {102, 183, 8, 12, 1},
7350 {104, 184, 0, 12, 1},
7351 {106, 184, 4, 12, 1},
7352 {108, 184, 8, 12, 1},
7353 {110, 185, 0, 12, 1},
7354 {112, 185, 4, 12, 1},
7355 {114, 185, 8, 12, 1},
7356 {116, 186, 0, 12, 1},
7357 {118, 186, 4, 12, 1},
7358 {120, 186, 8, 12, 1},
7359 {122, 187, 0, 12, 1},
7360 {124, 187, 4, 12, 1},
7361 {126, 187, 8, 12, 1},
7362 {128, 188, 0, 12, 1},
7363 {130, 188, 4, 12, 1},
7364 {132, 188, 8, 12, 1},
7365 {134, 189, 0, 12, 1},
7366 {136, 189, 4, 12, 1},
7367 {138, 189, 8, 12, 1},
7368 {140, 190, 0, 12, 1},
7369 {149, 191, 6, 12, 1},
7370 {151, 191, 10, 12, 1},
7371 {153, 192, 2, 12, 1},
7372 {155, 192, 6, 12, 1},
7373 {157, 192, 10, 12, 1},
7374 {159, 193, 2, 12, 1},
7375 {161, 193, 6, 12, 1},
7376 {165, 194, 2, 12, 1},
7377 {184, 164, 0, 12, 1},
7378 {188, 164, 4, 12, 1},
7379 {192, 165, 8, 12, 1},
7380 {196, 166, 0, 12, 1},
7381};
7382
7383static const struct rf_channel rf_vals_5592_xtal40[] = {
7384 /* Channel, N, K, mod, R */
7385 {1, 241, 2, 10, 3},
7386 {2, 241, 7, 10, 3},
7387 {3, 242, 2, 10, 3},
7388 {4, 242, 7, 10, 3},
7389 {5, 243, 2, 10, 3},
7390 {6, 243, 7, 10, 3},
7391 {7, 244, 2, 10, 3},
7392 {8, 244, 7, 10, 3},
7393 {9, 245, 2, 10, 3},
7394 {10, 245, 7, 10, 3},
7395 {11, 246, 2, 10, 3},
7396 {12, 246, 7, 10, 3},
7397 {13, 247, 2, 10, 3},
7398 {14, 248, 4, 10, 3},
7399 {36, 86, 4, 12, 1},
7400 {38, 86, 6, 12, 1},
7401 {40, 86, 8, 12, 1},
7402 {42, 86, 10, 12, 1},
7403 {44, 87, 0, 12, 1},
7404 {46, 87, 2, 12, 1},
7405 {48, 87, 4, 12, 1},
7406 {50, 87, 6, 12, 1},
7407 {52, 87, 8, 12, 1},
7408 {54, 87, 10, 12, 1},
7409 {56, 88, 0, 12, 1},
7410 {58, 88, 2, 12, 1},
7411 {60, 88, 4, 12, 1},
7412 {62, 88, 6, 12, 1},
7413 {64, 88, 8, 12, 1},
7414 {100, 91, 8, 12, 1},
7415 {102, 91, 10, 12, 1},
7416 {104, 92, 0, 12, 1},
7417 {106, 92, 2, 12, 1},
7418 {108, 92, 4, 12, 1},
7419 {110, 92, 6, 12, 1},
7420 {112, 92, 8, 12, 1},
7421 {114, 92, 10, 12, 1},
7422 {116, 93, 0, 12, 1},
7423 {118, 93, 2, 12, 1},
7424 {120, 93, 4, 12, 1},
7425 {122, 93, 6, 12, 1},
7426 {124, 93, 8, 12, 1},
7427 {126, 93, 10, 12, 1},
7428 {128, 94, 0, 12, 1},
7429 {130, 94, 2, 12, 1},
7430 {132, 94, 4, 12, 1},
7431 {134, 94, 6, 12, 1},
7432 {136, 94, 8, 12, 1},
7433 {138, 94, 10, 12, 1},
7434 {140, 95, 0, 12, 1},
7435 {149, 95, 9, 12, 1},
7436 {151, 95, 11, 12, 1},
7437 {153, 96, 1, 12, 1},
7438 {155, 96, 3, 12, 1},
7439 {157, 96, 5, 12, 1},
7440 {159, 96, 7, 12, 1},
7441 {161, 96, 9, 12, 1},
7442 {165, 97, 1, 12, 1},
7443 {184, 82, 0, 12, 1},
7444 {188, 82, 4, 12, 1},
7445 {192, 82, 8, 12, 1},
7446 {196, 83, 0, 12, 1},
7447};
7448
ad417a53 7449static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7450{
4da2933f
BZ		 7451 struct hw_mode_spec *spec = &rt2x00dev->spec;
7452 struct channel_info *info;
8d1331b3
ID		 7453 char *default_power1;
7454 char *default_power2;
c0a14369 7455 char *default_power3;
4da2933f 7456 unsigned int i;
7848b231 7457 u32 reg;
4da2933f 7458
93b6bd26 7459 /*
58e33a21 7460 * Disable powersaving as default.
93b6bd26 7461 */
58e33a21 7462 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7463
4da2933f
BZ		 7464 /*
7465 * Initialize all hw fields.
7466 */
7467 rt2x00dev->hw->flags =
4da2933f
BZ		 7468 IEEE80211_HW_SIGNAL_DBM |
7469 IEEE80211_HW_SUPPORTS_PS |
1df90809 7470 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 7471 IEEE80211_HW_AMPDU_AGGREGATION |
2dfca312
FF		 7472 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7473 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
9d4f09b8 7474
5a5b6ed6
HS		 7475 /*
7476 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7477 * unless we are capable of sending the buffered frames out after the
7478 * DTIM transmission using rt2x00lib_beacondone. This will send out
7479 * multicast and broadcast traffic immediately instead of buffering it
7480 * infinitly and thus dropping it after some time.
7481 */
7482 if (!rt2x00_is_usb(rt2x00dev))
7483 rt2x00dev->hw->flags |=
7484 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 7485
4da2933f
BZ		 7486 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7487 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7488 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7489 EEPROM_MAC_ADDR_0));
7490
3f2bee24
HS		 7491 /*
7492 * As rt2800 has a global fallback table we cannot specify
7493 * more then one tx rate per frame but since the hw will
7494 * try several rates (based on the fallback table) we should
ba3b9e5e 7495 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7496 * we are going to try. Otherwise mac80211 will truncate our
7497 * reported tx rates and the rc algortihm will end up with
7498 * incorrect data.
7499 */
ba3b9e5e
HS		 7500 rt2x00dev->hw->max_rates = 1;
7501 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7502 rt2x00dev->hw->max_rate_tries = 1;
7503
4da2933f
BZ		 7504 /*
7505 * Initialize hw_mode information.
7506 */
4da2933f
BZ		 7507 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7508
4a32c36d
GJ		 7509 switch (rt2x00dev->chip.rf) {
7510 case RF2720:
7511 case RF2820:
4da2933f
BZ		 7512 spec->num_channels = 14;
7513 spec->channels = rf_vals;
4a32c36d
GJ		 7514 break;
7515
7516 case RF2750:
7517 case RF2850:
4da2933f
BZ		 7518 spec->num_channels = ARRAY_SIZE(rf_vals);
7519 spec->channels = rf_vals;
4a32c36d
GJ		 7520 break;
7521
7522 case RF2020:
7523 case RF3020:
7524 case RF3021:
7525 case RF3022:
7526 case RF3070:
7527 case RF3290:
7528 case RF3320:
7529 case RF3322:
7530 case RF5360:
7531 case RF5370:
7532 case RF5372:
7533 case RF5390:
7534 case RF5392:
55f9321a
ID		 7535 spec->num_channels = 14;
7536 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7537 break;
7538
7539 case RF3052:
7540 case RF3053:
55f9321a
ID		 7541 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7542 spec->channels = rf_vals_3x;
4a32c36d 7543 break;
7848b231 7544
4a32c36d 7545 case RF5592:
7848b231
SG		 7546 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7547 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7548 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7549 spec->channels = rf_vals_5592_xtal40;
7550 } else {
7551 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7552 spec->channels = rf_vals_5592_xtal20;
7553 }
4a32c36d 7554 break;
4da2933f
BZ		 7555 }
7556
53216d6a
SG		 7557 if (WARN_ON_ONCE(!spec->channels))
7558 return -ENODEV;
7559
53c5a099
GJ		 7560 spec->supported_bands = SUPPORT_BAND_2GHZ;
7561 if (spec->num_channels > 14)
7562 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7563
4da2933f
BZ		 7564 /*
7565 * Initialize HT information.
7566 */
5122d898 7567 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7568 spec->ht.ht_supported = true;
7569 else
7570 spec->ht.ht_supported = false;
7571
4da2933f 7572 spec->ht.cap =
06443e46 7573 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7574 IEEE80211_HT_CAP_GRN_FLD |
7575 IEEE80211_HT_CAP_SGI_20 |
aa674631 7576 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7577
aa10350d 7578 if (rt2x00dev->default_ant.tx_chain_num >= 2)
22cabaa6
HS		 7579 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7580
aa10350d
GJ		 7581 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7582 IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7583
4da2933f
BZ		 7584 spec->ht.ampdu_factor = 3;
7585 spec->ht.ampdu_density = 4;
7586 spec->ht.mcs.tx_params =
7587 IEEE80211_HT_MCS_TX_DEFINED |
7588 IEEE80211_HT_MCS_TX_RX_DIFF |
aa10350d
GJ		 7589 ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7590 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4da2933f 7591
aa10350d 7592 switch (rt2x00dev->default_ant.rx_chain_num) {
4da2933f
BZ		 7593 case 3:
7594 spec->ht.mcs.rx_mask[2] = 0xff;
7595 case 2:
7596 spec->ht.mcs.rx_mask[1] = 0xff;
7597 case 1:
7598 spec->ht.mcs.rx_mask[0] = 0xff;
7599 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7600 break;
7601 }
7602
7603 /*
7604 * Create channel information array
7605 */
baeb2ffa 7606 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7607 if (!info)
7608 return -ENOMEM;
7609
7610 spec->channels_info = info;
7611
3e38d3da
GJ		 7612 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7613 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7614
c0a14369
GJ		 7615 if (rt2x00dev->default_ant.tx_chain_num > 2)
7616 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7617 EEPROM_EXT_TXPOWER_BG3);
7618 else
7619 default_power3 = NULL;
7620
4da2933f 7621 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7622 info[i].default_power1 = default_power1[i];
7623 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7624 if (default_power3)
7625 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7626 }
7627
7628 if (spec->num_channels > 14) {
3e38d3da
GJ		 7629 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7630 EEPROM_TXPOWER_A1);
7631 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7632 EEPROM_TXPOWER_A2);
4da2933f 7633
c0a14369
GJ		 7634 if (rt2x00dev->default_ant.tx_chain_num > 2)
7635 default_power3 =
7636 rt2800_eeprom_addr(rt2x00dev,
7637 EEPROM_EXT_TXPOWER_A3);
7638 else
7639 default_power3 = NULL;
7640
4da2933f 7641 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7642 info[i].default_power1 = default_power1[i - 14];
7643 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7644 if (default_power3)
7645 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7646 }
7647 }
7648
2e9c43dd
JL		 7649 switch (rt2x00dev->chip.rf) {
7650 case RF2020:
7651 case RF3020:
7652 case RF3021:
7653 case RF3022:
7654 case RF3320:
7655 case RF3052:
1095df07 7656 case RF3053:
3b9b74ba 7657 case RF3070:
a89534ed 7658 case RF3290:
ccf91bd6 7659 case RF5360:
2e9c43dd
JL		 7660 case RF5370:
7661 case RF5372:
7662 case RF5390:
cff3d1f0 7663 case RF5392:
2e9c43dd
JL		 7664 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7665 break;
7666 }
7667
4da2933f
BZ		 7668 return 0;
7669}
ad417a53 7670
cbafb601
GJ		 7671static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7672{
7673 u32 reg;
7674 u32 rt;
7675 u32 rev;
7676
7677 if (rt2x00_rt(rt2x00dev, RT3290))
7678 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7679 else
7680 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7681
7682 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7683 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7684
7685 switch (rt) {
7686 case RT2860:
7687 case RT2872:
7688 case RT2883:
7689 case RT3070:
7690 case RT3071:
7691 case RT3090:
7692 case RT3290:
7693 case RT3352:
7694 case RT3390:
7695 case RT3572:
2dc2bd2f 7696 case RT3593:
cbafb601
GJ		 7697 case RT5390:
7698 case RT5392:
7699 case RT5592:
7700 break;
7701 default:
ec9c4989
JP		 7702 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7703 rt, rev);
cbafb601
GJ		 7704 return -ENODEV;
7705 }
7706
7707 rt2x00_set_rt(rt2x00dev, rt, rev);
7708
7709 return 0;
7710}
7711
ad417a53
GW		 7712int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7713{
7714 int retval;
7715 u32 reg;
7716
cbafb601
GJ		 7717 retval = rt2800_probe_rt(rt2x00dev);
7718 if (retval)
7719 return retval;
7720
ad417a53
GW		 7721 /*
7722 * Allocate eeprom data.
7723 */
7724 retval = rt2800_validate_eeprom(rt2x00dev);
7725 if (retval)
7726 return retval;
7727
7728 retval = rt2800_init_eeprom(rt2x00dev);
7729 if (retval)
7730 return retval;
7731
7732 /*
7733 * Enable rfkill polling by setting GPIO direction of the
7734 * rfkill switch GPIO pin correctly.
7735 */
7736 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7737 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7738 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7739
7740 /*
7741 * Initialize hw specifications.
7742 */
7743 retval = rt2800_probe_hw_mode(rt2x00dev);
7744 if (retval)
7745 return retval;
7746
7747 /*
7748 * Set device capabilities.
7749 */
7750 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7751 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7752 if (!rt2x00_is_usb(rt2x00dev))
7753 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7754
7755 /*
7756 * Set device requirements.
7757 */
7758 if (!rt2x00_is_soc(rt2x00dev))
7759 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7760 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7761 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7762 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7763 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7764 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7765 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7766 if (rt2x00_is_usb(rt2x00dev))
7767 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7768 else {
7769 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7770 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7771 }
7772
7773 /*
7774 * Set the rssi offset.
7775 */
7776 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7777
7778 return 0;
7779}
7780EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7781
2ce33995
BZ		 7782/*
7783 * IEEE80211 stack callback functions.
7784 */
e783619e
HS		 7785void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7786 u16 *iv16)
2ce33995
BZ		 7787{
7788 struct rt2x00_dev *rt2x00dev = hw->priv;
7789 struct mac_iveiv_entry iveiv_entry;
7790 u32 offset;
7791
7792 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7793 rt2800_register_multiread(rt2x00dev, offset,
7794 &iveiv_entry, sizeof(iveiv_entry));
7795
855da5e0
JL		 7796 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7797 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 7798}
e783619e 7799EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 7800
e783619e 7801int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7802{
7803 struct rt2x00_dev *rt2x00dev = hw->priv;
7804 u32 reg;
7805 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7806
7807 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7808 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7809 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7810
7811 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7812 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7813 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7814
7815 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7816 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7817 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7818
7819 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7820 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7821 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7822
7823 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7824 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7825 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7826
7827 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7828 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7829 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7830
7831 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7832 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7833 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7834
7835 return 0;
7836}
e783619e 7837EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7838
8a3a3c85
EP		 7839int rt2800_conf_tx(struct ieee80211_hw *hw,
7840 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7841 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7842{
7843 struct rt2x00_dev *rt2x00dev = hw->priv;
7844 struct data_queue *queue;
7845 struct rt2x00_field32 field;
7846 int retval;
7847 u32 reg;
7848 u32 offset;
7849
7850 /*
7851 * First pass the configuration through rt2x00lib, that will
7852 * update the queue settings and validate the input. After that
7853 * we are free to update the registers based on the value
7854 * in the queue parameter.
7855 */
8a3a3c85 7856 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7857 if (retval)
7858 return retval;
7859
7860 /*
7861 * We only need to perform additional register initialization
7862 * for WMM queues/
7863 */
7864 if (queue_idx >= 4)
7865 return 0;
7866
11f818e0 7867 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7868
7869 /* Update WMM TXOP register */
7870 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7871 field.bit_offset = (queue_idx & 1) * 16;
7872 field.bit_mask = 0xffff << field.bit_offset;
7873
7874 rt2800_register_read(rt2x00dev, offset, &reg);
7875 rt2x00_set_field32(&reg, field, queue->txop);
7876 rt2800_register_write(rt2x00dev, offset, reg);
7877
7878 /* Update WMM registers */
7879 field.bit_offset = queue_idx * 4;
7880 field.bit_mask = 0xf << field.bit_offset;
7881
7882 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7883 rt2x00_set_field32(&reg, field, queue->aifs);
7884 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7885
7886 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7887 rt2x00_set_field32(&reg, field, queue->cw_min);
7888 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7889
7890 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7891 rt2x00_set_field32(&reg, field, queue->cw_max);
7892 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7893
7894 /* Update EDCA registers */
7895 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7896
7897 rt2800_register_read(rt2x00dev, offset, &reg);
7898 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7899 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7900 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7901 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7902 rt2800_register_write(rt2x00dev, offset, reg);
7903
7904 return 0;
7905}
e783619e 7906EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7907
37a41b4a 7908u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7909{
7910 struct rt2x00_dev *rt2x00dev = hw->priv;
7911 u64 tsf;
7912 u32 reg;
7913
7914 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7915 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7916 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7917 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7918
7919 return tsf;
7920}
e783619e 7921EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7922
e783619e
HS		 7923int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7924 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 7925 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7926 u8 buf_size)
1df90809 7927{
af35323d 7928 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7929 int ret = 0;
7930
af35323d
HS		 7931 /*
7932 * Don't allow aggregation for stations the hardware isn't aware
7933 * of because tx status reports for frames to an unknown station
7934 * always contain wcid=255 and thus we can't distinguish between
7935 * multiple stations which leads to unwanted situations when the
7936 * hw reorders frames due to aggregation.
7937 */
7938 if (sta_priv->wcid < 0)
7939 return 1;
7940
1df90809
HS		 7941 switch (action) {
7942 case IEEE80211_AMPDU_RX_START:
7943 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7944 /*
7945 * The hw itself takes care of setting up BlockAck mechanisms.
7946 * So, we only have to allow mac80211 to nagotiate a BlockAck
7947 * agreement. Once that is done, the hw will BlockAck incoming
7948 * AMPDUs without further setup.
7949 */
1df90809
HS		 7950 break;
7951 case IEEE80211_AMPDU_TX_START:
7952 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7953 break;
18b559d5
JB		 7954 case IEEE80211_AMPDU_TX_STOP_CONT:
7955 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7956 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7957 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7958 break;
7959 case IEEE80211_AMPDU_TX_OPERATIONAL:
7960 break;
7961 default:
ec9c4989
JP		 7962 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7963 "Unknown AMPDU action\n");
1df90809
HS		 7964 }
7965
7966 return ret;
7967}
e783619e 7968EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 7969
977206d7
HS		 7970int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7971 struct survey_info *survey)
7972{
7973 struct rt2x00_dev *rt2x00dev = hw->priv;
7974 struct ieee80211_conf *conf = &hw->conf;
7975 u32 idle, busy, busy_ext;
7976
7977 if (idx != 0)
7978 return -ENOENT;
7979
675a0b04 7980 survey->channel = conf->chandef.chan;
977206d7
HS		 7981
7982 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7983 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7984 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7985
7986 if (idle || busy) {
7987 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7988 SURVEY_INFO_CHANNEL_TIME_BUSY |
7989 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7990
7991 survey->channel_time = (idle + busy) / 1000;
7992 survey->channel_time_busy = busy / 1000;
7993 survey->channel_time_ext_busy = busy_ext / 1000;
7994 }
7995
9931df26
HS		 7996 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7997 survey->filled |= SURVEY_INFO_IN_USE;
7998
977206d7
HS		 7999 return 0;
8000
8001}
8002EXPORT_SYMBOL_GPL(rt2800_get_survey);
8003
a5ea2f02
ID		 8004MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8005MODULE_VERSION(DRV_VERSION);
8006MODULE_DESCRIPTION("Ralink RT2800 library");
8007MODULE_LICENSE("GPL");
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