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rt2x00: Update comment on freq_offset field in struct rt2x00_dev.
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c 402
adde5882 403 if (rt2x00_is_pci(rt2x00dev)) {
872834df
GW		 404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
adde5882
GJ		 406 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
407 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
408 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
409 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
410 }
f31c9a8c 411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 412 }
f31c9a8c 413
f31c9a8c
ID		 414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
4ed1dd2a
SG		 434 /*
435 * Disable DMA, will be reenabled later when enabling
436 * the radio.
437 */
438 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
441 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
442
f31c9a8c
ID		 443 /*
444 * Initialize firmware.
445 */
446 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
447 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 448 if (rt2x00_is_usb(rt2x00dev))
449 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 450 msleep(1);
451
452 return 0;
453}
454EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
0c5879bc
ID		 456void rt2800_write_tx_data(struct queue_entry *entry,
457 struct txentry_desc *txdesc)
59679b91 458{
0c5879bc 459 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 460 u32 word;
461
462 /*
463 * Initialize TX Info descriptor
464 */
465 rt2x00_desc_read(txwi, 0, &word);
466 rt2x00_set_field32(&word, TXWI_W0_FRAG,
467 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 468 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 470 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471 rt2x00_set_field32(&word, TXWI_W0_TS,
472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476 txdesc->u.ht.mpdu_density);
477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 479 rt2x00_set_field32(&word, TXWI_W0_BW,
480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485 rt2x00_desc_write(txwi, 0, word);
486
487 rt2x00_desc_read(txwi, 1, &word);
488 rt2x00_set_field32(&word, TXWI_W1_ACK,
489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 495 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 496 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497 txdesc->length);
2b23cdaa 498 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 499 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 500 rt2x00_desc_write(txwi, 1, word);
501
502 /*
503 * Always write 0 to IV/EIV fields, hardware will insert the IV
504 * from the IVEIV register when TXD_W3_WIV is set to 0.
505 * When TXD_W3_WIV is set to 1 it will use the IV data
506 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507 * crypto entry in the registers should be used to encrypt the frame.
508 */
509 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511}
0c5879bc 512EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 513
ff6133be 514static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 515{
74861922
ID		 516 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519 u16 eeprom;
520 u8 offset0;
521 u8 offset1;
522 u8 offset2;
523
e5ef5bad 524 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 525 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530 } else {
531 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536 }
537
538 /*
539 * Convert the value from the descriptor into the RSSI value
540 * If the value in the descriptor is 0, it is considered invalid
541 * and the default (extremely low) rssi value is assumed
542 */
543 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547 /*
548 * mac80211 only accepts a single RSSI value. Calculating the
549 * average doesn't deliver a fair answer either since -60:-60 would
550 * be considered equally good as -50:-70 while the second is the one
551 * which gives less energy...
552 */
553 rssi0 = max(rssi0, rssi1);
554 return max(rssi0, rssi2);
555}
556
557void rt2800_process_rxwi(struct queue_entry *entry,
558 struct rxdone_entry_desc *rxdesc)
559{
560 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 561 u32 word;
562
563 rt2x00_desc_read(rxwi, 0, &word);
564
565 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568 rt2x00_desc_read(rxwi, 1, &word);
569
570 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573 if (rt2x00_get_field32(word, RXWI_W1_BW))
574 rxdesc->flags |= RX_FLAG_40MHZ;
575
576 /*
577 * Detect RX rate, always use MCS as signal type.
578 */
579 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583 /*
584 * Mask of 0x8 bit to remove the short preamble flag.
585 */
586 if (rxdesc->rate_mode == RATE_MODE_CCK)
587 rxdesc->signal &= ~0x8;
588
589 rt2x00_desc_read(rxwi, 2, &word);
590
74861922
ID		 591 /*
592 * Convert descriptor AGC value to RSSI value.
593 */
594 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 595
596 /*
597 * Remove RXWI descriptor from start of buffer.
598 */
74861922 599 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 600}
601EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
31937c42 603void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 604{
605 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 607 struct txdone_entry_desc txdesc;
608 u32 word;
609 u16 mcs, real_mcs;
b34793ee 610 int aggr, ampdu;
14433331
HS		 611
612 /*
613 * Obtain the status about this packet.
614 */
615 txdesc.flags = 0;
14433331 616 rt2x00_desc_read(txwi, 0, &word);
b34793ee 617
14433331 618 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 619 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
620
14433331 621 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 622 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
623
624 /*
625 * If a frame was meant to be sent as a single non-aggregated MPDU
626 * but ended up in an aggregate the used tx rate doesn't correlate
627 * with the one specified in the TXWI as the whole aggregate is sent
628 * with the same rate.
629 *
630 * For example: two frames are sent to rt2x00, the first one sets
631 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
632 * and requests MCS15. If the hw aggregates both frames into one
633 * AMDPU the tx status for both frames will contain MCS7 although
634 * the frame was sent successfully.
635 *
636 * Hence, replace the requested rate with the real tx rate to not
637 * confuse the rate control algortihm by providing clearly wrong
638 * data.
639 */
5356d963 640 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 641 skbdesc->tx_rate_idx = real_mcs;
642 mcs = real_mcs;
643 }
14433331 644
f16d2db7
HS		 645 if (aggr == 1 || ampdu == 1)
646 __set_bit(TXDONE_AMPDU, &txdesc.flags);
647
14433331
HS		 648 /*
649 * Ralink has a retry mechanism using a global fallback
650 * table. We setup this fallback table to try the immediate
651 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
652 * always contains the MCS used for the last transmission, be
653 * it successful or not.
654 */
655 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
656 /*
657 * Transmission succeeded. The number of retries is
658 * mcs - real_mcs
659 */
660 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
661 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
662 } else {
663 /*
664 * Transmission failed. The number of retries is
665 * always 7 in this case (for a total number of 8
666 * frames sent).
667 */
668 __set_bit(TXDONE_FAILURE, &txdesc.flags);
669 txdesc.retry = rt2x00dev->long_retry;
670 }
671
672 /*
673 * the frame was retried at least once
674 * -> hw used fallback rates
675 */
676 if (txdesc.retry)
677 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
678
679 rt2x00lib_txdone(entry, &txdesc);
680}
681EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
682
f0194b2d
GW		 683void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
684{
685 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
686 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
687 unsigned int beacon_base;
739fd940 688 unsigned int padding_len;
d76dfc61 689 u32 orig_reg, reg;
f0194b2d
GW		 690
691 /*
692 * Disable beaconing while we are reloading the beacon data,
693 * otherwise we might be sending out invalid data.
694 */
695 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 696 orig_reg = reg;
f0194b2d
GW		 697 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
698 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
699
700 /*
701 * Add space for the TXWI in front of the skb.
702 */
b52398b6 703 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 704
705 /*
706 * Register descriptor details in skb frame descriptor.
707 */
708 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
709 skbdesc->desc = entry->skb->data;
710 skbdesc->desc_len = TXWI_DESC_SIZE;
711
712 /*
713 * Add the TXWI for the beacon to the skb.
714 */
0c5879bc 715 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 716
717 /*
718 * Dump beacon to userspace through debugfs.
719 */
720 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
721
722 /*
739fd940 723 * Write entire beacon with TXWI and padding to register.
f0194b2d 724 */
739fd940 725 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 726 if (padding_len && skb_pad(entry->skb, padding_len)) {
727 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
728 /* skb freed by skb_pad() on failure */
729 entry->skb = NULL;
730 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
731 return;
732 }
733
f0194b2d 734 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 735 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
736 entry->skb->len + padding_len);
f0194b2d
GW		 737
738 /*
739 * Enable beaconing again.
740 */
f0194b2d
GW		 741 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
742 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
743
744 /*
745 * Clean up beacon skb.
746 */
747 dev_kfree_skb_any(entry->skb);
748 entry->skb = NULL;
749}
50e888ea 750EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 751
69cf36a4
HS		 752static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
753 unsigned int beacon_base)
fdb87251
HS		 754{
755 int i;
756
757 /*
758 * For the Beacon base registers we only need to clear
759 * the whole TXWI which (when set to 0) will invalidate
760 * the entire beacon.
761 */
762 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
763 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
764}
765
69cf36a4
HS		 766void rt2800_clear_beacon(struct queue_entry *entry)
767{
768 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
769 u32 reg;
770
771 /*
772 * Disable beaconing while we are reloading the beacon data,
773 * otherwise we might be sending out invalid data.
774 */
775 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
776 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
777 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
778
779 /*
780 * Clear beacon.
781 */
782 rt2800_clear_beacon_register(rt2x00dev,
783 HW_BEACON_OFFSET(entry->entry_idx));
784
785 /*
786 * Enabled beaconing again.
787 */
788 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
790}
791EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
792
f4450616
BZ		 793#ifdef CONFIG_RT2X00_LIB_DEBUGFS
794const struct rt2x00debug rt2800_rt2x00debug = {
795 .owner = THIS_MODULE,
796 .csr = {
797 .read = rt2800_register_read,
798 .write = rt2800_register_write,
799 .flags = RT2X00DEBUGFS_OFFSET,
800 .word_base = CSR_REG_BASE,
801 .word_size = sizeof(u32),
802 .word_count = CSR_REG_SIZE / sizeof(u32),
803 },
804 .eeprom = {
805 .read = rt2x00_eeprom_read,
806 .write = rt2x00_eeprom_write,
807 .word_base = EEPROM_BASE,
808 .word_size = sizeof(u16),
809 .word_count = EEPROM_SIZE / sizeof(u16),
810 },
811 .bbp = {
812 .read = rt2800_bbp_read,
813 .write = rt2800_bbp_write,
814 .word_base = BBP_BASE,
815 .word_size = sizeof(u8),
816 .word_count = BBP_SIZE / sizeof(u8),
817 },
818 .rf = {
819 .read = rt2x00_rf_read,
820 .write = rt2800_rf_write,
821 .word_base = RF_BASE,
822 .word_size = sizeof(u32),
823 .word_count = RF_SIZE / sizeof(u32),
824 },
825};
826EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
827#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
828
829int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
830{
831 u32 reg;
832
833 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
834 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
835}
836EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
837
838#ifdef CONFIG_RT2X00_LIB_LEDS
839static void rt2800_brightness_set(struct led_classdev *led_cdev,
840 enum led_brightness brightness)
841{
842 struct rt2x00_led *led =
843 container_of(led_cdev, struct rt2x00_led, led_dev);
844 unsigned int enabled = brightness != LED_OFF;
845 unsigned int bg_mode =
846 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
847 unsigned int polarity =
848 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
849 EEPROM_FREQ_LED_POLARITY);
850 unsigned int ledmode =
851 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
852 EEPROM_FREQ_LED_MODE);
44704e5d 853 u32 reg;
f4450616 854
44704e5d
LE		 855 /* Check for SoC (SOC devices don't support MCU requests) */
856 if (rt2x00_is_soc(led->rt2x00dev)) {
857 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
858
859 /* Set LED Polarity */
860 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
861
862 /* Set LED Mode */
863 if (led->type == LED_TYPE_RADIO) {
864 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
865 enabled ? 3 : 0);
866 } else if (led->type == LED_TYPE_ASSOC) {
867 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
868 enabled ? 3 : 0);
869 } else if (led->type == LED_TYPE_QUALITY) {
870 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
871 enabled ? 3 : 0);
872 }
873
874 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
875
876 } else {
877 if (led->type == LED_TYPE_RADIO) {
878 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
879 enabled ? 0x20 : 0);
880 } else if (led->type == LED_TYPE_ASSOC) {
881 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
882 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
883 } else if (led->type == LED_TYPE_QUALITY) {
884 /*
885 * The brightness is divided into 6 levels (0 - 5),
886 * The specs tell us the following levels:
887 * 0, 1 ,3, 7, 15, 31
888 * to determine the level in a simple way we can simply
889 * work with bitshifting:
890 * (1 << level) - 1
891 */
892 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
893 (1 << brightness / (LED_FULL / 6)) - 1,
894 polarity);
895 }
f4450616
BZ		 896 }
897}
898
b3579d6a 899static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 900 struct rt2x00_led *led, enum led_type type)
901{
902 led->rt2x00dev = rt2x00dev;
903 led->type = type;
904 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 905 led->flags = LED_INITIALIZED;
906}
f4450616
BZ		 907#endif /* CONFIG_RT2X00_LIB_LEDS */
908
909/*
910 * Configuration handlers.
911 */
a2b1328a
HS		 912static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
913 const u8 *address,
914 int wcid)
f4450616
BZ		 915{
916 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 917 u32 offset;
918
919 offset = MAC_WCID_ENTRY(wcid);
920
921 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
922 if (address)
923 memcpy(wcid_entry.mac, address, ETH_ALEN);
924
925 rt2800_register_multiwrite(rt2x00dev, offset,
926 &wcid_entry, sizeof(wcid_entry));
927}
928
929static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
930{
931 u32 offset;
932 offset = MAC_WCID_ATTR_ENTRY(wcid);
933 rt2800_register_write(rt2x00dev, offset, 0);
934}
935
936static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
937 int wcid, u32 bssidx)
938{
939 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
940 u32 reg;
941
942 /*
943 * The BSS Idx numbers is split in a main value of 3 bits,
944 * and a extended field for adding one additional bit to the value.
945 */
946 rt2800_register_read(rt2x00dev, offset, &reg);
947 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
948 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
949 (bssidx & 0x8) >> 3);
950 rt2800_register_write(rt2x00dev, offset, reg);
951}
952
953static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
954 struct rt2x00lib_crypto *crypto,
955 struct ieee80211_key_conf *key)
956{
f4450616
BZ		 957 struct mac_iveiv_entry iveiv_entry;
958 u32 offset;
959 u32 reg;
960
961 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
962
e4a0ab34
ID		 963 if (crypto->cmd == SET_KEY) {
964 rt2800_register_read(rt2x00dev, offset, &reg);
965 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
966 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
967 /*
968 * Both the cipher as the BSS Idx numbers are split in a main
969 * value of 3 bits, and a extended field for adding one additional
970 * bit to the value.
971 */
972 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
973 (crypto->cipher & 0x7));
974 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
975 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 976 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
977 rt2800_register_write(rt2x00dev, offset, reg);
978 } else {
a2b1328a
HS		 979 /* Delete the cipher without touching the bssidx */
980 rt2800_register_read(rt2x00dev, offset, &reg);
981 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
982 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
983 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
984 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
985 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 986 }
f4450616
BZ		 987
988 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
989
990 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
991 if ((crypto->cipher == CIPHER_TKIP) ||
992 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
993 (crypto->cipher == CIPHER_AES))
994 iveiv_entry.iv[3] |= 0x20;
995 iveiv_entry.iv[3] |= key->keyidx << 6;
996 rt2800_register_multiwrite(rt2x00dev, offset,
997 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 998}
999
1000int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1001 struct rt2x00lib_crypto *crypto,
1002 struct ieee80211_key_conf *key)
1003{
1004 struct hw_key_entry key_entry;
1005 struct rt2x00_field32 field;
1006 u32 offset;
1007 u32 reg;
1008
1009 if (crypto->cmd == SET_KEY) {
1010 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1011
1012 memcpy(key_entry.key, crypto->key,
1013 sizeof(key_entry.key));
1014 memcpy(key_entry.tx_mic, crypto->tx_mic,
1015 sizeof(key_entry.tx_mic));
1016 memcpy(key_entry.rx_mic, crypto->rx_mic,
1017 sizeof(key_entry.rx_mic));
1018
1019 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1020 rt2800_register_multiwrite(rt2x00dev, offset,
1021 &key_entry, sizeof(key_entry));
1022 }
1023
1024 /*
1025 * The cipher types are stored over multiple registers
1026 * starting with SHARED_KEY_MODE_BASE each word will have
1027 * 32 bits and contains the cipher types for 2 bssidx each.
1028 * Using the correct defines correctly will cause overhead,
1029 * so just calculate the correct offset.
1030 */
1031 field.bit_offset = 4 * (key->hw_key_idx % 8);
1032 field.bit_mask = 0x7 << field.bit_offset;
1033
1034 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1035
1036 rt2800_register_read(rt2x00dev, offset, &reg);
1037 rt2x00_set_field32(&reg, field,
1038 (crypto->cmd == SET_KEY) * crypto->cipher);
1039 rt2800_register_write(rt2x00dev, offset, reg);
1040
1041 /*
1042 * Update WCID information
1043 */
a2b1328a
HS		 1044 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1045 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1046 crypto->bssidx);
1047 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1048
1049 return 0;
1050}
1051EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1052
a2b1328a 1053static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1054{
a2b1328a 1055 struct mac_wcid_entry wcid_entry;
1ed3811c 1056 int idx;
a2b1328a 1057 u32 offset;
1ed3811c
HS		 1058
1059 /*
a2b1328a
HS		 1060 * Search for the first free WCID entry and return the corresponding
1061 * index.
1ed3811c
HS		 1062 *
1063 * Make sure the WCID starts _after_ the last possible shared key
1064 * entry (>32).
1065 *
1066 * Since parts of the pairwise key table might be shared with
1067 * the beacon frame buffers 6 & 7 we should only write into the
1068 * first 222 entries.
1069 */
1070 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1071 offset = MAC_WCID_ENTRY(idx);
1072 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1073 sizeof(wcid_entry));
1074 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1075 return idx;
1076 }
a2b1328a
HS		 1077
1078 /*
1079 * Use -1 to indicate that we don't have any more space in the WCID
1080 * table.
1081 */
1ed3811c
HS		 1082 return -1;
1083}
1084
f4450616
BZ		 1085int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1086 struct rt2x00lib_crypto *crypto,
1087 struct ieee80211_key_conf *key)
1088{
1089 struct hw_key_entry key_entry;
1090 u32 offset;
1091
1092 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1093 /*
1094 * Allow key configuration only for STAs that are
1095 * known by the hw.
1096 */
1097 if (crypto->wcid < 0)
f4450616 1098 return -ENOSPC;
a2b1328a 1099 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1100
1101 memcpy(key_entry.key, crypto->key,
1102 sizeof(key_entry.key));
1103 memcpy(key_entry.tx_mic, crypto->tx_mic,
1104 sizeof(key_entry.tx_mic));
1105 memcpy(key_entry.rx_mic, crypto->rx_mic,
1106 sizeof(key_entry.rx_mic));
1107
1108 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1109 rt2800_register_multiwrite(rt2x00dev, offset,
1110 &key_entry, sizeof(key_entry));
1111 }
1112
1113 /*
1114 * Update WCID information
1115 */
a2b1328a 1116 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1117
1118 return 0;
1119}
1120EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1121
a2b1328a
HS		 1122int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1123 struct ieee80211_sta *sta)
1124{
1125 int wcid;
1126 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1127
1128 /*
1129 * Find next free WCID.
1130 */
1131 wcid = rt2800_find_wcid(rt2x00dev);
1132
1133 /*
1134 * Store selected wcid even if it is invalid so that we can
1135 * later decide if the STA is uploaded into the hw.
1136 */
1137 sta_priv->wcid = wcid;
1138
1139 /*
1140 * No space left in the device, however, we can still communicate
1141 * with the STA -> No error.
1142 */
1143 if (wcid < 0)
1144 return 0;
1145
1146 /*
1147 * Clean up WCID attributes and write STA address to the device.
1148 */
1149 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1150 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1151 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1152 rt2x00lib_get_bssidx(rt2x00dev, vif));
1153 return 0;
1154}
1155EXPORT_SYMBOL_GPL(rt2800_sta_add);
1156
1157int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1158{
1159 /*
1160 * Remove WCID entry, no need to clean the attributes as they will
1161 * get renewed when the WCID is reused.
1162 */
1163 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1164
1165 return 0;
1166}
1167EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1168
f4450616
BZ		 1169void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1170 const unsigned int filter_flags)
1171{
1172 u32 reg;
1173
1174 /*
1175 * Start configuration steps.
1176 * Note that the version error will always be dropped
1177 * and broadcast frames will always be accepted since
1178 * there is no filter for it at this time.
1179 */
1180 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1181 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1182 !(filter_flags & FIF_FCSFAIL));
1183 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1184 !(filter_flags & FIF_PLCPFAIL));
1185 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1186 !(filter_flags & FIF_PROMISC_IN_BSS));
1187 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1188 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1189 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1190 !(filter_flags & FIF_ALLMULTI));
1191 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1192 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1193 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1194 !(filter_flags & FIF_CONTROL));
1195 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1196 !(filter_flags & FIF_CONTROL));
1197 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1198 !(filter_flags & FIF_CONTROL));
1199 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1200 !(filter_flags & FIF_CONTROL));
1201 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1202 !(filter_flags & FIF_CONTROL));
1203 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1204 !(filter_flags & FIF_PSPOLL));
48839938
HS		 1205 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1206 !(filter_flags & FIF_CONTROL));
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1208 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1210 !(filter_flags & FIF_CONTROL));
1211 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1212}
1213EXPORT_SYMBOL_GPL(rt2800_config_filter);
1214
1215void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1216 struct rt2x00intf_conf *conf, const unsigned int flags)
1217{
f4450616 1218 u32 reg;
fa8b4b22 1219 bool update_bssid = false;
f4450616
BZ		 1220
1221 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1222 /*
1223 * Enable synchronisation.
1224 */
1225 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1226 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1227 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1228
1229 if (conf->sync == TSF_SYNC_AP_NONE) {
1230 /*
1231 * Tune beacon queue transmit parameters for AP mode
1232 */
1233 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1234 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1235 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1236 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1237 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1238 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1239 } else {
1240 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1241 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1242 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1243 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1244 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1245 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1246 }
f4450616
BZ		 1247 }
1248
1249 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1250 if (flags & CONFIG_UPDATE_TYPE &&
1251 conf->sync == TSF_SYNC_AP_NONE) {
1252 /*
1253 * The BSSID register has to be set to our own mac
1254 * address in AP mode.
1255 */
1256 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1257 update_bssid = true;
1258 }
1259
c600c826
ID		 1260 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1261 reg = le32_to_cpu(conf->mac[1]);
1262 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1263 conf->mac[1] = cpu_to_le32(reg);
1264 }
f4450616
BZ		 1265
1266 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1267 conf->mac, sizeof(conf->mac));
1268 }
1269
fa8b4b22 1270 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1271 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1272 reg = le32_to_cpu(conf->bssid[1]);
1273 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1274 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1275 conf->bssid[1] = cpu_to_le32(reg);
1276 }
f4450616
BZ		 1277
1278 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1279 conf->bssid, sizeof(conf->bssid));
1280 }
1281}
1282EXPORT_SYMBOL_GPL(rt2800_config_intf);
1283
87c1915d
HS		 1284static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_erp *erp)
1286{
1287 bool any_sta_nongf = !!(erp->ht_opmode &
1288 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1289 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1290 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1291 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1292 u32 reg;
1293
1294 /* default protection rate for HT20: OFDM 24M */
1295 mm20_rate = gf20_rate = 0x4004;
1296
1297 /* default protection rate for HT40: duplicate OFDM 24M */
1298 mm40_rate = gf40_rate = 0x4084;
1299
1300 switch (protection) {
1301 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1302 /*
1303 * All STAs in this BSS are HT20/40 but there might be
1304 * STAs not supporting greenfield mode.
1305 * => Disable protection for HT transmissions.
1306 */
1307 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1308
1309 break;
1310 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1311 /*
1312 * All STAs in this BSS are HT20 or HT20/40 but there
1313 * might be STAs not supporting greenfield mode.
1314 * => Protect all HT40 transmissions.
1315 */
1316 mm20_mode = gf20_mode = 0;
1317 mm40_mode = gf40_mode = 2;
1318
1319 break;
1320 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1321 /*
1322 * Nonmember protection:
1323 * According to 802.11n we _should_ protect all
1324 * HT transmissions (but we don't have to).
1325 *
1326 * But if cts_protection is enabled we _shall_ protect
1327 * all HT transmissions using a CCK rate.
1328 *
1329 * And if any station is non GF we _shall_ protect
1330 * GF transmissions.
1331 *
1332 * We decide to protect everything
1333 * -> fall through to mixed mode.
1334 */
1335 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1336 /*
1337 * Legacy STAs are present
1338 * => Protect all HT transmissions.
1339 */
1340 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1341
1342 /*
1343 * If erp protection is needed we have to protect HT
1344 * transmissions with CCK 11M long preamble.
1345 */
1346 if (erp->cts_protection) {
1347 /* don't duplicate RTS/CTS in CCK mode */
1348 mm20_rate = mm40_rate = 0x0003;
1349 gf20_rate = gf40_rate = 0x0003;
1350 }
1351 break;
6403eab1 1352 }
87c1915d
HS		 1353
1354 /* check for STAs not supporting greenfield mode */
1355 if (any_sta_nongf)
1356 gf20_mode = gf40_mode = 2;
1357
1358 /* Update HT protection config */
1359 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1360 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1361 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1362 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1363
1364 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1365 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1366 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1367 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1368
1369 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1370 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1371 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1372 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1373
1374 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1375 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1376 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1377 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1378}
1379
02044643
HS		 1380void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1381 u32 changed)
f4450616
BZ		 1382{
1383 u32 reg;
1384
02044643
HS		 1385 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1386 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1387 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1388 !!erp->short_preamble);
1389 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1390 !!erp->short_preamble);
1391 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1392 }
f4450616 1393
02044643
HS		 1394 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1395 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1396 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1397 erp->cts_protection ? 2 : 0);
1398 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1399 }
f4450616 1400
02044643
HS		 1401 if (changed & BSS_CHANGED_BASIC_RATES) {
1402 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1403 erp->basic_rates);
1404 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1405 }
f4450616 1406
02044643
HS		 1407 if (changed & BSS_CHANGED_ERP_SLOT) {
1408 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1409 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1410 erp->slot_time);
1411 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1412
02044643
HS		 1413 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1414 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1415 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1416 }
f4450616 1417
02044643
HS		 1418 if (changed & BSS_CHANGED_BEACON_INT) {
1419 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1420 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1421 erp->beacon_int * 16);
1422 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1423 }
87c1915d
HS		 1424
1425 if (changed & BSS_CHANGED_HT)
1426 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1427}
1428EXPORT_SYMBOL_GPL(rt2800_config_erp);
1429
872834df
GW		 1430static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1431{
1432 u32 reg;
1433 u16 eeprom;
1434 u8 led_ctrl, led_g_mode, led_r_mode;
1435
1436 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1437 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1438 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1439 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1440 } else {
1441 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1442 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1443 }
1444 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1445
1446 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1447 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1448 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1449 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1450 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1451 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1452 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1453 if (led_ctrl == 0 || led_ctrl > 0x40) {
1454 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1455 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1456 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1457 } else {
1458 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1459 (led_g_mode << 2) | led_r_mode, 1);
1460 }
1461 }
1462}
1463
d96aa640
RJH		 1464static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1465 enum antenna ant)
1466{
1467 u32 reg;
1468 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1469 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1470
1471 if (rt2x00_is_pci(rt2x00dev)) {
1472 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1473 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1474 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1475 } else if (rt2x00_is_usb(rt2x00dev))
1476 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1477 eesk_pin, 0);
1478
1479 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1480 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1481 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1482 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1483}
1484
f4450616
BZ		 1485void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1486{
1487 u8 r1;
1488 u8 r3;
d96aa640 1489 u16 eeprom;
f4450616
BZ		 1490
1491 rt2800_bbp_read(rt2x00dev, 1, &r1);
1492 rt2800_bbp_read(rt2x00dev, 3, &r3);
1493
872834df
GW		 1494 if (rt2x00_rt(rt2x00dev, RT3572) &&
1495 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1496 rt2800_config_3572bt_ant(rt2x00dev);
1497
f4450616
BZ		 1498 /*
1499 * Configure the TX antenna.
1500 */
d96aa640 1501 switch (ant->tx_chain_num) {
f4450616
BZ		 1502 case 1:
1503 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1504 break;
1505 case 2:
872834df
GW		 1506 if (rt2x00_rt(rt2x00dev, RT3572) &&
1507 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1508 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1509 else
1510 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1511 break;
1512 case 3:
e22557f2 1513 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1514 break;
1515 }
1516
1517 /*
1518 * Configure the RX antenna.
1519 */
d96aa640 1520 switch (ant->rx_chain_num) {
f4450616 1521 case 1:
d96aa640
RJH		 1522 if (rt2x00_rt(rt2x00dev, RT3070) ||
1523 rt2x00_rt(rt2x00dev, RT3090) ||
1524 rt2x00_rt(rt2x00dev, RT3390)) {
1525 rt2x00_eeprom_read(rt2x00dev,
1526 EEPROM_NIC_CONF1, &eeprom);
1527 if (rt2x00_get_field16(eeprom,
1528 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1529 rt2800_set_ant_diversity(rt2x00dev,
1530 rt2x00dev->default_ant.rx);
1531 }
f4450616
BZ		 1532 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1533 break;
1534 case 2:
872834df
GW		 1535 if (rt2x00_rt(rt2x00dev, RT3572) &&
1536 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1537 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1538 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1539 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1540 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1541 } else {
1542 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1543 }
f4450616
BZ		 1544 break;
1545 case 3:
1546 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1547 break;
1548 }
1549
1550 rt2800_bbp_write(rt2x00dev, 3, r3);
1551 rt2800_bbp_write(rt2x00dev, 1, r1);
1552}
1553EXPORT_SYMBOL_GPL(rt2800_config_ant);
1554
1555static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1556 struct rt2x00lib_conf *libconf)
1557{
1558 u16 eeprom;
1559 short lna_gain;
1560
1561 if (libconf->rf.channel <= 14) {
1562 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1563 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1564 } else if (libconf->rf.channel <= 64) {
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1566 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1567 } else if (libconf->rf.channel <= 128) {
1568 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1569 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1570 } else {
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1572 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1573 }
1574
1575 rt2x00dev->lna_gain = lna_gain;
1576}
1577
06855ef4
GW		 1578static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1579 struct ieee80211_conf *conf,
1580 struct rf_channel *rf,
1581 struct channel_info *info)
f4450616
BZ		 1582{
1583 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1584
d96aa640 1585 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1586 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1587
d96aa640 1588 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1589 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1590 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1591 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1592 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1593
1594 if (rf->channel > 14) {
1595 /*
1596 * When TX power is below 0, we should increase it by 7 to
25985edc 1597 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1598 * However this means that values between 0 and 7 have
1599 * double meaning, and we should set a 7DBm boost flag.
1600 */
1601 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1602 (info->default_power1 >= 0));
f4450616 1603
8d1331b3
ID		 1604 if (info->default_power1 < 0)
1605 info->default_power1 += 7;
f4450616 1606
8d1331b3 1607 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1608
1609 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1610 (info->default_power2 >= 0));
f4450616 1611
8d1331b3
ID		 1612 if (info->default_power2 < 0)
1613 info->default_power2 += 7;
f4450616 1614
8d1331b3 1615 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1616 } else {
8d1331b3
ID		 1617 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1618 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1619 }
1620
1621 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1622
1623 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1624 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1625 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1626 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1627
1628 udelay(200);
1629
1630 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1631 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1632 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1633 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1634
1635 udelay(200);
1636
1637 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1638 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1639 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1640 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1641}
1642
06855ef4
GW		 1643static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1644 struct ieee80211_conf *conf,
1645 struct rf_channel *rf,
1646 struct channel_info *info)
f4450616 1647{
3a1c0128 1648 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1649 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1650
1651 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1652
1653 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1654 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1655 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1656
1657 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1658 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1659 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1660
1661 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1662 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1663 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1664
5a673964 1665 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1666 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1667 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1668
1669 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1670 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1671 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1672 if (rt2x00_rt(rt2x00dev, RT3390)) {
1673 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1674 rt2x00dev->default_ant.rx_chain_num == 1);
1675 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1676 rt2x00dev->default_ant.tx_chain_num == 1);
1677 } else {
1678 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1679 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1680 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1681 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1682
1683 switch (rt2x00dev->default_ant.tx_chain_num) {
1684 case 1:
1685 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1686 /* fall through */
1687 case 2:
1688 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1689 break;
1690 }
1691
1692 switch (rt2x00dev->default_ant.rx_chain_num) {
1693 case 1:
1694 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1695 /* fall through */
1696 case 2:
1697 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1698 break;
1699 }
1700 }
1701 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1702
3e0c7643
SG		 1703 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1704 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1705 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1706 msleep(1);
1707 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1708 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1709
f4450616
BZ		 1710 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1711 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1712 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1713
f1f12f98
SG		 1714 if (rt2x00_rt(rt2x00dev, RT3390)) {
1715 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1716 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1717 } else {
3a1c0128
GW		 1718 if (conf_is_ht40(conf)) {
1719 calib_tx = drv_data->calibration_bw40;
1720 calib_rx = drv_data->calibration_bw40;
1721 } else {
1722 calib_tx = drv_data->calibration_bw20;
1723 calib_rx = drv_data->calibration_bw20;
1724 }
f1f12f98
SG		 1725 }
1726
1727 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1728 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1729 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1730
1731 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1732 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1733 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1734
71976907 1735 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1736 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1737 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1738
1739 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1740 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1741 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1742 msleep(1);
1743 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1744 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1745}
1746
872834df
GW		 1747static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1748 struct ieee80211_conf *conf,
1749 struct rf_channel *rf,
1750 struct channel_info *info)
1751{
3a1c0128 1752 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1753 u8 rfcsr;
1754 u32 reg;
1755
1756 if (rf->channel <= 14) {
1757 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1758 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1759 } else {
1760 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1761 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1762 }
1763
1764 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1765 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1766
1767 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1768 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1769 if (rf->channel <= 14)
1770 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1771 else
1772 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1773 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1774
1775 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1776 if (rf->channel <= 14)
1777 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1778 else
1779 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1780 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1781
1782 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1783 if (rf->channel <= 14) {
1784 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1785 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1786 (info->default_power1 & 0x3) |
1787 ((info->default_power1 & 0xC) << 1));
1788 } else {
1789 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1790 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1791 (info->default_power1 & 0x3) |
1792 ((info->default_power1 & 0xC) << 1));
1793 }
1794 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1795
1796 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1797 if (rf->channel <= 14) {
1798 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1799 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1800 (info->default_power2 & 0x3) |
1801 ((info->default_power2 & 0xC) << 1));
1802 } else {
1803 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1804 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1805 (info->default_power2 & 0x3) |
1806 ((info->default_power2 & 0xC) << 1));
1807 }
1808 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1809
1810 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1811 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1812 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1813 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1814 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1815 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1816 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1817 if (rf->channel <= 14) {
1818 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1819 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1820 }
1821 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1822 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1823 } else {
1824 switch (rt2x00dev->default_ant.tx_chain_num) {
1825 case 1:
1826 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1827 case 2:
1828 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1829 break;
1830 }
1831
1832 switch (rt2x00dev->default_ant.rx_chain_num) {
1833 case 1:
1834 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1835 case 2:
1836 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1837 break;
1838 }
1839 }
1840 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1841
1842 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1843 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1844 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1845
3a1c0128
GW		 1846 if (conf_is_ht40(conf)) {
1847 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1848 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1849 } else {
1850 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1851 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1852 }
872834df
GW		 1853
1854 if (rf->channel <= 14) {
1855 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1856 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1857 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1858 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1859 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1860 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1861 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1862 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1863 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1864 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1865 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1866 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1867 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1868 } else {
1869 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1870 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1871 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1872 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1873 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1874 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1875 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1876 if (rf->channel <= 64) {
1877 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1878 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1879 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1880 } else if (rf->channel <= 128) {
1881 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1882 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1883 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1884 } else {
1885 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1886 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1887 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1888 }
1889 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1890 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1891 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1892 }
1893
1894 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1895 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1896 if (rf->channel <= 14)
1897 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1898 else
1899 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1900 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1901
1902 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1903 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1904 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1905}
60687ba7
RST		 1906
1907#define RT5390_POWER_BOUND 0x27
1908#define RT5390_FREQ_OFFSET_BOUND 0x5f
1909
1910static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1911 struct ieee80211_conf *conf,
1912 struct rf_channel *rf,
1913 struct channel_info *info)
1914{
1915 u8 rfcsr;
adde5882
GJ		 1916
1917 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1918 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1919 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1920 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1921 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1922
1923 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1924 if (info->default_power1 > RT5390_POWER_BOUND)
1925 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1926 else
1927 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1928 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1929
1930 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1931 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1932 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1933 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1934 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1935 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1936
1937 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1938 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1939 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1940 RT5390_FREQ_OFFSET_BOUND);
1941 else
1942 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1943 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1944
adde5882
GJ		 1945 if (rf->channel <= 14) {
1946 int idx = rf->channel-1;
1947
fdbc7b0a 1948 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 1949 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1950 /* r55/r59 value array of channel 1~14 */
1951 static const char r55_bt_rev[] = {0x83, 0x83,
1952 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1953 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1954 static const char r59_bt_rev[] = {0x0e, 0x0e,
1955 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1956 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1957
1958 rt2800_rfcsr_write(rt2x00dev, 55,
1959 r55_bt_rev[idx]);
1960 rt2800_rfcsr_write(rt2x00dev, 59,
1961 r59_bt_rev[idx]);
1962 } else {
1963 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1964 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1965 0x88, 0x88, 0x86, 0x85, 0x84};
1966
1967 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1968 }
1969 } else {
1970 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1971 static const char r55_nonbt_rev[] = {0x23, 0x23,
1972 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1973 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1974 static const char r59_nonbt_rev[] = {0x07, 0x07,
1975 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1976 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1977
1978 rt2800_rfcsr_write(rt2x00dev, 55,
1979 r55_nonbt_rev[idx]);
1980 rt2800_rfcsr_write(rt2x00dev, 59,
1981 r59_nonbt_rev[idx]);
1982 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1983 static const char r59_non_bt[] = {0x8f, 0x8f,
1984 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1985 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1986
1987 rt2800_rfcsr_write(rt2x00dev, 59,
1988 r59_non_bt[idx]);
1989 }
1990 }
1991 }
1992
1993 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1994 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1995 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1996 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1997
1998 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1999 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2000 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 2001}
2002
f4450616
BZ		 2003static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2004 struct ieee80211_conf *conf,
2005 struct rf_channel *rf,
2006 struct channel_info *info)
2007{
2008 u32 reg;
2009 unsigned int tx_pin;
2010 u8 bbp;
2011
46323e11 2012 if (rf->channel <= 14) {
8d1331b3
ID		 2013 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2014 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2015 } else {
8d1331b3
ID		 2016 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2017 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2018 }
2019
5aa57015
GW		 2020 switch (rt2x00dev->chip.rf) {
2021 case RF2020:
2022 case RF3020:
2023 case RF3021:
2024 case RF3022:
2025 case RF3320:
06855ef4 2026 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2027 break;
2028 case RF3052:
872834df 2029 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015
GW		 2030 break;
2031 case RF5370:
2032 case RF5390:
adde5882 2033 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2034 break;
2035 default:
06855ef4 2036 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2037 }
f4450616
BZ		 2038
2039 /*
2040 * Change BBP settings
2041 */
2042 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2043 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2044 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2045 rt2800_bbp_write(rt2x00dev, 86, 0);
2046
2047 if (rf->channel <= 14) {
adde5882 2048 if (!rt2x00_rt(rt2x00dev, RT5390)) {
7dab73b3
ID		 2049 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2050 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2051 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2052 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2053 } else {
2054 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2055 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2056 }
f4450616
BZ		 2057 }
2058 } else {
872834df
GW		 2059 if (rt2x00_rt(rt2x00dev, RT3572))
2060 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2061 else
2062 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2063
7dab73b3 2064 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2065 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2066 else
2067 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2068 }
2069
2070 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2071 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2072 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2073 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2074 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2075
872834df
GW		 2076 if (rt2x00_rt(rt2x00dev, RT3572))
2077 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2078
f4450616
BZ		 2079 tx_pin = 0;
2080
2081 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2082 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2083 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2084 rf->channel > 14);
2085 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2086 rf->channel <= 14);
f4450616
BZ		 2087 }
2088
2089 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2090 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2091 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2092 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2093 }
2094
2095 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2096 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2097 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2098 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2099 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2100 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2101 else
2102 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2103 rf->channel <= 14);
f4450616
BZ		 2104 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2105
2106 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2107
872834df
GW		 2108 if (rt2x00_rt(rt2x00dev, RT3572))
2109 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2110
f4450616
BZ		 2111 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2112 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2113 rt2800_bbp_write(rt2x00dev, 4, bbp);
2114
2115 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2116 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2117 rt2800_bbp_write(rt2x00dev, 3, bbp);
2118
8d0c9b65 2119 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2120 if (conf_is_ht40(conf)) {
2121 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2122 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2123 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2124 } else {
2125 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2126 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2127 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2128 }
2129 }
2130
2131 msleep(1);
977206d7
HS		 2132
2133 /*
2134 * Clear channel statistic counters
2135 */
2136 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2137 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2138 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 2139}
2140
9e33a355
HS		 2141static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2142{
2143 u8 tssi_bounds[9];
2144 u8 current_tssi;
2145 u16 eeprom;
2146 u8 step;
2147 int i;
2148
2149 /*
2150 * Read TSSI boundaries for temperature compensation from
2151 * the EEPROM.
2152 *
2153 * Array idx 0 1 2 3 4 5 6 7 8
2154 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2155 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2156 */
2157 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2158 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2159 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2160 EEPROM_TSSI_BOUND_BG1_MINUS4);
2161 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2162 EEPROM_TSSI_BOUND_BG1_MINUS3);
2163
2164 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2165 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2166 EEPROM_TSSI_BOUND_BG2_MINUS2);
2167 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2168 EEPROM_TSSI_BOUND_BG2_MINUS1);
2169
2170 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2171 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2172 EEPROM_TSSI_BOUND_BG3_REF);
2173 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2174 EEPROM_TSSI_BOUND_BG3_PLUS1);
2175
2176 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2177 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2178 EEPROM_TSSI_BOUND_BG4_PLUS2);
2179 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2180 EEPROM_TSSI_BOUND_BG4_PLUS3);
2181
2182 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2183 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2184 EEPROM_TSSI_BOUND_BG5_PLUS4);
2185
2186 step = rt2x00_get_field16(eeprom,
2187 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2188 } else {
2189 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2190 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2191 EEPROM_TSSI_BOUND_A1_MINUS4);
2192 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2193 EEPROM_TSSI_BOUND_A1_MINUS3);
2194
2195 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2196 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2197 EEPROM_TSSI_BOUND_A2_MINUS2);
2198 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2199 EEPROM_TSSI_BOUND_A2_MINUS1);
2200
2201 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2202 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2203 EEPROM_TSSI_BOUND_A3_REF);
2204 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2205 EEPROM_TSSI_BOUND_A3_PLUS1);
2206
2207 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2208 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2209 EEPROM_TSSI_BOUND_A4_PLUS2);
2210 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2211 EEPROM_TSSI_BOUND_A4_PLUS3);
2212
2213 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2214 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2215 EEPROM_TSSI_BOUND_A5_PLUS4);
2216
2217 step = rt2x00_get_field16(eeprom,
2218 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2219 }
2220
2221 /*
2222 * Check if temperature compensation is supported.
2223 */
2224 if (tssi_bounds[4] == 0xff)
2225 return 0;
2226
2227 /*
2228 * Read current TSSI (BBP 49).
2229 */
2230 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2231
2232 /*
2233 * Compare TSSI value (BBP49) with the compensation boundaries
2234 * from the EEPROM and increase or decrease tx power.
2235 */
2236 for (i = 0; i <= 3; i++) {
2237 if (current_tssi > tssi_bounds[i])
2238 break;
2239 }
2240
2241 if (i == 4) {
2242 for (i = 8; i >= 5; i--) {
2243 if (current_tssi < tssi_bounds[i])
2244 break;
2245 }
2246 }
2247
2248 return (i - 4) * step;
2249}
2250
e90c54b2
RJH		 2251static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2252 enum ieee80211_band band)
2253{
2254 u16 eeprom;
2255 u8 comp_en;
2256 u8 comp_type;
75faae8b 2257 int comp_value = 0;
e90c54b2
RJH		 2258
2259 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2260
75faae8b
HS		 2261 /*
2262 * HT40 compensation not required.
2263 */
2264 if (eeprom == 0xffff ||
2265 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2266 return 0;
2267
2268 if (band == IEEE80211_BAND_2GHZ) {
2269 comp_en = rt2x00_get_field16(eeprom,
2270 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2271 if (comp_en) {
2272 comp_type = rt2x00_get_field16(eeprom,
2273 EEPROM_TXPOWER_DELTA_TYPE_2G);
2274 comp_value = rt2x00_get_field16(eeprom,
2275 EEPROM_TXPOWER_DELTA_VALUE_2G);
2276 if (!comp_type)
2277 comp_value = -comp_value;
2278 }
2279 } else {
2280 comp_en = rt2x00_get_field16(eeprom,
2281 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2282 if (comp_en) {
2283 comp_type = rt2x00_get_field16(eeprom,
2284 EEPROM_TXPOWER_DELTA_TYPE_5G);
2285 comp_value = rt2x00_get_field16(eeprom,
2286 EEPROM_TXPOWER_DELTA_VALUE_5G);
2287 if (!comp_type)
2288 comp_value = -comp_value;
2289 }
2290 }
2291
2292 return comp_value;
2293}
2294
fa71a160
HS		 2295static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2296 enum ieee80211_band band, int power_level,
2297 u8 txpower, int delta)
e90c54b2
RJH		 2298{
2299 u32 reg;
2300 u16 eeprom;
2301 u8 criterion;
2302 u8 eirp_txpower;
2303 u8 eirp_txpower_criterion;
2304 u8 reg_limit;
e90c54b2
RJH		 2305
2306 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2307 return txpower;
2308
7dab73b3 2309 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2310 /*
2311 * Check if eirp txpower exceed txpower_limit.
2312 * We use OFDM 6M as criterion and its eirp txpower
2313 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2314 * .11b data rate need add additional 4dbm
2315 * when calculating eirp txpower.
2316 */
2317 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2318 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2319
2320 rt2x00_eeprom_read(rt2x00dev,
2321 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2322
2323 if (band == IEEE80211_BAND_2GHZ)
2324 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2325 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2326 else
2327 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2328 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2329
2330 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2331 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2332
2333 reg_limit = (eirp_txpower > power_level) ?
2334 (eirp_txpower - power_level) : 0;
2335 } else
2336 reg_limit = 0;
2337
2af242e1 2338 return txpower + delta - reg_limit;
e90c54b2
RJH		 2339}
2340
f4450616 2341static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2342 enum ieee80211_band band,
2343 int power_level)
f4450616 2344{
5e846004 2345 u8 txpower;
5e846004 2346 u16 eeprom;
e90c54b2 2347 int i, is_rate_b;
f4450616 2348 u32 reg;
f4450616 2349 u8 r1;
5e846004 2350 u32 offset;
2af242e1
HS		 2351 int delta;
2352
2353 /*
2354 * Calculate HT40 compensation delta
2355 */
2356 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2357
9e33a355
HS		 2358 /*
2359 * calculate temperature compensation delta
2360 */
2361 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2362
5e846004 2363 /*
e90c54b2 2364 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2365 */
f4450616 2366 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2367 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2368 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2369 offset = TX_PWR_CFG_0;
2370
2371 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2372 /* just to be safe */
2373 if (offset > TX_PWR_CFG_4)
2374 break;
2375
2376 rt2800_register_read(rt2x00dev, offset, &reg);
2377
2378 /* read the next four txpower values */
2379 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2380 &eeprom);
2381
e90c54b2
RJH		 2382 is_rate_b = i ? 0 : 1;
2383 /*
2384 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2385 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2386 * TX_PWR_CFG_4: unknown
2387 */
5e846004
HS		 2388 txpower = rt2x00_get_field16(eeprom,
2389 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2390 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2391 power_level, txpower, delta);
e90c54b2 2392 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2393
e90c54b2
RJH		 2394 /*
2395 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2396 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2397 * TX_PWR_CFG_4: unknown
2398 */
5e846004
HS		 2399 txpower = rt2x00_get_field16(eeprom,
2400 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2401 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2402 power_level, txpower, delta);
e90c54b2 2403 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2404
e90c54b2
RJH		 2405 /*
2406 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2407 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2408 * TX_PWR_CFG_4: unknown
2409 */
5e846004
HS		 2410 txpower = rt2x00_get_field16(eeprom,
2411 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2412 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2413 power_level, txpower, delta);
e90c54b2 2414 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2415
e90c54b2
RJH		 2416 /*
2417 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2418 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2419 * TX_PWR_CFG_4: unknown
2420 */
5e846004
HS		 2421 txpower = rt2x00_get_field16(eeprom,
2422 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2423 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2424 power_level, txpower, delta);
e90c54b2 2425 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2426
2427 /* read the next four txpower values */
2428 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2429 &eeprom);
2430
e90c54b2
RJH		 2431 is_rate_b = 0;
2432 /*
2433 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2434 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2435 * TX_PWR_CFG_4: unknown
2436 */
5e846004
HS		 2437 txpower = rt2x00_get_field16(eeprom,
2438 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2439 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2440 power_level, txpower, delta);
e90c54b2 2441 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2442
e90c54b2
RJH		 2443 /*
2444 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2445 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2446 * TX_PWR_CFG_4: unknown
2447 */
5e846004
HS		 2448 txpower = rt2x00_get_field16(eeprom,
2449 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2450 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2451 power_level, txpower, delta);
e90c54b2 2452 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2453
e90c54b2
RJH		 2454 /*
2455 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2456 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2457 * TX_PWR_CFG_4: unknown
2458 */
5e846004
HS		 2459 txpower = rt2x00_get_field16(eeprom,
2460 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2461 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2462 power_level, txpower, delta);
e90c54b2 2463 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2464
e90c54b2
RJH		 2465 /*
2466 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2467 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2468 * TX_PWR_CFG_4: unknown
2469 */
5e846004
HS		 2470 txpower = rt2x00_get_field16(eeprom,
2471 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2472 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2473 power_level, txpower, delta);
e90c54b2 2474 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2475
2476 rt2800_register_write(rt2x00dev, offset, reg);
2477
2478 /* next TX_PWR_CFG register */
2479 offset += 4;
2480 }
f4450616
BZ		 2481}
2482
9e33a355
HS		 2483void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2484{
2485 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2486 rt2x00dev->tx_power);
2487}
2488EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2489
f4450616
BZ		 2490static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2491 struct rt2x00lib_conf *libconf)
2492{
2493 u32 reg;
2494
2495 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2496 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2497 libconf->conf->short_frame_max_tx_count);
2498 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2499 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2500 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2501}
2502
2503static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2504 struct rt2x00lib_conf *libconf)
2505{
2506 enum dev_state state =
2507 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2508 STATE_SLEEP : STATE_AWAKE;
2509 u32 reg;
2510
2511 if (state == STATE_SLEEP) {
2512 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2513
2514 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2515 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2516 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2517 libconf->conf->listen_interval - 1);
2518 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2519 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2520
2521 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2522 } else {
f4450616
BZ		 2523 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2524 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2525 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2526 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2527 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2528
2529 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2530 }
2531}
2532
2533void rt2800_config(struct rt2x00_dev *rt2x00dev,
2534 struct rt2x00lib_conf *libconf,
2535 const unsigned int flags)
2536{
2537 /* Always recalculate LNA gain before changing configuration */
2538 rt2800_config_lna_gain(rt2x00dev, libconf);
2539
e90c54b2 2540 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2541 rt2800_config_channel(rt2x00dev, libconf->conf,
2542 &libconf->rf, &libconf->channel);
9e33a355
HS		 2543 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2544 libconf->conf->power_level);
e90c54b2 2545 }
f4450616 2546 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2547 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2548 libconf->conf->power_level);
f4450616
BZ		 2549 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2550 rt2800_config_retry_limit(rt2x00dev, libconf);
2551 if (flags & IEEE80211_CONF_CHANGE_PS)
2552 rt2800_config_ps(rt2x00dev, libconf);
2553}
2554EXPORT_SYMBOL_GPL(rt2800_config);
2555
2556/*
2557 * Link tuning
2558 */
2559void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2560{
2561 u32 reg;
2562
2563 /*
2564 * Update FCS error count from register.
2565 */
2566 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2567 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2568}
2569EXPORT_SYMBOL_GPL(rt2800_link_stats);
2570
2571static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2572{
2573 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2574 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2575 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2576 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882
GJ		 2577 rt2x00_rt(rt2x00dev, RT3390) ||
2578 rt2x00_rt(rt2x00dev, RT5390))
f4450616
BZ		 2579 return 0x1c + (2 * rt2x00dev->lna_gain);
2580 else
2581 return 0x2e + rt2x00dev->lna_gain;
2582 }
2583
2584 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2585 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2586 else
2587 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2588}
2589
2590static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2591 struct link_qual *qual, u8 vgc_level)
2592{
2593 if (qual->vgc_level != vgc_level) {
2594 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2595 qual->vgc_level = vgc_level;
2596 qual->vgc_level_reg = vgc_level;
2597 }
2598}
2599
2600void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2601{
2602 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2603}
2604EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2605
2606void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2607 const u32 count)
2608{
8d0c9b65 2609 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2610 return;
2611
2612 /*
2613 * When RSSI is better then -80 increase VGC level with 0x10
2614 */
2615 rt2800_set_vgc(rt2x00dev, qual,
2616 rt2800_get_default_vgc(rt2x00dev) +
2617 ((qual->rssi > -80) * 0x10));
2618}
2619EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2620
2621/*
2622 * Initialization functions.
2623 */
b9a07ae9 2624static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2625{
2626 u32 reg;
d5385bfc 2627 u16 eeprom;
fcf51541 2628 unsigned int i;
e3a896b9 2629 int ret;
fcf51541 2630
a9dce149
GW		 2631 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2632 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2633 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2634 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2635 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2636 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2637 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2638
e3a896b9
GW		 2639 ret = rt2800_drv_init_registers(rt2x00dev);
2640 if (ret)
2641 return ret;
fcf51541
BZ		 2642
2643 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2644 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2645 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2646 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2647 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2648 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2649
2650 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2651 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2652 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2653 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2654 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2655 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2656
2657 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2658 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2659
2660 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2661
2662 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2663 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2664 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2665 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2666 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2667 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2668 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2669 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2670
a9dce149
GW		 2671 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2672
2673 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2674 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2675 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2676 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2677
64522957 2678 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2679 rt2x00_rt(rt2x00dev, RT3090) ||
2680 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2681 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2682 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2683 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2684 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2685 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2686 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2687 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2688 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2689 0x0000002c);
2690 else
2691 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2692 0x0000000f);
2693 } else {
2694 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2695 }
d5385bfc 2696 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2697 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2698
2699 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2700 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2701 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2702 } else {
2703 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2704 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2705 }
c295a81d
HS		 2706 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2707 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2708 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 2709 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
872834df
GW		 2710 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2711 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2712 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
adde5882
GJ		 2713 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2714 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2715 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2716 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2717 } else {
2718 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2719 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2720 }
2721
2722 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2723 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2724 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2725 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2726 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2727 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2728 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2729 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2730 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2731 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2732
2733 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2734 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2735 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2736 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2737 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2738
2739 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2740 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2741 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2742 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2743 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2744 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2745 else
2746 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2747 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2748 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2749 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2750
a9dce149
GW		 2751 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2752 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2753 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2754 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2755 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2756 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2757 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2758 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2759 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2760
fcf51541
BZ		 2761 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2762
a9dce149
GW		 2763 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2764 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2765 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2766 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2767 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2768 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2769 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2770 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2771
fcf51541
BZ		 2772 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2773 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2774 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2775 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2776 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2777 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2778 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2779 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2780 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2781
2782 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2783 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2784 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2785 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2786 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2787 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2788 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2789 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2790 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2791 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2792 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2793 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2794
2795 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2796 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2797 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2798 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2799 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2800 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2801 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2802 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2803 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2804 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2805 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2806 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2807
2808 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2809 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2810 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2811 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2812 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2813 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2814 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2815 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2816 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2817 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2818 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2819 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2820
2821 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2822 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2823 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2824 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2825 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2826 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2827 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2828 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2829 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2830 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2831 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2832 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2833
2834 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2835 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2836 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2837 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2838 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2839 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2840 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2841 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2842 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2843 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2844 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2845 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2846
2847 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2848 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2849 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2850 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2851 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2852 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2853 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2854 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2855 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2856 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2857 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2858 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2859
cea90e55 2860 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2861 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2862
2863 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2864 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2865 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2866 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2867 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2868 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2869 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2870 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2871 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2872 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2873 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2874 }
2875
961621ab
HS		 2876 /*
2877 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2878 * although it is reserved.
2879 */
2880 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2881 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2882 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2883 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2884 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2885 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2886 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2887 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2888 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2889 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2890 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2891 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2892
fcf51541
BZ		 2893 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2894
2895 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2896 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2897 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2898 IEEE80211_MAX_RTS_THRESHOLD);
2899 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2900 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2901
2902 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2903
a21c2ab4
HS		 2904 /*
2905 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2906 * time should be set to 16. However, the original Ralink driver uses
2907 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2908 * connection problems with 11g + CTS protection. Hence, use the same
2909 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2910 */
a9dce149 2911 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2912 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2913 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2914 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2915 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2916 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2917 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2918
fcf51541
BZ		 2919 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2920
2921 /*
2922 * ASIC will keep garbage value after boot, clear encryption keys.
2923 */
2924 for (i = 0; i < 4; i++)
2925 rt2800_register_write(rt2x00dev,
2926 SHARED_KEY_MODE_ENTRY(i), 0);
2927
2928 for (i = 0; i < 256; i++) {
d7d259d3
HS		 2929 rt2800_config_wcid(rt2x00dev, NULL, i);
2930 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 2931 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2932 }
2933
2934 /*
2935 * Clear all beacons
fcf51541 2936 */
69cf36a4
HS		 2937 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2938 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2939 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2940 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2941 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2942 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2943 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2944 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2945
cea90e55 2946 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2947 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2948 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2949 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2950 } else if (rt2x00_is_pcie(rt2x00dev)) {
2951 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2952 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2953 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2954 }
2955
2956 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2957 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2958 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2959 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2960 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2961 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2962 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2963 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2964 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2965 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2966
2967 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2968 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2969 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2970 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2971 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2972 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2973 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2974 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2975 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2976 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2977
2978 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2979 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2980 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2981 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2982 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2983 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2984 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2985 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2986 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2987 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2988
2989 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2990 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2991 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2992 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2993 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2994 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2995
47ee3eb1
HS		 2996 /*
2997 * Do not force the BA window size, we use the TXWI to set it
2998 */
2999 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3000 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3001 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3002 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3003
fcf51541
BZ		 3004 /*
3005 * We must clear the error counters.
3006 * These registers are cleared on read,
3007 * so we may pass a useless variable to store the value.
3008 */
3009 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3010 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3011 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3012 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3013 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3014 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3015
9f926fb5
HS		 3016 /*
3017 * Setup leadtime for pre tbtt interrupt to 6ms
3018 */
3019 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3020 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3021 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3022
977206d7
HS		 3023 /*
3024 * Set up channel statistics timer
3025 */
3026 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3027 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3028 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3029 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3030 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3031 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3032 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3033
fcf51541
BZ		 3034 return 0;
3035}
fcf51541
BZ		 3036
3037static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3038{
3039 unsigned int i;
3040 u32 reg;
3041
3042 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3043 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3044 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3045 return 0;
3046
3047 udelay(REGISTER_BUSY_DELAY);
3048 }
3049
3050 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3051 return -EACCES;
3052}
3053
3054static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3055{
3056 unsigned int i;
3057 u8 value;
3058
3059 /*
3060 * BBP was enabled after firmware was loaded,
3061 * but we need to reactivate it now.
3062 */
3063 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3064 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3065 msleep(1);
3066
3067 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3068 rt2800_bbp_read(rt2x00dev, 0, &value);
3069 if ((value != 0xff) && (value != 0x00))
3070 return 0;
3071 udelay(REGISTER_BUSY_DELAY);
3072 }
3073
3074 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3075 return -EACCES;
3076}
3077
b9a07ae9 3078static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3079{
3080 unsigned int i;
3081 u16 eeprom;
3082 u8 reg_id;
3083 u8 value;
3084
3085 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3086 rt2800_wait_bbp_ready(rt2x00dev)))
3087 return -EACCES;
3088
adde5882
GJ		 3089 if (rt2x00_rt(rt2x00dev, RT5390)) {
3090 rt2800_bbp_read(rt2x00dev, 4, &value);
3091 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3092 rt2800_bbp_write(rt2x00dev, 4, value);
3093 }
60687ba7 3094
adde5882 3095 if (rt2800_is_305x_soc(rt2x00dev) ||
872834df 3096 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3097 rt2x00_rt(rt2x00dev, RT5390))
baff8006
HS		 3098 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3099
fcf51541
BZ		 3100 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3101 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3102
adde5882
GJ		 3103 if (rt2x00_rt(rt2x00dev, RT5390))
3104 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3105
a9dce149
GW		 3106 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3107 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3108 rt2800_bbp_write(rt2x00dev, 73, 0x12);
adde5882
GJ		 3109 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3110 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3111 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3112 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3113 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3114 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3115 } else {
3116 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3117 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3118 }
3119
fcf51541 3120 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3121
d5385bfc 3122 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3123 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3124 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3125 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3126 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3127 rt2x00_rt(rt2x00dev, RT5390)) {
8cdd15e0
GW		 3128 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3129 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3130 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3131 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3132 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3133 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 3134 } else {
3135 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3136 }
3137
fcf51541 3138 rt2800_bbp_write(rt2x00dev, 82, 0x62);
adde5882
GJ		 3139 if (rt2x00_rt(rt2x00dev, RT5390))
3140 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3141 else
3142 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3143
5ed8f458 3144 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3145 rt2800_bbp_write(rt2x00dev, 84, 0x19);
adde5882
GJ		 3146 else if (rt2x00_rt(rt2x00dev, RT5390))
3147 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3148 else
3149 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3150
adde5882
GJ		 3151 if (rt2x00_rt(rt2x00dev, RT5390))
3152 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3153 else
3154 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3155
fcf51541 3156 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3157
adde5882
GJ		 3158 if (rt2x00_rt(rt2x00dev, RT5390))
3159 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3160 else
3161 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3162
d5385bfc 3163 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3164 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3165 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3166 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
872834df 3167 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3168 rt2x00_rt(rt2x00dev, RT5390) ||
baff8006 3169 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3170 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3171 else
3172 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3173
adde5882
GJ		 3174 if (rt2x00_rt(rt2x00dev, RT5390))
3175 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3176
baff8006
HS		 3177 if (rt2800_is_305x_soc(rt2x00dev))
3178 rt2800_bbp_write(rt2x00dev, 105, 0x01);
adde5882
GJ		 3179 else if (rt2x00_rt(rt2x00dev, RT5390))
3180 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3181 else
3182 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3183
adde5882
GJ		 3184 if (rt2x00_rt(rt2x00dev, RT5390))
3185 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3186 else
3187 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3188
adde5882
GJ		 3189 if (rt2x00_rt(rt2x00dev, RT5390))
3190 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3191
64522957 3192 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3193 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3194 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3195 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3196 rt2x00_rt(rt2x00dev, RT5390)) {
d5385bfc 3197 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3198
38c8a566
RJH		 3199 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3200 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3201 value |= 0x20;
38c8a566 3202 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3203 value &= ~0x02;
fcf51541 3204
d5385bfc 3205 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3206 }
3207
adde5882
GJ		 3208 if (rt2x00_rt(rt2x00dev, RT5390)) {
3209 int ant, div_mode;
3210
3211 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3212 div_mode = rt2x00_get_field16(eeprom,
3213 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3214 ant = (div_mode == 3) ? 1 : 0;
3215
3216 /* check if this is a Bluetooth combo card */
fdbc7b0a 3217 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3218 u32 reg;
3219
3220 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3221 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3222 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3223 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3224 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3225 if (ant == 0)
3226 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3227 else if (ant == 1)
3228 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3229 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3230 }
3231
3232 rt2800_bbp_read(rt2x00dev, 152, &value);
3233 if (ant == 0)
3234 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3235 else
3236 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3237 rt2800_bbp_write(rt2x00dev, 152, value);
3238
3239 /* Init frequency calibration */
3240 rt2800_bbp_write(rt2x00dev, 142, 1);
3241 rt2800_bbp_write(rt2x00dev, 143, 57);
3242 }
fcf51541
BZ		 3243
3244 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3245 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3246
3247 if (eeprom != 0xffff && eeprom != 0x0000) {
3248 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3249 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3250 rt2800_bbp_write(rt2x00dev, reg_id, value);
3251 }
3252 }
3253
3254 return 0;
3255}
fcf51541
BZ		 3256
3257static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3258 bool bw40, u8 rfcsr24, u8 filter_target)
3259{
3260 unsigned int i;
3261 u8 bbp;
3262 u8 rfcsr;
3263 u8 passband;
3264 u8 stopband;
3265 u8 overtuned = 0;
3266
3267 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3268
3269 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3270 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3271 rt2800_bbp_write(rt2x00dev, 4, bbp);
3272
80d184e6
RJH		 3273 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3274 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3275 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3276
fcf51541
BZ		 3277 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3278 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3279 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3280
3281 /*
3282 * Set power & frequency of passband test tone
3283 */
3284 rt2800_bbp_write(rt2x00dev, 24, 0);
3285
3286 for (i = 0; i < 100; i++) {
3287 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3288 msleep(1);
3289
3290 rt2800_bbp_read(rt2x00dev, 55, &passband);
3291 if (passband)
3292 break;
3293 }
3294
3295 /*
3296 * Set power & frequency of stopband test tone
3297 */
3298 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3299
3300 for (i = 0; i < 100; i++) {
3301 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3302 msleep(1);
3303
3304 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3305
3306 if ((passband - stopband) <= filter_target) {
3307 rfcsr24++;
3308 overtuned += ((passband - stopband) == filter_target);
3309 } else
3310 break;
3311
3312 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3313 }
3314
3315 rfcsr24 -= !!overtuned;
3316
3317 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3318 return rfcsr24;
3319}
3320
b9a07ae9 3321static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 3322{
3a1c0128 3323 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541
BZ		 3324 u8 rfcsr;
3325 u8 bbp;
8cdd15e0
GW		 3326 u32 reg;
3327 u16 eeprom;
fcf51541 3328
d5385bfc 3329 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3330 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3331 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3332 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3333 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3334 !rt2x00_rt(rt2x00dev, RT5390) &&
baff8006 3335 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3336 return 0;
3337
fcf51541
BZ		 3338 /*
3339 * Init RF calibration.
3340 */
adde5882
GJ		 3341 if (rt2x00_rt(rt2x00dev, RT5390)) {
3342 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3343 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3344 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3345 msleep(1);
3346 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3347 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3348 } else {
3349 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3350 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3351 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3352 msleep(1);
3353 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3354 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3355 }
fcf51541 3356
d5385bfc 3357 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3358 rt2x00_rt(rt2x00dev, RT3071) ||
3359 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3360 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3361 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3362 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3363 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3364 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3365 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3366 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3367 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3368 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3369 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3370 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3371 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3372 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3373 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3374 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3375 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3376 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3377 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3378 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3379 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3380 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3381 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3382 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3383 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3384 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3385 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3386 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3387 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3388 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3389 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3390 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3391 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3392 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3393 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3394 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3395 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3396 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3397 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3398 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3399 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3400 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3401 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3402 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3403 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3404 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3405 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3406 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3407 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3408 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3409 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3410 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3411 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3412 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3413 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3414 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3415 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3416 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3417 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3418 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3419 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3420 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3421 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3422 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3423 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3424 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3425 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3426 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3427 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3428 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3429 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3430 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3431 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3432 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3433 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3434 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3435 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3436 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3437 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3438 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3439 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3440 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3441 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3442 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3443 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 3444 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3445 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3446 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3447 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3448 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3449 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3450 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3451 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3452 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3453 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3454 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3455 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3456 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3457 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3458 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3459 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3460 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3461 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3462 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3463 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3464 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3465 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3466 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3467 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3468 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3469 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3470 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3471 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3472 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3473 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3474 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3475 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3476 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3477 return 0;
adde5882
GJ		 3478 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3479 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3480 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3481 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3482 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3483 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3484 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3485 else
3486 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3487 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3488 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3489 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3490 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3491 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3492 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3493 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3494 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3495 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3496 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3497
3498 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3499 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3500 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3501 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3502 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3503 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3504 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3505 else
3506 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3507 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3508 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3509 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3510 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3511
3512 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3513 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3514 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3515 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3516 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3517 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3518 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3519 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3520 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3521 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3522
3523 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3524 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3525 else
3526 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3527 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3528 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3529 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3530 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3531 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3532 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3533 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3534 else
3535 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3536 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3537 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3538 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3539
3540 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3541 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3542 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3543 else
3544 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3545 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3546 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3547 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3548 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3549 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3550 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3551
3552 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3553 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3554 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3555 else
3556 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3557 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3558 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8cdd15e0
GW		 3559 }
3560
3561 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3562 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3563 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3564 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3565 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3566 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3567 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3568 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3569
d5385bfc
GW		 3570 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3571 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3572 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3573
d5385bfc
GW		 3574 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3575 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3576 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3577 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3578 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3579 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3580 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3581 else
3582 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3583 }
3584 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3585
3586 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3587 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3588 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3589 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3590 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3591 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3592 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 3593 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3594 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3595 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3596 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3597
3598 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3599 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3600 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3601 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3602 msleep(1);
3603 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3604 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3605 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 3606 }
3607
3608 /*
3609 * Set RX Filter calibration for 20MHz and 40MHz
3610 */
8cdd15e0 3611 if (rt2x00_rt(rt2x00dev, RT3070)) {
3a1c0128 3612 drv_data->calibration_bw20 =
8cdd15e0 3613 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3a1c0128 3614 drv_data->calibration_bw40 =
8cdd15e0 3615 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3616 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3617 rt2x00_rt(rt2x00dev, RT3090) ||
872834df
GW		 3618 rt2x00_rt(rt2x00dev, RT3390) ||
3619 rt2x00_rt(rt2x00dev, RT3572)) {
3a1c0128 3620 drv_data->calibration_bw20 =
d5385bfc 3621 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3a1c0128 3622 drv_data->calibration_bw40 =
d5385bfc 3623 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3624 }
fcf51541 3625
adde5882
GJ		 3626 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3627 /*
3628 * Set back to initial state
3629 */
3630 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3631
adde5882
GJ		 3632 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3633 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3634 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3635
adde5882
GJ		 3636 /*
3637 * Set BBP back to BW20
3638 */
3639 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3640 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3641 rt2800_bbp_write(rt2x00dev, 4, bbp);
3642 }
fcf51541 3643
d5385bfc 3644 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3645 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3646 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3647 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3648 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3649
3650 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3651 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3652 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3653
adde5882
GJ		 3654 if (!rt2x00_rt(rt2x00dev, RT5390)) {
3655 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3656 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3657 if (rt2x00_rt(rt2x00dev, RT3070) ||
3658 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3659 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3660 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3661 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3662 &rt2x00dev->cap_flags))
adde5882
GJ		 3663 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3664 }
3665 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3666 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3667 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3668 rt2x00_get_field16(eeprom,
3669 EEPROM_TXMIXER_GAIN_BG_VAL));
3670 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3671 }
8cdd15e0 3672
64522957
GW		 3673 if (rt2x00_rt(rt2x00dev, RT3090)) {
3674 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3675
80d184e6 3676 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3677 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3678 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3679 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3680 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3681 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3682
3683 rt2800_bbp_write(rt2x00dev, 138, bbp);
3684 }
3685
3686 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3687 rt2x00_rt(rt2x00dev, RT3090) ||
3688 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3689 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3690 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3691 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3692 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3693 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3694 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3695 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3696
3697 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3698 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3699 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3700
3701 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3702 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3703 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3704
3705 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3706 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3707 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3708 }
3709
80d184e6 3710 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3711 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3712 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3713 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3714 else
3715 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3716 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3717 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3718 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3719 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3720 }
3721
adde5882
GJ		 3722 if (rt2x00_rt(rt2x00dev, RT5390)) {
3723 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3724 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3725 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3726
adde5882
GJ		 3727 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3728 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3729 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3730
adde5882
GJ		 3731 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3732 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3733 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3734 }
60687ba7 3735
fcf51541
BZ		 3736 return 0;
3737}
b9a07ae9
ID		 3738
3739int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3740{
3741 u32 reg;
3742 u16 word;
3743
3744 /*
3745 * Initialize all registers.
3746 */
3747 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3748 rt2800_init_registers(rt2x00dev) ||
3749 rt2800_init_bbp(rt2x00dev) ||
3750 rt2800_init_rfcsr(rt2x00dev)))
3751 return -EIO;
3752
3753 /*
3754 * Send signal to firmware during boot time.
3755 */
3756 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3757
3758 if (rt2x00_is_usb(rt2x00dev) &&
3759 (rt2x00_rt(rt2x00dev, RT3070) ||
3760 rt2x00_rt(rt2x00dev, RT3071) ||
3761 rt2x00_rt(rt2x00dev, RT3572))) {
3762 udelay(200);
3763 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3764 udelay(10);
3765 }
3766
3767 /*
3768 * Enable RX.
3769 */
3770 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3771 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3772 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3773 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3774
3775 udelay(50);
3776
3777 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3778 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3779 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3780 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3781 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3782 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3783
3784 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3785 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3786 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3787 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3788
3789 /*
3790 * Initialize LED control
3791 */
38c8a566
RJH		 3792 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3793 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3794 word & 0xff, (word >> 8) & 0xff);
3795
38c8a566
RJH		 3796 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3797 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3798 word & 0xff, (word >> 8) & 0xff);
3799
38c8a566
RJH		 3800 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3801 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3802 word & 0xff, (word >> 8) & 0xff);
3803
3804 return 0;
3805}
3806EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3807
3808void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3809{
3810 u32 reg;
3811
3812 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3813 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 3814 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 3815 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3816
3817 /* Wait for DMA, ignore error */
3818 rt2800_wait_wpdma_ready(rt2x00dev);
3819
3820 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3822 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3823 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 3824}
3825EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 3826
30e84034
BZ		 3827int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3828{
3829 u32 reg;
3830
3831 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3832
3833 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3834}
3835EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3836
3837static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3838{
3839 u32 reg;
3840
31a4cf1f
GW		 3841 mutex_lock(&rt2x00dev->csr_mutex);
3842
3843 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 3844 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3845 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3846 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 3847 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 3848
3849 /* Wait until the EEPROM has been loaded */
3850 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3851
3852 /* Apparently the data is read from end to start */
daabead1
LF		 3853 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3854 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 3855 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
daabead1
LF		 3856 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3857 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3858 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3859 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3860 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3861 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 3862
3863 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 3864}
3865
3866void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3867{
3868 unsigned int i;
3869
3870 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3871 rt2800_efuse_read(rt2x00dev, i);
3872}
3873EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3874
38bd7b8a
BZ		 3875int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3876{
3877 u16 word;
3878 u8 *mac;
3879 u8 default_lna_gain;
3880
3881 /*
3882 * Start validation of the data that has been read.
3883 */
3884 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3885 if (!is_valid_ether_addr(mac)) {
3886 random_ether_addr(mac);
3887 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3888 }
3889
38c8a566 3890 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 3891 if (word == 0xffff) {
38c8a566
RJH		 3892 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3893 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3894 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3895 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 3896 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 3897 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 3898 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 3899 /*
3900 * There is a max of 2 RX streams for RT28x0 series
3901 */
38c8a566
RJH		 3902 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3903 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3904 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 3905 }
3906
38c8a566 3907 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 3908 if (word == 0xffff) {
38c8a566
RJH		 3909 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3910 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3911 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3912 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3913 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3914 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3915 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3924 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 3925 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3926 }
3927
3928 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3929 if ((word & 0x00ff) == 0x00ff) {
3930 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 3931 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3932 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3933 }
3934 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 3935 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3936 LED_MODE_TXRX_ACTIVITY);
3937 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3938 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 3939 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3940 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3941 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3942 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3943 }
3944
3945 /*
3946 * During the LNA validation we are going to use
3947 * lna0 as correct value. Note that EEPROM_LNA
3948 * is never validated.
3949 */
3950 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3951 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3952
3953 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3954 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3955 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3956 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3957 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3958 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3959
3960 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3961 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3962 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3963 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3964 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3965 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3966 default_lna_gain);
3967 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3968
3969 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3970 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3971 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3972 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3973 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3974 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3975
3976 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3977 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3978 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3979 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3980 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3981 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3982 default_lna_gain);
3983 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3984
3985 return 0;
3986}
3987EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3988
3989int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3990{
3991 u32 reg;
3992 u16 value;
3993 u16 eeprom;
3994
3995 /*
3996 * Read EEPROM word for configuration.
3997 */
38c8a566 3998 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3999
4000 /*
adde5882
GJ		 4001 * Identify RF chipset by EEPROM value
4002 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4003 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 4004 */
38bd7b8a 4005 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
adde5882
GJ		 4006 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
4007 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4008 else
4009 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 4010
49e721ec
GW		 4011 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4012 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4013
5aa57015
GW		 4014 switch (rt2x00dev->chip.rt) {
4015 case RT2860:
4016 case RT2872:
4017 case RT2883:
4018 case RT3070:
4019 case RT3071:
4020 case RT3090:
4021 case RT3390:
4022 case RT3572:
4023 case RT5390:
4024 break;
4025 default:
49e721ec
GW		 4026 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
4027 return -ENODEV;
f273fe55 4028 }
714fa663 4029
d331eb51
LF		 4030 switch (rt2x00dev->chip.rf) {
4031 case RF2820:
4032 case RF2850:
4033 case RF2720:
4034 case RF2750:
4035 case RF3020:
4036 case RF2020:
4037 case RF3021:
4038 case RF3022:
4039 case RF3052:
4040 case RF3320:
4041 case RF5370:
4042 case RF5390:
4043 break;
4044 default:
4045 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
4046 rt2x00dev->chip.rf);
38bd7b8a
BZ		 4047 return -ENODEV;
4048 }
4049
4050 /*
4051 * Identify default antenna configuration.
4052 */
d96aa640 4053 rt2x00dev->default_ant.tx_chain_num =
38c8a566 4054 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 4055 rt2x00dev->default_ant.rx_chain_num =
38c8a566 4056 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 4057
d96aa640
RJH		 4058 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4059
4060 if (rt2x00_rt(rt2x00dev, RT3070) ||
4061 rt2x00_rt(rt2x00dev, RT3090) ||
4062 rt2x00_rt(rt2x00dev, RT3390)) {
4063 value = rt2x00_get_field16(eeprom,
4064 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4065 switch (value) {
4066 case 0:
4067 case 1:
4068 case 2:
4069 rt2x00dev->default_ant.tx = ANTENNA_A;
4070 rt2x00dev->default_ant.rx = ANTENNA_A;
4071 break;
4072 case 3:
4073 rt2x00dev->default_ant.tx = ANTENNA_A;
4074 rt2x00dev->default_ant.rx = ANTENNA_B;
4075 break;
4076 }
4077 } else {
4078 rt2x00dev->default_ant.tx = ANTENNA_A;
4079 rt2x00dev->default_ant.rx = ANTENNA_A;
4080 }
4081
38bd7b8a 4082 /*
9328fdac 4083 * Determine external LNA informations.
38bd7b8a 4084 */
38c8a566 4085 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4086 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4087 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4088 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4089
4090 /*
4091 * Detect if this device has an hardware controlled radio.
4092 */
38c8a566 4093 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4094 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4095
fdbc7b0a
GW		 4096 /*
4097 * Detect if this device has Bluetooth co-existence.
4098 */
4099 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4100 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4101
9328fdac
GW		 4102 /*
4103 * Read frequency offset and RF programming sequence.
4104 */
4105 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4106 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4107
38bd7b8a
BZ		 4108 /*
4109 * Store led settings, for correct led behaviour.
4110 */
4111#ifdef CONFIG_RT2X00_LIB_LEDS
4112 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4113 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4114 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4115
9328fdac 4116 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4117#endif /* CONFIG_RT2X00_LIB_LEDS */
4118
e90c54b2
RJH		 4119 /*
4120 * Check if support EIRP tx power limit feature.
4121 */
4122 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4123
4124 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4125 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4126 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4127
38bd7b8a
BZ		 4128 return 0;
4129}
4130EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4131
4da2933f 4132/*
55f9321a 4133 * RF value list for rt28xx
4da2933f
BZ		 4134 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4135 */
4136static const struct rf_channel rf_vals[] = {
4137 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4138 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4139 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4140 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4141 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4142 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4143 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4144 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4145 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4146 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4147 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4148 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4149 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4150 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4151
4152 /* 802.11 UNI / HyperLan 2 */
4153 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4154 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4155 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4156 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4157 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4158 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4159 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4160 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4161 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4162 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4163 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4164 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4165
4166 /* 802.11 HyperLan 2 */
4167 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4168 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4169 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4170 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4171 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4172 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4173 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4174 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4175 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4176 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4177 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4178 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4179 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4180 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4181 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4182 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4183
4184 /* 802.11 UNII */
4185 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4186 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4187 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4188 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4189 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4190 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4191 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4192 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4193 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4194 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4195 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4196
4197 /* 802.11 Japan */
4198 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4199 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4200 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4201 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4202 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4203 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4204 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4205};
4206
4207/*
55f9321a
ID		 4208 * RF value list for rt3xxx
4209 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4210 */
55f9321a 4211static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4212 {1, 241, 2, 2 },
4213 {2, 241, 2, 7 },
4214 {3, 242, 2, 2 },
4215 {4, 242, 2, 7 },
4216 {5, 243, 2, 2 },
4217 {6, 243, 2, 7 },
4218 {7, 244, 2, 2 },
4219 {8, 244, 2, 7 },
4220 {9, 245, 2, 2 },
4221 {10, 245, 2, 7 },
4222 {11, 246, 2, 2 },
4223 {12, 246, 2, 7 },
4224 {13, 247, 2, 2 },
4225 {14, 248, 2, 4 },
55f9321a
ID		 4226
4227 /* 802.11 UNI / HyperLan 2 */
4228 {36, 0x56, 0, 4},
4229 {38, 0x56, 0, 6},
4230 {40, 0x56, 0, 8},
4231 {44, 0x57, 0, 0},
4232 {46, 0x57, 0, 2},
4233 {48, 0x57, 0, 4},
4234 {52, 0x57, 0, 8},
4235 {54, 0x57, 0, 10},
4236 {56, 0x58, 0, 0},
4237 {60, 0x58, 0, 4},
4238 {62, 0x58, 0, 6},
4239 {64, 0x58, 0, 8},
4240
4241 /* 802.11 HyperLan 2 */
4242 {100, 0x5b, 0, 8},
4243 {102, 0x5b, 0, 10},
4244 {104, 0x5c, 0, 0},
4245 {108, 0x5c, 0, 4},
4246 {110, 0x5c, 0, 6},
4247 {112, 0x5c, 0, 8},
4248 {116, 0x5d, 0, 0},
4249 {118, 0x5d, 0, 2},
4250 {120, 0x5d, 0, 4},
4251 {124, 0x5d, 0, 8},
4252 {126, 0x5d, 0, 10},
4253 {128, 0x5e, 0, 0},
4254 {132, 0x5e, 0, 4},
4255 {134, 0x5e, 0, 6},
4256 {136, 0x5e, 0, 8},
4257 {140, 0x5f, 0, 0},
4258
4259 /* 802.11 UNII */
4260 {149, 0x5f, 0, 9},
4261 {151, 0x5f, 0, 11},
4262 {153, 0x60, 0, 1},
4263 {157, 0x60, 0, 5},
4264 {159, 0x60, 0, 7},
4265 {161, 0x60, 0, 9},
4266 {165, 0x61, 0, 1},
4267 {167, 0x61, 0, 3},
4268 {169, 0x61, 0, 5},
4269 {171, 0x61, 0, 7},
4270 {173, 0x61, 0, 9},
4da2933f
BZ		 4271};
4272
4273int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4274{
4da2933f
BZ		 4275 struct hw_mode_spec *spec = &rt2x00dev->spec;
4276 struct channel_info *info;
8d1331b3
ID		 4277 char *default_power1;
4278 char *default_power2;
4da2933f
BZ		 4279 unsigned int i;
4280 u16 eeprom;
4281
93b6bd26
GW		 4282 /*
4283 * Disable powersaving as default on PCI devices.
4284 */
cea90e55 4285 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 4286 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4287
4da2933f
BZ		 4288 /*
4289 * Initialize all hw fields.
4290 */
4291 rt2x00dev->hw->flags =
4da2933f
BZ		 4292 IEEE80211_HW_SIGNAL_DBM |
4293 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 4294 IEEE80211_HW_PS_NULLFUNC_STACK |
4295 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 4296 /*
4297 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4298 * unless we are capable of sending the buffered frames out after the
4299 * DTIM transmission using rt2x00lib_beacondone. This will send out
4300 * multicast and broadcast traffic immediately instead of buffering it
4301 * infinitly and thus dropping it after some time.
4302 */
4303 if (!rt2x00_is_usb(rt2x00dev))
4304 rt2x00dev->hw->flags |=
4305 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 4306
4da2933f
BZ		 4307 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4308 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4309 rt2x00_eeprom_addr(rt2x00dev,
4310 EEPROM_MAC_ADDR_0));
4311
3f2bee24
HS		 4312 /*
4313 * As rt2800 has a global fallback table we cannot specify
4314 * more then one tx rate per frame but since the hw will
4315 * try several rates (based on the fallback table) we should
ba3b9e5e 4316 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 4317 * we are going to try. Otherwise mac80211 will truncate our
4318 * reported tx rates and the rc algortihm will end up with
4319 * incorrect data.
4320 */
ba3b9e5e
HS		 4321 rt2x00dev->hw->max_rates = 1;
4322 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 4323 rt2x00dev->hw->max_rate_tries = 1;
4324
38c8a566 4325 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 4326
4327 /*
4328 * Initialize hw_mode information.
4329 */
4330 spec->supported_bands = SUPPORT_BAND_2GHZ;
4331 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4332
5122d898 4333 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 4334 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 4335 spec->num_channels = 14;
4336 spec->channels = rf_vals;
55f9321a
ID		 4337 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4338 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 4339 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4340 spec->num_channels = ARRAY_SIZE(rf_vals);
4341 spec->channels = rf_vals;
5122d898
GW		 4342 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4343 rt2x00_rf(rt2x00dev, RF2020) ||
4344 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4345 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882 4346 rt2x00_rf(rt2x00dev, RF3320) ||
aca355b9 4347 rt2x00_rf(rt2x00dev, RF5370) ||
adde5882 4348 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 4349 spec->num_channels = 14;
4350 spec->channels = rf_vals_3x;
4351 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4352 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4353 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4354 spec->channels = rf_vals_3x;
4da2933f
BZ		 4355 }
4356
4357 /*
4358 * Initialize HT information.
4359 */
5122d898 4360 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4361 spec->ht.ht_supported = true;
4362 else
4363 spec->ht.ht_supported = false;
4364
4da2933f 4365 spec->ht.cap =
06443e46 4366 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4367 IEEE80211_HT_CAP_GRN_FLD |
4368 IEEE80211_HT_CAP_SGI_20 |
aa674631 4369 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4370
38c8a566 4371 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4372 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4373
aa674631 4374 spec->ht.cap |=
38c8a566 4375 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4376 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4377
4da2933f
BZ		 4378 spec->ht.ampdu_factor = 3;
4379 spec->ht.ampdu_density = 4;
4380 spec->ht.mcs.tx_params =
4381 IEEE80211_HT_MCS_TX_DEFINED |
4382 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4383 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4384 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4385
38c8a566 4386 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4387 case 3:
4388 spec->ht.mcs.rx_mask[2] = 0xff;
4389 case 2:
4390 spec->ht.mcs.rx_mask[1] = 0xff;
4391 case 1:
4392 spec->ht.mcs.rx_mask[0] = 0xff;
4393 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4394 break;
4395 }
4396
4397 /*
4398 * Create channel information array
4399 */
baeb2ffa 4400 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4401 if (!info)
4402 return -ENOMEM;
4403
4404 spec->channels_info = info;
4405
8d1331b3
ID		 4406 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4407 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4408
4409 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4410 info[i].default_power1 = default_power1[i];
4411 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4412 }
4413
4414 if (spec->num_channels > 14) {
8d1331b3
ID		 4415 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4416 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4417
4418 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4419 info[i].default_power1 = default_power1[i];
4420 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4421 }
4422 }
4423
4424 return 0;
4425}
4426EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4427
2ce33995
BZ		 4428/*
4429 * IEEE80211 stack callback functions.
4430 */
e783619e
HS		 4431void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4432 u16 *iv16)
2ce33995
BZ		 4433{
4434 struct rt2x00_dev *rt2x00dev = hw->priv;
4435 struct mac_iveiv_entry iveiv_entry;
4436 u32 offset;
4437
4438 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4439 rt2800_register_multiread(rt2x00dev, offset,
4440 &iveiv_entry, sizeof(iveiv_entry));
4441
855da5e0
JL		 4442 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4443 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4444}
e783619e 4445EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4446
e783619e 4447int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4448{
4449 struct rt2x00_dev *rt2x00dev = hw->priv;
4450 u32 reg;
4451 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4452
4453 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4454 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4455 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4456
4457 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4458 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4459 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4460
4461 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4462 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4463 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4464
4465 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4466 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4467 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4468
4469 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4470 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4471 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4472
4473 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4474 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4475 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4476
4477 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4478 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4479 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4480
4481 return 0;
4482}
e783619e 4483EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4484
8a3a3c85
EP		 4485int rt2800_conf_tx(struct ieee80211_hw *hw,
4486 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 4487 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4488{
4489 struct rt2x00_dev *rt2x00dev = hw->priv;
4490 struct data_queue *queue;
4491 struct rt2x00_field32 field;
4492 int retval;
4493 u32 reg;
4494 u32 offset;
4495
4496 /*
4497 * First pass the configuration through rt2x00lib, that will
4498 * update the queue settings and validate the input. After that
4499 * we are free to update the registers based on the value
4500 * in the queue parameter.
4501 */
8a3a3c85 4502 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 4503 if (retval)
4504 return retval;
4505
4506 /*
4507 * We only need to perform additional register initialization
4508 * for WMM queues/
4509 */
4510 if (queue_idx >= 4)
4511 return 0;
4512
11f818e0 4513 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4514
4515 /* Update WMM TXOP register */
4516 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4517 field.bit_offset = (queue_idx & 1) * 16;
4518 field.bit_mask = 0xffff << field.bit_offset;
4519
4520 rt2800_register_read(rt2x00dev, offset, &reg);
4521 rt2x00_set_field32(&reg, field, queue->txop);
4522 rt2800_register_write(rt2x00dev, offset, reg);
4523
4524 /* Update WMM registers */
4525 field.bit_offset = queue_idx * 4;
4526 field.bit_mask = 0xf << field.bit_offset;
4527
4528 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4529 rt2x00_set_field32(&reg, field, queue->aifs);
4530 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4531
4532 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4533 rt2x00_set_field32(&reg, field, queue->cw_min);
4534 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4535
4536 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4537 rt2x00_set_field32(&reg, field, queue->cw_max);
4538 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4539
4540 /* Update EDCA registers */
4541 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4542
4543 rt2800_register_read(rt2x00dev, offset, &reg);
4544 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4545 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4546 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4547 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4548 rt2800_register_write(rt2x00dev, offset, reg);
4549
4550 return 0;
4551}
e783619e 4552EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4553
37a41b4a 4554u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 4555{
4556 struct rt2x00_dev *rt2x00dev = hw->priv;
4557 u64 tsf;
4558 u32 reg;
4559
4560 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4561 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4562 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4563 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4564
4565 return tsf;
4566}
e783619e 4567EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4568
e783619e
HS		 4569int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4570 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4571 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4572 u8 buf_size)
1df90809 4573{
af35323d 4574 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 4575 int ret = 0;
4576
af35323d
HS		 4577 /*
4578 * Don't allow aggregation for stations the hardware isn't aware
4579 * of because tx status reports for frames to an unknown station
4580 * always contain wcid=255 and thus we can't distinguish between
4581 * multiple stations which leads to unwanted situations when the
4582 * hw reorders frames due to aggregation.
4583 */
4584 if (sta_priv->wcid < 0)
4585 return 1;
4586
1df90809
HS		 4587 switch (action) {
4588 case IEEE80211_AMPDU_RX_START:
4589 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4590 /*
4591 * The hw itself takes care of setting up BlockAck mechanisms.
4592 * So, we only have to allow mac80211 to nagotiate a BlockAck
4593 * agreement. Once that is done, the hw will BlockAck incoming
4594 * AMPDUs without further setup.
4595 */
1df90809
HS		 4596 break;
4597 case IEEE80211_AMPDU_TX_START:
4598 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4599 break;
4600 case IEEE80211_AMPDU_TX_STOP:
4601 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4602 break;
4603 case IEEE80211_AMPDU_TX_OPERATIONAL:
4604 break;
4605 default:
4e9e58c6 4606 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4607 }
4608
4609 return ret;
4610}
e783619e 4611EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4612
977206d7
HS		 4613int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4614 struct survey_info *survey)
4615{
4616 struct rt2x00_dev *rt2x00dev = hw->priv;
4617 struct ieee80211_conf *conf = &hw->conf;
4618 u32 idle, busy, busy_ext;
4619
4620 if (idx != 0)
4621 return -ENOENT;
4622
4623 survey->channel = conf->channel;
4624
4625 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4626 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4627 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4628
4629 if (idle || busy) {
4630 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4631 SURVEY_INFO_CHANNEL_TIME_BUSY |
4632 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4633
4634 survey->channel_time = (idle + busy) / 1000;
4635 survey->channel_time_busy = busy / 1000;
4636 survey->channel_time_ext_busy = busy_ext / 1000;
4637 }
4638
9931df26
HS		 4639 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4640 survey->filled |= SURVEY_INFO_IN_USE;
4641
977206d7
HS		 4642 return 0;
4643
4644}
4645EXPORT_SYMBOL_GPL(rt2800_get_survey);
4646
a5ea2f02
ID		 4647MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4648MODULE_VERSION(DRV_VERSION);
4649MODULE_DESCRIPTION("Ralink RT2800 library");
4650MODULE_LICENSE("GPL");
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