]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/rt2x00/rt2800lib.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: add field definitions for the TBTT_SYNC_CFG register
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
280 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
282 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
283 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
284 return 0;
285
286 msleep(1);
287 }
288
289 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
290 return -EACCES;
291}
292EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
293
f31c9a8c
ID		 294static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
295{
296 u16 fw_crc;
297 u16 crc;
298
299 /*
300 * The last 2 bytes in the firmware array are the crc checksum itself,
301 * this means that we should never pass those 2 bytes to the crc
302 * algorithm.
303 */
304 fw_crc = (data[len - 2] << 8 | data[len - 1]);
305
306 /*
307 * Use the crc ccitt algorithm.
308 * This will return the same value as the legacy driver which
309 * used bit ordering reversion on the both the firmware bytes
310 * before input input as well as on the final output.
311 * Obviously using crc ccitt directly is much more efficient.
312 */
313 crc = crc_ccitt(~0, data, len - 2);
314
315 /*
316 * There is a small difference between the crc-itu-t + bitrev and
317 * the crc-ccitt crc calculation. In the latter method the 2 bytes
318 * will be swapped, use swab16 to convert the crc to the correct
319 * value.
320 */
321 crc = swab16(crc);
322
323 return fw_crc == crc;
324}
325
326int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
327 const u8 *data, const size_t len)
328{
329 size_t offset = 0;
330 size_t fw_len;
331 bool multiple;
332
333 /*
334 * PCI(e) & SOC devices require firmware with a length
335 * of 8kb. USB devices require firmware files with a length
336 * of 4kb. Certain USB chipsets however require different firmware,
337 * which Ralink only provides attached to the original firmware
338 * file. Thus for USB devices, firmware files have a length
339 * which is a multiple of 4kb.
340 */
341 if (rt2x00_is_usb(rt2x00dev)) {
342 fw_len = 4096;
343 multiple = true;
344 } else {
345 fw_len = 8192;
346 multiple = true;
347 }
348
349 /*
350 * Validate the firmware length
351 */
352 if (len != fw_len && (!multiple || (len % fw_len) != 0))
353 return FW_BAD_LENGTH;
354
355 /*
356 * Check if the chipset requires one of the upper parts
357 * of the firmware.
358 */
359 if (rt2x00_is_usb(rt2x00dev) &&
360 !rt2x00_rt(rt2x00dev, RT2860) &&
361 !rt2x00_rt(rt2x00dev, RT2872) &&
362 !rt2x00_rt(rt2x00dev, RT3070) &&
363 ((len / fw_len) == 1))
364 return FW_BAD_VERSION;
365
366 /*
367 * 8kb firmware files must be checked as if it were
368 * 2 separate firmware files.
369 */
370 while (offset < len) {
371 if (!rt2800_check_firmware_crc(data + offset, fw_len))
372 return FW_BAD_CRC;
373
374 offset += fw_len;
375 }
376
377 return FW_OK;
378}
379EXPORT_SYMBOL_GPL(rt2800_check_firmware);
380
381int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
382 const u8 *data, const size_t len)
383{
384 unsigned int i;
385 u32 reg;
386
b9eca242
ID		 387 /*
388 * If driver doesn't wake up firmware here,
389 * rt2800_load_firmware will hang forever when interface is up again.
390 */
391 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
392
f31c9a8c
ID		 393 /*
394 * Wait for stable hardware.
395 */
5ffddc49 396 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 397 return -EBUSY;
f31c9a8c
ID		 398
399 if (rt2x00_is_pci(rt2x00dev))
400 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
401
402 /*
403 * Disable DMA, will be reenabled later when enabling
404 * the radio.
405 */
406 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
407 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
408 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
409 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
410 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
413
414 /*
415 * Write firmware to the device.
416 */
417 rt2800_drv_write_firmware(rt2x00dev, data, len);
418
419 /*
420 * Wait for device to stabilize.
421 */
422 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
423 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
424 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
425 break;
426 msleep(1);
427 }
428
429 if (i == REGISTER_BUSY_COUNT) {
430 ERROR(rt2x00dev, "PBF system register not ready.\n");
431 return -EBUSY;
432 }
433
434 /*
435 * Initialize firmware.
436 */
437 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
438 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
439 msleep(1);
440
441 return 0;
442}
443EXPORT_SYMBOL_GPL(rt2800_load_firmware);
444
0c5879bc
ID		 445void rt2800_write_tx_data(struct queue_entry *entry,
446 struct txentry_desc *txdesc)
59679b91 447{
0c5879bc 448 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 449 u32 word;
450
451 /*
452 * Initialize TX Info descriptor
453 */
454 rt2x00_desc_read(txwi, 0, &word);
455 rt2x00_set_field32(&word, TXWI_W0_FRAG,
456 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 457 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
458 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 459 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
460 rt2x00_set_field32(&word, TXWI_W0_TS,
461 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
463 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
464 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
465 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
466 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
467 rt2x00_set_field32(&word, TXWI_W0_BW,
468 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
469 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
470 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
471 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
472 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
473 rt2x00_desc_write(txwi, 0, word);
474
475 rt2x00_desc_read(txwi, 1, &word);
476 rt2x00_set_field32(&word, TXWI_W1_ACK,
477 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
478 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
479 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
480 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
481 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
482 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
483 txdesc->key_idx : 0xff);
484 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
485 txdesc->length);
a908a743 486 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
59679b91
GW		 487 rt2x00_desc_write(txwi, 1, word);
488
489 /*
490 * Always write 0 to IV/EIV fields, hardware will insert the IV
491 * from the IVEIV register when TXD_W3_WIV is set to 0.
492 * When TXD_W3_WIV is set to 1 it will use the IV data
493 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
494 * crypto entry in the registers should be used to encrypt the frame.
495 */
496 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
497 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
498}
0c5879bc 499EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 500
74861922 501static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 502{
74861922
ID		 503 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
504 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
505 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
506 u16 eeprom;
507 u8 offset0;
508 u8 offset1;
509 u8 offset2;
510
e5ef5bad 511 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 512 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
513 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
514 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
515 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
516 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
517 } else {
518 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
519 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
520 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
521 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
522 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
523 }
524
525 /*
526 * Convert the value from the descriptor into the RSSI value
527 * If the value in the descriptor is 0, it is considered invalid
528 * and the default (extremely low) rssi value is assumed
529 */
530 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
531 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
532 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
533
534 /*
535 * mac80211 only accepts a single RSSI value. Calculating the
536 * average doesn't deliver a fair answer either since -60:-60 would
537 * be considered equally good as -50:-70 while the second is the one
538 * which gives less energy...
539 */
540 rssi0 = max(rssi0, rssi1);
541 return max(rssi0, rssi2);
542}
543
544void rt2800_process_rxwi(struct queue_entry *entry,
545 struct rxdone_entry_desc *rxdesc)
546{
547 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 548 u32 word;
549
550 rt2x00_desc_read(rxwi, 0, &word);
551
552 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
553 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
554
555 rt2x00_desc_read(rxwi, 1, &word);
556
557 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
558 rxdesc->flags |= RX_FLAG_SHORT_GI;
559
560 if (rt2x00_get_field32(word, RXWI_W1_BW))
561 rxdesc->flags |= RX_FLAG_40MHZ;
562
563 /*
564 * Detect RX rate, always use MCS as signal type.
565 */
566 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
567 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
568 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
569
570 /*
571 * Mask of 0x8 bit to remove the short preamble flag.
572 */
573 if (rxdesc->rate_mode == RATE_MODE_CCK)
574 rxdesc->signal &= ~0x8;
575
576 rt2x00_desc_read(rxwi, 2, &word);
577
74861922
ID		 578 /*
579 * Convert descriptor AGC value to RSSI value.
580 */
581 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 582
583 /*
584 * Remove RXWI descriptor from start of buffer.
585 */
74861922 586 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 587}
588EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
589
3613884d
ID		 590static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
591{
592 __le32 *txwi;
593 u32 word;
594 int wcid, ack, pid;
595 int tx_wcid, tx_ack, tx_pid;
596
597 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
598 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
599 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
600
601 /*
602 * This frames has returned with an IO error,
603 * so the status report is not intended for this
604 * frame.
605 */
606 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
607 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
608 return false;
609 }
610
611 /*
612 * Validate if this TX status report is intended for
613 * this entry by comparing the WCID/ACK/PID fields.
614 */
615 txwi = rt2800_drv_get_txwi(entry);
616
617 rt2x00_desc_read(txwi, 1, &word);
618 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
619 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
620 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
621
622 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
623 WARNING(entry->queue->rt2x00dev,
624 "TX status report missed for queue %d entry %d\n",
625 entry->queue->qid, entry->entry_idx);
626 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
627 return false;
628 }
629
630 return true;
631}
632
14433331
HS		 633void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
634{
635 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
636 struct txdone_entry_desc txdesc;
637 u32 word;
638 u16 mcs, real_mcs;
639 __le32 *txwi;
640
641 /*
642 * Obtain the status about this packet.
643 */
644 txdesc.flags = 0;
645 txwi = rt2800_drv_get_txwi(entry);
646 rt2x00_desc_read(txwi, 0, &word);
647 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
648 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
649
650 /*
651 * Ralink has a retry mechanism using a global fallback
652 * table. We setup this fallback table to try the immediate
653 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
654 * always contains the MCS used for the last transmission, be
655 * it successful or not.
656 */
657 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
658 /*
659 * Transmission succeeded. The number of retries is
660 * mcs - real_mcs
661 */
662 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
663 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
664 } else {
665 /*
666 * Transmission failed. The number of retries is
667 * always 7 in this case (for a total number of 8
668 * frames sent).
669 */
670 __set_bit(TXDONE_FAILURE, &txdesc.flags);
671 txdesc.retry = rt2x00dev->long_retry;
672 }
673
674 /*
675 * the frame was retried at least once
676 * -> hw used fallback rates
677 */
678 if (txdesc.retry)
679 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
680
681 rt2x00lib_txdone(entry, &txdesc);
682}
683EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
684
96481b20
ID		 685void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
686{
687 struct data_queue *queue;
688 struct queue_entry *entry;
96481b20 689 u32 reg;
3613884d 690 u8 pid;
96481b20
ID		 691 int i;
692
693 /*
694 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
695 * at most X times and also stop processing once the TX_STA_FIFO_VALID
696 * flag is not set anymore.
697 *
698 * The legacy drivers use X=TX_RING_SIZE but state in a comment
699 * that the TX_STA_FIFO stack has a size of 16. We stick to our
700 * tx ring size for now.
701 */
702 for (i = 0; i < TX_ENTRIES; i++) {
703 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
704 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
705 break;
706
96481b20
ID		 707 /*
708 * Skip this entry when it contains an invalid
709 * queue identication number.
710 */
3613884d
ID		 711 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
712 if (pid >= QID_RX)
96481b20
ID		 713 continue;
714
3613884d 715 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 716 if (unlikely(!queue))
717 continue;
718
719 /*
720 * Inside each queue, we process each entry in a chronological
721 * order. We first check that the queue is not empty.
722 */
723 entry = NULL;
724 while (!rt2x00queue_empty(queue)) {
725 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 726 if (rt2800_txdone_entry_check(entry, reg))
96481b20 727 break;
96481b20
ID		 728 }
729
730 if (!entry || rt2x00queue_empty(queue))
731 break;
732
14433331 733 rt2800_txdone_entry(entry, reg);
96481b20
ID		 734 }
735}
736EXPORT_SYMBOL_GPL(rt2800_txdone);
737
f0194b2d
GW		 738void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
739{
740 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
741 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
742 unsigned int beacon_base;
743 u32 reg;
744
745 /*
746 * Disable beaconing while we are reloading the beacon data,
747 * otherwise we might be sending out invalid data.
748 */
749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
750 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
751 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
752
753 /*
754 * Add space for the TXWI in front of the skb.
755 */
756 skb_push(entry->skb, TXWI_DESC_SIZE);
757 memset(entry->skb, 0, TXWI_DESC_SIZE);
758
759 /*
760 * Register descriptor details in skb frame descriptor.
761 */
762 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
763 skbdesc->desc = entry->skb->data;
764 skbdesc->desc_len = TXWI_DESC_SIZE;
765
766 /*
767 * Add the TXWI for the beacon to the skb.
768 */
0c5879bc 769 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 770
771 /*
772 * Dump beacon to userspace through debugfs.
773 */
774 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
775
776 /*
777 * Write entire beacon with TXWI to register.
778 */
779 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
780 rt2800_register_multiwrite(rt2x00dev, beacon_base,
781 entry->skb->data, entry->skb->len);
782
783 /*
784 * Enable beaconing again.
785 */
786 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
787 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
788 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
790
791 /*
792 * Clean up beacon skb.
793 */
794 dev_kfree_skb_any(entry->skb);
795 entry->skb = NULL;
796}
50e888ea 797EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 798
fdb87251
HS		 799static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
800 unsigned int beacon_base)
801{
802 int i;
803
804 /*
805 * For the Beacon base registers we only need to clear
806 * the whole TXWI which (when set to 0) will invalidate
807 * the entire beacon.
808 */
809 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
810 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
811}
812
f4450616
BZ		 813#ifdef CONFIG_RT2X00_LIB_DEBUGFS
814const struct rt2x00debug rt2800_rt2x00debug = {
815 .owner = THIS_MODULE,
816 .csr = {
817 .read = rt2800_register_read,
818 .write = rt2800_register_write,
819 .flags = RT2X00DEBUGFS_OFFSET,
820 .word_base = CSR_REG_BASE,
821 .word_size = sizeof(u32),
822 .word_count = CSR_REG_SIZE / sizeof(u32),
823 },
824 .eeprom = {
825 .read = rt2x00_eeprom_read,
826 .write = rt2x00_eeprom_write,
827 .word_base = EEPROM_BASE,
828 .word_size = sizeof(u16),
829 .word_count = EEPROM_SIZE / sizeof(u16),
830 },
831 .bbp = {
832 .read = rt2800_bbp_read,
833 .write = rt2800_bbp_write,
834 .word_base = BBP_BASE,
835 .word_size = sizeof(u8),
836 .word_count = BBP_SIZE / sizeof(u8),
837 },
838 .rf = {
839 .read = rt2x00_rf_read,
840 .write = rt2800_rf_write,
841 .word_base = RF_BASE,
842 .word_size = sizeof(u32),
843 .word_count = RF_SIZE / sizeof(u32),
844 },
845};
846EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
847#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
848
849int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
850{
851 u32 reg;
852
853 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
854 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
855}
856EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
857
858#ifdef CONFIG_RT2X00_LIB_LEDS
859static void rt2800_brightness_set(struct led_classdev *led_cdev,
860 enum led_brightness brightness)
861{
862 struct rt2x00_led *led =
863 container_of(led_cdev, struct rt2x00_led, led_dev);
864 unsigned int enabled = brightness != LED_OFF;
865 unsigned int bg_mode =
866 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
867 unsigned int polarity =
868 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
869 EEPROM_FREQ_LED_POLARITY);
870 unsigned int ledmode =
871 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
872 EEPROM_FREQ_LED_MODE);
873
874 if (led->type == LED_TYPE_RADIO) {
875 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
876 enabled ? 0x20 : 0);
877 } else if (led->type == LED_TYPE_ASSOC) {
878 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
879 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
880 } else if (led->type == LED_TYPE_QUALITY) {
881 /*
882 * The brightness is divided into 6 levels (0 - 5),
883 * The specs tell us the following levels:
884 * 0, 1 ,3, 7, 15, 31
885 * to determine the level in a simple way we can simply
886 * work with bitshifting:
887 * (1 << level) - 1
888 */
889 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
890 (1 << brightness / (LED_FULL / 6)) - 1,
891 polarity);
892 }
893}
894
895static int rt2800_blink_set(struct led_classdev *led_cdev,
896 unsigned long *delay_on, unsigned long *delay_off)
897{
898 struct rt2x00_led *led =
899 container_of(led_cdev, struct rt2x00_led, led_dev);
900 u32 reg;
901
902 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
903 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
904 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 905 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
906
907 return 0;
908}
909
b3579d6a 910static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 911 struct rt2x00_led *led, enum led_type type)
912{
913 led->rt2x00dev = rt2x00dev;
914 led->type = type;
915 led->led_dev.brightness_set = rt2800_brightness_set;
916 led->led_dev.blink_set = rt2800_blink_set;
917 led->flags = LED_INITIALIZED;
918}
f4450616
BZ		 919#endif /* CONFIG_RT2X00_LIB_LEDS */
920
921/*
922 * Configuration handlers.
923 */
924static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
925 struct rt2x00lib_crypto *crypto,
926 struct ieee80211_key_conf *key)
927{
928 struct mac_wcid_entry wcid_entry;
929 struct mac_iveiv_entry iveiv_entry;
930 u32 offset;
931 u32 reg;
932
933 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
934
e4a0ab34
ID		 935 if (crypto->cmd == SET_KEY) {
936 rt2800_register_read(rt2x00dev, offset, &reg);
937 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
938 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
939 /*
940 * Both the cipher as the BSS Idx numbers are split in a main
941 * value of 3 bits, and a extended field for adding one additional
942 * bit to the value.
943 */
944 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
945 (crypto->cipher & 0x7));
946 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
947 (crypto->cipher & 0x8) >> 3);
948 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
949 (crypto->bssidx & 0x7));
950 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
951 (crypto->bssidx & 0x8) >> 3);
952 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
953 rt2800_register_write(rt2x00dev, offset, reg);
954 } else {
955 rt2800_register_write(rt2x00dev, offset, 0);
956 }
f4450616
BZ		 957
958 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
959
960 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
961 if ((crypto->cipher == CIPHER_TKIP) ||
962 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
963 (crypto->cipher == CIPHER_AES))
964 iveiv_entry.iv[3] |= 0x20;
965 iveiv_entry.iv[3] |= key->keyidx << 6;
966 rt2800_register_multiwrite(rt2x00dev, offset,
967 &iveiv_entry, sizeof(iveiv_entry));
968
969 offset = MAC_WCID_ENTRY(key->hw_key_idx);
970
971 memset(&wcid_entry, 0, sizeof(wcid_entry));
972 if (crypto->cmd == SET_KEY)
973 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
974 rt2800_register_multiwrite(rt2x00dev, offset,
975 &wcid_entry, sizeof(wcid_entry));
976}
977
978int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
979 struct rt2x00lib_crypto *crypto,
980 struct ieee80211_key_conf *key)
981{
982 struct hw_key_entry key_entry;
983 struct rt2x00_field32 field;
984 u32 offset;
985 u32 reg;
986
987 if (crypto->cmd == SET_KEY) {
988 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
989
990 memcpy(key_entry.key, crypto->key,
991 sizeof(key_entry.key));
992 memcpy(key_entry.tx_mic, crypto->tx_mic,
993 sizeof(key_entry.tx_mic));
994 memcpy(key_entry.rx_mic, crypto->rx_mic,
995 sizeof(key_entry.rx_mic));
996
997 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
998 rt2800_register_multiwrite(rt2x00dev, offset,
999 &key_entry, sizeof(key_entry));
1000 }
1001
1002 /*
1003 * The cipher types are stored over multiple registers
1004 * starting with SHARED_KEY_MODE_BASE each word will have
1005 * 32 bits and contains the cipher types for 2 bssidx each.
1006 * Using the correct defines correctly will cause overhead,
1007 * so just calculate the correct offset.
1008 */
1009 field.bit_offset = 4 * (key->hw_key_idx % 8);
1010 field.bit_mask = 0x7 << field.bit_offset;
1011
1012 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1013
1014 rt2800_register_read(rt2x00dev, offset, &reg);
1015 rt2x00_set_field32(&reg, field,
1016 (crypto->cmd == SET_KEY) * crypto->cipher);
1017 rt2800_register_write(rt2x00dev, offset, reg);
1018
1019 /*
1020 * Update WCID information
1021 */
1022 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1023
1024 return 0;
1025}
1026EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1027
1028int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1029 struct rt2x00lib_crypto *crypto,
1030 struct ieee80211_key_conf *key)
1031{
1032 struct hw_key_entry key_entry;
1033 u32 offset;
1034
1035 if (crypto->cmd == SET_KEY) {
1036 /*
1037 * 1 pairwise key is possible per AID, this means that the AID
1038 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1039 * last possible shared key entry.
2a0cfeb8
HS		 1040 *
1041 * Since parts of the pairwise key table might be shared with
1042 * the beacon frame buffers 6 & 7 we should only write into the
1043 * first 222 entries.
f4450616 1044 */
2a0cfeb8 1045 if (crypto->aid > (222 - 32))
f4450616
BZ		 1046 return -ENOSPC;
1047
1048 key->hw_key_idx = 32 + crypto->aid;
1049
1050 memcpy(key_entry.key, crypto->key,
1051 sizeof(key_entry.key));
1052 memcpy(key_entry.tx_mic, crypto->tx_mic,
1053 sizeof(key_entry.tx_mic));
1054 memcpy(key_entry.rx_mic, crypto->rx_mic,
1055 sizeof(key_entry.rx_mic));
1056
1057 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1058 rt2800_register_multiwrite(rt2x00dev, offset,
1059 &key_entry, sizeof(key_entry));
1060 }
1061
1062 /*
1063 * Update WCID information
1064 */
1065 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1066
1067 return 0;
1068}
1069EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1070
1071void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1072 const unsigned int filter_flags)
1073{
1074 u32 reg;
1075
1076 /*
1077 * Start configuration steps.
1078 * Note that the version error will always be dropped
1079 * and broadcast frames will always be accepted since
1080 * there is no filter for it at this time.
1081 */
1082 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1083 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1084 !(filter_flags & FIF_FCSFAIL));
1085 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1086 !(filter_flags & FIF_PLCPFAIL));
1087 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1088 !(filter_flags & FIF_PROMISC_IN_BSS));
1089 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1090 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1091 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1092 !(filter_flags & FIF_ALLMULTI));
1093 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1094 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1095 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1096 !(filter_flags & FIF_CONTROL));
1097 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1098 !(filter_flags & FIF_CONTROL));
1099 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1100 !(filter_flags & FIF_CONTROL));
1101 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1102 !(filter_flags & FIF_CONTROL));
1103 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1104 !(filter_flags & FIF_CONTROL));
1105 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1106 !(filter_flags & FIF_PSPOLL));
1107 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1108 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1109 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1110 !(filter_flags & FIF_CONTROL));
1111 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1112}
1113EXPORT_SYMBOL_GPL(rt2800_config_filter);
1114
1115void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1116 struct rt2x00intf_conf *conf, const unsigned int flags)
1117{
f4450616
BZ		 1118 u32 reg;
1119
1120 if (flags & CONFIG_UPDATE_TYPE) {
1121 /*
1122 * Clear current synchronisation setup.
f4450616 1123 */
fdb87251
HS		 1124 rt2800_clear_beacon(rt2x00dev,
1125 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1126 /*
1127 * Enable synchronisation.
1128 */
1129 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1130 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1131 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1132 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1133 (conf->sync == TSF_SYNC_ADHOC ||
1134 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1135 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1136
1137 /*
1138 * Enable pre tbtt interrupt for beaconing modes
1139 */
1140 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1141 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1142 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1143 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1144
f4450616
BZ		 1145 }
1146
1147 if (flags & CONFIG_UPDATE_MAC) {
c600c826
ID		 1148 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1149 reg = le32_to_cpu(conf->mac[1]);
1150 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1151 conf->mac[1] = cpu_to_le32(reg);
1152 }
f4450616
BZ		 1153
1154 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1155 conf->mac, sizeof(conf->mac));
1156 }
1157
1158 if (flags & CONFIG_UPDATE_BSSID) {
c600c826
ID		 1159 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1160 reg = le32_to_cpu(conf->bssid[1]);
1161 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1162 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1163 conf->bssid[1] = cpu_to_le32(reg);
1164 }
f4450616
BZ		 1165
1166 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1167 conf->bssid, sizeof(conf->bssid));
1168 }
1169}
1170EXPORT_SYMBOL_GPL(rt2800_config_intf);
1171
87c1915d
HS		 1172static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1173 struct rt2x00lib_erp *erp)
1174{
1175 bool any_sta_nongf = !!(erp->ht_opmode &
1176 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1177 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1178 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1179 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1180 u32 reg;
1181
1182 /* default protection rate for HT20: OFDM 24M */
1183 mm20_rate = gf20_rate = 0x4004;
1184
1185 /* default protection rate for HT40: duplicate OFDM 24M */
1186 mm40_rate = gf40_rate = 0x4084;
1187
1188 switch (protection) {
1189 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1190 /*
1191 * All STAs in this BSS are HT20/40 but there might be
1192 * STAs not supporting greenfield mode.
1193 * => Disable protection for HT transmissions.
1194 */
1195 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1196
1197 break;
1198 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1199 /*
1200 * All STAs in this BSS are HT20 or HT20/40 but there
1201 * might be STAs not supporting greenfield mode.
1202 * => Protect all HT40 transmissions.
1203 */
1204 mm20_mode = gf20_mode = 0;
1205 mm40_mode = gf40_mode = 2;
1206
1207 break;
1208 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1209 /*
1210 * Nonmember protection:
1211 * According to 802.11n we _should_ protect all
1212 * HT transmissions (but we don't have to).
1213 *
1214 * But if cts_protection is enabled we _shall_ protect
1215 * all HT transmissions using a CCK rate.
1216 *
1217 * And if any station is non GF we _shall_ protect
1218 * GF transmissions.
1219 *
1220 * We decide to protect everything
1221 * -> fall through to mixed mode.
1222 */
1223 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1224 /*
1225 * Legacy STAs are present
1226 * => Protect all HT transmissions.
1227 */
1228 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1229
1230 /*
1231 * If erp protection is needed we have to protect HT
1232 * transmissions with CCK 11M long preamble.
1233 */
1234 if (erp->cts_protection) {
1235 /* don't duplicate RTS/CTS in CCK mode */
1236 mm20_rate = mm40_rate = 0x0003;
1237 gf20_rate = gf40_rate = 0x0003;
1238 }
1239 break;
1240 };
1241
1242 /* check for STAs not supporting greenfield mode */
1243 if (any_sta_nongf)
1244 gf20_mode = gf40_mode = 2;
1245
1246 /* Update HT protection config */
1247 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1248 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1249 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1250 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1251
1252 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1253 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1254 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1255 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1256
1257 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1258 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1259 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1260 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1261
1262 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1263 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1264 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1265 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1266}
1267
02044643
HS		 1268void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1269 u32 changed)
f4450616
BZ		 1270{
1271 u32 reg;
1272
02044643
HS		 1273 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1274 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1275 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1276 !!erp->short_preamble);
1277 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1278 !!erp->short_preamble);
1279 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1280 }
f4450616 1281
02044643
HS		 1282 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1283 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1284 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1285 erp->cts_protection ? 2 : 0);
1286 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1287 }
f4450616 1288
02044643
HS		 1289 if (changed & BSS_CHANGED_BASIC_RATES) {
1290 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1291 erp->basic_rates);
1292 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1293 }
f4450616 1294
02044643
HS		 1295 if (changed & BSS_CHANGED_ERP_SLOT) {
1296 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1297 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1298 erp->slot_time);
1299 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1300
02044643
HS		 1301 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1302 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1303 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1304 }
f4450616 1305
02044643
HS		 1306 if (changed & BSS_CHANGED_BEACON_INT) {
1307 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1308 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1309 erp->beacon_int * 16);
1310 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1311 }
87c1915d
HS		 1312
1313 if (changed & BSS_CHANGED_HT)
1314 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1315}
1316EXPORT_SYMBOL_GPL(rt2800_config_erp);
1317
1318void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1319{
1320 u8 r1;
1321 u8 r3;
1322
1323 rt2800_bbp_read(rt2x00dev, 1, &r1);
1324 rt2800_bbp_read(rt2x00dev, 3, &r3);
1325
1326 /*
1327 * Configure the TX antenna.
1328 */
1329 switch ((int)ant->tx) {
1330 case 1:
1331 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1332 break;
1333 case 2:
1334 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1335 break;
1336 case 3:
e22557f2 1337 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1338 break;
1339 }
1340
1341 /*
1342 * Configure the RX antenna.
1343 */
1344 switch ((int)ant->rx) {
1345 case 1:
1346 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1347 break;
1348 case 2:
1349 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1350 break;
1351 case 3:
1352 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1353 break;
1354 }
1355
1356 rt2800_bbp_write(rt2x00dev, 3, r3);
1357 rt2800_bbp_write(rt2x00dev, 1, r1);
1358}
1359EXPORT_SYMBOL_GPL(rt2800_config_ant);
1360
1361static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1362 struct rt2x00lib_conf *libconf)
1363{
1364 u16 eeprom;
1365 short lna_gain;
1366
1367 if (libconf->rf.channel <= 14) {
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1369 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1370 } else if (libconf->rf.channel <= 64) {
1371 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1372 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1373 } else if (libconf->rf.channel <= 128) {
1374 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1375 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1376 } else {
1377 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1378 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1379 }
1380
1381 rt2x00dev->lna_gain = lna_gain;
1382}
1383
06855ef4
GW		 1384static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1385 struct ieee80211_conf *conf,
1386 struct rf_channel *rf,
1387 struct channel_info *info)
f4450616
BZ		 1388{
1389 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1390
1391 if (rt2x00dev->default_ant.tx == 1)
1392 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1393
1394 if (rt2x00dev->default_ant.rx == 1) {
1395 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1396 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1397 } else if (rt2x00dev->default_ant.rx == 2)
1398 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1399
1400 if (rf->channel > 14) {
1401 /*
1402 * When TX power is below 0, we should increase it by 7 to
1403 * make it a positive value (Minumum value is -7).
1404 * However this means that values between 0 and 7 have
1405 * double meaning, and we should set a 7DBm boost flag.
1406 */
1407 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1408 (info->default_power1 >= 0));
f4450616 1409
8d1331b3
ID		 1410 if (info->default_power1 < 0)
1411 info->default_power1 += 7;
f4450616 1412
8d1331b3 1413 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1414
1415 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1416 (info->default_power2 >= 0));
f4450616 1417
8d1331b3
ID		 1418 if (info->default_power2 < 0)
1419 info->default_power2 += 7;
f4450616 1420
8d1331b3 1421 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1422 } else {
8d1331b3
ID		 1423 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1424 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1425 }
1426
1427 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1428
1429 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1430 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1431 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1432 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1433
1434 udelay(200);
1435
1436 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1437 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1438 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1439 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1440
1441 udelay(200);
1442
1443 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1444 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1445 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1446 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1447}
1448
06855ef4
GW		 1449static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1450 struct ieee80211_conf *conf,
1451 struct rf_channel *rf,
1452 struct channel_info *info)
f4450616
BZ		 1453{
1454 u8 rfcsr;
1455
1456 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1457 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1458
1459 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1460 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1461 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1462
1463 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1464 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1465 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1466
5a673964 1467 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1468 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1469 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1470
f4450616
BZ		 1471 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1472 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1473 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1474
1475 rt2800_rfcsr_write(rt2x00dev, 24,
1476 rt2x00dev->calibration[conf_is_ht40(conf)]);
1477
71976907 1478 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1479 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1480 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1481}
1482
1483static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1484 struct ieee80211_conf *conf,
1485 struct rf_channel *rf,
1486 struct channel_info *info)
1487{
1488 u32 reg;
1489 unsigned int tx_pin;
1490 u8 bbp;
1491
46323e11 1492 if (rf->channel <= 14) {
8d1331b3
ID		 1493 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1494 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1495 } else {
8d1331b3
ID		 1496 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1497 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1498 }
1499
06855ef4
GW		 1500 if (rt2x00_rf(rt2x00dev, RF2020) ||
1501 rt2x00_rf(rt2x00dev, RF3020) ||
1502 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11
ID		 1503 rt2x00_rf(rt2x00dev, RF3022) ||
1504 rt2x00_rf(rt2x00dev, RF3052))
06855ef4 1505 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1506 else
06855ef4 1507 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1508
1509 /*
1510 * Change BBP settings
1511 */
1512 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1513 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1514 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1515 rt2800_bbp_write(rt2x00dev, 86, 0);
1516
1517 if (rf->channel <= 14) {
1518 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1519 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1520 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1521 } else {
1522 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1523 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1524 }
1525 } else {
1526 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1527
1528 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1529 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1530 else
1531 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1532 }
1533
1534 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1535 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1536 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1537 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1538 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1539
1540 tx_pin = 0;
1541
1542 /* Turn on unused PA or LNA when not using 1T or 1R */
1543 if (rt2x00dev->default_ant.tx != 1) {
1544 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1545 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1546 }
1547
1548 /* Turn on unused PA or LNA when not using 1T or 1R */
1549 if (rt2x00dev->default_ant.rx != 1) {
1550 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1551 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1552 }
1553
1554 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1555 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1556 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1557 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1558 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1559 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1560
1561 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1562
1563 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1564 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1565 rt2800_bbp_write(rt2x00dev, 4, bbp);
1566
1567 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1568 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1569 rt2800_bbp_write(rt2x00dev, 3, bbp);
1570
8d0c9b65 1571 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1572 if (conf_is_ht40(conf)) {
1573 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1574 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1575 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1576 } else {
1577 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1578 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1579 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1580 }
1581 }
1582
1583 msleep(1);
1584}
1585
1586static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1587 const int max_txpower)
f4450616 1588{
5e846004
HS		 1589 u8 txpower;
1590 u8 max_value = (u8)max_txpower;
1591 u16 eeprom;
1592 int i;
f4450616 1593 u32 reg;
f4450616 1594 u8 r1;
5e846004 1595 u32 offset;
f4450616 1596
5e846004
HS		 1597 /*
1598 * set to normal tx power mode: +/- 0dBm
1599 */
f4450616 1600 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1601 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1602 rt2800_bbp_write(rt2x00dev, 1, r1);
1603
5e846004
HS		 1604 /*
1605 * The eeprom contains the tx power values for each rate. These
1606 * values map to 100% tx power. Each 16bit word contains four tx
1607 * power values and the order is the same as used in the TX_PWR_CFG
1608 * registers.
1609 */
1610 offset = TX_PWR_CFG_0;
1611
1612 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1613 /* just to be safe */
1614 if (offset > TX_PWR_CFG_4)
1615 break;
1616
1617 rt2800_register_read(rt2x00dev, offset, &reg);
1618
1619 /* read the next four txpower values */
1620 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1621 &eeprom);
1622
1623 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1624 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1625 * TX_PWR_CFG_4: unknown */
1626 txpower = rt2x00_get_field16(eeprom,
1627 EEPROM_TXPOWER_BYRATE_RATE0);
1628 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1629 min(txpower, max_value));
1630
1631 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1632 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1633 * TX_PWR_CFG_4: unknown */
1634 txpower = rt2x00_get_field16(eeprom,
1635 EEPROM_TXPOWER_BYRATE_RATE1);
1636 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1637 min(txpower, max_value));
1638
1639 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1640 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1641 * TX_PWR_CFG_4: unknown */
1642 txpower = rt2x00_get_field16(eeprom,
1643 EEPROM_TXPOWER_BYRATE_RATE2);
1644 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1645 min(txpower, max_value));
1646
1647 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1648 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1649 * TX_PWR_CFG_4: unknown */
1650 txpower = rt2x00_get_field16(eeprom,
1651 EEPROM_TXPOWER_BYRATE_RATE3);
1652 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1653 min(txpower, max_value));
1654
1655 /* read the next four txpower values */
1656 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1657 &eeprom);
1658
1659 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1660 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1661 * TX_PWR_CFG_4: unknown */
1662 txpower = rt2x00_get_field16(eeprom,
1663 EEPROM_TXPOWER_BYRATE_RATE0);
1664 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1665 min(txpower, max_value));
1666
1667 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1668 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1669 * TX_PWR_CFG_4: unknown */
1670 txpower = rt2x00_get_field16(eeprom,
1671 EEPROM_TXPOWER_BYRATE_RATE1);
1672 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1673 min(txpower, max_value));
1674
1675 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1676 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1677 * TX_PWR_CFG_4: unknown */
1678 txpower = rt2x00_get_field16(eeprom,
1679 EEPROM_TXPOWER_BYRATE_RATE2);
1680 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1681 min(txpower, max_value));
1682
1683 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1684 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1685 * TX_PWR_CFG_4: unknown */
1686 txpower = rt2x00_get_field16(eeprom,
1687 EEPROM_TXPOWER_BYRATE_RATE3);
1688 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1689 min(txpower, max_value));
1690
1691 rt2800_register_write(rt2x00dev, offset, reg);
1692
1693 /* next TX_PWR_CFG register */
1694 offset += 4;
1695 }
f4450616
BZ		 1696}
1697
1698static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1699 struct rt2x00lib_conf *libconf)
1700{
1701 u32 reg;
1702
1703 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1704 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1705 libconf->conf->short_frame_max_tx_count);
1706 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1707 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1708 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1709}
1710
1711static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1712 struct rt2x00lib_conf *libconf)
1713{
1714 enum dev_state state =
1715 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1716 STATE_SLEEP : STATE_AWAKE;
1717 u32 reg;
1718
1719 if (state == STATE_SLEEP) {
1720 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1721
1722 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1723 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1724 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1725 libconf->conf->listen_interval - 1);
1726 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1727 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1728
1729 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1730 } else {
f4450616
BZ		 1731 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1732 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1733 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1734 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1735 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1736
1737 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1738 }
1739}
1740
1741void rt2800_config(struct rt2x00_dev *rt2x00dev,
1742 struct rt2x00lib_conf *libconf,
1743 const unsigned int flags)
1744{
1745 /* Always recalculate LNA gain before changing configuration */
1746 rt2800_config_lna_gain(rt2x00dev, libconf);
1747
1748 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1749 rt2800_config_channel(rt2x00dev, libconf->conf,
1750 &libconf->rf, &libconf->channel);
1751 if (flags & IEEE80211_CONF_CHANGE_POWER)
1752 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1753 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1754 rt2800_config_retry_limit(rt2x00dev, libconf);
1755 if (flags & IEEE80211_CONF_CHANGE_PS)
1756 rt2800_config_ps(rt2x00dev, libconf);
1757}
1758EXPORT_SYMBOL_GPL(rt2800_config);
1759
1760/*
1761 * Link tuning
1762 */
1763void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1764{
1765 u32 reg;
1766
1767 /*
1768 * Update FCS error count from register.
1769 */
1770 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1771 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1772}
1773EXPORT_SYMBOL_GPL(rt2800_link_stats);
1774
1775static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1776{
1777 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1778 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1779 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1780 rt2x00_rt(rt2x00dev, RT3090) ||
1781 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1782 return 0x1c + (2 * rt2x00dev->lna_gain);
1783 else
1784 return 0x2e + rt2x00dev->lna_gain;
1785 }
1786
1787 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1788 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1789 else
1790 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1791}
1792
1793static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1794 struct link_qual *qual, u8 vgc_level)
1795{
1796 if (qual->vgc_level != vgc_level) {
1797 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1798 qual->vgc_level = vgc_level;
1799 qual->vgc_level_reg = vgc_level;
1800 }
1801}
1802
1803void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1804{
1805 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1806}
1807EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1808
1809void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1810 const u32 count)
1811{
8d0c9b65 1812 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1813 return;
1814
1815 /*
1816 * When RSSI is better then -80 increase VGC level with 0x10
1817 */
1818 rt2800_set_vgc(rt2x00dev, qual,
1819 rt2800_get_default_vgc(rt2x00dev) +
1820 ((qual->rssi > -80) * 0x10));
1821}
1822EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1823
1824/*
1825 * Initialization functions.
1826 */
b9a07ae9 1827static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1828{
1829 u32 reg;
d5385bfc 1830 u16 eeprom;
fcf51541 1831 unsigned int i;
e3a896b9 1832 int ret;
fcf51541 1833
a9dce149
GW		 1834 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1835 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1836 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1837 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1838 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1839 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1840 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1841
e3a896b9
GW		 1842 ret = rt2800_drv_init_registers(rt2x00dev);
1843 if (ret)
1844 return ret;
fcf51541
BZ		 1845
1846 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1847 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1848 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1849 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1850 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1851 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1852
1853 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1854 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1855 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1856 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1857 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1858 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1859
1860 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1861 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1862
1863 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1864
1865 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1866 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1867 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1868 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1869 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1870 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1871 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1872 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1873
a9dce149
GW		 1874 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1875
1876 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1877 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1878 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1879 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1880
64522957 1881 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1882 rt2x00_rt(rt2x00dev, RT3090) ||
1883 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1884 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1885 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1886 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1887 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1888 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1889 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1890 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1891 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1892 0x0000002c);
1893 else
1894 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1895 0x0000000f);
1896 } else {
1897 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1898 }
d5385bfc 1899 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1900 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1901
1902 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1903 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1904 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1905 } else {
1906 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1907 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1908 }
c295a81d
HS		 1909 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1910 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1911 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1912 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1913 } else {
1914 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1915 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1916 }
1917
1918 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1919 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1920 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1921 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1922 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1923 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1924 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1925 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1926 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1927 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1928
1929 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1930 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1931 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1932 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1933 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1934
1935 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1936 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1937 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1938 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1939 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1940 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1941 else
1942 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1943 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1944 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1945 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1946
a9dce149
GW		 1947 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1948 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1949 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1950 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1951 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1952 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1953 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1954 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1955 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1956
fcf51541
BZ		 1957 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1958
a9dce149
GW		 1959 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1960 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1961 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1962 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1963 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1964 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1965 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1966 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1967
fcf51541
BZ		 1968 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1969 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1970 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1971 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1972 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1973 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1974 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1975 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1976 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1977
1978 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1979 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1980 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1981 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1982 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1983 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1984 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1985 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1986 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1987 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1988 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1989 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1990
1991 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1992 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1993 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1994 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1995 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1996 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1997 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1998 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1999 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2000 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2001 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2002 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2003
2004 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2005 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2006 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2007 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2008 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2009 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2010 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2011 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2012 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2013 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2014 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2015 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2016
2017 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2018 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2019 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2020 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2021 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2022 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2023 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2024 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2025 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2026 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2027 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2028 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2029
2030 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2031 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2032 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2033 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2034 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2035 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2036 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2037 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2038 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2039 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2040 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2041 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2042
2043 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2044 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2045 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2046 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2047 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2048 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2049 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2050 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2051 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2052 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2053 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2054 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2055
cea90e55 2056 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2057 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2058
2059 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2060 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2061 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2062 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2063 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2064 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2065 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2066 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2067 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2068 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2069 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2070 }
2071
2072 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
2073 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2074
2075 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2076 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2077 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2078 IEEE80211_MAX_RTS_THRESHOLD);
2079 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2080 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2081
2082 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2083
a21c2ab4
HS		 2084 /*
2085 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2086 * time should be set to 16. However, the original Ralink driver uses
2087 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2088 * connection problems with 11g + CTS protection. Hence, use the same
2089 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2090 */
a9dce149 2091 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2092 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2093 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2094 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2095 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2096 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2097 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2098
fcf51541
BZ		 2099 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2100
2101 /*
2102 * ASIC will keep garbage value after boot, clear encryption keys.
2103 */
2104 for (i = 0; i < 4; i++)
2105 rt2800_register_write(rt2x00dev,
2106 SHARED_KEY_MODE_ENTRY(i), 0);
2107
2108 for (i = 0; i < 256; i++) {
2109 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2110 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2111 wcid, sizeof(wcid));
2112
2113 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2114 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2115 }
2116
2117 /*
2118 * Clear all beacons
fcf51541 2119 */
fdb87251
HS		 2120 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2121 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2122 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2123 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2124 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2125 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2126 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2127 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2128
cea90e55 2129 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2130 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2131 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2132 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2133 }
2134
2135 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2136 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2137 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2138 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2139 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2140 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2141 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2142 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2143 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2144 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2145
2146 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2147 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2148 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2149 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2150 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2151 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2152 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2153 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2154 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2155 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2156
2157 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2158 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2159 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2160 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2161 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2162 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2163 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2164 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2165 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2166 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2167
2168 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2169 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2170 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2171 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2172 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2173 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2174
47ee3eb1
HS		 2175 /*
2176 * Do not force the BA window size, we use the TXWI to set it
2177 */
2178 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2179 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2180 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2181 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2182
fcf51541
BZ		 2183 /*
2184 * We must clear the error counters.
2185 * These registers are cleared on read,
2186 * so we may pass a useless variable to store the value.
2187 */
2188 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2189 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2190 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2191 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2192 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2193 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2194
9f926fb5
HS		 2195 /*
2196 * Setup leadtime for pre tbtt interrupt to 6ms
2197 */
2198 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2199 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2200 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2201
fcf51541
BZ		 2202 return 0;
2203}
fcf51541
BZ		 2204
2205static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2206{
2207 unsigned int i;
2208 u32 reg;
2209
2210 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2211 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2212 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2213 return 0;
2214
2215 udelay(REGISTER_BUSY_DELAY);
2216 }
2217
2218 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2219 return -EACCES;
2220}
2221
2222static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2223{
2224 unsigned int i;
2225 u8 value;
2226
2227 /*
2228 * BBP was enabled after firmware was loaded,
2229 * but we need to reactivate it now.
2230 */
2231 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2232 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2233 msleep(1);
2234
2235 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2236 rt2800_bbp_read(rt2x00dev, 0, &value);
2237 if ((value != 0xff) && (value != 0x00))
2238 return 0;
2239 udelay(REGISTER_BUSY_DELAY);
2240 }
2241
2242 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2243 return -EACCES;
2244}
2245
b9a07ae9 2246static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2247{
2248 unsigned int i;
2249 u16 eeprom;
2250 u8 reg_id;
2251 u8 value;
2252
2253 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2254 rt2800_wait_bbp_ready(rt2x00dev)))
2255 return -EACCES;
2256
baff8006
HS		 2257 if (rt2800_is_305x_soc(rt2x00dev))
2258 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2259
fcf51541
BZ		 2260 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2261 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2262
2263 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2264 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2265 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2266 } else {
2267 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2268 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2269 }
2270
fcf51541 2271 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2272
d5385bfc 2273 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2274 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2275 rt2x00_rt(rt2x00dev, RT3090) ||
2276 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2277 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2278 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2279 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2280 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2281 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2282 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2283 } else {
2284 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2285 }
2286
fcf51541
BZ		 2287 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2288 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2289
5ed8f458 2290 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2291 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2292 else
2293 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2294
fcf51541
BZ		 2295 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2296 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2297 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2298
d5385bfc 2299 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2300 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2301 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2302 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2303 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2304 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2305 else
2306 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2307
baff8006
HS		 2308 if (rt2800_is_305x_soc(rt2x00dev))
2309 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2310 else
2311 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2312 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2313
64522957 2314 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2315 rt2x00_rt(rt2x00dev, RT3090) ||
2316 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2317 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2318
d5385bfc
GW		 2319 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2320 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2321 value |= 0x20;
2322 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2323 value &= ~0x02;
fcf51541 2324
d5385bfc 2325 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2326 }
2327
fcf51541
BZ		 2328
2329 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2330 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2331
2332 if (eeprom != 0xffff && eeprom != 0x0000) {
2333 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2334 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2335 rt2800_bbp_write(rt2x00dev, reg_id, value);
2336 }
2337 }
2338
2339 return 0;
2340}
fcf51541
BZ		 2341
2342static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2343 bool bw40, u8 rfcsr24, u8 filter_target)
2344{
2345 unsigned int i;
2346 u8 bbp;
2347 u8 rfcsr;
2348 u8 passband;
2349 u8 stopband;
2350 u8 overtuned = 0;
2351
2352 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2353
2354 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2355 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2356 rt2800_bbp_write(rt2x00dev, 4, bbp);
2357
2358 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2359 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2360 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2361
2362 /*
2363 * Set power & frequency of passband test tone
2364 */
2365 rt2800_bbp_write(rt2x00dev, 24, 0);
2366
2367 for (i = 0; i < 100; i++) {
2368 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2369 msleep(1);
2370
2371 rt2800_bbp_read(rt2x00dev, 55, &passband);
2372 if (passband)
2373 break;
2374 }
2375
2376 /*
2377 * Set power & frequency of stopband test tone
2378 */
2379 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2380
2381 for (i = 0; i < 100; i++) {
2382 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2383 msleep(1);
2384
2385 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2386
2387 if ((passband - stopband) <= filter_target) {
2388 rfcsr24++;
2389 overtuned += ((passband - stopband) == filter_target);
2390 } else
2391 break;
2392
2393 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2394 }
2395
2396 rfcsr24 -= !!overtuned;
2397
2398 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2399 return rfcsr24;
2400}
2401
b9a07ae9 2402static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2403{
2404 u8 rfcsr;
2405 u8 bbp;
8cdd15e0
GW		 2406 u32 reg;
2407 u16 eeprom;
fcf51541 2408
d5385bfc 2409 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2410 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2411 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2412 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2413 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2414 return 0;
2415
fcf51541
BZ		 2416 /*
2417 * Init RF calibration.
2418 */
2419 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2420 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2421 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2422 msleep(1);
2423 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2424 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2425
d5385bfc 2426 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2427 rt2x00_rt(rt2x00dev, RT3071) ||
2428 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2429 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2430 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2431 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2432 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2433 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2434 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2435 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2436 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2437 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2438 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2439 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2440 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2441 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2442 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2443 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2444 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2445 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2446 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2447 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2448 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2449 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2450 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2451 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2452 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2453 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2454 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2455 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2456 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2457 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2458 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2459 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2460 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2461 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2462 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2463 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2464 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2465 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2466 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2467 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2468 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2469 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2470 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2471 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2472 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2473 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2474 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2475 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2476 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2477 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2478 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2479 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2480 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2481 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2482 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2483 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2484 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2485 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2486 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2487 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2488 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2489 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2490 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2491 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2492 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2493 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2494 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2495 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2496 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2497 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2498 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2499 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2500 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2501 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2502 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2503 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2504 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2505 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2506 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2507 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2508 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2509 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2510 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2511 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2512 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2513 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2514 return 0;
8cdd15e0
GW		 2515 }
2516
2517 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2518 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2519 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2520 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2521 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2522 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2523 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2524 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2525 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2526 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2527
2528 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2529
2530 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2531 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2532 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2533 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2534 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2535 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2536 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2537 else
2538 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2539 }
2540 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2541 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2542 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2543 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2544 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2545 }
2546
2547 /*
2548 * Set RX Filter calibration for 20MHz and 40MHz
2549 */
8cdd15e0
GW		 2550 if (rt2x00_rt(rt2x00dev, RT3070)) {
2551 rt2x00dev->calibration[0] =
2552 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2553 rt2x00dev->calibration[1] =
2554 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2555 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2556 rt2x00_rt(rt2x00dev, RT3090) ||
2557 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2558 rt2x00dev->calibration[0] =
2559 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2560 rt2x00dev->calibration[1] =
2561 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2562 }
fcf51541
BZ		 2563
2564 /*
2565 * Set back to initial state
2566 */
2567 rt2800_bbp_write(rt2x00dev, 24, 0);
2568
2569 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2570 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2571 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2572
2573 /*
2574 * set BBP back to BW20
2575 */
2576 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2577 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2578 rt2800_bbp_write(rt2x00dev, 4, bbp);
2579
d5385bfc 2580 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2581 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2582 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2583 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2584 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2585
2586 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2587 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2588 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2589
2590 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2591 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2592 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2593 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2594 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2595 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2596 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2597 }
8cdd15e0
GW		 2598 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2599 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2600 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2601 rt2x00_get_field16(eeprom,
2602 EEPROM_TXMIXER_GAIN_BG_VAL));
2603 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2604
64522957
GW		 2605 if (rt2x00_rt(rt2x00dev, RT3090)) {
2606 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2607
2608 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2609 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2610 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2611 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2612 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2613
2614 rt2800_bbp_write(rt2x00dev, 138, bbp);
2615 }
2616
2617 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2618 rt2x00_rt(rt2x00dev, RT3090) ||
2619 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2620 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2621 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2622 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2623 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2624 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2625 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2626 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2627
2628 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2629 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2630 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2631
2632 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2633 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2634 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2635
2636 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2637 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2638 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2639 }
2640
2641 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2642 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2643 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2644 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2645 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2646 else
2647 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2648 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2649 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2650 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2651 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2652 }
2653
fcf51541
BZ		 2654 return 0;
2655}
b9a07ae9
ID		 2656
2657int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2658{
2659 u32 reg;
2660 u16 word;
2661
2662 /*
2663 * Initialize all registers.
2664 */
2665 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2666 rt2800_init_registers(rt2x00dev) ||
2667 rt2800_init_bbp(rt2x00dev) ||
2668 rt2800_init_rfcsr(rt2x00dev)))
2669 return -EIO;
2670
2671 /*
2672 * Send signal to firmware during boot time.
2673 */
2674 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2675
2676 if (rt2x00_is_usb(rt2x00dev) &&
2677 (rt2x00_rt(rt2x00dev, RT3070) ||
2678 rt2x00_rt(rt2x00dev, RT3071) ||
2679 rt2x00_rt(rt2x00dev, RT3572))) {
2680 udelay(200);
2681 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2682 udelay(10);
2683 }
2684
2685 /*
2686 * Enable RX.
2687 */
2688 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2689 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2690 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2691 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2692
2693 udelay(50);
2694
2695 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2696 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2697 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2698 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2699 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2700 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2701
2702 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2703 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2704 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2705 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2706
2707 /*
2708 * Initialize LED control
2709 */
2710 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2711 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2712 word & 0xff, (word >> 8) & 0xff);
2713
2714 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2715 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2716 word & 0xff, (word >> 8) & 0xff);
2717
2718 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2719 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2720 word & 0xff, (word >> 8) & 0xff);
2721
2722 return 0;
2723}
2724EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2725
2726void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2727{
2728 u32 reg;
2729
2730 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2731 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2732 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2733 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2734 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2735 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2736 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2737
2738 /* Wait for DMA, ignore error */
2739 rt2800_wait_wpdma_ready(rt2x00dev);
2740
2741 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2742 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2743 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2744 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2745
2746 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2747 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2748}
2749EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2750
30e84034
BZ		 2751int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2752{
2753 u32 reg;
2754
2755 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2756
2757 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2758}
2759EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2760
2761static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2762{
2763 u32 reg;
2764
31a4cf1f
GW		 2765 mutex_lock(&rt2x00dev->csr_mutex);
2766
2767 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2768 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2769 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2770 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2771 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2772
2773 /* Wait until the EEPROM has been loaded */
2774 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2775
2776 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2777 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2778 (u32 *)&rt2x00dev->eeprom[i]);
2779 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2780 (u32 *)&rt2x00dev->eeprom[i + 2]);
2781 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2782 (u32 *)&rt2x00dev->eeprom[i + 4]);
2783 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2784 (u32 *)&rt2x00dev->eeprom[i + 6]);
2785
2786 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2787}
2788
2789void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2790{
2791 unsigned int i;
2792
2793 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2794 rt2800_efuse_read(rt2x00dev, i);
2795}
2796EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2797
38bd7b8a
BZ		 2798int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2799{
2800 u16 word;
2801 u8 *mac;
2802 u8 default_lna_gain;
2803
2804 /*
2805 * Start validation of the data that has been read.
2806 */
2807 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2808 if (!is_valid_ether_addr(mac)) {
2809 random_ether_addr(mac);
2810 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2811 }
2812
2813 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2814 if (word == 0xffff) {
2815 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2816 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2817 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2818 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2819 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2820 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2821 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2822 /*
2823 * There is a max of 2 RX streams for RT28x0 series
2824 */
2825 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2826 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2827 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2828 }
2829
2830 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2831 if (word == 0xffff) {
2832 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2833 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2834 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2835 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2836 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2837 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2838 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2839 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2840 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2841 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2842 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2843 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2844 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2845 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2846 }
2847
2848 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2849 if ((word & 0x00ff) == 0x00ff) {
2850 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2851 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2852 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2853 }
2854 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2855 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2856 LED_MODE_TXRX_ACTIVITY);
2857 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2858 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2859 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2860 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2861 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2862 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2863 }
2864
2865 /*
2866 * During the LNA validation we are going to use
2867 * lna0 as correct value. Note that EEPROM_LNA
2868 * is never validated.
2869 */
2870 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2871 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2872
2873 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2874 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2875 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2876 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2877 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2878 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2879
2880 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2881 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2882 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2883 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2884 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2885 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2886 default_lna_gain);
2887 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2888
2889 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2890 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2891 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2892 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2893 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2894 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2895
2896 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2897 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2898 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2899 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2900 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2901 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2902 default_lna_gain);
2903 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2904
8d1331b3
ID		 2905 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2906 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2907 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2908 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2909 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2910 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2911
38bd7b8a
BZ		 2912 return 0;
2913}
2914EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2915
2916int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2917{
2918 u32 reg;
2919 u16 value;
2920 u16 eeprom;
2921
2922 /*
2923 * Read EEPROM word for configuration.
2924 */
2925 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2926
2927 /*
2928 * Identify RF chipset.
2929 */
2930 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2931 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2932
49e721ec
GW		 2933 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2934 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2935
2936 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2937 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2938 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2939 !rt2x00_rt(rt2x00dev, RT3070) &&
2940 !rt2x00_rt(rt2x00dev, RT3071) &&
2941 !rt2x00_rt(rt2x00dev, RT3090) &&
2942 !rt2x00_rt(rt2x00dev, RT3390) &&
2943 !rt2x00_rt(rt2x00dev, RT3572)) {
2944 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2945 return -ENODEV;
f273fe55 2946 }
714fa663 2947
5122d898
GW		 2948 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2949 !rt2x00_rf(rt2x00dev, RF2850) &&
2950 !rt2x00_rf(rt2x00dev, RF2720) &&
2951 !rt2x00_rf(rt2x00dev, RF2750) &&
2952 !rt2x00_rf(rt2x00dev, RF3020) &&
2953 !rt2x00_rf(rt2x00dev, RF2020) &&
2954 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2955 !rt2x00_rf(rt2x00dev, RF3022) &&
2956 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2957 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2958 return -ENODEV;
2959 }
2960
2961 /*
2962 * Identify default antenna configuration.
2963 */
2964 rt2x00dev->default_ant.tx =
2965 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2966 rt2x00dev->default_ant.rx =
2967 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2968
2969 /*
2970 * Read frequency offset and RF programming sequence.
2971 */
2972 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2973 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2974
2975 /*
2976 * Read external LNA informations.
2977 */
2978 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2979
2980 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2981 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2982 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2983 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2984
2985 /*
2986 * Detect if this device has an hardware controlled radio.
2987 */
2988 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2989 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2990
2991 /*
2992 * Store led settings, for correct led behaviour.
2993 */
2994#ifdef CONFIG_RT2X00_LIB_LEDS
2995 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2996 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2997 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2998
2999 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3000#endif /* CONFIG_RT2X00_LIB_LEDS */
3001
3002 return 0;
3003}
3004EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3005
4da2933f 3006/*
55f9321a 3007 * RF value list for rt28xx
4da2933f
BZ		 3008 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3009 */
3010static const struct rf_channel rf_vals[] = {
3011 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3012 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3013 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3014 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3015 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3016 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3017 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3018 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3019 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3020 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3021 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3022 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3023 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3024 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3025
3026 /* 802.11 UNI / HyperLan 2 */
3027 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3028 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3029 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3030 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3031 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3032 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3033 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3034 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3035 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3036 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3037 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3038 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3039
3040 /* 802.11 HyperLan 2 */
3041 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3042 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3043 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3044 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3045 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3046 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3047 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3048 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3049 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3050 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3051 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3052 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3053 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3054 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3055 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3056 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3057
3058 /* 802.11 UNII */
3059 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3060 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3061 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3062 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3063 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3064 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3065 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3066 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3067 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3068 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3069 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3070
3071 /* 802.11 Japan */
3072 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3073 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3074 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3075 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3076 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3077 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3078 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3079};
3080
3081/*
55f9321a
ID		 3082 * RF value list for rt3xxx
3083 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3084 */
55f9321a 3085static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3086 {1, 241, 2, 2 },
3087 {2, 241, 2, 7 },
3088 {3, 242, 2, 2 },
3089 {4, 242, 2, 7 },
3090 {5, 243, 2, 2 },
3091 {6, 243, 2, 7 },
3092 {7, 244, 2, 2 },
3093 {8, 244, 2, 7 },
3094 {9, 245, 2, 2 },
3095 {10, 245, 2, 7 },
3096 {11, 246, 2, 2 },
3097 {12, 246, 2, 7 },
3098 {13, 247, 2, 2 },
3099 {14, 248, 2, 4 },
55f9321a
ID		 3100
3101 /* 802.11 UNI / HyperLan 2 */
3102 {36, 0x56, 0, 4},
3103 {38, 0x56, 0, 6},
3104 {40, 0x56, 0, 8},
3105 {44, 0x57, 0, 0},
3106 {46, 0x57, 0, 2},
3107 {48, 0x57, 0, 4},
3108 {52, 0x57, 0, 8},
3109 {54, 0x57, 0, 10},
3110 {56, 0x58, 0, 0},
3111 {60, 0x58, 0, 4},
3112 {62, 0x58, 0, 6},
3113 {64, 0x58, 0, 8},
3114
3115 /* 802.11 HyperLan 2 */
3116 {100, 0x5b, 0, 8},
3117 {102, 0x5b, 0, 10},
3118 {104, 0x5c, 0, 0},
3119 {108, 0x5c, 0, 4},
3120 {110, 0x5c, 0, 6},
3121 {112, 0x5c, 0, 8},
3122 {116, 0x5d, 0, 0},
3123 {118, 0x5d, 0, 2},
3124 {120, 0x5d, 0, 4},
3125 {124, 0x5d, 0, 8},
3126 {126, 0x5d, 0, 10},
3127 {128, 0x5e, 0, 0},
3128 {132, 0x5e, 0, 4},
3129 {134, 0x5e, 0, 6},
3130 {136, 0x5e, 0, 8},
3131 {140, 0x5f, 0, 0},
3132
3133 /* 802.11 UNII */
3134 {149, 0x5f, 0, 9},
3135 {151, 0x5f, 0, 11},
3136 {153, 0x60, 0, 1},
3137 {157, 0x60, 0, 5},
3138 {159, 0x60, 0, 7},
3139 {161, 0x60, 0, 9},
3140 {165, 0x61, 0, 1},
3141 {167, 0x61, 0, 3},
3142 {169, 0x61, 0, 5},
3143 {171, 0x61, 0, 7},
3144 {173, 0x61, 0, 9},
4da2933f
BZ		 3145};
3146
3147int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3148{
4da2933f
BZ		 3149 struct hw_mode_spec *spec = &rt2x00dev->spec;
3150 struct channel_info *info;
8d1331b3
ID		 3151 char *default_power1;
3152 char *default_power2;
4da2933f 3153 unsigned int i;
8d1331b3 3154 unsigned short max_power;
4da2933f
BZ		 3155 u16 eeprom;
3156
93b6bd26
GW		 3157 /*
3158 * Disable powersaving as default on PCI devices.
3159 */
cea90e55 3160 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3161 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3162
4da2933f
BZ		 3163 /*
3164 * Initialize all hw fields.
3165 */
3166 rt2x00dev->hw->flags =
3167 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3168 IEEE80211_HW_SIGNAL_DBM |
3169 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3170 IEEE80211_HW_PS_NULLFUNC_STACK |
3171 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 3172
4da2933f
BZ		 3173 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3174 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3175 rt2x00_eeprom_addr(rt2x00dev,
3176 EEPROM_MAC_ADDR_0));
3177
3f2bee24
HS		 3178 /*
3179 * As rt2800 has a global fallback table we cannot specify
3180 * more then one tx rate per frame but since the hw will
3181 * try several rates (based on the fallback table) we should
3182 * still initialize max_rates to the maximum number of rates
3183 * we are going to try. Otherwise mac80211 will truncate our
3184 * reported tx rates and the rc algortihm will end up with
3185 * incorrect data.
3186 */
3187 rt2x00dev->hw->max_rates = 7;
3188 rt2x00dev->hw->max_rate_tries = 1;
3189
4da2933f
BZ		 3190 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3191
3192 /*
3193 * Initialize hw_mode information.
3194 */
3195 spec->supported_bands = SUPPORT_BAND_2GHZ;
3196 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3197
5122d898 3198 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3199 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3200 spec->num_channels = 14;
3201 spec->channels = rf_vals;
55f9321a
ID		 3202 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3203 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3204 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3205 spec->num_channels = ARRAY_SIZE(rf_vals);
3206 spec->channels = rf_vals;
5122d898
GW		 3207 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3208 rt2x00_rf(rt2x00dev, RF2020) ||
3209 rt2x00_rf(rt2x00dev, RF3021) ||
3210 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 3211 spec->num_channels = 14;
3212 spec->channels = rf_vals_3x;
3213 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3214 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3215 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3216 spec->channels = rf_vals_3x;
4da2933f
BZ		 3217 }
3218
3219 /*
3220 * Initialize HT information.
3221 */
5122d898 3222 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3223 spec->ht.ht_supported = true;
3224 else
3225 spec->ht.ht_supported = false;
3226
4da2933f 3227 spec->ht.cap =
06443e46 3228 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3229 IEEE80211_HT_CAP_GRN_FLD |
3230 IEEE80211_HT_CAP_SGI_20 |
aa674631 3231 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 3232
3233 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3234 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3235
aa674631
ID		 3236 spec->ht.cap |=
3237 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3238 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3239
4da2933f
BZ		 3240 spec->ht.ampdu_factor = 3;
3241 spec->ht.ampdu_density = 4;
3242 spec->ht.mcs.tx_params =
3243 IEEE80211_HT_MCS_TX_DEFINED |
3244 IEEE80211_HT_MCS_TX_RX_DIFF |
3245 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3246 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3247
3248 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3249 case 3:
3250 spec->ht.mcs.rx_mask[2] = 0xff;
3251 case 2:
3252 spec->ht.mcs.rx_mask[1] = 0xff;
3253 case 1:
3254 spec->ht.mcs.rx_mask[0] = 0xff;
3255 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3256 break;
3257 }
3258
3259 /*
3260 * Create channel information array
3261 */
3262 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3263 if (!info)
3264 return -ENOMEM;
3265
3266 spec->channels_info = info;
3267
8d1331b3
ID		 3268 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3269 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3270 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3271 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3272
3273 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3274 info[i].max_power = max_power;
3275 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3276 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3277 }
3278
3279 if (spec->num_channels > 14) {
8d1331b3
ID		 3280 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3281 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3282 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3283
3284 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3285 info[i].max_power = max_power;
3286 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3287 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3288 }
3289 }
3290
3291 return 0;
3292}
3293EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3294
2ce33995
BZ		 3295/*
3296 * IEEE80211 stack callback functions.
3297 */
e783619e
HS		 3298void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3299 u16 *iv16)
2ce33995
BZ		 3300{
3301 struct rt2x00_dev *rt2x00dev = hw->priv;
3302 struct mac_iveiv_entry iveiv_entry;
3303 u32 offset;
3304
3305 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3306 rt2800_register_multiread(rt2x00dev, offset,
3307 &iveiv_entry, sizeof(iveiv_entry));
3308
855da5e0
JL		 3309 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3310 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3311}
e783619e 3312EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3313
e783619e 3314int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3315{
3316 struct rt2x00_dev *rt2x00dev = hw->priv;
3317 u32 reg;
3318 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3319
3320 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3321 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3322 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3323
3324 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3325 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3326 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3327
3328 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3329 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3330 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3331
3332 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3333 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3334 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3335
3336 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3337 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3338 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3339
3340 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3341 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3342 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3343
3344 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3345 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3346 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3347
3348 return 0;
3349}
e783619e 3350EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3351
e783619e
HS		 3352int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3353 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3354{
3355 struct rt2x00_dev *rt2x00dev = hw->priv;
3356 struct data_queue *queue;
3357 struct rt2x00_field32 field;
3358 int retval;
3359 u32 reg;
3360 u32 offset;
3361
3362 /*
3363 * First pass the configuration through rt2x00lib, that will
3364 * update the queue settings and validate the input. After that
3365 * we are free to update the registers based on the value
3366 * in the queue parameter.
3367 */
3368 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3369 if (retval)
3370 return retval;
3371
3372 /*
3373 * We only need to perform additional register initialization
3374 * for WMM queues/
3375 */
3376 if (queue_idx >= 4)
3377 return 0;
3378
3379 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3380
3381 /* Update WMM TXOP register */
3382 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3383 field.bit_offset = (queue_idx & 1) * 16;
3384 field.bit_mask = 0xffff << field.bit_offset;
3385
3386 rt2800_register_read(rt2x00dev, offset, &reg);
3387 rt2x00_set_field32(&reg, field, queue->txop);
3388 rt2800_register_write(rt2x00dev, offset, reg);
3389
3390 /* Update WMM registers */
3391 field.bit_offset = queue_idx * 4;
3392 field.bit_mask = 0xf << field.bit_offset;
3393
3394 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3395 rt2x00_set_field32(&reg, field, queue->aifs);
3396 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3397
3398 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3399 rt2x00_set_field32(&reg, field, queue->cw_min);
3400 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3401
3402 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3403 rt2x00_set_field32(&reg, field, queue->cw_max);
3404 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3405
3406 /* Update EDCA registers */
3407 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3408
3409 rt2800_register_read(rt2x00dev, offset, &reg);
3410 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3411 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3412 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3413 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3414 rt2800_register_write(rt2x00dev, offset, reg);
3415
3416 return 0;
3417}
e783619e 3418EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3419
e783619e 3420u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3421{
3422 struct rt2x00_dev *rt2x00dev = hw->priv;
3423 u64 tsf;
3424 u32 reg;
3425
3426 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3427 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3428 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3429 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3430
3431 return tsf;
3432}
e783619e 3433EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3434
e783619e
HS		 3435int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3436 enum ieee80211_ampdu_mlme_action action,
3437 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3438{
1df90809
HS		 3439 int ret = 0;
3440
3441 switch (action) {
3442 case IEEE80211_AMPDU_RX_START:
3443 case IEEE80211_AMPDU_RX_STOP:
3444 /* we don't support RX aggregation yet */
3445 ret = -ENOTSUPP;
3446 break;
3447 case IEEE80211_AMPDU_TX_START:
3448 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3449 break;
3450 case IEEE80211_AMPDU_TX_STOP:
3451 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3452 break;
3453 case IEEE80211_AMPDU_TX_OPERATIONAL:
3454 break;
3455 default:
4e9e58c6 3456 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3457 }
3458
3459 return ret;
3460}
e783619e 3461EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3462
3463MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3464MODULE_VERSION(DRV_VERSION);
3465MODULE_DESCRIPTION("Ralink RT2800 library");
3466MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror