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89297425 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> |
cce5fc45 | 3 | Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
89297425 | 4 | |
9c9a0d14 GW |
5 | Based on the original rt2800pci.c and rt2800usb.c. |
6 | Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com> | |
7 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> | |
8 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
9 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
10 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
11 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
12 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
89297425 BZ |
13 | <http://rt2x00.serialmonkey.com> |
14 | ||
15 | This program is free software; you can redistribute it and/or modify | |
16 | it under the terms of the GNU General Public License as published by | |
17 | the Free Software Foundation; either version 2 of the License, or | |
18 | (at your option) any later version. | |
19 | ||
20 | This program is distributed in the hope that it will be useful, | |
21 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | GNU General Public License for more details. | |
24 | ||
25 | You should have received a copy of the GNU General Public License | |
26 | along with this program; if not, write to the | |
27 | Free Software Foundation, Inc., | |
28 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
29 | */ | |
30 | ||
31 | /* | |
32 | Module: rt2800lib | |
33 | Abstract: rt2800 generic device routines. | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/module.h> | |
38 | ||
39 | #include "rt2x00.h" | |
fcf51541 BZ |
40 | #ifdef CONFIG_RT2800USB |
41 | #include "rt2x00usb.h" | |
42 | #endif | |
89297425 BZ |
43 | #include "rt2800lib.h" |
44 | #include "rt2800.h" | |
fcf51541 | 45 | #include "rt2800usb.h" |
89297425 BZ |
46 | |
47 | MODULE_AUTHOR("Bartlomiej Zolnierkiewicz"); | |
48 | MODULE_DESCRIPTION("rt2800 library"); | |
49 | MODULE_LICENSE("GPL"); | |
50 | ||
51 | /* | |
52 | * Register access. | |
53 | * All access to the CSR registers will go through the methods | |
54 | * rt2800_register_read and rt2800_register_write. | |
55 | * BBP and RF register require indirect register access, | |
56 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
57 | * These indirect registers work with busy bits, | |
58 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
59 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
60 | * between each attampt. When the busy bit is still set at that time, | |
61 | * the access attempt is considered to have failed, | |
62 | * and we will print an error. | |
63 | * The _lock versions must be used if you already hold the csr_mutex | |
64 | */ | |
65 | #define WAIT_FOR_BBP(__dev, __reg) \ | |
66 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) | |
67 | #define WAIT_FOR_RFCSR(__dev, __reg) \ | |
68 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) | |
69 | #define WAIT_FOR_RF(__dev, __reg) \ | |
70 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) | |
71 | #define WAIT_FOR_MCU(__dev, __reg) \ | |
72 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ | |
73 | H2M_MAILBOX_CSR_OWNER, (__reg)) | |
74 | ||
fcf51541 BZ |
75 | static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
76 | const unsigned int word, const u8 value) | |
89297425 BZ |
77 | { |
78 | u32 reg; | |
79 | ||
80 | mutex_lock(&rt2x00dev->csr_mutex); | |
81 | ||
82 | /* | |
83 | * Wait until the BBP becomes available, afterwards we | |
84 | * can safely write the new data into the register. | |
85 | */ | |
86 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
87 | reg = 0; | |
88 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); | |
89 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
90 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
91 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); | |
92 | if (rt2x00_intf_is_pci(rt2x00dev)) | |
93 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); | |
94 | ||
95 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
96 | } | |
97 | ||
98 | mutex_unlock(&rt2x00dev->csr_mutex); | |
99 | } | |
89297425 | 100 | |
fcf51541 BZ |
101 | static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
102 | const unsigned int word, u8 *value) | |
89297425 BZ |
103 | { |
104 | u32 reg; | |
105 | ||
106 | mutex_lock(&rt2x00dev->csr_mutex); | |
107 | ||
108 | /* | |
109 | * Wait until the BBP becomes available, afterwards we | |
110 | * can safely write the read request into the register. | |
111 | * After the data has been written, we wait until hardware | |
112 | * returns the correct value, if at any time the register | |
113 | * doesn't become available in time, reg will be 0xffffffff | |
114 | * which means we return 0xff to the caller. | |
115 | */ | |
116 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { | |
117 | reg = 0; | |
118 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); | |
119 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); | |
120 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); | |
121 | if (rt2x00_intf_is_pci(rt2x00dev)) | |
122 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); | |
123 | ||
124 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); | |
125 | ||
126 | WAIT_FOR_BBP(rt2x00dev, ®); | |
127 | } | |
128 | ||
129 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); | |
130 | ||
131 | mutex_unlock(&rt2x00dev->csr_mutex); | |
132 | } | |
89297425 | 133 | |
fcf51541 BZ |
134 | static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
135 | const unsigned int word, const u8 value) | |
89297425 BZ |
136 | { |
137 | u32 reg; | |
138 | ||
139 | mutex_lock(&rt2x00dev->csr_mutex); | |
140 | ||
141 | /* | |
142 | * Wait until the RFCSR becomes available, afterwards we | |
143 | * can safely write the new data into the register. | |
144 | */ | |
145 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
146 | reg = 0; | |
147 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); | |
148 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
149 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); | |
150 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
151 | ||
152 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
153 | } | |
154 | ||
155 | mutex_unlock(&rt2x00dev->csr_mutex); | |
156 | } | |
89297425 | 157 | |
fcf51541 BZ |
158 | static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
159 | const unsigned int word, u8 *value) | |
89297425 BZ |
160 | { |
161 | u32 reg; | |
162 | ||
163 | mutex_lock(&rt2x00dev->csr_mutex); | |
164 | ||
165 | /* | |
166 | * Wait until the RFCSR becomes available, afterwards we | |
167 | * can safely write the read request into the register. | |
168 | * After the data has been written, we wait until hardware | |
169 | * returns the correct value, if at any time the register | |
170 | * doesn't become available in time, reg will be 0xffffffff | |
171 | * which means we return 0xff to the caller. | |
172 | */ | |
173 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { | |
174 | reg = 0; | |
175 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); | |
176 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); | |
177 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); | |
178 | ||
179 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); | |
180 | ||
181 | WAIT_FOR_RFCSR(rt2x00dev, ®); | |
182 | } | |
183 | ||
184 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); | |
185 | ||
186 | mutex_unlock(&rt2x00dev->csr_mutex); | |
187 | } | |
89297425 | 188 | |
fcf51541 BZ |
189 | static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
190 | const unsigned int word, const u32 value) | |
89297425 BZ |
191 | { |
192 | u32 reg; | |
193 | ||
194 | mutex_lock(&rt2x00dev->csr_mutex); | |
195 | ||
196 | /* | |
197 | * Wait until the RF becomes available, afterwards we | |
198 | * can safely write the new data into the register. | |
199 | */ | |
200 | if (WAIT_FOR_RF(rt2x00dev, ®)) { | |
201 | reg = 0; | |
202 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); | |
203 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); | |
204 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); | |
205 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); | |
206 | ||
207 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); | |
208 | rt2x00_rf_write(rt2x00dev, word, value); | |
209 | } | |
210 | ||
211 | mutex_unlock(&rt2x00dev->csr_mutex); | |
212 | } | |
89297425 BZ |
213 | |
214 | void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, | |
215 | const u8 command, const u8 token, | |
216 | const u8 arg0, const u8 arg1) | |
217 | { | |
218 | u32 reg; | |
219 | ||
220 | if (rt2x00_intf_is_pci(rt2x00dev)) { | |
221 | /* | |
222 | * RT2880 and RT3052 don't support MCU requests. | |
223 | */ | |
224 | if (rt2x00_rt(&rt2x00dev->chip, RT2880) || | |
225 | rt2x00_rt(&rt2x00dev->chip, RT3052)) | |
226 | return; | |
227 | } | |
228 | ||
229 | mutex_lock(&rt2x00dev->csr_mutex); | |
230 | ||
231 | /* | |
232 | * Wait until the MCU becomes available, afterwards we | |
233 | * can safely write the new data into the register. | |
234 | */ | |
235 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { | |
236 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
237 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
238 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
239 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
240 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); | |
241 | ||
242 | reg = 0; | |
243 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); | |
244 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); | |
245 | } | |
246 | ||
247 | mutex_unlock(&rt2x00dev->csr_mutex); | |
248 | } | |
249 | EXPORT_SYMBOL_GPL(rt2800_mcu_request); | |
f4450616 BZ |
250 | |
251 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
252 | const struct rt2x00debug rt2800_rt2x00debug = { | |
253 | .owner = THIS_MODULE, | |
254 | .csr = { | |
255 | .read = rt2800_register_read, | |
256 | .write = rt2800_register_write, | |
257 | .flags = RT2X00DEBUGFS_OFFSET, | |
258 | .word_base = CSR_REG_BASE, | |
259 | .word_size = sizeof(u32), | |
260 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
261 | }, | |
262 | .eeprom = { | |
263 | .read = rt2x00_eeprom_read, | |
264 | .write = rt2x00_eeprom_write, | |
265 | .word_base = EEPROM_BASE, | |
266 | .word_size = sizeof(u16), | |
267 | .word_count = EEPROM_SIZE / sizeof(u16), | |
268 | }, | |
269 | .bbp = { | |
270 | .read = rt2800_bbp_read, | |
271 | .write = rt2800_bbp_write, | |
272 | .word_base = BBP_BASE, | |
273 | .word_size = sizeof(u8), | |
274 | .word_count = BBP_SIZE / sizeof(u8), | |
275 | }, | |
276 | .rf = { | |
277 | .read = rt2x00_rf_read, | |
278 | .write = rt2800_rf_write, | |
279 | .word_base = RF_BASE, | |
280 | .word_size = sizeof(u32), | |
281 | .word_count = RF_SIZE / sizeof(u32), | |
282 | }, | |
283 | }; | |
284 | EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); | |
285 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
286 | ||
287 | int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) | |
288 | { | |
289 | u32 reg; | |
290 | ||
291 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | |
292 | return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); | |
293 | } | |
294 | EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); | |
295 | ||
296 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
297 | static void rt2800_brightness_set(struct led_classdev *led_cdev, | |
298 | enum led_brightness brightness) | |
299 | { | |
300 | struct rt2x00_led *led = | |
301 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
302 | unsigned int enabled = brightness != LED_OFF; | |
303 | unsigned int bg_mode = | |
304 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
305 | unsigned int polarity = | |
306 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
307 | EEPROM_FREQ_LED_POLARITY); | |
308 | unsigned int ledmode = | |
309 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, | |
310 | EEPROM_FREQ_LED_MODE); | |
311 | ||
312 | if (led->type == LED_TYPE_RADIO) { | |
313 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
314 | enabled ? 0x20 : 0); | |
315 | } else if (led->type == LED_TYPE_ASSOC) { | |
316 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, | |
317 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); | |
318 | } else if (led->type == LED_TYPE_QUALITY) { | |
319 | /* | |
320 | * The brightness is divided into 6 levels (0 - 5), | |
321 | * The specs tell us the following levels: | |
322 | * 0, 1 ,3, 7, 15, 31 | |
323 | * to determine the level in a simple way we can simply | |
324 | * work with bitshifting: | |
325 | * (1 << level) - 1 | |
326 | */ | |
327 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
328 | (1 << brightness / (LED_FULL / 6)) - 1, | |
329 | polarity); | |
330 | } | |
331 | } | |
332 | ||
333 | static int rt2800_blink_set(struct led_classdev *led_cdev, | |
334 | unsigned long *delay_on, unsigned long *delay_off) | |
335 | { | |
336 | struct rt2x00_led *led = | |
337 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
338 | u32 reg; | |
339 | ||
340 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); | |
341 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on); | |
342 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off); | |
343 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); | |
344 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); | |
345 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 12); | |
346 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); | |
347 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); | |
348 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | void rt2800_init_led(struct rt2x00_dev *rt2x00dev, | |
354 | struct rt2x00_led *led, enum led_type type) | |
355 | { | |
356 | led->rt2x00dev = rt2x00dev; | |
357 | led->type = type; | |
358 | led->led_dev.brightness_set = rt2800_brightness_set; | |
359 | led->led_dev.blink_set = rt2800_blink_set; | |
360 | led->flags = LED_INITIALIZED; | |
361 | } | |
362 | EXPORT_SYMBOL_GPL(rt2800_init_led); | |
363 | #endif /* CONFIG_RT2X00_LIB_LEDS */ | |
364 | ||
365 | /* | |
366 | * Configuration handlers. | |
367 | */ | |
368 | static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev, | |
369 | struct rt2x00lib_crypto *crypto, | |
370 | struct ieee80211_key_conf *key) | |
371 | { | |
372 | struct mac_wcid_entry wcid_entry; | |
373 | struct mac_iveiv_entry iveiv_entry; | |
374 | u32 offset; | |
375 | u32 reg; | |
376 | ||
377 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); | |
378 | ||
379 | rt2800_register_read(rt2x00dev, offset, ®); | |
380 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, | |
381 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); | |
382 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, | |
383 | (crypto->cmd == SET_KEY) * crypto->cipher); | |
384 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, | |
385 | (crypto->cmd == SET_KEY) * crypto->bssidx); | |
386 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); | |
387 | rt2800_register_write(rt2x00dev, offset, reg); | |
388 | ||
389 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); | |
390 | ||
391 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); | |
392 | if ((crypto->cipher == CIPHER_TKIP) || | |
393 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || | |
394 | (crypto->cipher == CIPHER_AES)) | |
395 | iveiv_entry.iv[3] |= 0x20; | |
396 | iveiv_entry.iv[3] |= key->keyidx << 6; | |
397 | rt2800_register_multiwrite(rt2x00dev, offset, | |
398 | &iveiv_entry, sizeof(iveiv_entry)); | |
399 | ||
400 | offset = MAC_WCID_ENTRY(key->hw_key_idx); | |
401 | ||
402 | memset(&wcid_entry, 0, sizeof(wcid_entry)); | |
403 | if (crypto->cmd == SET_KEY) | |
404 | memcpy(&wcid_entry, crypto->address, ETH_ALEN); | |
405 | rt2800_register_multiwrite(rt2x00dev, offset, | |
406 | &wcid_entry, sizeof(wcid_entry)); | |
407 | } | |
408 | ||
409 | int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, | |
410 | struct rt2x00lib_crypto *crypto, | |
411 | struct ieee80211_key_conf *key) | |
412 | { | |
413 | struct hw_key_entry key_entry; | |
414 | struct rt2x00_field32 field; | |
415 | u32 offset; | |
416 | u32 reg; | |
417 | ||
418 | if (crypto->cmd == SET_KEY) { | |
419 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; | |
420 | ||
421 | memcpy(key_entry.key, crypto->key, | |
422 | sizeof(key_entry.key)); | |
423 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
424 | sizeof(key_entry.tx_mic)); | |
425 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
426 | sizeof(key_entry.rx_mic)); | |
427 | ||
428 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); | |
429 | rt2800_register_multiwrite(rt2x00dev, offset, | |
430 | &key_entry, sizeof(key_entry)); | |
431 | } | |
432 | ||
433 | /* | |
434 | * The cipher types are stored over multiple registers | |
435 | * starting with SHARED_KEY_MODE_BASE each word will have | |
436 | * 32 bits and contains the cipher types for 2 bssidx each. | |
437 | * Using the correct defines correctly will cause overhead, | |
438 | * so just calculate the correct offset. | |
439 | */ | |
440 | field.bit_offset = 4 * (key->hw_key_idx % 8); | |
441 | field.bit_mask = 0x7 << field.bit_offset; | |
442 | ||
443 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); | |
444 | ||
445 | rt2800_register_read(rt2x00dev, offset, ®); | |
446 | rt2x00_set_field32(®, field, | |
447 | (crypto->cmd == SET_KEY) * crypto->cipher); | |
448 | rt2800_register_write(rt2x00dev, offset, reg); | |
449 | ||
450 | /* | |
451 | * Update WCID information | |
452 | */ | |
453 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | EXPORT_SYMBOL_GPL(rt2800_config_shared_key); | |
458 | ||
459 | int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
460 | struct rt2x00lib_crypto *crypto, | |
461 | struct ieee80211_key_conf *key) | |
462 | { | |
463 | struct hw_key_entry key_entry; | |
464 | u32 offset; | |
465 | ||
466 | if (crypto->cmd == SET_KEY) { | |
467 | /* | |
468 | * 1 pairwise key is possible per AID, this means that the AID | |
469 | * equals our hw_key_idx. Make sure the WCID starts _after_ the | |
470 | * last possible shared key entry. | |
471 | */ | |
472 | if (crypto->aid > (256 - 32)) | |
473 | return -ENOSPC; | |
474 | ||
475 | key->hw_key_idx = 32 + crypto->aid; | |
476 | ||
477 | memcpy(key_entry.key, crypto->key, | |
478 | sizeof(key_entry.key)); | |
479 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
480 | sizeof(key_entry.tx_mic)); | |
481 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
482 | sizeof(key_entry.rx_mic)); | |
483 | ||
484 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
485 | rt2800_register_multiwrite(rt2x00dev, offset, | |
486 | &key_entry, sizeof(key_entry)); | |
487 | } | |
488 | ||
489 | /* | |
490 | * Update WCID information | |
491 | */ | |
492 | rt2800_config_wcid_attr(rt2x00dev, crypto, key); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); | |
497 | ||
498 | void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, | |
499 | const unsigned int filter_flags) | |
500 | { | |
501 | u32 reg; | |
502 | ||
503 | /* | |
504 | * Start configuration steps. | |
505 | * Note that the version error will always be dropped | |
506 | * and broadcast frames will always be accepted since | |
507 | * there is no filter for it at this time. | |
508 | */ | |
509 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); | |
510 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, | |
511 | !(filter_flags & FIF_FCSFAIL)); | |
512 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, | |
513 | !(filter_flags & FIF_PLCPFAIL)); | |
514 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, | |
515 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
516 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); | |
517 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); | |
518 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, | |
519 | !(filter_flags & FIF_ALLMULTI)); | |
520 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); | |
521 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); | |
522 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, | |
523 | !(filter_flags & FIF_CONTROL)); | |
524 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, | |
525 | !(filter_flags & FIF_CONTROL)); | |
526 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, | |
527 | !(filter_flags & FIF_CONTROL)); | |
528 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, | |
529 | !(filter_flags & FIF_CONTROL)); | |
530 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, | |
531 | !(filter_flags & FIF_CONTROL)); | |
532 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, | |
533 | !(filter_flags & FIF_PSPOLL)); | |
534 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1); | |
535 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0); | |
536 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, | |
537 | !(filter_flags & FIF_CONTROL)); | |
538 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); | |
539 | } | |
540 | EXPORT_SYMBOL_GPL(rt2800_config_filter); | |
541 | ||
542 | void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, | |
543 | struct rt2x00intf_conf *conf, const unsigned int flags) | |
544 | { | |
545 | unsigned int beacon_base; | |
546 | u32 reg; | |
547 | ||
548 | if (flags & CONFIG_UPDATE_TYPE) { | |
549 | /* | |
550 | * Clear current synchronisation setup. | |
551 | * For the Beacon base registers we only need to clear | |
552 | * the first byte since that byte contains the VALID and OWNER | |
553 | * bits which (when set to 0) will invalidate the entire beacon. | |
554 | */ | |
555 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); | |
556 | rt2800_register_write(rt2x00dev, beacon_base, 0); | |
557 | ||
558 | /* | |
559 | * Enable synchronisation. | |
560 | */ | |
561 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
562 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); | |
563 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); | |
6a62e5ef JB |
564 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, |
565 | (conf->sync == TSF_SYNC_BEACON)); | |
f4450616 BZ |
566 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
567 | } | |
568 | ||
569 | if (flags & CONFIG_UPDATE_MAC) { | |
570 | reg = le32_to_cpu(conf->mac[1]); | |
571 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); | |
572 | conf->mac[1] = cpu_to_le32(reg); | |
573 | ||
574 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, | |
575 | conf->mac, sizeof(conf->mac)); | |
576 | } | |
577 | ||
578 | if (flags & CONFIG_UPDATE_BSSID) { | |
579 | reg = le32_to_cpu(conf->bssid[1]); | |
580 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 0); | |
581 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); | |
582 | conf->bssid[1] = cpu_to_le32(reg); | |
583 | ||
584 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, | |
585 | conf->bssid, sizeof(conf->bssid)); | |
586 | } | |
587 | } | |
588 | EXPORT_SYMBOL_GPL(rt2800_config_intf); | |
589 | ||
590 | void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp) | |
591 | { | |
592 | u32 reg; | |
593 | ||
594 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); | |
595 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20); | |
596 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); | |
597 | ||
598 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); | |
599 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, | |
600 | !!erp->short_preamble); | |
601 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, | |
602 | !!erp->short_preamble); | |
603 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
604 | ||
605 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
606 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, | |
607 | erp->cts_protection ? 2 : 0); | |
608 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
609 | ||
610 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, | |
611 | erp->basic_rates); | |
612 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
613 | ||
614 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); | |
615 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); | |
616 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); | |
617 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); | |
618 | ||
619 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); | |
620 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); | |
621 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); | |
622 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); | |
623 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); | |
624 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); | |
625 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); | |
626 | ||
627 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
628 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, | |
629 | erp->beacon_int * 16); | |
630 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
631 | } | |
632 | EXPORT_SYMBOL_GPL(rt2800_config_erp); | |
633 | ||
634 | void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |
635 | { | |
636 | u8 r1; | |
637 | u8 r3; | |
638 | ||
639 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
640 | rt2800_bbp_read(rt2x00dev, 3, &r3); | |
641 | ||
642 | /* | |
643 | * Configure the TX antenna. | |
644 | */ | |
645 | switch ((int)ant->tx) { | |
646 | case 1: | |
647 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | |
648 | if (rt2x00_intf_is_pci(rt2x00dev)) | |
649 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); | |
650 | break; | |
651 | case 2: | |
652 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | |
653 | break; | |
654 | case 3: | |
655 | /* Do nothing */ | |
656 | break; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Configure the RX antenna. | |
661 | */ | |
662 | switch ((int)ant->rx) { | |
663 | case 1: | |
664 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); | |
665 | break; | |
666 | case 2: | |
667 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | |
668 | break; | |
669 | case 3: | |
670 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); | |
671 | break; | |
672 | } | |
673 | ||
674 | rt2800_bbp_write(rt2x00dev, 3, r3); | |
675 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
676 | } | |
677 | EXPORT_SYMBOL_GPL(rt2800_config_ant); | |
678 | ||
679 | static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, | |
680 | struct rt2x00lib_conf *libconf) | |
681 | { | |
682 | u16 eeprom; | |
683 | short lna_gain; | |
684 | ||
685 | if (libconf->rf.channel <= 14) { | |
686 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
687 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); | |
688 | } else if (libconf->rf.channel <= 64) { | |
689 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); | |
690 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); | |
691 | } else if (libconf->rf.channel <= 128) { | |
692 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); | |
693 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); | |
694 | } else { | |
695 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); | |
696 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); | |
697 | } | |
698 | ||
699 | rt2x00dev->lna_gain = lna_gain; | |
700 | } | |
701 | ||
702 | static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev, | |
703 | struct ieee80211_conf *conf, | |
704 | struct rf_channel *rf, | |
705 | struct channel_info *info) | |
706 | { | |
707 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
708 | ||
709 | if (rt2x00dev->default_ant.tx == 1) | |
710 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); | |
711 | ||
712 | if (rt2x00dev->default_ant.rx == 1) { | |
713 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); | |
714 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); | |
715 | } else if (rt2x00dev->default_ant.rx == 2) | |
716 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); | |
717 | ||
718 | if (rf->channel > 14) { | |
719 | /* | |
720 | * When TX power is below 0, we should increase it by 7 to | |
721 | * make it a positive value (Minumum value is -7). | |
722 | * However this means that values between 0 and 7 have | |
723 | * double meaning, and we should set a 7DBm boost flag. | |
724 | */ | |
725 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, | |
726 | (info->tx_power1 >= 0)); | |
727 | ||
728 | if (info->tx_power1 < 0) | |
729 | info->tx_power1 += 7; | |
730 | ||
731 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, | |
732 | TXPOWER_A_TO_DEV(info->tx_power1)); | |
733 | ||
734 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, | |
735 | (info->tx_power2 >= 0)); | |
736 | ||
737 | if (info->tx_power2 < 0) | |
738 | info->tx_power2 += 7; | |
739 | ||
740 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, | |
741 | TXPOWER_A_TO_DEV(info->tx_power2)); | |
742 | } else { | |
743 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, | |
744 | TXPOWER_G_TO_DEV(info->tx_power1)); | |
745 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, | |
746 | TXPOWER_G_TO_DEV(info->tx_power2)); | |
747 | } | |
748 | ||
749 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); | |
750 | ||
751 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
752 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
753 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
754 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
755 | ||
756 | udelay(200); | |
757 | ||
758 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
759 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
760 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
761 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
762 | ||
763 | udelay(200); | |
764 | ||
765 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); | |
766 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); | |
767 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
768 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); | |
769 | } | |
770 | ||
771 | static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev, | |
772 | struct ieee80211_conf *conf, | |
773 | struct rf_channel *rf, | |
774 | struct channel_info *info) | |
775 | { | |
776 | u8 rfcsr; | |
777 | ||
778 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | |
41a26170 | 779 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); |
f4450616 BZ |
780 | |
781 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | |
782 | rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2); | |
783 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | |
784 | ||
785 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | |
786 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | |
787 | TXPOWER_G_TO_DEV(info->tx_power1)); | |
788 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); | |
789 | ||
790 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | |
791 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | |
792 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
793 | ||
794 | rt2800_rfcsr_write(rt2x00dev, 24, | |
795 | rt2x00dev->calibration[conf_is_ht40(conf)]); | |
796 | ||
797 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | |
798 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); | |
799 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | |
800 | } | |
801 | ||
802 | static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |
803 | struct ieee80211_conf *conf, | |
804 | struct rf_channel *rf, | |
805 | struct channel_info *info) | |
806 | { | |
807 | u32 reg; | |
808 | unsigned int tx_pin; | |
809 | u8 bbp; | |
810 | ||
cce5fc45 GW |
811 | if ((rt2x00_rt(&rt2x00dev->chip, RT3070) || |
812 | rt2x00_rt(&rt2x00dev->chip, RT3090)) && | |
fa6f632f GW |
813 | (rt2x00_rf(&rt2x00dev->chip, RF2020) || |
814 | rt2x00_rf(&rt2x00dev->chip, RF3020) || | |
815 | rt2x00_rf(&rt2x00dev->chip, RF3021) || | |
816 | rt2x00_rf(&rt2x00dev->chip, RF3022))) | |
f4450616 | 817 | rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info); |
fa6f632f GW |
818 | else |
819 | rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info); | |
f4450616 BZ |
820 | |
821 | /* | |
822 | * Change BBP settings | |
823 | */ | |
824 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); | |
825 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); | |
826 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); | |
827 | rt2800_bbp_write(rt2x00dev, 86, 0); | |
828 | ||
829 | if (rf->channel <= 14) { | |
830 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { | |
831 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
832 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
833 | } else { | |
834 | rt2800_bbp_write(rt2x00dev, 82, 0x84); | |
835 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
836 | } | |
837 | } else { | |
838 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | |
839 | ||
840 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) | |
841 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | |
842 | else | |
843 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | |
844 | } | |
845 | ||
846 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); | |
847 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf)); | |
848 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); | |
849 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); | |
850 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); | |
851 | ||
852 | tx_pin = 0; | |
853 | ||
854 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
855 | if (rt2x00dev->default_ant.tx != 1) { | |
856 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); | |
857 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); | |
858 | } | |
859 | ||
860 | /* Turn on unused PA or LNA when not using 1T or 1R */ | |
861 | if (rt2x00dev->default_ant.rx != 1) { | |
862 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); | |
863 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); | |
864 | } | |
865 | ||
866 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); | |
867 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); | |
868 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); | |
869 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); | |
870 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); | |
871 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); | |
872 | ||
873 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | |
874 | ||
875 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
876 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); | |
877 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
878 | ||
879 | rt2800_bbp_read(rt2x00dev, 3, &bbp); | |
880 | rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); | |
881 | rt2800_bbp_write(rt2x00dev, 3, bbp); | |
882 | ||
883 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) { | |
884 | if (conf_is_ht40(conf)) { | |
885 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); | |
886 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
887 | rt2800_bbp_write(rt2x00dev, 73, 0x16); | |
888 | } else { | |
889 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
890 | rt2800_bbp_write(rt2x00dev, 70, 0x08); | |
891 | rt2800_bbp_write(rt2x00dev, 73, 0x11); | |
892 | } | |
893 | } | |
894 | ||
895 | msleep(1); | |
896 | } | |
897 | ||
898 | static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, | |
899 | const int txpower) | |
900 | { | |
901 | u32 reg; | |
902 | u32 value = TXPOWER_G_TO_DEV(txpower); | |
903 | u8 r1; | |
904 | ||
905 | rt2800_bbp_read(rt2x00dev, 1, &r1); | |
906 | rt2x00_set_field8(®, BBP1_TX_POWER, 0); | |
907 | rt2800_bbp_write(rt2x00dev, 1, r1); | |
908 | ||
909 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®); | |
910 | rt2x00_set_field32(®, TX_PWR_CFG_0_1MBS, value); | |
911 | rt2x00_set_field32(®, TX_PWR_CFG_0_2MBS, value); | |
912 | rt2x00_set_field32(®, TX_PWR_CFG_0_55MBS, value); | |
913 | rt2x00_set_field32(®, TX_PWR_CFG_0_11MBS, value); | |
914 | rt2x00_set_field32(®, TX_PWR_CFG_0_6MBS, value); | |
915 | rt2x00_set_field32(®, TX_PWR_CFG_0_9MBS, value); | |
916 | rt2x00_set_field32(®, TX_PWR_CFG_0_12MBS, value); | |
917 | rt2x00_set_field32(®, TX_PWR_CFG_0_18MBS, value); | |
918 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg); | |
919 | ||
920 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, ®); | |
921 | rt2x00_set_field32(®, TX_PWR_CFG_1_24MBS, value); | |
922 | rt2x00_set_field32(®, TX_PWR_CFG_1_36MBS, value); | |
923 | rt2x00_set_field32(®, TX_PWR_CFG_1_48MBS, value); | |
924 | rt2x00_set_field32(®, TX_PWR_CFG_1_54MBS, value); | |
925 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS0, value); | |
926 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS1, value); | |
927 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS2, value); | |
928 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS3, value); | |
929 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg); | |
930 | ||
931 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, ®); | |
932 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS4, value); | |
933 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS5, value); | |
934 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS6, value); | |
935 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS7, value); | |
936 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS8, value); | |
937 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS9, value); | |
938 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS10, value); | |
939 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS11, value); | |
940 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg); | |
941 | ||
942 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, ®); | |
943 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS12, value); | |
944 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS13, value); | |
945 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS14, value); | |
946 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS15, value); | |
947 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN1, value); | |
948 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN2, value); | |
949 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN3, value); | |
950 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN4, value); | |
951 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg); | |
952 | ||
953 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, ®); | |
954 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN5, value); | |
955 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN6, value); | |
956 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN7, value); | |
957 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN8, value); | |
958 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg); | |
959 | } | |
960 | ||
961 | static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
962 | struct rt2x00lib_conf *libconf) | |
963 | { | |
964 | u32 reg; | |
965 | ||
966 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); | |
967 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, | |
968 | libconf->conf->short_frame_max_tx_count); | |
969 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, | |
970 | libconf->conf->long_frame_max_tx_count); | |
971 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); | |
972 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); | |
973 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); | |
974 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); | |
975 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); | |
976 | } | |
977 | ||
978 | static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, | |
979 | struct rt2x00lib_conf *libconf) | |
980 | { | |
981 | enum dev_state state = | |
982 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
983 | STATE_SLEEP : STATE_AWAKE; | |
984 | u32 reg; | |
985 | ||
986 | if (state == STATE_SLEEP) { | |
987 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); | |
988 | ||
989 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); | |
990 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); | |
991 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, | |
992 | libconf->conf->listen_interval - 1); | |
993 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); | |
994 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
995 | ||
996 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
997 | } else { | |
998 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); | |
999 | ||
1000 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); | |
1001 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); | |
1002 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); | |
1003 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); | |
1004 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | void rt2800_config(struct rt2x00_dev *rt2x00dev, | |
1009 | struct rt2x00lib_conf *libconf, | |
1010 | const unsigned int flags) | |
1011 | { | |
1012 | /* Always recalculate LNA gain before changing configuration */ | |
1013 | rt2800_config_lna_gain(rt2x00dev, libconf); | |
1014 | ||
1015 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) | |
1016 | rt2800_config_channel(rt2x00dev, libconf->conf, | |
1017 | &libconf->rf, &libconf->channel); | |
1018 | if (flags & IEEE80211_CONF_CHANGE_POWER) | |
1019 | rt2800_config_txpower(rt2x00dev, libconf->conf->power_level); | |
1020 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) | |
1021 | rt2800_config_retry_limit(rt2x00dev, libconf); | |
1022 | if (flags & IEEE80211_CONF_CHANGE_PS) | |
1023 | rt2800_config_ps(rt2x00dev, libconf); | |
1024 | } | |
1025 | EXPORT_SYMBOL_GPL(rt2800_config); | |
1026 | ||
1027 | /* | |
1028 | * Link tuning | |
1029 | */ | |
1030 | void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
1031 | { | |
1032 | u32 reg; | |
1033 | ||
1034 | /* | |
1035 | * Update FCS error count from register. | |
1036 | */ | |
1037 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
1038 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(rt2800_link_stats); | |
1041 | ||
1042 | static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |
1043 | { | |
1044 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { | |
1045 | if (rt2x00_intf_is_usb(rt2x00dev) && | |
1046 | rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) | |
1047 | return 0x1c + (2 * rt2x00dev->lna_gain); | |
1048 | else | |
1049 | return 0x2e + rt2x00dev->lna_gain; | |
1050 | } | |
1051 | ||
1052 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) | |
1053 | return 0x32 + (rt2x00dev->lna_gain * 5) / 3; | |
1054 | else | |
1055 | return 0x3a + (rt2x00dev->lna_gain * 5) / 3; | |
1056 | } | |
1057 | ||
1058 | static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, | |
1059 | struct link_qual *qual, u8 vgc_level) | |
1060 | { | |
1061 | if (qual->vgc_level != vgc_level) { | |
1062 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); | |
1063 | qual->vgc_level = vgc_level; | |
1064 | qual->vgc_level_reg = vgc_level; | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) | |
1069 | { | |
1070 | rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); | |
1071 | } | |
1072 | EXPORT_SYMBOL_GPL(rt2800_reset_tuner); | |
1073 | ||
1074 | void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, | |
1075 | const u32 count) | |
1076 | { | |
1077 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) | |
1078 | return; | |
1079 | ||
1080 | /* | |
1081 | * When RSSI is better then -80 increase VGC level with 0x10 | |
1082 | */ | |
1083 | rt2800_set_vgc(rt2x00dev, qual, | |
1084 | rt2800_get_default_vgc(rt2x00dev) + | |
1085 | ((qual->rssi > -80) * 0x10)); | |
1086 | } | |
1087 | EXPORT_SYMBOL_GPL(rt2800_link_tuner); | |
fcf51541 BZ |
1088 | |
1089 | /* | |
1090 | * Initialization functions. | |
1091 | */ | |
1092 | int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) | |
1093 | { | |
1094 | u32 reg; | |
1095 | unsigned int i; | |
1096 | ||
1097 | if (rt2x00_intf_is_usb(rt2x00dev)) { | |
1098 | /* | |
235faf9b | 1099 | * Wait until BBP and RF are ready. |
fcf51541 BZ |
1100 | */ |
1101 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1102 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
1103 | if (reg && reg != ~0) | |
1104 | break; | |
1105 | msleep(1); | |
1106 | } | |
1107 | ||
1108 | if (i == REGISTER_BUSY_COUNT) { | |
1109 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
1110 | return -EBUSY; | |
1111 | } | |
1112 | ||
1113 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); | |
1114 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, | |
1115 | reg & ~0x00002000); | |
1116 | } else if (rt2x00_intf_is_pci(rt2x00dev)) | |
1117 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); | |
1118 | ||
1119 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); | |
1120 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); | |
1121 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); | |
1122 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); | |
1123 | ||
1124 | if (rt2x00_intf_is_usb(rt2x00dev)) { | |
1125 | rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000); | |
1126 | #ifdef CONFIG_RT2800USB | |
1127 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
1128 | USB_MODE_RESET, REGISTER_TIMEOUT); | |
1129 | #endif | |
1130 | } | |
1131 | ||
1132 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); | |
1133 | ||
1134 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); | |
1135 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ | |
1136 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ | |
1137 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ | |
1138 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ | |
1139 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); | |
1140 | ||
1141 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); | |
1142 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ | |
1143 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ | |
1144 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ | |
1145 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ | |
1146 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); | |
1147 | ||
1148 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); | |
1149 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); | |
1150 | ||
1151 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); | |
1152 | ||
1153 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); | |
1154 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 0); | |
1155 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); | |
1156 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); | |
1157 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); | |
1158 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); | |
1159 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); | |
1160 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); | |
1161 | ||
1162 | if (rt2x00_intf_is_usb(rt2x00dev) && | |
1163 | rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) { | |
1164 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | |
1165 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | |
1166 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); | |
1167 | } else { | |
1168 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); | |
1169 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | |
1170 | } | |
1171 | ||
1172 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); | |
1173 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); | |
1174 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); | |
1175 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); | |
1176 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); | |
1177 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); | |
1178 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); | |
1179 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); | |
1180 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); | |
1181 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); | |
1182 | ||
1183 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); | |
1184 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); | |
1185 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); | |
1186 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); | |
1187 | ||
1188 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); | |
1189 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); | |
1190 | if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION && | |
1191 | rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION) | |
1192 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); | |
1193 | else | |
1194 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); | |
1195 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); | |
1196 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); | |
1197 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); | |
1198 | ||
1199 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); | |
1200 | ||
1201 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); | |
1202 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); | |
1203 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); | |
1204 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); | |
1205 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); | |
1206 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); | |
1207 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); | |
1208 | ||
1209 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
1210 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 8); | |
1211 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); | |
1212 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1); | |
1213 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1214 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1215 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1216 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
1217 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1218 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
1219 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); | |
1220 | ||
1221 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
1222 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 8); | |
1223 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); | |
1224 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1); | |
1225 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1226 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1227 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1228 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
1229 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1230 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
1231 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
1232 | ||
1233 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
1234 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); | |
1235 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); | |
1236 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1); | |
1237 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1238 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1239 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1240 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
1241 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1242 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
1243 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
1244 | ||
1245 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
1246 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); | |
1247 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); | |
1248 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1); | |
1249 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1250 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1251 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1252 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
1253 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1254 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
1255 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
1256 | ||
1257 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
1258 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); | |
1259 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); | |
1260 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1); | |
1261 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1262 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1263 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1264 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); | |
1265 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1266 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); | |
1267 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
1268 | ||
1269 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
1270 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); | |
1271 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); | |
1272 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1); | |
1273 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); | |
1274 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); | |
1275 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); | |
1276 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); | |
1277 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); | |
1278 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); | |
1279 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
1280 | ||
1281 | if (rt2x00_intf_is_usb(rt2x00dev)) { | |
1282 | rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); | |
1283 | ||
1284 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); | |
1285 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); | |
1286 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); | |
1287 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); | |
1288 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); | |
1289 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); | |
1290 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); | |
1291 | rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); | |
1292 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); | |
1293 | rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); | |
1294 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); | |
1295 | } | |
1296 | ||
1297 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); | |
1298 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); | |
1299 | ||
1300 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
1301 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); | |
1302 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, | |
1303 | IEEE80211_MAX_RTS_THRESHOLD); | |
1304 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); | |
1305 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
1306 | ||
1307 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); | |
1308 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); | |
1309 | ||
1310 | /* | |
1311 | * ASIC will keep garbage value after boot, clear encryption keys. | |
1312 | */ | |
1313 | for (i = 0; i < 4; i++) | |
1314 | rt2800_register_write(rt2x00dev, | |
1315 | SHARED_KEY_MODE_ENTRY(i), 0); | |
1316 | ||
1317 | for (i = 0; i < 256; i++) { | |
1318 | u32 wcid[2] = { 0xffffffff, 0x00ffffff }; | |
1319 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), | |
1320 | wcid, sizeof(wcid)); | |
1321 | ||
1322 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); | |
1323 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); | |
1324 | } | |
1325 | ||
1326 | /* | |
1327 | * Clear all beacons | |
1328 | * For the Beacon base registers we only need to clear | |
1329 | * the first byte since that byte contains the VALID and OWNER | |
1330 | * bits which (when set to 0) will invalidate the entire beacon. | |
1331 | */ | |
1332 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0); | |
1333 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1334 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1335 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
1336 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0); | |
1337 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0); | |
1338 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0); | |
1339 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0); | |
1340 | ||
1341 | if (rt2x00_intf_is_usb(rt2x00dev)) { | |
1342 | rt2800_register_read(rt2x00dev, USB_CYC_CFG, ®); | |
1343 | rt2x00_set_field32(®, USB_CYC_CFG_CLOCK_CYCLE, 30); | |
1344 | rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg); | |
1345 | } | |
1346 | ||
1347 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); | |
1348 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); | |
1349 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); | |
1350 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); | |
1351 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); | |
1352 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); | |
1353 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); | |
1354 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); | |
1355 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); | |
1356 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); | |
1357 | ||
1358 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); | |
1359 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); | |
1360 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); | |
1361 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); | |
1362 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); | |
1363 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); | |
1364 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); | |
1365 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); | |
1366 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); | |
1367 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); | |
1368 | ||
1369 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); | |
1370 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); | |
1371 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); | |
1372 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); | |
1373 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); | |
1374 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); | |
1375 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); | |
1376 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); | |
1377 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); | |
1378 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); | |
1379 | ||
1380 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); | |
1381 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); | |
1382 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); | |
1383 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); | |
1384 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); | |
1385 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); | |
1386 | ||
1387 | /* | |
1388 | * We must clear the error counters. | |
1389 | * These registers are cleared on read, | |
1390 | * so we may pass a useless variable to store the value. | |
1391 | */ | |
1392 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); | |
1393 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); | |
1394 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); | |
1395 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); | |
1396 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); | |
1397 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | EXPORT_SYMBOL_GPL(rt2800_init_registers); | |
1402 | ||
1403 | static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) | |
1404 | { | |
1405 | unsigned int i; | |
1406 | u32 reg; | |
1407 | ||
1408 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1409 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); | |
1410 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) | |
1411 | return 0; | |
1412 | ||
1413 | udelay(REGISTER_BUSY_DELAY); | |
1414 | } | |
1415 | ||
1416 | ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); | |
1417 | return -EACCES; | |
1418 | } | |
1419 | ||
1420 | static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) | |
1421 | { | |
1422 | unsigned int i; | |
1423 | u8 value; | |
1424 | ||
1425 | /* | |
1426 | * BBP was enabled after firmware was loaded, | |
1427 | * but we need to reactivate it now. | |
1428 | */ | |
1429 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | |
1430 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
1431 | msleep(1); | |
1432 | ||
1433 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1434 | rt2800_bbp_read(rt2x00dev, 0, &value); | |
1435 | if ((value != 0xff) && (value != 0x00)) | |
1436 | return 0; | |
1437 | udelay(REGISTER_BUSY_DELAY); | |
1438 | } | |
1439 | ||
1440 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1441 | return -EACCES; | |
1442 | } | |
1443 | ||
1444 | int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1445 | { | |
1446 | unsigned int i; | |
1447 | u16 eeprom; | |
1448 | u8 reg_id; | |
1449 | u8 value; | |
1450 | ||
1451 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) || | |
1452 | rt2800_wait_bbp_ready(rt2x00dev))) | |
1453 | return -EACCES; | |
1454 | ||
1455 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); | |
1456 | rt2800_bbp_write(rt2x00dev, 66, 0x38); | |
1457 | rt2800_bbp_write(rt2x00dev, 69, 0x12); | |
1458 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
1459 | rt2800_bbp_write(rt2x00dev, 73, 0x10); | |
1460 | rt2800_bbp_write(rt2x00dev, 81, 0x37); | |
1461 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | |
1462 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); | |
1463 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
1464 | rt2800_bbp_write(rt2x00dev, 86, 0x00); | |
1465 | rt2800_bbp_write(rt2x00dev, 91, 0x04); | |
1466 | rt2800_bbp_write(rt2x00dev, 92, 0x00); | |
1467 | rt2800_bbp_write(rt2x00dev, 103, 0x00); | |
1468 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
1469 | ||
1470 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) { | |
1471 | rt2800_bbp_write(rt2x00dev, 69, 0x16); | |
1472 | rt2800_bbp_write(rt2x00dev, 73, 0x12); | |
1473 | } | |
1474 | ||
1475 | if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) | |
1476 | rt2800_bbp_write(rt2x00dev, 84, 0x19); | |
1477 | ||
1478 | if (rt2x00_intf_is_usb(rt2x00dev) && | |
1479 | rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) { | |
1480 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); | |
1481 | rt2800_bbp_write(rt2x00dev, 84, 0x99); | |
1482 | rt2800_bbp_write(rt2x00dev, 105, 0x05); | |
1483 | } | |
1484 | ||
1485 | if (rt2x00_intf_is_pci(rt2x00dev) && | |
1486 | rt2x00_rt(&rt2x00dev->chip, RT3052)) { | |
1487 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | |
1488 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); | |
1489 | rt2800_bbp_write(rt2x00dev, 80, 0x08); | |
1490 | } | |
1491 | ||
1492 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { | |
1493 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1494 | ||
1495 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1496 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1497 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
1498 | rt2800_bbp_write(rt2x00dev, reg_id, value); | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | EXPORT_SYMBOL_GPL(rt2800_init_bbp); | |
1505 | ||
1506 | static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, | |
1507 | bool bw40, u8 rfcsr24, u8 filter_target) | |
1508 | { | |
1509 | unsigned int i; | |
1510 | u8 bbp; | |
1511 | u8 rfcsr; | |
1512 | u8 passband; | |
1513 | u8 stopband; | |
1514 | u8 overtuned = 0; | |
1515 | ||
1516 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
1517 | ||
1518 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
1519 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); | |
1520 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
1521 | ||
1522 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); | |
1523 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); | |
1524 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
1525 | ||
1526 | /* | |
1527 | * Set power & frequency of passband test tone | |
1528 | */ | |
1529 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
1530 | ||
1531 | for (i = 0; i < 100; i++) { | |
1532 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
1533 | msleep(1); | |
1534 | ||
1535 | rt2800_bbp_read(rt2x00dev, 55, &passband); | |
1536 | if (passband) | |
1537 | break; | |
1538 | } | |
1539 | ||
1540 | /* | |
1541 | * Set power & frequency of stopband test tone | |
1542 | */ | |
1543 | rt2800_bbp_write(rt2x00dev, 24, 0x06); | |
1544 | ||
1545 | for (i = 0; i < 100; i++) { | |
1546 | rt2800_bbp_write(rt2x00dev, 25, 0x90); | |
1547 | msleep(1); | |
1548 | ||
1549 | rt2800_bbp_read(rt2x00dev, 55, &stopband); | |
1550 | ||
1551 | if ((passband - stopband) <= filter_target) { | |
1552 | rfcsr24++; | |
1553 | overtuned += ((passband - stopband) == filter_target); | |
1554 | } else | |
1555 | break; | |
1556 | ||
1557 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
1558 | } | |
1559 | ||
1560 | rfcsr24 -= !!overtuned; | |
1561 | ||
1562 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); | |
1563 | return rfcsr24; | |
1564 | } | |
1565 | ||
1566 | int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |
1567 | { | |
1568 | u8 rfcsr; | |
1569 | u8 bbp; | |
1570 | ||
1571 | if (rt2x00_intf_is_usb(rt2x00dev) && | |
1572 | rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION) | |
1573 | return 0; | |
1574 | ||
1575 | if (rt2x00_intf_is_pci(rt2x00dev)) { | |
1576 | if (!rt2x00_rf(&rt2x00dev->chip, RF3020) && | |
1577 | !rt2x00_rf(&rt2x00dev->chip, RF3021) && | |
1578 | !rt2x00_rf(&rt2x00dev->chip, RF3022)) | |
1579 | return 0; | |
1580 | } | |
1581 | ||
1582 | /* | |
1583 | * Init RF calibration. | |
1584 | */ | |
1585 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | |
1586 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | |
1587 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1588 | msleep(1); | |
1589 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | |
1590 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | |
1591 | ||
1592 | if (rt2x00_intf_is_usb(rt2x00dev)) { | |
1593 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
1594 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
1595 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
1596 | rt2800_rfcsr_write(rt2x00dev, 7, 0x70); | |
1597 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
1598 | rt2800_rfcsr_write(rt2x00dev, 10, 0x71); | |
1599 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
1600 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | |
1601 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
1602 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
1603 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
1604 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
1605 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
1606 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
1607 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
1608 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
1609 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | |
1610 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
1611 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | |
1612 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); | |
1613 | } else if (rt2x00_intf_is_pci(rt2x00dev)) { | |
1614 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); | |
1615 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | |
1616 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | |
1617 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | |
1618 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | |
1619 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | |
1620 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | |
1621 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | |
1622 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | |
1623 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | |
1624 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | |
1625 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | |
1626 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | |
1627 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | |
1628 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | |
1629 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | |
1630 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | |
1631 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | |
1632 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | |
1633 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | |
1634 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | |
1635 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | |
1636 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | |
1637 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | |
1638 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | |
1639 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | |
1640 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | |
1641 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | |
1642 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | |
1643 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | |
1644 | } | |
1645 | ||
1646 | /* | |
1647 | * Set RX Filter calibration for 20MHz and 40MHz | |
1648 | */ | |
1649 | rt2x00dev->calibration[0] = | |
1650 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); | |
1651 | rt2x00dev->calibration[1] = | |
1652 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); | |
1653 | ||
1654 | /* | |
1655 | * Set back to initial state | |
1656 | */ | |
1657 | rt2800_bbp_write(rt2x00dev, 24, 0); | |
1658 | ||
1659 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); | |
1660 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); | |
1661 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); | |
1662 | ||
1663 | /* | |
1664 | * set BBP back to BW20 | |
1665 | */ | |
1666 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | |
1667 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); | |
1668 | rt2800_bbp_write(rt2x00dev, 4, bbp); | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); | |
2ce33995 | 1673 | |
30e84034 BZ |
1674 | int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) |
1675 | { | |
1676 | u32 reg; | |
1677 | ||
1678 | rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®); | |
1679 | ||
1680 | return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); | |
1681 | } | |
1682 | EXPORT_SYMBOL_GPL(rt2800_efuse_detect); | |
1683 | ||
1684 | static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) | |
1685 | { | |
1686 | u32 reg; | |
1687 | ||
31a4cf1f GW |
1688 | mutex_lock(&rt2x00dev->csr_mutex); |
1689 | ||
1690 | rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®); | |
30e84034 BZ |
1691 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
1692 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); | |
1693 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); | |
31a4cf1f | 1694 | rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); |
30e84034 BZ |
1695 | |
1696 | /* Wait until the EEPROM has been loaded */ | |
1697 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); | |
1698 | ||
1699 | /* Apparently the data is read from end to start */ | |
31a4cf1f GW |
1700 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, |
1701 | (u32 *)&rt2x00dev->eeprom[i]); | |
1702 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, | |
1703 | (u32 *)&rt2x00dev->eeprom[i + 2]); | |
1704 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, | |
1705 | (u32 *)&rt2x00dev->eeprom[i + 4]); | |
1706 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, | |
1707 | (u32 *)&rt2x00dev->eeprom[i + 6]); | |
1708 | ||
1709 | mutex_unlock(&rt2x00dev->csr_mutex); | |
30e84034 BZ |
1710 | } |
1711 | ||
1712 | void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) | |
1713 | { | |
1714 | unsigned int i; | |
1715 | ||
1716 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) | |
1717 | rt2800_efuse_read(rt2x00dev, i); | |
1718 | } | |
1719 | EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); | |
1720 | ||
38bd7b8a BZ |
1721 | int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
1722 | { | |
1723 | u16 word; | |
1724 | u8 *mac; | |
1725 | u8 default_lna_gain; | |
1726 | ||
1727 | /* | |
1728 | * Start validation of the data that has been read. | |
1729 | */ | |
1730 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1731 | if (!is_valid_ether_addr(mac)) { | |
1732 | random_ether_addr(mac); | |
1733 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); | |
1734 | } | |
1735 | ||
1736 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1737 | if (word == 0xffff) { | |
1738 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); | |
1739 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1); | |
1740 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820); | |
1741 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1742 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1743 | } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) { | |
1744 | /* | |
1745 | * There is a max of 2 RX streams for RT28x0 series | |
1746 | */ | |
1747 | if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2) | |
1748 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); | |
1749 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1750 | } | |
1751 | ||
1752 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1753 | if (word == 0xffff) { | |
1754 | rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0); | |
1755 | rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0); | |
1756 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); | |
1757 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); | |
1758 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); | |
1759 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0); | |
1760 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0); | |
1761 | rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0); | |
1762 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0); | |
1763 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0); | |
1764 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1765 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1766 | } | |
1767 | ||
1768 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1769 | if ((word & 0x00ff) == 0x00ff) { | |
1770 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1771 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, | |
1772 | LED_MODE_TXRX_ACTIVITY); | |
1773 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); | |
1774 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
1775 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555); | |
1776 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221); | |
1777 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8); | |
1778 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
1779 | } | |
1780 | ||
1781 | /* | |
1782 | * During the LNA validation we are going to use | |
1783 | * lna0 as correct value. Note that EEPROM_LNA | |
1784 | * is never validated. | |
1785 | */ | |
1786 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); | |
1787 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); | |
1788 | ||
1789 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); | |
1790 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) | |
1791 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); | |
1792 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) | |
1793 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); | |
1794 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); | |
1795 | ||
1796 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); | |
1797 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) | |
1798 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); | |
1799 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || | |
1800 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) | |
1801 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, | |
1802 | default_lna_gain); | |
1803 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); | |
1804 | ||
1805 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); | |
1806 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) | |
1807 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); | |
1808 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) | |
1809 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); | |
1810 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); | |
1811 | ||
1812 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); | |
1813 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) | |
1814 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); | |
1815 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || | |
1816 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) | |
1817 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, | |
1818 | default_lna_gain); | |
1819 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); | |
1824 | ||
1825 | int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1826 | { | |
1827 | u32 reg; | |
1828 | u16 value; | |
1829 | u16 eeprom; | |
1830 | ||
1831 | /* | |
1832 | * Read EEPROM word for configuration. | |
1833 | */ | |
1834 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1835 | ||
1836 | /* | |
1837 | * Identify RF chipset. | |
1838 | */ | |
1839 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
1840 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); | |
1841 | ||
f273fe55 GW |
1842 | rt2x00_set_chip_rf(rt2x00dev, value, reg); |
1843 | ||
38bd7b8a BZ |
1844 | if (rt2x00_intf_is_usb(rt2x00dev)) { |
1845 | struct rt2x00_chip *chip = &rt2x00dev->chip; | |
1846 | ||
38bd7b8a BZ |
1847 | /* |
1848 | * The check for rt2860 is not a typo, some rt2870 hardware | |
1849 | * identifies itself as rt2860 in the CSR register. | |
1850 | */ | |
f273fe55 GW |
1851 | if (rt2x00_check_rev(chip, 0xfff00000, 0x28600000) || |
1852 | rt2x00_check_rev(chip, 0xfff00000, 0x28700000) || | |
1853 | rt2x00_check_rev(chip, 0xfff00000, 0x28800000)) { | |
1854 | rt2x00_set_chip_rt(rt2x00dev, RT2870); | |
1855 | } else if (rt2x00_check_rev(chip, 0xffff0000, 0x30700000)) { | |
1856 | rt2x00_set_chip_rt(rt2x00dev, RT3070); | |
1857 | } else { | |
38bd7b8a BZ |
1858 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
1859 | return -ENODEV; | |
1860 | } | |
f273fe55 | 1861 | } |
16475b09 | 1862 | rt2x00_print_chip(rt2x00dev); |
38bd7b8a BZ |
1863 | |
1864 | if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && | |
1865 | !rt2x00_rf(&rt2x00dev->chip, RF2850) && | |
1866 | !rt2x00_rf(&rt2x00dev->chip, RF2720) && | |
1867 | !rt2x00_rf(&rt2x00dev->chip, RF2750) && | |
1868 | !rt2x00_rf(&rt2x00dev->chip, RF3020) && | |
1869 | !rt2x00_rf(&rt2x00dev->chip, RF2020) && | |
f273fe55 GW |
1870 | !rt2x00_rf(&rt2x00dev->chip, RF3021) && |
1871 | !rt2x00_rf(&rt2x00dev->chip, RF3022)) { | |
38bd7b8a BZ |
1872 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
1873 | return -ENODEV; | |
1874 | } | |
1875 | ||
1876 | /* | |
1877 | * Identify default antenna configuration. | |
1878 | */ | |
1879 | rt2x00dev->default_ant.tx = | |
1880 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH); | |
1881 | rt2x00dev->default_ant.rx = | |
1882 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH); | |
1883 | ||
1884 | /* | |
1885 | * Read frequency offset and RF programming sequence. | |
1886 | */ | |
1887 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1888 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1889 | ||
1890 | /* | |
1891 | * Read external LNA informations. | |
1892 | */ | |
1893 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1894 | ||
1895 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) | |
1896 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
1897 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) | |
1898 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
1899 | ||
1900 | /* | |
1901 | * Detect if this device has an hardware controlled radio. | |
1902 | */ | |
1903 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO)) | |
1904 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); | |
1905 | ||
1906 | /* | |
1907 | * Store led settings, for correct led behaviour. | |
1908 | */ | |
1909 | #ifdef CONFIG_RT2X00_LIB_LEDS | |
1910 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); | |
1911 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
1912 | rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); | |
1913 | ||
1914 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); | |
1915 | #endif /* CONFIG_RT2X00_LIB_LEDS */ | |
1916 | ||
1917 | return 0; | |
1918 | } | |
1919 | EXPORT_SYMBOL_GPL(rt2800_init_eeprom); | |
1920 | ||
4da2933f BZ |
1921 | /* |
1922 | * RF value list for rt28x0 | |
1923 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) | |
1924 | */ | |
1925 | static const struct rf_channel rf_vals[] = { | |
1926 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, | |
1927 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, | |
1928 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, | |
1929 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, | |
1930 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, | |
1931 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, | |
1932 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, | |
1933 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, | |
1934 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, | |
1935 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, | |
1936 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, | |
1937 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, | |
1938 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, | |
1939 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, | |
1940 | ||
1941 | /* 802.11 UNI / HyperLan 2 */ | |
1942 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, | |
1943 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, | |
1944 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, | |
1945 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, | |
1946 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, | |
1947 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, | |
1948 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, | |
1949 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, | |
1950 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, | |
1951 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, | |
1952 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, | |
1953 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, | |
1954 | ||
1955 | /* 802.11 HyperLan 2 */ | |
1956 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, | |
1957 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, | |
1958 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, | |
1959 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, | |
1960 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, | |
1961 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, | |
1962 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, | |
1963 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, | |
1964 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, | |
1965 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, | |
1966 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, | |
1967 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, | |
1968 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, | |
1969 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, | |
1970 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, | |
1971 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, | |
1972 | ||
1973 | /* 802.11 UNII */ | |
1974 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, | |
1975 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, | |
1976 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, | |
1977 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, | |
1978 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, | |
1979 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, | |
1980 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, | |
1981 | { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, | |
1982 | { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, | |
1983 | { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, | |
1984 | { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, | |
1985 | ||
1986 | /* 802.11 Japan */ | |
1987 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, | |
1988 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, | |
1989 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, | |
1990 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, | |
1991 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, | |
1992 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, | |
1993 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, | |
1994 | }; | |
1995 | ||
1996 | /* | |
1997 | * RF value list for rt3070 | |
1998 | * Supports: 2.4 GHz | |
1999 | */ | |
cce5fc45 | 2000 | static const struct rf_channel rf_vals_302x[] = { |
4da2933f BZ |
2001 | {1, 241, 2, 2 }, |
2002 | {2, 241, 2, 7 }, | |
2003 | {3, 242, 2, 2 }, | |
2004 | {4, 242, 2, 7 }, | |
2005 | {5, 243, 2, 2 }, | |
2006 | {6, 243, 2, 7 }, | |
2007 | {7, 244, 2, 2 }, | |
2008 | {8, 244, 2, 7 }, | |
2009 | {9, 245, 2, 2 }, | |
2010 | {10, 245, 2, 7 }, | |
2011 | {11, 246, 2, 2 }, | |
2012 | {12, 246, 2, 7 }, | |
2013 | {13, 247, 2, 2 }, | |
2014 | {14, 248, 2, 4 }, | |
2015 | }; | |
2016 | ||
2017 | int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |
2018 | { | |
2019 | struct rt2x00_chip *chip = &rt2x00dev->chip; | |
2020 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
2021 | struct channel_info *info; | |
2022 | char *tx_power1; | |
2023 | char *tx_power2; | |
2024 | unsigned int i; | |
2025 | u16 eeprom; | |
2026 | ||
2027 | /* | |
2028 | * Initialize all hw fields. | |
2029 | */ | |
2030 | rt2x00dev->hw->flags = | |
2031 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
2032 | IEEE80211_HW_SIGNAL_DBM | | |
2033 | IEEE80211_HW_SUPPORTS_PS | | |
2034 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
2035 | ||
2036 | if (rt2x00_intf_is_usb(rt2x00dev)) | |
2037 | rt2x00dev->hw->extra_tx_headroom = | |
2038 | TXINFO_DESC_SIZE + TXWI_DESC_SIZE; | |
2039 | else if (rt2x00_intf_is_pci(rt2x00dev)) | |
2040 | rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE; | |
2041 | ||
2042 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); | |
2043 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | |
2044 | rt2x00_eeprom_addr(rt2x00dev, | |
2045 | EEPROM_MAC_ADDR_0)); | |
2046 | ||
2047 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
2048 | ||
2049 | /* | |
2050 | * Initialize hw_mode information. | |
2051 | */ | |
2052 | spec->supported_bands = SUPPORT_BAND_2GHZ; | |
2053 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
2054 | ||
2055 | if (rt2x00_rf(chip, RF2820) || | |
2056 | rt2x00_rf(chip, RF2720) || | |
cce5fc45 | 2057 | (rt2x00_intf_is_pci(rt2x00dev) && rt2x00_rf(chip, RF3052))) { |
4da2933f BZ |
2058 | spec->num_channels = 14; |
2059 | spec->channels = rf_vals; | |
cce5fc45 | 2060 | } else if (rt2x00_rf(chip, RF2850) || rt2x00_rf(chip, RF2750)) { |
4da2933f BZ |
2061 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
2062 | spec->num_channels = ARRAY_SIZE(rf_vals); | |
2063 | spec->channels = rf_vals; | |
cce5fc45 GW |
2064 | } else if (rt2x00_rf(chip, RF3020) || |
2065 | rt2x00_rf(chip, RF2020) || | |
2066 | rt2x00_rf(chip, RF3021) || | |
2067 | rt2x00_rf(chip, RF3022)) { | |
2068 | spec->num_channels = ARRAY_SIZE(rf_vals_302x); | |
2069 | spec->channels = rf_vals_302x; | |
4da2933f BZ |
2070 | } |
2071 | ||
2072 | /* | |
2073 | * Initialize HT information. | |
2074 | */ | |
2075 | spec->ht.ht_supported = true; | |
2076 | spec->ht.cap = | |
2077 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
2078 | IEEE80211_HT_CAP_GRN_FLD | | |
2079 | IEEE80211_HT_CAP_SGI_20 | | |
2080 | IEEE80211_HT_CAP_SGI_40 | | |
2081 | IEEE80211_HT_CAP_TX_STBC | | |
2082 | IEEE80211_HT_CAP_RX_STBC | | |
2083 | IEEE80211_HT_CAP_PSMP_SUPPORT; | |
2084 | spec->ht.ampdu_factor = 3; | |
2085 | spec->ht.ampdu_density = 4; | |
2086 | spec->ht.mcs.tx_params = | |
2087 | IEEE80211_HT_MCS_TX_DEFINED | | |
2088 | IEEE80211_HT_MCS_TX_RX_DIFF | | |
2089 | ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) << | |
2090 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
2091 | ||
2092 | switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) { | |
2093 | case 3: | |
2094 | spec->ht.mcs.rx_mask[2] = 0xff; | |
2095 | case 2: | |
2096 | spec->ht.mcs.rx_mask[1] = 0xff; | |
2097 | case 1: | |
2098 | spec->ht.mcs.rx_mask[0] = 0xff; | |
2099 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ | |
2100 | break; | |
2101 | } | |
2102 | ||
2103 | /* | |
2104 | * Create channel information array | |
2105 | */ | |
2106 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); | |
2107 | if (!info) | |
2108 | return -ENOMEM; | |
2109 | ||
2110 | spec->channels_info = info; | |
2111 | ||
2112 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); | |
2113 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); | |
2114 | ||
2115 | for (i = 0; i < 14; i++) { | |
2116 | info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]); | |
2117 | info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]); | |
2118 | } | |
2119 | ||
2120 | if (spec->num_channels > 14) { | |
2121 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); | |
2122 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); | |
2123 | ||
2124 | for (i = 14; i < spec->num_channels; i++) { | |
2125 | info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]); | |
2126 | info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]); | |
2127 | } | |
2128 | } | |
2129 | ||
2130 | return 0; | |
2131 | } | |
2132 | EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode); | |
2133 | ||
2ce33995 BZ |
2134 | /* |
2135 | * IEEE80211 stack callback functions. | |
2136 | */ | |
2137 | static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, | |
2138 | u32 *iv32, u16 *iv16) | |
2139 | { | |
2140 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2141 | struct mac_iveiv_entry iveiv_entry; | |
2142 | u32 offset; | |
2143 | ||
2144 | offset = MAC_IVEIV_ENTRY(hw_key_idx); | |
2145 | rt2800_register_multiread(rt2x00dev, offset, | |
2146 | &iveiv_entry, sizeof(iveiv_entry)); | |
2147 | ||
2148 | memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16)); | |
2149 | memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32)); | |
2150 | } | |
2151 | ||
2152 | static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) | |
2153 | { | |
2154 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2155 | u32 reg; | |
2156 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); | |
2157 | ||
2158 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); | |
2159 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); | |
2160 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); | |
2161 | ||
2162 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); | |
2163 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); | |
2164 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); | |
2165 | ||
2166 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); | |
2167 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); | |
2168 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); | |
2169 | ||
2170 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); | |
2171 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); | |
2172 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); | |
2173 | ||
2174 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); | |
2175 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); | |
2176 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); | |
2177 | ||
2178 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); | |
2179 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); | |
2180 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); | |
2181 | ||
2182 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); | |
2183 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); | |
2184 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); | |
2185 | ||
2186 | return 0; | |
2187 | } | |
2188 | ||
2189 | static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, | |
2190 | const struct ieee80211_tx_queue_params *params) | |
2191 | { | |
2192 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2193 | struct data_queue *queue; | |
2194 | struct rt2x00_field32 field; | |
2195 | int retval; | |
2196 | u32 reg; | |
2197 | u32 offset; | |
2198 | ||
2199 | /* | |
2200 | * First pass the configuration through rt2x00lib, that will | |
2201 | * update the queue settings and validate the input. After that | |
2202 | * we are free to update the registers based on the value | |
2203 | * in the queue parameter. | |
2204 | */ | |
2205 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
2206 | if (retval) | |
2207 | return retval; | |
2208 | ||
2209 | /* | |
2210 | * We only need to perform additional register initialization | |
2211 | * for WMM queues/ | |
2212 | */ | |
2213 | if (queue_idx >= 4) | |
2214 | return 0; | |
2215 | ||
2216 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | |
2217 | ||
2218 | /* Update WMM TXOP register */ | |
2219 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); | |
2220 | field.bit_offset = (queue_idx & 1) * 16; | |
2221 | field.bit_mask = 0xffff << field.bit_offset; | |
2222 | ||
2223 | rt2800_register_read(rt2x00dev, offset, ®); | |
2224 | rt2x00_set_field32(®, field, queue->txop); | |
2225 | rt2800_register_write(rt2x00dev, offset, reg); | |
2226 | ||
2227 | /* Update WMM registers */ | |
2228 | field.bit_offset = queue_idx * 4; | |
2229 | field.bit_mask = 0xf << field.bit_offset; | |
2230 | ||
2231 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); | |
2232 | rt2x00_set_field32(®, field, queue->aifs); | |
2233 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); | |
2234 | ||
2235 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); | |
2236 | rt2x00_set_field32(®, field, queue->cw_min); | |
2237 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); | |
2238 | ||
2239 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); | |
2240 | rt2x00_set_field32(®, field, queue->cw_max); | |
2241 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); | |
2242 | ||
2243 | /* Update EDCA registers */ | |
2244 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); | |
2245 | ||
2246 | rt2800_register_read(rt2x00dev, offset, ®); | |
2247 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); | |
2248 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); | |
2249 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); | |
2250 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); | |
2251 | rt2800_register_write(rt2x00dev, offset, reg); | |
2252 | ||
2253 | return 0; | |
2254 | } | |
2255 | ||
2256 | static u64 rt2800_get_tsf(struct ieee80211_hw *hw) | |
2257 | { | |
2258 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2259 | u64 tsf; | |
2260 | u32 reg; | |
2261 | ||
2262 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); | |
2263 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; | |
2264 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); | |
2265 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); | |
2266 | ||
2267 | return tsf; | |
2268 | } | |
2269 | ||
2270 | const struct ieee80211_ops rt2800_mac80211_ops = { | |
2271 | .tx = rt2x00mac_tx, | |
2272 | .start = rt2x00mac_start, | |
2273 | .stop = rt2x00mac_stop, | |
2274 | .add_interface = rt2x00mac_add_interface, | |
2275 | .remove_interface = rt2x00mac_remove_interface, | |
2276 | .config = rt2x00mac_config, | |
2277 | .configure_filter = rt2x00mac_configure_filter, | |
2278 | .set_tim = rt2x00mac_set_tim, | |
2279 | .set_key = rt2x00mac_set_key, | |
2280 | .get_stats = rt2x00mac_get_stats, | |
2281 | .get_tkip_seq = rt2800_get_tkip_seq, | |
2282 | .set_rts_threshold = rt2800_set_rts_threshold, | |
2283 | .bss_info_changed = rt2x00mac_bss_info_changed, | |
2284 | .conf_tx = rt2800_conf_tx, | |
2285 | .get_tx_stats = rt2x00mac_get_tx_stats, | |
2286 | .get_tsf = rt2800_get_tsf, | |
2287 | .rfkill_poll = rt2x00mac_rfkill_poll, | |
2288 | }; | |
2289 | EXPORT_SYMBOL_GPL(rt2800_mac80211_ops); |