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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c
ID		 402
403 if (rt2x00_is_pci(rt2x00dev))
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
405
406 /*
407 * Disable DMA, will be reenabled later when enabling
408 * the radio.
409 */
410 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
417
418 /*
419 * Write firmware to the device.
420 */
421 rt2800_drv_write_firmware(rt2x00dev, data, len);
422
423 /*
424 * Wait for device to stabilize.
425 */
426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
428 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429 break;
430 msleep(1);
431 }
432
433 if (i == REGISTER_BUSY_COUNT) {
434 ERROR(rt2x00dev, "PBF system register not ready.\n");
435 return -EBUSY;
436 }
437
438 /*
439 * Initialize firmware.
440 */
441 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
443 msleep(1);
444
445 return 0;
446}
447EXPORT_SYMBOL_GPL(rt2800_load_firmware);
448
0c5879bc
ID		 449void rt2800_write_tx_data(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
59679b91 451{
0c5879bc 452 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 453 u32 word;
454
455 /*
456 * Initialize TX Info descriptor
457 */
458 rt2x00_desc_read(txwi, 0, &word);
459 rt2x00_set_field32(&word, TXWI_W0_FRAG,
460 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 461 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 463 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464 rt2x00_set_field32(&word, TXWI_W0_TS,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word);
478
479 rt2x00_desc_read(txwi, 1, &word);
480 rt2x00_set_field32(&word, TXWI_W1_ACK,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff);
488 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
489 txdesc->length);
2b23cdaa 490 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 491 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 492 rt2x00_desc_write(txwi, 1, word);
493
494 /*
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
500 */
501 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
503}
0c5879bc 504EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 505
ff6133be 506static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 507{
74861922
ID		 508 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
511 u16 eeprom;
512 u8 offset0;
513 u8 offset1;
514 u8 offset2;
515
e5ef5bad 516 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 517 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
522 } else {
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
528 }
529
530 /*
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
534 */
535 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
538
539 /*
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
544 */
545 rssi0 = max(rssi0, rssi1);
546 return max(rssi0, rssi2);
547}
548
549void rt2800_process_rxwi(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc)
551{
552 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 553 u32 word;
554
555 rt2x00_desc_read(rxwi, 0, &word);
556
557 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
559
560 rt2x00_desc_read(rxwi, 1, &word);
561
562 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563 rxdesc->flags |= RX_FLAG_SHORT_GI;
564
565 if (rt2x00_get_field32(word, RXWI_W1_BW))
566 rxdesc->flags |= RX_FLAG_40MHZ;
567
568 /*
569 * Detect RX rate, always use MCS as signal type.
570 */
571 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
574
575 /*
576 * Mask of 0x8 bit to remove the short preamble flag.
577 */
578 if (rxdesc->rate_mode == RATE_MODE_CCK)
579 rxdesc->signal &= ~0x8;
580
581 rt2x00_desc_read(rxwi, 2, &word);
582
74861922
ID		 583 /*
584 * Convert descriptor AGC value to RSSI value.
585 */
586 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 587
588 /*
589 * Remove RXWI descriptor from start of buffer.
590 */
74861922 591 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 592}
593EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
594
3613884d
ID		 595static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
596{
597 __le32 *txwi;
598 u32 word;
599 int wcid, ack, pid;
600 int tx_wcid, tx_ack, tx_pid;
601
602 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
605
606 /*
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
609 * frame.
610 */
611 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
613 return false;
614 }
615
616 /*
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
619 */
620 txwi = rt2800_drv_get_txwi(entry);
621
622 rt2x00_desc_read(txwi, 1, &word);
623 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
625 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
626
627 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628 WARNING(entry->queue->rt2x00dev,
629 "TX status report missed for queue %d entry %d\n",
630 entry->queue->qid, entry->entry_idx);
631 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
632 return false;
633 }
634
635 return true;
636}
637
14433331
HS		 638void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
639{
640 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 642 struct txdone_entry_desc txdesc;
643 u32 word;
644 u16 mcs, real_mcs;
b34793ee 645 int aggr, ampdu;
14433331
HS		 646 __le32 *txwi;
647
648 /*
649 * Obtain the status about this packet.
650 */
651 txdesc.flags = 0;
652 txwi = rt2800_drv_get_txwi(entry);
653 rt2x00_desc_read(txwi, 0, &word);
b34793ee 654
14433331 655 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 656 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
657
14433331 658 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 659 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
660
661 /*
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
666 *
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
672 *
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
675 * data.
676 */
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678 skbdesc->tx_rate_idx = real_mcs;
679 mcs = real_mcs;
680 }
14433331
HS		 681
682 /*
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
688 */
689 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
690 /*
691 * Transmission succeeded. The number of retries is
692 * mcs - real_mcs
693 */
694 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
696 } else {
697 /*
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
700 * frames sent).
701 */
702 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703 txdesc.retry = rt2x00dev->long_retry;
704 }
705
706 /*
707 * the frame was retried at least once
708 * -> hw used fallback rates
709 */
710 if (txdesc.retry)
711 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
712
713 rt2x00lib_txdone(entry, &txdesc);
714}
715EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
716
96481b20
ID		 717void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
718{
719 struct data_queue *queue;
720 struct queue_entry *entry;
96481b20 721 u32 reg;
3613884d 722 u8 pid;
96481b20
ID		 723 int i;
724
725 /*
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
729 *
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
733 */
efd2f271 734 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 735 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737 break;
738
96481b20
ID		 739 /*
740 * Skip this entry when it contains an invalid
741 * queue identication number.
742 */
bc8a979e 743 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 744 if (pid >= QID_RX)
96481b20
ID		 745 continue;
746
3613884d 747 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 748 if (unlikely(!queue))
749 continue;
750
751 /*
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
754 */
755 entry = NULL;
756 while (!rt2x00queue_empty(queue)) {
757 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 758 if (rt2800_txdone_entry_check(entry, reg))
96481b20 759 break;
96481b20
ID		 760 }
761
762 if (!entry || rt2x00queue_empty(queue))
763 break;
764
14433331 765 rt2800_txdone_entry(entry, reg);
96481b20
ID		 766 }
767}
768EXPORT_SYMBOL_GPL(rt2800_txdone);
769
f0194b2d
GW		 770void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
771{
772 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base;
739fd940 775 unsigned int padding_len;
f0194b2d
GW		 776 u32 reg;
777
778 /*
779 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data.
781 */
782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
783 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
784 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
785
786 /*
787 * Add space for the TXWI in front of the skb.
788 */
789 skb_push(entry->skb, TXWI_DESC_SIZE);
790 memset(entry->skb, 0, TXWI_DESC_SIZE);
791
792 /*
793 * Register descriptor details in skb frame descriptor.
794 */
795 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
796 skbdesc->desc = entry->skb->data;
797 skbdesc->desc_len = TXWI_DESC_SIZE;
798
799 /*
800 * Add the TXWI for the beacon to the skb.
801 */
0c5879bc 802 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 803
804 /*
805 * Dump beacon to userspace through debugfs.
806 */
807 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
808
809 /*
739fd940 810 * Write entire beacon with TXWI and padding to register.
f0194b2d 811 */
739fd940
WK		 812 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
813 skb_pad(entry->skb, padding_len);
f0194b2d 814 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 815 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
816 entry->skb->len + padding_len);
f0194b2d
GW		 817
818 /*
819 * Enable beaconing again.
820 */
821 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
822 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
826 /*
827 * Clean up beacon skb.
828 */
829 dev_kfree_skb_any(entry->skb);
830 entry->skb = NULL;
831}
50e888ea 832EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 833
bf1b1512 834static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
fdb87251
HS		 835 unsigned int beacon_base)
836{
837 int i;
838
839 /*
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon.
843 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846}
847
f4450616
BZ		 848#ifdef CONFIG_RT2X00_LIB_DEBUGFS
849const struct rt2x00debug rt2800_rt2x00debug = {
850 .owner = THIS_MODULE,
851 .csr = {
852 .read = rt2800_register_read,
853 .write = rt2800_register_write,
854 .flags = RT2X00DEBUGFS_OFFSET,
855 .word_base = CSR_REG_BASE,
856 .word_size = sizeof(u32),
857 .word_count = CSR_REG_SIZE / sizeof(u32),
858 },
859 .eeprom = {
860 .read = rt2x00_eeprom_read,
861 .write = rt2x00_eeprom_write,
862 .word_base = EEPROM_BASE,
863 .word_size = sizeof(u16),
864 .word_count = EEPROM_SIZE / sizeof(u16),
865 },
866 .bbp = {
867 .read = rt2800_bbp_read,
868 .write = rt2800_bbp_write,
869 .word_base = BBP_BASE,
870 .word_size = sizeof(u8),
871 .word_count = BBP_SIZE / sizeof(u8),
872 },
873 .rf = {
874 .read = rt2x00_rf_read,
875 .write = rt2800_rf_write,
876 .word_base = RF_BASE,
877 .word_size = sizeof(u32),
878 .word_count = RF_SIZE / sizeof(u32),
879 },
880};
881EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
882#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
883
884int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
885{
886 u32 reg;
887
888 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
889 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
890}
891EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
892
893#ifdef CONFIG_RT2X00_LIB_LEDS
894static void rt2800_brightness_set(struct led_classdev *led_cdev,
895 enum led_brightness brightness)
896{
897 struct rt2x00_led *led =
898 container_of(led_cdev, struct rt2x00_led, led_dev);
899 unsigned int enabled = brightness != LED_OFF;
900 unsigned int bg_mode =
901 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
902 unsigned int polarity =
903 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
904 EEPROM_FREQ_LED_POLARITY);
905 unsigned int ledmode =
906 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
907 EEPROM_FREQ_LED_MODE);
908
909 if (led->type == LED_TYPE_RADIO) {
910 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
911 enabled ? 0x20 : 0);
912 } else if (led->type == LED_TYPE_ASSOC) {
913 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
914 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
915 } else if (led->type == LED_TYPE_QUALITY) {
916 /*
917 * The brightness is divided into 6 levels (0 - 5),
918 * The specs tell us the following levels:
919 * 0, 1 ,3, 7, 15, 31
920 * to determine the level in a simple way we can simply
921 * work with bitshifting:
922 * (1 << level) - 1
923 */
924 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
925 (1 << brightness / (LED_FULL / 6)) - 1,
926 polarity);
927 }
928}
929
930static int rt2800_blink_set(struct led_classdev *led_cdev,
931 unsigned long *delay_on, unsigned long *delay_off)
932{
933 struct rt2x00_led *led =
934 container_of(led_cdev, struct rt2x00_led, led_dev);
935 u32 reg;
936
937 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
938 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
939 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 940 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
941
942 return 0;
943}
944
b3579d6a 945static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 946 struct rt2x00_led *led, enum led_type type)
947{
948 led->rt2x00dev = rt2x00dev;
949 led->type = type;
950 led->led_dev.brightness_set = rt2800_brightness_set;
951 led->led_dev.blink_set = rt2800_blink_set;
952 led->flags = LED_INITIALIZED;
953}
f4450616
BZ		 954#endif /* CONFIG_RT2X00_LIB_LEDS */
955
956/*
957 * Configuration handlers.
958 */
959static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
960 struct rt2x00lib_crypto *crypto,
961 struct ieee80211_key_conf *key)
962{
963 struct mac_wcid_entry wcid_entry;
964 struct mac_iveiv_entry iveiv_entry;
965 u32 offset;
966 u32 reg;
967
968 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
969
e4a0ab34
ID		 970 if (crypto->cmd == SET_KEY) {
971 rt2800_register_read(rt2x00dev, offset, &reg);
972 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
973 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
974 /*
975 * Both the cipher as the BSS Idx numbers are split in a main
976 * value of 3 bits, and a extended field for adding one additional
977 * bit to the value.
978 */
979 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
980 (crypto->cipher & 0x7));
981 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
982 (crypto->cipher & 0x8) >> 3);
983 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
984 (crypto->bssidx & 0x7));
985 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
986 (crypto->bssidx & 0x8) >> 3);
987 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
988 rt2800_register_write(rt2x00dev, offset, reg);
989 } else {
990 rt2800_register_write(rt2x00dev, offset, 0);
991 }
f4450616
BZ		 992
993 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
994
995 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
996 if ((crypto->cipher == CIPHER_TKIP) ||
997 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
998 (crypto->cipher == CIPHER_AES))
999 iveiv_entry.iv[3] |= 0x20;
1000 iveiv_entry.iv[3] |= key->keyidx << 6;
1001 rt2800_register_multiwrite(rt2x00dev, offset,
1002 &iveiv_entry, sizeof(iveiv_entry));
1003
1004 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1005
1006 memset(&wcid_entry, 0, sizeof(wcid_entry));
1007 if (crypto->cmd == SET_KEY)
1008 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1009 rt2800_register_multiwrite(rt2x00dev, offset,
1010 &wcid_entry, sizeof(wcid_entry));
1011}
1012
1013int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1014 struct rt2x00lib_crypto *crypto,
1015 struct ieee80211_key_conf *key)
1016{
1017 struct hw_key_entry key_entry;
1018 struct rt2x00_field32 field;
1019 u32 offset;
1020 u32 reg;
1021
1022 if (crypto->cmd == SET_KEY) {
1023 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1024
1025 memcpy(key_entry.key, crypto->key,
1026 sizeof(key_entry.key));
1027 memcpy(key_entry.tx_mic, crypto->tx_mic,
1028 sizeof(key_entry.tx_mic));
1029 memcpy(key_entry.rx_mic, crypto->rx_mic,
1030 sizeof(key_entry.rx_mic));
1031
1032 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1033 rt2800_register_multiwrite(rt2x00dev, offset,
1034 &key_entry, sizeof(key_entry));
1035 }
1036
1037 /*
1038 * The cipher types are stored over multiple registers
1039 * starting with SHARED_KEY_MODE_BASE each word will have
1040 * 32 bits and contains the cipher types for 2 bssidx each.
1041 * Using the correct defines correctly will cause overhead,
1042 * so just calculate the correct offset.
1043 */
1044 field.bit_offset = 4 * (key->hw_key_idx % 8);
1045 field.bit_mask = 0x7 << field.bit_offset;
1046
1047 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1048
1049 rt2800_register_read(rt2x00dev, offset, &reg);
1050 rt2x00_set_field32(&reg, field,
1051 (crypto->cmd == SET_KEY) * crypto->cipher);
1052 rt2800_register_write(rt2x00dev, offset, reg);
1053
1054 /*
1055 * Update WCID information
1056 */
1057 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1058
1059 return 0;
1060}
1061EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1062
1063int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1064 struct rt2x00lib_crypto *crypto,
1065 struct ieee80211_key_conf *key)
1066{
1067 struct hw_key_entry key_entry;
1068 u32 offset;
1069
1070 if (crypto->cmd == SET_KEY) {
1071 /*
1072 * 1 pairwise key is possible per AID, this means that the AID
1073 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1074 * last possible shared key entry.
2a0cfeb8
HS		 1075 *
1076 * Since parts of the pairwise key table might be shared with
1077 * the beacon frame buffers 6 & 7 we should only write into the
1078 * first 222 entries.
f4450616 1079 */
2a0cfeb8 1080 if (crypto->aid > (222 - 32))
f4450616
BZ		 1081 return -ENOSPC;
1082
1083 key->hw_key_idx = 32 + crypto->aid;
1084
1085 memcpy(key_entry.key, crypto->key,
1086 sizeof(key_entry.key));
1087 memcpy(key_entry.tx_mic, crypto->tx_mic,
1088 sizeof(key_entry.tx_mic));
1089 memcpy(key_entry.rx_mic, crypto->rx_mic,
1090 sizeof(key_entry.rx_mic));
1091
1092 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1093 rt2800_register_multiwrite(rt2x00dev, offset,
1094 &key_entry, sizeof(key_entry));
1095 }
1096
1097 /*
1098 * Update WCID information
1099 */
1100 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1101
1102 return 0;
1103}
1104EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1105
1106void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1107 const unsigned int filter_flags)
1108{
1109 u32 reg;
1110
1111 /*
1112 * Start configuration steps.
1113 * Note that the version error will always be dropped
1114 * and broadcast frames will always be accepted since
1115 * there is no filter for it at this time.
1116 */
1117 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1118 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1119 !(filter_flags & FIF_FCSFAIL));
1120 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1121 !(filter_flags & FIF_PLCPFAIL));
1122 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1123 !(filter_flags & FIF_PROMISC_IN_BSS));
1124 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1125 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1126 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1127 !(filter_flags & FIF_ALLMULTI));
1128 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1129 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1130 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1131 !(filter_flags & FIF_CONTROL));
1132 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1133 !(filter_flags & FIF_CONTROL));
1134 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1135 !(filter_flags & FIF_CONTROL));
1136 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1137 !(filter_flags & FIF_CONTROL));
1138 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1139 !(filter_flags & FIF_CONTROL));
1140 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1141 !(filter_flags & FIF_PSPOLL));
1142 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1143 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1144 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1145 !(filter_flags & FIF_CONTROL));
1146 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1147}
1148EXPORT_SYMBOL_GPL(rt2800_config_filter);
1149
1150void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1151 struct rt2x00intf_conf *conf, const unsigned int flags)
1152{
f4450616 1153 u32 reg;
fa8b4b22 1154 bool update_bssid = false;
f4450616
BZ		 1155
1156 if (flags & CONFIG_UPDATE_TYPE) {
1157 /*
1158 * Clear current synchronisation setup.
f4450616 1159 */
fdb87251
HS		 1160 rt2800_clear_beacon(rt2x00dev,
1161 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 1162 /*
1163 * Enable synchronisation.
1164 */
1165 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1166 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1167 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 1168 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 1169 (conf->sync == TSF_SYNC_ADHOC ||
1170 conf->sync == TSF_SYNC_AP_NONE));
f4450616 1171 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 1172
1173 /*
1174 * Enable pre tbtt interrupt for beaconing modes
1175 */
1176 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1177 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 1178 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 1179 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1180
f4450616
BZ		 1181 }
1182
1183 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1184 if (flags & CONFIG_UPDATE_TYPE &&
1185 conf->sync == TSF_SYNC_AP_NONE) {
1186 /*
1187 * The BSSID register has to be set to our own mac
1188 * address in AP mode.
1189 */
1190 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1191 update_bssid = true;
1192 }
1193
c600c826
ID		 1194 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1195 reg = le32_to_cpu(conf->mac[1]);
1196 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1197 conf->mac[1] = cpu_to_le32(reg);
1198 }
f4450616
BZ		 1199
1200 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1201 conf->mac, sizeof(conf->mac));
1202 }
1203
fa8b4b22 1204 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1205 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1206 reg = le32_to_cpu(conf->bssid[1]);
1207 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1208 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1209 conf->bssid[1] = cpu_to_le32(reg);
1210 }
f4450616
BZ		 1211
1212 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1213 conf->bssid, sizeof(conf->bssid));
1214 }
1215}
1216EXPORT_SYMBOL_GPL(rt2800_config_intf);
1217
87c1915d
HS		 1218static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1219 struct rt2x00lib_erp *erp)
1220{
1221 bool any_sta_nongf = !!(erp->ht_opmode &
1222 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1223 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1224 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1225 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1226 u32 reg;
1227
1228 /* default protection rate for HT20: OFDM 24M */
1229 mm20_rate = gf20_rate = 0x4004;
1230
1231 /* default protection rate for HT40: duplicate OFDM 24M */
1232 mm40_rate = gf40_rate = 0x4084;
1233
1234 switch (protection) {
1235 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1236 /*
1237 * All STAs in this BSS are HT20/40 but there might be
1238 * STAs not supporting greenfield mode.
1239 * => Disable protection for HT transmissions.
1240 */
1241 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1242
1243 break;
1244 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1245 /*
1246 * All STAs in this BSS are HT20 or HT20/40 but there
1247 * might be STAs not supporting greenfield mode.
1248 * => Protect all HT40 transmissions.
1249 */
1250 mm20_mode = gf20_mode = 0;
1251 mm40_mode = gf40_mode = 2;
1252
1253 break;
1254 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1255 /*
1256 * Nonmember protection:
1257 * According to 802.11n we _should_ protect all
1258 * HT transmissions (but we don't have to).
1259 *
1260 * But if cts_protection is enabled we _shall_ protect
1261 * all HT transmissions using a CCK rate.
1262 *
1263 * And if any station is non GF we _shall_ protect
1264 * GF transmissions.
1265 *
1266 * We decide to protect everything
1267 * -> fall through to mixed mode.
1268 */
1269 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1270 /*
1271 * Legacy STAs are present
1272 * => Protect all HT transmissions.
1273 */
1274 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1275
1276 /*
1277 * If erp protection is needed we have to protect HT
1278 * transmissions with CCK 11M long preamble.
1279 */
1280 if (erp->cts_protection) {
1281 /* don't duplicate RTS/CTS in CCK mode */
1282 mm20_rate = mm40_rate = 0x0003;
1283 gf20_rate = gf40_rate = 0x0003;
1284 }
1285 break;
1286 };
1287
1288 /* check for STAs not supporting greenfield mode */
1289 if (any_sta_nongf)
1290 gf20_mode = gf40_mode = 2;
1291
1292 /* Update HT protection config */
1293 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1294 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1295 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1296 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1297
1298 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1299 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1300 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1301 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1302
1303 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1304 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1305 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1306 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1307
1308 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1309 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1310 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1311 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1312}
1313
02044643
HS		 1314void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1315 u32 changed)
f4450616
BZ		 1316{
1317 u32 reg;
1318
02044643
HS		 1319 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1320 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1321 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1322 !!erp->short_preamble);
1323 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1324 !!erp->short_preamble);
1325 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1326 }
f4450616 1327
02044643
HS		 1328 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1329 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1330 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1331 erp->cts_protection ? 2 : 0);
1332 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1333 }
f4450616 1334
02044643
HS		 1335 if (changed & BSS_CHANGED_BASIC_RATES) {
1336 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1337 erp->basic_rates);
1338 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1339 }
f4450616 1340
02044643
HS		 1341 if (changed & BSS_CHANGED_ERP_SLOT) {
1342 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1343 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1344 erp->slot_time);
1345 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1346
02044643
HS		 1347 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1348 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1349 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1350 }
f4450616 1351
02044643
HS		 1352 if (changed & BSS_CHANGED_BEACON_INT) {
1353 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1354 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1355 erp->beacon_int * 16);
1356 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1357 }
87c1915d
HS		 1358
1359 if (changed & BSS_CHANGED_HT)
1360 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1361}
1362EXPORT_SYMBOL_GPL(rt2800_config_erp);
1363
1364void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1365{
1366 u8 r1;
1367 u8 r3;
1368
1369 rt2800_bbp_read(rt2x00dev, 1, &r1);
1370 rt2800_bbp_read(rt2x00dev, 3, &r3);
1371
1372 /*
1373 * Configure the TX antenna.
1374 */
1375 switch ((int)ant->tx) {
1376 case 1:
1377 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1378 break;
1379 case 2:
1380 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1381 break;
1382 case 3:
e22557f2 1383 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1384 break;
1385 }
1386
1387 /*
1388 * Configure the RX antenna.
1389 */
1390 switch ((int)ant->rx) {
1391 case 1:
1392 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1393 break;
1394 case 2:
1395 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1396 break;
1397 case 3:
1398 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1399 break;
1400 }
1401
1402 rt2800_bbp_write(rt2x00dev, 3, r3);
1403 rt2800_bbp_write(rt2x00dev, 1, r1);
1404}
1405EXPORT_SYMBOL_GPL(rt2800_config_ant);
1406
1407static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1408 struct rt2x00lib_conf *libconf)
1409{
1410 u16 eeprom;
1411 short lna_gain;
1412
1413 if (libconf->rf.channel <= 14) {
1414 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1415 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1416 } else if (libconf->rf.channel <= 64) {
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1418 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1419 } else if (libconf->rf.channel <= 128) {
1420 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1421 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1422 } else {
1423 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1424 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1425 }
1426
1427 rt2x00dev->lna_gain = lna_gain;
1428}
1429
06855ef4
GW		 1430static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1431 struct ieee80211_conf *conf,
1432 struct rf_channel *rf,
1433 struct channel_info *info)
f4450616
BZ		 1434{
1435 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1436
1437 if (rt2x00dev->default_ant.tx == 1)
1438 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1439
1440 if (rt2x00dev->default_ant.rx == 1) {
1441 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1442 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1443 } else if (rt2x00dev->default_ant.rx == 2)
1444 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1445
1446 if (rf->channel > 14) {
1447 /*
1448 * When TX power is below 0, we should increase it by 7 to
1449 * make it a positive value (Minumum value is -7).
1450 * However this means that values between 0 and 7 have
1451 * double meaning, and we should set a 7DBm boost flag.
1452 */
1453 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1454 (info->default_power1 >= 0));
f4450616 1455
8d1331b3
ID		 1456 if (info->default_power1 < 0)
1457 info->default_power1 += 7;
f4450616 1458
8d1331b3 1459 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1460
1461 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1462 (info->default_power2 >= 0));
f4450616 1463
8d1331b3
ID		 1464 if (info->default_power2 < 0)
1465 info->default_power2 += 7;
f4450616 1466
8d1331b3 1467 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1468 } else {
8d1331b3
ID		 1469 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1470 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1471 }
1472
1473 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1474
1475 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1476 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1477 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1478 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1479
1480 udelay(200);
1481
1482 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1483 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1484 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1485 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1486
1487 udelay(200);
1488
1489 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1490 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1491 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1492 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1493}
1494
06855ef4
GW		 1495static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1496 struct ieee80211_conf *conf,
1497 struct rf_channel *rf,
1498 struct channel_info *info)
f4450616
BZ		 1499{
1500 u8 rfcsr;
1501
1502 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1503 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1504
1505 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1506 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1507 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1508
1509 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1510 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1511 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1512
5a673964 1513 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1514 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1515 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1516
f4450616
BZ		 1517 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1518 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1519 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1520
1521 rt2800_rfcsr_write(rt2x00dev, 24,
1522 rt2x00dev->calibration[conf_is_ht40(conf)]);
1523
71976907 1524 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1525 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1526 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1527}
1528
1529static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1530 struct ieee80211_conf *conf,
1531 struct rf_channel *rf,
1532 struct channel_info *info)
1533{
1534 u32 reg;
1535 unsigned int tx_pin;
1536 u8 bbp;
1537
46323e11 1538 if (rf->channel <= 14) {
8d1331b3
ID		 1539 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1540 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1541 } else {
8d1331b3
ID		 1542 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1543 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1544 }
1545
06855ef4
GW		 1546 if (rt2x00_rf(rt2x00dev, RF2020) ||
1547 rt2x00_rf(rt2x00dev, RF3020) ||
1548 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1549 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1550 rt2x00_rf(rt2x00dev, RF3052) ||
1551 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1552 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1553 else
06855ef4 1554 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1555
1556 /*
1557 * Change BBP settings
1558 */
1559 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1560 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1561 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1562 rt2800_bbp_write(rt2x00dev, 86, 0);
1563
1564 if (rf->channel <= 14) {
1565 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1566 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1567 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1568 } else {
1569 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1570 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1571 }
1572 } else {
1573 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1574
1575 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1576 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1577 else
1578 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1579 }
1580
1581 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1582 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1583 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1584 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1585 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1586
1587 tx_pin = 0;
1588
1589 /* Turn on unused PA or LNA when not using 1T or 1R */
1590 if (rt2x00dev->default_ant.tx != 1) {
1591 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1592 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1593 }
1594
1595 /* Turn on unused PA or LNA when not using 1T or 1R */
1596 if (rt2x00dev->default_ant.rx != 1) {
1597 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1599 }
1600
1601 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1602 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1603 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1604 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1605 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1606 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1607
1608 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1609
1610 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1611 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1612 rt2800_bbp_write(rt2x00dev, 4, bbp);
1613
1614 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1615 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1616 rt2800_bbp_write(rt2x00dev, 3, bbp);
1617
8d0c9b65 1618 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1619 if (conf_is_ht40(conf)) {
1620 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1621 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1622 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1623 } else {
1624 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1625 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1626 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1627 }
1628 }
1629
1630 msleep(1);
977206d7
HS		 1631
1632 /*
1633 * Clear channel statistic counters
1634 */
1635 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1636 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1637 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1638}
1639
1640static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1641 const int max_txpower)
f4450616 1642{
5e846004
HS		 1643 u8 txpower;
1644 u8 max_value = (u8)max_txpower;
1645 u16 eeprom;
1646 int i;
f4450616 1647 u32 reg;
f4450616 1648 u8 r1;
5e846004 1649 u32 offset;
f4450616 1650
5e846004
HS		 1651 /*
1652 * set to normal tx power mode: +/- 0dBm
1653 */
f4450616 1654 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1655 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1656 rt2800_bbp_write(rt2x00dev, 1, r1);
1657
5e846004
HS		 1658 /*
1659 * The eeprom contains the tx power values for each rate. These
1660 * values map to 100% tx power. Each 16bit word contains four tx
1661 * power values and the order is the same as used in the TX_PWR_CFG
1662 * registers.
1663 */
1664 offset = TX_PWR_CFG_0;
1665
1666 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1667 /* just to be safe */
1668 if (offset > TX_PWR_CFG_4)
1669 break;
1670
1671 rt2800_register_read(rt2x00dev, offset, &reg);
1672
1673 /* read the next four txpower values */
1674 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1675 &eeprom);
1676
1677 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1678 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1679 * TX_PWR_CFG_4: unknown */
1680 txpower = rt2x00_get_field16(eeprom,
1681 EEPROM_TXPOWER_BYRATE_RATE0);
1682 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1683 min(txpower, max_value));
1684
1685 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1686 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1687 * TX_PWR_CFG_4: unknown */
1688 txpower = rt2x00_get_field16(eeprom,
1689 EEPROM_TXPOWER_BYRATE_RATE1);
1690 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1691 min(txpower, max_value));
1692
1693 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1694 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1695 * TX_PWR_CFG_4: unknown */
1696 txpower = rt2x00_get_field16(eeprom,
1697 EEPROM_TXPOWER_BYRATE_RATE2);
1698 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1699 min(txpower, max_value));
1700
1701 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1702 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1703 * TX_PWR_CFG_4: unknown */
1704 txpower = rt2x00_get_field16(eeprom,
1705 EEPROM_TXPOWER_BYRATE_RATE3);
1706 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1707 min(txpower, max_value));
1708
1709 /* read the next four txpower values */
1710 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1711 &eeprom);
1712
1713 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1714 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1715 * TX_PWR_CFG_4: unknown */
1716 txpower = rt2x00_get_field16(eeprom,
1717 EEPROM_TXPOWER_BYRATE_RATE0);
1718 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1719 min(txpower, max_value));
1720
1721 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1722 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1723 * TX_PWR_CFG_4: unknown */
1724 txpower = rt2x00_get_field16(eeprom,
1725 EEPROM_TXPOWER_BYRATE_RATE1);
1726 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1727 min(txpower, max_value));
1728
1729 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1730 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1731 * TX_PWR_CFG_4: unknown */
1732 txpower = rt2x00_get_field16(eeprom,
1733 EEPROM_TXPOWER_BYRATE_RATE2);
1734 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1735 min(txpower, max_value));
1736
1737 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1738 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1739 * TX_PWR_CFG_4: unknown */
1740 txpower = rt2x00_get_field16(eeprom,
1741 EEPROM_TXPOWER_BYRATE_RATE3);
1742 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1743 min(txpower, max_value));
1744
1745 rt2800_register_write(rt2x00dev, offset, reg);
1746
1747 /* next TX_PWR_CFG register */
1748 offset += 4;
1749 }
f4450616
BZ		 1750}
1751
1752static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1753 struct rt2x00lib_conf *libconf)
1754{
1755 u32 reg;
1756
1757 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1758 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1759 libconf->conf->short_frame_max_tx_count);
1760 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1761 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1762 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1763}
1764
1765static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1766 struct rt2x00lib_conf *libconf)
1767{
1768 enum dev_state state =
1769 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1770 STATE_SLEEP : STATE_AWAKE;
1771 u32 reg;
1772
1773 if (state == STATE_SLEEP) {
1774 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1775
1776 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1777 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1778 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1779 libconf->conf->listen_interval - 1);
1780 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1781 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1782
1783 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1784 } else {
f4450616
BZ		 1785 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1786 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1787 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1788 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1789 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1790
1791 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1792 }
1793}
1794
1795void rt2800_config(struct rt2x00_dev *rt2x00dev,
1796 struct rt2x00lib_conf *libconf,
1797 const unsigned int flags)
1798{
1799 /* Always recalculate LNA gain before changing configuration */
1800 rt2800_config_lna_gain(rt2x00dev, libconf);
1801
1802 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1803 rt2800_config_channel(rt2x00dev, libconf->conf,
1804 &libconf->rf, &libconf->channel);
1805 if (flags & IEEE80211_CONF_CHANGE_POWER)
1806 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1807 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1808 rt2800_config_retry_limit(rt2x00dev, libconf);
1809 if (flags & IEEE80211_CONF_CHANGE_PS)
1810 rt2800_config_ps(rt2x00dev, libconf);
1811}
1812EXPORT_SYMBOL_GPL(rt2800_config);
1813
1814/*
1815 * Link tuning
1816 */
1817void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1818{
1819 u32 reg;
1820
1821 /*
1822 * Update FCS error count from register.
1823 */
1824 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1825 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1826}
1827EXPORT_SYMBOL_GPL(rt2800_link_stats);
1828
1829static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1830{
1831 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1832 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1833 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1834 rt2x00_rt(rt2x00dev, RT3090) ||
1835 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1836 return 0x1c + (2 * rt2x00dev->lna_gain);
1837 else
1838 return 0x2e + rt2x00dev->lna_gain;
1839 }
1840
1841 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1842 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1843 else
1844 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1845}
1846
1847static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1848 struct link_qual *qual, u8 vgc_level)
1849{
1850 if (qual->vgc_level != vgc_level) {
1851 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1852 qual->vgc_level = vgc_level;
1853 qual->vgc_level_reg = vgc_level;
1854 }
1855}
1856
1857void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1858{
1859 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1860}
1861EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1862
1863void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1864 const u32 count)
1865{
8d0c9b65 1866 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1867 return;
1868
1869 /*
1870 * When RSSI is better then -80 increase VGC level with 0x10
1871 */
1872 rt2800_set_vgc(rt2x00dev, qual,
1873 rt2800_get_default_vgc(rt2x00dev) +
1874 ((qual->rssi > -80) * 0x10));
1875}
1876EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1877
1878/*
1879 * Initialization functions.
1880 */
b9a07ae9 1881static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1882{
1883 u32 reg;
d5385bfc 1884 u16 eeprom;
fcf51541 1885 unsigned int i;
e3a896b9 1886 int ret;
fcf51541 1887
a9dce149
GW		 1888 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1889 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1890 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1891 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1892 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1893 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1894 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1895
e3a896b9
GW		 1896 ret = rt2800_drv_init_registers(rt2x00dev);
1897 if (ret)
1898 return ret;
fcf51541
BZ		 1899
1900 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1901 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1902 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1903 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1904 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1905 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1906
1907 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1908 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1909 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1910 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1911 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1912 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1913
1914 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1915 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1916
1917 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1918
1919 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1920 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1921 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1922 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1923 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1924 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1925 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1926 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1927
a9dce149
GW		 1928 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1929
1930 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1931 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1932 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1933 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1934
64522957 1935 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1936 rt2x00_rt(rt2x00dev, RT3090) ||
1937 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1938 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1939 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1940 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1941 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1942 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 1943 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1944 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 1945 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1946 0x0000002c);
1947 else
1948 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1949 0x0000000f);
1950 } else {
1951 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1952 }
d5385bfc 1953 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1954 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1955
1956 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1957 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1958 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1959 } else {
1960 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1961 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1962 }
c295a81d
HS		 1963 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1964 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1965 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1966 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1967 } else {
1968 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1969 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1970 }
1971
1972 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1973 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1974 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1975 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1976 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1977 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1978 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1979 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1980 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1981 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1982
1983 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1984 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1985 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1986 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1987 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1988
1989 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1990 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1991 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1992 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1993 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1994 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1995 else
1996 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1997 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1998 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1999 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2000
a9dce149
GW		 2001 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2002 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2003 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2004 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2005 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2006 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2007 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2008 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2009 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2010
fcf51541
BZ		 2011 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2012
a9dce149
GW		 2013 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2014 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2015 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2016 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2017 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2018 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2019 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2020 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2021
fcf51541
BZ		 2022 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2023 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2024 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2025 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2026 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2027 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2028 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2029 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2030 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2031
2032 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2033 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2034 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2035 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2036 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2037 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2038 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2039 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2040 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2041 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2042 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2043 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2044
2045 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2046 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2047 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2048 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2049 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2050 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2051 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2052 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2053 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2054 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2055 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2056 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2057
2058 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2059 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2060 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2061 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2062 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2063 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2064 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2065 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2066 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2067 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2068 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2069 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2070
2071 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2072 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2073 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2074 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2075 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2076 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2077 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2078 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2079 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2080 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2081 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2082 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2083
2084 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2085 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2086 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2087 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2088 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2089 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2090 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2091 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2092 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2093 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2094 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2095 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2096
2097 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2098 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2099 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2100 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2101 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2102 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2103 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2104 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2105 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2106 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2107 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2108 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2109
cea90e55 2110 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2111 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2112
2113 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2114 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2115 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2116 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2117 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2118 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2119 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2120 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2121 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2122 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2123 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2124 }
2125
961621ab
HS		 2126 /*
2127 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2128 * although it is reserved.
2129 */
2130 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2131 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2132 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2133 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2134 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2135 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2136 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2137 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2138 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2139 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2140 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2141 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2142
fcf51541
BZ		 2143 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2144
2145 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2146 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2147 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2148 IEEE80211_MAX_RTS_THRESHOLD);
2149 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2150 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2151
2152 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2153
a21c2ab4
HS		 2154 /*
2155 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2156 * time should be set to 16. However, the original Ralink driver uses
2157 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2158 * connection problems with 11g + CTS protection. Hence, use the same
2159 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2160 */
a9dce149 2161 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2162 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2163 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2164 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2165 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2166 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2167 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2168
fcf51541
BZ		 2169 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2170
2171 /*
2172 * ASIC will keep garbage value after boot, clear encryption keys.
2173 */
2174 for (i = 0; i < 4; i++)
2175 rt2800_register_write(rt2x00dev,
2176 SHARED_KEY_MODE_ENTRY(i), 0);
2177
2178 for (i = 0; i < 256; i++) {
f4e16e41 2179 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2180 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2181 wcid, sizeof(wcid));
2182
2183 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2184 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2185 }
2186
2187 /*
2188 * Clear all beacons
fcf51541 2189 */
fdb87251
HS		 2190 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2191 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2192 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2193 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2194 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2195 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2196 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2197 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2198
cea90e55 2199 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2200 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2201 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2202 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2203 }
2204
2205 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2206 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2207 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2208 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2209 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2210 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2211 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2212 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2213 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2214 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2215
2216 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2217 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2218 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2219 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2220 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2221 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2222 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2223 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2224 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2225 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2226
2227 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2228 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2229 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2230 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2231 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2232 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2233 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2234 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2235 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2236 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2237
2238 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2239 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2240 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2241 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2242 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2243 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2244
47ee3eb1
HS		 2245 /*
2246 * Do not force the BA window size, we use the TXWI to set it
2247 */
2248 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2249 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2250 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2251 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2252
fcf51541
BZ		 2253 /*
2254 * We must clear the error counters.
2255 * These registers are cleared on read,
2256 * so we may pass a useless variable to store the value.
2257 */
2258 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2259 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2260 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2261 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2262 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2263 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2264
9f926fb5
HS		 2265 /*
2266 * Setup leadtime for pre tbtt interrupt to 6ms
2267 */
2268 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2269 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2270 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2271
977206d7
HS		 2272 /*
2273 * Set up channel statistics timer
2274 */
2275 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2276 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2277 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2278 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2279 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2280 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2281 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2282
fcf51541
BZ		 2283 return 0;
2284}
fcf51541
BZ		 2285
2286static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2287{
2288 unsigned int i;
2289 u32 reg;
2290
2291 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2292 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2293 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2294 return 0;
2295
2296 udelay(REGISTER_BUSY_DELAY);
2297 }
2298
2299 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2300 return -EACCES;
2301}
2302
2303static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2304{
2305 unsigned int i;
2306 u8 value;
2307
2308 /*
2309 * BBP was enabled after firmware was loaded,
2310 * but we need to reactivate it now.
2311 */
2312 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2313 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2314 msleep(1);
2315
2316 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2317 rt2800_bbp_read(rt2x00dev, 0, &value);
2318 if ((value != 0xff) && (value != 0x00))
2319 return 0;
2320 udelay(REGISTER_BUSY_DELAY);
2321 }
2322
2323 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2324 return -EACCES;
2325}
2326
b9a07ae9 2327static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2328{
2329 unsigned int i;
2330 u16 eeprom;
2331 u8 reg_id;
2332 u8 value;
2333
2334 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2335 rt2800_wait_bbp_ready(rt2x00dev)))
2336 return -EACCES;
2337
baff8006
HS		 2338 if (rt2800_is_305x_soc(rt2x00dev))
2339 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2340
fcf51541
BZ		 2341 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2342 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2343
2344 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2345 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2346 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2347 } else {
2348 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2349 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2350 }
2351
fcf51541 2352 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2353
d5385bfc 2354 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2355 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2356 rt2x00_rt(rt2x00dev, RT3090) ||
2357 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2358 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2359 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2360 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2361 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2362 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2363 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2364 } else {
2365 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2366 }
2367
fcf51541
BZ		 2368 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2369 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2370
5ed8f458 2371 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2372 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2373 else
2374 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2375
fcf51541
BZ		 2376 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2377 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2378 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2379
d5385bfc 2380 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2381 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2382 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2383 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2384 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2385 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2386 else
2387 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2388
baff8006
HS		 2389 if (rt2800_is_305x_soc(rt2x00dev))
2390 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2391 else
2392 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2393 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2394
64522957 2395 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2396 rt2x00_rt(rt2x00dev, RT3090) ||
2397 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2398 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2399
38c8a566
RJH		 2400 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2401 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2402 value |= 0x20;
38c8a566 2403 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2404 value &= ~0x02;
fcf51541 2405
d5385bfc 2406 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2407 }
2408
fcf51541
BZ		 2409
2410 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2411 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2412
2413 if (eeprom != 0xffff && eeprom != 0x0000) {
2414 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2415 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2416 rt2800_bbp_write(rt2x00dev, reg_id, value);
2417 }
2418 }
2419
2420 return 0;
2421}
fcf51541
BZ		 2422
2423static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2424 bool bw40, u8 rfcsr24, u8 filter_target)
2425{
2426 unsigned int i;
2427 u8 bbp;
2428 u8 rfcsr;
2429 u8 passband;
2430 u8 stopband;
2431 u8 overtuned = 0;
2432
2433 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2434
2435 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2436 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2437 rt2800_bbp_write(rt2x00dev, 4, bbp);
2438
80d184e6
RJH		 2439 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2440 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2441 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2442
fcf51541
BZ		 2443 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2444 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2445 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2446
2447 /*
2448 * Set power & frequency of passband test tone
2449 */
2450 rt2800_bbp_write(rt2x00dev, 24, 0);
2451
2452 for (i = 0; i < 100; i++) {
2453 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2454 msleep(1);
2455
2456 rt2800_bbp_read(rt2x00dev, 55, &passband);
2457 if (passband)
2458 break;
2459 }
2460
2461 /*
2462 * Set power & frequency of stopband test tone
2463 */
2464 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2465
2466 for (i = 0; i < 100; i++) {
2467 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2468 msleep(1);
2469
2470 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2471
2472 if ((passband - stopband) <= filter_target) {
2473 rfcsr24++;
2474 overtuned += ((passband - stopband) == filter_target);
2475 } else
2476 break;
2477
2478 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2479 }
2480
2481 rfcsr24 -= !!overtuned;
2482
2483 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2484 return rfcsr24;
2485}
2486
b9a07ae9 2487static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2488{
2489 u8 rfcsr;
2490 u8 bbp;
8cdd15e0
GW		 2491 u32 reg;
2492 u16 eeprom;
fcf51541 2493
d5385bfc 2494 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2495 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2496 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2497 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2498 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2499 return 0;
2500
fcf51541
BZ		 2501 /*
2502 * Init RF calibration.
2503 */
2504 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2505 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2506 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2507 msleep(1);
2508 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2509 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2510
d5385bfc 2511 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2512 rt2x00_rt(rt2x00dev, RT3071) ||
2513 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2514 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2515 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2516 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 2517 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 2518 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2519 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2520 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2521 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2522 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2523 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2524 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2525 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2526 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2527 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2528 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2529 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2530 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2531 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2532 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2533 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2534 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2535 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2536 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2537 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2538 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2539 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2540 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2541 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2542 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2543 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2544 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2545 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2546 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2547 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2548 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2549 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2550 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2551 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2552 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2553 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2554 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2555 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2556 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2557 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2558 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2559 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2560 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2561 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2562 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2563 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2564 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2565 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2566 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2567 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2568 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2569 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2570 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2571 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2572 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2573 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2574 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2575 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2576 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2577 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2578 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2579 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2580 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2581 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2582 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2583 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2584 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2585 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2586 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2587 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2588 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2589 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2590 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2591 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2592 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2593 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2594 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2595 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2596 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2597 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2598 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2599 return 0;
8cdd15e0
GW		 2600 }
2601
2602 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2603 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2604 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2605 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2606 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2607 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2608 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 2609 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2610
d5385bfc
GW		 2611 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2612 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2613 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2614
d5385bfc
GW		 2615 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2616 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2617 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2618 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 2619 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2620 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2621 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2622 else
2623 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2624 }
2625 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 2626
2627 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2628 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2629 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 2630 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2631 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2632 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2633 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2634 }
2635
2636 /*
2637 * Set RX Filter calibration for 20MHz and 40MHz
2638 */
8cdd15e0
GW		 2639 if (rt2x00_rt(rt2x00dev, RT3070)) {
2640 rt2x00dev->calibration[0] =
2641 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2642 rt2x00dev->calibration[1] =
2643 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2644 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2645 rt2x00_rt(rt2x00dev, RT3090) ||
2646 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2647 rt2x00dev->calibration[0] =
2648 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2649 rt2x00dev->calibration[1] =
2650 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2651 }
fcf51541
BZ		 2652
2653 /*
2654 * Set back to initial state
2655 */
2656 rt2800_bbp_write(rt2x00dev, 24, 0);
2657
2658 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2659 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2660 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2661
2662 /*
2663 * set BBP back to BW20
2664 */
2665 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2666 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2667 rt2800_bbp_write(rt2x00dev, 4, bbp);
2668
d5385bfc 2669 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2670 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2671 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2672 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2673 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2674
2675 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2676 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2677 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2678
2679 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2680 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
80d184e6
RJH		 2681 if (rt2x00_rt(rt2x00dev, RT3070) ||
2682 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2683 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2684 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
80d184e6 2685 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2686 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2687 }
8cdd15e0
GW		 2688 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2689 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2690 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2691 rt2x00_get_field16(eeprom,
2692 EEPROM_TXMIXER_GAIN_BG_VAL));
2693 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2694
64522957
GW		 2695 if (rt2x00_rt(rt2x00dev, RT3090)) {
2696 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2697
80d184e6 2698 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 2699 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2700 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 2701 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 2702 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 2703 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2704
2705 rt2800_bbp_write(rt2x00dev, 138, bbp);
2706 }
2707
2708 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2709 rt2x00_rt(rt2x00dev, RT3090) ||
2710 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2711 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2712 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2713 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2714 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2715 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2716 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2717 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2718
2719 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2720 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2721 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2722
2723 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2724 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2725 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2726
2727 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2728 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2729 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2730 }
2731
80d184e6 2732 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 2733 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 2734 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 2735 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2736 else
2737 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2738 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2739 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2740 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2741 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2742 }
2743
fcf51541
BZ		 2744 return 0;
2745}
b9a07ae9
ID		 2746
2747int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2748{
2749 u32 reg;
2750 u16 word;
2751
2752 /*
2753 * Initialize all registers.
2754 */
2755 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2756 rt2800_init_registers(rt2x00dev) ||
2757 rt2800_init_bbp(rt2x00dev) ||
2758 rt2800_init_rfcsr(rt2x00dev)))
2759 return -EIO;
2760
2761 /*
2762 * Send signal to firmware during boot time.
2763 */
2764 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2765
2766 if (rt2x00_is_usb(rt2x00dev) &&
2767 (rt2x00_rt(rt2x00dev, RT3070) ||
2768 rt2x00_rt(rt2x00dev, RT3071) ||
2769 rt2x00_rt(rt2x00dev, RT3572))) {
2770 udelay(200);
2771 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2772 udelay(10);
2773 }
2774
2775 /*
2776 * Enable RX.
2777 */
2778 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2779 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2780 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2781 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2782
2783 udelay(50);
2784
2785 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2786 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2787 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2788 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2789 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2790 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2791
2792 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2793 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2794 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2795 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2796
2797 /*
2798 * Initialize LED control
2799 */
38c8a566
RJH		 2800 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2801 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 2802 word & 0xff, (word >> 8) & 0xff);
2803
38c8a566
RJH		 2804 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2805 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 2806 word & 0xff, (word >> 8) & 0xff);
2807
38c8a566
RJH		 2808 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2809 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 2810 word & 0xff, (word >> 8) & 0xff);
2811
2812 return 0;
2813}
2814EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2815
2816void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2817{
2818 u32 reg;
2819
2820 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2821 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 2822 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 2823 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2824
2825 /* Wait for DMA, ignore error */
2826 rt2800_wait_wpdma_ready(rt2x00dev);
2827
2828 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2829 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2830 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2831 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 2832}
2833EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2834
30e84034
BZ		 2835int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2836{
2837 u32 reg;
2838
2839 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2840
2841 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2842}
2843EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2844
2845static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2846{
2847 u32 reg;
2848
31a4cf1f
GW		 2849 mutex_lock(&rt2x00dev->csr_mutex);
2850
2851 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2852 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2853 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2854 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2855 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2856
2857 /* Wait until the EEPROM has been loaded */
2858 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2859
2860 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2861 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2862 (u32 *)&rt2x00dev->eeprom[i]);
2863 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2864 (u32 *)&rt2x00dev->eeprom[i + 2]);
2865 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2866 (u32 *)&rt2x00dev->eeprom[i + 4]);
2867 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2868 (u32 *)&rt2x00dev->eeprom[i + 6]);
2869
2870 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2871}
2872
2873void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2874{
2875 unsigned int i;
2876
2877 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2878 rt2800_efuse_read(rt2x00dev, i);
2879}
2880EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2881
38bd7b8a
BZ		 2882int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2883{
2884 u16 word;
2885 u8 *mac;
2886 u8 default_lna_gain;
2887
2888 /*
2889 * Start validation of the data that has been read.
2890 */
2891 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2892 if (!is_valid_ether_addr(mac)) {
2893 random_ether_addr(mac);
2894 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2895 }
2896
38c8a566 2897 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 2898 if (word == 0xffff) {
38c8a566
RJH		 2899 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2900 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2901 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2902 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 2903 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2904 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2905 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2906 /*
2907 * There is a max of 2 RX streams for RT28x0 series
2908 */
38c8a566
RJH		 2909 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2910 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2911 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 2912 }
2913
38c8a566 2914 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 2915 if (word == 0xffff) {
38c8a566
RJH		 2916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2924 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2925 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2926 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2927 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2928 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2929 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2930 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2931 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 2932 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2933 }
2934
2935 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2936 if ((word & 0x00ff) == 0x00ff) {
2937 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2938 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2939 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2940 }
2941 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2942 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2943 LED_MODE_TXRX_ACTIVITY);
2944 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2945 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 2946 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2947 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2948 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 2949 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2950 }
2951
2952 /*
2953 * During the LNA validation we are going to use
2954 * lna0 as correct value. Note that EEPROM_LNA
2955 * is never validated.
2956 */
2957 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2958 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2959
2960 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2961 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2962 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2963 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2964 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2965 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2966
2967 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2968 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2969 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2970 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2971 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2972 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2973 default_lna_gain);
2974 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2975
2976 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2977 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2978 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2979 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2980 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2981 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2982
2983 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2984 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2985 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2986 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2987 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2988 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2989 default_lna_gain);
2990 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2991
8d1331b3
ID		 2992 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2993 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2994 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2995 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2996 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2997 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2998
38bd7b8a
BZ		 2999 return 0;
3000}
3001EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3002
3003int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3004{
3005 u32 reg;
3006 u16 value;
3007 u16 eeprom;
3008
3009 /*
3010 * Read EEPROM word for configuration.
3011 */
38c8a566 3012 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3013
3014 /*
3015 * Identify RF chipset.
3016 */
38c8a566 3017 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a
BZ		 3018 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3019
49e721ec
GW		 3020 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3021 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3022
3023 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3024 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3025 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3026 !rt2x00_rt(rt2x00dev, RT3070) &&
3027 !rt2x00_rt(rt2x00dev, RT3071) &&
3028 !rt2x00_rt(rt2x00dev, RT3090) &&
3029 !rt2x00_rt(rt2x00dev, RT3390) &&
3030 !rt2x00_rt(rt2x00dev, RT3572)) {
3031 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3032 return -ENODEV;
f273fe55 3033 }
714fa663 3034
5122d898
GW		 3035 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3036 !rt2x00_rf(rt2x00dev, RF2850) &&
3037 !rt2x00_rf(rt2x00dev, RF2720) &&
3038 !rt2x00_rf(rt2x00dev, RF2750) &&
3039 !rt2x00_rf(rt2x00dev, RF3020) &&
3040 !rt2x00_rf(rt2x00dev, RF2020) &&
3041 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3042 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3
GW		 3043 !rt2x00_rf(rt2x00dev, RF3052) &&
3044 !rt2x00_rf(rt2x00dev, RF3320)) {
38bd7b8a
BZ		 3045 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3046 return -ENODEV;
3047 }
3048
3049 /*
3050 * Identify default antenna configuration.
3051 */
3052 rt2x00dev->default_ant.tx =
38c8a566 3053 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
38bd7b8a 3054 rt2x00dev->default_ant.rx =
38c8a566 3055 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a
BZ		 3056
3057 /*
3058 * Read frequency offset and RF programming sequence.
3059 */
3060 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3061 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3062
3063 /*
3064 * Read external LNA informations.
3065 */
38c8a566 3066 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3067
38c8a566 3068 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
38bd7b8a 3069 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
38c8a566 3070 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
38bd7b8a
BZ		 3071 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3072
3073 /*
3074 * Detect if this device has an hardware controlled radio.
3075 */
38c8a566 3076 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
38bd7b8a
BZ		 3077 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3078
3079 /*
3080 * Store led settings, for correct led behaviour.
3081 */
3082#ifdef CONFIG_RT2X00_LIB_LEDS
3083 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3084 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3085 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3086
3087 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3088#endif /* CONFIG_RT2X00_LIB_LEDS */
3089
3090 return 0;
3091}
3092EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3093
4da2933f 3094/*
55f9321a 3095 * RF value list for rt28xx
4da2933f
BZ		 3096 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3097 */
3098static const struct rf_channel rf_vals[] = {
3099 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3100 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3101 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3102 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3103 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3104 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3105 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3106 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3107 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3108 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3109 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3110 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3111 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3112 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3113
3114 /* 802.11 UNI / HyperLan 2 */
3115 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3116 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3117 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3118 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3119 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3120 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3121 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3122 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3123 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3124 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3125 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3126 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3127
3128 /* 802.11 HyperLan 2 */
3129 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3130 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3131 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3132 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3133 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3134 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3135 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3136 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3137 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3138 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3139 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3140 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3141 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3142 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3143 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3144 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3145
3146 /* 802.11 UNII */
3147 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3148 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3149 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3150 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3151 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3152 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3153 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3154 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3155 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3156 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3157 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3158
3159 /* 802.11 Japan */
3160 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3161 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3162 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3163 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3164 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3165 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3166 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3167};
3168
3169/*
55f9321a
ID		 3170 * RF value list for rt3xxx
3171 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3172 */
55f9321a 3173static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3174 {1, 241, 2, 2 },
3175 {2, 241, 2, 7 },
3176 {3, 242, 2, 2 },
3177 {4, 242, 2, 7 },
3178 {5, 243, 2, 2 },
3179 {6, 243, 2, 7 },
3180 {7, 244, 2, 2 },
3181 {8, 244, 2, 7 },
3182 {9, 245, 2, 2 },
3183 {10, 245, 2, 7 },
3184 {11, 246, 2, 2 },
3185 {12, 246, 2, 7 },
3186 {13, 247, 2, 2 },
3187 {14, 248, 2, 4 },
55f9321a
ID		 3188
3189 /* 802.11 UNI / HyperLan 2 */
3190 {36, 0x56, 0, 4},
3191 {38, 0x56, 0, 6},
3192 {40, 0x56, 0, 8},
3193 {44, 0x57, 0, 0},
3194 {46, 0x57, 0, 2},
3195 {48, 0x57, 0, 4},
3196 {52, 0x57, 0, 8},
3197 {54, 0x57, 0, 10},
3198 {56, 0x58, 0, 0},
3199 {60, 0x58, 0, 4},
3200 {62, 0x58, 0, 6},
3201 {64, 0x58, 0, 8},
3202
3203 /* 802.11 HyperLan 2 */
3204 {100, 0x5b, 0, 8},
3205 {102, 0x5b, 0, 10},
3206 {104, 0x5c, 0, 0},
3207 {108, 0x5c, 0, 4},
3208 {110, 0x5c, 0, 6},
3209 {112, 0x5c, 0, 8},
3210 {116, 0x5d, 0, 0},
3211 {118, 0x5d, 0, 2},
3212 {120, 0x5d, 0, 4},
3213 {124, 0x5d, 0, 8},
3214 {126, 0x5d, 0, 10},
3215 {128, 0x5e, 0, 0},
3216 {132, 0x5e, 0, 4},
3217 {134, 0x5e, 0, 6},
3218 {136, 0x5e, 0, 8},
3219 {140, 0x5f, 0, 0},
3220
3221 /* 802.11 UNII */
3222 {149, 0x5f, 0, 9},
3223 {151, 0x5f, 0, 11},
3224 {153, 0x60, 0, 1},
3225 {157, 0x60, 0, 5},
3226 {159, 0x60, 0, 7},
3227 {161, 0x60, 0, 9},
3228 {165, 0x61, 0, 1},
3229 {167, 0x61, 0, 3},
3230 {169, 0x61, 0, 5},
3231 {171, 0x61, 0, 7},
3232 {173, 0x61, 0, 9},
4da2933f
BZ		 3233};
3234
3235int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3236{
4da2933f
BZ		 3237 struct hw_mode_spec *spec = &rt2x00dev->spec;
3238 struct channel_info *info;
8d1331b3
ID		 3239 char *default_power1;
3240 char *default_power2;
4da2933f 3241 unsigned int i;
8d1331b3 3242 unsigned short max_power;
4da2933f
BZ		 3243 u16 eeprom;
3244
93b6bd26
GW		 3245 /*
3246 * Disable powersaving as default on PCI devices.
3247 */
cea90e55 3248 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3249 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3250
4da2933f
BZ		 3251 /*
3252 * Initialize all hw fields.
3253 */
3254 rt2x00dev->hw->flags =
4da2933f
BZ		 3255 IEEE80211_HW_SIGNAL_DBM |
3256 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3257 IEEE80211_HW_PS_NULLFUNC_STACK |
3258 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3259 /*
3260 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3261 * unless we are capable of sending the buffered frames out after the
3262 * DTIM transmission using rt2x00lib_beacondone. This will send out
3263 * multicast and broadcast traffic immediately instead of buffering it
3264 * infinitly and thus dropping it after some time.
3265 */
3266 if (!rt2x00_is_usb(rt2x00dev))
3267 rt2x00dev->hw->flags |=
3268 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3269
4da2933f
BZ		 3270 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3271 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3272 rt2x00_eeprom_addr(rt2x00dev,
3273 EEPROM_MAC_ADDR_0));
3274
3f2bee24
HS		 3275 /*
3276 * As rt2800 has a global fallback table we cannot specify
3277 * more then one tx rate per frame but since the hw will
3278 * try several rates (based on the fallback table) we should
ba3b9e5e 3279 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3280 * we are going to try. Otherwise mac80211 will truncate our
3281 * reported tx rates and the rc algortihm will end up with
3282 * incorrect data.
3283 */
ba3b9e5e
HS		 3284 rt2x00dev->hw->max_rates = 1;
3285 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3286 rt2x00dev->hw->max_rate_tries = 1;
3287
38c8a566 3288 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3289
3290 /*
3291 * Initialize hw_mode information.
3292 */
3293 spec->supported_bands = SUPPORT_BAND_2GHZ;
3294 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3295
5122d898 3296 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3297 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3298 spec->num_channels = 14;
3299 spec->channels = rf_vals;
55f9321a
ID		 3300 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3301 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3302 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3303 spec->num_channels = ARRAY_SIZE(rf_vals);
3304 spec->channels = rf_vals;
5122d898
GW		 3305 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3306 rt2x00_rf(rt2x00dev, RF2020) ||
3307 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3
GW		 3308 rt2x00_rf(rt2x00dev, RF3022) ||
3309 rt2x00_rf(rt2x00dev, RF3320)) {
55f9321a
ID		 3310 spec->num_channels = 14;
3311 spec->channels = rf_vals_3x;
3312 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3313 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3314 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3315 spec->channels = rf_vals_3x;
4da2933f
BZ		 3316 }
3317
3318 /*
3319 * Initialize HT information.
3320 */
5122d898 3321 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3322 spec->ht.ht_supported = true;
3323 else
3324 spec->ht.ht_supported = false;
3325
4da2933f 3326 spec->ht.cap =
06443e46 3327 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3328 IEEE80211_HT_CAP_GRN_FLD |
3329 IEEE80211_HT_CAP_SGI_20 |
aa674631 3330 IEEE80211_HT_CAP_SGI_40;
22cabaa6 3331
38c8a566 3332 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 3333 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3334
aa674631 3335 spec->ht.cap |=
38c8a566 3336 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 3337 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3338
4da2933f
BZ		 3339 spec->ht.ampdu_factor = 3;
3340 spec->ht.ampdu_density = 4;
3341 spec->ht.mcs.tx_params =
3342 IEEE80211_HT_MCS_TX_DEFINED |
3343 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 3344 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 3345 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3346
38c8a566 3347 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 3348 case 3:
3349 spec->ht.mcs.rx_mask[2] = 0xff;
3350 case 2:
3351 spec->ht.mcs.rx_mask[1] = 0xff;
3352 case 1:
3353 spec->ht.mcs.rx_mask[0] = 0xff;
3354 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3355 break;
3356 }
3357
3358 /*
3359 * Create channel information array
3360 */
baeb2ffa 3361 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3362 if (!info)
3363 return -ENOMEM;
3364
3365 spec->channels_info = info;
3366
8d1331b3
ID		 3367 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3368 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3369 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3370 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3371
3372 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3373 info[i].max_power = max_power;
3374 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3375 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3376 }
3377
3378 if (spec->num_channels > 14) {
8d1331b3
ID		 3379 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3380 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3381 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3382
3383 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3384 info[i].max_power = max_power;
3385 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3386 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3387 }
3388 }
3389
3390 return 0;
3391}
3392EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3393
2ce33995
BZ		 3394/*
3395 * IEEE80211 stack callback functions.
3396 */
e783619e
HS		 3397void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3398 u16 *iv16)
2ce33995
BZ		 3399{
3400 struct rt2x00_dev *rt2x00dev = hw->priv;
3401 struct mac_iveiv_entry iveiv_entry;
3402 u32 offset;
3403
3404 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3405 rt2800_register_multiread(rt2x00dev, offset,
3406 &iveiv_entry, sizeof(iveiv_entry));
3407
855da5e0
JL		 3408 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3409 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3410}
e783619e 3411EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3412
e783619e 3413int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3414{
3415 struct rt2x00_dev *rt2x00dev = hw->priv;
3416 u32 reg;
3417 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3418
3419 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3420 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3421 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3422
3423 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3424 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3425 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3426
3427 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3428 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3429 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3430
3431 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3432 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3433 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3434
3435 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3436 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3437 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3438
3439 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3440 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3441 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3442
3443 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3444 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3445 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3446
3447 return 0;
3448}
e783619e 3449EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3450
e783619e
HS		 3451int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3452 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3453{
3454 struct rt2x00_dev *rt2x00dev = hw->priv;
3455 struct data_queue *queue;
3456 struct rt2x00_field32 field;
3457 int retval;
3458 u32 reg;
3459 u32 offset;
3460
3461 /*
3462 * First pass the configuration through rt2x00lib, that will
3463 * update the queue settings and validate the input. After that
3464 * we are free to update the registers based on the value
3465 * in the queue parameter.
3466 */
3467 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3468 if (retval)
3469 return retval;
3470
3471 /*
3472 * We only need to perform additional register initialization
3473 * for WMM queues/
3474 */
3475 if (queue_idx >= 4)
3476 return 0;
3477
3478 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3479
3480 /* Update WMM TXOP register */
3481 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3482 field.bit_offset = (queue_idx & 1) * 16;
3483 field.bit_mask = 0xffff << field.bit_offset;
3484
3485 rt2800_register_read(rt2x00dev, offset, &reg);
3486 rt2x00_set_field32(&reg, field, queue->txop);
3487 rt2800_register_write(rt2x00dev, offset, reg);
3488
3489 /* Update WMM registers */
3490 field.bit_offset = queue_idx * 4;
3491 field.bit_mask = 0xf << field.bit_offset;
3492
3493 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3494 rt2x00_set_field32(&reg, field, queue->aifs);
3495 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3496
3497 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3498 rt2x00_set_field32(&reg, field, queue->cw_min);
3499 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3500
3501 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3502 rt2x00_set_field32(&reg, field, queue->cw_max);
3503 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3504
3505 /* Update EDCA registers */
3506 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3507
3508 rt2800_register_read(rt2x00dev, offset, &reg);
3509 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3510 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3511 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3512 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3513 rt2800_register_write(rt2x00dev, offset, reg);
3514
3515 return 0;
3516}
e783619e 3517EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3518
e783619e 3519u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3520{
3521 struct rt2x00_dev *rt2x00dev = hw->priv;
3522 u64 tsf;
3523 u32 reg;
3524
3525 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3526 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3527 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3528 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3529
3530 return tsf;
3531}
e783619e 3532EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3533
e783619e
HS		 3534int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3535 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 3536 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3537 u8 buf_size)
1df90809 3538{
1df90809
HS		 3539 int ret = 0;
3540
3541 switch (action) {
3542 case IEEE80211_AMPDU_RX_START:
3543 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 3544 /*
3545 * The hw itself takes care of setting up BlockAck mechanisms.
3546 * So, we only have to allow mac80211 to nagotiate a BlockAck
3547 * agreement. Once that is done, the hw will BlockAck incoming
3548 * AMPDUs without further setup.
3549 */
1df90809
HS		 3550 break;
3551 case IEEE80211_AMPDU_TX_START:
3552 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3553 break;
3554 case IEEE80211_AMPDU_TX_STOP:
3555 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3556 break;
3557 case IEEE80211_AMPDU_TX_OPERATIONAL:
3558 break;
3559 default:
4e9e58c6 3560 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3561 }
3562
3563 return ret;
3564}
e783619e 3565EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 3566
977206d7
HS		 3567int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3568 struct survey_info *survey)
3569{
3570 struct rt2x00_dev *rt2x00dev = hw->priv;
3571 struct ieee80211_conf *conf = &hw->conf;
3572 u32 idle, busy, busy_ext;
3573
3574 if (idx != 0)
3575 return -ENOENT;
3576
3577 survey->channel = conf->channel;
3578
3579 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3580 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3581 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3582
3583 if (idle || busy) {
3584 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3585 SURVEY_INFO_CHANNEL_TIME_BUSY |
3586 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3587
3588 survey->channel_time = (idle + busy) / 1000;
3589 survey->channel_time_busy = busy / 1000;
3590 survey->channel_time_ext_busy = busy_ext / 1000;
3591 }
3592
3593 return 0;
3594
3595}
3596EXPORT_SYMBOL_GPL(rt2800_get_survey);
3597
a5ea2f02
ID		 3598MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3599MODULE_VERSION(DRV_VERSION);
3600MODULE_DESCRIPTION("Ralink RT2800 library");
3601MODULE_LICENSE("GPL");
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