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rt2x00: Add antenna setting for RT3070/RT3090/RT3390 with RX antenna diversity support
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f31c9a8c
ID		 298static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299{
300 u16 fw_crc;
301 u16 crc;
302
303 /*
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
306 * algorithm.
307 */
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310 /*
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
316 */
317 crc = crc_ccitt(~0, data, len - 2);
318
319 /*
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
323 * value.
324 */
325 crc = swab16(crc);
326
327 return fw_crc == crc;
328}
329
330int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
332{
333 size_t offset = 0;
334 size_t fw_len;
335 bool multiple;
336
337 /*
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
344 */
345 if (rt2x00_is_usb(rt2x00dev)) {
346 fw_len = 4096;
347 multiple = true;
348 } else {
349 fw_len = 8192;
350 multiple = true;
351 }
352
353 /*
354 * Validate the firmware length
355 */
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
358
359 /*
360 * Check if the chipset requires one of the upper parts
361 * of the firmware.
362 */
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
369
370 /*
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
373 */
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376 return FW_BAD_CRC;
377
378 offset += fw_len;
379 }
380
381 return FW_OK;
382}
383EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
387{
388 unsigned int i;
389 u32 reg;
390
391 /*
b9eca242
ID		 392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 394 */
b9eca242 395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 396
f31c9a8c
ID		 397 /*
398 * Wait for stable hardware.
399 */
5ffddc49 400 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 401 return -EBUSY;
f31c9a8c
ID		 402
403 if (rt2x00_is_pci(rt2x00dev))
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
405
406 /*
407 * Disable DMA, will be reenabled later when enabling
408 * the radio.
409 */
410 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
411 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
417
418 /*
419 * Write firmware to the device.
420 */
421 rt2800_drv_write_firmware(rt2x00dev, data, len);
422
423 /*
424 * Wait for device to stabilize.
425 */
426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
428 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429 break;
430 msleep(1);
431 }
432
433 if (i == REGISTER_BUSY_COUNT) {
434 ERROR(rt2x00dev, "PBF system register not ready.\n");
435 return -EBUSY;
436 }
437
438 /*
439 * Initialize firmware.
440 */
441 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
443 msleep(1);
444
445 return 0;
446}
447EXPORT_SYMBOL_GPL(rt2800_load_firmware);
448
0c5879bc
ID		 449void rt2800_write_tx_data(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
59679b91 451{
0c5879bc 452 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 453 u32 word;
454
455 /*
456 * Initialize TX Info descriptor
457 */
458 rt2x00_desc_read(txwi, 0, &word);
459 rt2x00_set_field32(&word, TXWI_W0_FRAG,
460 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 461 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 463 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464 rt2x00_set_field32(&word, TXWI_W0_TS,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word);
478
479 rt2x00_desc_read(txwi, 1, &word);
480 rt2x00_set_field32(&word, TXWI_W1_ACK,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff);
488 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
489 txdesc->length);
2b23cdaa 490 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 491 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 492 rt2x00_desc_write(txwi, 1, word);
493
494 /*
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
500 */
501 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
503}
0c5879bc 504EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 505
ff6133be 506static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 507{
74861922
ID		 508 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
511 u16 eeprom;
512 u8 offset0;
513 u8 offset1;
514 u8 offset2;
515
e5ef5bad 516 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 517 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
522 } else {
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
528 }
529
530 /*
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
534 */
535 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
538
539 /*
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
544 */
545 rssi0 = max(rssi0, rssi1);
546 return max(rssi0, rssi2);
547}
548
549void rt2800_process_rxwi(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc)
551{
552 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 553 u32 word;
554
555 rt2x00_desc_read(rxwi, 0, &word);
556
557 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
559
560 rt2x00_desc_read(rxwi, 1, &word);
561
562 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563 rxdesc->flags |= RX_FLAG_SHORT_GI;
564
565 if (rt2x00_get_field32(word, RXWI_W1_BW))
566 rxdesc->flags |= RX_FLAG_40MHZ;
567
568 /*
569 * Detect RX rate, always use MCS as signal type.
570 */
571 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
574
575 /*
576 * Mask of 0x8 bit to remove the short preamble flag.
577 */
578 if (rxdesc->rate_mode == RATE_MODE_CCK)
579 rxdesc->signal &= ~0x8;
580
581 rt2x00_desc_read(rxwi, 2, &word);
582
74861922
ID		 583 /*
584 * Convert descriptor AGC value to RSSI value.
585 */
586 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 587
588 /*
589 * Remove RXWI descriptor from start of buffer.
590 */
74861922 591 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 592}
593EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
594
3613884d
ID		 595static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
596{
597 __le32 *txwi;
598 u32 word;
599 int wcid, ack, pid;
600 int tx_wcid, tx_ack, tx_pid;
601
602 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
605
606 /*
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
609 * frame.
610 */
611 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
613 return false;
614 }
615
616 /*
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
619 */
620 txwi = rt2800_drv_get_txwi(entry);
621
622 rt2x00_desc_read(txwi, 1, &word);
623 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
625 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
626
627 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628 WARNING(entry->queue->rt2x00dev,
629 "TX status report missed for queue %d entry %d\n",
630 entry->queue->qid, entry->entry_idx);
631 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
632 return false;
633 }
634
635 return true;
636}
637
14433331
HS		 638void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
639{
640 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 642 struct txdone_entry_desc txdesc;
643 u32 word;
644 u16 mcs, real_mcs;
b34793ee 645 int aggr, ampdu;
14433331
HS		 646 __le32 *txwi;
647
648 /*
649 * Obtain the status about this packet.
650 */
651 txdesc.flags = 0;
652 txwi = rt2800_drv_get_txwi(entry);
653 rt2x00_desc_read(txwi, 0, &word);
b34793ee 654
14433331 655 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 656 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
657
14433331 658 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 659 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
660
661 /*
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
666 *
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
672 *
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
675 * data.
676 */
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678 skbdesc->tx_rate_idx = real_mcs;
679 mcs = real_mcs;
680 }
14433331
HS		 681
682 /*
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
688 */
689 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
690 /*
691 * Transmission succeeded. The number of retries is
692 * mcs - real_mcs
693 */
694 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
696 } else {
697 /*
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
700 * frames sent).
701 */
702 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703 txdesc.retry = rt2x00dev->long_retry;
704 }
705
706 /*
707 * the frame was retried at least once
708 * -> hw used fallback rates
709 */
710 if (txdesc.retry)
711 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
712
713 rt2x00lib_txdone(entry, &txdesc);
714}
715EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
716
96481b20
ID		 717void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
718{
719 struct data_queue *queue;
720 struct queue_entry *entry;
96481b20 721 u32 reg;
3613884d 722 u8 pid;
96481b20
ID		 723 int i;
724
725 /*
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
729 *
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
733 */
efd2f271 734 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
96481b20
ID		 735 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737 break;
738
96481b20
ID		 739 /*
740 * Skip this entry when it contains an invalid
741 * queue identication number.
742 */
bc8a979e 743 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
3613884d 744 if (pid >= QID_RX)
96481b20
ID		 745 continue;
746
3613884d 747 queue = rt2x00queue_get_queue(rt2x00dev, pid);
96481b20
ID		 748 if (unlikely(!queue))
749 continue;
750
751 /*
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
754 */
755 entry = NULL;
756 while (!rt2x00queue_empty(queue)) {
757 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
3613884d 758 if (rt2800_txdone_entry_check(entry, reg))
96481b20 759 break;
96481b20
ID		 760 }
761
762 if (!entry || rt2x00queue_empty(queue))
763 break;
764
14433331 765 rt2800_txdone_entry(entry, reg);
96481b20
ID		 766 }
767}
768EXPORT_SYMBOL_GPL(rt2800_txdone);
769
f0194b2d
GW		 770void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
771{
772 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base;
739fd940 775 unsigned int padding_len;
d76dfc61 776 u32 orig_reg, reg;
f0194b2d
GW		 777
778 /*
779 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data.
781 */
782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 783 orig_reg = reg;
f0194b2d
GW		 784 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
785 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
786
787 /*
788 * Add space for the TXWI in front of the skb.
789 */
790 skb_push(entry->skb, TXWI_DESC_SIZE);
791 memset(entry->skb, 0, TXWI_DESC_SIZE);
792
793 /*
794 * Register descriptor details in skb frame descriptor.
795 */
796 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
797 skbdesc->desc = entry->skb->data;
798 skbdesc->desc_len = TXWI_DESC_SIZE;
799
800 /*
801 * Add the TXWI for the beacon to the skb.
802 */
0c5879bc 803 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 804
805 /*
806 * Dump beacon to userspace through debugfs.
807 */
808 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
809
810 /*
739fd940 811 * Write entire beacon with TXWI and padding to register.
f0194b2d 812 */
739fd940 813 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 814 if (padding_len && skb_pad(entry->skb, padding_len)) {
815 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
816 /* skb freed by skb_pad() on failure */
817 entry->skb = NULL;
818 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
819 return;
820 }
821
f0194b2d 822 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 823 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
824 entry->skb->len + padding_len);
f0194b2d
GW		 825
826 /*
827 * Enable beaconing again.
828 */
f0194b2d
GW		 829 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
830 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
831
832 /*
833 * Clean up beacon skb.
834 */
835 dev_kfree_skb_any(entry->skb);
836 entry->skb = NULL;
837}
50e888ea 838EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 839
69cf36a4
HS		 840static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
841 unsigned int beacon_base)
fdb87251
HS		 842{
843 int i;
844
845 /*
846 * For the Beacon base registers we only need to clear
847 * the whole TXWI which (when set to 0) will invalidate
848 * the entire beacon.
849 */
850 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
851 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
852}
853
69cf36a4
HS		 854void rt2800_clear_beacon(struct queue_entry *entry)
855{
856 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
857 u32 reg;
858
859 /*
860 * Disable beaconing while we are reloading the beacon data,
861 * otherwise we might be sending out invalid data.
862 */
863 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
864 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
865 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
866
867 /*
868 * Clear beacon.
869 */
870 rt2800_clear_beacon_register(rt2x00dev,
871 HW_BEACON_OFFSET(entry->entry_idx));
872
873 /*
874 * Enabled beaconing again.
875 */
876 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
877 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
878}
879EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
880
f4450616
BZ		 881#ifdef CONFIG_RT2X00_LIB_DEBUGFS
882const struct rt2x00debug rt2800_rt2x00debug = {
883 .owner = THIS_MODULE,
884 .csr = {
885 .read = rt2800_register_read,
886 .write = rt2800_register_write,
887 .flags = RT2X00DEBUGFS_OFFSET,
888 .word_base = CSR_REG_BASE,
889 .word_size = sizeof(u32),
890 .word_count = CSR_REG_SIZE / sizeof(u32),
891 },
892 .eeprom = {
893 .read = rt2x00_eeprom_read,
894 .write = rt2x00_eeprom_write,
895 .word_base = EEPROM_BASE,
896 .word_size = sizeof(u16),
897 .word_count = EEPROM_SIZE / sizeof(u16),
898 },
899 .bbp = {
900 .read = rt2800_bbp_read,
901 .write = rt2800_bbp_write,
902 .word_base = BBP_BASE,
903 .word_size = sizeof(u8),
904 .word_count = BBP_SIZE / sizeof(u8),
905 },
906 .rf = {
907 .read = rt2x00_rf_read,
908 .write = rt2800_rf_write,
909 .word_base = RF_BASE,
910 .word_size = sizeof(u32),
911 .word_count = RF_SIZE / sizeof(u32),
912 },
913};
914EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
915#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
916
917int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
918{
919 u32 reg;
920
921 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
922 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
923}
924EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
925
926#ifdef CONFIG_RT2X00_LIB_LEDS
927static void rt2800_brightness_set(struct led_classdev *led_cdev,
928 enum led_brightness brightness)
929{
930 struct rt2x00_led *led =
931 container_of(led_cdev, struct rt2x00_led, led_dev);
932 unsigned int enabled = brightness != LED_OFF;
933 unsigned int bg_mode =
934 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
935 unsigned int polarity =
936 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
937 EEPROM_FREQ_LED_POLARITY);
938 unsigned int ledmode =
939 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
940 EEPROM_FREQ_LED_MODE);
941
942 if (led->type == LED_TYPE_RADIO) {
943 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
944 enabled ? 0x20 : 0);
945 } else if (led->type == LED_TYPE_ASSOC) {
946 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
947 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
948 } else if (led->type == LED_TYPE_QUALITY) {
949 /*
950 * The brightness is divided into 6 levels (0 - 5),
951 * The specs tell us the following levels:
952 * 0, 1 ,3, 7, 15, 31
953 * to determine the level in a simple way we can simply
954 * work with bitshifting:
955 * (1 << level) - 1
956 */
957 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
958 (1 << brightness / (LED_FULL / 6)) - 1,
959 polarity);
960 }
961}
962
963static int rt2800_blink_set(struct led_classdev *led_cdev,
964 unsigned long *delay_on, unsigned long *delay_off)
965{
966 struct rt2x00_led *led =
967 container_of(led_cdev, struct rt2x00_led, led_dev);
968 u32 reg;
969
970 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
971 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
972 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 973 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
974
975 return 0;
976}
977
b3579d6a 978static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 979 struct rt2x00_led *led, enum led_type type)
980{
981 led->rt2x00dev = rt2x00dev;
982 led->type = type;
983 led->led_dev.brightness_set = rt2800_brightness_set;
984 led->led_dev.blink_set = rt2800_blink_set;
985 led->flags = LED_INITIALIZED;
986}
f4450616
BZ		 987#endif /* CONFIG_RT2X00_LIB_LEDS */
988
989/*
990 * Configuration handlers.
991 */
992static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
993 struct rt2x00lib_crypto *crypto,
994 struct ieee80211_key_conf *key)
995{
996 struct mac_wcid_entry wcid_entry;
997 struct mac_iveiv_entry iveiv_entry;
998 u32 offset;
999 u32 reg;
1000
1001 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1002
e4a0ab34
ID		 1003 if (crypto->cmd == SET_KEY) {
1004 rt2800_register_read(rt2x00dev, offset, &reg);
1005 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1006 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1007 /*
1008 * Both the cipher as the BSS Idx numbers are split in a main
1009 * value of 3 bits, and a extended field for adding one additional
1010 * bit to the value.
1011 */
1012 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1013 (crypto->cipher & 0x7));
1014 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1015 (crypto->cipher & 0x8) >> 3);
1016 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1017 (crypto->bssidx & 0x7));
1018 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1019 (crypto->bssidx & 0x8) >> 3);
1020 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1021 rt2800_register_write(rt2x00dev, offset, reg);
1022 } else {
1023 rt2800_register_write(rt2x00dev, offset, 0);
1024 }
f4450616
BZ		 1025
1026 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1027
1028 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1029 if ((crypto->cipher == CIPHER_TKIP) ||
1030 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1031 (crypto->cipher == CIPHER_AES))
1032 iveiv_entry.iv[3] |= 0x20;
1033 iveiv_entry.iv[3] |= key->keyidx << 6;
1034 rt2800_register_multiwrite(rt2x00dev, offset,
1035 &iveiv_entry, sizeof(iveiv_entry));
1036
1037 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1038
1039 memset(&wcid_entry, 0, sizeof(wcid_entry));
1040 if (crypto->cmd == SET_KEY)
10026f77 1041 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
f4450616
BZ		 1042 rt2800_register_multiwrite(rt2x00dev, offset,
1043 &wcid_entry, sizeof(wcid_entry));
1044}
1045
1046int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1047 struct rt2x00lib_crypto *crypto,
1048 struct ieee80211_key_conf *key)
1049{
1050 struct hw_key_entry key_entry;
1051 struct rt2x00_field32 field;
1052 u32 offset;
1053 u32 reg;
1054
1055 if (crypto->cmd == SET_KEY) {
1056 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1057
1058 memcpy(key_entry.key, crypto->key,
1059 sizeof(key_entry.key));
1060 memcpy(key_entry.tx_mic, crypto->tx_mic,
1061 sizeof(key_entry.tx_mic));
1062 memcpy(key_entry.rx_mic, crypto->rx_mic,
1063 sizeof(key_entry.rx_mic));
1064
1065 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1066 rt2800_register_multiwrite(rt2x00dev, offset,
1067 &key_entry, sizeof(key_entry));
1068 }
1069
1070 /*
1071 * The cipher types are stored over multiple registers
1072 * starting with SHARED_KEY_MODE_BASE each word will have
1073 * 32 bits and contains the cipher types for 2 bssidx each.
1074 * Using the correct defines correctly will cause overhead,
1075 * so just calculate the correct offset.
1076 */
1077 field.bit_offset = 4 * (key->hw_key_idx % 8);
1078 field.bit_mask = 0x7 << field.bit_offset;
1079
1080 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1081
1082 rt2800_register_read(rt2x00dev, offset, &reg);
1083 rt2x00_set_field32(&reg, field,
1084 (crypto->cmd == SET_KEY) * crypto->cipher);
1085 rt2800_register_write(rt2x00dev, offset, reg);
1086
1087 /*
1088 * Update WCID information
1089 */
1090 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1091
1092 return 0;
1093}
1094EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1095
1096int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1097 struct rt2x00lib_crypto *crypto,
1098 struct ieee80211_key_conf *key)
1099{
1100 struct hw_key_entry key_entry;
1101 u32 offset;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 /*
1105 * 1 pairwise key is possible per AID, this means that the AID
1106 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1107 * last possible shared key entry.
2a0cfeb8
HS		 1108 *
1109 * Since parts of the pairwise key table might be shared with
1110 * the beacon frame buffers 6 & 7 we should only write into the
1111 * first 222 entries.
f4450616 1112 */
2a0cfeb8 1113 if (crypto->aid > (222 - 32))
f4450616
BZ		 1114 return -ENOSPC;
1115
1116 key->hw_key_idx = 32 + crypto->aid;
1117
1118 memcpy(key_entry.key, crypto->key,
1119 sizeof(key_entry.key));
1120 memcpy(key_entry.tx_mic, crypto->tx_mic,
1121 sizeof(key_entry.tx_mic));
1122 memcpy(key_entry.rx_mic, crypto->rx_mic,
1123 sizeof(key_entry.rx_mic));
1124
1125 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1126 rt2800_register_multiwrite(rt2x00dev, offset,
1127 &key_entry, sizeof(key_entry));
1128 }
1129
1130 /*
1131 * Update WCID information
1132 */
1133 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1134
1135 return 0;
1136}
1137EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1138
1139void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1140 const unsigned int filter_flags)
1141{
1142 u32 reg;
1143
1144 /*
1145 * Start configuration steps.
1146 * Note that the version error will always be dropped
1147 * and broadcast frames will always be accepted since
1148 * there is no filter for it at this time.
1149 */
1150 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1151 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1152 !(filter_flags & FIF_FCSFAIL));
1153 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1154 !(filter_flags & FIF_PLCPFAIL));
1155 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1156 !(filter_flags & FIF_PROMISC_IN_BSS));
1157 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1158 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1159 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1160 !(filter_flags & FIF_ALLMULTI));
1161 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1162 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1163 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1164 !(filter_flags & FIF_CONTROL));
1165 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1166 !(filter_flags & FIF_CONTROL));
1167 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1168 !(filter_flags & FIF_CONTROL));
1169 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1170 !(filter_flags & FIF_CONTROL));
1171 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1172 !(filter_flags & FIF_CONTROL));
1173 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1174 !(filter_flags & FIF_PSPOLL));
1175 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1176 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1177 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1178 !(filter_flags & FIF_CONTROL));
1179 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1180}
1181EXPORT_SYMBOL_GPL(rt2800_config_filter);
1182
1183void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1184 struct rt2x00intf_conf *conf, const unsigned int flags)
1185{
f4450616 1186 u32 reg;
fa8b4b22 1187 bool update_bssid = false;
f4450616
BZ		 1188
1189 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1190 /*
1191 * Enable synchronisation.
1192 */
1193 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1194 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616
BZ		 1195 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1196 }
1197
1198 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1199 if (flags & CONFIG_UPDATE_TYPE &&
1200 conf->sync == TSF_SYNC_AP_NONE) {
1201 /*
1202 * The BSSID register has to be set to our own mac
1203 * address in AP mode.
1204 */
1205 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1206 update_bssid = true;
1207 }
1208
c600c826
ID		 1209 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1210 reg = le32_to_cpu(conf->mac[1]);
1211 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1212 conf->mac[1] = cpu_to_le32(reg);
1213 }
f4450616
BZ		 1214
1215 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1216 conf->mac, sizeof(conf->mac));
1217 }
1218
fa8b4b22 1219 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1220 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1221 reg = le32_to_cpu(conf->bssid[1]);
1222 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1223 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1224 conf->bssid[1] = cpu_to_le32(reg);
1225 }
f4450616
BZ		 1226
1227 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1228 conf->bssid, sizeof(conf->bssid));
1229 }
1230}
1231EXPORT_SYMBOL_GPL(rt2800_config_intf);
1232
87c1915d
HS		 1233static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1234 struct rt2x00lib_erp *erp)
1235{
1236 bool any_sta_nongf = !!(erp->ht_opmode &
1237 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1238 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1239 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1240 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1241 u32 reg;
1242
1243 /* default protection rate for HT20: OFDM 24M */
1244 mm20_rate = gf20_rate = 0x4004;
1245
1246 /* default protection rate for HT40: duplicate OFDM 24M */
1247 mm40_rate = gf40_rate = 0x4084;
1248
1249 switch (protection) {
1250 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1251 /*
1252 * All STAs in this BSS are HT20/40 but there might be
1253 * STAs not supporting greenfield mode.
1254 * => Disable protection for HT transmissions.
1255 */
1256 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1257
1258 break;
1259 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1260 /*
1261 * All STAs in this BSS are HT20 or HT20/40 but there
1262 * might be STAs not supporting greenfield mode.
1263 * => Protect all HT40 transmissions.
1264 */
1265 mm20_mode = gf20_mode = 0;
1266 mm40_mode = gf40_mode = 2;
1267
1268 break;
1269 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1270 /*
1271 * Nonmember protection:
1272 * According to 802.11n we _should_ protect all
1273 * HT transmissions (but we don't have to).
1274 *
1275 * But if cts_protection is enabled we _shall_ protect
1276 * all HT transmissions using a CCK rate.
1277 *
1278 * And if any station is non GF we _shall_ protect
1279 * GF transmissions.
1280 *
1281 * We decide to protect everything
1282 * -> fall through to mixed mode.
1283 */
1284 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1285 /*
1286 * Legacy STAs are present
1287 * => Protect all HT transmissions.
1288 */
1289 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1290
1291 /*
1292 * If erp protection is needed we have to protect HT
1293 * transmissions with CCK 11M long preamble.
1294 */
1295 if (erp->cts_protection) {
1296 /* don't duplicate RTS/CTS in CCK mode */
1297 mm20_rate = mm40_rate = 0x0003;
1298 gf20_rate = gf40_rate = 0x0003;
1299 }
1300 break;
1301 };
1302
1303 /* check for STAs not supporting greenfield mode */
1304 if (any_sta_nongf)
1305 gf20_mode = gf40_mode = 2;
1306
1307 /* Update HT protection config */
1308 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1309 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1310 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1311 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1312
1313 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1314 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1315 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1316 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1317
1318 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1319 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1320 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1321 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1322
1323 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1324 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1325 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1326 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1327}
1328
02044643
HS		 1329void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1330 u32 changed)
f4450616
BZ		 1331{
1332 u32 reg;
1333
02044643
HS		 1334 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1335 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1336 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1337 !!erp->short_preamble);
1338 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1339 !!erp->short_preamble);
1340 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1341 }
f4450616 1342
02044643
HS		 1343 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1344 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1345 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1346 erp->cts_protection ? 2 : 0);
1347 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1348 }
f4450616 1349
02044643
HS		 1350 if (changed & BSS_CHANGED_BASIC_RATES) {
1351 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1352 erp->basic_rates);
1353 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1354 }
f4450616 1355
02044643
HS		 1356 if (changed & BSS_CHANGED_ERP_SLOT) {
1357 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1358 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1359 erp->slot_time);
1360 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1361
02044643
HS		 1362 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1363 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1364 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1365 }
f4450616 1366
02044643
HS		 1367 if (changed & BSS_CHANGED_BEACON_INT) {
1368 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1369 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1370 erp->beacon_int * 16);
1371 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1372 }
87c1915d
HS		 1373
1374 if (changed & BSS_CHANGED_HT)
1375 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1376}
1377EXPORT_SYMBOL_GPL(rt2800_config_erp);
1378
d96aa640
RJH		 1379static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1380 enum antenna ant)
1381{
1382 u32 reg;
1383 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1384 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1385
1386 if (rt2x00_is_pci(rt2x00dev)) {
1387 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1388 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1389 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1390 } else if (rt2x00_is_usb(rt2x00dev))
1391 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1392 eesk_pin, 0);
1393
1394 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1395 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD, 0);
1396 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1397 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1398}
1399
f4450616
BZ		 1400void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1401{
1402 u8 r1;
1403 u8 r3;
d96aa640 1404 u16 eeprom;
f4450616
BZ		 1405
1406 rt2800_bbp_read(rt2x00dev, 1, &r1);
1407 rt2800_bbp_read(rt2x00dev, 3, &r3);
1408
1409 /*
1410 * Configure the TX antenna.
1411 */
d96aa640 1412 switch (ant->tx_chain_num) {
f4450616
BZ		 1413 case 1:
1414 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1415 break;
1416 case 2:
1417 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1418 break;
1419 case 3:
e22557f2 1420 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1421 break;
1422 }
1423
1424 /*
1425 * Configure the RX antenna.
1426 */
d96aa640 1427 switch (ant->rx_chain_num) {
f4450616 1428 case 1:
d96aa640
RJH		 1429 if (rt2x00_rt(rt2x00dev, RT3070) ||
1430 rt2x00_rt(rt2x00dev, RT3090) ||
1431 rt2x00_rt(rt2x00dev, RT3390)) {
1432 rt2x00_eeprom_read(rt2x00dev,
1433 EEPROM_NIC_CONF1, &eeprom);
1434 if (rt2x00_get_field16(eeprom,
1435 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1436 rt2800_set_ant_diversity(rt2x00dev,
1437 rt2x00dev->default_ant.rx);
1438 }
f4450616
BZ		 1439 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1440 break;
1441 case 2:
1442 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1443 break;
1444 case 3:
1445 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1446 break;
1447 }
1448
1449 rt2800_bbp_write(rt2x00dev, 3, r3);
1450 rt2800_bbp_write(rt2x00dev, 1, r1);
1451}
1452EXPORT_SYMBOL_GPL(rt2800_config_ant);
1453
1454static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1455 struct rt2x00lib_conf *libconf)
1456{
1457 u16 eeprom;
1458 short lna_gain;
1459
1460 if (libconf->rf.channel <= 14) {
1461 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1462 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1463 } else if (libconf->rf.channel <= 64) {
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1465 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1466 } else if (libconf->rf.channel <= 128) {
1467 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1468 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1469 } else {
1470 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1471 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1472 }
1473
1474 rt2x00dev->lna_gain = lna_gain;
1475}
1476
06855ef4
GW		 1477static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1478 struct ieee80211_conf *conf,
1479 struct rf_channel *rf,
1480 struct channel_info *info)
f4450616
BZ		 1481{
1482 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1483
d96aa640 1484 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1485 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1486
d96aa640 1487 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1488 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1489 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1490 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1491 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1492
1493 if (rf->channel > 14) {
1494 /*
1495 * When TX power is below 0, we should increase it by 7 to
1496 * make it a positive value (Minumum value is -7).
1497 * However this means that values between 0 and 7 have
1498 * double meaning, and we should set a 7DBm boost flag.
1499 */
1500 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1501 (info->default_power1 >= 0));
f4450616 1502
8d1331b3
ID		 1503 if (info->default_power1 < 0)
1504 info->default_power1 += 7;
f4450616 1505
8d1331b3 1506 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1507
1508 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1509 (info->default_power2 >= 0));
f4450616 1510
8d1331b3
ID		 1511 if (info->default_power2 < 0)
1512 info->default_power2 += 7;
f4450616 1513
8d1331b3 1514 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1515 } else {
8d1331b3
ID		 1516 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1517 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1518 }
1519
1520 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1521
1522 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1523 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1524 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1525 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1526
1527 udelay(200);
1528
1529 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1530 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1531 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1532 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1533
1534 udelay(200);
1535
1536 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1537 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1538 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1539 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1540}
1541
06855ef4
GW		 1542static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1543 struct ieee80211_conf *conf,
1544 struct rf_channel *rf,
1545 struct channel_info *info)
f4450616
BZ		 1546{
1547 u8 rfcsr;
1548
1549 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1550 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1551
1552 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1553 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1554 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1555
1556 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1557 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1558 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1559
5a673964 1560 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1561 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964
HS		 1562 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1563
f4450616
BZ		 1564 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1565 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1566 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1567
1568 rt2800_rfcsr_write(rt2x00dev, 24,
1569 rt2x00dev->calibration[conf_is_ht40(conf)]);
1570
71976907 1571 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1572 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1573 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1574}
1575
1576static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1577 struct ieee80211_conf *conf,
1578 struct rf_channel *rf,
1579 struct channel_info *info)
1580{
1581 u32 reg;
1582 unsigned int tx_pin;
1583 u8 bbp;
1584
46323e11 1585 if (rf->channel <= 14) {
8d1331b3
ID		 1586 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1587 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 1588 } else {
8d1331b3
ID		 1589 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1590 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 1591 }
1592
06855ef4
GW		 1593 if (rt2x00_rf(rt2x00dev, RF2020) ||
1594 rt2x00_rf(rt2x00dev, RF3020) ||
1595 rt2x00_rf(rt2x00dev, RF3021) ||
46323e11 1596 rt2x00_rf(rt2x00dev, RF3022) ||
f93bc9b3
GW		 1597 rt2x00_rf(rt2x00dev, RF3052) ||
1598 rt2x00_rf(rt2x00dev, RF3320))
06855ef4 1599 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1600 else
06855ef4 1601 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1602
1603 /*
1604 * Change BBP settings
1605 */
1606 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1607 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1608 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1609 rt2800_bbp_write(rt2x00dev, 86, 0);
1610
1611 if (rf->channel <= 14) {
1612 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1613 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1614 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1615 } else {
1616 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1617 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1618 }
1619 } else {
1620 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1621
1622 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1623 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1624 else
1625 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1626 }
1627
1628 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1629 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1630 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1631 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1632 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1633
1634 tx_pin = 0;
1635
1636 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1637 if (rt2x00dev->default_ant.tx_chain_num == 2) {
f4450616
BZ		 1638 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1639 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1640 }
1641
1642 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 1643 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 1644 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1645 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1646 }
1647
1648 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1649 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1650 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1651 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1652 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1653 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1654
1655 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1656
1657 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1658 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1659 rt2800_bbp_write(rt2x00dev, 4, bbp);
1660
1661 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1662 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1663 rt2800_bbp_write(rt2x00dev, 3, bbp);
1664
8d0c9b65 1665 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1666 if (conf_is_ht40(conf)) {
1667 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1668 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1669 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1670 } else {
1671 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1672 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1673 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1674 }
1675 }
1676
1677 msleep(1);
977206d7
HS		 1678
1679 /*
1680 * Clear channel statistic counters
1681 */
1682 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1683 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1684 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 1685}
1686
1687static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1688 const int max_txpower)
f4450616 1689{
5e846004
HS		 1690 u8 txpower;
1691 u8 max_value = (u8)max_txpower;
1692 u16 eeprom;
1693 int i;
f4450616 1694 u32 reg;
f4450616 1695 u8 r1;
5e846004 1696 u32 offset;
f4450616 1697
5e846004
HS		 1698 /*
1699 * set to normal tx power mode: +/- 0dBm
1700 */
f4450616 1701 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1702 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1703 rt2800_bbp_write(rt2x00dev, 1, r1);
1704
5e846004
HS		 1705 /*
1706 * The eeprom contains the tx power values for each rate. These
1707 * values map to 100% tx power. Each 16bit word contains four tx
1708 * power values and the order is the same as used in the TX_PWR_CFG
1709 * registers.
1710 */
1711 offset = TX_PWR_CFG_0;
1712
1713 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1714 /* just to be safe */
1715 if (offset > TX_PWR_CFG_4)
1716 break;
1717
1718 rt2800_register_read(rt2x00dev, offset, &reg);
1719
1720 /* read the next four txpower values */
1721 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1722 &eeprom);
1723
1724 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1725 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1726 * TX_PWR_CFG_4: unknown */
1727 txpower = rt2x00_get_field16(eeprom,
1728 EEPROM_TXPOWER_BYRATE_RATE0);
1729 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1730 min(txpower, max_value));
1731
1732 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1733 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1734 * TX_PWR_CFG_4: unknown */
1735 txpower = rt2x00_get_field16(eeprom,
1736 EEPROM_TXPOWER_BYRATE_RATE1);
1737 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1738 min(txpower, max_value));
1739
1740 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1741 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1742 * TX_PWR_CFG_4: unknown */
1743 txpower = rt2x00_get_field16(eeprom,
1744 EEPROM_TXPOWER_BYRATE_RATE2);
1745 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1746 min(txpower, max_value));
1747
1748 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1749 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1750 * TX_PWR_CFG_4: unknown */
1751 txpower = rt2x00_get_field16(eeprom,
1752 EEPROM_TXPOWER_BYRATE_RATE3);
1753 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1754 min(txpower, max_value));
1755
1756 /* read the next four txpower values */
1757 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1758 &eeprom);
1759
1760 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1761 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1762 * TX_PWR_CFG_4: unknown */
1763 txpower = rt2x00_get_field16(eeprom,
1764 EEPROM_TXPOWER_BYRATE_RATE0);
1765 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1766 min(txpower, max_value));
1767
1768 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1769 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1770 * TX_PWR_CFG_4: unknown */
1771 txpower = rt2x00_get_field16(eeprom,
1772 EEPROM_TXPOWER_BYRATE_RATE1);
1773 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1774 min(txpower, max_value));
1775
1776 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1777 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1778 * TX_PWR_CFG_4: unknown */
1779 txpower = rt2x00_get_field16(eeprom,
1780 EEPROM_TXPOWER_BYRATE_RATE2);
1781 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1782 min(txpower, max_value));
1783
1784 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1785 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1786 * TX_PWR_CFG_4: unknown */
1787 txpower = rt2x00_get_field16(eeprom,
1788 EEPROM_TXPOWER_BYRATE_RATE3);
1789 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1790 min(txpower, max_value));
1791
1792 rt2800_register_write(rt2x00dev, offset, reg);
1793
1794 /* next TX_PWR_CFG register */
1795 offset += 4;
1796 }
f4450616
BZ		 1797}
1798
1799static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1800 struct rt2x00lib_conf *libconf)
1801{
1802 u32 reg;
1803
1804 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1805 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1806 libconf->conf->short_frame_max_tx_count);
1807 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1808 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1809 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1810}
1811
1812static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1813 struct rt2x00lib_conf *libconf)
1814{
1815 enum dev_state state =
1816 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1817 STATE_SLEEP : STATE_AWAKE;
1818 u32 reg;
1819
1820 if (state == STATE_SLEEP) {
1821 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1822
1823 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1824 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1825 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1826 libconf->conf->listen_interval - 1);
1827 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1828 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1829
1830 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1831 } else {
f4450616
BZ		 1832 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1833 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1834 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1835 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1836 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1837
1838 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1839 }
1840}
1841
1842void rt2800_config(struct rt2x00_dev *rt2x00dev,
1843 struct rt2x00lib_conf *libconf,
1844 const unsigned int flags)
1845{
1846 /* Always recalculate LNA gain before changing configuration */
1847 rt2800_config_lna_gain(rt2x00dev, libconf);
1848
1849 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1850 rt2800_config_channel(rt2x00dev, libconf->conf,
1851 &libconf->rf, &libconf->channel);
1852 if (flags & IEEE80211_CONF_CHANGE_POWER)
1853 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1854 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1855 rt2800_config_retry_limit(rt2x00dev, libconf);
1856 if (flags & IEEE80211_CONF_CHANGE_PS)
1857 rt2800_config_ps(rt2x00dev, libconf);
1858}
1859EXPORT_SYMBOL_GPL(rt2800_config);
1860
1861/*
1862 * Link tuning
1863 */
1864void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1865{
1866 u32 reg;
1867
1868 /*
1869 * Update FCS error count from register.
1870 */
1871 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1872 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1873}
1874EXPORT_SYMBOL_GPL(rt2800_link_stats);
1875
1876static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1877{
1878 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1879 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1880 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1881 rt2x00_rt(rt2x00dev, RT3090) ||
1882 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1883 return 0x1c + (2 * rt2x00dev->lna_gain);
1884 else
1885 return 0x2e + rt2x00dev->lna_gain;
1886 }
1887
1888 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1889 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1890 else
1891 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1892}
1893
1894static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1895 struct link_qual *qual, u8 vgc_level)
1896{
1897 if (qual->vgc_level != vgc_level) {
1898 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1899 qual->vgc_level = vgc_level;
1900 qual->vgc_level_reg = vgc_level;
1901 }
1902}
1903
1904void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1905{
1906 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1907}
1908EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1909
1910void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1911 const u32 count)
1912{
8d0c9b65 1913 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1914 return;
1915
1916 /*
1917 * When RSSI is better then -80 increase VGC level with 0x10
1918 */
1919 rt2800_set_vgc(rt2x00dev, qual,
1920 rt2800_get_default_vgc(rt2x00dev) +
1921 ((qual->rssi > -80) * 0x10));
1922}
1923EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1924
1925/*
1926 * Initialization functions.
1927 */
b9a07ae9 1928static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 1929{
1930 u32 reg;
d5385bfc 1931 u16 eeprom;
fcf51541 1932 unsigned int i;
e3a896b9 1933 int ret;
fcf51541 1934
a9dce149
GW		 1935 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1936 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1937 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1938 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1939 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1940 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1941 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1942
e3a896b9
GW		 1943 ret = rt2800_drv_init_registers(rt2x00dev);
1944 if (ret)
1945 return ret;
fcf51541
BZ		 1946
1947 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1948 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1949 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1950 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1951 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1952 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1953
1954 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1955 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1956 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1957 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1958 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1959 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1960
1961 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1962 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1963
1964 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1965
1966 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1967 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1968 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1969 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1970 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1971 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1972 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1973 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1974
a9dce149
GW		 1975 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1976
1977 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1978 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1979 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1980 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1981
64522957 1982 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1983 rt2x00_rt(rt2x00dev, RT3090) ||
1984 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1985 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1986 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1987 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1988 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1989 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 1990 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1991 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 1992 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1993 0x0000002c);
1994 else
1995 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1996 0x0000000f);
1997 } else {
1998 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1999 }
d5385bfc 2000 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2001 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2002
2003 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2004 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2005 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2006 } else {
2007 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2008 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2009 }
c295a81d
HS		 2010 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2011 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2012 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2013 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 2014 } else {
2015 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2016 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2017 }
2018
2019 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2020 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2021 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2022 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2023 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2024 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2025 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2026 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2027 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2028 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2029
2030 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2031 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2032 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2033 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2034 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2035
2036 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2037 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2038 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2039 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2040 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2041 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2042 else
2043 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2044 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2045 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2046 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2047
a9dce149
GW		 2048 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2049 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2050 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2051 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2052 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2053 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2054 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2055 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2056 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2057
fcf51541
BZ		 2058 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2059
a9dce149
GW		 2060 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2061 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2062 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2063 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2064 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2065 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2066 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2067 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2068
fcf51541
BZ		 2069 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2070 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2071 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2072 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2073 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2074 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2075 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2076 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2077 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2078
2079 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2080 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2081 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2082 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2083 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2084 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2085 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2086 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2087 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2088 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2089 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2090 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2091
2092 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2093 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 2094 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2095 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2096 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2097 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2098 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2099 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2100 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2101 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2102 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2103 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2104
2105 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2106 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2107 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2108 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2109 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2110 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2111 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2112 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2113 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2114 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2115 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2116 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2117
2118 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2119 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2120 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
fcf51541
BZ		 2121 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2122 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2123 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2124 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2125 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2126 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2127 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2128 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2129 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2130
2131 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2132 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2133 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2134 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2135 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2136 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2137 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2138 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2139 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2140 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2141 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2142 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2143
2144 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2145 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2146 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2147 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2148 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2149 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2150 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2151 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2152 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2153 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2154 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2155 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2156
cea90e55 2157 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2158 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2159
2160 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2161 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2162 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2163 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2164 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2165 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2166 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2167 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2168 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2169 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2170 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2171 }
2172
961621ab
HS		 2173 /*
2174 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2175 * although it is reserved.
2176 */
2177 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2178 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2179 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2180 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2181 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2182 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2183 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2184 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2185 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2186 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2187 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2188 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2189
fcf51541
BZ		 2190 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2191
2192 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2193 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2194 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2195 IEEE80211_MAX_RTS_THRESHOLD);
2196 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2197 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2198
2199 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2200
a21c2ab4
HS		 2201 /*
2202 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2203 * time should be set to 16. However, the original Ralink driver uses
2204 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2205 * connection problems with 11g + CTS protection. Hence, use the same
2206 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2207 */
a9dce149 2208 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 2209 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2210 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 2211 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2212 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2213 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2214 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2215
fcf51541
BZ		 2216 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2217
2218 /*
2219 * ASIC will keep garbage value after boot, clear encryption keys.
2220 */
2221 for (i = 0; i < 4; i++)
2222 rt2800_register_write(rt2x00dev,
2223 SHARED_KEY_MODE_ENTRY(i), 0);
2224
2225 for (i = 0; i < 256; i++) {
f4e16e41 2226 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
fcf51541
BZ		 2227 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2228 wcid, sizeof(wcid));
2229
2230 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2231 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2232 }
2233
2234 /*
2235 * Clear all beacons
fcf51541 2236 */
69cf36a4
HS		 2237 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2238 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2239 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2240 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2241 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2242 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2243 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2244 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 2245
cea90e55 2246 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 2247 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2248 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2249 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 2250 } else if (rt2x00_is_pcie(rt2x00dev)) {
2251 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2252 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2253 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 2254 }
2255
2256 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2257 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2258 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2259 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2260 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2261 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2262 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2263 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2264 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2265 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2266
2267 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2268 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2269 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2270 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2271 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2272 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2273 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2274 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2275 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2276 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2277
2278 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2279 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2280 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2281 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2282 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2283 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2284 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2285 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2286 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2287 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2288
2289 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2290 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2291 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2292 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2293 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2294 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2295
47ee3eb1
HS		 2296 /*
2297 * Do not force the BA window size, we use the TXWI to set it
2298 */
2299 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2300 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2301 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2302 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2303
fcf51541
BZ		 2304 /*
2305 * We must clear the error counters.
2306 * These registers are cleared on read,
2307 * so we may pass a useless variable to store the value.
2308 */
2309 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2310 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2311 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2312 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2313 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2314 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2315
9f926fb5
HS		 2316 /*
2317 * Setup leadtime for pre tbtt interrupt to 6ms
2318 */
2319 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2320 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2321 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2322
977206d7
HS		 2323 /*
2324 * Set up channel statistics timer
2325 */
2326 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2327 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2328 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2329 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2330 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2331 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2332 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2333
fcf51541
BZ		 2334 return 0;
2335}
fcf51541
BZ		 2336
2337static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2338{
2339 unsigned int i;
2340 u32 reg;
2341
2342 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2343 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2344 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2345 return 0;
2346
2347 udelay(REGISTER_BUSY_DELAY);
2348 }
2349
2350 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2351 return -EACCES;
2352}
2353
2354static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2355{
2356 unsigned int i;
2357 u8 value;
2358
2359 /*
2360 * BBP was enabled after firmware was loaded,
2361 * but we need to reactivate it now.
2362 */
2363 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2364 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2365 msleep(1);
2366
2367 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2368 rt2800_bbp_read(rt2x00dev, 0, &value);
2369 if ((value != 0xff) && (value != 0x00))
2370 return 0;
2371 udelay(REGISTER_BUSY_DELAY);
2372 }
2373
2374 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2375 return -EACCES;
2376}
2377
b9a07ae9 2378static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2379{
2380 unsigned int i;
2381 u16 eeprom;
2382 u8 reg_id;
2383 u8 value;
2384
2385 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2386 rt2800_wait_bbp_ready(rt2x00dev)))
2387 return -EACCES;
2388
baff8006
HS		 2389 if (rt2800_is_305x_soc(rt2x00dev))
2390 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2391
fcf51541
BZ		 2392 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2393 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 2394
2395 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2396 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2397 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2398 } else {
2399 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2400 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2401 }
2402
fcf51541 2403 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 2404
d5385bfc 2405 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2406 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2407 rt2x00_rt(rt2x00dev, RT3090) ||
2408 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 2409 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2410 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2411 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 2412 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2413 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2414 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 2415 } else {
2416 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2417 }
2418
fcf51541
BZ		 2419 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2420 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 2421
5ed8f458 2422 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 2423 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2424 else
2425 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2426
fcf51541
BZ		 2427 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2428 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2429 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2430
d5385bfc 2431 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2432 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2433 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2434 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2435 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2436 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2437 else
2438 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2439
baff8006
HS		 2440 if (rt2800_is_305x_soc(rt2x00dev))
2441 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2442 else
2443 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2444 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2445
64522957 2446 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2447 rt2x00_rt(rt2x00dev, RT3090) ||
2448 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2449 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2450
38c8a566
RJH		 2451 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2452 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 2453 value |= 0x20;
38c8a566 2454 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 2455 value &= ~0x02;
fcf51541 2456
d5385bfc 2457 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2458 }
2459
fcf51541
BZ		 2460
2461 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2462 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2463
2464 if (eeprom != 0xffff && eeprom != 0x0000) {
2465 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2466 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2467 rt2800_bbp_write(rt2x00dev, reg_id, value);
2468 }
2469 }
2470
2471 return 0;
2472}
fcf51541
BZ		 2473
2474static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2475 bool bw40, u8 rfcsr24, u8 filter_target)
2476{
2477 unsigned int i;
2478 u8 bbp;
2479 u8 rfcsr;
2480 u8 passband;
2481 u8 stopband;
2482 u8 overtuned = 0;
2483
2484 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2485
2486 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2487 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2488 rt2800_bbp_write(rt2x00dev, 4, bbp);
2489
80d184e6
RJH		 2490 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2491 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2492 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2493
fcf51541
BZ		 2494 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2495 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2496 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2497
2498 /*
2499 * Set power & frequency of passband test tone
2500 */
2501 rt2800_bbp_write(rt2x00dev, 24, 0);
2502
2503 for (i = 0; i < 100; i++) {
2504 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2505 msleep(1);
2506
2507 rt2800_bbp_read(rt2x00dev, 55, &passband);
2508 if (passband)
2509 break;
2510 }
2511
2512 /*
2513 * Set power & frequency of stopband test tone
2514 */
2515 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2516
2517 for (i = 0; i < 100; i++) {
2518 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2519 msleep(1);
2520
2521 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2522
2523 if ((passband - stopband) <= filter_target) {
2524 rfcsr24++;
2525 overtuned += ((passband - stopband) == filter_target);
2526 } else
2527 break;
2528
2529 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2530 }
2531
2532 rfcsr24 -= !!overtuned;
2533
2534 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2535 return rfcsr24;
2536}
2537
b9a07ae9 2538static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2539{
2540 u8 rfcsr;
2541 u8 bbp;
8cdd15e0
GW		 2542 u32 reg;
2543 u16 eeprom;
fcf51541 2544
d5385bfc 2545 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2546 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2547 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2548 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2549 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2550 return 0;
2551
fcf51541
BZ		 2552 /*
2553 * Init RF calibration.
2554 */
2555 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2556 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2557 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2558 msleep(1);
2559 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2560 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2561
d5385bfc 2562 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2563 rt2x00_rt(rt2x00dev, RT3071) ||
2564 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2565 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2566 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2567 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 2568 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 2569 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2570 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2571 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2572 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2573 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2574 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2575 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2576 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2577 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2578 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2579 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2580 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2581 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2582 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2583 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2584 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2585 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2586 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2587 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2588 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2589 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2590 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2591 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2592 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2593 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2594 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2595 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2596 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2597 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2598 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2599 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2600 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2601 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2602 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2603 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2604 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2605 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2606 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2607 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2608 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2609 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2610 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2611 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2612 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2613 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2614 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2615 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2616 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2617 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2618 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2619 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2620 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2621 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2622 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2623 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2624 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2625 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2626 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2627 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2628 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2629 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2630 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2631 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2632 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2633 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2634 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2635 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2636 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2637 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2638 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2639 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2640 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2641 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2642 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2643 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2644 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2645 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2646 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2647 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2648 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2649 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2650 return 0;
8cdd15e0
GW		 2651 }
2652
2653 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2654 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2655 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2656 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2657 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2658 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2659 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 2660 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2661
d5385bfc
GW		 2662 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2663 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2664 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2665
d5385bfc
GW		 2666 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2667 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2668 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2669 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 2670 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2671 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2672 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2673 else
2674 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2675 }
2676 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 2677
2678 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2679 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2680 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 2681 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2682 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2683 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2684 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2685 }
2686
2687 /*
2688 * Set RX Filter calibration for 20MHz and 40MHz
2689 */
8cdd15e0
GW		 2690 if (rt2x00_rt(rt2x00dev, RT3070)) {
2691 rt2x00dev->calibration[0] =
2692 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2693 rt2x00dev->calibration[1] =
2694 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2695 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2696 rt2x00_rt(rt2x00dev, RT3090) ||
2697 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2698 rt2x00dev->calibration[0] =
2699 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2700 rt2x00dev->calibration[1] =
2701 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2702 }
fcf51541
BZ		 2703
2704 /*
2705 * Set back to initial state
2706 */
2707 rt2800_bbp_write(rt2x00dev, 24, 0);
2708
2709 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2710 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2711 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2712
2713 /*
2714 * set BBP back to BW20
2715 */
2716 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2717 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2718 rt2800_bbp_write(rt2x00dev, 4, bbp);
2719
d5385bfc 2720 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2721 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2722 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2723 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2724 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2725
2726 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2727 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2728 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2729
2730 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2731 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
80d184e6
RJH		 2732 if (rt2x00_rt(rt2x00dev, RT3070) ||
2733 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2734 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2735 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
80d184e6 2736 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2737 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2738 }
8cdd15e0
GW		 2739 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2740 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2741 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2742 rt2x00_get_field16(eeprom,
2743 EEPROM_TXMIXER_GAIN_BG_VAL));
2744 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2745
64522957
GW		 2746 if (rt2x00_rt(rt2x00dev, RT3090)) {
2747 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2748
80d184e6 2749 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 2750 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2751 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 2752 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 2753 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 2754 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2755
2756 rt2800_bbp_write(rt2x00dev, 138, bbp);
2757 }
2758
2759 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2760 rt2x00_rt(rt2x00dev, RT3090) ||
2761 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2762 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2763 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2764 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2765 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2766 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2767 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2768 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2769
2770 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2771 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2772 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2773
2774 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2775 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2776 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2777
2778 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2779 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2780 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2781 }
2782
80d184e6 2783 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 2784 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 2785 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 2786 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2787 else
2788 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2789 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2790 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2791 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2792 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2793 }
2794
fcf51541
BZ		 2795 return 0;
2796}
b9a07ae9
ID		 2797
2798int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2799{
2800 u32 reg;
2801 u16 word;
2802
2803 /*
2804 * Initialize all registers.
2805 */
2806 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2807 rt2800_init_registers(rt2x00dev) ||
2808 rt2800_init_bbp(rt2x00dev) ||
2809 rt2800_init_rfcsr(rt2x00dev)))
2810 return -EIO;
2811
2812 /*
2813 * Send signal to firmware during boot time.
2814 */
2815 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2816
2817 if (rt2x00_is_usb(rt2x00dev) &&
2818 (rt2x00_rt(rt2x00dev, RT3070) ||
2819 rt2x00_rt(rt2x00dev, RT3071) ||
2820 rt2x00_rt(rt2x00dev, RT3572))) {
2821 udelay(200);
2822 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2823 udelay(10);
2824 }
2825
2826 /*
2827 * Enable RX.
2828 */
2829 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2830 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2831 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2832 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2833
2834 udelay(50);
2835
2836 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2837 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2838 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2839 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2840 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2841 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2842
2843 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2844 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2845 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2846 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2847
2848 /*
2849 * Initialize LED control
2850 */
38c8a566
RJH		 2851 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2852 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 2853 word & 0xff, (word >> 8) & 0xff);
2854
38c8a566
RJH		 2855 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2856 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 2857 word & 0xff, (word >> 8) & 0xff);
2858
38c8a566
RJH		 2859 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2860 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 2861 word & 0xff, (word >> 8) & 0xff);
2862
2863 return 0;
2864}
2865EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2866
2867void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2868{
2869 u32 reg;
2870
2871 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2872 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
b9a07ae9 2873 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
b9a07ae9
ID		 2874 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2875
2876 /* Wait for DMA, ignore error */
2877 rt2800_wait_wpdma_ready(rt2x00dev);
2878
2879 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2880 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2881 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2882 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 2883}
2884EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 2885
30e84034
BZ		 2886int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2887{
2888 u32 reg;
2889
2890 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2891
2892 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2893}
2894EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2895
2896static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2897{
2898 u32 reg;
2899
31a4cf1f
GW		 2900 mutex_lock(&rt2x00dev->csr_mutex);
2901
2902 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2903 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2904 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2905 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2906 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2907
2908 /* Wait until the EEPROM has been loaded */
2909 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2910
2911 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2912 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2913 (u32 *)&rt2x00dev->eeprom[i]);
2914 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2915 (u32 *)&rt2x00dev->eeprom[i + 2]);
2916 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2917 (u32 *)&rt2x00dev->eeprom[i + 4]);
2918 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2919 (u32 *)&rt2x00dev->eeprom[i + 6]);
2920
2921 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2922}
2923
2924void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2925{
2926 unsigned int i;
2927
2928 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2929 rt2800_efuse_read(rt2x00dev, i);
2930}
2931EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2932
38bd7b8a
BZ		 2933int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2934{
2935 u16 word;
2936 u8 *mac;
2937 u8 default_lna_gain;
2938
2939 /*
2940 * Start validation of the data that has been read.
2941 */
2942 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2943 if (!is_valid_ether_addr(mac)) {
2944 random_ether_addr(mac);
2945 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2946 }
2947
38c8a566 2948 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 2949 if (word == 0xffff) {
38c8a566
RJH		 2950 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2951 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2952 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2953 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 2954 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2955 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2956 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2957 /*
2958 * There is a max of 2 RX streams for RT28x0 series
2959 */
38c8a566
RJH		 2960 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2961 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2962 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 2963 }
2964
38c8a566 2965 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 2966 if (word == 0xffff) {
38c8a566
RJH		 2967 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2968 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2969 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2970 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2971 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2972 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2973 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2974 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2975 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2976 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2977 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2978 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2979 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2980 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2981 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2982 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 2983 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2984 }
2985
2986 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2987 if ((word & 0x00ff) == 0x00ff) {
2988 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2989 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2990 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2991 }
2992 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2993 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2994 LED_MODE_TXRX_ACTIVITY);
2995 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2996 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 2997 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2998 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2999 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 3000 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 3001 }
3002
3003 /*
3004 * During the LNA validation we are going to use
3005 * lna0 as correct value. Note that EEPROM_LNA
3006 * is never validated.
3007 */
3008 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3009 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3010
3011 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3012 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3013 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3014 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3015 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3016 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3017
3018 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3019 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3020 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3021 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3022 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3023 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3024 default_lna_gain);
3025 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3026
3027 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3028 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3029 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3030 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3031 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3032 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3033
3034 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3035 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3036 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3037 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3038 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3039 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3040 default_lna_gain);
3041 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3042
8d1331b3
ID		 3043 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
3044 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
3045 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
3046 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
3047 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
3048 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
3049
38bd7b8a
BZ		 3050 return 0;
3051}
3052EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3053
3054int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3055{
3056 u32 reg;
3057 u16 value;
3058 u16 eeprom;
3059
3060 /*
3061 * Read EEPROM word for configuration.
3062 */
38c8a566 3063 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 3064
3065 /*
3066 * Identify RF chipset.
3067 */
38c8a566 3068 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a
BZ		 3069 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3070
49e721ec
GW		 3071 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3072 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3073
3074 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 3075 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 3076 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 3077 !rt2x00_rt(rt2x00dev, RT3070) &&
3078 !rt2x00_rt(rt2x00dev, RT3071) &&
3079 !rt2x00_rt(rt2x00dev, RT3090) &&
3080 !rt2x00_rt(rt2x00dev, RT3390) &&
3081 !rt2x00_rt(rt2x00dev, RT3572)) {
3082 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3083 return -ENODEV;
f273fe55 3084 }
714fa663 3085
5122d898
GW		 3086 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3087 !rt2x00_rf(rt2x00dev, RF2850) &&
3088 !rt2x00_rf(rt2x00dev, RF2720) &&
3089 !rt2x00_rf(rt2x00dev, RF2750) &&
3090 !rt2x00_rf(rt2x00dev, RF3020) &&
3091 !rt2x00_rf(rt2x00dev, RF2020) &&
3092 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265 3093 !rt2x00_rf(rt2x00dev, RF3022) &&
f93bc9b3
GW		 3094 !rt2x00_rf(rt2x00dev, RF3052) &&
3095 !rt2x00_rf(rt2x00dev, RF3320)) {
38bd7b8a
BZ		 3096 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3097 return -ENODEV;
3098 }
3099
3100 /*
3101 * Identify default antenna configuration.
3102 */
d96aa640 3103 rt2x00dev->default_ant.tx_chain_num =
38c8a566 3104 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 3105 rt2x00dev->default_ant.rx_chain_num =
38c8a566 3106 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 3107
d96aa640
RJH		 3108 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3109
3110 if (rt2x00_rt(rt2x00dev, RT3070) ||
3111 rt2x00_rt(rt2x00dev, RT3090) ||
3112 rt2x00_rt(rt2x00dev, RT3390)) {
3113 value = rt2x00_get_field16(eeprom,
3114 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3115 switch (value) {
3116 case 0:
3117 case 1:
3118 case 2:
3119 rt2x00dev->default_ant.tx = ANTENNA_A;
3120 rt2x00dev->default_ant.rx = ANTENNA_A;
3121 break;
3122 case 3:
3123 rt2x00dev->default_ant.tx = ANTENNA_A;
3124 rt2x00dev->default_ant.rx = ANTENNA_B;
3125 break;
3126 }
3127 } else {
3128 rt2x00dev->default_ant.tx = ANTENNA_A;
3129 rt2x00dev->default_ant.rx = ANTENNA_A;
3130 }
3131
38bd7b8a
BZ		 3132 /*
3133 * Read frequency offset and RF programming sequence.
3134 */
3135 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3136 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3137
3138 /*
3139 * Read external LNA informations.
3140 */
38c8a566 3141 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
38bd7b8a 3142
38c8a566 3143 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
38bd7b8a 3144 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
38c8a566 3145 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
38bd7b8a
BZ		 3146 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3147
3148 /*
3149 * Detect if this device has an hardware controlled radio.
3150 */
38c8a566 3151 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
38bd7b8a
BZ		 3152 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3153
3154 /*
3155 * Store led settings, for correct led behaviour.
3156 */
3157#ifdef CONFIG_RT2X00_LIB_LEDS
3158 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3159 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3160 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3161
3162 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3163#endif /* CONFIG_RT2X00_LIB_LEDS */
3164
3165 return 0;
3166}
3167EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3168
4da2933f 3169/*
55f9321a 3170 * RF value list for rt28xx
4da2933f
BZ		 3171 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3172 */
3173static const struct rf_channel rf_vals[] = {
3174 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3175 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3176 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3177 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3178 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3179 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3180 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3181 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3182 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3183 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3184 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3185 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3186 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3187 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3188
3189 /* 802.11 UNI / HyperLan 2 */
3190 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3191 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3192 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3193 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3194 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3195 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3196 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3197 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3198 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3199 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3200 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3201 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3202
3203 /* 802.11 HyperLan 2 */
3204 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3205 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3206 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3207 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3208 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3209 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3210 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3211 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3212 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3213 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3214 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3215 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3216 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3217 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3218 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3219 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3220
3221 /* 802.11 UNII */
3222 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3223 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3224 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3225 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3226 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3227 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3228 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3229 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3230 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3231 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3232 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3233
3234 /* 802.11 Japan */
3235 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3236 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3237 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3238 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3239 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3240 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3241 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3242};
3243
3244/*
55f9321a
ID		 3245 * RF value list for rt3xxx
3246 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 3247 */
55f9321a 3248static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 3249 {1, 241, 2, 2 },
3250 {2, 241, 2, 7 },
3251 {3, 242, 2, 2 },
3252 {4, 242, 2, 7 },
3253 {5, 243, 2, 2 },
3254 {6, 243, 2, 7 },
3255 {7, 244, 2, 2 },
3256 {8, 244, 2, 7 },
3257 {9, 245, 2, 2 },
3258 {10, 245, 2, 7 },
3259 {11, 246, 2, 2 },
3260 {12, 246, 2, 7 },
3261 {13, 247, 2, 2 },
3262 {14, 248, 2, 4 },
55f9321a
ID		 3263
3264 /* 802.11 UNI / HyperLan 2 */
3265 {36, 0x56, 0, 4},
3266 {38, 0x56, 0, 6},
3267 {40, 0x56, 0, 8},
3268 {44, 0x57, 0, 0},
3269 {46, 0x57, 0, 2},
3270 {48, 0x57, 0, 4},
3271 {52, 0x57, 0, 8},
3272 {54, 0x57, 0, 10},
3273 {56, 0x58, 0, 0},
3274 {60, 0x58, 0, 4},
3275 {62, 0x58, 0, 6},
3276 {64, 0x58, 0, 8},
3277
3278 /* 802.11 HyperLan 2 */
3279 {100, 0x5b, 0, 8},
3280 {102, 0x5b, 0, 10},
3281 {104, 0x5c, 0, 0},
3282 {108, 0x5c, 0, 4},
3283 {110, 0x5c, 0, 6},
3284 {112, 0x5c, 0, 8},
3285 {116, 0x5d, 0, 0},
3286 {118, 0x5d, 0, 2},
3287 {120, 0x5d, 0, 4},
3288 {124, 0x5d, 0, 8},
3289 {126, 0x5d, 0, 10},
3290 {128, 0x5e, 0, 0},
3291 {132, 0x5e, 0, 4},
3292 {134, 0x5e, 0, 6},
3293 {136, 0x5e, 0, 8},
3294 {140, 0x5f, 0, 0},
3295
3296 /* 802.11 UNII */
3297 {149, 0x5f, 0, 9},
3298 {151, 0x5f, 0, 11},
3299 {153, 0x60, 0, 1},
3300 {157, 0x60, 0, 5},
3301 {159, 0x60, 0, 7},
3302 {161, 0x60, 0, 9},
3303 {165, 0x61, 0, 1},
3304 {167, 0x61, 0, 3},
3305 {169, 0x61, 0, 5},
3306 {171, 0x61, 0, 7},
3307 {173, 0x61, 0, 9},
4da2933f
BZ		 3308};
3309
3310int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3311{
4da2933f
BZ		 3312 struct hw_mode_spec *spec = &rt2x00dev->spec;
3313 struct channel_info *info;
8d1331b3
ID		 3314 char *default_power1;
3315 char *default_power2;
4da2933f 3316 unsigned int i;
8d1331b3 3317 unsigned short max_power;
4da2933f
BZ		 3318 u16 eeprom;
3319
93b6bd26
GW		 3320 /*
3321 * Disable powersaving as default on PCI devices.
3322 */
cea90e55 3323 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 3324 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3325
4da2933f
BZ		 3326 /*
3327 * Initialize all hw fields.
3328 */
3329 rt2x00dev->hw->flags =
4da2933f
BZ		 3330 IEEE80211_HW_SIGNAL_DBM |
3331 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 3332 IEEE80211_HW_PS_NULLFUNC_STACK |
3333 IEEE80211_HW_AMPDU_AGGREGATION;
5a5b6ed6
HS		 3334 /*
3335 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3336 * unless we are capable of sending the buffered frames out after the
3337 * DTIM transmission using rt2x00lib_beacondone. This will send out
3338 * multicast and broadcast traffic immediately instead of buffering it
3339 * infinitly and thus dropping it after some time.
3340 */
3341 if (!rt2x00_is_usb(rt2x00dev))
3342 rt2x00dev->hw->flags |=
3343 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 3344
4da2933f
BZ		 3345 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3346 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3347 rt2x00_eeprom_addr(rt2x00dev,
3348 EEPROM_MAC_ADDR_0));
3349
3f2bee24
HS		 3350 /*
3351 * As rt2800 has a global fallback table we cannot specify
3352 * more then one tx rate per frame but since the hw will
3353 * try several rates (based on the fallback table) we should
ba3b9e5e 3354 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 3355 * we are going to try. Otherwise mac80211 will truncate our
3356 * reported tx rates and the rc algortihm will end up with
3357 * incorrect data.
3358 */
ba3b9e5e
HS		 3359 rt2x00dev->hw->max_rates = 1;
3360 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 3361 rt2x00dev->hw->max_rate_tries = 1;
3362
38c8a566 3363 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 3364
3365 /*
3366 * Initialize hw_mode information.
3367 */
3368 spec->supported_bands = SUPPORT_BAND_2GHZ;
3369 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3370
5122d898 3371 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 3372 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 3373 spec->num_channels = 14;
3374 spec->channels = rf_vals;
55f9321a
ID		 3375 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3376 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 3377 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3378 spec->num_channels = ARRAY_SIZE(rf_vals);
3379 spec->channels = rf_vals;
5122d898
GW		 3380 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3381 rt2x00_rf(rt2x00dev, RF2020) ||
3382 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3
GW		 3383 rt2x00_rf(rt2x00dev, RF3022) ||
3384 rt2x00_rf(rt2x00dev, RF3320)) {
55f9321a
ID		 3385 spec->num_channels = 14;
3386 spec->channels = rf_vals_3x;
3387 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3388 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3389 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3390 spec->channels = rf_vals_3x;
4da2933f
BZ		 3391 }
3392
3393 /*
3394 * Initialize HT information.
3395 */
5122d898 3396 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 3397 spec->ht.ht_supported = true;
3398 else
3399 spec->ht.ht_supported = false;
3400
4da2933f 3401 spec->ht.cap =
06443e46 3402 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 3403 IEEE80211_HT_CAP_GRN_FLD |
3404 IEEE80211_HT_CAP_SGI_20 |
aa674631 3405 IEEE80211_HT_CAP_SGI_40;
22cabaa6 3406
38c8a566 3407 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 3408 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3409
aa674631 3410 spec->ht.cap |=
38c8a566 3411 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 3412 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3413
4da2933f
BZ		 3414 spec->ht.ampdu_factor = 3;
3415 spec->ht.ampdu_density = 4;
3416 spec->ht.mcs.tx_params =
3417 IEEE80211_HT_MCS_TX_DEFINED |
3418 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 3419 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 3420 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3421
38c8a566 3422 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 3423 case 3:
3424 spec->ht.mcs.rx_mask[2] = 0xff;
3425 case 2:
3426 spec->ht.mcs.rx_mask[1] = 0xff;
3427 case 1:
3428 spec->ht.mcs.rx_mask[0] = 0xff;
3429 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3430 break;
3431 }
3432
3433 /*
3434 * Create channel information array
3435 */
baeb2ffa 3436 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 3437 if (!info)
3438 return -ENOMEM;
3439
3440 spec->channels_info = info;
3441
8d1331b3
ID		 3442 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3443 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3444 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3445 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 3446
3447 for (i = 0; i < 14; i++) {
8d1331b3
ID		 3448 info[i].max_power = max_power;
3449 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3450 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3451 }
3452
3453 if (spec->num_channels > 14) {
8d1331b3
ID		 3454 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3455 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3456 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 3457
3458 for (i = 14; i < spec->num_channels; i++) {
8d1331b3
ID		 3459 info[i].max_power = max_power;
3460 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3461 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
4da2933f
BZ		 3462 }
3463 }
3464
3465 return 0;
3466}
3467EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3468
2ce33995
BZ		 3469/*
3470 * IEEE80211 stack callback functions.
3471 */
e783619e
HS		 3472void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3473 u16 *iv16)
2ce33995
BZ		 3474{
3475 struct rt2x00_dev *rt2x00dev = hw->priv;
3476 struct mac_iveiv_entry iveiv_entry;
3477 u32 offset;
3478
3479 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3480 rt2800_register_multiread(rt2x00dev, offset,
3481 &iveiv_entry, sizeof(iveiv_entry));
3482
855da5e0
JL		 3483 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3484 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 3485}
e783619e 3486EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 3487
e783619e 3488int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 3489{
3490 struct rt2x00_dev *rt2x00dev = hw->priv;
3491 u32 reg;
3492 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3493
3494 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3495 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3496 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3497
3498 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3499 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3500 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3501
3502 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3503 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3504 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3505
3506 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3507 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3508 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3509
3510 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3511 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3512 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3513
3514 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3515 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3516 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3517
3518 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3519 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3520 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3521
3522 return 0;
3523}
e783619e 3524EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 3525
e783619e
HS		 3526int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3527 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 3528{
3529 struct rt2x00_dev *rt2x00dev = hw->priv;
3530 struct data_queue *queue;
3531 struct rt2x00_field32 field;
3532 int retval;
3533 u32 reg;
3534 u32 offset;
3535
3536 /*
3537 * First pass the configuration through rt2x00lib, that will
3538 * update the queue settings and validate the input. After that
3539 * we are free to update the registers based on the value
3540 * in the queue parameter.
3541 */
3542 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3543 if (retval)
3544 return retval;
3545
3546 /*
3547 * We only need to perform additional register initialization
3548 * for WMM queues/
3549 */
3550 if (queue_idx >= 4)
3551 return 0;
3552
3553 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3554
3555 /* Update WMM TXOP register */
3556 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3557 field.bit_offset = (queue_idx & 1) * 16;
3558 field.bit_mask = 0xffff << field.bit_offset;
3559
3560 rt2800_register_read(rt2x00dev, offset, &reg);
3561 rt2x00_set_field32(&reg, field, queue->txop);
3562 rt2800_register_write(rt2x00dev, offset, reg);
3563
3564 /* Update WMM registers */
3565 field.bit_offset = queue_idx * 4;
3566 field.bit_mask = 0xf << field.bit_offset;
3567
3568 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3569 rt2x00_set_field32(&reg, field, queue->aifs);
3570 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3571
3572 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3573 rt2x00_set_field32(&reg, field, queue->cw_min);
3574 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3575
3576 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3577 rt2x00_set_field32(&reg, field, queue->cw_max);
3578 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3579
3580 /* Update EDCA registers */
3581 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3582
3583 rt2800_register_read(rt2x00dev, offset, &reg);
3584 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3585 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3586 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3587 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3588 rt2800_register_write(rt2x00dev, offset, reg);
3589
3590 return 0;
3591}
e783619e 3592EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3593
e783619e 3594u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3595{
3596 struct rt2x00_dev *rt2x00dev = hw->priv;
3597 u64 tsf;
3598 u32 reg;
3599
3600 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3601 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3602 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3603 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3604
3605 return tsf;
3606}
e783619e 3607EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3608
e783619e
HS		 3609int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3610 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 3611 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3612 u8 buf_size)
1df90809 3613{
1df90809
HS		 3614 int ret = 0;
3615
3616 switch (action) {
3617 case IEEE80211_AMPDU_RX_START:
3618 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 3619 /*
3620 * The hw itself takes care of setting up BlockAck mechanisms.
3621 * So, we only have to allow mac80211 to nagotiate a BlockAck
3622 * agreement. Once that is done, the hw will BlockAck incoming
3623 * AMPDUs without further setup.
3624 */
1df90809
HS		 3625 break;
3626 case IEEE80211_AMPDU_TX_START:
3627 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3628 break;
3629 case IEEE80211_AMPDU_TX_STOP:
3630 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3631 break;
3632 case IEEE80211_AMPDU_TX_OPERATIONAL:
3633 break;
3634 default:
4e9e58c6 3635 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3636 }
3637
3638 return ret;
3639}
e783619e 3640EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 3641
977206d7
HS		 3642int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3643 struct survey_info *survey)
3644{
3645 struct rt2x00_dev *rt2x00dev = hw->priv;
3646 struct ieee80211_conf *conf = &hw->conf;
3647 u32 idle, busy, busy_ext;
3648
3649 if (idx != 0)
3650 return -ENOENT;
3651
3652 survey->channel = conf->channel;
3653
3654 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3655 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3656 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3657
3658 if (idle || busy) {
3659 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3660 SURVEY_INFO_CHANNEL_TIME_BUSY |
3661 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3662
3663 survey->channel_time = (idle + busy) / 1000;
3664 survey->channel_time_busy = busy / 1000;
3665 survey->channel_time_ext_busy = busy_ext / 1000;
3666 }
3667
3668 return 0;
3669
3670}
3671EXPORT_SYMBOL_GPL(rt2800_get_survey);
3672
a5ea2f02
ID		 3673MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3674MODULE_VERSION(DRV_VERSION);
3675MODULE_DESCRIPTION("Ralink RT2800 library");
3676MODULE_LICENSE("GPL");
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