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rt2x00: Enable fallback rates for rt61pci and rt73usb
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
9c9a0d14 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 4
9c9a0d14
GW		 5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
44MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
45MODULE_DESCRIPTION("rt2800 library");
46MODULE_LICENSE("GPL");
47
48/*
49 * Register access.
50 * All access to the CSR registers will go through the methods
51 * rt2800_register_read and rt2800_register_write.
52 * BBP and RF register require indirect register access,
53 * and use the CSR registers BBPCSR and RFCSR to achieve this.
54 * These indirect registers work with busy bits,
55 * and we will try maximal REGISTER_BUSY_COUNT times to access
56 * the register while taking a REGISTER_BUSY_DELAY us delay
57 * between each attampt. When the busy bit is still set at that time,
58 * the access attempt is considered to have failed,
59 * and we will print an error.
60 * The _lock versions must be used if you already hold the csr_mutex
61 */
62#define WAIT_FOR_BBP(__dev, __reg) \
63 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RFCSR(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
66#define WAIT_FOR_RF(__dev, __reg) \
67 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
68#define WAIT_FOR_MCU(__dev, __reg) \
69 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
70 H2M_MAILBOX_CSR_OWNER, (__reg))
71
baff8006
HS		 72static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
73{
74 /* check for rt2872 on SoC */
75 if (!rt2x00_is_soc(rt2x00dev) ||
76 !rt2x00_rt(rt2x00dev, RT2872))
77 return false;
78
79 /* we know for sure that these rf chipsets are used on rt305x boards */
80 if (rt2x00_rf(rt2x00dev, RF3020) ||
81 rt2x00_rf(rt2x00dev, RF3021) ||
82 rt2x00_rf(rt2x00dev, RF3022))
83 return true;
84
85 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
86 return false;
87}
88
fcf51541
BZ		 89static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
90 const unsigned int word, const u8 value)
89297425
BZ		 91{
92 u32 reg;
93
94 mutex_lock(&rt2x00dev->csr_mutex);
95
96 /*
97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the new data into the register.
99 */
100 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
101 reg = 0;
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
105 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 106 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 107 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
108
109 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
110 }
111
112 mutex_unlock(&rt2x00dev->csr_mutex);
113}
89297425 114
fcf51541
BZ		 115static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
116 const unsigned int word, u8 *value)
89297425
BZ		 117{
118 u32 reg;
119
120 mutex_lock(&rt2x00dev->csr_mutex);
121
122 /*
123 * Wait until the BBP becomes available, afterwards we
124 * can safely write the read request into the register.
125 * After the data has been written, we wait until hardware
126 * returns the correct value, if at any time the register
127 * doesn't become available in time, reg will be 0xffffffff
128 * which means we return 0xff to the caller.
129 */
130 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
131 reg = 0;
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
133 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
134 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 135 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 136 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
137
138 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
139
140 WAIT_FOR_BBP(rt2x00dev, &reg);
141 }
142
143 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
144
145 mutex_unlock(&rt2x00dev->csr_mutex);
146}
89297425 147
fcf51541
BZ		 148static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
149 const unsigned int word, const u8 value)
89297425
BZ		 150{
151 u32 reg;
152
153 mutex_lock(&rt2x00dev->csr_mutex);
154
155 /*
156 * Wait until the RFCSR becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
160 reg = 0;
161 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
162 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
163 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
164 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
165
166 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
167 }
168
169 mutex_unlock(&rt2x00dev->csr_mutex);
170}
89297425 171
fcf51541
BZ		 172static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
173 const unsigned int word, u8 *value)
89297425
BZ		 174{
175 u32 reg;
176
177 mutex_lock(&rt2x00dev->csr_mutex);
178
179 /*
180 * Wait until the RFCSR becomes available, afterwards we
181 * can safely write the read request into the register.
182 * After the data has been written, we wait until hardware
183 * returns the correct value, if at any time the register
184 * doesn't become available in time, reg will be 0xffffffff
185 * which means we return 0xff to the caller.
186 */
187 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
188 reg = 0;
189 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
190 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
191 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
192
193 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
194
195 WAIT_FOR_RFCSR(rt2x00dev, &reg);
196 }
197
198 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
199
200 mutex_unlock(&rt2x00dev->csr_mutex);
201}
89297425 202
fcf51541
BZ		 203static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
204 const unsigned int word, const u32 value)
89297425
BZ		 205{
206 u32 reg;
207
208 mutex_lock(&rt2x00dev->csr_mutex);
209
210 /*
211 * Wait until the RF becomes available, afterwards we
212 * can safely write the new data into the register.
213 */
214 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
215 reg = 0;
216 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
217 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
218 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
219 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
220
221 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
222 rt2x00_rf_write(rt2x00dev, word, value);
223 }
224
225 mutex_unlock(&rt2x00dev->csr_mutex);
226}
89297425
BZ		 227
228void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
229 const u8 command, const u8 token,
230 const u8 arg0, const u8 arg1)
231{
232 u32 reg;
233
ee303e54 234 /*
cea90e55 235 * SOC devices don't support MCU requests.
ee303e54 236 */
cea90e55 237 if (rt2x00_is_soc(rt2x00dev))
ee303e54 238 return;
89297425
BZ		 239
240 mutex_lock(&rt2x00dev->csr_mutex);
241
242 /*
243 * Wait until the MCU becomes available, afterwards we
244 * can safely write the new data into the register.
245 */
246 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
247 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
248 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
249 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
250 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
251 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
252
253 reg = 0;
254 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
255 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
256 }
257
258 mutex_unlock(&rt2x00dev->csr_mutex);
259}
260EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 261
67a4c1e2
GW		 262int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
263{
264 unsigned int i;
265 u32 reg;
266
267 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
268 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
269 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
270 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
271 return 0;
272
273 msleep(1);
274 }
275
276 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
277 return -EACCES;
278}
279EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
280
0b8004aa 281void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
59679b91 282{
59679b91
GW		 283 u32 word;
284
285 /*
286 * Initialize TX Info descriptor
287 */
288 rt2x00_desc_read(txwi, 0, &word);
289 rt2x00_set_field32(&word, TXWI_W0_FRAG,
290 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
291 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
292 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
293 rt2x00_set_field32(&word, TXWI_W0_TS,
294 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
295 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
296 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
297 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
298 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
299 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
300 rt2x00_set_field32(&word, TXWI_W0_BW,
301 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
302 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
303 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
304 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
305 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
306 rt2x00_desc_write(txwi, 0, word);
307
308 rt2x00_desc_read(txwi, 1, &word);
309 rt2x00_set_field32(&word, TXWI_W1_ACK,
310 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
311 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
312 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
313 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
314 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
315 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
316 txdesc->key_idx : 0xff);
317 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
318 txdesc->length);
319 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
320 rt2x00_desc_write(txwi, 1, word);
321
322 /*
323 * Always write 0 to IV/EIV fields, hardware will insert the IV
324 * from the IVEIV register when TXD_W3_WIV is set to 0.
325 * When TXD_W3_WIV is set to 1 it will use the IV data
326 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
327 * crypto entry in the registers should be used to encrypt the frame.
328 */
329 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
330 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
331}
332EXPORT_SYMBOL_GPL(rt2800_write_txwi);
333
2de64dd2
GW		 334void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
335{
336 __le32 *rxwi = (__le32 *) skb->data;
337 u32 word;
338
339 rt2x00_desc_read(rxwi, 0, &word);
340
341 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
342 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
343
344 rt2x00_desc_read(rxwi, 1, &word);
345
346 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
347 rxdesc->flags |= RX_FLAG_SHORT_GI;
348
349 if (rt2x00_get_field32(word, RXWI_W1_BW))
350 rxdesc->flags |= RX_FLAG_40MHZ;
351
352 /*
353 * Detect RX rate, always use MCS as signal type.
354 */
355 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
356 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
357 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
358
359 /*
360 * Mask of 0x8 bit to remove the short preamble flag.
361 */
362 if (rxdesc->rate_mode == RATE_MODE_CCK)
363 rxdesc->signal &= ~0x8;
364
365 rt2x00_desc_read(rxwi, 2, &word);
366
367 rxdesc->rssi =
368 (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
369 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
370
371 /*
372 * Remove RXWI descriptor from start of buffer.
373 */
374 skb_pull(skb, RXWI_DESC_SIZE);
375}
376EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
377
f0194b2d
GW		 378void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
379{
380 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
381 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
382 unsigned int beacon_base;
383 u32 reg;
384
385 /*
386 * Disable beaconing while we are reloading the beacon data,
387 * otherwise we might be sending out invalid data.
388 */
389 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
390 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
391 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
392
393 /*
394 * Add space for the TXWI in front of the skb.
395 */
396 skb_push(entry->skb, TXWI_DESC_SIZE);
397 memset(entry->skb, 0, TXWI_DESC_SIZE);
398
399 /*
400 * Register descriptor details in skb frame descriptor.
401 */
402 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
403 skbdesc->desc = entry->skb->data;
404 skbdesc->desc_len = TXWI_DESC_SIZE;
405
406 /*
407 * Add the TXWI for the beacon to the skb.
408 */
409 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
410
411 /*
412 * Dump beacon to userspace through debugfs.
413 */
414 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
415
416 /*
417 * Write entire beacon with TXWI to register.
418 */
419 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
420 rt2800_register_multiwrite(rt2x00dev, beacon_base,
421 entry->skb->data, entry->skb->len);
422
423 /*
424 * Enable beaconing again.
425 */
426 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
427 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
428 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
429 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
430
431 /*
432 * Clean up beacon skb.
433 */
434 dev_kfree_skb_any(entry->skb);
435 entry->skb = NULL;
436}
437EXPORT_SYMBOL(rt2800_write_beacon);
438
f4450616
BZ		 439#ifdef CONFIG_RT2X00_LIB_DEBUGFS
440const struct rt2x00debug rt2800_rt2x00debug = {
441 .owner = THIS_MODULE,
442 .csr = {
443 .read = rt2800_register_read,
444 .write = rt2800_register_write,
445 .flags = RT2X00DEBUGFS_OFFSET,
446 .word_base = CSR_REG_BASE,
447 .word_size = sizeof(u32),
448 .word_count = CSR_REG_SIZE / sizeof(u32),
449 },
450 .eeprom = {
451 .read = rt2x00_eeprom_read,
452 .write = rt2x00_eeprom_write,
453 .word_base = EEPROM_BASE,
454 .word_size = sizeof(u16),
455 .word_count = EEPROM_SIZE / sizeof(u16),
456 },
457 .bbp = {
458 .read = rt2800_bbp_read,
459 .write = rt2800_bbp_write,
460 .word_base = BBP_BASE,
461 .word_size = sizeof(u8),
462 .word_count = BBP_SIZE / sizeof(u8),
463 },
464 .rf = {
465 .read = rt2x00_rf_read,
466 .write = rt2800_rf_write,
467 .word_base = RF_BASE,
468 .word_size = sizeof(u32),
469 .word_count = RF_SIZE / sizeof(u32),
470 },
471};
472EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
473#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
474
475int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
476{
477 u32 reg;
478
479 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
480 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
481}
482EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
483
484#ifdef CONFIG_RT2X00_LIB_LEDS
485static void rt2800_brightness_set(struct led_classdev *led_cdev,
486 enum led_brightness brightness)
487{
488 struct rt2x00_led *led =
489 container_of(led_cdev, struct rt2x00_led, led_dev);
490 unsigned int enabled = brightness != LED_OFF;
491 unsigned int bg_mode =
492 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
493 unsigned int polarity =
494 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
495 EEPROM_FREQ_LED_POLARITY);
496 unsigned int ledmode =
497 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
498 EEPROM_FREQ_LED_MODE);
499
500 if (led->type == LED_TYPE_RADIO) {
501 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
502 enabled ? 0x20 : 0);
503 } else if (led->type == LED_TYPE_ASSOC) {
504 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
505 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
506 } else if (led->type == LED_TYPE_QUALITY) {
507 /*
508 * The brightness is divided into 6 levels (0 - 5),
509 * The specs tell us the following levels:
510 * 0, 1 ,3, 7, 15, 31
511 * to determine the level in a simple way we can simply
512 * work with bitshifting:
513 * (1 << level) - 1
514 */
515 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
516 (1 << brightness / (LED_FULL / 6)) - 1,
517 polarity);
518 }
519}
520
521static int rt2800_blink_set(struct led_classdev *led_cdev,
522 unsigned long *delay_on, unsigned long *delay_off)
523{
524 struct rt2x00_led *led =
525 container_of(led_cdev, struct rt2x00_led, led_dev);
526 u32 reg;
527
528 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
529 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
530 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 531 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
532
533 return 0;
534}
535
b3579d6a 536static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 537 struct rt2x00_led *led, enum led_type type)
538{
539 led->rt2x00dev = rt2x00dev;
540 led->type = type;
541 led->led_dev.brightness_set = rt2800_brightness_set;
542 led->led_dev.blink_set = rt2800_blink_set;
543 led->flags = LED_INITIALIZED;
544}
f4450616
BZ		 545#endif /* CONFIG_RT2X00_LIB_LEDS */
546
547/*
548 * Configuration handlers.
549 */
550static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00lib_crypto *crypto,
552 struct ieee80211_key_conf *key)
553{
554 struct mac_wcid_entry wcid_entry;
555 struct mac_iveiv_entry iveiv_entry;
556 u32 offset;
557 u32 reg;
558
559 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
560
561 rt2800_register_read(rt2x00dev, offset, &reg);
562 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
563 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
564 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
565 (crypto->cmd == SET_KEY) * crypto->cipher);
566 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
567 (crypto->cmd == SET_KEY) * crypto->bssidx);
568 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
569 rt2800_register_write(rt2x00dev, offset, reg);
570
571 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
572
573 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
574 if ((crypto->cipher == CIPHER_TKIP) ||
575 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
576 (crypto->cipher == CIPHER_AES))
577 iveiv_entry.iv[3] |= 0x20;
578 iveiv_entry.iv[3] |= key->keyidx << 6;
579 rt2800_register_multiwrite(rt2x00dev, offset,
580 &iveiv_entry, sizeof(iveiv_entry));
581
582 offset = MAC_WCID_ENTRY(key->hw_key_idx);
583
584 memset(&wcid_entry, 0, sizeof(wcid_entry));
585 if (crypto->cmd == SET_KEY)
586 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
587 rt2800_register_multiwrite(rt2x00dev, offset,
588 &wcid_entry, sizeof(wcid_entry));
589}
590
591int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
592 struct rt2x00lib_crypto *crypto,
593 struct ieee80211_key_conf *key)
594{
595 struct hw_key_entry key_entry;
596 struct rt2x00_field32 field;
597 u32 offset;
598 u32 reg;
599
600 if (crypto->cmd == SET_KEY) {
601 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
602
603 memcpy(key_entry.key, crypto->key,
604 sizeof(key_entry.key));
605 memcpy(key_entry.tx_mic, crypto->tx_mic,
606 sizeof(key_entry.tx_mic));
607 memcpy(key_entry.rx_mic, crypto->rx_mic,
608 sizeof(key_entry.rx_mic));
609
610 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
611 rt2800_register_multiwrite(rt2x00dev, offset,
612 &key_entry, sizeof(key_entry));
613 }
614
615 /*
616 * The cipher types are stored over multiple registers
617 * starting with SHARED_KEY_MODE_BASE each word will have
618 * 32 bits and contains the cipher types for 2 bssidx each.
619 * Using the correct defines correctly will cause overhead,
620 * so just calculate the correct offset.
621 */
622 field.bit_offset = 4 * (key->hw_key_idx % 8);
623 field.bit_mask = 0x7 << field.bit_offset;
624
625 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
626
627 rt2800_register_read(rt2x00dev, offset, &reg);
628 rt2x00_set_field32(&reg, field,
629 (crypto->cmd == SET_KEY) * crypto->cipher);
630 rt2800_register_write(rt2x00dev, offset, reg);
631
632 /*
633 * Update WCID information
634 */
635 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
636
637 return 0;
638}
639EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
640
641int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
642 struct rt2x00lib_crypto *crypto,
643 struct ieee80211_key_conf *key)
644{
645 struct hw_key_entry key_entry;
646 u32 offset;
647
648 if (crypto->cmd == SET_KEY) {
649 /*
650 * 1 pairwise key is possible per AID, this means that the AID
651 * equals our hw_key_idx. Make sure the WCID starts _after_ the
652 * last possible shared key entry.
653 */
654 if (crypto->aid > (256 - 32))
655 return -ENOSPC;
656
657 key->hw_key_idx = 32 + crypto->aid;
658
659 memcpy(key_entry.key, crypto->key,
660 sizeof(key_entry.key));
661 memcpy(key_entry.tx_mic, crypto->tx_mic,
662 sizeof(key_entry.tx_mic));
663 memcpy(key_entry.rx_mic, crypto->rx_mic,
664 sizeof(key_entry.rx_mic));
665
666 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
667 rt2800_register_multiwrite(rt2x00dev, offset,
668 &key_entry, sizeof(key_entry));
669 }
670
671 /*
672 * Update WCID information
673 */
674 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
675
676 return 0;
677}
678EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
679
680void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
681 const unsigned int filter_flags)
682{
683 u32 reg;
684
685 /*
686 * Start configuration steps.
687 * Note that the version error will always be dropped
688 * and broadcast frames will always be accepted since
689 * there is no filter for it at this time.
690 */
691 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
692 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
693 !(filter_flags & FIF_FCSFAIL));
694 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
695 !(filter_flags & FIF_PLCPFAIL));
696 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
697 !(filter_flags & FIF_PROMISC_IN_BSS));
698 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
699 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
700 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
701 !(filter_flags & FIF_ALLMULTI));
702 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
703 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
704 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
705 !(filter_flags & FIF_CONTROL));
706 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
707 !(filter_flags & FIF_CONTROL));
708 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
709 !(filter_flags & FIF_CONTROL));
710 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
711 !(filter_flags & FIF_CONTROL));
712 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
713 !(filter_flags & FIF_CONTROL));
714 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
715 !(filter_flags & FIF_PSPOLL));
716 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
717 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
718 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
719 !(filter_flags & FIF_CONTROL));
720 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
721}
722EXPORT_SYMBOL_GPL(rt2800_config_filter);
723
724void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
725 struct rt2x00intf_conf *conf, const unsigned int flags)
726{
727 unsigned int beacon_base;
728 u32 reg;
729
730 if (flags & CONFIG_UPDATE_TYPE) {
731 /*
732 * Clear current synchronisation setup.
733 * For the Beacon base registers we only need to clear
734 * the first byte since that byte contains the VALID and OWNER
735 * bits which (when set to 0) will invalidate the entire beacon.
736 */
737 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
738 rt2800_register_write(rt2x00dev, beacon_base, 0);
739
740 /*
741 * Enable synchronisation.
742 */
743 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
744 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
745 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 746 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
747 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 748 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
749 }
750
751 if (flags & CONFIG_UPDATE_MAC) {
752 reg = le32_to_cpu(conf->mac[1]);
753 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
754 conf->mac[1] = cpu_to_le32(reg);
755
756 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
757 conf->mac, sizeof(conf->mac));
758 }
759
760 if (flags & CONFIG_UPDATE_BSSID) {
761 reg = le32_to_cpu(conf->bssid[1]);
762 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
763 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
764 conf->bssid[1] = cpu_to_le32(reg);
765
766 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
767 conf->bssid, sizeof(conf->bssid));
768 }
769}
770EXPORT_SYMBOL_GPL(rt2800_config_intf);
771
772void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
773{
774 u32 reg;
775
f4450616
BZ		 776 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
777 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
778 !!erp->short_preamble);
779 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
780 !!erp->short_preamble);
781 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
782
783 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
784 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
785 erp->cts_protection ? 2 : 0);
786 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
787
788 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
789 erp->basic_rates);
790 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
791
792 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
793 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 794 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
795
796 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 797 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 798 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
799
800 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
801 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
802 erp->beacon_int * 16);
803 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
804}
805EXPORT_SYMBOL_GPL(rt2800_config_erp);
806
807void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
808{
809 u8 r1;
810 u8 r3;
811
812 rt2800_bbp_read(rt2x00dev, 1, &r1);
813 rt2800_bbp_read(rt2x00dev, 3, &r3);
814
815 /*
816 * Configure the TX antenna.
817 */
818 switch ((int)ant->tx) {
819 case 1:
820 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 821 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 822 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
823 break;
824 case 2:
825 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
826 break;
827 case 3:
828 /* Do nothing */
829 break;
830 }
831
832 /*
833 * Configure the RX antenna.
834 */
835 switch ((int)ant->rx) {
836 case 1:
837 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
838 break;
839 case 2:
840 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
841 break;
842 case 3:
843 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
844 break;
845 }
846
847 rt2800_bbp_write(rt2x00dev, 3, r3);
848 rt2800_bbp_write(rt2x00dev, 1, r1);
849}
850EXPORT_SYMBOL_GPL(rt2800_config_ant);
851
852static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
853 struct rt2x00lib_conf *libconf)
854{
855 u16 eeprom;
856 short lna_gain;
857
858 if (libconf->rf.channel <= 14) {
859 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
860 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
861 } else if (libconf->rf.channel <= 64) {
862 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
863 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
864 } else if (libconf->rf.channel <= 128) {
865 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
866 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
867 } else {
868 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
869 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
870 }
871
872 rt2x00dev->lna_gain = lna_gain;
873}
874
06855ef4
GW		 875static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
876 struct ieee80211_conf *conf,
877 struct rf_channel *rf,
878 struct channel_info *info)
f4450616
BZ		 879{
880 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
881
882 if (rt2x00dev->default_ant.tx == 1)
883 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
884
885 if (rt2x00dev->default_ant.rx == 1) {
886 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
887 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
888 } else if (rt2x00dev->default_ant.rx == 2)
889 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
890
891 if (rf->channel > 14) {
892 /*
893 * When TX power is below 0, we should increase it by 7 to
894 * make it a positive value (Minumum value is -7).
895 * However this means that values between 0 and 7 have
896 * double meaning, and we should set a 7DBm boost flag.
897 */
898 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
899 (info->tx_power1 >= 0));
900
901 if (info->tx_power1 < 0)
902 info->tx_power1 += 7;
903
904 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
905 TXPOWER_A_TO_DEV(info->tx_power1));
906
907 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
908 (info->tx_power2 >= 0));
909
910 if (info->tx_power2 < 0)
911 info->tx_power2 += 7;
912
913 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
914 TXPOWER_A_TO_DEV(info->tx_power2));
915 } else {
916 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
917 TXPOWER_G_TO_DEV(info->tx_power1));
918 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
919 TXPOWER_G_TO_DEV(info->tx_power2));
920 }
921
922 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
923
924 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
925 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
926 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
927 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
928
929 udelay(200);
930
931 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
932 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
933 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
934 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
935
936 udelay(200);
937
938 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
939 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
940 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
941 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
942}
943
06855ef4
GW		 944static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
945 struct ieee80211_conf *conf,
946 struct rf_channel *rf,
947 struct channel_info *info)
f4450616
BZ		 948{
949 u8 rfcsr;
950
951 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 952 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 953
954 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 955 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 956 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
957
958 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
959 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
960 TXPOWER_G_TO_DEV(info->tx_power1));
961 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
962
5a673964
HS		 963 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
964 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
965 TXPOWER_G_TO_DEV(info->tx_power2));
966 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
967
f4450616
BZ		 968 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
969 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
970 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
971
972 rt2800_rfcsr_write(rt2x00dev, 24,
973 rt2x00dev->calibration[conf_is_ht40(conf)]);
974
71976907 975 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 976 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 977 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 978}
979
980static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
981 struct ieee80211_conf *conf,
982 struct rf_channel *rf,
983 struct channel_info *info)
984{
985 u32 reg;
986 unsigned int tx_pin;
987 u8 bbp;
988
06855ef4
GW		 989 if (rt2x00_rf(rt2x00dev, RF2020) ||
990 rt2x00_rf(rt2x00dev, RF3020) ||
991 rt2x00_rf(rt2x00dev, RF3021) ||
992 rt2x00_rf(rt2x00dev, RF3022))
993 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 994 else
06855ef4 995 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 996
997 /*
998 * Change BBP settings
999 */
1000 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1001 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1002 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1003 rt2800_bbp_write(rt2x00dev, 86, 0);
1004
1005 if (rf->channel <= 14) {
1006 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1007 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1008 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1009 } else {
1010 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1011 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1012 }
1013 } else {
1014 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1015
1016 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1017 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1018 else
1019 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1020 }
1021
1022 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1023 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1024 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1025 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1026 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1027
1028 tx_pin = 0;
1029
1030 /* Turn on unused PA or LNA when not using 1T or 1R */
1031 if (rt2x00dev->default_ant.tx != 1) {
1032 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1033 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1034 }
1035
1036 /* Turn on unused PA or LNA when not using 1T or 1R */
1037 if (rt2x00dev->default_ant.rx != 1) {
1038 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1039 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1040 }
1041
1042 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1043 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1044 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1045 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1046 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1047 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1048
1049 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1050
1051 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1052 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1053 rt2800_bbp_write(rt2x00dev, 4, bbp);
1054
1055 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1056 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1057 rt2800_bbp_write(rt2x00dev, 3, bbp);
1058
8d0c9b65 1059 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1060 if (conf_is_ht40(conf)) {
1061 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1062 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1063 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1064 } else {
1065 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1066 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1067 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1068 }
1069 }
1070
1071 msleep(1);
1072}
1073
1074static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1075 const int txpower)
1076{
1077 u32 reg;
1078 u32 value = TXPOWER_G_TO_DEV(txpower);
1079 u8 r1;
1080
1081 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1082 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1083 rt2800_bbp_write(rt2x00dev, 1, r1);
1084
1085 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1086 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1087 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1088 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1089 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1090 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1091 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1092 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1093 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1094 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1095
1096 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1097 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1098 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1099 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1100 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1101 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1102 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1103 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1104 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1105 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1106
1107 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1108 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1109 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1110 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1111 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1112 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1113 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1114 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1115 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1116 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1117
1118 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1119 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1120 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1121 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1122 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1123 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1124 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1125 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1126 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1127 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1128
1129 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1130 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1131 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1132 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1133 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1134 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1135}
1136
1137static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1138 struct rt2x00lib_conf *libconf)
1139{
1140 u32 reg;
1141
1142 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1143 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1144 libconf->conf->short_frame_max_tx_count);
1145 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1146 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1147 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1148}
1149
1150static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1151 struct rt2x00lib_conf *libconf)
1152{
1153 enum dev_state state =
1154 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1155 STATE_SLEEP : STATE_AWAKE;
1156 u32 reg;
1157
1158 if (state == STATE_SLEEP) {
1159 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1160
1161 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1162 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1163 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1164 libconf->conf->listen_interval - 1);
1165 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1166 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1167
1168 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1169 } else {
f4450616
BZ		 1170 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1171 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1172 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1173 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1174 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1175
1176 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1177 }
1178}
1179
1180void rt2800_config(struct rt2x00_dev *rt2x00dev,
1181 struct rt2x00lib_conf *libconf,
1182 const unsigned int flags)
1183{
1184 /* Always recalculate LNA gain before changing configuration */
1185 rt2800_config_lna_gain(rt2x00dev, libconf);
1186
1187 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1188 rt2800_config_channel(rt2x00dev, libconf->conf,
1189 &libconf->rf, &libconf->channel);
1190 if (flags & IEEE80211_CONF_CHANGE_POWER)
1191 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1192 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1193 rt2800_config_retry_limit(rt2x00dev, libconf);
1194 if (flags & IEEE80211_CONF_CHANGE_PS)
1195 rt2800_config_ps(rt2x00dev, libconf);
1196}
1197EXPORT_SYMBOL_GPL(rt2800_config);
1198
1199/*
1200 * Link tuning
1201 */
1202void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1203{
1204 u32 reg;
1205
1206 /*
1207 * Update FCS error count from register.
1208 */
1209 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1210 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1211}
1212EXPORT_SYMBOL_GPL(rt2800_link_stats);
1213
1214static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1215{
1216 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1217 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1218 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1219 rt2x00_rt(rt2x00dev, RT3090) ||
1220 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1221 return 0x1c + (2 * rt2x00dev->lna_gain);
1222 else
1223 return 0x2e + rt2x00dev->lna_gain;
1224 }
1225
1226 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1227 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1228 else
1229 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1230}
1231
1232static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1233 struct link_qual *qual, u8 vgc_level)
1234{
1235 if (qual->vgc_level != vgc_level) {
1236 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1237 qual->vgc_level = vgc_level;
1238 qual->vgc_level_reg = vgc_level;
1239 }
1240}
1241
1242void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1243{
1244 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1245}
1246EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1247
1248void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1249 const u32 count)
1250{
8d0c9b65 1251 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1252 return;
1253
1254 /*
1255 * When RSSI is better then -80 increase VGC level with 0x10
1256 */
1257 rt2800_set_vgc(rt2x00dev, qual,
1258 rt2800_get_default_vgc(rt2x00dev) +
1259 ((qual->rssi > -80) * 0x10));
1260}
1261EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1262
1263/*
1264 * Initialization functions.
1265 */
1266int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1267{
1268 u32 reg;
d5385bfc 1269 u16 eeprom;
fcf51541 1270 unsigned int i;
e3a896b9 1271 int ret;
fcf51541 1272
a9dce149
GW		 1273 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1274 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1275 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1279 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1280
e3a896b9
GW		 1281 ret = rt2800_drv_init_registers(rt2x00dev);
1282 if (ret)
1283 return ret;
fcf51541
BZ		 1284
1285 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1286 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1287 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1288 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1289 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1290 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1291
1292 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1293 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1294 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1295 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1296 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1297 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1298
1299 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1300 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1301
1302 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1303
1304 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1305 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1306 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1307 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1308 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1309 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1310 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1311 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1312
a9dce149
GW		 1313 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1314
1315 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1316 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1317 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1318 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1319
64522957 1320 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1321 rt2x00_rt(rt2x00dev, RT3090) ||
1322 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1323 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1324 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1325 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1326 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1327 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1328 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1329 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1330 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1331 0x0000002c);
1332 else
1333 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1334 0x0000000f);
1335 } else {
1336 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1337 }
d5385bfc 1338 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1339 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1340
1341 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1342 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1343 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1344 } else {
1345 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1346 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1347 }
c295a81d
HS		 1348 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1349 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1350 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1351 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1352 } else {
1353 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1354 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1355 }
1356
1357 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1358 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1359 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1360 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1361 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1362 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1363 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1364 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1365 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1366 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1367
1368 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1369 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1370 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1371 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1372 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1373
1374 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1375 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1376 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1377 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1378 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1379 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1380 else
1381 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1382 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1383 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1384 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1385
a9dce149
GW		 1386 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1387 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1388 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1389 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1390 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1391 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1392 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1393 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1394 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1395
fcf51541
BZ		 1396 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1397
a9dce149
GW		 1398 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1399 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1400 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1401 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1402 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1403 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1404 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1405 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1406
fcf51541
BZ		 1407 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1408 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1409 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1410 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1411 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1412 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1413 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1414 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1415 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1416
1417 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1418 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1419 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1420 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1421 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1422 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1423 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1424 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1425 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1426 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1427 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1428 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1429
1430 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1431 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1432 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1433 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1434 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1435 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1436 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1437 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1438 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1439 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1440 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1441 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1442
1443 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1444 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1445 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1446 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1447 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1448 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1449 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1450 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1451 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1452 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1453 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1454 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1455
1456 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1457 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1458 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1459 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1460 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1461 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1462 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1463 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1464 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1465 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1466 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1467 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1468 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1469
1470 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1471 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1472 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1473 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1474 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1475 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1476 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1477 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1478 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1479 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1480 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1481 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1482
1483 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1484 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1485 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1486 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1487 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1488 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1489 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1490 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1491 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1492 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1493 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1494 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1495
cea90e55 1496 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1497 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1498
1499 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1500 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1501 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1502 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1503 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1504 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1505 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1506 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1507 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1508 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1509 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1510 }
1511
1512 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1513 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1514
1515 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1516 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1517 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1518 IEEE80211_MAX_RTS_THRESHOLD);
1519 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1520 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1521
1522 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1523
a21c2ab4
HS		 1524 /*
1525 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1526 * time should be set to 16. However, the original Ralink driver uses
1527 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1528 * connection problems with 11g + CTS protection. Hence, use the same
1529 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1530 */
a9dce149 1531 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1532 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1533 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1534 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1535 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1536 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1537 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1538
fcf51541
BZ		 1539 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1540
1541 /*
1542 * ASIC will keep garbage value after boot, clear encryption keys.
1543 */
1544 for (i = 0; i < 4; i++)
1545 rt2800_register_write(rt2x00dev,
1546 SHARED_KEY_MODE_ENTRY(i), 0);
1547
1548 for (i = 0; i < 256; i++) {
1549 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1550 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1551 wcid, sizeof(wcid));
1552
1553 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1554 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1555 }
1556
1557 /*
1558 * Clear all beacons
1559 * For the Beacon base registers we only need to clear
1560 * the first byte since that byte contains the VALID and OWNER
1561 * bits which (when set to 0) will invalidate the entire beacon.
1562 */
1563 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1564 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1565 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1566 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1567 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1568 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1569 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1570 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1571
cea90e55 1572 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 1573 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1574 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1575 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 1576 }
1577
1578 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1579 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1580 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1581 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1582 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1583 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1584 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1585 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1586 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1587 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1588
1589 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1590 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1591 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1592 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1593 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1594 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1595 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1596 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1597 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1598 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1599
1600 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1601 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1602 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1603 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1604 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1605 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1606 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1607 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1608 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1609 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1610
1611 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1612 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1613 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1614 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1615 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1616 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1617
1618 /*
1619 * We must clear the error counters.
1620 * These registers are cleared on read,
1621 * so we may pass a useless variable to store the value.
1622 */
1623 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1624 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1625 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1626 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1627 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1628 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1629
1630 return 0;
1631}
1632EXPORT_SYMBOL_GPL(rt2800_init_registers);
1633
1634static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1635{
1636 unsigned int i;
1637 u32 reg;
1638
1639 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1640 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1641 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1642 return 0;
1643
1644 udelay(REGISTER_BUSY_DELAY);
1645 }
1646
1647 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1648 return -EACCES;
1649}
1650
1651static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1652{
1653 unsigned int i;
1654 u8 value;
1655
1656 /*
1657 * BBP was enabled after firmware was loaded,
1658 * but we need to reactivate it now.
1659 */
1660 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1661 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1662 msleep(1);
1663
1664 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1665 rt2800_bbp_read(rt2x00dev, 0, &value);
1666 if ((value != 0xff) && (value != 0x00))
1667 return 0;
1668 udelay(REGISTER_BUSY_DELAY);
1669 }
1670
1671 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1672 return -EACCES;
1673}
1674
1675int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1676{
1677 unsigned int i;
1678 u16 eeprom;
1679 u8 reg_id;
1680 u8 value;
1681
1682 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1683 rt2800_wait_bbp_ready(rt2x00dev)))
1684 return -EACCES;
1685
baff8006
HS		 1686 if (rt2800_is_305x_soc(rt2x00dev))
1687 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1688
fcf51541
BZ		 1689 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1690 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1691
1692 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1693 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1694 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1695 } else {
1696 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1697 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1698 }
1699
fcf51541 1700 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1701
d5385bfc 1702 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1703 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1704 rt2x00_rt(rt2x00dev, RT3090) ||
1705 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1706 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1707 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1708 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1709 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1710 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1711 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1712 } else {
1713 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1714 }
1715
fcf51541
BZ		 1716 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1717 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 1718
5ed8f458 1719 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 1720 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1721 else
1722 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1723
fcf51541
BZ		 1724 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1725 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1726 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1727
d5385bfc 1728 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1729 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 1730 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 1731 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1732 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 1733 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1734 else
1735 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1736
baff8006
HS		 1737 if (rt2800_is_305x_soc(rt2x00dev))
1738 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1739 else
1740 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1741 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1742
64522957 1743 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1744 rt2x00_rt(rt2x00dev, RT3090) ||
1745 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 1746 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 1747
d5385bfc
GW		 1748 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1749 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1750 value |= 0x20;
1751 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1752 value &= ~0x02;
fcf51541 1753
d5385bfc 1754 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 1755 }
1756
fcf51541
BZ		 1757
1758 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1759 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1760
1761 if (eeprom != 0xffff && eeprom != 0x0000) {
1762 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1763 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1764 rt2800_bbp_write(rt2x00dev, reg_id, value);
1765 }
1766 }
1767
1768 return 0;
1769}
1770EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1771
1772static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1773 bool bw40, u8 rfcsr24, u8 filter_target)
1774{
1775 unsigned int i;
1776 u8 bbp;
1777 u8 rfcsr;
1778 u8 passband;
1779 u8 stopband;
1780 u8 overtuned = 0;
1781
1782 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1783
1784 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1785 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1786 rt2800_bbp_write(rt2x00dev, 4, bbp);
1787
1788 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1789 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1790 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1791
1792 /*
1793 * Set power & frequency of passband test tone
1794 */
1795 rt2800_bbp_write(rt2x00dev, 24, 0);
1796
1797 for (i = 0; i < 100; i++) {
1798 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1799 msleep(1);
1800
1801 rt2800_bbp_read(rt2x00dev, 55, &passband);
1802 if (passband)
1803 break;
1804 }
1805
1806 /*
1807 * Set power & frequency of stopband test tone
1808 */
1809 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1810
1811 for (i = 0; i < 100; i++) {
1812 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1813 msleep(1);
1814
1815 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1816
1817 if ((passband - stopband) <= filter_target) {
1818 rfcsr24++;
1819 overtuned += ((passband - stopband) == filter_target);
1820 } else
1821 break;
1822
1823 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1824 }
1825
1826 rfcsr24 -= !!overtuned;
1827
1828 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1829 return rfcsr24;
1830}
1831
1832int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1833{
1834 u8 rfcsr;
1835 u8 bbp;
8cdd15e0
GW		 1836 u32 reg;
1837 u16 eeprom;
fcf51541 1838
d5385bfc 1839 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1840 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1841 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 1842 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 1843 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 1844 return 0;
1845
fcf51541
BZ		 1846 /*
1847 * Init RF calibration.
1848 */
1849 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1850 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1851 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1852 msleep(1);
1853 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1854 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1855
d5385bfc 1856 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1857 rt2x00_rt(rt2x00dev, RT3071) ||
1858 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1859 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1860 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1861 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1862 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1863 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1864 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1865 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1866 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1867 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1868 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1869 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1870 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1871 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1872 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1873 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1874 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1875 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1876 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1877 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1878 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1879 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1880 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1881 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1882 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 1883 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 1884 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1885 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1886 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1887 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1888 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1889 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 1890 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 1891 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1892 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 1893 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 1894 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1895 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1896 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1897 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1898 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1899 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1900 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 1901 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 1902 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 1903 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 1904 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1905 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1906 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1907 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1908 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1909 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1910 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 1911 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 1912 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1913 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1914 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1915 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1916 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1917 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1918 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1919 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1920 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1921 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1922 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1923 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1924 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1925 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1926 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1927 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1928 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1929 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1930 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1931 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1932 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1933 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1934 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1935 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1936 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1937 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1938 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1939 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1940 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1941 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 1942 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1943 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1944 return 0;
8cdd15e0
GW		 1945 }
1946
1947 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1948 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1949 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1950 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1951 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 1952 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1953 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 1954 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1955 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1956 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1957
1958 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1959
1960 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1961 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 1962 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1963 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 1964 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1965 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1966 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1967 else
1968 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1969 }
1970 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 1971 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1972 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1973 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1974 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 1975 }
1976
1977 /*
1978 * Set RX Filter calibration for 20MHz and 40MHz
1979 */
8cdd15e0
GW		 1980 if (rt2x00_rt(rt2x00dev, RT3070)) {
1981 rt2x00dev->calibration[0] =
1982 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1983 rt2x00dev->calibration[1] =
1984 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 1985 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1986 rt2x00_rt(rt2x00dev, RT3090) ||
1987 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1988 rt2x00dev->calibration[0] =
1989 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1990 rt2x00dev->calibration[1] =
1991 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 1992 }
fcf51541
BZ		 1993
1994 /*
1995 * Set back to initial state
1996 */
1997 rt2800_bbp_write(rt2x00dev, 24, 0);
1998
1999 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2000 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2001 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2002
2003 /*
2004 * set BBP back to BW20
2005 */
2006 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2007 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2008 rt2800_bbp_write(rt2x00dev, 4, bbp);
2009
d5385bfc 2010 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2011 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2012 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2013 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2014 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2015
2016 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2017 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2018 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2019
2020 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2021 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2022 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2023 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2024 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2025 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2026 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2027 }
8cdd15e0
GW		 2028 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2029 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2030 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2031 rt2x00_get_field16(eeprom,
2032 EEPROM_TXMIXER_GAIN_BG_VAL));
2033 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2034
64522957
GW		 2035 if (rt2x00_rt(rt2x00dev, RT3090)) {
2036 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2037
2038 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2039 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2040 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2041 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2042 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2043
2044 rt2800_bbp_write(rt2x00dev, 138, bbp);
2045 }
2046
2047 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2048 rt2x00_rt(rt2x00dev, RT3090) ||
2049 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2050 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2051 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2052 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2053 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2054 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2055 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2056 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2057
2058 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2059 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2060 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2061
2062 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2063 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2064 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2065
2066 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2067 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2068 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2069 }
2070
2071 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2072 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2073 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2074 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2075 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2076 else
2077 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2078 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2079 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2080 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2081 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2082 }
2083
fcf51541
BZ		 2084 return 0;
2085}
2086EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 2087
30e84034
BZ		 2088int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2089{
2090 u32 reg;
2091
2092 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2093
2094 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2095}
2096EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2097
2098static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2099{
2100 u32 reg;
2101
31a4cf1f
GW		 2102 mutex_lock(&rt2x00dev->csr_mutex);
2103
2104 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2105 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2106 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2107 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2108 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2109
2110 /* Wait until the EEPROM has been loaded */
2111 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2112
2113 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2114 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2115 (u32 *)&rt2x00dev->eeprom[i]);
2116 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2117 (u32 *)&rt2x00dev->eeprom[i + 2]);
2118 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2119 (u32 *)&rt2x00dev->eeprom[i + 4]);
2120 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2121 (u32 *)&rt2x00dev->eeprom[i + 6]);
2122
2123 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2124}
2125
2126void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2127{
2128 unsigned int i;
2129
2130 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2131 rt2800_efuse_read(rt2x00dev, i);
2132}
2133EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2134
38bd7b8a
BZ		 2135int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2136{
2137 u16 word;
2138 u8 *mac;
2139 u8 default_lna_gain;
2140
2141 /*
2142 * Start validation of the data that has been read.
2143 */
2144 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2145 if (!is_valid_ether_addr(mac)) {
2146 random_ether_addr(mac);
2147 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2148 }
2149
2150 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2151 if (word == 0xffff) {
2152 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2153 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2154 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2155 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2156 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2157 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2158 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2159 /*
2160 * There is a max of 2 RX streams for RT28x0 series
2161 */
2162 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2163 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2164 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2165 }
2166
2167 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2168 if (word == 0xffff) {
2169 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2170 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2171 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2172 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2173 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2174 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2175 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2176 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2177 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2178 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2179 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2180 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2181 }
2182
2183 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2184 if ((word & 0x00ff) == 0x00ff) {
2185 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2186 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2187 LED_MODE_TXRX_ACTIVITY);
2188 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2189 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2190 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2191 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2192 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2193 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2194 }
2195
2196 /*
2197 * During the LNA validation we are going to use
2198 * lna0 as correct value. Note that EEPROM_LNA
2199 * is never validated.
2200 */
2201 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2202 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2203
2204 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2205 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2206 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2207 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2208 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2209 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2210
2211 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2212 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2213 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2214 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2215 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2216 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2217 default_lna_gain);
2218 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2219
2220 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2221 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2222 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2223 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2224 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2225 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2226
2227 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2228 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2229 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2230 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2231 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2232 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2233 default_lna_gain);
2234 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2235
2236 return 0;
2237}
2238EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2239
2240int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2241{
2242 u32 reg;
2243 u16 value;
2244 u16 eeprom;
2245
2246 /*
2247 * Read EEPROM word for configuration.
2248 */
2249 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2250
2251 /*
2252 * Identify RF chipset.
2253 */
2254 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2255 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2256
49e721ec
GW		 2257 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2258 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2259
2260 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2261 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2262 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2263 !rt2x00_rt(rt2x00dev, RT3070) &&
2264 !rt2x00_rt(rt2x00dev, RT3071) &&
2265 !rt2x00_rt(rt2x00dev, RT3090) &&
2266 !rt2x00_rt(rt2x00dev, RT3390) &&
2267 !rt2x00_rt(rt2x00dev, RT3572)) {
2268 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2269 return -ENODEV;
f273fe55 2270 }
714fa663 2271
5122d898
GW		 2272 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2273 !rt2x00_rf(rt2x00dev, RF2850) &&
2274 !rt2x00_rf(rt2x00dev, RF2720) &&
2275 !rt2x00_rf(rt2x00dev, RF2750) &&
2276 !rt2x00_rf(rt2x00dev, RF3020) &&
2277 !rt2x00_rf(rt2x00dev, RF2020) &&
2278 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2279 !rt2x00_rf(rt2x00dev, RF3022) &&
2280 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2281 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2282 return -ENODEV;
2283 }
2284
2285 /*
2286 * Identify default antenna configuration.
2287 */
2288 rt2x00dev->default_ant.tx =
2289 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2290 rt2x00dev->default_ant.rx =
2291 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2292
2293 /*
2294 * Read frequency offset and RF programming sequence.
2295 */
2296 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2297 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2298
2299 /*
2300 * Read external LNA informations.
2301 */
2302 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2303
2304 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2305 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2306 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2307 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2308
2309 /*
2310 * Detect if this device has an hardware controlled radio.
2311 */
2312 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2313 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2314
2315 /*
2316 * Store led settings, for correct led behaviour.
2317 */
2318#ifdef CONFIG_RT2X00_LIB_LEDS
2319 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2320 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2321 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2322
2323 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2324#endif /* CONFIG_RT2X00_LIB_LEDS */
2325
2326 return 0;
2327}
2328EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2329
4da2933f 2330/*
55f9321a 2331 * RF value list for rt28xx
4da2933f
BZ		 2332 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2333 */
2334static const struct rf_channel rf_vals[] = {
2335 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2336 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2337 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2338 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2339 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2340 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2341 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2342 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2343 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2344 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2345 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2346 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2347 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2348 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2349
2350 /* 802.11 UNI / HyperLan 2 */
2351 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2352 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2353 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2354 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2355 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2356 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2357 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2358 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2359 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2360 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2361 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2362 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2363
2364 /* 802.11 HyperLan 2 */
2365 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2366 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2367 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2368 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2369 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2370 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2371 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2372 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2373 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2374 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2375 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2376 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2377 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2378 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2379 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2380 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2381
2382 /* 802.11 UNII */
2383 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2384 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2385 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2386 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2387 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2388 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2389 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2390 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2391 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2392 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2393 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2394
2395 /* 802.11 Japan */
2396 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2397 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2398 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2399 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2400 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2401 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2402 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2403};
2404
2405/*
55f9321a
ID		 2406 * RF value list for rt3xxx
2407 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2408 */
55f9321a 2409static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2410 {1, 241, 2, 2 },
2411 {2, 241, 2, 7 },
2412 {3, 242, 2, 2 },
2413 {4, 242, 2, 7 },
2414 {5, 243, 2, 2 },
2415 {6, 243, 2, 7 },
2416 {7, 244, 2, 2 },
2417 {8, 244, 2, 7 },
2418 {9, 245, 2, 2 },
2419 {10, 245, 2, 7 },
2420 {11, 246, 2, 2 },
2421 {12, 246, 2, 7 },
2422 {13, 247, 2, 2 },
2423 {14, 248, 2, 4 },
55f9321a
ID		 2424
2425 /* 802.11 UNI / HyperLan 2 */
2426 {36, 0x56, 0, 4},
2427 {38, 0x56, 0, 6},
2428 {40, 0x56, 0, 8},
2429 {44, 0x57, 0, 0},
2430 {46, 0x57, 0, 2},
2431 {48, 0x57, 0, 4},
2432 {52, 0x57, 0, 8},
2433 {54, 0x57, 0, 10},
2434 {56, 0x58, 0, 0},
2435 {60, 0x58, 0, 4},
2436 {62, 0x58, 0, 6},
2437 {64, 0x58, 0, 8},
2438
2439 /* 802.11 HyperLan 2 */
2440 {100, 0x5b, 0, 8},
2441 {102, 0x5b, 0, 10},
2442 {104, 0x5c, 0, 0},
2443 {108, 0x5c, 0, 4},
2444 {110, 0x5c, 0, 6},
2445 {112, 0x5c, 0, 8},
2446 {116, 0x5d, 0, 0},
2447 {118, 0x5d, 0, 2},
2448 {120, 0x5d, 0, 4},
2449 {124, 0x5d, 0, 8},
2450 {126, 0x5d, 0, 10},
2451 {128, 0x5e, 0, 0},
2452 {132, 0x5e, 0, 4},
2453 {134, 0x5e, 0, 6},
2454 {136, 0x5e, 0, 8},
2455 {140, 0x5f, 0, 0},
2456
2457 /* 802.11 UNII */
2458 {149, 0x5f, 0, 9},
2459 {151, 0x5f, 0, 11},
2460 {153, 0x60, 0, 1},
2461 {157, 0x60, 0, 5},
2462 {159, 0x60, 0, 7},
2463 {161, 0x60, 0, 9},
2464 {165, 0x61, 0, 1},
2465 {167, 0x61, 0, 3},
2466 {169, 0x61, 0, 5},
2467 {171, 0x61, 0, 7},
2468 {173, 0x61, 0, 9},
4da2933f
BZ		 2469};
2470
2471int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2472{
4da2933f
BZ		 2473 struct hw_mode_spec *spec = &rt2x00dev->spec;
2474 struct channel_info *info;
2475 char *tx_power1;
2476 char *tx_power2;
2477 unsigned int i;
2478 u16 eeprom;
2479
93b6bd26
GW		 2480 /*
2481 * Disable powersaving as default on PCI devices.
2482 */
cea90e55 2483 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2484 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2485
4da2933f
BZ		 2486 /*
2487 * Initialize all hw fields.
2488 */
2489 rt2x00dev->hw->flags =
2490 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2491 IEEE80211_HW_SIGNAL_DBM |
2492 IEEE80211_HW_SUPPORTS_PS |
2493 IEEE80211_HW_PS_NULLFUNC_STACK;
2494
4da2933f
BZ		 2495 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2496 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2497 rt2x00_eeprom_addr(rt2x00dev,
2498 EEPROM_MAC_ADDR_0));
2499
3f2bee24
HS		 2500 /*
2501 * As rt2800 has a global fallback table we cannot specify
2502 * more then one tx rate per frame but since the hw will
2503 * try several rates (based on the fallback table) we should
2504 * still initialize max_rates to the maximum number of rates
2505 * we are going to try. Otherwise mac80211 will truncate our
2506 * reported tx rates and the rc algortihm will end up with
2507 * incorrect data.
2508 */
2509 rt2x00dev->hw->max_rates = 7;
2510 rt2x00dev->hw->max_rate_tries = 1;
2511
4da2933f
BZ		 2512 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2513
2514 /*
2515 * Initialize hw_mode information.
2516 */
2517 spec->supported_bands = SUPPORT_BAND_2GHZ;
2518 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2519
5122d898 2520 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 2521 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 2522 spec->num_channels = 14;
2523 spec->channels = rf_vals;
55f9321a
ID		 2524 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2525 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2526 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2527 spec->num_channels = ARRAY_SIZE(rf_vals);
2528 spec->channels = rf_vals;
5122d898
GW		 2529 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2530 rt2x00_rf(rt2x00dev, RF2020) ||
2531 rt2x00_rf(rt2x00dev, RF3021) ||
2532 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 2533 spec->num_channels = 14;
2534 spec->channels = rf_vals_3x;
2535 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2536 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2537 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2538 spec->channels = rf_vals_3x;
4da2933f
BZ		 2539 }
2540
2541 /*
2542 * Initialize HT information.
2543 */
5122d898 2544 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2545 spec->ht.ht_supported = true;
2546 else
2547 spec->ht.ht_supported = false;
2548
4da2933f 2549 spec->ht.cap =
06443e46 2550 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 2551 IEEE80211_HT_CAP_GRN_FLD |
2552 IEEE80211_HT_CAP_SGI_20 |
2553 IEEE80211_HT_CAP_SGI_40 |
9a418af5 2554 IEEE80211_HT_CAP_RX_STBC;
22cabaa6
HS		 2555
2556 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2557 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2558
4da2933f
BZ		 2559 spec->ht.ampdu_factor = 3;
2560 spec->ht.ampdu_density = 4;
2561 spec->ht.mcs.tx_params =
2562 IEEE80211_HT_MCS_TX_DEFINED |
2563 IEEE80211_HT_MCS_TX_RX_DIFF |
2564 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2565 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2566
2567 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2568 case 3:
2569 spec->ht.mcs.rx_mask[2] = 0xff;
2570 case 2:
2571 spec->ht.mcs.rx_mask[1] = 0xff;
2572 case 1:
2573 spec->ht.mcs.rx_mask[0] = 0xff;
2574 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2575 break;
2576 }
2577
2578 /*
2579 * Create channel information array
2580 */
2581 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2582 if (!info)
2583 return -ENOMEM;
2584
2585 spec->channels_info = info;
2586
2587 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2588 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2589
2590 for (i = 0; i < 14; i++) {
2591 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2592 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2593 }
2594
2595 if (spec->num_channels > 14) {
2596 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2597 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2598
2599 for (i = 14; i < spec->num_channels; i++) {
2600 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2601 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2602 }
2603 }
2604
2605 return 0;
2606}
2607EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2608
2ce33995
BZ		 2609/*
2610 * IEEE80211 stack callback functions.
2611 */
2612static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2613 u32 *iv32, u16 *iv16)
2614{
2615 struct rt2x00_dev *rt2x00dev = hw->priv;
2616 struct mac_iveiv_entry iveiv_entry;
2617 u32 offset;
2618
2619 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2620 rt2800_register_multiread(rt2x00dev, offset,
2621 &iveiv_entry, sizeof(iveiv_entry));
2622
855da5e0
JL		 2623 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2624 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2625}
2626
2627static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2628{
2629 struct rt2x00_dev *rt2x00dev = hw->priv;
2630 u32 reg;
2631 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2632
2633 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2634 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2635 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2636
2637 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2638 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2639 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2640
2641 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2642 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2643 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2644
2645 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2646 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2647 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2648
2649 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2650 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2651 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2652
2653 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2654 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2655 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2656
2657 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2658 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2659 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2660
2661 return 0;
2662}
2663
2664static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2665 const struct ieee80211_tx_queue_params *params)
2666{
2667 struct rt2x00_dev *rt2x00dev = hw->priv;
2668 struct data_queue *queue;
2669 struct rt2x00_field32 field;
2670 int retval;
2671 u32 reg;
2672 u32 offset;
2673
2674 /*
2675 * First pass the configuration through rt2x00lib, that will
2676 * update the queue settings and validate the input. After that
2677 * we are free to update the registers based on the value
2678 * in the queue parameter.
2679 */
2680 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2681 if (retval)
2682 return retval;
2683
2684 /*
2685 * We only need to perform additional register initialization
2686 * for WMM queues/
2687 */
2688 if (queue_idx >= 4)
2689 return 0;
2690
2691 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2692
2693 /* Update WMM TXOP register */
2694 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2695 field.bit_offset = (queue_idx & 1) * 16;
2696 field.bit_mask = 0xffff << field.bit_offset;
2697
2698 rt2800_register_read(rt2x00dev, offset, &reg);
2699 rt2x00_set_field32(&reg, field, queue->txop);
2700 rt2800_register_write(rt2x00dev, offset, reg);
2701
2702 /* Update WMM registers */
2703 field.bit_offset = queue_idx * 4;
2704 field.bit_mask = 0xf << field.bit_offset;
2705
2706 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2707 rt2x00_set_field32(&reg, field, queue->aifs);
2708 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2709
2710 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2711 rt2x00_set_field32(&reg, field, queue->cw_min);
2712 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2713
2714 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2715 rt2x00_set_field32(&reg, field, queue->cw_max);
2716 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2717
2718 /* Update EDCA registers */
2719 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2720
2721 rt2800_register_read(rt2x00dev, offset, &reg);
2722 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2723 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2724 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2725 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2726 rt2800_register_write(rt2x00dev, offset, reg);
2727
2728 return 0;
2729}
2730
2731static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2732{
2733 struct rt2x00_dev *rt2x00dev = hw->priv;
2734 u64 tsf;
2735 u32 reg;
2736
2737 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2738 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2739 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2740 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2741
2742 return tsf;
2743}
2744
2745const struct ieee80211_ops rt2800_mac80211_ops = {
2746 .tx = rt2x00mac_tx,
2747 .start = rt2x00mac_start,
2748 .stop = rt2x00mac_stop,
2749 .add_interface = rt2x00mac_add_interface,
2750 .remove_interface = rt2x00mac_remove_interface,
2751 .config = rt2x00mac_config,
2752 .configure_filter = rt2x00mac_configure_filter,
2753 .set_tim = rt2x00mac_set_tim,
2754 .set_key = rt2x00mac_set_key,
2755 .get_stats = rt2x00mac_get_stats,
2756 .get_tkip_seq = rt2800_get_tkip_seq,
2757 .set_rts_threshold = rt2800_set_rts_threshold,
2758 .bss_info_changed = rt2x00mac_bss_info_changed,
2759 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2760 .get_tsf = rt2800_get_tsf,
2761 .rfkill_poll = rt2x00mac_rfkill_poll,
2762};
2763EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
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