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rt2800: introduce wpdma_disable function
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
f31c9a8c 37#include <linux/crc-ccitt.h>
89297425
BZ		 38#include <linux/kernel.h>
39#include <linux/module.h>
5a0e3ad6 40#include <linux/slab.h>
89297425
BZ		 41
42#include "rt2x00.h"
43#include "rt2800lib.h"
44#include "rt2800.h"
45
89297425
BZ		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
baff8006
HS		 70static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71{
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85}
86
fcf51541
BZ		 87static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89297425
BZ		 89{
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
89297425 111
fcf51541
BZ		 112static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
89297425
BZ		 114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
5ffddc49
ID		 258int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i = 0;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265 if (reg && reg != ~0)
266 return 0;
267 msleep(1);
268 }
269
270 ERROR(rt2x00dev, "Unstable hardware.\n");
271 return -EBUSY;
272}
273EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
67a4c1e2
GW		 275int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276{
277 unsigned int i;
278 u32 reg;
279
08e53100
HS		 280 /*
281 * Some devices are really slow to respond here. Wait a whole second
282 * before timing out.
283 */
67a4c1e2
GW		 284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288 return 0;
289
08e53100 290 msleep(10);
67a4c1e2
GW		 291 }
292
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294 return -EACCES;
295}
296EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
f7b395e9
JK		 298void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
299{
300 u32 reg;
301
302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
303 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
306 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
307 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
309}
310EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
311
f31c9a8c
ID		 312static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
313{
314 u16 fw_crc;
315 u16 crc;
316
317 /*
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
320 * algorithm.
321 */
322 fw_crc = (data[len - 2] << 8 | data[len - 1]);
323
324 /*
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
330 */
331 crc = crc_ccitt(~0, data, len - 2);
332
333 /*
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
337 * value.
338 */
339 crc = swab16(crc);
340
341 return fw_crc == crc;
342}
343
344int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
345 const u8 *data, const size_t len)
346{
347 size_t offset = 0;
348 size_t fw_len;
349 bool multiple;
350
351 /*
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb.
358 */
359 if (rt2x00_is_usb(rt2x00dev)) {
360 fw_len = 4096;
361 multiple = true;
362 } else {
363 fw_len = 8192;
364 multiple = true;
365 }
366
367 /*
368 * Validate the firmware length
369 */
370 if (len != fw_len && (!multiple || (len % fw_len) != 0))
371 return FW_BAD_LENGTH;
372
373 /*
374 * Check if the chipset requires one of the upper parts
375 * of the firmware.
376 */
377 if (rt2x00_is_usb(rt2x00dev) &&
378 !rt2x00_rt(rt2x00dev, RT2860) &&
379 !rt2x00_rt(rt2x00dev, RT2872) &&
380 !rt2x00_rt(rt2x00dev, RT3070) &&
381 ((len / fw_len) == 1))
382 return FW_BAD_VERSION;
383
384 /*
385 * 8kb firmware files must be checked as if it were
386 * 2 separate firmware files.
387 */
388 while (offset < len) {
389 if (!rt2800_check_firmware_crc(data + offset, fw_len))
390 return FW_BAD_CRC;
391
392 offset += fw_len;
393 }
394
395 return FW_OK;
396}
397EXPORT_SYMBOL_GPL(rt2800_check_firmware);
398
399int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 const u8 *data, const size_t len)
401{
402 unsigned int i;
403 u32 reg;
404
405 /*
b9eca242
ID		 406 * If driver doesn't wake up firmware here,
407 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 408 */
b9eca242 409 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 410
f31c9a8c
ID		 411 /*
412 * Wait for stable hardware.
413 */
5ffddc49 414 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 415 return -EBUSY;
f31c9a8c 416
adde5882 417 if (rt2x00_is_pci(rt2x00dev)) {
872834df 418 if (rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
422 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
423 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
424 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
425 }
f31c9a8c 426 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 427 }
f31c9a8c 428
f31c9a8c
ID		 429 /*
430 * Write firmware to the device.
431 */
432 rt2800_drv_write_firmware(rt2x00dev, data, len);
433
434 /*
435 * Wait for device to stabilize.
436 */
437 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
438 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
439 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
440 break;
441 msleep(1);
442 }
443
444 if (i == REGISTER_BUSY_COUNT) {
445 ERROR(rt2x00dev, "PBF system register not ready.\n");
446 return -EBUSY;
447 }
448
4ed1dd2a
SG		 449 /*
450 * Disable DMA, will be reenabled later when enabling
451 * the radio.
452 */
f7b395e9 453 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 454
f31c9a8c
ID		 455 /*
456 * Initialize firmware.
457 */
458 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
459 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
0c17cf96
SG		 460 if (rt2x00_is_usb(rt2x00dev))
461 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f31c9a8c
ID		 462 msleep(1);
463
464 return 0;
465}
466EXPORT_SYMBOL_GPL(rt2800_load_firmware);
467
0c5879bc
ID		 468void rt2800_write_tx_data(struct queue_entry *entry,
469 struct txentry_desc *txdesc)
59679b91 470{
0c5879bc 471 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91
GW		 472 u32 word;
473
474 /*
475 * Initialize TX Info descriptor
476 */
477 rt2x00_desc_read(txwi, 0, &word);
478 rt2x00_set_field32(&word, TXWI_W0_FRAG,
479 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 480 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
481 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 482 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
483 rt2x00_set_field32(&word, TXWI_W0_TS,
484 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
485 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
486 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 487 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
488 txdesc->u.ht.mpdu_density);
489 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
490 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 491 rt2x00_set_field32(&word, TXWI_W0_BW,
492 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
493 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
494 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 495 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 496 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
497 rt2x00_desc_write(txwi, 0, word);
498
499 rt2x00_desc_read(txwi, 1, &word);
500 rt2x00_set_field32(&word, TXWI_W1_ACK,
501 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
502 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
503 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 504 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 505 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
506 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 507 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 508 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
509 txdesc->length);
2b23cdaa 510 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 511 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 512 rt2x00_desc_write(txwi, 1, word);
513
514 /*
515 * Always write 0 to IV/EIV fields, hardware will insert the IV
516 * from the IVEIV register when TXD_W3_WIV is set to 0.
517 * When TXD_W3_WIV is set to 1 it will use the IV data
518 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
519 * crypto entry in the registers should be used to encrypt the frame.
520 */
521 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
522 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
523}
0c5879bc 524EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 525
ff6133be 526static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 527{
7fc41755
LT		 528 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
529 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
530 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 531 u16 eeprom;
532 u8 offset0;
533 u8 offset1;
534 u8 offset2;
535
e5ef5bad 536 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
74861922
ID		 537 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
538 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
539 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
540 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
541 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
542 } else {
543 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
544 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
545 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
546 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
547 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
548 }
549
550 /*
551 * Convert the value from the descriptor into the RSSI value
552 * If the value in the descriptor is 0, it is considered invalid
553 * and the default (extremely low) rssi value is assumed
554 */
555 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
556 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
557 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
558
559 /*
560 * mac80211 only accepts a single RSSI value. Calculating the
561 * average doesn't deliver a fair answer either since -60:-60 would
562 * be considered equally good as -50:-70 while the second is the one
563 * which gives less energy...
564 */
565 rssi0 = max(rssi0, rssi1);
7fc41755 566 return (int)max(rssi0, rssi2);
74861922
ID		 567}
568
569void rt2800_process_rxwi(struct queue_entry *entry,
570 struct rxdone_entry_desc *rxdesc)
571{
572 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 573 u32 word;
574
575 rt2x00_desc_read(rxwi, 0, &word);
576
577 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
578 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
579
580 rt2x00_desc_read(rxwi, 1, &word);
581
582 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
583 rxdesc->flags |= RX_FLAG_SHORT_GI;
584
585 if (rt2x00_get_field32(word, RXWI_W1_BW))
586 rxdesc->flags |= RX_FLAG_40MHZ;
587
588 /*
589 * Detect RX rate, always use MCS as signal type.
590 */
591 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
592 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
593 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
594
595 /*
596 * Mask of 0x8 bit to remove the short preamble flag.
597 */
598 if (rxdesc->rate_mode == RATE_MODE_CCK)
599 rxdesc->signal &= ~0x8;
600
601 rt2x00_desc_read(rxwi, 2, &word);
602
74861922
ID		 603 /*
604 * Convert descriptor AGC value to RSSI value.
605 */
606 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 607
608 /*
609 * Remove RXWI descriptor from start of buffer.
610 */
74861922 611 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 612}
613EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
614
31937c42 615void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 616{
617 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 618 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 619 struct txdone_entry_desc txdesc;
620 u32 word;
621 u16 mcs, real_mcs;
b34793ee 622 int aggr, ampdu;
14433331
HS		 623
624 /*
625 * Obtain the status about this packet.
626 */
627 txdesc.flags = 0;
14433331 628 rt2x00_desc_read(txwi, 0, &word);
b34793ee 629
14433331 630 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 631 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
632
14433331 633 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 634 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
635
636 /*
637 * If a frame was meant to be sent as a single non-aggregated MPDU
638 * but ended up in an aggregate the used tx rate doesn't correlate
639 * with the one specified in the TXWI as the whole aggregate is sent
640 * with the same rate.
641 *
642 * For example: two frames are sent to rt2x00, the first one sets
643 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
644 * and requests MCS15. If the hw aggregates both frames into one
645 * AMDPU the tx status for both frames will contain MCS7 although
646 * the frame was sent successfully.
647 *
648 * Hence, replace the requested rate with the real tx rate to not
649 * confuse the rate control algortihm by providing clearly wrong
650 * data.
651 */
5356d963 652 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 653 skbdesc->tx_rate_idx = real_mcs;
654 mcs = real_mcs;
655 }
14433331 656
f16d2db7
HS		 657 if (aggr == 1 || ampdu == 1)
658 __set_bit(TXDONE_AMPDU, &txdesc.flags);
659
14433331
HS		 660 /*
661 * Ralink has a retry mechanism using a global fallback
662 * table. We setup this fallback table to try the immediate
663 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
664 * always contains the MCS used for the last transmission, be
665 * it successful or not.
666 */
667 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
668 /*
669 * Transmission succeeded. The number of retries is
670 * mcs - real_mcs
671 */
672 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
673 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
674 } else {
675 /*
676 * Transmission failed. The number of retries is
677 * always 7 in this case (for a total number of 8
678 * frames sent).
679 */
680 __set_bit(TXDONE_FAILURE, &txdesc.flags);
681 txdesc.retry = rt2x00dev->long_retry;
682 }
683
684 /*
685 * the frame was retried at least once
686 * -> hw used fallback rates
687 */
688 if (txdesc.retry)
689 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
690
691 rt2x00lib_txdone(entry, &txdesc);
692}
693EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
694
f0194b2d
GW		 695void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
696{
697 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
698 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
699 unsigned int beacon_base;
739fd940 700 unsigned int padding_len;
d76dfc61 701 u32 orig_reg, reg;
f0194b2d
GW		 702
703 /*
704 * Disable beaconing while we are reloading the beacon data,
705 * otherwise we might be sending out invalid data.
706 */
707 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 708 orig_reg = reg;
f0194b2d
GW		 709 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
710 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
711
712 /*
713 * Add space for the TXWI in front of the skb.
714 */
b52398b6 715 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
f0194b2d
GW		 716
717 /*
718 * Register descriptor details in skb frame descriptor.
719 */
720 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
721 skbdesc->desc = entry->skb->data;
722 skbdesc->desc_len = TXWI_DESC_SIZE;
723
724 /*
725 * Add the TXWI for the beacon to the skb.
726 */
0c5879bc 727 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 728
729 /*
730 * Dump beacon to userspace through debugfs.
731 */
732 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
733
734 /*
739fd940 735 * Write entire beacon with TXWI and padding to register.
f0194b2d 736 */
739fd940 737 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61
SF		 738 if (padding_len && skb_pad(entry->skb, padding_len)) {
739 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
740 /* skb freed by skb_pad() on failure */
741 entry->skb = NULL;
742 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
743 return;
744 }
745
f0194b2d 746 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 747 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
748 entry->skb->len + padding_len);
f0194b2d
GW		 749
750 /*
751 * Enable beaconing again.
752 */
f0194b2d
GW		 753 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
754 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
755
756 /*
757 * Clean up beacon skb.
758 */
759 dev_kfree_skb_any(entry->skb);
760 entry->skb = NULL;
761}
50e888ea 762EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 763
69cf36a4
HS		 764static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
765 unsigned int beacon_base)
fdb87251
HS		 766{
767 int i;
768
769 /*
770 * For the Beacon base registers we only need to clear
771 * the whole TXWI which (when set to 0) will invalidate
772 * the entire beacon.
773 */
774 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
775 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
776}
777
69cf36a4
HS		 778void rt2800_clear_beacon(struct queue_entry *entry)
779{
780 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
781 u32 reg;
782
783 /*
784 * Disable beaconing while we are reloading the beacon data,
785 * otherwise we might be sending out invalid data.
786 */
787 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
788 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
789 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
790
791 /*
792 * Clear beacon.
793 */
794 rt2800_clear_beacon_register(rt2x00dev,
795 HW_BEACON_OFFSET(entry->entry_idx));
796
797 /*
798 * Enabled beaconing again.
799 */
800 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
801 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
802}
803EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
804
f4450616
BZ		 805#ifdef CONFIG_RT2X00_LIB_DEBUGFS
806const struct rt2x00debug rt2800_rt2x00debug = {
807 .owner = THIS_MODULE,
808 .csr = {
809 .read = rt2800_register_read,
810 .write = rt2800_register_write,
811 .flags = RT2X00DEBUGFS_OFFSET,
812 .word_base = CSR_REG_BASE,
813 .word_size = sizeof(u32),
814 .word_count = CSR_REG_SIZE / sizeof(u32),
815 },
816 .eeprom = {
817 .read = rt2x00_eeprom_read,
818 .write = rt2x00_eeprom_write,
819 .word_base = EEPROM_BASE,
820 .word_size = sizeof(u16),
821 .word_count = EEPROM_SIZE / sizeof(u16),
822 },
823 .bbp = {
824 .read = rt2800_bbp_read,
825 .write = rt2800_bbp_write,
826 .word_base = BBP_BASE,
827 .word_size = sizeof(u8),
828 .word_count = BBP_SIZE / sizeof(u8),
829 },
830 .rf = {
831 .read = rt2x00_rf_read,
832 .write = rt2800_rf_write,
833 .word_base = RF_BASE,
834 .word_size = sizeof(u32),
835 .word_count = RF_SIZE / sizeof(u32),
836 },
837};
838EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
839#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
840
841int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
842{
843 u32 reg;
844
845 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
846 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
847}
848EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
849
850#ifdef CONFIG_RT2X00_LIB_LEDS
851static void rt2800_brightness_set(struct led_classdev *led_cdev,
852 enum led_brightness brightness)
853{
854 struct rt2x00_led *led =
855 container_of(led_cdev, struct rt2x00_led, led_dev);
856 unsigned int enabled = brightness != LED_OFF;
857 unsigned int bg_mode =
858 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
859 unsigned int polarity =
860 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
861 EEPROM_FREQ_LED_POLARITY);
862 unsigned int ledmode =
863 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
864 EEPROM_FREQ_LED_MODE);
44704e5d 865 u32 reg;
f4450616 866
44704e5d
LE		 867 /* Check for SoC (SOC devices don't support MCU requests) */
868 if (rt2x00_is_soc(led->rt2x00dev)) {
869 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
870
871 /* Set LED Polarity */
872 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
873
874 /* Set LED Mode */
875 if (led->type == LED_TYPE_RADIO) {
876 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
877 enabled ? 3 : 0);
878 } else if (led->type == LED_TYPE_ASSOC) {
879 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
880 enabled ? 3 : 0);
881 } else if (led->type == LED_TYPE_QUALITY) {
882 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
883 enabled ? 3 : 0);
884 }
885
886 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
887
888 } else {
889 if (led->type == LED_TYPE_RADIO) {
890 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
891 enabled ? 0x20 : 0);
892 } else if (led->type == LED_TYPE_ASSOC) {
893 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
894 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
895 } else if (led->type == LED_TYPE_QUALITY) {
896 /*
897 * The brightness is divided into 6 levels (0 - 5),
898 * The specs tell us the following levels:
899 * 0, 1 ,3, 7, 15, 31
900 * to determine the level in a simple way we can simply
901 * work with bitshifting:
902 * (1 << level) - 1
903 */
904 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
905 (1 << brightness / (LED_FULL / 6)) - 1,
906 polarity);
907 }
f4450616
BZ		 908 }
909}
910
b3579d6a 911static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 912 struct rt2x00_led *led, enum led_type type)
913{
914 led->rt2x00dev = rt2x00dev;
915 led->type = type;
916 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 917 led->flags = LED_INITIALIZED;
918}
f4450616
BZ		 919#endif /* CONFIG_RT2X00_LIB_LEDS */
920
921/*
922 * Configuration handlers.
923 */
a2b1328a
HS		 924static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
925 const u8 *address,
926 int wcid)
f4450616
BZ		 927{
928 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 929 u32 offset;
930
931 offset = MAC_WCID_ENTRY(wcid);
932
933 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
934 if (address)
935 memcpy(wcid_entry.mac, address, ETH_ALEN);
936
937 rt2800_register_multiwrite(rt2x00dev, offset,
938 &wcid_entry, sizeof(wcid_entry));
939}
940
941static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
942{
943 u32 offset;
944 offset = MAC_WCID_ATTR_ENTRY(wcid);
945 rt2800_register_write(rt2x00dev, offset, 0);
946}
947
948static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
949 int wcid, u32 bssidx)
950{
951 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
952 u32 reg;
953
954 /*
955 * The BSS Idx numbers is split in a main value of 3 bits,
956 * and a extended field for adding one additional bit to the value.
957 */
958 rt2800_register_read(rt2x00dev, offset, &reg);
959 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
960 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
961 (bssidx & 0x8) >> 3);
962 rt2800_register_write(rt2x00dev, offset, reg);
963}
964
965static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
966 struct rt2x00lib_crypto *crypto,
967 struct ieee80211_key_conf *key)
968{
f4450616
BZ		 969 struct mac_iveiv_entry iveiv_entry;
970 u32 offset;
971 u32 reg;
972
973 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
974
e4a0ab34
ID		 975 if (crypto->cmd == SET_KEY) {
976 rt2800_register_read(rt2x00dev, offset, &reg);
977 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
978 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
979 /*
980 * Both the cipher as the BSS Idx numbers are split in a main
981 * value of 3 bits, and a extended field for adding one additional
982 * bit to the value.
983 */
984 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
985 (crypto->cipher & 0x7));
986 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
987 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 988 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
989 rt2800_register_write(rt2x00dev, offset, reg);
990 } else {
a2b1328a
HS		 991 /* Delete the cipher without touching the bssidx */
992 rt2800_register_read(rt2x00dev, offset, &reg);
993 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
994 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
995 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
996 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
997 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 998 }
f4450616
BZ		 999
1000 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1001
1002 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1003 if ((crypto->cipher == CIPHER_TKIP) ||
1004 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1005 (crypto->cipher == CIPHER_AES))
1006 iveiv_entry.iv[3] |= 0x20;
1007 iveiv_entry.iv[3] |= key->keyidx << 6;
1008 rt2800_register_multiwrite(rt2x00dev, offset,
1009 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1010}
1011
1012int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1013 struct rt2x00lib_crypto *crypto,
1014 struct ieee80211_key_conf *key)
1015{
1016 struct hw_key_entry key_entry;
1017 struct rt2x00_field32 field;
1018 u32 offset;
1019 u32 reg;
1020
1021 if (crypto->cmd == SET_KEY) {
1022 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1023
1024 memcpy(key_entry.key, crypto->key,
1025 sizeof(key_entry.key));
1026 memcpy(key_entry.tx_mic, crypto->tx_mic,
1027 sizeof(key_entry.tx_mic));
1028 memcpy(key_entry.rx_mic, crypto->rx_mic,
1029 sizeof(key_entry.rx_mic));
1030
1031 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1032 rt2800_register_multiwrite(rt2x00dev, offset,
1033 &key_entry, sizeof(key_entry));
1034 }
1035
1036 /*
1037 * The cipher types are stored over multiple registers
1038 * starting with SHARED_KEY_MODE_BASE each word will have
1039 * 32 bits and contains the cipher types for 2 bssidx each.
1040 * Using the correct defines correctly will cause overhead,
1041 * so just calculate the correct offset.
1042 */
1043 field.bit_offset = 4 * (key->hw_key_idx % 8);
1044 field.bit_mask = 0x7 << field.bit_offset;
1045
1046 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1047
1048 rt2800_register_read(rt2x00dev, offset, &reg);
1049 rt2x00_set_field32(&reg, field,
1050 (crypto->cmd == SET_KEY) * crypto->cipher);
1051 rt2800_register_write(rt2x00dev, offset, reg);
1052
1053 /*
1054 * Update WCID information
1055 */
a2b1328a
HS		 1056 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1057 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1058 crypto->bssidx);
1059 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1064
a2b1328a 1065static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1066{
a2b1328a 1067 struct mac_wcid_entry wcid_entry;
1ed3811c 1068 int idx;
a2b1328a 1069 u32 offset;
1ed3811c
HS		 1070
1071 /*
a2b1328a
HS		 1072 * Search for the first free WCID entry and return the corresponding
1073 * index.
1ed3811c
HS		 1074 *
1075 * Make sure the WCID starts _after_ the last possible shared key
1076 * entry (>32).
1077 *
1078 * Since parts of the pairwise key table might be shared with
1079 * the beacon frame buffers 6 & 7 we should only write into the
1080 * first 222 entries.
1081 */
1082 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1083 offset = MAC_WCID_ENTRY(idx);
1084 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1085 sizeof(wcid_entry));
1086 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1087 return idx;
1088 }
a2b1328a
HS		 1089
1090 /*
1091 * Use -1 to indicate that we don't have any more space in the WCID
1092 * table.
1093 */
1ed3811c
HS		 1094 return -1;
1095}
1096
f4450616
BZ		 1097int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1098 struct rt2x00lib_crypto *crypto,
1099 struct ieee80211_key_conf *key)
1100{
1101 struct hw_key_entry key_entry;
1102 u32 offset;
1103
1104 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1105 /*
1106 * Allow key configuration only for STAs that are
1107 * known by the hw.
1108 */
1109 if (crypto->wcid < 0)
f4450616 1110 return -ENOSPC;
a2b1328a 1111 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1112
1113 memcpy(key_entry.key, crypto->key,
1114 sizeof(key_entry.key));
1115 memcpy(key_entry.tx_mic, crypto->tx_mic,
1116 sizeof(key_entry.tx_mic));
1117 memcpy(key_entry.rx_mic, crypto->rx_mic,
1118 sizeof(key_entry.rx_mic));
1119
1120 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1121 rt2800_register_multiwrite(rt2x00dev, offset,
1122 &key_entry, sizeof(key_entry));
1123 }
1124
1125 /*
1126 * Update WCID information
1127 */
a2b1328a 1128 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1129
1130 return 0;
1131}
1132EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1133
a2b1328a
HS		 1134int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1135 struct ieee80211_sta *sta)
1136{
1137 int wcid;
1138 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1139
1140 /*
1141 * Find next free WCID.
1142 */
1143 wcid = rt2800_find_wcid(rt2x00dev);
1144
1145 /*
1146 * Store selected wcid even if it is invalid so that we can
1147 * later decide if the STA is uploaded into the hw.
1148 */
1149 sta_priv->wcid = wcid;
1150
1151 /*
1152 * No space left in the device, however, we can still communicate
1153 * with the STA -> No error.
1154 */
1155 if (wcid < 0)
1156 return 0;
1157
1158 /*
1159 * Clean up WCID attributes and write STA address to the device.
1160 */
1161 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1162 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1163 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1164 rt2x00lib_get_bssidx(rt2x00dev, vif));
1165 return 0;
1166}
1167EXPORT_SYMBOL_GPL(rt2800_sta_add);
1168
1169int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1170{
1171 /*
1172 * Remove WCID entry, no need to clean the attributes as they will
1173 * get renewed when the WCID is reused.
1174 */
1175 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1176
1177 return 0;
1178}
1179EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1180
f4450616
BZ		 1181void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1182 const unsigned int filter_flags)
1183{
1184 u32 reg;
1185
1186 /*
1187 * Start configuration steps.
1188 * Note that the version error will always be dropped
1189 * and broadcast frames will always be accepted since
1190 * there is no filter for it at this time.
1191 */
1192 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1193 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1194 !(filter_flags & FIF_FCSFAIL));
1195 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1196 !(filter_flags & FIF_PLCPFAIL));
1197 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1198 !(filter_flags & FIF_PROMISC_IN_BSS));
1199 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1200 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1201 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1202 !(filter_flags & FIF_ALLMULTI));
1203 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1204 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1205 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1206 !(filter_flags & FIF_CONTROL));
1207 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1208 !(filter_flags & FIF_CONTROL));
1209 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1210 !(filter_flags & FIF_CONTROL));
1211 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1212 !(filter_flags & FIF_CONTROL));
1213 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1214 !(filter_flags & FIF_CONTROL));
1215 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1216 !(filter_flags & FIF_PSPOLL));
48839938
HS		 1217 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1218 !(filter_flags & FIF_CONTROL));
1219 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1220 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1221 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1222 !(filter_flags & FIF_CONTROL));
1223 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1224}
1225EXPORT_SYMBOL_GPL(rt2800_config_filter);
1226
1227void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1228 struct rt2x00intf_conf *conf, const unsigned int flags)
1229{
f4450616 1230 u32 reg;
fa8b4b22 1231 bool update_bssid = false;
f4450616
BZ		 1232
1233 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1234 /*
1235 * Enable synchronisation.
1236 */
1237 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1238 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1239 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1240
1241 if (conf->sync == TSF_SYNC_AP_NONE) {
1242 /*
1243 * Tune beacon queue transmit parameters for AP mode
1244 */
1245 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1246 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1247 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1248 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1249 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1250 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1251 } else {
1252 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1253 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1254 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1255 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1256 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1257 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1258 }
f4450616
BZ		 1259 }
1260
1261 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1262 if (flags & CONFIG_UPDATE_TYPE &&
1263 conf->sync == TSF_SYNC_AP_NONE) {
1264 /*
1265 * The BSSID register has to be set to our own mac
1266 * address in AP mode.
1267 */
1268 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1269 update_bssid = true;
1270 }
1271
c600c826
ID		 1272 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1273 reg = le32_to_cpu(conf->mac[1]);
1274 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1275 conf->mac[1] = cpu_to_le32(reg);
1276 }
f4450616
BZ		 1277
1278 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1279 conf->mac, sizeof(conf->mac));
1280 }
1281
fa8b4b22 1282 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1283 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1284 reg = le32_to_cpu(conf->bssid[1]);
1285 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1286 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1287 conf->bssid[1] = cpu_to_le32(reg);
1288 }
f4450616
BZ		 1289
1290 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1291 conf->bssid, sizeof(conf->bssid));
1292 }
1293}
1294EXPORT_SYMBOL_GPL(rt2800_config_intf);
1295
87c1915d
HS		 1296static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1297 struct rt2x00lib_erp *erp)
1298{
1299 bool any_sta_nongf = !!(erp->ht_opmode &
1300 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1301 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1302 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1303 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1304 u32 reg;
1305
1306 /* default protection rate for HT20: OFDM 24M */
1307 mm20_rate = gf20_rate = 0x4004;
1308
1309 /* default protection rate for HT40: duplicate OFDM 24M */
1310 mm40_rate = gf40_rate = 0x4084;
1311
1312 switch (protection) {
1313 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1314 /*
1315 * All STAs in this BSS are HT20/40 but there might be
1316 * STAs not supporting greenfield mode.
1317 * => Disable protection for HT transmissions.
1318 */
1319 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1320
1321 break;
1322 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1323 /*
1324 * All STAs in this BSS are HT20 or HT20/40 but there
1325 * might be STAs not supporting greenfield mode.
1326 * => Protect all HT40 transmissions.
1327 */
1328 mm20_mode = gf20_mode = 0;
1329 mm40_mode = gf40_mode = 2;
1330
1331 break;
1332 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1333 /*
1334 * Nonmember protection:
1335 * According to 802.11n we _should_ protect all
1336 * HT transmissions (but we don't have to).
1337 *
1338 * But if cts_protection is enabled we _shall_ protect
1339 * all HT transmissions using a CCK rate.
1340 *
1341 * And if any station is non GF we _shall_ protect
1342 * GF transmissions.
1343 *
1344 * We decide to protect everything
1345 * -> fall through to mixed mode.
1346 */
1347 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1348 /*
1349 * Legacy STAs are present
1350 * => Protect all HT transmissions.
1351 */
1352 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1353
1354 /*
1355 * If erp protection is needed we have to protect HT
1356 * transmissions with CCK 11M long preamble.
1357 */
1358 if (erp->cts_protection) {
1359 /* don't duplicate RTS/CTS in CCK mode */
1360 mm20_rate = mm40_rate = 0x0003;
1361 gf20_rate = gf40_rate = 0x0003;
1362 }
1363 break;
6403eab1 1364 }
87c1915d
HS		 1365
1366 /* check for STAs not supporting greenfield mode */
1367 if (any_sta_nongf)
1368 gf20_mode = gf40_mode = 2;
1369
1370 /* Update HT protection config */
1371 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1372 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1373 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1374 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1375
1376 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1377 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1378 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1379 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1380
1381 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1382 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1383 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1384 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1385
1386 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1387 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1388 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1389 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1390}
1391
02044643
HS		 1392void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1393 u32 changed)
f4450616
BZ		 1394{
1395 u32 reg;
1396
02044643
HS		 1397 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1398 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1399 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1400 !!erp->short_preamble);
1401 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1402 !!erp->short_preamble);
1403 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1404 }
f4450616 1405
02044643
HS		 1406 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1407 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1408 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1409 erp->cts_protection ? 2 : 0);
1410 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1411 }
f4450616 1412
02044643
HS		 1413 if (changed & BSS_CHANGED_BASIC_RATES) {
1414 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1415 erp->basic_rates);
1416 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1417 }
f4450616 1418
02044643
HS		 1419 if (changed & BSS_CHANGED_ERP_SLOT) {
1420 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1421 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1422 erp->slot_time);
1423 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1424
02044643
HS		 1425 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1426 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1427 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1428 }
f4450616 1429
02044643
HS		 1430 if (changed & BSS_CHANGED_BEACON_INT) {
1431 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1432 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1433 erp->beacon_int * 16);
1434 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1435 }
87c1915d
HS		 1436
1437 if (changed & BSS_CHANGED_HT)
1438 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1439}
1440EXPORT_SYMBOL_GPL(rt2800_config_erp);
1441
872834df
GW		 1442static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1443{
1444 u32 reg;
1445 u16 eeprom;
1446 u8 led_ctrl, led_g_mode, led_r_mode;
1447
1448 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1449 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1450 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1451 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1452 } else {
1453 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1454 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1455 }
1456 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1457
1458 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1459 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1460 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1461 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1462 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1463 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1464 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1465 if (led_ctrl == 0 || led_ctrl > 0x40) {
1466 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1467 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1468 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1469 } else {
1470 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1471 (led_g_mode << 2) | led_r_mode, 1);
1472 }
1473 }
1474}
1475
d96aa640
RJH		 1476static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1477 enum antenna ant)
1478{
1479 u32 reg;
1480 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1481 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1482
1483 if (rt2x00_is_pci(rt2x00dev)) {
1484 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1485 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1486 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1487 } else if (rt2x00_is_usb(rt2x00dev))
1488 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1489 eesk_pin, 0);
1490
1491 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
fe59147c 1492 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
d96aa640
RJH		 1493 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1494 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1495}
1496
f4450616
BZ		 1497void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1498{
1499 u8 r1;
1500 u8 r3;
d96aa640 1501 u16 eeprom;
f4450616
BZ		 1502
1503 rt2800_bbp_read(rt2x00dev, 1, &r1);
1504 rt2800_bbp_read(rt2x00dev, 3, &r3);
1505
872834df
GW		 1506 if (rt2x00_rt(rt2x00dev, RT3572) &&
1507 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1508 rt2800_config_3572bt_ant(rt2x00dev);
1509
f4450616
BZ		 1510 /*
1511 * Configure the TX antenna.
1512 */
d96aa640 1513 switch (ant->tx_chain_num) {
f4450616
BZ		 1514 case 1:
1515 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1516 break;
1517 case 2:
872834df
GW		 1518 if (rt2x00_rt(rt2x00dev, RT3572) &&
1519 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1520 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1521 else
1522 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1523 break;
1524 case 3:
e22557f2 1525 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1526 break;
1527 }
1528
1529 /*
1530 * Configure the RX antenna.
1531 */
d96aa640 1532 switch (ant->rx_chain_num) {
f4450616 1533 case 1:
d96aa640
RJH		 1534 if (rt2x00_rt(rt2x00dev, RT3070) ||
1535 rt2x00_rt(rt2x00dev, RT3090) ||
1536 rt2x00_rt(rt2x00dev, RT3390)) {
1537 rt2x00_eeprom_read(rt2x00dev,
1538 EEPROM_NIC_CONF1, &eeprom);
1539 if (rt2x00_get_field16(eeprom,
1540 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1541 rt2800_set_ant_diversity(rt2x00dev,
1542 rt2x00dev->default_ant.rx);
1543 }
f4450616
BZ		 1544 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1545 break;
1546 case 2:
872834df
GW		 1547 if (rt2x00_rt(rt2x00dev, RT3572) &&
1548 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1549 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1550 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1551 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1552 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1553 } else {
1554 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1555 }
f4450616
BZ		 1556 break;
1557 case 3:
1558 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1559 break;
1560 }
1561
1562 rt2800_bbp_write(rt2x00dev, 3, r3);
1563 rt2800_bbp_write(rt2x00dev, 1, r1);
1564}
1565EXPORT_SYMBOL_GPL(rt2800_config_ant);
1566
1567static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1568 struct rt2x00lib_conf *libconf)
1569{
1570 u16 eeprom;
1571 short lna_gain;
1572
1573 if (libconf->rf.channel <= 14) {
1574 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1575 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1576 } else if (libconf->rf.channel <= 64) {
1577 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1578 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1579 } else if (libconf->rf.channel <= 128) {
1580 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1581 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1582 } else {
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1584 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1585 }
1586
1587 rt2x00dev->lna_gain = lna_gain;
1588}
1589
06855ef4
GW		 1590static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1591 struct ieee80211_conf *conf,
1592 struct rf_channel *rf,
1593 struct channel_info *info)
f4450616
BZ		 1594{
1595 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1596
d96aa640 1597 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1598 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1599
d96aa640 1600 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1601 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1602 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1603 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1604 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1605
1606 if (rf->channel > 14) {
1607 /*
1608 * When TX power is below 0, we should increase it by 7 to
25985edc 1609 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1610 * However this means that values between 0 and 7 have
1611 * double meaning, and we should set a 7DBm boost flag.
1612 */
1613 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1614 (info->default_power1 >= 0));
f4450616 1615
8d1331b3
ID		 1616 if (info->default_power1 < 0)
1617 info->default_power1 += 7;
f4450616 1618
8d1331b3 1619 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1620
1621 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1622 (info->default_power2 >= 0));
f4450616 1623
8d1331b3
ID		 1624 if (info->default_power2 < 0)
1625 info->default_power2 += 7;
f4450616 1626
8d1331b3 1627 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 1628 } else {
8d1331b3
ID		 1629 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1630 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 1631 }
1632
1633 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1634
1635 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1636 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1637 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1638 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1639
1640 udelay(200);
1641
1642 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1643 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1644 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1645 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1646
1647 udelay(200);
1648
1649 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1650 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1651 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1652 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1653}
1654
06855ef4
GW		 1655static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1656 struct ieee80211_conf *conf,
1657 struct rf_channel *rf,
1658 struct channel_info *info)
f4450616 1659{
3a1c0128 1660 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 1661 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 1662
1663 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 1664
1665 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1666 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1667 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 1668
1669 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1670 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1671 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1672
1673 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 1674 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 1675 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1676
5a673964 1677 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 1678 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 1679 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 1680
1681 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1682 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1683 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1684 if (rt2x00_rt(rt2x00dev, RT3390)) {
1685 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1686 rt2x00dev->default_ant.rx_chain_num == 1);
1687 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1688 rt2x00dev->default_ant.tx_chain_num == 1);
1689 } else {
1690 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1691 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1692 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1693 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1694
1695 switch (rt2x00dev->default_ant.tx_chain_num) {
1696 case 1:
1697 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1698 /* fall through */
1699 case 2:
1700 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1701 break;
1702 }
1703
1704 switch (rt2x00dev->default_ant.rx_chain_num) {
1705 case 1:
1706 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1707 /* fall through */
1708 case 2:
1709 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1710 break;
1711 }
1712 }
1713 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 1714
3e0c7643
SG		 1715 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1716 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1717 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1718 msleep(1);
1719 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1720 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1721
f4450616
BZ		 1722 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1723 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1724 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1725
f1f12f98
SG		 1726 if (rt2x00_rt(rt2x00dev, RT3390)) {
1727 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1728 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1729 } else {
3a1c0128
GW		 1730 if (conf_is_ht40(conf)) {
1731 calib_tx = drv_data->calibration_bw40;
1732 calib_rx = drv_data->calibration_bw40;
1733 } else {
1734 calib_tx = drv_data->calibration_bw20;
1735 calib_rx = drv_data->calibration_bw20;
1736 }
f1f12f98
SG		 1737 }
1738
1739 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1740 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1741 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1742
1743 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1744 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1745 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 1746
71976907 1747 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1748 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1749 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 1750
1751 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1752 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1753 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1754 msleep(1);
1755 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1756 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 1757}
1758
872834df
GW		 1759static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1760 struct ieee80211_conf *conf,
1761 struct rf_channel *rf,
1762 struct channel_info *info)
1763{
3a1c0128 1764 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 1765 u8 rfcsr;
1766 u32 reg;
1767
1768 if (rf->channel <= 14) {
5d137dff
GW		 1769 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1770 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 1771 } else {
1772 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1773 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1774 }
1775
1776 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1777 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1778
1779 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1780 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1781 if (rf->channel <= 14)
1782 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1783 else
1784 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1785 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1786
1787 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1788 if (rf->channel <= 14)
1789 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1790 else
1791 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1792 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1793
1794 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1795 if (rf->channel <= 14) {
1796 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1797 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 1798 info->default_power1);
872834df
GW		 1799 } else {
1800 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1801 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1802 (info->default_power1 & 0x3) |
1803 ((info->default_power1 & 0xC) << 1));
1804 }
1805 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1806
1807 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1808 if (rf->channel <= 14) {
1809 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1810 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 1811 info->default_power2);
872834df
GW		 1812 } else {
1813 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1814 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1815 (info->default_power2 & 0x3) |
1816 ((info->default_power2 & 0xC) << 1));
1817 }
1818 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1819
1820 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 1821 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1822 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1823 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1824 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 1825 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1826 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
872834df
GW		 1827 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1828 if (rf->channel <= 14) {
1829 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1830 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1831 }
1832 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1833 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1834 } else {
1835 switch (rt2x00dev->default_ant.tx_chain_num) {
1836 case 1:
1837 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1838 case 2:
1839 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1840 break;
1841 }
1842
1843 switch (rt2x00dev->default_ant.rx_chain_num) {
1844 case 1:
1845 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1846 case 2:
1847 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1848 break;
1849 }
1850 }
1851 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1852
1853 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1854 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1855 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1856
3a1c0128
GW		 1857 if (conf_is_ht40(conf)) {
1858 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1859 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1860 } else {
1861 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1862 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1863 }
872834df
GW		 1864
1865 if (rf->channel <= 14) {
1866 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1867 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1868 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1869 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1870 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 1871 rfcsr = 0x4c;
1872 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1873 drv_data->txmixer_gain_24g);
1874 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1875 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1876 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1877 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1878 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1879 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1880 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1881 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1882 } else {
58b8ae14
GW		 1883 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1884 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1885 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1886 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1887 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1888 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 1889 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1890 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1891 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1892 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 1893 rfcsr = 0x7a;
1894 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1895 drv_data->txmixer_gain_5g);
1896 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 1897 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1898 if (rf->channel <= 64) {
1899 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1900 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1901 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1902 } else if (rf->channel <= 128) {
1903 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1904 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1905 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1906 } else {
1907 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1908 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1909 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1910 }
1911 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1912 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1913 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1914 }
1915
1916 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1917 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1918 if (rf->channel <= 14)
1919 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1920 else
1921 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1922 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1923
1924 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1925 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1926 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1927}
60687ba7
RST		 1928
1929#define RT5390_POWER_BOUND 0x27
1930#define RT5390_FREQ_OFFSET_BOUND 0x5f
1931
1932static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 1933 struct ieee80211_conf *conf,
1934 struct rf_channel *rf,
1935 struct channel_info *info)
1936{
1937 u8 rfcsr;
adde5882
GJ		 1938
1939 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1940 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1941 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1942 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1943 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1944
1945 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1946 if (info->default_power1 > RT5390_POWER_BOUND)
1947 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1948 else
1949 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1950 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1951
1952 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1953 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1954 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1955 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1956 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1957 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1958
1959 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1960 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1961 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1962 RT5390_FREQ_OFFSET_BOUND);
1963 else
1964 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1965 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1966
adde5882
GJ		 1967 if (rf->channel <= 14) {
1968 int idx = rf->channel-1;
1969
fdbc7b0a 1970 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 1971 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1972 /* r55/r59 value array of channel 1~14 */
1973 static const char r55_bt_rev[] = {0x83, 0x83,
1974 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1975 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1976 static const char r59_bt_rev[] = {0x0e, 0x0e,
1977 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1978 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1979
1980 rt2800_rfcsr_write(rt2x00dev, 55,
1981 r55_bt_rev[idx]);
1982 rt2800_rfcsr_write(rt2x00dev, 59,
1983 r59_bt_rev[idx]);
1984 } else {
1985 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1986 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1987 0x88, 0x88, 0x86, 0x85, 0x84};
1988
1989 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1990 }
1991 } else {
1992 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1993 static const char r55_nonbt_rev[] = {0x23, 0x23,
1994 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1995 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1996 static const char r59_nonbt_rev[] = {0x07, 0x07,
1997 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1998 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1999
2000 rt2800_rfcsr_write(rt2x00dev, 55,
2001 r55_nonbt_rev[idx]);
2002 rt2800_rfcsr_write(rt2x00dev, 59,
2003 r59_nonbt_rev[idx]);
2ed71884
JL		 2004 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2005 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2006 static const char r59_non_bt[] = {0x8f, 0x8f,
2007 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2008 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2009
2010 rt2800_rfcsr_write(rt2x00dev, 59,
2011 r59_non_bt[idx]);
2012 }
2013 }
2014 }
2015
2016 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2017 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2018 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2019 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2020
2021 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2022 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2023 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
60687ba7
RST		 2024}
2025
f4450616
BZ		 2026static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2027 struct ieee80211_conf *conf,
2028 struct rf_channel *rf,
2029 struct channel_info *info)
2030{
2031 u32 reg;
2032 unsigned int tx_pin;
2033 u8 bbp;
2034
46323e11 2035 if (rf->channel <= 14) {
8d1331b3
ID		 2036 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2037 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
46323e11 2038 } else {
8d1331b3
ID		 2039 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2040 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
46323e11
ID		 2041 }
2042
5aa57015
GW		 2043 switch (rt2x00dev->chip.rf) {
2044 case RF2020:
2045 case RF3020:
2046 case RF3021:
2047 case RF3022:
2048 case RF3320:
06855ef4 2049 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2050 break;
2051 case RF3052:
872834df 2052 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015
GW		 2053 break;
2054 case RF5370:
2ed71884 2055 case RF5372:
5aa57015 2056 case RF5390:
adde5882 2057 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015
GW		 2058 break;
2059 default:
06855ef4 2060 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 2061 }
f4450616
BZ		 2062
2063 /*
2064 * Change BBP settings
2065 */
2066 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2067 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2068 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2069 rt2800_bbp_write(rt2x00dev, 86, 0);
2070
2071 if (rf->channel <= 14) {
2ed71884
JL		 2072 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2073 !rt2x00_rt(rt2x00dev, RT5392)) {
7dab73b3
ID		 2074 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2075 &rt2x00dev->cap_flags)) {
adde5882
GJ		 2076 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2077 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2078 } else {
2079 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2080 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2081 }
f4450616
BZ		 2082 }
2083 } else {
872834df
GW		 2084 if (rt2x00_rt(rt2x00dev, RT3572))
2085 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2086 else
2087 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 2088
7dab73b3 2089 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
f4450616
BZ		 2090 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2091 else
2092 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2093 }
2094
2095 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 2096 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2097 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2098 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2099 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2100
872834df
GW		 2101 if (rt2x00_rt(rt2x00dev, RT3572))
2102 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2103
f4450616
BZ		 2104 tx_pin = 0;
2105
2106 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2107 if (rt2x00dev->default_ant.tx_chain_num == 2) {
65f31b5e
GW		 2108 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2109 rf->channel > 14);
2110 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2111 rf->channel <= 14);
f4450616
BZ		 2112 }
2113
2114 /* Turn on unused PA or LNA when not using 1T or 1R */
d96aa640 2115 if (rt2x00dev->default_ant.rx_chain_num == 2) {
f4450616
BZ		 2116 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2117 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2118 }
2119
2120 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2121 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2122 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2123 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
8f96e91f
GW		 2124 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2125 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2126 else
2127 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2128 rf->channel <= 14);
f4450616
BZ		 2129 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2130
2131 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2132
872834df
GW		 2133 if (rt2x00_rt(rt2x00dev, RT3572))
2134 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2135
f4450616
BZ		 2136 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2137 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2138 rt2800_bbp_write(rt2x00dev, 4, bbp);
2139
2140 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 2141 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 2142 rt2800_bbp_write(rt2x00dev, 3, bbp);
2143
8d0c9b65 2144 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 2145 if (conf_is_ht40(conf)) {
2146 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2147 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2148 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2149 } else {
2150 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2151 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2152 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2153 }
2154 }
2155
2156 msleep(1);
977206d7
HS		 2157
2158 /*
2159 * Clear channel statistic counters
2160 */
2161 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2162 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2163 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
f4450616
BZ		 2164}
2165
9e33a355
HS		 2166static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2167{
2168 u8 tssi_bounds[9];
2169 u8 current_tssi;
2170 u16 eeprom;
2171 u8 step;
2172 int i;
2173
2174 /*
2175 * Read TSSI boundaries for temperature compensation from
2176 * the EEPROM.
2177 *
2178 * Array idx 0 1 2 3 4 5 6 7 8
2179 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2180 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2181 */
2182 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2183 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2184 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2185 EEPROM_TSSI_BOUND_BG1_MINUS4);
2186 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2187 EEPROM_TSSI_BOUND_BG1_MINUS3);
2188
2189 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2190 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2191 EEPROM_TSSI_BOUND_BG2_MINUS2);
2192 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2193 EEPROM_TSSI_BOUND_BG2_MINUS1);
2194
2195 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2196 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2197 EEPROM_TSSI_BOUND_BG3_REF);
2198 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2199 EEPROM_TSSI_BOUND_BG3_PLUS1);
2200
2201 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2202 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2203 EEPROM_TSSI_BOUND_BG4_PLUS2);
2204 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2205 EEPROM_TSSI_BOUND_BG4_PLUS3);
2206
2207 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2208 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2209 EEPROM_TSSI_BOUND_BG5_PLUS4);
2210
2211 step = rt2x00_get_field16(eeprom,
2212 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2213 } else {
2214 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2215 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2216 EEPROM_TSSI_BOUND_A1_MINUS4);
2217 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2218 EEPROM_TSSI_BOUND_A1_MINUS3);
2219
2220 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2221 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2222 EEPROM_TSSI_BOUND_A2_MINUS2);
2223 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2224 EEPROM_TSSI_BOUND_A2_MINUS1);
2225
2226 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2227 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2228 EEPROM_TSSI_BOUND_A3_REF);
2229 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2230 EEPROM_TSSI_BOUND_A3_PLUS1);
2231
2232 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2233 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2234 EEPROM_TSSI_BOUND_A4_PLUS2);
2235 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2236 EEPROM_TSSI_BOUND_A4_PLUS3);
2237
2238 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2239 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2240 EEPROM_TSSI_BOUND_A5_PLUS4);
2241
2242 step = rt2x00_get_field16(eeprom,
2243 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2244 }
2245
2246 /*
2247 * Check if temperature compensation is supported.
2248 */
2249 if (tssi_bounds[4] == 0xff)
2250 return 0;
2251
2252 /*
2253 * Read current TSSI (BBP 49).
2254 */
2255 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2256
2257 /*
2258 * Compare TSSI value (BBP49) with the compensation boundaries
2259 * from the EEPROM and increase or decrease tx power.
2260 */
2261 for (i = 0; i <= 3; i++) {
2262 if (current_tssi > tssi_bounds[i])
2263 break;
2264 }
2265
2266 if (i == 4) {
2267 for (i = 8; i >= 5; i--) {
2268 if (current_tssi < tssi_bounds[i])
2269 break;
2270 }
2271 }
2272
2273 return (i - 4) * step;
2274}
2275
e90c54b2
RJH		 2276static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2277 enum ieee80211_band band)
2278{
2279 u16 eeprom;
2280 u8 comp_en;
2281 u8 comp_type;
75faae8b 2282 int comp_value = 0;
e90c54b2
RJH		 2283
2284 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2285
75faae8b
HS		 2286 /*
2287 * HT40 compensation not required.
2288 */
2289 if (eeprom == 0xffff ||
2290 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 2291 return 0;
2292
2293 if (band == IEEE80211_BAND_2GHZ) {
2294 comp_en = rt2x00_get_field16(eeprom,
2295 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2296 if (comp_en) {
2297 comp_type = rt2x00_get_field16(eeprom,
2298 EEPROM_TXPOWER_DELTA_TYPE_2G);
2299 comp_value = rt2x00_get_field16(eeprom,
2300 EEPROM_TXPOWER_DELTA_VALUE_2G);
2301 if (!comp_type)
2302 comp_value = -comp_value;
2303 }
2304 } else {
2305 comp_en = rt2x00_get_field16(eeprom,
2306 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2307 if (comp_en) {
2308 comp_type = rt2x00_get_field16(eeprom,
2309 EEPROM_TXPOWER_DELTA_TYPE_5G);
2310 comp_value = rt2x00_get_field16(eeprom,
2311 EEPROM_TXPOWER_DELTA_VALUE_5G);
2312 if (!comp_type)
2313 comp_value = -comp_value;
2314 }
2315 }
2316
2317 return comp_value;
2318}
2319
fa71a160
HS		 2320static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2321 enum ieee80211_band band, int power_level,
2322 u8 txpower, int delta)
e90c54b2
RJH		 2323{
2324 u32 reg;
2325 u16 eeprom;
2326 u8 criterion;
2327 u8 eirp_txpower;
2328 u8 eirp_txpower_criterion;
2329 u8 reg_limit;
e90c54b2
RJH		 2330
2331 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2332 return txpower;
2333
7dab73b3 2334 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
e90c54b2
RJH		 2335 /*
2336 * Check if eirp txpower exceed txpower_limit.
2337 * We use OFDM 6M as criterion and its eirp txpower
2338 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2339 * .11b data rate need add additional 4dbm
2340 * when calculating eirp txpower.
2341 */
2342 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2343 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2344
2345 rt2x00_eeprom_read(rt2x00dev,
2346 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2347
2348 if (band == IEEE80211_BAND_2GHZ)
2349 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2350 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2351 else
2352 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2353 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2354
2355 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 2356 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 2357
2358 reg_limit = (eirp_txpower > power_level) ?
2359 (eirp_txpower - power_level) : 0;
2360 } else
2361 reg_limit = 0;
2362
2af242e1 2363 return txpower + delta - reg_limit;
e90c54b2
RJH		 2364}
2365
f4450616 2366static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
9e33a355
HS		 2367 enum ieee80211_band band,
2368 int power_level)
f4450616 2369{
5e846004 2370 u8 txpower;
5e846004 2371 u16 eeprom;
e90c54b2 2372 int i, is_rate_b;
f4450616 2373 u32 reg;
f4450616 2374 u8 r1;
5e846004 2375 u32 offset;
2af242e1
HS		 2376 int delta;
2377
2378 /*
2379 * Calculate HT40 compensation delta
2380 */
2381 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 2382
9e33a355
HS		 2383 /*
2384 * calculate temperature compensation delta
2385 */
2386 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
f4450616 2387
5e846004 2388 /*
e90c54b2 2389 * set to normal bbp tx power control mode: +/- 0dBm
5e846004 2390 */
f4450616 2391 rt2800_bbp_read(rt2x00dev, 1, &r1);
e90c54b2 2392 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
f4450616 2393 rt2800_bbp_write(rt2x00dev, 1, r1);
5e846004
HS		 2394 offset = TX_PWR_CFG_0;
2395
2396 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2397 /* just to be safe */
2398 if (offset > TX_PWR_CFG_4)
2399 break;
2400
2401 rt2800_register_read(rt2x00dev, offset, &reg);
2402
2403 /* read the next four txpower values */
2404 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2405 &eeprom);
2406
e90c54b2
RJH		 2407 is_rate_b = i ? 0 : 1;
2408 /*
2409 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 2410 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 2411 * TX_PWR_CFG_4: unknown
2412 */
5e846004
HS		 2413 txpower = rt2x00_get_field16(eeprom,
2414 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2415 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2416 power_level, txpower, delta);
e90c54b2 2417 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 2418
e90c54b2
RJH		 2419 /*
2420 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 2421 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 2422 * TX_PWR_CFG_4: unknown
2423 */
5e846004
HS		 2424 txpower = rt2x00_get_field16(eeprom,
2425 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2426 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2427 power_level, txpower, delta);
e90c54b2 2428 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 2429
e90c54b2
RJH		 2430 /*
2431 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 2432 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 2433 * TX_PWR_CFG_4: unknown
2434 */
5e846004
HS		 2435 txpower = rt2x00_get_field16(eeprom,
2436 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2437 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2438 power_level, txpower, delta);
e90c54b2 2439 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 2440
e90c54b2
RJH		 2441 /*
2442 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 2443 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 2444 * TX_PWR_CFG_4: unknown
2445 */
5e846004
HS		 2446 txpower = rt2x00_get_field16(eeprom,
2447 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2448 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2449 power_level, txpower, delta);
e90c54b2 2450 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 2451
2452 /* read the next four txpower values */
2453 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2454 &eeprom);
2455
e90c54b2
RJH		 2456 is_rate_b = 0;
2457 /*
2458 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 2459 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2460 * TX_PWR_CFG_4: unknown
2461 */
5e846004
HS		 2462 txpower = rt2x00_get_field16(eeprom,
2463 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 2464 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2465 power_level, txpower, delta);
e90c54b2 2466 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 2467
e90c54b2
RJH		 2468 /*
2469 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 2470 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2471 * TX_PWR_CFG_4: unknown
2472 */
5e846004
HS		 2473 txpower = rt2x00_get_field16(eeprom,
2474 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 2475 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2476 power_level, txpower, delta);
e90c54b2 2477 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 2478
e90c54b2
RJH		 2479 /*
2480 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 2481 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2482 * TX_PWR_CFG_4: unknown
2483 */
5e846004
HS		 2484 txpower = rt2x00_get_field16(eeprom,
2485 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 2486 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2487 power_level, txpower, delta);
e90c54b2 2488 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 2489
e90c54b2
RJH		 2490 /*
2491 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 2492 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 2493 * TX_PWR_CFG_4: unknown
2494 */
5e846004
HS		 2495 txpower = rt2x00_get_field16(eeprom,
2496 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 2497 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 2498 power_level, txpower, delta);
e90c54b2 2499 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 2500
2501 rt2800_register_write(rt2x00dev, offset, reg);
2502
2503 /* next TX_PWR_CFG register */
2504 offset += 4;
2505 }
f4450616
BZ		 2506}
2507
9e33a355
HS		 2508void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2509{
2510 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2511 rt2x00dev->tx_power);
2512}
2513EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2514
2e9c43dd
JL		 2515void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2516{
2517 u32 tx_pin;
2518 u8 rfcsr;
2519
2520 /*
2521 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2522 * designed to be controlled in oscillation frequency by a voltage
2523 * input. Maybe the temperature will affect the frequency of
2524 * oscillation to be shifted. The VCO calibration will be called
2525 * periodically to adjust the frequency to be precision.
2526 */
2527
2528 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2529 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2530 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2531
2532 switch (rt2x00dev->chip.rf) {
2533 case RF2020:
2534 case RF3020:
2535 case RF3021:
2536 case RF3022:
2537 case RF3320:
2538 case RF3052:
2539 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2540 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2541 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2542 break;
2543 case RF5370:
2544 case RF5372:
2545 case RF5390:
2546 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2547 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2548 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2549 break;
2550 default:
2551 return;
2552 }
2553
2554 mdelay(1);
2555
2556 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2557 if (rt2x00dev->rf_channel <= 14) {
2558 switch (rt2x00dev->default_ant.tx_chain_num) {
2559 case 3:
2560 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2561 /* fall through */
2562 case 2:
2563 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2564 /* fall through */
2565 case 1:
2566 default:
2567 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2568 break;
2569 }
2570 } else {
2571 switch (rt2x00dev->default_ant.tx_chain_num) {
2572 case 3:
2573 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2574 /* fall through */
2575 case 2:
2576 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2577 /* fall through */
2578 case 1:
2579 default:
2580 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2581 break;
2582 }
2583 }
2584 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2585
2586}
2587EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2588
f4450616
BZ		 2589static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2590 struct rt2x00lib_conf *libconf)
2591{
2592 u32 reg;
2593
2594 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2595 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2596 libconf->conf->short_frame_max_tx_count);
2597 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2598 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 2599 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2600}
2601
2602static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2603 struct rt2x00lib_conf *libconf)
2604{
2605 enum dev_state state =
2606 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2607 STATE_SLEEP : STATE_AWAKE;
2608 u32 reg;
2609
2610 if (state == STATE_SLEEP) {
2611 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2612
2613 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2614 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2615 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2616 libconf->conf->listen_interval - 1);
2617 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2618 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2619
2620 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2621 } else {
f4450616
BZ		 2622 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2623 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2624 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2625 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2626 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 2627
2628 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 2629 }
2630}
2631
2632void rt2800_config(struct rt2x00_dev *rt2x00dev,
2633 struct rt2x00lib_conf *libconf,
2634 const unsigned int flags)
2635{
2636 /* Always recalculate LNA gain before changing configuration */
2637 rt2800_config_lna_gain(rt2x00dev, libconf);
2638
e90c54b2 2639 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 2640 rt2800_config_channel(rt2x00dev, libconf->conf,
2641 &libconf->rf, &libconf->channel);
9e33a355
HS		 2642 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2643 libconf->conf->power_level);
e90c54b2 2644 }
f4450616 2645 if (flags & IEEE80211_CONF_CHANGE_POWER)
9e33a355
HS		 2646 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2647 libconf->conf->power_level);
f4450616
BZ		 2648 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2649 rt2800_config_retry_limit(rt2x00dev, libconf);
2650 if (flags & IEEE80211_CONF_CHANGE_PS)
2651 rt2800_config_ps(rt2x00dev, libconf);
2652}
2653EXPORT_SYMBOL_GPL(rt2800_config);
2654
2655/*
2656 * Link tuning
2657 */
2658void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2659{
2660 u32 reg;
2661
2662 /*
2663 * Update FCS error count from register.
2664 */
2665 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2666 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2667}
2668EXPORT_SYMBOL_GPL(rt2800_link_stats);
2669
2670static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2671{
2672 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 2673 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 2674 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 2675 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 2676 rt2x00_rt(rt2x00dev, RT3390) ||
2ed71884
JL		 2677 rt2x00_rt(rt2x00dev, RT5390) ||
2678 rt2x00_rt(rt2x00dev, RT5392))
f4450616
BZ		 2679 return 0x1c + (2 * rt2x00dev->lna_gain);
2680 else
2681 return 0x2e + rt2x00dev->lna_gain;
2682 }
2683
2684 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2685 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2686 else
2687 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2688}
2689
2690static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2691 struct link_qual *qual, u8 vgc_level)
2692{
2693 if (qual->vgc_level != vgc_level) {
2694 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2695 qual->vgc_level = vgc_level;
2696 qual->vgc_level_reg = vgc_level;
2697 }
2698}
2699
2700void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2701{
2702 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2703}
2704EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2705
2706void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2707 const u32 count)
2708{
8d0c9b65 2709 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 2710 return;
2711
2712 /*
2713 * When RSSI is better then -80 increase VGC level with 0x10
2714 */
2715 rt2800_set_vgc(rt2x00dev, qual,
2716 rt2800_get_default_vgc(rt2x00dev) +
2717 ((qual->rssi > -80) * 0x10));
2718}
2719EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 2720
2721/*
2722 * Initialization functions.
2723 */
b9a07ae9 2724static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 2725{
2726 u32 reg;
d5385bfc 2727 u16 eeprom;
fcf51541 2728 unsigned int i;
e3a896b9 2729 int ret;
fcf51541 2730
f7b395e9 2731 rt2800_disable_wpdma(rt2x00dev);
a9dce149 2732
e3a896b9
GW		 2733 ret = rt2800_drv_init_registers(rt2x00dev);
2734 if (ret)
2735 return ret;
fcf51541
BZ		 2736
2737 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2738 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2739 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2740 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2741 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2742 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2743
2744 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2745 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2746 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2747 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2748 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2749 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2750
2751 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2752 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2753
2754 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2755
2756 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 2757 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 2758 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2759 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2760 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2761 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2762 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2763 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2764
a9dce149
GW		 2765 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2766
2767 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2768 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2769 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2770 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2771
64522957 2772 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2773 rt2x00_rt(rt2x00dev, RT3090) ||
2774 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 2775 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2776 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 2777 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2778 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2779 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
38c8a566
RJH		 2780 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2781 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 2782 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2783 0x0000002c);
2784 else
2785 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2786 0x0000000f);
2787 } else {
2788 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2789 }
d5385bfc 2790 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 2791 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 2792
2793 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2794 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2795 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2796 } else {
2797 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2798 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2799 }
c295a81d
HS		 2800 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2801 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2802 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 2803 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
872834df
GW		 2804 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2805 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2806 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2ed71884
JL		 2807 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2808 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2809 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2810 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2811 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 2812 } else {
2813 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2814 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2815 }
2816
2817 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2818 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2819 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2820 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2821 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2822 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2823 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2824 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2825 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2826 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2827
2828 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2829 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 2830 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 2831 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2832 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2833
2834 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2835 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 2836 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 2837 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 2838 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 2839 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2840 else
2841 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2842 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2843 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2844 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2845
a9dce149
GW		 2846 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2847 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2848 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2849 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2850 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2851 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2852 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2853 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2854 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2855
fcf51541
BZ		 2856 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2857
a9dce149
GW		 2858 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2859 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2860 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2861 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2862 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2863 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2864 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2865 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2866
fcf51541
BZ		 2867 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2868 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 2869 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 2870 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2871 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 2872 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 2873 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2874 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2875 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2876
2877 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 2878 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2879 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2880 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2881 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2882 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2883 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2884 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2885 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2886 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2887 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2888 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2889
2890 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 2891 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 2892 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2893 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2894 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2895 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2896 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 2897 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 2898 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 2899 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2900 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 2901 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2902
2903 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2904 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2905 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2906 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2907 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2908 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2909 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2910 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2911 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2912 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2913 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2914 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2915
2916 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2917 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 2918 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2919 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2920 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2921 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2922 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2923 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2924 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2925 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2926 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2927 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2928
2929 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2930 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2931 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2932 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2933 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2934 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2935 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2936 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2937 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2938 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 2939 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2940 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2941
2942 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2943 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2944 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 2945 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 2946 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2947 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2948 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2949 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2950 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2951 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 2952 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 2953 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2954
cea90e55 2955 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 2956 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2957
2958 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2959 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2960 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2961 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2962 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2963 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2964 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2965 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2966 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2967 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2968 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2969 }
2970
961621ab
HS		 2971 /*
2972 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2973 * although it is reserved.
2974 */
2975 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2976 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2977 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2978 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2979 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2980 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2981 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2982 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2983 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2984 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2985 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2986 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2987
fcf51541
BZ		 2988 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2989
2990 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2991 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2992 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2993 IEEE80211_MAX_RTS_THRESHOLD);
2994 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2995 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2996
2997 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 2998
a21c2ab4
HS		 2999 /*
3000 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3001 * time should be set to 16. However, the original Ralink driver uses
3002 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3003 * connection problems with 11g + CTS protection. Hence, use the same
3004 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3005 */
a9dce149 3006 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 3007 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3008 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 3009 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3010 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3011 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3012 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3013
fcf51541
BZ		 3014 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3015
3016 /*
3017 * ASIC will keep garbage value after boot, clear encryption keys.
3018 */
3019 for (i = 0; i < 4; i++)
3020 rt2800_register_write(rt2x00dev,
3021 SHARED_KEY_MODE_ENTRY(i), 0);
3022
3023 for (i = 0; i < 256; i++) {
d7d259d3
HS		 3024 rt2800_config_wcid(rt2x00dev, NULL, i);
3025 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 3026 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3027 }
3028
3029 /*
3030 * Clear all beacons
fcf51541 3031 */
69cf36a4
HS		 3032 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3033 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3034 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3035 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3036 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3037 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3038 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3039 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
fcf51541 3040
cea90e55 3041 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 3042 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3043 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3044 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 3045 } else if (rt2x00_is_pcie(rt2x00dev)) {
3046 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3047 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3048 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 3049 }
3050
3051 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3052 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3053 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3054 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3055 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3056 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3057 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3058 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3059 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3060 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3061
3062 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3063 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3064 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3065 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3066 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3067 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3068 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3069 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3070 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3071 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3072
3073 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3074 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3075 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3076 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3077 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3078 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3079 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3080 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3081 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3082 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3083
3084 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3085 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3086 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3087 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3088 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3089 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3090
47ee3eb1
HS		 3091 /*
3092 * Do not force the BA window size, we use the TXWI to set it
3093 */
3094 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3095 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3096 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3097 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3098
fcf51541
BZ		 3099 /*
3100 * We must clear the error counters.
3101 * These registers are cleared on read,
3102 * so we may pass a useless variable to store the value.
3103 */
3104 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3105 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3106 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3107 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3108 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3109 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3110
9f926fb5
HS		 3111 /*
3112 * Setup leadtime for pre tbtt interrupt to 6ms
3113 */
3114 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3115 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3116 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3117
977206d7
HS		 3118 /*
3119 * Set up channel statistics timer
3120 */
3121 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3122 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3123 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3124 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3125 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3126 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3127 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3128
fcf51541
BZ		 3129 return 0;
3130}
fcf51541
BZ		 3131
3132static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3133{
3134 unsigned int i;
3135 u32 reg;
3136
3137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3138 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3139 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3140 return 0;
3141
3142 udelay(REGISTER_BUSY_DELAY);
3143 }
3144
3145 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3146 return -EACCES;
3147}
3148
3149static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3150{
3151 unsigned int i;
3152 u8 value;
3153
3154 /*
3155 * BBP was enabled after firmware was loaded,
3156 * but we need to reactivate it now.
3157 */
3158 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3159 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3160 msleep(1);
3161
3162 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3163 rt2800_bbp_read(rt2x00dev, 0, &value);
3164 if ((value != 0xff) && (value != 0x00))
3165 return 0;
3166 udelay(REGISTER_BUSY_DELAY);
3167 }
3168
3169 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3170 return -EACCES;
3171}
3172
b9a07ae9 3173static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 3174{
3175 unsigned int i;
3176 u16 eeprom;
3177 u8 reg_id;
3178 u8 value;
3179
3180 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3181 rt2800_wait_bbp_ready(rt2x00dev)))
3182 return -EACCES;
3183
2ed71884
JL		 3184 if (rt2x00_rt(rt2x00dev, RT5390) ||
3185 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3186 rt2800_bbp_read(rt2x00dev, 4, &value);
3187 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3188 rt2800_bbp_write(rt2x00dev, 4, value);
3189 }
60687ba7 3190
adde5882 3191 if (rt2800_is_305x_soc(rt2x00dev) ||
872834df 3192 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3193 rt2x00_rt(rt2x00dev, RT5390) ||
3194 rt2x00_rt(rt2x00dev, RT5392))
baff8006
HS		 3195 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3196
fcf51541
BZ		 3197 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3198 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149 3199
2ed71884
JL		 3200 if (rt2x00_rt(rt2x00dev, RT5390) ||
3201 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3202 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
60687ba7 3203
a9dce149
GW		 3204 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3205 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3206 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2ed71884
JL		 3207 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3208 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3209 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3210 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3211 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3212 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3213 rt2800_bbp_write(rt2x00dev, 77, 0x59);
a9dce149
GW		 3214 } else {
3215 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3216 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3217 }
3218
fcf51541 3219 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 3220
d5385bfc 3221 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 3222 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3223 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3224 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3225 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3226 rt2x00_rt(rt2x00dev, RT5390) ||
3227 rt2x00_rt(rt2x00dev, RT5392)) {
8cdd15e0
GW		 3228 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3229 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3230 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 3231 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3232 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3233 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 3234 } else {
3235 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3236 }
3237
fcf51541 3238 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2ed71884
JL		 3239 if (rt2x00_rt(rt2x00dev, RT5390) ||
3240 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3241 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3242 else
3243 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 3244
5ed8f458 3245 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149 3246 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2ed71884
JL		 3247 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3248 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3249 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
a9dce149
GW		 3250 else
3251 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3252
2ed71884
JL		 3253 if (rt2x00_rt(rt2x00dev, RT5390) ||
3254 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3255 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3256 else
3257 rt2800_bbp_write(rt2x00dev, 86, 0x00);
60687ba7 3258
2ed71884
JL		 3259 if (rt2x00_rt(rt2x00dev, RT5392))
3260 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3261
fcf51541 3262 rt2800_bbp_write(rt2x00dev, 91, 0x04);
60687ba7 3263
2ed71884
JL		 3264 if (rt2x00_rt(rt2x00dev, RT5390) ||
3265 rt2x00_rt(rt2x00dev, RT5392))
adde5882
GJ		 3266 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3267 else
3268 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 3269
2ed71884
JL		 3270 if (rt2x00_rt(rt2x00dev, RT5392)) {
3271 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3272 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3273 }
3274
d5385bfc 3275 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3276 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 3277 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006 3278 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
872834df 3279 rt2x00_rt(rt2x00dev, RT3572) ||
adde5882 3280 rt2x00_rt(rt2x00dev, RT5390) ||
2ed71884 3281 rt2x00_rt(rt2x00dev, RT5392) ||
baff8006 3282 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 3283 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3284 else
3285 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3286
2ed71884
JL		 3287 if (rt2x00_rt(rt2x00dev, RT5390) ||
3288 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3289 rt2800_bbp_write(rt2x00dev, 104, 0x92);
60687ba7 3290
baff8006
HS		 3291 if (rt2800_is_305x_soc(rt2x00dev))
3292 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2ed71884
JL		 3293 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3294 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3295 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
baff8006
HS		 3296 else
3297 rt2800_bbp_write(rt2x00dev, 105, 0x05);
60687ba7 3298
adde5882
GJ		 3299 if (rt2x00_rt(rt2x00dev, RT5390))
3300 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2ed71884
JL		 3301 else if (rt2x00_rt(rt2x00dev, RT5392))
3302 rt2800_bbp_write(rt2x00dev, 106, 0x12);
adde5882
GJ		 3303 else
3304 rt2800_bbp_write(rt2x00dev, 106, 0x35);
60687ba7 3305
2ed71884
JL		 3306 if (rt2x00_rt(rt2x00dev, RT5390) ||
3307 rt2x00_rt(rt2x00dev, RT5392))
adde5882 3308 rt2800_bbp_write(rt2x00dev, 128, 0x12);
fcf51541 3309
2ed71884
JL		 3310 if (rt2x00_rt(rt2x00dev, RT5392)) {
3311 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3312 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3313 }
3314
64522957 3315 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3316 rt2x00_rt(rt2x00dev, RT3090) ||
adde5882 3317 rt2x00_rt(rt2x00dev, RT3390) ||
872834df 3318 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 3319 rt2x00_rt(rt2x00dev, RT5390) ||
3320 rt2x00_rt(rt2x00dev, RT5392)) {
d5385bfc 3321 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 3322
38c8a566
RJH		 3323 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3324 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
d5385bfc 3325 value |= 0x20;
38c8a566 3326 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
d5385bfc 3327 value &= ~0x02;
fcf51541 3328
d5385bfc 3329 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 3330 }
3331
2ed71884
JL		 3332 if (rt2x00_rt(rt2x00dev, RT5390) ||
3333 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3334 int ant, div_mode;
3335
3336 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3337 div_mode = rt2x00_get_field16(eeprom,
3338 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3339 ant = (div_mode == 3) ? 1 : 0;
3340
3341 /* check if this is a Bluetooth combo card */
fdbc7b0a 3342 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
adde5882
GJ		 3343 u32 reg;
3344
3345 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3346 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3347 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3348 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3349 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3350 if (ant == 0)
3351 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3352 else if (ant == 1)
3353 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3354 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3355 }
3356
3357 rt2800_bbp_read(rt2x00dev, 152, &value);
3358 if (ant == 0)
3359 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3360 else
3361 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3362 rt2800_bbp_write(rt2x00dev, 152, value);
3363
3364 /* Init frequency calibration */
3365 rt2800_bbp_write(rt2x00dev, 142, 1);
3366 rt2800_bbp_write(rt2x00dev, 143, 57);
3367 }
fcf51541
BZ		 3368
3369 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3370 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3371
3372 if (eeprom != 0xffff && eeprom != 0x0000) {
3373 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3374 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3375 rt2800_bbp_write(rt2x00dev, reg_id, value);
3376 }
3377 }
3378
3379 return 0;
3380}
fcf51541
BZ		 3381
3382static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3383 bool bw40, u8 rfcsr24, u8 filter_target)
3384{
3385 unsigned int i;
3386 u8 bbp;
3387 u8 rfcsr;
3388 u8 passband;
3389 u8 stopband;
3390 u8 overtuned = 0;
3391
3392 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3393
3394 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3395 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3396 rt2800_bbp_write(rt2x00dev, 4, bbp);
3397
80d184e6
RJH		 3398 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3399 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3400 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3401
fcf51541
BZ		 3402 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3403 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3404 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3405
3406 /*
3407 * Set power & frequency of passband test tone
3408 */
3409 rt2800_bbp_write(rt2x00dev, 24, 0);
3410
3411 for (i = 0; i < 100; i++) {
3412 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3413 msleep(1);
3414
3415 rt2800_bbp_read(rt2x00dev, 55, &passband);
3416 if (passband)
3417 break;
3418 }
3419
3420 /*
3421 * Set power & frequency of stopband test tone
3422 */
3423 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3424
3425 for (i = 0; i < 100; i++) {
3426 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3427 msleep(1);
3428
3429 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3430
3431 if ((passband - stopband) <= filter_target) {
3432 rfcsr24++;
3433 overtuned += ((passband - stopband) == filter_target);
3434 } else
3435 break;
3436
3437 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3438 }
3439
3440 rfcsr24 -= !!overtuned;
3441
3442 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3443 return rfcsr24;
3444}
3445
b9a07ae9 3446static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 3447{
3a1c0128 3448 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
fcf51541
BZ		 3449 u8 rfcsr;
3450 u8 bbp;
8cdd15e0
GW		 3451 u32 reg;
3452 u16 eeprom;
fcf51541 3453
d5385bfc 3454 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 3455 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 3456 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 3457 !rt2x00_rt(rt2x00dev, RT3390) &&
872834df 3458 !rt2x00_rt(rt2x00dev, RT3572) &&
adde5882 3459 !rt2x00_rt(rt2x00dev, RT5390) &&
2ed71884 3460 !rt2x00_rt(rt2x00dev, RT5392) &&
baff8006 3461 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 3462 return 0;
3463
fcf51541
BZ		 3464 /*
3465 * Init RF calibration.
3466 */
2ed71884
JL		 3467 if (rt2x00_rt(rt2x00dev, RT5390) ||
3468 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3469 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3470 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3471 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3472 msleep(1);
3473 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3474 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3475 } else {
3476 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3477 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3478 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3479 msleep(1);
3480 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3481 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3482 }
fcf51541 3483
d5385bfc 3484 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 3485 rt2x00_rt(rt2x00dev, RT3071) ||
3486 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 3487 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3488 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3489 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
80d184e6 3490 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
fcf51541 3491 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 3492 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 3493 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3494 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3495 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3496 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3497 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3498 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3499 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3500 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3501 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3502 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3503 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3504 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 3505 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 3506 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3507 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3508 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3509 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3510 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 3511 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 3512 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3513 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3514 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3515 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3516 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3517 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 3518 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 3519 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3520 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 3521 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 3522 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3523 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3524 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3525 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3526 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3527 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3528 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 3529 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 3530 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 3531 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 3532 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3533 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3534 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3535 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3536 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3537 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3538 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
872834df
GW		 3539 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3540 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3541 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3542 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3543 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3544 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3545 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3546 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3547 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3548 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3549 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3550 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3551 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3552 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3553 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3554 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3555 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3556 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3557 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3558 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3559 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3560 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3561 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3562 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3563 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3564 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3565 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3566 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3567 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3568 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3569 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3570 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
baff8006 3571 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 3572 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3573 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3574 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3575 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3576 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3577 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3578 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3579 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3580 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3581 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3582 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3583 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3584 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3585 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3586 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3587 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3588 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3589 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3590 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3591 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3592 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3593 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3594 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3595 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3596 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3597 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3598 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3599 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3600 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3601 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 3602 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3603 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3604 return 0;
adde5882
GJ		 3605 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3606 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3607 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3608 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3609 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3610 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3611 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3612 else
3613 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3614 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3615 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3616 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3617 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3618 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3619 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3620 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3621 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3622 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3623 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3624
3625 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3626 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3627 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3628 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3629 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3630 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3631 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3632 else
3633 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3634 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3635 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3636 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3637 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3638
3639 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3640 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3641 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3642 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3643 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3644 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3645 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3646 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3647 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3648 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3649
3650 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3651 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3652 else
3653 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3654 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3655 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3656 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3657 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3658 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3659 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3660 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3661 else
3662 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3663 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3664 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3665 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3666
3667 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3668 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3669 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3670 else
3671 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3672 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3673 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3674 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3675 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3676 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3677 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3678
3679 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3680 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3681 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3682 else
3683 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3684 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3685 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2ed71884
JL		 3686 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3687 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3688 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3689 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3690 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3691 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3692 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3693 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3694 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3695 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3696 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3697 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3698 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3699 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3700 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3701 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3702 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3703 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3704 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3705 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3706 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3707 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3708 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3709 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3710 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3711 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3712 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3713 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3714 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3715 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3716 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3717 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3718 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3719 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3720 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3721 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3722 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3723 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3724 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3725 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3726 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3727 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3728 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3729 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3730 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3731 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3732 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3733 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3734 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3735 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3736 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3737 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3738 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3739 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3740 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3741 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3742 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3743 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3744 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3745 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8cdd15e0
GW		 3746 }
3747
3748 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3749 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3750 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3751 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3752 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 3753 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3754 rt2x00_rt(rt2x00dev, RT3090)) {
80d184e6
RJH		 3755 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3756
d5385bfc
GW		 3757 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3758 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3759 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3760
d5385bfc
GW		 3761 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3762 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 3763 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3764 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
38c8a566
RJH		 3765 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3766 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 3767 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3768 else
3769 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3770 }
3771 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
80d184e6
RJH		 3772
3773 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3774 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3775 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
cc78e904
GW		 3776 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3777 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3778 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3779 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
872834df
GW		 3780 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3781 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3782 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3783 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3784
3785 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3786 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3787 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3788 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3789 msleep(1);
3790 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3791 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3792 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
fcf51541
BZ		 3793 }
3794
3795 /*
3796 * Set RX Filter calibration for 20MHz and 40MHz
3797 */
8cdd15e0 3798 if (rt2x00_rt(rt2x00dev, RT3070)) {
3a1c0128 3799 drv_data->calibration_bw20 =
8cdd15e0 3800 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3a1c0128 3801 drv_data->calibration_bw40 =
8cdd15e0 3802 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 3803 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 3804 rt2x00_rt(rt2x00dev, RT3090) ||
872834df
GW		 3805 rt2x00_rt(rt2x00dev, RT3390) ||
3806 rt2x00_rt(rt2x00dev, RT3572)) {
3a1c0128 3807 drv_data->calibration_bw20 =
d5385bfc 3808 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3a1c0128 3809 drv_data->calibration_bw40 =
d5385bfc 3810 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 3811 }
fcf51541 3812
5d137dff
GW		 3813 /*
3814 * Save BBP 25 & 26 values for later use in channel switching
3815 */
3816 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3817 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3818
2ed71884
JL		 3819 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3820 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3821 /*
3822 * Set back to initial state
3823 */
3824 rt2800_bbp_write(rt2x00dev, 24, 0);
fcf51541 3825
adde5882
GJ		 3826 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3827 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3828 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
fcf51541 3829
adde5882
GJ		 3830 /*
3831 * Set BBP back to BW20
3832 */
3833 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3834 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3835 rt2800_bbp_write(rt2x00dev, 4, bbp);
3836 }
fcf51541 3837
d5385bfc 3838 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 3839 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 3840 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3841 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 3842 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3843
3844 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3845 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3846 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3847
2ed71884
JL		 3848 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3849 !rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3850 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3851 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3852 if (rt2x00_rt(rt2x00dev, RT3070) ||
3853 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3854 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3855 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7dab73b3
ID		 3856 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3857 &rt2x00dev->cap_flags))
adde5882
GJ		 3858 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3859 }
77c06c2c
GW		 3860 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3861 drv_data->txmixer_gain_24g);
adde5882
GJ		 3862 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3863 }
8cdd15e0 3864
64522957
GW		 3865 if (rt2x00_rt(rt2x00dev, RT3090)) {
3866 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3867
80d184e6 3868 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
38c8a566
RJH		 3869 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3870 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
64522957 3871 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
38c8a566 3872 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
64522957
GW		 3873 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3874
3875 rt2800_bbp_write(rt2x00dev, 138, bbp);
3876 }
3877
3878 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 3879 rt2x00_rt(rt2x00dev, RT3090) ||
3880 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 3881 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3882 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3883 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3884 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3885 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3886 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3887 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3888
3889 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3890 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3891 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3892
3893 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3894 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3895 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3896
3897 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3898 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3899 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3900 }
3901
80d184e6 3902 if (rt2x00_rt(rt2x00dev, RT3070)) {
8cdd15e0 3903 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
80d184e6 3904 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
8cdd15e0
GW		 3905 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3906 else
3907 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3908 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3909 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3910 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3911 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3912 }
3913
2ed71884
JL		 3914 if (rt2x00_rt(rt2x00dev, RT5390) ||
3915 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 3916 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3917 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3918 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
60687ba7 3919
adde5882
GJ		 3920 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3921 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3922 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
60687ba7 3923
adde5882
GJ		 3924 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3925 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3926 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3927 }
60687ba7 3928
fcf51541
BZ		 3929 return 0;
3930}
b9a07ae9
ID		 3931
3932int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3933{
3934 u32 reg;
3935 u16 word;
3936
3937 /*
3938 * Initialize all registers.
3939 */
3940 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3941 rt2800_init_registers(rt2x00dev) ||
3942 rt2800_init_bbp(rt2x00dev) ||
3943 rt2800_init_rfcsr(rt2x00dev)))
3944 return -EIO;
3945
3946 /*
3947 * Send signal to firmware during boot time.
3948 */
3949 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3950
3951 if (rt2x00_is_usb(rt2x00dev) &&
3952 (rt2x00_rt(rt2x00dev, RT3070) ||
3953 rt2x00_rt(rt2x00dev, RT3071) ||
3954 rt2x00_rt(rt2x00dev, RT3572))) {
3955 udelay(200);
3956 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3957 udelay(10);
3958 }
3959
3960 /*
3961 * Enable RX.
3962 */
3963 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3964 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3965 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3966 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3967
3968 udelay(50);
3969
3970 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3971 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3972 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3973 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3974 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3975 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3976
3977 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3978 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3979 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3980 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3981
3982 /*
3983 * Initialize LED control
3984 */
38c8a566
RJH		 3985 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3986 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 3987 word & 0xff, (word >> 8) & 0xff);
3988
38c8a566
RJH		 3989 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3990 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 3991 word & 0xff, (word >> 8) & 0xff);
3992
38c8a566
RJH		 3993 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3994 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 3995 word & 0xff, (word >> 8) & 0xff);
3996
3997 return 0;
3998}
3999EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4000
4001void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4002{
4003 u32 reg;
4004
f7b395e9 4005 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 4006
4007 /* Wait for DMA, ignore error */
4008 rt2800_wait_wpdma_ready(rt2x00dev);
4009
4010 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4011 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4012 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4013 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 4014}
4015EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 4016
30e84034
BZ		 4017int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4018{
4019 u32 reg;
4020
4021 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
4022
4023 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4024}
4025EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4026
4027static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4028{
4029 u32 reg;
4030
31a4cf1f
GW		 4031 mutex_lock(&rt2x00dev->csr_mutex);
4032
4033 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 4034 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4035 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4036 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 4037 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 4038
4039 /* Wait until the EEPROM has been loaded */
4040 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
4041
4042 /* Apparently the data is read from end to start */
daabead1
LF		 4043 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
4044 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 4045 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
daabead1
LF		 4046 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
4047 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4048 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
4049 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4050 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
4051 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 4052
4053 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 4054}
4055
4056void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4057{
4058 unsigned int i;
4059
4060 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4061 rt2800_efuse_read(rt2x00dev, i);
4062}
4063EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4064
38bd7b8a
BZ		 4065int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4066{
77c06c2c 4067 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 4068 u16 word;
4069 u8 *mac;
4070 u8 default_lna_gain;
4071
4072 /*
4073 * Start validation of the data that has been read.
4074 */
4075 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4076 if (!is_valid_ether_addr(mac)) {
4077 random_ether_addr(mac);
4078 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4079 }
4080
38c8a566 4081 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 4082 if (word == 0xffff) {
38c8a566
RJH		 4083 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4084 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4085 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4086 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a 4087 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 4088 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 4089 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 4090 /*
4091 * There is a max of 2 RX streams for RT28x0 series
4092 */
38c8a566
RJH		 4093 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4094 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4095 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 4096 }
4097
38c8a566 4098 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 4099 if (word == 0xffff) {
38c8a566
RJH		 4100 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4101 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4102 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4103 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4104 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4105 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4106 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4107 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4108 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4109 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4110 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4111 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4112 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4113 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4114 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4115 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
38bd7b8a
BZ		 4116 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4117 }
4118
4119 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4120 if ((word & 0x00ff) == 0x00ff) {
4121 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 4122 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4123 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4124 }
4125 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 4126 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4127 LED_MODE_TXRX_ACTIVITY);
4128 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4129 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
38c8a566
RJH		 4130 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4131 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4132 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec2d1791 4133 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 4134 }
4135
4136 /*
4137 * During the LNA validation we are going to use
4138 * lna0 as correct value. Note that EEPROM_LNA
4139 * is never validated.
4140 */
4141 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4142 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4143
4144 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4145 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4146 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4147 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4148 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4149 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4150
77c06c2c
GW		 4151 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4152 if ((word & 0x00ff) != 0x00ff) {
4153 drv_data->txmixer_gain_24g =
4154 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4155 } else {
4156 drv_data->txmixer_gain_24g = 0;
4157 }
4158
38bd7b8a
BZ		 4159 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4160 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4161 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4162 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4163 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4164 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4165 default_lna_gain);
4166 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4167
77c06c2c
GW		 4168 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4169 if ((word & 0x00ff) != 0x00ff) {
4170 drv_data->txmixer_gain_5g =
4171 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4172 } else {
4173 drv_data->txmixer_gain_5g = 0;
4174 }
4175
38bd7b8a
BZ		 4176 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4177 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4178 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4179 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4180 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4181 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4182
4183 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4184 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4185 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4186 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4187 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4188 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4189 default_lna_gain);
4190 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4191
4192 return 0;
4193}
4194EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4195
4196int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4197{
4198 u32 reg;
4199 u16 value;
4200 u16 eeprom;
4201
4202 /*
4203 * Read EEPROM word for configuration.
4204 */
38c8a566 4205 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
38bd7b8a
BZ		 4206
4207 /*
adde5882
GJ		 4208 * Identify RF chipset by EEPROM value
4209 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4210 * RT53xx: defined in "EEPROM_CHIP_ID" field
38bd7b8a 4211 */
38bd7b8a 4212 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2ed71884
JL		 4213 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4214 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
adde5882
GJ		 4215 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4216 else
4217 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
38bd7b8a 4218
49e721ec
GW		 4219 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4220 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4221
5aa57015
GW		 4222 switch (rt2x00dev->chip.rt) {
4223 case RT2860:
4224 case RT2872:
4225 case RT2883:
4226 case RT3070:
4227 case RT3071:
4228 case RT3090:
4229 case RT3390:
4230 case RT3572:
4231 case RT5390:
2ed71884 4232 case RT5392:
5aa57015
GW		 4233 break;
4234 default:
b6df7f1d 4235 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
49e721ec 4236 return -ENODEV;
f273fe55 4237 }
714fa663 4238
d331eb51
LF		 4239 switch (rt2x00dev->chip.rf) {
4240 case RF2820:
4241 case RF2850:
4242 case RF2720:
4243 case RF2750:
4244 case RF3020:
4245 case RF2020:
4246 case RF3021:
4247 case RF3022:
4248 case RF3052:
4249 case RF3320:
4250 case RF5370:
2ed71884 4251 case RF5372:
d331eb51
LF		 4252 case RF5390:
4253 break;
4254 default:
b6df7f1d 4255 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
d331eb51 4256 rt2x00dev->chip.rf);
38bd7b8a
BZ		 4257 return -ENODEV;
4258 }
4259
4260 /*
4261 * Identify default antenna configuration.
4262 */
d96aa640 4263 rt2x00dev->default_ant.tx_chain_num =
38c8a566 4264 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 4265 rt2x00dev->default_ant.rx_chain_num =
38c8a566 4266 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 4267
d96aa640
RJH		 4268 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4269
4270 if (rt2x00_rt(rt2x00dev, RT3070) ||
4271 rt2x00_rt(rt2x00dev, RT3090) ||
4272 rt2x00_rt(rt2x00dev, RT3390)) {
4273 value = rt2x00_get_field16(eeprom,
4274 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4275 switch (value) {
4276 case 0:
4277 case 1:
4278 case 2:
4279 rt2x00dev->default_ant.tx = ANTENNA_A;
4280 rt2x00dev->default_ant.rx = ANTENNA_A;
4281 break;
4282 case 3:
4283 rt2x00dev->default_ant.tx = ANTENNA_A;
4284 rt2x00dev->default_ant.rx = ANTENNA_B;
4285 break;
4286 }
4287 } else {
4288 rt2x00dev->default_ant.tx = ANTENNA_A;
4289 rt2x00dev->default_ant.rx = ANTENNA_A;
4290 }
4291
38bd7b8a 4292 /*
9328fdac 4293 * Determine external LNA informations.
38bd7b8a 4294 */
38c8a566 4295 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 4296 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 4297 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 4298 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 4299
4300 /*
4301 * Detect if this device has an hardware controlled radio.
4302 */
38c8a566 4303 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 4304 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 4305
fdbc7b0a
GW		 4306 /*
4307 * Detect if this device has Bluetooth co-existence.
4308 */
4309 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4310 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4311
9328fdac
GW		 4312 /*
4313 * Read frequency offset and RF programming sequence.
4314 */
4315 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4316 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4317
38bd7b8a
BZ		 4318 /*
4319 * Store led settings, for correct led behaviour.
4320 */
4321#ifdef CONFIG_RT2X00_LIB_LEDS
4322 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4323 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4324 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4325
9328fdac 4326 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 4327#endif /* CONFIG_RT2X00_LIB_LEDS */
4328
e90c54b2
RJH		 4329 /*
4330 * Check if support EIRP tx power limit feature.
4331 */
4332 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4333
4334 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4335 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 4336 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 4337
38bd7b8a
BZ		 4338 return 0;
4339}
4340EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4341
4da2933f 4342/*
55f9321a 4343 * RF value list for rt28xx
4da2933f
BZ		 4344 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4345 */
4346static const struct rf_channel rf_vals[] = {
4347 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4348 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4349 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4350 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4351 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4352 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4353 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4354 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4355 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4356 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4357 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4358 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4359 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4360 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4361
4362 /* 802.11 UNI / HyperLan 2 */
4363 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4364 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4365 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4366 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4367 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4368 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4369 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4370 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4371 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4372 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4373 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4374 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4375
4376 /* 802.11 HyperLan 2 */
4377 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4378 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4379 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4380 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4381 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4382 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4383 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4384 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4385 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4386 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4387 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4388 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4389 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4390 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4391 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4392 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4393
4394 /* 802.11 UNII */
4395 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4396 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4397 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4398 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4399 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4400 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4401 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4402 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4403 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4404 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4405 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4406
4407 /* 802.11 Japan */
4408 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4409 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4410 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4411 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4412 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4413 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4414 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4415};
4416
4417/*
55f9321a
ID		 4418 * RF value list for rt3xxx
4419 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 4420 */
55f9321a 4421static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 4422 {1, 241, 2, 2 },
4423 {2, 241, 2, 7 },
4424 {3, 242, 2, 2 },
4425 {4, 242, 2, 7 },
4426 {5, 243, 2, 2 },
4427 {6, 243, 2, 7 },
4428 {7, 244, 2, 2 },
4429 {8, 244, 2, 7 },
4430 {9, 245, 2, 2 },
4431 {10, 245, 2, 7 },
4432 {11, 246, 2, 2 },
4433 {12, 246, 2, 7 },
4434 {13, 247, 2, 2 },
4435 {14, 248, 2, 4 },
55f9321a
ID		 4436
4437 /* 802.11 UNI / HyperLan 2 */
4438 {36, 0x56, 0, 4},
4439 {38, 0x56, 0, 6},
4440 {40, 0x56, 0, 8},
4441 {44, 0x57, 0, 0},
4442 {46, 0x57, 0, 2},
4443 {48, 0x57, 0, 4},
4444 {52, 0x57, 0, 8},
4445 {54, 0x57, 0, 10},
4446 {56, 0x58, 0, 0},
4447 {60, 0x58, 0, 4},
4448 {62, 0x58, 0, 6},
4449 {64, 0x58, 0, 8},
4450
4451 /* 802.11 HyperLan 2 */
4452 {100, 0x5b, 0, 8},
4453 {102, 0x5b, 0, 10},
4454 {104, 0x5c, 0, 0},
4455 {108, 0x5c, 0, 4},
4456 {110, 0x5c, 0, 6},
4457 {112, 0x5c, 0, 8},
4458 {116, 0x5d, 0, 0},
4459 {118, 0x5d, 0, 2},
4460 {120, 0x5d, 0, 4},
4461 {124, 0x5d, 0, 8},
4462 {126, 0x5d, 0, 10},
4463 {128, 0x5e, 0, 0},
4464 {132, 0x5e, 0, 4},
4465 {134, 0x5e, 0, 6},
4466 {136, 0x5e, 0, 8},
4467 {140, 0x5f, 0, 0},
4468
4469 /* 802.11 UNII */
4470 {149, 0x5f, 0, 9},
4471 {151, 0x5f, 0, 11},
4472 {153, 0x60, 0, 1},
4473 {157, 0x60, 0, 5},
4474 {159, 0x60, 0, 7},
4475 {161, 0x60, 0, 9},
4476 {165, 0x61, 0, 1},
4477 {167, 0x61, 0, 3},
4478 {169, 0x61, 0, 5},
4479 {171, 0x61, 0, 7},
4480 {173, 0x61, 0, 9},
4da2933f
BZ		 4481};
4482
4483int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4484{
4da2933f
BZ		 4485 struct hw_mode_spec *spec = &rt2x00dev->spec;
4486 struct channel_info *info;
8d1331b3
ID		 4487 char *default_power1;
4488 char *default_power2;
4da2933f
BZ		 4489 unsigned int i;
4490 u16 eeprom;
4491
93b6bd26
GW		 4492 /*
4493 * Disable powersaving as default on PCI devices.
4494 */
cea90e55 4495 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 4496 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4497
4da2933f
BZ		 4498 /*
4499 * Initialize all hw fields.
4500 */
4501 rt2x00dev->hw->flags =
4da2933f
BZ		 4502 IEEE80211_HW_SIGNAL_DBM |
4503 IEEE80211_HW_SUPPORTS_PS |
1df90809 4504 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8
HS		 4505 IEEE80211_HW_AMPDU_AGGREGATION |
4506 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4507
5a5b6ed6
HS		 4508 /*
4509 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4510 * unless we are capable of sending the buffered frames out after the
4511 * DTIM transmission using rt2x00lib_beacondone. This will send out
4512 * multicast and broadcast traffic immediately instead of buffering it
4513 * infinitly and thus dropping it after some time.
4514 */
4515 if (!rt2x00_is_usb(rt2x00dev))
4516 rt2x00dev->hw->flags |=
4517 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 4518
4da2933f
BZ		 4519 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4520 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4521 rt2x00_eeprom_addr(rt2x00dev,
4522 EEPROM_MAC_ADDR_0));
4523
3f2bee24
HS		 4524 /*
4525 * As rt2800 has a global fallback table we cannot specify
4526 * more then one tx rate per frame but since the hw will
4527 * try several rates (based on the fallback table) we should
ba3b9e5e 4528 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 4529 * we are going to try. Otherwise mac80211 will truncate our
4530 * reported tx rates and the rc algortihm will end up with
4531 * incorrect data.
4532 */
ba3b9e5e
HS		 4533 rt2x00dev->hw->max_rates = 1;
4534 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 4535 rt2x00dev->hw->max_rate_tries = 1;
4536
38c8a566 4537 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4da2933f
BZ		 4538
4539 /*
4540 * Initialize hw_mode information.
4541 */
4542 spec->supported_bands = SUPPORT_BAND_2GHZ;
4543 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4544
5122d898 4545 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 4546 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 4547 spec->num_channels = 14;
4548 spec->channels = rf_vals;
55f9321a
ID		 4549 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4550 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 4551 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4552 spec->num_channels = ARRAY_SIZE(rf_vals);
4553 spec->channels = rf_vals;
5122d898
GW		 4554 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4555 rt2x00_rf(rt2x00dev, RF2020) ||
4556 rt2x00_rf(rt2x00dev, RF3021) ||
f93bc9b3 4557 rt2x00_rf(rt2x00dev, RF3022) ||
adde5882 4558 rt2x00_rf(rt2x00dev, RF3320) ||
aca355b9 4559 rt2x00_rf(rt2x00dev, RF5370) ||
2ed71884 4560 rt2x00_rf(rt2x00dev, RF5372) ||
adde5882 4561 rt2x00_rf(rt2x00dev, RF5390)) {
55f9321a
ID		 4562 spec->num_channels = 14;
4563 spec->channels = rf_vals_3x;
4564 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4565 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4566 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4567 spec->channels = rf_vals_3x;
4da2933f
BZ		 4568 }
4569
4570 /*
4571 * Initialize HT information.
4572 */
5122d898 4573 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 4574 spec->ht.ht_supported = true;
4575 else
4576 spec->ht.ht_supported = false;
4577
4da2933f 4578 spec->ht.cap =
06443e46 4579 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 4580 IEEE80211_HT_CAP_GRN_FLD |
4581 IEEE80211_HT_CAP_SGI_20 |
aa674631 4582 IEEE80211_HT_CAP_SGI_40;
22cabaa6 4583
38c8a566 4584 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
22cabaa6
HS		 4585 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4586
aa674631 4587 spec->ht.cap |=
38c8a566 4588 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
aa674631
ID		 4589 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4590
4da2933f
BZ		 4591 spec->ht.ampdu_factor = 3;
4592 spec->ht.ampdu_density = 4;
4593 spec->ht.mcs.tx_params =
4594 IEEE80211_HT_MCS_TX_DEFINED |
4595 IEEE80211_HT_MCS_TX_RX_DIFF |
38c8a566 4596 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4da2933f
BZ		 4597 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4598
38c8a566 4599 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4da2933f
BZ		 4600 case 3:
4601 spec->ht.mcs.rx_mask[2] = 0xff;
4602 case 2:
4603 spec->ht.mcs.rx_mask[1] = 0xff;
4604 case 1:
4605 spec->ht.mcs.rx_mask[0] = 0xff;
4606 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4607 break;
4608 }
4609
4610 /*
4611 * Create channel information array
4612 */
baeb2ffa 4613 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 4614 if (!info)
4615 return -ENOMEM;
4616
4617 spec->channels_info = info;
4618
8d1331b3
ID		 4619 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4620 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f
BZ		 4621
4622 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 4623 info[i].default_power1 = default_power1[i];
4624 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4625 }
4626
4627 if (spec->num_channels > 14) {
8d1331b3
ID		 4628 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4629 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4da2933f
BZ		 4630
4631 for (i = 14; i < spec->num_channels; i++) {
e90c54b2
RJH		 4632 info[i].default_power1 = default_power1[i];
4633 info[i].default_power2 = default_power2[i];
4da2933f
BZ		 4634 }
4635 }
4636
2e9c43dd
JL		 4637 switch (rt2x00dev->chip.rf) {
4638 case RF2020:
4639 case RF3020:
4640 case RF3021:
4641 case RF3022:
4642 case RF3320:
4643 case RF3052:
4644 case RF5370:
4645 case RF5372:
4646 case RF5390:
4647 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4648 break;
4649 }
4650
4da2933f
BZ		 4651 return 0;
4652}
4653EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4654
2ce33995
BZ		 4655/*
4656 * IEEE80211 stack callback functions.
4657 */
e783619e
HS		 4658void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4659 u16 *iv16)
2ce33995
BZ		 4660{
4661 struct rt2x00_dev *rt2x00dev = hw->priv;
4662 struct mac_iveiv_entry iveiv_entry;
4663 u32 offset;
4664
4665 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4666 rt2800_register_multiread(rt2x00dev, offset,
4667 &iveiv_entry, sizeof(iveiv_entry));
4668
855da5e0
JL		 4669 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4670 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 4671}
e783619e 4672EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 4673
e783619e 4674int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 4675{
4676 struct rt2x00_dev *rt2x00dev = hw->priv;
4677 u32 reg;
4678 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4679
4680 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4681 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4682 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4683
4684 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4685 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4686 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4687
4688 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4689 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4690 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4691
4692 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4693 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4694 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4695
4696 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4697 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4698 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4699
4700 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4701 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4702 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4703
4704 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4705 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4706 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4707
4708 return 0;
4709}
e783619e 4710EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 4711
8a3a3c85
EP		 4712int rt2800_conf_tx(struct ieee80211_hw *hw,
4713 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 4714 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 4715{
4716 struct rt2x00_dev *rt2x00dev = hw->priv;
4717 struct data_queue *queue;
4718 struct rt2x00_field32 field;
4719 int retval;
4720 u32 reg;
4721 u32 offset;
4722
4723 /*
4724 * First pass the configuration through rt2x00lib, that will
4725 * update the queue settings and validate the input. After that
4726 * we are free to update the registers based on the value
4727 * in the queue parameter.
4728 */
8a3a3c85 4729 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 4730 if (retval)
4731 return retval;
4732
4733 /*
4734 * We only need to perform additional register initialization
4735 * for WMM queues/
4736 */
4737 if (queue_idx >= 4)
4738 return 0;
4739
11f818e0 4740 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 4741
4742 /* Update WMM TXOP register */
4743 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4744 field.bit_offset = (queue_idx & 1) * 16;
4745 field.bit_mask = 0xffff << field.bit_offset;
4746
4747 rt2800_register_read(rt2x00dev, offset, &reg);
4748 rt2x00_set_field32(&reg, field, queue->txop);
4749 rt2800_register_write(rt2x00dev, offset, reg);
4750
4751 /* Update WMM registers */
4752 field.bit_offset = queue_idx * 4;
4753 field.bit_mask = 0xf << field.bit_offset;
4754
4755 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4756 rt2x00_set_field32(&reg, field, queue->aifs);
4757 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4758
4759 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4760 rt2x00_set_field32(&reg, field, queue->cw_min);
4761 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4762
4763 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4764 rt2x00_set_field32(&reg, field, queue->cw_max);
4765 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4766
4767 /* Update EDCA registers */
4768 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4769
4770 rt2800_register_read(rt2x00dev, offset, &reg);
4771 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4772 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4773 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4774 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4775 rt2800_register_write(rt2x00dev, offset, reg);
4776
4777 return 0;
4778}
e783619e 4779EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 4780
37a41b4a 4781u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 4782{
4783 struct rt2x00_dev *rt2x00dev = hw->priv;
4784 u64 tsf;
4785 u32 reg;
4786
4787 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4788 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4789 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4790 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4791
4792 return tsf;
4793}
e783619e 4794EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 4795
e783619e
HS		 4796int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4797 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4798 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4799 u8 buf_size)
1df90809 4800{
af35323d 4801 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 4802 int ret = 0;
4803
af35323d
HS		 4804 /*
4805 * Don't allow aggregation for stations the hardware isn't aware
4806 * of because tx status reports for frames to an unknown station
4807 * always contain wcid=255 and thus we can't distinguish between
4808 * multiple stations which leads to unwanted situations when the
4809 * hw reorders frames due to aggregation.
4810 */
4811 if (sta_priv->wcid < 0)
4812 return 1;
4813
1df90809
HS		 4814 switch (action) {
4815 case IEEE80211_AMPDU_RX_START:
4816 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 4817 /*
4818 * The hw itself takes care of setting up BlockAck mechanisms.
4819 * So, we only have to allow mac80211 to nagotiate a BlockAck
4820 * agreement. Once that is done, the hw will BlockAck incoming
4821 * AMPDUs without further setup.
4822 */
1df90809
HS		 4823 break;
4824 case IEEE80211_AMPDU_TX_START:
4825 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4826 break;
4827 case IEEE80211_AMPDU_TX_STOP:
4828 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4829 break;
4830 case IEEE80211_AMPDU_TX_OPERATIONAL:
4831 break;
4832 default:
4e9e58c6 4833 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 4834 }
4835
4836 return ret;
4837}
e783619e 4838EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 4839
977206d7
HS		 4840int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4841 struct survey_info *survey)
4842{
4843 struct rt2x00_dev *rt2x00dev = hw->priv;
4844 struct ieee80211_conf *conf = &hw->conf;
4845 u32 idle, busy, busy_ext;
4846
4847 if (idx != 0)
4848 return -ENOENT;
4849
4850 survey->channel = conf->channel;
4851
4852 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4853 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4854 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4855
4856 if (idle || busy) {
4857 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4858 SURVEY_INFO_CHANNEL_TIME_BUSY |
4859 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4860
4861 survey->channel_time = (idle + busy) / 1000;
4862 survey->channel_time_busy = busy / 1000;
4863 survey->channel_time_ext_busy = busy_ext / 1000;
4864 }
4865
9931df26
HS		 4866 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4867 survey->filled |= SURVEY_INFO_IN_USE;
4868
977206d7
HS		 4869 return 0;
4870
4871}
4872EXPORT_SYMBOL_GPL(rt2800_get_survey);
4873
a5ea2f02
ID		 4874MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4875MODULE_VERSION(DRV_VERSION);
4876MODULE_DESCRIPTION("Ralink RT2800 library");
4877MODULE_LICENSE("GPL");
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