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rt2x00: fix beacon reset on rt2800
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
a5ea2f02 2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 5
9c9a0d14 6 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
81 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 102 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
104
105 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
106 }
107
108 mutex_unlock(&rt2x00dev->csr_mutex);
109}
89297425 110
fcf51541
BZ		 111static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
112 const unsigned int word, u8 *value)
89297425
BZ		 113{
114 u32 reg;
115
116 mutex_lock(&rt2x00dev->csr_mutex);
117
118 /*
119 * Wait until the BBP becomes available, afterwards we
120 * can safely write the read request into the register.
121 * After the data has been written, we wait until hardware
122 * returns the correct value, if at any time the register
123 * doesn't become available in time, reg will be 0xffffffff
124 * which means we return 0xff to the caller.
125 */
126 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 131 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142}
89297425 143
fcf51541
BZ		 144static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
89297425
BZ		 146{
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166}
89297425 167
fcf51541
BZ		 168static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
89297425
BZ		 170{
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197}
89297425 198
fcf51541
BZ		 199static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
89297425
BZ		 201{
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222}
89297425
BZ		 223
224void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
227{
228 u32 reg;
229
ee303e54 230 /*
cea90e55 231 * SOC devices don't support MCU requests.
ee303e54 232 */
cea90e55 233 if (rt2x00_is_soc(rt2x00dev))
ee303e54 234 return;
89297425
BZ		 235
236 mutex_lock(&rt2x00dev->csr_mutex);
237
238 /*
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
241 */
242 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249 reg = 0;
250 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252 }
253
254 mutex_unlock(&rt2x00dev->csr_mutex);
255}
256EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 257
67a4c1e2
GW		 258int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
259{
260 unsigned int i;
261 u32 reg;
262
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
265 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
266 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
267 return 0;
268
269 msleep(1);
270 }
271
272 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
273 return -EACCES;
274}
275EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
276
0b8004aa 277void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
59679b91 278{
59679b91
GW		 279 u32 word;
280
281 /*
282 * Initialize TX Info descriptor
283 */
284 rt2x00_desc_read(txwi, 0, &word);
285 rt2x00_set_field32(&word, TXWI_W0_FRAG,
286 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
287 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
288 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
289 rt2x00_set_field32(&word, TXWI_W0_TS,
290 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
291 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
292 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
293 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
294 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
295 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
296 rt2x00_set_field32(&word, TXWI_W0_BW,
297 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
298 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
299 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
300 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
301 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
302 rt2x00_desc_write(txwi, 0, word);
303
304 rt2x00_desc_read(txwi, 1, &word);
305 rt2x00_set_field32(&word, TXWI_W1_ACK,
306 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
307 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
308 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
309 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
310 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
311 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
312 txdesc->key_idx : 0xff);
313 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
314 txdesc->length);
315 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
316 rt2x00_desc_write(txwi, 1, word);
317
318 /*
319 * Always write 0 to IV/EIV fields, hardware will insert the IV
320 * from the IVEIV register when TXD_W3_WIV is set to 0.
321 * When TXD_W3_WIV is set to 1 it will use the IV data
322 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
323 * crypto entry in the registers should be used to encrypt the frame.
324 */
325 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
326 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
327}
328EXPORT_SYMBOL_GPL(rt2800_write_txwi);
329
2de64dd2
GW		 330void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
331{
332 __le32 *rxwi = (__le32 *) skb->data;
333 u32 word;
334
335 rt2x00_desc_read(rxwi, 0, &word);
336
337 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
338 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
339
340 rt2x00_desc_read(rxwi, 1, &word);
341
342 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
343 rxdesc->flags |= RX_FLAG_SHORT_GI;
344
345 if (rt2x00_get_field32(word, RXWI_W1_BW))
346 rxdesc->flags |= RX_FLAG_40MHZ;
347
348 /*
349 * Detect RX rate, always use MCS as signal type.
350 */
351 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
352 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
353 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
354
355 /*
356 * Mask of 0x8 bit to remove the short preamble flag.
357 */
358 if (rxdesc->rate_mode == RATE_MODE_CCK)
359 rxdesc->signal &= ~0x8;
360
361 rt2x00_desc_read(rxwi, 2, &word);
362
363 rxdesc->rssi =
364 (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
365 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
366
367 /*
368 * Remove RXWI descriptor from start of buffer.
369 */
370 skb_pull(skb, RXWI_DESC_SIZE);
371}
372EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
373
f0194b2d
GW		 374void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
375{
376 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
377 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
378 unsigned int beacon_base;
379 u32 reg;
380
381 /*
382 * Disable beaconing while we are reloading the beacon data,
383 * otherwise we might be sending out invalid data.
384 */
385 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
386 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
387 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
388
389 /*
390 * Add space for the TXWI in front of the skb.
391 */
392 skb_push(entry->skb, TXWI_DESC_SIZE);
393 memset(entry->skb, 0, TXWI_DESC_SIZE);
394
395 /*
396 * Register descriptor details in skb frame descriptor.
397 */
398 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
399 skbdesc->desc = entry->skb->data;
400 skbdesc->desc_len = TXWI_DESC_SIZE;
401
402 /*
403 * Add the TXWI for the beacon to the skb.
404 */
405 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
406
407 /*
408 * Dump beacon to userspace through debugfs.
409 */
410 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
411
412 /*
413 * Write entire beacon with TXWI to register.
414 */
415 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
416 rt2800_register_multiwrite(rt2x00dev, beacon_base,
417 entry->skb->data, entry->skb->len);
418
419 /*
420 * Enable beaconing again.
421 */
422 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
423 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
424 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
425 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
426
427 /*
428 * Clean up beacon skb.
429 */
430 dev_kfree_skb_any(entry->skb);
431 entry->skb = NULL;
432}
433EXPORT_SYMBOL(rt2800_write_beacon);
434
fdb87251
HS		 435static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
436 unsigned int beacon_base)
437{
438 int i;
439
440 /*
441 * For the Beacon base registers we only need to clear
442 * the whole TXWI which (when set to 0) will invalidate
443 * the entire beacon.
444 */
445 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
446 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
447}
448
f4450616
BZ		 449#ifdef CONFIG_RT2X00_LIB_DEBUGFS
450const struct rt2x00debug rt2800_rt2x00debug = {
451 .owner = THIS_MODULE,
452 .csr = {
453 .read = rt2800_register_read,
454 .write = rt2800_register_write,
455 .flags = RT2X00DEBUGFS_OFFSET,
456 .word_base = CSR_REG_BASE,
457 .word_size = sizeof(u32),
458 .word_count = CSR_REG_SIZE / sizeof(u32),
459 },
460 .eeprom = {
461 .read = rt2x00_eeprom_read,
462 .write = rt2x00_eeprom_write,
463 .word_base = EEPROM_BASE,
464 .word_size = sizeof(u16),
465 .word_count = EEPROM_SIZE / sizeof(u16),
466 },
467 .bbp = {
468 .read = rt2800_bbp_read,
469 .write = rt2800_bbp_write,
470 .word_base = BBP_BASE,
471 .word_size = sizeof(u8),
472 .word_count = BBP_SIZE / sizeof(u8),
473 },
474 .rf = {
475 .read = rt2x00_rf_read,
476 .write = rt2800_rf_write,
477 .word_base = RF_BASE,
478 .word_size = sizeof(u32),
479 .word_count = RF_SIZE / sizeof(u32),
480 },
481};
482EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
483#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
484
485int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
486{
487 u32 reg;
488
489 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
490 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
491}
492EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
493
494#ifdef CONFIG_RT2X00_LIB_LEDS
495static void rt2800_brightness_set(struct led_classdev *led_cdev,
496 enum led_brightness brightness)
497{
498 struct rt2x00_led *led =
499 container_of(led_cdev, struct rt2x00_led, led_dev);
500 unsigned int enabled = brightness != LED_OFF;
501 unsigned int bg_mode =
502 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
503 unsigned int polarity =
504 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
505 EEPROM_FREQ_LED_POLARITY);
506 unsigned int ledmode =
507 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
508 EEPROM_FREQ_LED_MODE);
509
510 if (led->type == LED_TYPE_RADIO) {
511 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
512 enabled ? 0x20 : 0);
513 } else if (led->type == LED_TYPE_ASSOC) {
514 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
515 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
516 } else if (led->type == LED_TYPE_QUALITY) {
517 /*
518 * The brightness is divided into 6 levels (0 - 5),
519 * The specs tell us the following levels:
520 * 0, 1 ,3, 7, 15, 31
521 * to determine the level in a simple way we can simply
522 * work with bitshifting:
523 * (1 << level) - 1
524 */
525 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
526 (1 << brightness / (LED_FULL / 6)) - 1,
527 polarity);
528 }
529}
530
531static int rt2800_blink_set(struct led_classdev *led_cdev,
532 unsigned long *delay_on, unsigned long *delay_off)
533{
534 struct rt2x00_led *led =
535 container_of(led_cdev, struct rt2x00_led, led_dev);
536 u32 reg;
537
538 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
539 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
540 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 541 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
542
543 return 0;
544}
545
b3579d6a 546static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 547 struct rt2x00_led *led, enum led_type type)
548{
549 led->rt2x00dev = rt2x00dev;
550 led->type = type;
551 led->led_dev.brightness_set = rt2800_brightness_set;
552 led->led_dev.blink_set = rt2800_blink_set;
553 led->flags = LED_INITIALIZED;
554}
f4450616
BZ		 555#endif /* CONFIG_RT2X00_LIB_LEDS */
556
557/*
558 * Configuration handlers.
559 */
560static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
561 struct rt2x00lib_crypto *crypto,
562 struct ieee80211_key_conf *key)
563{
564 struct mac_wcid_entry wcid_entry;
565 struct mac_iveiv_entry iveiv_entry;
566 u32 offset;
567 u32 reg;
568
569 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
570
e4a0ab34
ID		 571 if (crypto->cmd == SET_KEY) {
572 rt2800_register_read(rt2x00dev, offset, &reg);
573 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
574 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
575 /*
576 * Both the cipher as the BSS Idx numbers are split in a main
577 * value of 3 bits, and a extended field for adding one additional
578 * bit to the value.
579 */
580 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
581 (crypto->cipher & 0x7));
582 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
583 (crypto->cipher & 0x8) >> 3);
584 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
585 (crypto->bssidx & 0x7));
586 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
587 (crypto->bssidx & 0x8) >> 3);
588 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
589 rt2800_register_write(rt2x00dev, offset, reg);
590 } else {
591 rt2800_register_write(rt2x00dev, offset, 0);
592 }
f4450616
BZ		 593
594 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
595
596 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
597 if ((crypto->cipher == CIPHER_TKIP) ||
598 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
599 (crypto->cipher == CIPHER_AES))
600 iveiv_entry.iv[3] |= 0x20;
601 iveiv_entry.iv[3] |= key->keyidx << 6;
602 rt2800_register_multiwrite(rt2x00dev, offset,
603 &iveiv_entry, sizeof(iveiv_entry));
604
605 offset = MAC_WCID_ENTRY(key->hw_key_idx);
606
607 memset(&wcid_entry, 0, sizeof(wcid_entry));
608 if (crypto->cmd == SET_KEY)
609 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
610 rt2800_register_multiwrite(rt2x00dev, offset,
611 &wcid_entry, sizeof(wcid_entry));
612}
613
614int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
615 struct rt2x00lib_crypto *crypto,
616 struct ieee80211_key_conf *key)
617{
618 struct hw_key_entry key_entry;
619 struct rt2x00_field32 field;
620 u32 offset;
621 u32 reg;
622
623 if (crypto->cmd == SET_KEY) {
624 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
625
626 memcpy(key_entry.key, crypto->key,
627 sizeof(key_entry.key));
628 memcpy(key_entry.tx_mic, crypto->tx_mic,
629 sizeof(key_entry.tx_mic));
630 memcpy(key_entry.rx_mic, crypto->rx_mic,
631 sizeof(key_entry.rx_mic));
632
633 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
634 rt2800_register_multiwrite(rt2x00dev, offset,
635 &key_entry, sizeof(key_entry));
636 }
637
638 /*
639 * The cipher types are stored over multiple registers
640 * starting with SHARED_KEY_MODE_BASE each word will have
641 * 32 bits and contains the cipher types for 2 bssidx each.
642 * Using the correct defines correctly will cause overhead,
643 * so just calculate the correct offset.
644 */
645 field.bit_offset = 4 * (key->hw_key_idx % 8);
646 field.bit_mask = 0x7 << field.bit_offset;
647
648 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
649
650 rt2800_register_read(rt2x00dev, offset, &reg);
651 rt2x00_set_field32(&reg, field,
652 (crypto->cmd == SET_KEY) * crypto->cipher);
653 rt2800_register_write(rt2x00dev, offset, reg);
654
655 /*
656 * Update WCID information
657 */
658 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
659
660 return 0;
661}
662EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
663
664int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_crypto *crypto,
666 struct ieee80211_key_conf *key)
667{
668 struct hw_key_entry key_entry;
669 u32 offset;
670
671 if (crypto->cmd == SET_KEY) {
672 /*
673 * 1 pairwise key is possible per AID, this means that the AID
674 * equals our hw_key_idx. Make sure the WCID starts _after_ the
675 * last possible shared key entry.
676 */
677 if (crypto->aid > (256 - 32))
678 return -ENOSPC;
679
680 key->hw_key_idx = 32 + crypto->aid;
681
682 memcpy(key_entry.key, crypto->key,
683 sizeof(key_entry.key));
684 memcpy(key_entry.tx_mic, crypto->tx_mic,
685 sizeof(key_entry.tx_mic));
686 memcpy(key_entry.rx_mic, crypto->rx_mic,
687 sizeof(key_entry.rx_mic));
688
689 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
690 rt2800_register_multiwrite(rt2x00dev, offset,
691 &key_entry, sizeof(key_entry));
692 }
693
694 /*
695 * Update WCID information
696 */
697 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
698
699 return 0;
700}
701EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
702
703void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
704 const unsigned int filter_flags)
705{
706 u32 reg;
707
708 /*
709 * Start configuration steps.
710 * Note that the version error will always be dropped
711 * and broadcast frames will always be accepted since
712 * there is no filter for it at this time.
713 */
714 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
715 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
716 !(filter_flags & FIF_FCSFAIL));
717 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
718 !(filter_flags & FIF_PLCPFAIL));
719 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
720 !(filter_flags & FIF_PROMISC_IN_BSS));
721 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
722 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
723 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
724 !(filter_flags & FIF_ALLMULTI));
725 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
726 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
727 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
728 !(filter_flags & FIF_CONTROL));
729 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
730 !(filter_flags & FIF_CONTROL));
731 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
732 !(filter_flags & FIF_CONTROL));
733 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
734 !(filter_flags & FIF_CONTROL));
735 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
736 !(filter_flags & FIF_CONTROL));
737 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
738 !(filter_flags & FIF_PSPOLL));
739 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
740 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
741 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
742 !(filter_flags & FIF_CONTROL));
743 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
744}
745EXPORT_SYMBOL_GPL(rt2800_config_filter);
746
747void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
748 struct rt2x00intf_conf *conf, const unsigned int flags)
749{
f4450616
BZ		 750 u32 reg;
751
752 if (flags & CONFIG_UPDATE_TYPE) {
753 /*
754 * Clear current synchronisation setup.
f4450616 755 */
fdb87251
HS		 756 rt2800_clear_beacon(rt2x00dev,
757 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 758 /*
759 * Enable synchronisation.
760 */
761 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
762 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
763 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 764 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
765 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 766 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
767 }
768
769 if (flags & CONFIG_UPDATE_MAC) {
770 reg = le32_to_cpu(conf->mac[1]);
771 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
772 conf->mac[1] = cpu_to_le32(reg);
773
774 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
775 conf->mac, sizeof(conf->mac));
776 }
777
778 if (flags & CONFIG_UPDATE_BSSID) {
779 reg = le32_to_cpu(conf->bssid[1]);
d440cb9e
ID		 780 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
781 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
f4450616
BZ		 782 conf->bssid[1] = cpu_to_le32(reg);
783
784 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
785 conf->bssid, sizeof(conf->bssid));
786 }
787}
788EXPORT_SYMBOL_GPL(rt2800_config_intf);
789
790void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
791{
792 u32 reg;
793
f4450616
BZ		 794 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
795 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
796 !!erp->short_preamble);
797 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
798 !!erp->short_preamble);
799 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
800
801 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
802 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
803 erp->cts_protection ? 2 : 0);
804 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
805
806 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
807 erp->basic_rates);
808 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
809
810 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
811 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 812 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
813
814 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 815 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 816 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
817
818 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
819 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
820 erp->beacon_int * 16);
821 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
822}
823EXPORT_SYMBOL_GPL(rt2800_config_erp);
824
825void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
826{
827 u8 r1;
828 u8 r3;
829
830 rt2800_bbp_read(rt2x00dev, 1, &r1);
831 rt2800_bbp_read(rt2x00dev, 3, &r3);
832
833 /*
834 * Configure the TX antenna.
835 */
836 switch ((int)ant->tx) {
837 case 1:
838 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 839 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 840 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
841 break;
842 case 2:
843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
844 break;
845 case 3:
846 /* Do nothing */
847 break;
848 }
849
850 /*
851 * Configure the RX antenna.
852 */
853 switch ((int)ant->rx) {
854 case 1:
855 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
856 break;
857 case 2:
858 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
859 break;
860 case 3:
861 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
862 break;
863 }
864
865 rt2800_bbp_write(rt2x00dev, 3, r3);
866 rt2800_bbp_write(rt2x00dev, 1, r1);
867}
868EXPORT_SYMBOL_GPL(rt2800_config_ant);
869
870static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
871 struct rt2x00lib_conf *libconf)
872{
873 u16 eeprom;
874 short lna_gain;
875
876 if (libconf->rf.channel <= 14) {
877 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
878 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
879 } else if (libconf->rf.channel <= 64) {
880 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
881 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
882 } else if (libconf->rf.channel <= 128) {
883 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
884 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
885 } else {
886 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
887 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
888 }
889
890 rt2x00dev->lna_gain = lna_gain;
891}
892
06855ef4
GW		 893static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
894 struct ieee80211_conf *conf,
895 struct rf_channel *rf,
896 struct channel_info *info)
f4450616
BZ		 897{
898 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
899
900 if (rt2x00dev->default_ant.tx == 1)
901 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
902
903 if (rt2x00dev->default_ant.rx == 1) {
904 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
905 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
906 } else if (rt2x00dev->default_ant.rx == 2)
907 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
908
909 if (rf->channel > 14) {
910 /*
911 * When TX power is below 0, we should increase it by 7 to
912 * make it a positive value (Minumum value is -7).
913 * However this means that values between 0 and 7 have
914 * double meaning, and we should set a 7DBm boost flag.
915 */
916 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
917 (info->tx_power1 >= 0));
918
919 if (info->tx_power1 < 0)
920 info->tx_power1 += 7;
921
922 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
923 TXPOWER_A_TO_DEV(info->tx_power1));
924
925 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
926 (info->tx_power2 >= 0));
927
928 if (info->tx_power2 < 0)
929 info->tx_power2 += 7;
930
931 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
932 TXPOWER_A_TO_DEV(info->tx_power2));
933 } else {
934 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
935 TXPOWER_G_TO_DEV(info->tx_power1));
936 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
937 TXPOWER_G_TO_DEV(info->tx_power2));
938 }
939
940 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
941
942 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
943 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
944 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
945 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
946
947 udelay(200);
948
949 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
950 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
951 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
952 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
953
954 udelay(200);
955
956 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
957 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
958 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
959 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
960}
961
06855ef4
GW		 962static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
963 struct ieee80211_conf *conf,
964 struct rf_channel *rf,
965 struct channel_info *info)
f4450616
BZ		 966{
967 u8 rfcsr;
968
969 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 970 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 971
972 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 973 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 974 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
975
976 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
977 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
978 TXPOWER_G_TO_DEV(info->tx_power1));
979 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
980
5a673964
HS		 981 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
982 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
983 TXPOWER_G_TO_DEV(info->tx_power2));
984 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
985
f4450616
BZ		 986 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
987 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
988 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
989
990 rt2800_rfcsr_write(rt2x00dev, 24,
991 rt2x00dev->calibration[conf_is_ht40(conf)]);
992
71976907 993 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 994 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 995 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 996}
997
998static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
999 struct ieee80211_conf *conf,
1000 struct rf_channel *rf,
1001 struct channel_info *info)
1002{
1003 u32 reg;
1004 unsigned int tx_pin;
1005 u8 bbp;
1006
06855ef4
GW		 1007 if (rt2x00_rf(rt2x00dev, RF2020) ||
1008 rt2x00_rf(rt2x00dev, RF3020) ||
1009 rt2x00_rf(rt2x00dev, RF3021) ||
1010 rt2x00_rf(rt2x00dev, RF3022))
1011 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1012 else
06855ef4 1013 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1014
1015 /*
1016 * Change BBP settings
1017 */
1018 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1019 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1020 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1021 rt2800_bbp_write(rt2x00dev, 86, 0);
1022
1023 if (rf->channel <= 14) {
1024 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1025 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1026 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1027 } else {
1028 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1029 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1030 }
1031 } else {
1032 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1033
1034 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1035 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1036 else
1037 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1038 }
1039
1040 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1041 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1042 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1043 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1044 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1045
1046 tx_pin = 0;
1047
1048 /* Turn on unused PA or LNA when not using 1T or 1R */
1049 if (rt2x00dev->default_ant.tx != 1) {
1050 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1051 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1052 }
1053
1054 /* Turn on unused PA or LNA when not using 1T or 1R */
1055 if (rt2x00dev->default_ant.rx != 1) {
1056 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1057 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1058 }
1059
1060 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1061 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1062 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1063 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1064 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1065 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1066
1067 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1068
1069 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1070 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1071 rt2800_bbp_write(rt2x00dev, 4, bbp);
1072
1073 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1074 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1075 rt2800_bbp_write(rt2x00dev, 3, bbp);
1076
8d0c9b65 1077 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1078 if (conf_is_ht40(conf)) {
1079 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1080 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1081 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1082 } else {
1083 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1084 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1085 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1086 }
1087 }
1088
1089 msleep(1);
1090}
1091
1092static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1093 const int txpower)
1094{
1095 u32 reg;
1096 u32 value = TXPOWER_G_TO_DEV(txpower);
1097 u8 r1;
1098
1099 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1100 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1101 rt2800_bbp_write(rt2x00dev, 1, r1);
1102
1103 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1104 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1105 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1106 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1107 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1108 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1109 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1110 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1111 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1112 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1113
1114 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1115 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1116 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1117 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1118 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1119 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1120 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1121 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1122 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1123 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1124
1125 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1126 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1127 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1128 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1129 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1130 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1131 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1132 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1133 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1134 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1135
1136 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1137 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1138 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1139 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1140 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1141 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1142 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1143 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1144 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1145 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1146
1147 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1148 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1149 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1150 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1151 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1152 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1153}
1154
1155static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1156 struct rt2x00lib_conf *libconf)
1157{
1158 u32 reg;
1159
1160 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1161 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1162 libconf->conf->short_frame_max_tx_count);
1163 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1164 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1165 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1166}
1167
1168static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1169 struct rt2x00lib_conf *libconf)
1170{
1171 enum dev_state state =
1172 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1173 STATE_SLEEP : STATE_AWAKE;
1174 u32 reg;
1175
1176 if (state == STATE_SLEEP) {
1177 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1178
1179 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1180 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1181 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1182 libconf->conf->listen_interval - 1);
1183 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1184 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1185
1186 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1187 } else {
f4450616
BZ		 1188 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1189 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1190 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1191 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1192 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1193
1194 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1195 }
1196}
1197
1198void rt2800_config(struct rt2x00_dev *rt2x00dev,
1199 struct rt2x00lib_conf *libconf,
1200 const unsigned int flags)
1201{
1202 /* Always recalculate LNA gain before changing configuration */
1203 rt2800_config_lna_gain(rt2x00dev, libconf);
1204
1205 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1206 rt2800_config_channel(rt2x00dev, libconf->conf,
1207 &libconf->rf, &libconf->channel);
1208 if (flags & IEEE80211_CONF_CHANGE_POWER)
1209 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1210 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1211 rt2800_config_retry_limit(rt2x00dev, libconf);
1212 if (flags & IEEE80211_CONF_CHANGE_PS)
1213 rt2800_config_ps(rt2x00dev, libconf);
1214}
1215EXPORT_SYMBOL_GPL(rt2800_config);
1216
1217/*
1218 * Link tuning
1219 */
1220void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1221{
1222 u32 reg;
1223
1224 /*
1225 * Update FCS error count from register.
1226 */
1227 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1228 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1229}
1230EXPORT_SYMBOL_GPL(rt2800_link_stats);
1231
1232static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1233{
1234 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1235 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1236 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1237 rt2x00_rt(rt2x00dev, RT3090) ||
1238 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1239 return 0x1c + (2 * rt2x00dev->lna_gain);
1240 else
1241 return 0x2e + rt2x00dev->lna_gain;
1242 }
1243
1244 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1245 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1246 else
1247 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1248}
1249
1250static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1251 struct link_qual *qual, u8 vgc_level)
1252{
1253 if (qual->vgc_level != vgc_level) {
1254 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1255 qual->vgc_level = vgc_level;
1256 qual->vgc_level_reg = vgc_level;
1257 }
1258}
1259
1260void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1261{
1262 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1263}
1264EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1265
1266void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1267 const u32 count)
1268{
8d0c9b65 1269 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1270 return;
1271
1272 /*
1273 * When RSSI is better then -80 increase VGC level with 0x10
1274 */
1275 rt2800_set_vgc(rt2x00dev, qual,
1276 rt2800_get_default_vgc(rt2x00dev) +
1277 ((qual->rssi > -80) * 0x10));
1278}
1279EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1280
1281/*
1282 * Initialization functions.
1283 */
1284int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1285{
1286 u32 reg;
d5385bfc 1287 u16 eeprom;
fcf51541 1288 unsigned int i;
e3a896b9 1289 int ret;
fcf51541 1290
a9dce149
GW		 1291 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1292 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1293 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1294 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1295 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1296 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1297 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1298
e3a896b9
GW		 1299 ret = rt2800_drv_init_registers(rt2x00dev);
1300 if (ret)
1301 return ret;
fcf51541
BZ		 1302
1303 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1304 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1305 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1306 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1307 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1308 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1309
1310 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1311 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1312 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1313 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1314 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1315 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1316
1317 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1318 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1319
1320 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1321
1322 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1323 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1324 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1325 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1326 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1327 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1328 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1329 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1330
a9dce149
GW		 1331 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1332
1333 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1334 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1335 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1336 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1337
64522957 1338 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1339 rt2x00_rt(rt2x00dev, RT3090) ||
1340 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1341 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1342 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1343 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1344 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1345 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1346 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1347 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1348 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1349 0x0000002c);
1350 else
1351 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1352 0x0000000f);
1353 } else {
1354 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1355 }
d5385bfc 1356 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1357 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1358
1359 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1360 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1361 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1362 } else {
1363 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1364 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1365 }
c295a81d
HS		 1366 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1367 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1368 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1369 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1370 } else {
1371 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1372 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1373 }
1374
1375 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1376 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1377 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1378 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1379 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1380 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1381 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1382 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1383 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1384 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1385
1386 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1387 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1388 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1389 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1390 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1391
1392 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1393 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1394 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1395 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1396 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1397 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1398 else
1399 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1400 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1401 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1402 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1403
a9dce149
GW		 1404 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1405 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1406 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1407 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1408 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1409 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1410 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1411 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1412 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1413
fcf51541
BZ		 1414 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1415
a9dce149
GW		 1416 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1417 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1418 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1419 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1420 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1421 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1422 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1423 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1424
fcf51541
BZ		 1425 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1426 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1427 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1428 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1429 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1430 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1431 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1432 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1433 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1434
1435 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1436 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1437 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1438 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1439 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1440 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1441 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1442 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1443 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1444 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1445 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1446 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1447
1448 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1449 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1450 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1451 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1452 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1453 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1454 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1455 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1456 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1457 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1458 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1459 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1460
1461 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1462 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1463 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1464 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1465 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1466 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1467 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1468 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1469 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1470 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1471 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1472 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1473
1474 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1475 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1476 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1477 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1478 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1479 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1480 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1481 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1482 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1483 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1484 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1485 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1486 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1487
1488 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1489 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1490 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1491 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1492 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1493 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1494 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1495 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1496 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1497 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1498 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1499 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1500
1501 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1502 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1503 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1504 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1505 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1506 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1507 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1508 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1509 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1510 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1511 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1512 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1513
cea90e55 1514 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1515 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1516
1517 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1520 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1521 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1522 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1526 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1527 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1528 }
1529
1530 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1531 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1532
1533 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1534 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1535 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1536 IEEE80211_MAX_RTS_THRESHOLD);
1537 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1538 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1539
1540 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1541
a21c2ab4
HS		 1542 /*
1543 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1544 * time should be set to 16. However, the original Ralink driver uses
1545 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1546 * connection problems with 11g + CTS protection. Hence, use the same
1547 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1548 */
a9dce149 1549 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1550 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1551 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1552 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1553 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1554 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1555 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1556
fcf51541
BZ		 1557 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1558
1559 /*
1560 * ASIC will keep garbage value after boot, clear encryption keys.
1561 */
1562 for (i = 0; i < 4; i++)
1563 rt2800_register_write(rt2x00dev,
1564 SHARED_KEY_MODE_ENTRY(i), 0);
1565
1566 for (i = 0; i < 256; i++) {
1567 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1568 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1569 wcid, sizeof(wcid));
1570
1571 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1572 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1573 }
1574
1575 /*
1576 * Clear all beacons
fcf51541 1577 */
fdb87251
HS		 1578 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1579 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1580 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1581 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1582 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1583 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1584 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1585 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 1586
cea90e55 1587 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 1588 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1589 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1590 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 1591 }
1592
1593 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1594 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1595 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1596 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1597 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1598 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1599 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1600 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1601 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1602 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1603
1604 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1605 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1606 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1607 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1608 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1609 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1610 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1611 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1612 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1613 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1614
1615 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1616 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1617 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1618 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1619 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1620 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1621 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1622 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1623 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1624 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1625
1626 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1627 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1628 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1629 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1630 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1631 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1632
1633 /*
1634 * We must clear the error counters.
1635 * These registers are cleared on read,
1636 * so we may pass a useless variable to store the value.
1637 */
1638 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1639 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1640 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1641 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1642 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1643 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1644
1645 return 0;
1646}
1647EXPORT_SYMBOL_GPL(rt2800_init_registers);
1648
1649static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1650{
1651 unsigned int i;
1652 u32 reg;
1653
1654 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1655 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1656 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1657 return 0;
1658
1659 udelay(REGISTER_BUSY_DELAY);
1660 }
1661
1662 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1663 return -EACCES;
1664}
1665
1666static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1667{
1668 unsigned int i;
1669 u8 value;
1670
1671 /*
1672 * BBP was enabled after firmware was loaded,
1673 * but we need to reactivate it now.
1674 */
1675 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1676 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1677 msleep(1);
1678
1679 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1680 rt2800_bbp_read(rt2x00dev, 0, &value);
1681 if ((value != 0xff) && (value != 0x00))
1682 return 0;
1683 udelay(REGISTER_BUSY_DELAY);
1684 }
1685
1686 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1687 return -EACCES;
1688}
1689
1690int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1691{
1692 unsigned int i;
1693 u16 eeprom;
1694 u8 reg_id;
1695 u8 value;
1696
1697 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1698 rt2800_wait_bbp_ready(rt2x00dev)))
1699 return -EACCES;
1700
baff8006
HS		 1701 if (rt2800_is_305x_soc(rt2x00dev))
1702 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1703
fcf51541
BZ		 1704 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1705 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1706
1707 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1708 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1709 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1710 } else {
1711 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1712 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1713 }
1714
fcf51541 1715 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1716
d5385bfc 1717 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1718 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1719 rt2x00_rt(rt2x00dev, RT3090) ||
1720 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1721 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1722 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1723 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1724 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1725 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1726 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1727 } else {
1728 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1729 }
1730
fcf51541
BZ		 1731 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1732 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 1733
5ed8f458 1734 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 1735 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1736 else
1737 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1738
fcf51541
BZ		 1739 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1740 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1741 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1742
d5385bfc 1743 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1744 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 1745 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 1746 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1747 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 1748 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1749 else
1750 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1751
baff8006
HS		 1752 if (rt2800_is_305x_soc(rt2x00dev))
1753 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1754 else
1755 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1756 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1757
64522957 1758 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1759 rt2x00_rt(rt2x00dev, RT3090) ||
1760 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 1761 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 1762
d5385bfc
GW		 1763 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1764 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1765 value |= 0x20;
1766 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1767 value &= ~0x02;
fcf51541 1768
d5385bfc 1769 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 1770 }
1771
fcf51541
BZ		 1772
1773 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1774 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1775
1776 if (eeprom != 0xffff && eeprom != 0x0000) {
1777 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1778 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1779 rt2800_bbp_write(rt2x00dev, reg_id, value);
1780 }
1781 }
1782
1783 return 0;
1784}
1785EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1786
1787static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1788 bool bw40, u8 rfcsr24, u8 filter_target)
1789{
1790 unsigned int i;
1791 u8 bbp;
1792 u8 rfcsr;
1793 u8 passband;
1794 u8 stopband;
1795 u8 overtuned = 0;
1796
1797 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1798
1799 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1800 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1801 rt2800_bbp_write(rt2x00dev, 4, bbp);
1802
1803 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1804 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1805 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1806
1807 /*
1808 * Set power & frequency of passband test tone
1809 */
1810 rt2800_bbp_write(rt2x00dev, 24, 0);
1811
1812 for (i = 0; i < 100; i++) {
1813 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1814 msleep(1);
1815
1816 rt2800_bbp_read(rt2x00dev, 55, &passband);
1817 if (passband)
1818 break;
1819 }
1820
1821 /*
1822 * Set power & frequency of stopband test tone
1823 */
1824 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1825
1826 for (i = 0; i < 100; i++) {
1827 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1828 msleep(1);
1829
1830 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1831
1832 if ((passband - stopband) <= filter_target) {
1833 rfcsr24++;
1834 overtuned += ((passband - stopband) == filter_target);
1835 } else
1836 break;
1837
1838 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1839 }
1840
1841 rfcsr24 -= !!overtuned;
1842
1843 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1844 return rfcsr24;
1845}
1846
1847int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1848{
1849 u8 rfcsr;
1850 u8 bbp;
8cdd15e0
GW		 1851 u32 reg;
1852 u16 eeprom;
fcf51541 1853
d5385bfc 1854 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1855 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1856 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 1857 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 1858 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 1859 return 0;
1860
fcf51541
BZ		 1861 /*
1862 * Init RF calibration.
1863 */
1864 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1865 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1866 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1867 msleep(1);
1868 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1869 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1870
d5385bfc 1871 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1872 rt2x00_rt(rt2x00dev, RT3071) ||
1873 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1874 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1875 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1876 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1877 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1878 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1879 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1880 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1881 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1882 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1883 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1884 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1885 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1886 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1887 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1888 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1889 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1890 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1891 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1892 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1893 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1894 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1895 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1896 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1897 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 1898 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 1899 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1900 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1901 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1902 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1903 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1904 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 1905 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 1906 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1907 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 1908 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 1909 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1910 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1911 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1912 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1913 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1914 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1915 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 1916 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 1917 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 1918 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 1919 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1920 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1921 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1922 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1923 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1924 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1925 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 1926 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 1927 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1928 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1929 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1930 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1931 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1932 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1933 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1934 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1935 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1936 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1937 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1938 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1939 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1940 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1941 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1942 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1943 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1944 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1945 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1946 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1947 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1948 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1949 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1950 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1951 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1952 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1953 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1954 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1955 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1956 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 1957 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1958 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1959 return 0;
8cdd15e0
GW		 1960 }
1961
1962 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1963 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1964 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1965 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1966 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 1967 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1968 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 1969 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1970 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1971 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1972
1973 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1974
1975 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1976 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 1977 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1978 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 1979 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1980 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1981 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1982 else
1983 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1984 }
1985 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 1986 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1987 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1988 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1989 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 1990 }
1991
1992 /*
1993 * Set RX Filter calibration for 20MHz and 40MHz
1994 */
8cdd15e0
GW		 1995 if (rt2x00_rt(rt2x00dev, RT3070)) {
1996 rt2x00dev->calibration[0] =
1997 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1998 rt2x00dev->calibration[1] =
1999 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2000 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2001 rt2x00_rt(rt2x00dev, RT3090) ||
2002 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2003 rt2x00dev->calibration[0] =
2004 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2005 rt2x00dev->calibration[1] =
2006 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2007 }
fcf51541
BZ		 2008
2009 /*
2010 * Set back to initial state
2011 */
2012 rt2800_bbp_write(rt2x00dev, 24, 0);
2013
2014 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2015 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2016 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2017
2018 /*
2019 * set BBP back to BW20
2020 */
2021 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2022 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2023 rt2800_bbp_write(rt2x00dev, 4, bbp);
2024
d5385bfc 2025 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2026 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2027 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2028 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2029 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2030
2031 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2032 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2033 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2034
2035 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2036 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2037 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2038 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2039 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2040 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2041 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2042 }
8cdd15e0
GW		 2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2044 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2045 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2046 rt2x00_get_field16(eeprom,
2047 EEPROM_TXMIXER_GAIN_BG_VAL));
2048 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2049
64522957
GW		 2050 if (rt2x00_rt(rt2x00dev, RT3090)) {
2051 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2052
2053 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2054 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2055 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2056 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2057 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2058
2059 rt2800_bbp_write(rt2x00dev, 138, bbp);
2060 }
2061
2062 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2063 rt2x00_rt(rt2x00dev, RT3090) ||
2064 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2065 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2066 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2067 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2068 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2069 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2070 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2071 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2072
2073 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2074 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2075 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2076
2077 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2078 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2079 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2080
2081 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2082 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2083 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2084 }
2085
2086 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2087 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2088 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2089 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2090 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2091 else
2092 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2093 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2094 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2095 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2096 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2097 }
2098
fcf51541
BZ		 2099 return 0;
2100}
2101EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 2102
30e84034
BZ		 2103int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2104{
2105 u32 reg;
2106
2107 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2108
2109 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2110}
2111EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2112
2113static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2114{
2115 u32 reg;
2116
31a4cf1f
GW		 2117 mutex_lock(&rt2x00dev->csr_mutex);
2118
2119 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2120 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2121 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2122 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2123 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2124
2125 /* Wait until the EEPROM has been loaded */
2126 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2127
2128 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2129 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2130 (u32 *)&rt2x00dev->eeprom[i]);
2131 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2132 (u32 *)&rt2x00dev->eeprom[i + 2]);
2133 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2134 (u32 *)&rt2x00dev->eeprom[i + 4]);
2135 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2136 (u32 *)&rt2x00dev->eeprom[i + 6]);
2137
2138 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2139}
2140
2141void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2142{
2143 unsigned int i;
2144
2145 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2146 rt2800_efuse_read(rt2x00dev, i);
2147}
2148EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2149
38bd7b8a
BZ		 2150int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2151{
2152 u16 word;
2153 u8 *mac;
2154 u8 default_lna_gain;
2155
2156 /*
2157 * Start validation of the data that has been read.
2158 */
2159 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2160 if (!is_valid_ether_addr(mac)) {
2161 random_ether_addr(mac);
2162 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2163 }
2164
2165 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2166 if (word == 0xffff) {
2167 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2168 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2169 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2170 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2171 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2172 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2173 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2174 /*
2175 * There is a max of 2 RX streams for RT28x0 series
2176 */
2177 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2178 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2179 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2180 }
2181
2182 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2183 if (word == 0xffff) {
2184 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2185 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2186 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2187 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2188 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2189 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2190 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2191 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2192 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2193 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2194 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2195 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2196 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2197 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2198 }
2199
2200 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2201 if ((word & 0x00ff) == 0x00ff) {
2202 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2203 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2204 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2205 }
2206 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2207 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2208 LED_MODE_TXRX_ACTIVITY);
2209 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2210 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2211 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2212 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2213 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2214 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2215 }
2216
2217 /*
2218 * During the LNA validation we are going to use
2219 * lna0 as correct value. Note that EEPROM_LNA
2220 * is never validated.
2221 */
2222 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2223 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2224
2225 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2226 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2227 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2228 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2229 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2230 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2231
2232 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2233 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2234 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2235 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2236 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2237 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2238 default_lna_gain);
2239 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2240
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2242 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2243 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2244 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2245 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2246 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2247
2248 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2249 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2250 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2251 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2252 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2253 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2254 default_lna_gain);
2255 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2256
2257 return 0;
2258}
2259EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2260
2261int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2262{
2263 u32 reg;
2264 u16 value;
2265 u16 eeprom;
2266
2267 /*
2268 * Read EEPROM word for configuration.
2269 */
2270 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2271
2272 /*
2273 * Identify RF chipset.
2274 */
2275 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2276 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2277
49e721ec
GW		 2278 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2279 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2280
2281 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2282 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2283 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2284 !rt2x00_rt(rt2x00dev, RT3070) &&
2285 !rt2x00_rt(rt2x00dev, RT3071) &&
2286 !rt2x00_rt(rt2x00dev, RT3090) &&
2287 !rt2x00_rt(rt2x00dev, RT3390) &&
2288 !rt2x00_rt(rt2x00dev, RT3572)) {
2289 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2290 return -ENODEV;
f273fe55 2291 }
714fa663 2292
5122d898
GW		 2293 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2294 !rt2x00_rf(rt2x00dev, RF2850) &&
2295 !rt2x00_rf(rt2x00dev, RF2720) &&
2296 !rt2x00_rf(rt2x00dev, RF2750) &&
2297 !rt2x00_rf(rt2x00dev, RF3020) &&
2298 !rt2x00_rf(rt2x00dev, RF2020) &&
2299 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2300 !rt2x00_rf(rt2x00dev, RF3022) &&
2301 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2302 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2303 return -ENODEV;
2304 }
2305
2306 /*
2307 * Identify default antenna configuration.
2308 */
2309 rt2x00dev->default_ant.tx =
2310 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2311 rt2x00dev->default_ant.rx =
2312 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2313
2314 /*
2315 * Read frequency offset and RF programming sequence.
2316 */
2317 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2318 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2319
2320 /*
2321 * Read external LNA informations.
2322 */
2323 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2324
2325 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2326 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2327 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2328 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2329
2330 /*
2331 * Detect if this device has an hardware controlled radio.
2332 */
2333 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2334 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2335
2336 /*
2337 * Store led settings, for correct led behaviour.
2338 */
2339#ifdef CONFIG_RT2X00_LIB_LEDS
2340 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2341 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2342 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2343
2344 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2345#endif /* CONFIG_RT2X00_LIB_LEDS */
2346
2347 return 0;
2348}
2349EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2350
4da2933f 2351/*
55f9321a 2352 * RF value list for rt28xx
4da2933f
BZ		 2353 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2354 */
2355static const struct rf_channel rf_vals[] = {
2356 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2357 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2358 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2359 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2360 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2361 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2362 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2363 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2364 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2365 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2366 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2367 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2368 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2369 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2370
2371 /* 802.11 UNI / HyperLan 2 */
2372 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2373 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2374 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2375 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2376 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2377 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2378 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2379 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2380 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2381 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2382 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2383 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2384
2385 /* 802.11 HyperLan 2 */
2386 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2387 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2388 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2389 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2390 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2391 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2392 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2393 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2394 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2395 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2396 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2397 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2398 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2399 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2400 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2401 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2402
2403 /* 802.11 UNII */
2404 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2405 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2406 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2407 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2408 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2409 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2410 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2411 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2412 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2413 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2414 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2415
2416 /* 802.11 Japan */
2417 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2418 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2419 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2420 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2421 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2422 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2423 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2424};
2425
2426/*
55f9321a
ID		 2427 * RF value list for rt3xxx
2428 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2429 */
55f9321a 2430static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2431 {1, 241, 2, 2 },
2432 {2, 241, 2, 7 },
2433 {3, 242, 2, 2 },
2434 {4, 242, 2, 7 },
2435 {5, 243, 2, 2 },
2436 {6, 243, 2, 7 },
2437 {7, 244, 2, 2 },
2438 {8, 244, 2, 7 },
2439 {9, 245, 2, 2 },
2440 {10, 245, 2, 7 },
2441 {11, 246, 2, 2 },
2442 {12, 246, 2, 7 },
2443 {13, 247, 2, 2 },
2444 {14, 248, 2, 4 },
55f9321a
ID		 2445
2446 /* 802.11 UNI / HyperLan 2 */
2447 {36, 0x56, 0, 4},
2448 {38, 0x56, 0, 6},
2449 {40, 0x56, 0, 8},
2450 {44, 0x57, 0, 0},
2451 {46, 0x57, 0, 2},
2452 {48, 0x57, 0, 4},
2453 {52, 0x57, 0, 8},
2454 {54, 0x57, 0, 10},
2455 {56, 0x58, 0, 0},
2456 {60, 0x58, 0, 4},
2457 {62, 0x58, 0, 6},
2458 {64, 0x58, 0, 8},
2459
2460 /* 802.11 HyperLan 2 */
2461 {100, 0x5b, 0, 8},
2462 {102, 0x5b, 0, 10},
2463 {104, 0x5c, 0, 0},
2464 {108, 0x5c, 0, 4},
2465 {110, 0x5c, 0, 6},
2466 {112, 0x5c, 0, 8},
2467 {116, 0x5d, 0, 0},
2468 {118, 0x5d, 0, 2},
2469 {120, 0x5d, 0, 4},
2470 {124, 0x5d, 0, 8},
2471 {126, 0x5d, 0, 10},
2472 {128, 0x5e, 0, 0},
2473 {132, 0x5e, 0, 4},
2474 {134, 0x5e, 0, 6},
2475 {136, 0x5e, 0, 8},
2476 {140, 0x5f, 0, 0},
2477
2478 /* 802.11 UNII */
2479 {149, 0x5f, 0, 9},
2480 {151, 0x5f, 0, 11},
2481 {153, 0x60, 0, 1},
2482 {157, 0x60, 0, 5},
2483 {159, 0x60, 0, 7},
2484 {161, 0x60, 0, 9},
2485 {165, 0x61, 0, 1},
2486 {167, 0x61, 0, 3},
2487 {169, 0x61, 0, 5},
2488 {171, 0x61, 0, 7},
2489 {173, 0x61, 0, 9},
4da2933f
BZ		 2490};
2491
2492int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2493{
4da2933f
BZ		 2494 struct hw_mode_spec *spec = &rt2x00dev->spec;
2495 struct channel_info *info;
2496 char *tx_power1;
2497 char *tx_power2;
2498 unsigned int i;
2499 u16 eeprom;
2500
93b6bd26
GW		 2501 /*
2502 * Disable powersaving as default on PCI devices.
2503 */
cea90e55 2504 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2505 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2506
4da2933f
BZ		 2507 /*
2508 * Initialize all hw fields.
2509 */
2510 rt2x00dev->hw->flags =
2511 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2512 IEEE80211_HW_SIGNAL_DBM |
2513 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 2514 IEEE80211_HW_PS_NULLFUNC_STACK |
2515 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 2516
4da2933f
BZ		 2517 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2518 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2519 rt2x00_eeprom_addr(rt2x00dev,
2520 EEPROM_MAC_ADDR_0));
2521
3f2bee24
HS		 2522 /*
2523 * As rt2800 has a global fallback table we cannot specify
2524 * more then one tx rate per frame but since the hw will
2525 * try several rates (based on the fallback table) we should
2526 * still initialize max_rates to the maximum number of rates
2527 * we are going to try. Otherwise mac80211 will truncate our
2528 * reported tx rates and the rc algortihm will end up with
2529 * incorrect data.
2530 */
2531 rt2x00dev->hw->max_rates = 7;
2532 rt2x00dev->hw->max_rate_tries = 1;
2533
4da2933f
BZ		 2534 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2535
2536 /*
2537 * Initialize hw_mode information.
2538 */
2539 spec->supported_bands = SUPPORT_BAND_2GHZ;
2540 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2541
5122d898 2542 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 2543 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 2544 spec->num_channels = 14;
2545 spec->channels = rf_vals;
55f9321a
ID		 2546 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2547 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2548 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2549 spec->num_channels = ARRAY_SIZE(rf_vals);
2550 spec->channels = rf_vals;
5122d898
GW		 2551 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2552 rt2x00_rf(rt2x00dev, RF2020) ||
2553 rt2x00_rf(rt2x00dev, RF3021) ||
2554 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 2555 spec->num_channels = 14;
2556 spec->channels = rf_vals_3x;
2557 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2558 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2559 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2560 spec->channels = rf_vals_3x;
4da2933f
BZ		 2561 }
2562
2563 /*
2564 * Initialize HT information.
2565 */
5122d898 2566 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2567 spec->ht.ht_supported = true;
2568 else
2569 spec->ht.ht_supported = false;
2570
4da2933f 2571 spec->ht.cap =
06443e46 2572 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 2573 IEEE80211_HT_CAP_GRN_FLD |
2574 IEEE80211_HT_CAP_SGI_20 |
2575 IEEE80211_HT_CAP_SGI_40 |
9a418af5 2576 IEEE80211_HT_CAP_RX_STBC;
22cabaa6
HS		 2577
2578 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2579 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2580
4da2933f
BZ		 2581 spec->ht.ampdu_factor = 3;
2582 spec->ht.ampdu_density = 4;
2583 spec->ht.mcs.tx_params =
2584 IEEE80211_HT_MCS_TX_DEFINED |
2585 IEEE80211_HT_MCS_TX_RX_DIFF |
2586 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2587 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2588
2589 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2590 case 3:
2591 spec->ht.mcs.rx_mask[2] = 0xff;
2592 case 2:
2593 spec->ht.mcs.rx_mask[1] = 0xff;
2594 case 1:
2595 spec->ht.mcs.rx_mask[0] = 0xff;
2596 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2597 break;
2598 }
2599
2600 /*
2601 * Create channel information array
2602 */
2603 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2604 if (!info)
2605 return -ENOMEM;
2606
2607 spec->channels_info = info;
2608
2609 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2610 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2611
2612 for (i = 0; i < 14; i++) {
2613 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2614 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2615 }
2616
2617 if (spec->num_channels > 14) {
2618 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2619 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2620
2621 for (i = 14; i < spec->num_channels; i++) {
2622 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2623 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2624 }
2625 }
2626
2627 return 0;
2628}
2629EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2630
2ce33995
BZ		 2631/*
2632 * IEEE80211 stack callback functions.
2633 */
2634static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2635 u32 *iv32, u16 *iv16)
2636{
2637 struct rt2x00_dev *rt2x00dev = hw->priv;
2638 struct mac_iveiv_entry iveiv_entry;
2639 u32 offset;
2640
2641 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2642 rt2800_register_multiread(rt2x00dev, offset,
2643 &iveiv_entry, sizeof(iveiv_entry));
2644
855da5e0
JL		 2645 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2646 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2647}
2648
2649static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2650{
2651 struct rt2x00_dev *rt2x00dev = hw->priv;
2652 u32 reg;
2653 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2654
2655 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2656 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2657 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2658
2659 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2660 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2661 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2662
2663 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2664 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2665 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2666
2667 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2668 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2669 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2670
2671 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2672 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2673 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2674
2675 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2676 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2677 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2678
2679 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2680 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2681 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2682
2683 return 0;
2684}
2685
2686static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2687 const struct ieee80211_tx_queue_params *params)
2688{
2689 struct rt2x00_dev *rt2x00dev = hw->priv;
2690 struct data_queue *queue;
2691 struct rt2x00_field32 field;
2692 int retval;
2693 u32 reg;
2694 u32 offset;
2695
2696 /*
2697 * First pass the configuration through rt2x00lib, that will
2698 * update the queue settings and validate the input. After that
2699 * we are free to update the registers based on the value
2700 * in the queue parameter.
2701 */
2702 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2703 if (retval)
2704 return retval;
2705
2706 /*
2707 * We only need to perform additional register initialization
2708 * for WMM queues/
2709 */
2710 if (queue_idx >= 4)
2711 return 0;
2712
2713 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2714
2715 /* Update WMM TXOP register */
2716 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2717 field.bit_offset = (queue_idx & 1) * 16;
2718 field.bit_mask = 0xffff << field.bit_offset;
2719
2720 rt2800_register_read(rt2x00dev, offset, &reg);
2721 rt2x00_set_field32(&reg, field, queue->txop);
2722 rt2800_register_write(rt2x00dev, offset, reg);
2723
2724 /* Update WMM registers */
2725 field.bit_offset = queue_idx * 4;
2726 field.bit_mask = 0xf << field.bit_offset;
2727
2728 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2729 rt2x00_set_field32(&reg, field, queue->aifs);
2730 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2731
2732 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2733 rt2x00_set_field32(&reg, field, queue->cw_min);
2734 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2735
2736 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2737 rt2x00_set_field32(&reg, field, queue->cw_max);
2738 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2739
2740 /* Update EDCA registers */
2741 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2742
2743 rt2800_register_read(rt2x00dev, offset, &reg);
2744 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2745 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2746 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2747 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2748 rt2800_register_write(rt2x00dev, offset, reg);
2749
2750 return 0;
2751}
2752
2753static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2754{
2755 struct rt2x00_dev *rt2x00dev = hw->priv;
2756 u64 tsf;
2757 u32 reg;
2758
2759 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2760 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2761 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2762 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2763
2764 return tsf;
2765}
2766
1df90809
HS		 2767static int rt2800_ampdu_action(struct ieee80211_hw *hw,
2768 struct ieee80211_vif *vif,
2769 enum ieee80211_ampdu_mlme_action action,
2770 struct ieee80211_sta *sta,
2771 u16 tid, u16 *ssn)
2772{
2773 struct rt2x00_dev *rt2x00dev = hw->priv;
2774 int ret = 0;
2775
2776 switch (action) {
2777 case IEEE80211_AMPDU_RX_START:
2778 case IEEE80211_AMPDU_RX_STOP:
2779 /* we don't support RX aggregation yet */
2780 ret = -ENOTSUPP;
2781 break;
2782 case IEEE80211_AMPDU_TX_START:
2783 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2784 break;
2785 case IEEE80211_AMPDU_TX_STOP:
2786 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2787 break;
2788 case IEEE80211_AMPDU_TX_OPERATIONAL:
2789 break;
2790 default:
2791 WARNING(rt2x00dev, "Unknown AMPDU action\n");
2792 }
2793
2794 return ret;
2795}
2796
2ce33995
BZ		 2797const struct ieee80211_ops rt2800_mac80211_ops = {
2798 .tx = rt2x00mac_tx,
2799 .start = rt2x00mac_start,
2800 .stop = rt2x00mac_stop,
2801 .add_interface = rt2x00mac_add_interface,
2802 .remove_interface = rt2x00mac_remove_interface,
2803 .config = rt2x00mac_config,
2804 .configure_filter = rt2x00mac_configure_filter,
2805 .set_tim = rt2x00mac_set_tim,
2806 .set_key = rt2x00mac_set_key,
2807 .get_stats = rt2x00mac_get_stats,
2808 .get_tkip_seq = rt2800_get_tkip_seq,
2809 .set_rts_threshold = rt2800_set_rts_threshold,
2810 .bss_info_changed = rt2x00mac_bss_info_changed,
2811 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2812 .get_tsf = rt2800_get_tsf,
2813 .rfkill_poll = rt2x00mac_rfkill_poll,
1df90809 2814 .ampdu_action = rt2800_ampdu_action,
2ce33995
BZ		 2815};
2816EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
a5ea2f02
ID		 2817
2818MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
2819MODULE_VERSION(DRV_VERSION);
2820MODULE_DESCRIPTION("Ralink RT2800 library");
2821MODULE_LICENSE("GPL");
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